[keystone-rtos/edma3_lld.git] / packages / ti / sdo / edma3 / rm / src / configs / edma3_c6657_cfg.c
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_c6657_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_c6657_cfg.c
index 69490864ed3b661358a12c56c0b1a318d6c12c3b..877c7f3a4ce6d10bbad136e0cde0960d9ec62217 100644 (file)
#include <ti/sdo/edma3/rm/edma3_rm.h>
-#define NUM_EDMA3_INSTANCES 3u
+#define NUM_EDMA3_INSTANCES 1u
/* Driver Object Initialization Configuration */
EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
{
/* EDMA3 INSTANCE# 0 */
/** Total number of DMA Channels supported by the EDMA3 Controller */
- 16u,
- /** Total number of QDMA Channels supported by the EDMA3 Controller */
- 8u,
- /** Total number of TCCs supported by the EDMA3 Controller */
- 16u,
- /** Total number of PaRAM Sets supported by the EDMA3 Controller */
- 128u,
- /** Total number of Event Queues in the EDMA3 Controller */
- 2u,
- /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
- 2u,
- /** Number of Regions on this EDMA3 controller */
- 8u,
-
- /**
- * \brief Channel mapping existence
- * A value of 0 (No channel mapping) implies that there is fixed association
- * for a channel number to a parameter entry number or, in other words,
- * PaRAM entry n corresponds to channel n.
- */
- 1u,
-
- /** Existence of memory protection feature */
- 1u,
-
- /** Global Register Region of CC Registers */
- (void *)0x02700000u,
- /** Transfer Controller (TC) Registers */
- {
- (void *)0x02760000u,
- (void *)0x02768000u,
- (void *)NULL,
- (void *)NULL,
- (void *)NULL,
- (void *)NULL,
- (void *)NULL,
- (void *)NULL
- },
- /** Interrupt no. for Transfer Completion */
- 38u,
- /** Interrupt no. for CC Error */
- 32u,
- /** Interrupt no. for TCs Error */
- {
- 34u,
- 35u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- },
-
- /**
- * \brief EDMA3 TC priority setting
- *
- * User can program the priority of the Event Queues
- * at a system-wide level. This means that the user can set the
- * priority of an IO initiated by either of the TCs (Transfer Controllers)
- * relative to IO initiated by the other bus masters on the
- * device (ARM, DSP, USB, etc)
- */
- {
- 0u,
- 1u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
- },
- /**
- * \brief To Configure the Threshold level of number of events
- * that can be queued up in the Event queues. EDMA3CC error register
- * (CCERR) will indicate whether or not at any instant of time the
- * number of events queued up in any of the event queues exceeds
- * or equals the threshold/watermark value that is set
- * in the queue watermark threshold register (QWMTHRA).
- */
- {
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
- },
-
- /**
- * \brief To Configure the Default Burst Size (DBS) of TCs.
- * An optimally-sized command is defined by the transfer controller
- * default burst size (DBS). Different TCs can have different
- * DBS values. It is defined in Bytes.
- */
- {
- 128u,
- 128u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
- },
-
- /**
- * \brief Mapping from each DMA channel to a Parameter RAM set,
- * if it exists, otherwise of no use.
- */
- {
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- /* DMA channels 16-63 DOES NOT exist */
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
- },
-
- /**
- * \brief Mapping from each DMA channel to a TCC. This specific
- * TCC code will be returned when the transfer is completed
- * on the mapped channel.
- */
- {
- 0u, 1u, 2u, 3u,
- 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u,
- 12u, 13u, 14u, 15u,
- /* DMA channels 16-63 DOES NOT exist */
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
- },
-
- /**
- * \brief Mapping of DMA channels to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- */
- {
- 0x0000FFFFu,
- 0x00000000u
- }
- },
-
- {
- /* EDMA3 INSTANCE# 1 */
- /** Total number of DMA Channels supported by the EDMA3 Controller */
64u,
/** Total number of QDMA Channels supported by the EDMA3 Controller */
8u,
1u,
/** Global Register Region of CC Registers */
- (void *)0x02720000u,
+ (void *)0x02740000u,
/** Transfer Controller (TC) Registers */
{
- (void *)0x02770000u,
- (void *)0x02778000u,
- (void *)0x02780000u,
- (void *)0x02788000u,
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
(void *)NULL,
(void *)NULL,
(void *)NULL,
(void *)NULL
},
/** Interrupt no. for Transfer Completion */
- 8u,
+ 24u,
/** Interrupt no. for CC Error */
- 0u,
+ 16u,
/** Interrupt no. for TCs Error */
{
- 2u,
- 3u,
- 4u,
- 5u,
+ 18u,
+ 19u,
+ 20u,
+ 21u,
0u,
0u,
0u,
* if it exists, otherwise of no use.
*/
{
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
- 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
},
/**
*/
{
0xFFFFFFFFu,
- 0x0000FFFFu
+ 0xFF0000FFu
}
},
+ };
+EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
{
- /* EDMA3 INSTANCE# 2 */
- /** Total number of DMA Channels supported by the EDMA3 Controller */
- 64u,
- /** Total number of QDMA Channels supported by the EDMA3 Controller */
- 8u,
- /** Total number of TCCs supported by the EDMA3 Controller */
- 64u,
- /** Total number of PaRAM Sets supported by the EDMA3 Controller */
- 512u,
- /** Total number of Event Queues in the EDMA3 Controller */
- 4u,
- /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
- 4u,
- /** Number of Regions on this EDMA3 controller */
- 8u,
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
- /**
- * \brief Channel mapping existence
- * A value of 0 (No channel mapping) implies that there is fixed association
- * for a channel number to a parameter entry number or, in other words,
- * PaRAM entry n corresponds to channel n.
- */
- 1u,
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
- /** Existence of memory protection feature */
- 1u,
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Fu},
- /** Global Register Region of CC Registers */
- (void *)0x02740000u,
- /** Transfer Controller (TC) Registers */
- {
- (void *)0x02790000u,
- (void *)0x02798000u,
- (void *)0x027A0000u,
- (void *)0x027A8000u,
- (void *)NULL,
- (void *)NULL,
- (void *)NULL,
- (void *)NULL
- },
- /** Interrupt no. for Transfer Completion */
- 24u,
- /** Interrupt no. for CC Error */
- 16u,
- /** Interrupt no. for TCs Error */
- {
- 18u,
- 19u,
- 20u,
- 21u,
- 0u,
- 0u,
- 0u,
- 0u,
- },
-
- /**
- * \brief EDMA3 TC priority setting
- *
- * User can program the priority of the Event Queues
- * at a system-wide level. This means that the user can set the
- * priority of an IO initiated by either of the TCs (Transfer Controllers)
- * relative to IO initiated by the other bus masters on the
- * device (ARM, DSP, USB, etc)
- */
- {
- 0u,
- 1u,
- 2u,
- 3u,
- 0u,
- 0u,
- 0u,
- 0u
- },
- /**
- * \brief To Configure the Threshold level of number of events
- * that can be queued up in the Event queues. EDMA3CC error register
- * (CCERR) will indicate whether or not at any instant of time the
- * number of events queued up in any of the event queues exceeds
- * or equals the threshold/watermark value that is set
- * in the queue watermark threshold register (QWMTHRA).
- */
- {
- 16u,
- 16u,
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u
- },
-
- /**
- * \brief To Configure the Default Burst Size (DBS) of TCs.
- * An optimally-sized command is defined by the transfer controller
- * default burst size (DBS). Different TCs can have different
- * DBS values. It is defined in Bytes.
- */
- {
- 64u,
- 64u,
- 64u,
- 64u,
- 0u,
- 0u,
- 0u,
- 0u
- },
-
- /**
- * \brief Mapping from each DMA channel to a Parameter RAM set,
- * if it exists, otherwise of no use.
- */
- {
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
- },
-
- /**
- * \brief Mapping from each DMA channel to a TCC. This specific
- * TCC code will be returned when the transfer is completed
- * on the mapped channel.
- */
- {
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
- },
-
- /**
- * \brief Mapping of DMA channels to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- */
- {
- 0xFFFFFFFFu,
- 0xFF0000FFu
- }
- },
- };
-
-EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
- {
- /* EDMA3 INSTANCE# 0 */
- {
- /* Resources owned/reserved by region 0 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32*/
- {0x0000FFFFu, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x000000FFu},
-
- /* resvdTccs */
- /* 31 0 63 32*/
- {0x0000FFFFu, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 1 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32*/
- {0x0000FFFFu, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x000000FFu},
-
- /* resvdTccs */
- /* 31 0 63 32*/
- {0x0000FFFFu, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 2 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32*/
- {0x0000FFFFu, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x000000FFu},
-
- /* resvdTccs */
- /* 31 0 63 32*/
- {0x0000FFFFu, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 3 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32*/
- {0x0000FFFFu, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x000000FFu},
-
- /* resvdTccs */
- /* 31 0 63 32*/
- {0x0000FFFFu, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 4 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 5 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 6 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
- },
-
- /* Resources owned/reserved by region 7 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
- },
- },
-
- /* EDMA3 INSTANCE# 1 */
- {
- /* Resources owned/reserved by region 0 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00FF0000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x0000000Fu},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00FF0000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x0000FFFFu},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x0000FFFFu},
- },
-
- /* Resources owned/reserved by region 1 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0xFF000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x000000F0u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0xFF000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x0000FFFFu},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x0000FFFFu},
- },
-
- /* Resources owned/reserved by region 2 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x0000FFFFu},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x0000FFFFu},
- },
-
- /* Resources owned/reserved by region 3 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x0000FFFFu},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x0000FFFFu},
- },
-
- /* Resources owned/reserved by region 4 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0xFF0000FFu},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1207,10 +272,10 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0xFF0000FFu},
},
- /* Resources owned/reserved by region 5 */
+ /* Resources owned/reserved by region 1 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
@@ -1218,35 +283,35 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x0000FF00u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x000000F0u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x0000FF00u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0xFF0000FFu},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1254,10 +319,10 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0xFF0000FFu},
},
- /* Resources owned/reserved by region 6 */
+ /* Resources owned/reserved by region 2 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
@@ -1304,7 +369,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
{0x00000000u, 0x00000000u},
},
- /* Resources owned/reserved by region 7 */
+ /* Resources owned/reserved by region 3 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
@@ -1350,197 +415,6 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* 31 0 63 32 */
{0x00000000u, 0x00000000u},
},
- },
-
- /* EDMA3 INSTANCE# 2 */
- {
- /* Resources owned/reserved by region 0 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFF0000FFu},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFF0000FFu},
- },
-
- /* Resources owned/reserved by region 1 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFF0000FFu},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFF0000FFu},
- },
-
- /* Resources owned/reserved by region 2 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x0000FF00u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x0000000Fu},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x0000FF00u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFF0000FFu},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFF0000FFu},
- },
-
- /* Resources owned/reserved by region 3 */
- {
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0x00000000u, 0x00FF0000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x000000F0u},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0x00000000u, 0x00FF0000u},
-
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFF0000FFu},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFF0000FFu},
- },
/* Resources owned/reserved by region 4 */
{