diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.c b/packages/ti/sdo/edma3/rm/src/edma3resmgr.c
-/*******************************************************************************\r
-**+--------------------------------------------------------------------------+**\r
-**| **** |**\r
-**| **** |**\r
-**| ******o*** |**\r
-**| ********_///_**** |**\r
-**| ***** /_//_/ **** |**\r
-**| ** ** (__/ **** |**\r
-**| ********* |**\r
-**| **** |**\r
-**| *** |**\r
-**| |**\r
-**| Copyright (c) 1998-2006 Texas Instruments Incorporated |**\r
-**| ALL RIGHTS RESERVED |**\r
-**| |**\r
-**| Permission is hereby granted to licensees of Texas Instruments |**\r
-**| Incorporated (TI) products to use this computer program for the sole |**\r
-**| purpose of implementing a licensee product based on TI products. |**\r
-**| No other rights to reproduce, use, or disseminate this computer |**\r
-**| program, whether in part or in whole, are granted. |**\r
-**| |**\r
-**| TI makes no representation or warranties with respect to the |**\r
-**| performance of this computer program, and specifically disclaims |**\r
-**| any responsibility for any damages, special or consequential, |**\r
-**| connected with the use of this program. |**\r
-**| |**\r
-**+--------------------------------------------------------------------------+**\r
-*******************************************************************************/\r
-\r
-/** \file edma3resmgr.c\r
- \brief EDMA3 Controller Resource Manager Interface Implementation\r
-\r
- This file contains Resource Manager Implementation for the EDMA3 Controller.\r
-\r
- (C) Copyright 2006, Texas Instruments, Inc\r
-\r
- \version 0.0.1 Purushotam Kumar - Created\r
- 0.1.0 Joseph Fernandez - Made generic\r
- - Added documentation\r
- - Moved SoC specific defines\r
- to SoC specific header.\r
- 0.2.0 Anuj Aggarwal - Modified it for EDMA3 package\r
- - Added multiple instances\r
- capability\r
- 0.2.1 Anuj Aggarwal - Modified it for more run time\r
- configuration.\r
- - Made EDMA3 package OS\r
- independent.\r
- 0.2.2 Anuj Aggarwal - Critical section handling code\r
- modification. Uses semaphore and\r
- interrupts disabling mechanism\r
- for resource sharing.\r
- 0.3.0 Anuj Aggarwal - Renamed EDMA3_DVR to EDMA3_DRV\r
- - IPR bit clearing in RM ISR\r
- issue fixed.\r
- - Sample application made generic\r
- 0.3.1 Anuj Aggarwal - Added DMA/QDMA Channel to TCC\r
- mapping, to fix QDMA missed\r
- event issue.\r
- 0.3.2 Anuj Aggarwal - Added support for POLL mode\r
- - Added a new API to modify the\r
- CC Register.\r
- 1.0.0 Anuj Aggarwal - Fixed resource allocation related\r
- bugs.\r
- 1.0.0.1 Anuj Aggarwal - Fixed spurious missed event\r
- generation related bug.\r
- 1.0.0.2 Anuj Aggarwal - Made the EDMA3 package RTSC\r
- compliant.\r
- 1.0.0.3 Anuj Aggarwal - Changed the directory structure\r
- as per RTSC standard.\r
- 1.01.00.01 Anuj Aggarwal - a) Added new APIs to allocate\r
- logical channels\r
- b) Created EDMA3 config files\r
- for different platforms\r
- c) Misc changes\r
- 1.02.00.01 Anuj Aggarwal - a) Added DM6467 support\r
- b) Fixed some MRs\r
- 1.03.00.01 Anuj Aggarwal - a) Added non-RTSC PJT files\r
- b) IOCTL Interface added.\r
- c) Fixed some MRs.\r
- 1.04 Anuj Aggarwal - a) Added new IOCTLs and APIs.\r
- b) Number of maximum Resource\r
- Manager Instances is configurable.\r
- c) Header files modified to have\r
- extern "C" declarations.\r
-\r
- */\r
-\r
-/* Resource Manager Internal Header Files */\r
-#include <ti/sdo/edma3/rm/src/edma3resmgr.h>\r
-\r
-/* Instrumentation Header File */\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
-#include <ti/sdo/edma3/rm/src/edma3_log.h>\r
-#endif\r
-\r
-/* For assert() */\r
-/**\r
- * Define NDEBUG to ignore assert().\r
- * NDEBUG should be defined before including assert.h header file.\r
- */\r
-#include <assert.h>\r
-\r
-\r
-/* Global Defines, need to re-compile if values are changed */\r
-/*---------------------------------------------------------------------------*/\r
-/**\r
- * \brief EDMA3 Resource Manager behaviour of clearing CC ERROR interrupts.\r
- * This macro controls the driver to enable/disable clearing of error\r
- * status of all channels.\r
- *\r
- * On disabling this (with value 0x0), the channels owned by the region\r
- * is cleared and its expected that some other entity is responsible for\r
- * clearing the error status for channels not owned.\r
- *\r
- * Its recomended that this flag is a positive value, to ensure that\r
- * error flags are cleared for all the channels.\r
- */\r
-#define EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS (TRUE)\r
-\r
-/**\r
- * \brief EDMA3 Resource Manager retry count to check the pending interrupts inside ISR.\r
- * This macro controls the driver to check the pending interrupt for\r
- * 'n' number of times.\r
- * Minumum value is 1.\r
- */\r
-#define EDMA3_RM_COMPL_HANDLER_RETRY_COUNT (10u)\r
-\r
-/**\r
- * \brief EDMA3 Resource Manager retry count to check the pending CC Error Interrupt inside ISR\r
- * This macro controls the driver to check the pending CC Error\r
- * interrupt for 'n' number of times.\r
- * Minumum value is 1.\r
- */\r
-#define EDMA3_RM_CCERR_HANDLER_RETRY_COUNT (10u)\r
-\r
-\r
-\r
-/* Externel Variables */\r
-/*---------------------------------------------------------------------------*/\r
-/**\r
- * Maximum Resource Manager Instances supported by the EDMA3 Package.\r
- */\r
-extern const unsigned int EDMA3_MAX_RM_INSTANCES;\r
-\r
-\r
-/**\r
- * \brief Static Configuration structure for EDMA3\r
- * controller, to provide Global SoC specific Information.\r
- *\r
- * This configuration info can also be provided by the user at run-time,\r
- * while calling EDMA3_RM_create (). If not provided at run-time,\r
- * this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",\r
- * for the specified platform.\r
- */\r
-extern EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES];\r
-\r
-/**\r
- * \brief Default Static Region Specific Configuration structure for\r
- * EDMA3 controller, to provide region specific Information.\r
- */\r
-extern EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
-\r
-\r
-/**\r
- * \brief Region Specific Configuration structure for\r
- * EDMA3 controller, to provide region specific Information.\r
- *\r
- * This configuration info can also be provided by the user at run-time,\r
- * while calling EDMA3_RM_open (). If not provided at run-time,\r
- * this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",\r
- * for the specified platform.\r
- */\r
-extern EDMA3_RM_InstanceInitConfig *userInitConfig;\r
-extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;\r
-\r
-\r
-/**\r
- * Handles of EDMA3 Resource Manager Instances.\r
- *\r
- * Used to maintain information of the EDMA3 RM Instances\r
- * for each HW controller.\r
- * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per\r
- * EDMA3 HW.\r
- */\r
-extern EDMA3_RM_Instance *resMgrInstance;\r
-extern EDMA3_RM_Instance *ptrRMIArray;\r
-\r
-\r
-\r
-/* Globals */\r
-/*---------------------------------------------------------------------------*/\r
-/**\r
- * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.\r
- *\r
- * Typically one RM object will cater to one EDMA3 HW controller\r
- * and will have all the global config information.\r
- */\r
-EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];\r
-\r
-\r
-/**\r
- * Global Array to store the mapping between DMA channels and Interrupt\r
- * channels i.e. TCCs.\r
- * DMA channel X can use any TCC Y. Transfer completion\r
- * interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error\r
- * interrupt will occur on DMA channel X (EMR/EMRH register, bit X). In that\r
- * scenario, this DMA channel <-> TCC mapping will be used to point to\r
- * the correct callback function.\r
- */\r
-static unsigned int edma3DmaChTccMapping [EDMA3_MAX_DMA_CH];\r
-\r
-\r
-/**\r
- * Global Array to store the mapping between QDMA channels and Interrupt\r
- * channels i.e. TCCs.\r
- * QDMA channel X can use any TCC Y. Transfer completion\r
- * interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error\r
- * interrupt will occur on QDMA channel X (QEMR register, bit X). In that\r
- * scenario, this QDMA channel <-> TCC mapping will be used to point to\r
- * the correct callback function.\r
- */\r
-static unsigned int edma3QdmaChTccMapping [EDMA3_MAX_QDMA_CH];\r
-\r
-\r
-/**\r
- * Global Array to maintain the Callback details registered\r
- * against a particular TCC. Used to call the callback\r
- * functions linked to the particular channel.\r
- */\r
-static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_TCC];\r
-\r
-\r
-/** edma3RegionId will be updated ONCE using the parameter regionId passed to\r
- * the EDMA3_RM_open() function, for the Master RM instance (one who\r
- * configures the Global Registers).\r
- * This global variable will be used within the Interrupt handlers to know\r
- * which shadow region registers to access. All other interrupts coming\r
- * from other shadow regions will not be handled.\r
- */\r
-static EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS;\r
-\r
-/** masterExists will be updated when the Master RM Instance modifies the\r
- * Global EDMA3 configuration registers. It is used to prevent any other\r
- * Master RM Instance creation.\r
- */\r
-static unsigned short masterExists = FALSE;\r
-\r
-/**\r
- * Number of PaRAM Sets actually present on the SoC. This will be updated\r
- * while creating the Resource Manager Object.\r
- */\r
-unsigned int edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS;\r
-\r
-\r
-/**\r
- * The list of Interrupt Channels which get allocated while requesting the\r
- * TCC. It will be used while checking the IPR/IPRH bits in the RM ISR.\r
- */\r
-static unsigned int allocatedTCCs[2u] = {0x0u, 0x0u};\r
-\r
-\r
-/**\r
- * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed\r
- * and stored in this array. It will be referenced in\r
- * EDMA3_RM_allocContiguousResource () to look for contiguous resources.\r
- */\r
-static unsigned int contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u};\r
-\r
-/**\r
- * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed\r
- * and stored in this array. It will be referenced in\r
- * EDMA3_RM_allocContiguousResource () to look for contiguous resources.\r
- */\r
-static unsigned int contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u};\r
-\r
-/**\r
- * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed\r
- * and stored in this array. It will be referenced in\r
- * EDMA3_RM_allocContiguousResource () to look for contiguous resources.\r
- */\r
-static unsigned int contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u};\r
-\r
-/**\r
- * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed\r
- * and stored in this array. It will be referenced in\r
- * EDMA3_RM_allocContiguousResource () to look for contiguous resources.\r
- */\r
-static unsigned int contiguousParamRes[EDMA3_MAX_PARAM_DWRDS];\r
-\r
-\r
-/**\r
- * \brief Resources bound to a Channel\r
- *\r
- * When a request for a channel is made, the resources PaRAM Set and TCC\r
- * get bound to that channel. This information is needed internally by the\r
- * resource manager, when a request is made to free the channel,\r
- * to free up the channel-associated resources.\r
- */\r
-static EDMA3_RM_ChBoundResources edma3RmChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];\r
-\r
-\r
-\r
-/*---------------------------------------------------------------------------*/\r
-\r
-/* Local functions prototypes */\r
-/*---------------------------------------------------------------------------*/\r
-/** EDMA3 Instance 0 Completion Handler Interrupt Service Routine */\r
-void lisrEdma3ComplHandler0(unsigned int arg);\r
-/** EDMA3 Instance 0 CC Error Interrupt Service Routine */\r
-void lisrEdma3CCErrHandler0(unsigned int arg);\r
-/**\r
- * EDMA3 Instance 0 TC[0-7] Error Interrupt Service Routines\r
- * for a maximum of 8 TCs (Transfer Controllers).\r
- */\r
-void lisrEdma3TC0ErrHandler0(unsigned int arg);\r
-void lisrEdma3TC1ErrHandler0(unsigned int arg);\r
-void lisrEdma3TC2ErrHandler0(unsigned int arg);\r
-void lisrEdma3TC3ErrHandler0(unsigned int arg);\r
-void lisrEdma3TC4ErrHandler0(unsigned int arg);\r
-void lisrEdma3TC5ErrHandler0(unsigned int arg);\r
-void lisrEdma3TC6ErrHandler0(unsigned int arg);\r
-void lisrEdma3TC7ErrHandler0(unsigned int arg);\r
-\r
-\r
-/** Interrupt Handler for the Transfer Completion interrupt */\r
-static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj);\r
-/** Interrupt Handler for the Channel Controller Error interrupt */\r
-static void edma3CCErrHandler (const EDMA3_RM_Obj *rmObj);\r
-/** Interrupt Handler for the Transfer Controller Error interrupt */\r
-static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum);\r
-\r
-\r
-/** Local MemSet function */\r
-void edma3MemSet(void *dst, unsigned char data, unsigned int len);\r
-/** Local MemCpy function */\r
-void edma3MemCpy(void *dst, const void *src, unsigned int len);\r
-\r
-/** Initialization of the Global region registers of the EDMA3 Controller */\r
-static void edma3GlobalRegionInit (unsigned int phyCtrllerInstId);\r
-/** Initialization of the Shadow region registers of the EDMA3 Controller */\r
-static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance);\r
-\r
-\r
-\r
-/* Internal functions for contiguous resource allocation */\r
-/**\r
- * Finds a particular bit ('0' or '1') in the particular word from 'start'.\r
- * If found, returns the position, else return -1.\r
- */\r
-static int findBitInWord (int source, unsigned int start, unsigned short bit);\r
-\r
-/**\r
- * Finds a particular bit ('0' or '1') in the specified resources' array\r
- * from 'start' to 'end'. If found, returns the position, else return -1.\r
- */\r
-static int findBit (EDMA3_RM_ResType resType,\r
- unsigned int start,\r
- unsigned int end,\r
- unsigned short bit);\r
-\r
-/**\r
- * If successful, this function returns EDMA3_RM_SOK and the position\r
- * of first available resource in 'positionRes'. Else returns error.\r
- */\r
-static EDMA3_RM_Result allocAnyContigRes(EDMA3_RM_ResType resType,\r
- unsigned int numResources,\r
- unsigned int *positionRes);\r
-\r
-/**\r
- * Starting from 'firstResIdObj', this function makes the next 'numResources'\r
- * Resources non-available for future. Also, it does some global resisters'\r
- * setting also.\r
- */\r
-static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,\r
- const EDMA3_RM_ResDesc *firstResIdObj,\r
- unsigned int numResources);\r
-\r
-/*---------------------------------------------------------------------------*/\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,\r
- * const EDMA3_RM_GblConfigParams *gblCfgParams,\r
- * const void *miscParam)\r
- * \brief Create EDMA3 Resource Manager Object\r
- *\r
- * This API is used to create the EDMA3 Resource Manager Object. It should be\r
- * called only ONCE for each EDMA3 hardware instance.\r
- *\r
- * Init-time Configuration structure for EDMA3 hardware is provided to pass the\r
- * SoC specific information. This configuration information could be provided\r
- * by the user at init-time. In case user doesn't provide it, this information\r
- * could be taken from the SoC specific configuration file\r
- * edma3_<SOC_NAME>_cfg.c, in case it is available.\r
- *\r
- * This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR)\r
- * and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam'\r
- * argument is NULL. User can avoid these registers' programming (in some specific\r
- * use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration\r
- * structure and passing this structure as the third argument (miscParam).\r
- *\r
- * After successful completion of this API, Resource Manager Object's state\r
- * changes to EDMA3_RM_CREATED from EDMA3_RM_DELETED.\r
- *\r
- * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id\r
- * (Hardware instance id, starting from 0).\r
- * \param gblCfgParams [IN] SoC specific configuration structure for the\r
- * EDMA3 Hardware.\r
- * \param miscParam [IN] Misc configuration options provided in the\r
- * structure 'EDMA3_RM_MiscParam'.\r
- * For default options, user can pass NULL\r
- * in this argument.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- */\r
-EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,\r
- const EDMA3_RM_GblConfigParams *gblCfgParams,\r
- const void *miscParam)\r
- {\r
- unsigned int count = 0u;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- /**\r
- * Used to reset the Internal EDMA3 Resource Manager Data Structures for the first time.\r
- */\r
- static unsigned short rmInitDone = FALSE;\r
- const EDMA3_RM_MiscParam *miscOpt = (const EDMA3_RM_MiscParam *)miscParam;\r
-\r
- /**\r
- * We are NOT checking 'gblCfgParams' for NULL.\r
- * If user has passed NULL, default config info will be\r
- * taken from config file.\r
- * 'param' is also not being checked because it could be\r
- * NULL also.\r
- */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /* Initialize the global variables for the first time */\r
- if (FALSE == rmInitDone)\r
- {\r
- edma3MemSet((void *)&(resMgrObj[count]) , 0x00u,\r
- sizeof(resMgrObj));\r
- rmInitDone = TRUE;\r
- }\r
-\r
- /* Initialization has been done */\r
- if (resMgrObj[phyCtrllerInstId].state != EDMA3_RM_DELETED)\r
- {\r
- result = EDMA3_RM_E_OBJ_NOT_DELETED;\r
- }\r
- else\r
- {\r
- /**\r
- * Check whether user has passed the Global Config Info.\r
- * If yes, copy it to the driver data structures. Else, use the\r
- * info from the config file edma3Cfg.c\r
- */\r
- if (NULL == gblCfgParams)\r
- {\r
- /* Take info from the specific config file */\r
- edma3MemCpy((void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams),\r
- (const void *)(&edma3GblCfgParams[phyCtrllerInstId]),\r
- sizeof (EDMA3_RM_GblConfigParams));\r
- }\r
- else\r
- {\r
- /* User passed the info, save it in the RM object first */\r
- edma3MemCpy((void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams),\r
- (const void *)(gblCfgParams),\r
- sizeof (EDMA3_RM_GblConfigParams));\r
- }\r
-\r
-\r
- /**\r
- * Check whether DMA channel to PaRAM Set mapping exists or not.\r
- * If it does not exist, set the mapping array as 1-to-1 mapped.\r
- */\r
- if (FALSE == resMgrObj[phyCtrllerInstId].gblCfgParams.dmaChPaRAMMapExists)\r
- {\r
- for (count = 0u; count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels; count++)\r
- {\r
- resMgrObj[phyCtrllerInstId].gblCfgParams.dmaChannelPaRAMMap[count] = count;\r
- }\r
- }\r
-\r
-\r
- /**\r
- * Update the actual number of PaRAM sets.\r
- */\r
- edma3NumPaRAMSets = resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets;\r
-\r
- resMgrObj[phyCtrllerInstId].phyCtrllerInstId = phyCtrllerInstId;\r
- resMgrObj[phyCtrllerInstId].state = EDMA3_RM_CREATED;\r
- resMgrObj[phyCtrllerInstId].numOpens = 0u;\r
-\r
- /* Make all the RM instances for this EDMA3 HW NULL */\r
- for (count = 0u; count < EDMA3_MAX_RM_INSTANCES; count++)\r
- {\r
- edma3MemSet((void *)((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count),\r
- 0x00u,\r
- sizeof(EDMA3_RM_Instance));\r
-\r
- /* Also make this data structure NULL */\r
- edma3MemSet((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count),\r
- 0x00u,\r
- sizeof(EDMA3_RM_InstanceInitConfig));\r
- }\r
-\r
- /* Initialize the global edma3DmaChTccMapping array with EDMA3_MAX_TCC */\r
- for ( count = 0u;\r
- count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels;\r
- count++\r
- )\r
- {\r
- edma3DmaChTccMapping[count] = EDMA3_MAX_TCC;\r
- }\r
-\r
- /* Initialize the global edma3QdmaChTccMapping array with EDMA3_MAX_TCC */\r
- for ( count = 0u;\r
- count < resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels;\r
- count++\r
- )\r
- {\r
- edma3QdmaChTccMapping[count] = EDMA3_MAX_TCC;\r
- }\r
-\r
- /* Make the global edma3IntrParams array for interrupts NULL */\r
- edma3MemSet((void *)(&(edma3IntrParams[0u])), 0x00u,\r
- sizeof(edma3IntrParams));\r
-\r
-\r
- /* Reset edma3RmChBoundRes Array*/\r
- for (count = 0u; count < EDMA3_MAX_LOGICAL_CH; count++)\r
- {\r
- edma3RmChBoundRes[phyCtrllerInstId][count].paRAMId = -1;\r
- edma3RmChBoundRes[phyCtrllerInstId][count].tcc = EDMA3_MAX_TCC;\r
- }\r
-\r
- /* Make the contiguousParamRes array NULL */\r
- edma3MemSet((void *)(&(contiguousParamRes[0u])), 0x00u,\r
- sizeof(contiguousParamRes));\r
-\r
-\r
- /**\r
- * Check the misc configuration options structure.\r
- * Check whether the global registers' initialization\r
- * is required or not.\r
- * It is required ONLY if RM is running on the Master Processor.\r
- */\r
- if (NULL != miscOpt)\r
- {\r
- if (miscOpt->isSlave == FALSE)\r
- {\r
- /* It is a master. */\r
- edma3GlobalRegionInit(phyCtrllerInstId);\r
- }\r
- }\r
- else\r
- {\r
- /* By default, global registers will be initialized. */\r
- edma3GlobalRegionInit(phyCtrllerInstId);\r
- }\r
- }\r
- }\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId,\r
- * const void *param)\r
- * \brief Delete EDMA3 Resource Manager Object\r
- *\r
- * This API is used to delete the EDMA3 RM Object. It should be called\r
- * once for each EDMA3 hardware instance, ONLY after closing all the\r
- * previously opened EDMA3 RM Instances.\r
- *\r
- * After successful completion of this API, Resource Manager Object's state\r
- * changes to EDMA3_RM_DELETED.\r
- *\r
- * \param phyCtrllerInstId [IN] EDMA3 Phy Controller Instance Id (Hardware\r
- * instance id, starting from 0).\r
- * \param param [IN] For possible future use.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- */\r
-EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId,\r
- const void *param)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /*to remove CCS remark: parameter "param" was never referenced */\r
- (void)param;\r
-\r
- /**\r
- * If number of RM Instances is 0, then state should be\r
- * EDMA3_RM_CLOSED OR EDMA3_RM_CREATED.\r
- */\r
- if ((NULL == resMgrObj[phyCtrllerInstId].numOpens)\r
- && ((resMgrObj[phyCtrllerInstId].state != EDMA3_RM_CLOSED)\r
- && (resMgrObj[phyCtrllerInstId].state != EDMA3_RM_CREATED)))\r
- {\r
- result = EDMA3_RM_E_OBJ_NOT_CLOSED;\r
- }\r
- else\r
- {\r
- /**\r
- * If number of RM Instances is NOT 0, then this function\r
- * SHOULD NOT be called by anybody.\r
- */\r
- if (NULL != resMgrObj[phyCtrllerInstId].numOpens)\r
- {\r
- result = EDMA3_RM_E_INVALID_STATE;\r
- }\r
- else\r
- {\r
- /** Change state to EDMA3_RM_DELETED */\r
- resMgrObj[phyCtrllerInstId].state = EDMA3_RM_DELETED;\r
-\r
- /* Reset the Allocated TCCs Array also. */\r
- allocatedTCCs[0u] = 0x0u;\r
- allocatedTCCs[1u] = 0x0u;\r
-\r
- /* Also, reset the RM Object Global Config Info */\r
- edma3MemSet((void *)&(resMgrObj[phyCtrllerInstId].gblCfgParams),\r
- 0x00u,\r
- sizeof(EDMA3_RM_GblConfigParams));\r
- }\r
- }\r
- }\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\fn EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,\r
- * const EDMA3_RM_Param *initParam,\r
- * EDMA3_RM_Result *errorCode)\r
- * \brief Open EDMA3 Resource Manager Instance\r
- *\r
- * This API is used to open an EDMA3 Resource Manager Instance. It could be\r
- * called multiple times, for each possible EDMA3 shadow region. Maximum\r
- * EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware\r
- * instance.\r
- *\r
- * Also, only ONE Master Resource Manager Instance is permitted. This master\r
- * instance (and hence the region to which it belongs) will only receive the\r
- * EDMA3 interrupts, if enabled.\r
- *\r
- * User could pass the instance specific configuration structure\r
- * (initParam->rmInstInitConfig) as a part of the 'initParam' structure,\r
- * during init-time. In case user doesn't provide it, this information could\r
- * be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c,\r
- * in case it is available.\r
- *\r
- * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware\r
- * instance id, starting from 0).\r
- * \param initParam [IN] Used to Initialize the Resource Manager\r
- * Instance (Master or Slave).\r
- * \param errorCode [OUT] Error code while opening RM instance.\r
- *\r
- * \return Handle to the opened Resource Manager instance Or NULL in case of\r
- * error.\r
- *\r
- * \note This function disables the global interrupts (by calling API\r
- * edma3OsProtectEntry with protection level\r
- * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data\r
- * structures, to make it re-entrant.\r
- */\r
-EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,\r
- const EDMA3_RM_Param *initParam,\r
- EDMA3_RM_Result *errorCode)\r
- {\r
- unsigned int intState = 0u;\r
- unsigned int resMgrIdx = 0u;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Instance *temp_ptr_rm_inst = NULL;\r
- EDMA3_RM_Handle retVal = NULL;\r
- unsigned int dmaChDwrds = 0u;\r
- unsigned int paramSetDwrds = 0u;\r
- unsigned int tccDwrds = 0u;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
- unsigned int mappedPaRAMId;\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (((initParam == NULL)\r
- || (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES))\r
- || (errorCode == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /* Check whether the semaphore handle is null or not */\r
- if (NULL == initParam->rmSemHandle)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- rmObj = &resMgrObj[phyCtrllerInstId];\r
- if (\r
- (NULL == rmObj)\r
- || (initParam->regionId >=\r
- resMgrObj[phyCtrllerInstId].gblCfgParams.numRegions)\r
- )\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);\r
-\r
- /** Check state of RM Object.\r
- * If no RM instance is opened and this is the first one,\r
- * then state should be created/closed.\r
- */\r
- if ((rmObj->numOpens == NULL) &&\r
- ((rmObj->state != EDMA3_RM_CREATED) &&\r
- (rmObj->state != EDMA3_RM_CLOSED)))\r
- {\r
- result = EDMA3_RM_E_INVALID_STATE;\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);\r
- }\r
- else\r
- {\r
- /**\r
- * If num of instances opened is more than 0 and less than\r
- * max allowed, then state should be opened.\r
- */\r
- if (((rmObj->numOpens > 0) &&\r
- (rmObj->numOpens < EDMA3_MAX_RM_INSTANCES))\r
- && (rmObj->state != EDMA3_RM_OPENED))\r
- {\r
- result = EDMA3_RM_E_INVALID_STATE;\r
- edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState);\r
- }\r
- else\r
- {\r
- /* Check if max opens have passed */\r
- if (rmObj->numOpens >= EDMA3_MAX_RM_INSTANCES)\r
- {\r
- result = EDMA3_RM_E_MAX_RM_INST_OPENED;\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT,\r
- intState);\r
- }\r
- }\r
- }\r
- }\r
- }\r
- }\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /*\r
- * Check whether the RM instance is Master or not.\r
- * If it is master, check whether a master already exists\r
- * or not. There should NOT be more than 1 master.\r
- * Return error code if master already exists\r
- */\r
- if ((TRUE == masterExists) && (TRUE == initParam->isMaster))\r
- {\r
- /* No two masters should exist, return error */\r
- result = EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS;\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);\r
- }\r
- else\r
- {\r
- /* Create Res Mgr Instance */\r
- for (resMgrIdx = 0u; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)\r
- {\r
- temp_ptr_rm_inst = ((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);\r
-\r
- if (NULL != temp_ptr_rm_inst)\r
- {\r
- if (NULL == temp_ptr_rm_inst->pResMgrObjHandle)\r
- {\r
- /* Handle to the EDMA3 HW Object */\r
- temp_ptr_rm_inst->pResMgrObjHandle = rmObj;\r
- /* Handle of the Res Mgr Instance */\r
- rmInstance = temp_ptr_rm_inst;\r
-\r
- /* Also make this data structure NULL, just for safety. */\r
- edma3MemSet((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx),\r
- 0x00u,\r
- sizeof(EDMA3_RM_InstanceInitConfig));\r
-\r
- break;\r
- }\r
- }\r
- }\r
-\r
- /* Check whether a RM instance has been created or not */\r
- if (NULL == rmInstance)\r
- {\r
- result = EDMA3_RM_E_MAX_RM_INST_OPENED;\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);\r
- }\r
- else\r
- {\r
- /* Copy the InitPaRAM first */\r
- edma3MemCpy((void *)(&rmInstance->initParam),\r
- (const void *)(initParam),\r
- sizeof (EDMA3_RM_Param));\r
-\r
- if (rmObj->gblCfgParams.globalRegs != NULL)\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)\r
- (rmObj->gblCfgParams.globalRegs);\r
- rmInstance->shadowRegs = (EDMA3_CCRL_ShadowRegs *)\r
- &(globalRegs->SHADOW[rmInstance->initParam.regionId]);\r
-\r
- /* copy the instance specific semaphore handle */\r
- rmInstance->initParam.rmSemHandle = initParam->rmSemHandle;\r
-\r
- /**\r
- * Check whether user has passed information about resources\r
- * owned and reserved by this instance. This is region specific\r
- * information. If he has not passed, dafault static config info will be taken\r
- * from the config file edma3Cfg.c, according to the regionId specified.\r
- *\r
- * resMgrIdx specifies the RM instance number created just now.\r
- * Use it to populate the userInitConfig [].\r
- */\r
- if (NULL == initParam->rmInstInitConfig)\r
- {\r
- /* Take the info from the specific config file */\r
- edma3MemCpy((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx),\r
- (const void *)(&defInstInitConfig[phyCtrllerInstId][initParam->regionId]),\r
- sizeof (EDMA3_RM_InstanceInitConfig));\r
- }\r
- else\r
- {\r
- /* User has passed the region specific info. */\r
- edma3MemCpy((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx),\r
- (const void *)(initParam->rmInstInitConfig),\r
- sizeof (EDMA3_RM_InstanceInitConfig));\r
- }\r
-\r
- rmInstance->initParam.rmInstInitConfig =\r
- ((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);\r
-\r
- dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32u;\r
- paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32u;\r
- tccDwrds = rmObj->gblCfgParams.numTccs / 32u;\r
-\r
- for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx)\r
- {\r
- rmInstance->avlblDmaChannels[resMgrIdx]\r
- = rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resMgrIdx];\r
- }\r
-\r
- rmInstance->avlblQdmaChannels[0u]\r
- = rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u];\r
-\r
- for (resMgrIdx = 0u; resMgrIdx < paramSetDwrds; ++resMgrIdx)\r
- {\r
- rmInstance->avlblPaRAMSets[resMgrIdx]\r
- = rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resMgrIdx];\r
- }\r
-\r
- for (resMgrIdx = 0u; resMgrIdx < tccDwrds; ++resMgrIdx)\r
- {\r
- rmInstance->avlblTccs [resMgrIdx]\r
- = rmInstance->initParam.rmInstInitConfig->ownTccs[resMgrIdx];\r
- }\r
-\r
- /*\r
- * If mapping exists b/w DMA channel and PaRAM set (i.e. programmable),\r
- * then mark those PaRAM sets which are mapped to some specific\r
- * DMA channels as RESERVED. If NO mapping (ie ch 0 is tied to PaRAM 0,\r
- * ch 1 is tied to PaRAM 1), mark all as RESERVED.\r
- */\r
- if (rmObj->gblCfgParams.dmaChPaRAMMapExists == TRUE)\r
- {\r
- /* Mapping Exists */\r
- for (resMgrIdx = 0u; resMgrIdx < rmObj->gblCfgParams.numDmaChannels; ++resMgrIdx)\r
- {\r
- mappedPaRAMId = rmObj->gblCfgParams.dmaChannelPaRAMMap[resMgrIdx];\r
- if (mappedPaRAMId != EDMA3_RM_CH_NO_PARAM_MAP)\r
- {\r
- /* Channel is mapped to a particular PaRAM Set, mark it as Reserved. */\r
- rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[mappedPaRAMId/32u] |= (1u<<(mappedPaRAMId%32u));\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Mapping Doesnot Exist, PaRAM Sets are 1-to-1 mapped, mark all as Reserved */\r
- for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx)\r
- {\r
- rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[resMgrIdx] = 0xFFFFFFFFu;\r
- }\r
- }\r
-\r
- /*\r
- * If the EDMA RM instance is MASTER (ie. initParam->isMaster\r
- * is TRUE), save the region ID.\r
- * Only this shadow region will receive the\r
- * EDMA3 interrupts, if enabled.\r
- */\r
- if (TRUE == initParam->isMaster)\r
- {\r
- /* Store the region id to use it in the ISRs */\r
- edma3RegionId = rmInstance->initParam.regionId;\r
- masterExists = TRUE;\r
- }\r
-\r
- if (TRUE == initParam->regionInitEnable)\r
- {\r
- edma3ShadowRegionInit (rmInstance);\r
- }\r
-\r
- /**\r
- * By default, PaRAM Sets allocated using this RM Instance\r
- * will get cleared during their allocation.\r
- * User can stop their clearing by calling specific IOCTL\r
- * command.\r
- */\r
- rmInstance->paramInitRequired = TRUE;\r
-\r
-\r
- /**\r
- * By default, during the EDMA3_RM_allocLogicalChannel (),\r
- * global EDMA3 registers (DCHMAP/QCHMAP) and the allocated\r
- * PaRAM Set will be programmed accordingly, for users using this\r
- * RM Instance.\r
- * User can stop their pre-programming by calling\r
- * EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION\r
- * IOCTL command.\r
- */\r
- rmInstance->regModificationRequired = TRUE;\r
-\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmObj->state = EDMA3_RM_OPENED;\r
- /* Increase the Instance count */\r
- resMgrObj[phyCtrllerInstId].numOpens++;\r
- retVal = rmInstance;\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);\r
- }\r
- }\r
- }\r
-\r
- *errorCode = result;\r
- return (EDMA3_RM_Handle)retVal;\r
- }\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr,\r
- * const void *param)\r
- * \brief Close EDMA3 Resource Manager Instance\r
- *\r
- * This API is used to close a previously opened EDMA3 RM Instance.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param param [IN] For possible future use.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function disables the global interrupts (by calling API\r
- * edma3OsProtectEntry with protection level\r
- * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data\r
- * structures, to make it re-entrant.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr,\r
- const void *param)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- unsigned int intState = 0u;\r
- unsigned int resMgrIdx = 0u;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- unsigned int dmaChDwrds;\r
- unsigned int paramSetDwrds;\r
- unsigned int tccDwrds;\r
-\r
- /*to remove CCS remark: parameter "param" was never referenced */\r
- (void)param;\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (NULL == hEdmaResMgr)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
- else\r
- {\r
- /* Check state of driver, state should be opened */\r
- if (rmObj->state != EDMA3_RM_OPENED)\r
- {\r
- result = (EDMA3_RM_E_OBJ_NOT_OPENED);\r
- }\r
- else\r
- {\r
- dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32u;\r
- paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32u;\r
- tccDwrds = rmObj->gblCfgParams.numTccs / 32u;\r
-\r
- /* Set the instance config as NULL*/\r
- for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx)\r
- {\r
- rmInstance->avlblDmaChannels[resMgrIdx] = 0x0u;\r
- }\r
- for (resMgrIdx = 0u; resMgrIdx < paramSetDwrds; ++resMgrIdx)\r
- {\r
- rmInstance->avlblPaRAMSets[resMgrIdx] = 0x0u;\r
- }\r
- rmInstance->avlblQdmaChannels[0u] = 0x0u;\r
- for (resMgrIdx = 0u; resMgrIdx < tccDwrds; ++resMgrIdx)\r
- {\r
- rmInstance->avlblTccs[resMgrIdx] = 0x0u;\r
- }\r
-\r
- /**\r
- * If this is the Master Instance, reset the static variable\r
- * 'masterExists'.\r
- */\r
- if (TRUE == rmInstance->initParam.isMaster)\r
- {\r
- masterExists = FALSE;\r
- edma3RegionId = EDMA3_MAX_REGIONS;\r
- }\r
-\r
- /* Reset the Initparam for this RM Instance */\r
- edma3MemSet((void *)&(rmInstance->initParam) , 0x00u,\r
- sizeof(EDMA3_RM_Param));\r
-\r
- /* Critical section starts */\r
- edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);\r
-\r
- /* Decrease the Number of Opens */\r
- --rmObj->numOpens;\r
- if (NULL == rmObj->numOpens)\r
- {\r
- edma3MemSet((void *)&(edma3RmChBoundRes[rmObj->phyCtrllerInstId]), 0x00u,\r
- sizeof(edma3RmChBoundRes));\r
-\r
- rmObj->state = EDMA3_RM_CLOSED;\r
- }\r
-\r
- /* Critical section ends */\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);\r
-\r
- rmInstance->pResMgrObjHandle = NULL;\r
- rmInstance->shadowRegs = NULL;\r
- rmInstance = NULL;\r
- }\r
- }\r
- }\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr,\r
- * EDMA3_RM_ResDesc *resObj)\r
- * \brief This API is used to allocate specified EDMA3 Resources like\r
- * DMA/QDMA channel, PaRAM Set or TCC.\r
- *\r
- * Note: To free the resources allocated by this API, user should call\r
- * EDMA3_RM_freeResource () ONLY to de-allocate all the allocated resources.\r
- *\r
- * User can either request a specific resource by passing the resource id\r
- * in 'resObj->resId' OR request ANY available resource of the type\r
- * 'resObj->type'.\r
- *\r
- * ANY types of resources are those resources when user doesn't care about the\r
- * actual resource allocated; user just wants a resource of the type specified.\r
- * One use-case is to perform memory-to-memory data transfer operation. This\r
- * operation can be performed using any available DMA or QDMA channel.\r
- * User doesn't need any specific channel for the same.\r
- *\r
- * To allocate a specific resource, first this API checks whether that resource\r
- * is OWNED by the Resource Manager instance. Then it checks the current\r
- * availability of that resource.\r
- *\r
- * To allocate ANY available resource, this API tries to allocate a resource\r
- * from the pool of (owned && non_reserved && available_right_now) resources.\r
- *\r
- * After allocating a DMA/QDMA channel or TCC, the same resource is enabled in\r
- * the shadow region specific register (DRAE/DRAEH/QRAE).\r
- *\r
- * Allocated PaRAM Set is initialized to NULL before this API returns if user\r
- * has requested for one.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param resObj [IN/OUT] Handle to the resource descriptor\r
- * object, which needs to be allocated.\r
- * In case user passes a specific resource\r
- * Id, resObj value is left unchanged.\r
- * In case user requests ANY available\r
- * resource, the allocated resource id is\r
- * returned in resObj.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function acquires a RM Instance specific semaphore\r
- * to prevent simultaneous access to the global pool of resources.\r
- * It is re-entrant, but should not be called from the user callback\r
- * function (ISR context).\r
- */\r
-EDMA3_RM_Result EDMA3_RM_allocResource(EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_ResDesc *resObj)\r
- {\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Result semResult = EDMA3_RM_SOK;\r
- unsigned int avlblIdx = 0u;\r
- unsigned int resIdClr = 0x0;\r
- unsigned int resIdSet = 0x0;\r
- unsigned int resId;\r
- volatile EDMA3_CCRL_Regs *gblRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((hEdmaResMgr == NULL) || (resObj == NULL))\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if ((rmObj == NULL) ||\r
- (rmObj->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
- else\r
- {\r
- gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- resId = resObj->resId;\r
-\r
- resIdClr = (unsigned int)(~(1u << (resId%32u)));\r
- resIdSet = (1u << (resId%32u));\r
-\r
- /**\r
- * Take the instance specific semaphore, to prevent simultaneous\r
- * access to the shared resources.\r
- */\r
- semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,\r
- EDMA3_OSSEM_NO_TIMEOUT);\r
- if (EDMA3_RM_SOK == semResult)\r
- {\r
- switch (resObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL :\r
- {\r
- if (resId == EDMA3_RM_RES_ANY)\r
- {\r
- for (avlblIdx=0u;\r
- avlblIdx <\r
- rmObj->gblCfgParams.numDmaChannels;\r
- ++avlblIdx)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[avlblIdx/32u])\r
- &\r
- (rmInstance->avlblDmaChannels[avlblIdx/32u])\r
- &\r
- ~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[avlblIdx/32u])\r
- &\r
- (1u << (avlblIdx%32u))) != FALSE)\r
- {\r
- /*\r
- * Match found.\r
- * A resource which is owned by this instance of the\r
- * Resource Manager and which is presently available\r
- * and which has not been reserved - is found.\r
- */\r
- resObj->resId = avlblIdx;\r
- /*\r
- * Mark the 'match found' resource as "Not Available"\r
- * for future requests\r
- */\r
- rmInstance->avlblDmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));\r
-\r
- /**\r
- * Check if the register modification flag is\r
- * set or not.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- /**\r
- * Enable the DMA channel in the\r
- * DRAE/DRAEH registers also.\r
- */\r
- if (avlblIdx < 32u)\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE\r
- |= (0x1u << avlblIdx);\r
- }\r
- else\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH\r
- |= (0x1u << (avlblIdx - 32u));\r
- }\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- break;\r
- }\r
- }\r
- /*\r
- * If none of the owned resources of this type is available\r
- * then report "All Resources of this type not available" error\r
- */\r
- if (avlblIdx == rmObj->gblCfgParams.numDmaChannels)\r
- {\r
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;\r
- }\r
- }\r
- else\r
- {\r
- if (resId < rmObj->gblCfgParams.numDmaChannels)\r
- {\r
- /*\r
- * Check if specified resource is owned\r
- * by this instance of the resource manager\r
- */\r
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resId/32u])&(resIdSet))!=FALSE)\r
- {\r
- /* Now check if specified resource is available presently*/\r
- if (((rmInstance->avlblDmaChannels[resId/32u])&(resIdSet))!=FALSE)\r
- {\r
- /*\r
- * Mark the specified channel as "Not Available"\r
- * for future requests\r
- */\r
- rmInstance->avlblDmaChannels[resId/32u] &= resIdClr;\r
-\r
- /**\r
- * Check if the register modification flag is\r
- * set or not.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- if (resId < 32u)\r
- {\r
- rmInstance->shadowRegs->EECR = (1UL << resId);\r
-\r
- /**\r
- * Enable the DMA channel in the\r
- * DRAE registers also.\r
- */\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE\r
- |= (0x1u << resId);\r
- }\r
- else\r
- {\r
- rmInstance->shadowRegs->EECRH = (1UL << resId);\r
-\r
- /**\r
- * Enable the DMA channel in the\r
- * DRAEH registers also.\r
- */\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH\r
- |= (0x1u << (resId - 32u));\r
- }\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- /* Specified resource is owned but is already booked */\r
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL :\r
- {\r
- if (resId == EDMA3_RM_RES_ANY)\r
- {\r
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numQdmaChannels; ++avlblIdx)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[avlblIdx/32u])\r
- &\r
- (rmInstance->avlblQdmaChannels[avlblIdx/32u])\r
- &\r
- ~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[avlblIdx/32u])\r
- &\r
- (1u << (avlblIdx%32u))) != FALSE)\r
- {\r
- resObj->resId = avlblIdx;\r
- rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));\r
-\r
- /**\r
- * Check if the register modification flag is\r
- * set or not.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- /**\r
- * Enable the QDMA channel in the\r
- * QRAE register also.\r
- */\r
- gblRegs->QRAE[rmInstance->initParam.regionId]\r
- |= (0x1u << avlblIdx);\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- break;\r
- }\r
- }\r
- /*\r
- * If none of the owned resources of this type is available\r
- * then report "All Resources of this type not available" error\r
- */\r
- if (avlblIdx == rmObj->gblCfgParams.numQdmaChannels)\r
- {\r
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;\r
- }\r
- }\r
- else\r
- {\r
- if (resId < rmObj->gblCfgParams.numQdmaChannels)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32u])&(resIdSet))!=FALSE)\r
- {\r
- if (((rmInstance->avlblQdmaChannels [resId/32u])&(resIdSet))!=FALSE)\r
- {\r
- rmInstance->avlblQdmaChannels [resId/32u] &= resIdClr;\r
-\r
- /**\r
- * Check if the register modification flag is\r
- * set or not.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- /**\r
- * Enable the QDMA channel in the\r
- * QRAE register also.\r
- */\r
- gblRegs->QRAE[rmInstance->initParam.regionId]\r
- |= (0x1u << resId);\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- /* Specified resource is owned but is already booked */\r
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_TCC :\r
- {\r
- if (resId == EDMA3_RM_RES_ANY)\r
- {\r
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numTccs; ++avlblIdx)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [avlblIdx/32u])\r
- & (rmInstance->avlblTccs [avlblIdx/32u])\r
- & ~(rmInstance->initParam.rmInstInitConfig->resvdTccs [avlblIdx/32u])\r
- & (1u << (avlblIdx%32u)))!=FALSE)\r
- {\r
- resObj->resId = avlblIdx;\r
- rmInstance->avlblTccs [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));\r
-\r
- /**\r
- * Check if the register modification flag is\r
- * set or not.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- /**\r
- * Enable the Interrupt channel in the\r
- * DRAE/DRAEH registers also.\r
- * Also, If the region id coming from this\r
- * RM instance is same as the Master RM\r
- * Instance's region id, only then we will be\r
- * getting the interrupts on the same side.\r
- * So save the TCC in the allocatedTCCs[] array.\r
- */\r
- if (avlblIdx < 32u)\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE\r
- |= (0x1u << avlblIdx);\r
-\r
- /**\r
- * Do not modify this global array if the register\r
- * modificatio flag is not set.\r
- * Reason being is based on this flag, the IPR/ICR\r
- * or error bit is cleared in the completion or\r
- * error handler ISR.\r
- */\r
- if (edma3RegionId == rmInstance->initParam.regionId)\r
- {\r
- allocatedTCCs[0u] |= (0x1u << avlblIdx);\r
- }\r
- }\r
- else\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH\r
- |= (0x1u << (avlblIdx - 32u));\r
-\r
- /**\r
- * Do not modify this global array if the register\r
- * modificatio flag is not set.\r
- * Reason being is based on this flag, the IPR/ICR\r
- * or error bit is cleared in the completion or\r
- * error handler ISR.\r
- */\r
- if (edma3RegionId == rmInstance->initParam.regionId)\r
- {\r
- allocatedTCCs[1u] |= (0x1u << (avlblIdx - 32u));\r
- }\r
- }\r
- }\r
-\r
-\r
- result = EDMA3_RM_SOK;\r
- break;\r
- }\r
- }\r
- /*\r
- * If none of the owned resources of this type is available\r
- * then report "All Resources of this type not available" error\r
- */\r
- if ( avlblIdx == rmObj->gblCfgParams.numTccs)\r
- {\r
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;\r
- }\r
- }\r
- else\r
- {\r
- if (resId < rmObj->gblCfgParams.numTccs)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32u])&(resIdSet))!=FALSE)\r
- {\r
- if (((rmInstance->avlblTccs [resId/32u])&(resIdSet))!=FALSE)\r
- {\r
- rmInstance->avlblTccs [resId/32u] &= resIdClr;\r
-\r
- /**\r
- * Check if the register modification flag is\r
- * set or not.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- /**\r
- * Enable the Interrupt channel in the\r
- * DRAE/DRAEH registers also.\r
- * Also, If the region id coming from this\r
- * RM instance is same as the Master RM\r
- * Instance's region id, only then we will be\r
- * getting the interrupts on the same side.\r
- * So save the TCC in the allocatedTCCs[] array.\r
- */\r
- if (resId < 32u)\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE\r
- |= (0x1u << resId);\r
-\r
- /**\r
- * Do not modify this global array if the register\r
- * modificatio flag is not set.\r
- * Reason being is based on this flag, the IPR/ICR\r
- * or error bit is cleared in the completion or\r
- * error handler ISR.\r
- */\r
- if (edma3RegionId == rmInstance->initParam.regionId)\r
- {\r
- allocatedTCCs[0u] |= (0x1u << resId);\r
- }\r
- }\r
- else\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH\r
- |= (0x1u << (resId - 32u));\r
-\r
- /**\r
- * Do not modify this global array if the register\r
- * modificatio flag is not set.\r
- * Reason being is based on this flag, the IPR/ICR\r
- * or error bit is cleared in the completion or\r
- * error handler ISR.\r
- */\r
- if (edma3RegionId == rmInstance->initParam.regionId)\r
- {\r
- allocatedTCCs[1u] |= (0x1u << (resId - 32u));\r
- }\r
- }\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- /* Specified resource is owned but is already booked */\r
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_PARAM_SET :\r
- {\r
- if (resId == EDMA3_RM_RES_ANY)\r
- {\r
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numPaRAMSets; ++avlblIdx)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [avlblIdx/32u])\r
- &\r
- (rmInstance->avlblPaRAMSets [avlblIdx/32u])\r
- &\r
- ~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets [avlblIdx/32u])\r
- &\r
- (1u << (avlblIdx%32u)))!=FALSE)\r
- {\r
- resObj->resId = avlblIdx;\r
- rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));\r
-\r
- /**\r
- * Also, make the actual PARAM Set NULL, checking the flag\r
- * whether it is required or not.\r
- */\r
- if ((TRUE == rmInstance->regModificationRequired)\r
- && (TRUE == rmInstance->paramInitRequired))\r
- {\r
- edma3MemSet((void *)(&gblRegs->PARAMENTRY[avlblIdx]),\r
- 0x00u,\r
- sizeof(gblRegs->PARAMENTRY[avlblIdx]));\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- break;\r
- }\r
- }\r
- /*\r
- * If none of the owned resources of this type is available\r
- * then report "All Resources of this type not available" error\r
- */\r
- if ( avlblIdx == rmObj->gblCfgParams.numPaRAMSets)\r
- {\r
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;\r
- }\r
- }\r
- else\r
- {\r
- if (resId < rmObj->gblCfgParams.numPaRAMSets)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32u])&(resIdSet))!=FALSE)\r
- {\r
- if (((rmInstance->avlblPaRAMSets [resId/32u])&(resIdSet)) !=FALSE)\r
- {\r
- rmInstance->avlblPaRAMSets [resId/32u] &= resIdClr;\r
-\r
- /**\r
- * Also, make the actual PARAM Set NULL, checking the flag\r
- * whether it is required or not.\r
- */\r
- if ((TRUE == rmInstance->regModificationRequired)\r
- && (TRUE == rmInstance->paramInitRequired))\r
- {\r
- edma3MemSet((void *)(&gblRegs->PARAMENTRY[resId]),\r
- 0x00u,\r
- sizeof(gblRegs->PARAMENTRY[resId]));\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- /* Specified resource is owned but is already booked */\r
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- break;\r
- }\r
-\r
- /* Return the semaphore back */\r
- semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);\r
- }\r
- }\r
- }\r
-\r
- /**\r
- * Check the Resource Allocation Result 'result' first. If Resource\r
- * Allocation has resulted in an error, return it (having more priority than\r
- * semResult.\r
- * Else, return semResult.\r
- */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /**\r
- * Resource Allocation successful, return semResult for returning\r
- * semaphore.\r
- */\r
- result = semResult;\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr,\r
- * const EDMA3_RM_ResDesc *resObj)\r
- * \brief This API is used to free previously allocated EDMA3 Resources like\r
- * DMA/QDMA channel, PaRAM Set or TCC.\r
- *\r
- * To free a specific resource, first this API checks whether that resource is\r
- * OWNED by the Resource Manager Instance. Then it checks whether that resource\r
- * has been allocated by the Resource Manager instance or not.\r
- *\r
- * After freeing a DMA/QDMA channel or TCC, the same resource is disabled in\r
- * the shadow region specific register (DRAE/DRAEH/QRAE).\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param resObj [IN] Handle to the resource descriptor\r
- * object, which needs to be freed.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function disables the global interrupts to prevent\r
- * simultaneous access to the global pool of resources.\r
- * It is re-entrant.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr,\r
- const EDMA3_RM_ResDesc *resObj)\r
- {\r
- unsigned int intState;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- unsigned int resId;\r
- unsigned int resIdSet = 0x0;\r
- volatile EDMA3_CCRL_Regs *gblRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((hEdmaResMgr == NULL) || (resObj == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if ((rmObj == NULL) ||\r
- (rmObj->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- resId = resObj->resId;\r
-\r
- resIdSet = 1u << (resId%32u);\r
-\r
- edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- switch (resObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL :\r
- {\r
- if (resId < rmObj->gblCfgParams.numDmaChannels)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels [resId/32u]) & (resIdSet))!=FALSE)\r
- {\r
- if (((~(rmInstance->avlblDmaChannels[resId/32u]))&(resIdSet))!=FALSE)\r
- {\r
- /*\r
- * Mark the specified channel as "Available"\r
- * for future requests\r
- */\r
- rmInstance->avlblDmaChannels[resId/32u] |= resIdSet;\r
-\r
- /**\r
- * Check if the register modification flag is\r
- * set or not.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- /**\r
- * DMA Channel is freed.\r
- * Reset the bit specific to the DMA channel\r
- * in the DRAE/DRAEH register also.\r
- */\r
- if (resId < 32u)\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE\r
- &= (~(0x1u << resId));\r
- }\r
- else\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH\r
- &= (~(0x1u << (resId-32u)));\r
- }\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_RES_ALREADY_FREE;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL :\r
- {\r
- if (resId < rmObj->gblCfgParams.numQdmaChannels)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32u]) & (resIdSet))!=FALSE)\r
- {\r
- if (((~(rmInstance->avlblQdmaChannels [resId/32u])) & (resIdSet))!=FALSE)\r
- {\r
- rmInstance->avlblQdmaChannels [resId/32u] |= resIdSet;\r
-\r
- /**\r
- * Check if the register modification flag is\r
- * set or not.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- /**\r
- * QDMA Channel is freed.\r
- * Reset the bit specific to the QDMA channel\r
- * in the QRAE register also.\r
- */\r
- gblRegs->QRAE[rmInstance->initParam.regionId]\r
- &= (~(0x1u << resId));\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_RES_ALREADY_FREE;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_TCC :\r
- {\r
- if (resId < rmObj->gblCfgParams.numTccs)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32u]) & (resIdSet))!=FALSE)\r
- {\r
- if (((~(rmInstance->avlblTccs [resId/32u])) & (resIdSet))!=FALSE)\r
- {\r
- rmInstance->avlblTccs [resId/32u] |= resIdSet;\r
-\r
- /**\r
- * Check if the register modification flag is\r
- * set or not.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- /**\r
- * Interrupt Channel is freed.\r
- * Reset the bit specific to the Interrupt\r
- * channel in the DRAE/DRAEH register also.\r
- * Also, if we have earlier saved this\r
- * TCC in allocatedTCCs[] array,\r
- * remove it from there too.\r
- */\r
- if (resId < 32u)\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE\r
- &= (~(0x1u << resId));\r
-\r
- if (edma3RegionId == rmInstance->initParam.regionId)\r
- {\r
- allocatedTCCs[0u] &= (~(0x1u << resId));\r
- }\r
- }\r
- else\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH\r
- &= (~(0x1u << (resId-32u)));\r
-\r
- if (edma3RegionId == rmInstance->initParam.regionId)\r
- {\r
- allocatedTCCs[1u] &= (~(0x1u << (resId -32u)));\r
- }\r
- }\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_RES_ALREADY_FREE;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_PARAM_SET :\r
- {\r
- if (resId < rmObj->gblCfgParams.numPaRAMSets)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32u])&(resIdSet))!=FALSE)\r
- {\r
- if (((~(rmInstance->avlblPaRAMSets [resId/32u]))&(resIdSet))!=FALSE)\r
- {\r
- rmInstance->avlblPaRAMSets [resId/32u] |= resIdSet;\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_RES_ALREADY_FREE;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- break;\r
- }\r
-\r
- }\r
-\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\r
- * \fn EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle\r
- * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj,\r
- * unsigned int *pParam, unsigned int *pTcc)\r
- * \brief Request a DMA/QDMA/Link channel.\r
- *\r
- * This API is used to allocate a logical channel (DMA/QDMA/Link) along with\r
- * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are\r
- * also allocated along with the requested channel. For Link channel, ONLY a\r
- * PaRAM Set is allocated.\r
- *\r
- * Note: To free the logical channel allocated by this API, user should call\r
- * EDMA3_RM_freeLogicalChannel () ONLY to de-allocate all the allocated resources\r
- * and remove certain mappings.\r
- *\r
- * User can request a specific logical channel by passing the channel id in\r
- * 'lChObj->resId' and channel type in 'lChObj->type'. Note that the channel\r
- * id is the same as the actual resource id. For e.g. in the case of QDMA\r
- * channels, valid channel ids are from 0 to 7 only.\r
- *\r
- * User can also request ANY available logical channel of the type\r
- * 'lChObj->type' by specifying 'lChObj->resId' as:\r
- * a) EDMA3_RM_DMA_CHANNEL_ANY: For DMA channels\r
- * b) EDMA3_RM_QDMA_CHANNEL_ANY: For QDMA channels, and\r
- * c) EDMA3_RM_PARAM_ANY: For Link channels. Normally user should use this\r
- * value to request link channels (PaRAM Sets used for linking purpose\r
- * only), unless he wants to use some specific link channels (PaRAM Sets)\r
- * which is also allowed.\r
- *\r
- * This API internally uses EDMA3_RM_allocResource () to allocate the desired\r
- * resources (DMA/QDMA channel, PaRAM Set and TCC).\r
- *\r
- * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API\r
- * sets the TCC field of the OPT PaRAM Word with the allocated TCC.\r
- *\r
- * For DMA channel, it also sets the DCHMAP register, if required.\r
- *\r
- * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and\r
- * enables the QDMA channel by writing to the QEESR register.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param lChObj [IN/OUT] Handle to the requested logical channel\r
- * object, which needs to be allocated.\r
- * It could be a specific logical channel\r
- * or ANY available logical channel of the\r
- * requested type.\r
- * In case user passes a specific resource\r
- * Id, lChObj value is left unchanged. In\r
- * case user requests ANY available\r
- * resource, the allocated resource id is\r
- * returned in lChObj->resId.\r
- *\r
- * \param pParam [IN/OUT] PaRAM Set for a particular logical\r
- * (DMA/QDMA) channel. Not used if user\r
- * requested for a Link channel.\r
- * In case user passes a specific PaRAM\r
- * Set value, pParam value is left\r
- * unchanged. In case user requests ANY\r
- * available PaRAM Set, the allocated one\r
- * is returned in pParam.\r
- *\r
- * \param pTcc [IN/OUT] TCC for a particular logical (DMA/QDMA)\r
- * channel. Not used if user requested for\r
- * a Link channel.\r
- * In case user passes a specific TCC\r
- * value, pTcc value is left unchanged.\r
- * In case user requests ANY available TCC,\r
- * the allocated one is returned in pTcc\r
- *\r
- * \return EDMA3_RM_SOK or EDMA_RM Error Code\r
- *\r
- * \note This function internally calls EDMA3_RM_allocResource (), which\r
- * acquires a RM Instance specific semaphore to prevent simultaneous\r
- * access to the global pool of resources. It is re-entrant for unique\r
- * logical channel values, but SHOULD NOT be called from the user\r
- * callback function (ISR context).\r
- */\r
-EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_ResDesc *lChObj,\r
- unsigned int *pParam,\r
- unsigned int *pTcc)\r
- {\r
- EDMA3_RM_ResDesc *chObj;\r
- EDMA3_RM_ResDesc resObj;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- unsigned int mappedPaRAMId=0u;\r
- unsigned int mappedTcc = EDMA3_RM_CH_NO_TCC_MAP;\r
- int paRAMId = (int)EDMA3_RM_RES_ANY;\r
- volatile EDMA3_CCRL_Regs *gblRegs = NULL;\r
- unsigned int qdmaChId = EDMA3_MAX_PARAM_SETS;\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((lChObj == NULL) || (hEdmaResMgr == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- chObj = lChObj;\r
-\r
- if ((chObj->type == EDMA3_RM_RES_DMA_CHANNEL)\r
- || (chObj->type == EDMA3_RM_RES_QDMA_CHANNEL))\r
- {\r
- /**\r
- * If the request is for a DMA or QDMA channel, check the\r
- * pParam and pTcc objects also.\r
- * For the Link channel request, they could be NULL.\r
- */\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((pParam == NULL) || (pTcc == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
-\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- if (rmObj->gblCfgParams.globalRegs == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- switch (chObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL:\r
- {\r
- if ((chObj->resId == EDMA3_RM_DMA_CHANNEL_ANY)\r
- || (chObj->resId == EDMA3_RM_RES_ANY))\r
- {\r
- /* Request for ANY DMA channel. */\r
- resObj.type = EDMA3_RM_RES_DMA_CHANNEL;\r
- resObj.resId = EDMA3_RM_RES_ANY;\r
- result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* DMA channel allocated successfully. */\r
- chObj->resId = resObj.resId;\r
-\r
- /**\r
- * Check the PaRAM Set user has specified for this DMA channel.\r
- * Two cases exist:\r
- * a) DCHMAP exists: Any PaRAM Set can be used\r
- * b) DCHMAP does not exist: Should not be possible\r
- * only if the channel allocated (ANY) and PaRAM requested\r
- * are same.\r
- */\r
- if ((*pParam) == EDMA3_RM_PARAM_ANY)\r
- {\r
- /* User specified ANY PaRAM Set; Check the mapping. */\r
- mappedPaRAMId = rmObj->gblCfgParams.dmaChannelPaRAMMap[resObj.resId];\r
- if (mappedPaRAMId != EDMA3_RM_CH_NO_PARAM_MAP)\r
- {\r
- /** If some PaRAM set is statically mapped to the returned\r
- * channel number, use that.\r
- */\r
- paRAMId = (int)mappedPaRAMId;\r
- }\r
- }\r
- else\r
- {\r
- /* User specified some PaRAM Set; check that can be used or not. */\r
- if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)\r
- {\r
- paRAMId = (int)(*pParam);\r
- }\r
- else\r
- {\r
- /**\r
- * Channel mapping does not exist. If the PaRAM Set requested\r
- * is the same as dma channel allocated (coincidentally), it is fine.\r
- * Else return error.\r
- */\r
- if ((*pParam) != (resObj.resId))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
-\r
- /**\r
- * Free the previously allocated DMA channel also.\r
- */\r
- EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- else\r
- {\r
- paRAMId = (int)(*pParam);\r
- }\r
- }\r
- }\r
-\r
- mappedTcc = rmObj->gblCfgParams.dmaChannelTccMap[resObj.resId];\r
- }\r
- }\r
- else\r
- {\r
- if (chObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL)\r
- {\r
- /* Request for a specific DMA channel */\r
- resObj.type = EDMA3_RM_RES_DMA_CHANNEL;\r
- resObj.resId = chObj->resId;\r
- result = EDMA3_RM_allocResource(hEdmaResMgr,\r
- (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /**\r
- * Check the PaRAM Set user has specified for this DMA channel.\r
- * Two cases exist:\r
- * a) DCHMAP exists: Any PaRAM Set can be used\r
- * b) DCHMAP does not exist: Should not be possible\r
- * only if the channel allocated (ANY) and PaRAM requested\r
- * are same.\r
- */\r
- if ((*pParam) == EDMA3_RM_PARAM_ANY)\r
- {\r
- /* User specified ANY PaRAM Set; Check the mapping. */\r
- mappedPaRAMId = rmObj->gblCfgParams.dmaChannelPaRAMMap[resObj.resId];\r
- if (mappedPaRAMId != EDMA3_RM_CH_NO_PARAM_MAP)\r
- {\r
- /** If some PaRAM set is statically mapped to the returned\r
- * channel number, use that.\r
- */\r
- paRAMId = (int)mappedPaRAMId;\r
- }\r
- }\r
- else\r
- {\r
- /* User specified some PaRAM Set; check that can be used or not. */\r
- if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)\r
- {\r
- paRAMId = (int)(*pParam);\r
- }\r
- else\r
- {\r
- /**\r
- * Channel mapping does not exist. If the PaRAM Set requested\r
- * is the same as dma channel allocated (coincidentally), it is fine.\r
- * Else return error.\r
- */\r
- if ((*pParam) != (resObj.resId))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
-\r
- /**\r
- * Free the previously allocated DMA channel also.\r
- */\r
- EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- else\r
- {\r
- paRAMId = (int)(*pParam);\r
- }\r
- }\r
- }\r
-\r
- mappedTcc = rmObj->gblCfgParams.dmaChannelTccMap[chObj->resId];\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
- break;\r
-\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL:\r
- {\r
- if ((chObj->resId == EDMA3_RM_QDMA_CHANNEL_ANY)\r
- || (chObj->resId == EDMA3_RM_RES_ANY))\r
- {\r
- /* First request for any available QDMA channel */\r
- resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;\r
- resObj.resId = EDMA3_RM_RES_ANY;\r
- result = EDMA3_RM_allocResource(hEdmaResMgr,\r
- (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* Return the actual QDMA channel id. */\r
- chObj->resId = resObj.resId;\r
-\r
- /* Save the Logical-QDMA channel id for future use. */\r
- qdmaChId = resObj.resId + EDMA3_RM_QDMA_CH_MIN_VAL;\r
-\r
- /**\r
- * Check the PaRAM Set user has specified for this QDMA channel.\r
- * If he has specified any particular PaRAM Set, use that.\r
- */\r
- if ((*pParam) != EDMA3_RM_PARAM_ANY)\r
- {\r
- /* User specified ANY PaRAM Set; Check the mapping. */\r
- paRAMId = (int)(*pParam);\r
- }\r
- }\r
- }\r
- else\r
- {\r
- if (chObj->resId < EDMA3_MAX_QDMA_CH)\r
- {\r
- /* Request for a specific QDMA channel */\r
- resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;\r
- resObj.resId = chObj->resId;\r
- result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* Save the Logical-QDMA channel id for future use. */\r
- qdmaChId = chObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL;\r
-\r
- /**\r
- * Check the PaRAM Set user has specified for this QDMA channel.\r
- * If he has specified any particular PaRAM Set, use that.\r
- */\r
- if ((*pParam) != EDMA3_RM_PARAM_ANY)\r
- {\r
- /* User specified ANY PaRAM Set; Check the mapping. */\r
- paRAMId = (int)(*pParam);\r
- }\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_PARAM_SET:\r
- {\r
- /* Request for a LINK channel. */\r
- if ((chObj->resId == EDMA3_RM_PARAM_ANY)\r
- || (chObj->resId == EDMA3_RM_RES_ANY))\r
- {\r
- /* Request for ANY LINK channel. */\r
- paRAMId = (int)EDMA3_RM_RES_ANY;\r
- }\r
- else\r
- {\r
- if (chObj->resId < edma3NumPaRAMSets)\r
- {\r
- /* Request for a Specific LINK channel. */\r
- paRAMId = (int)(chObj->resId);\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* Try to allocate the link channel */\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- resObj.resId = (unsigned int)paRAMId;\r
- result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- unsigned int linkCh = EDMA3_RM_LINK_CH_MIN_VAL;\r
-\r
- /* Return the actual PaRAM Id. */\r
- chObj->resId = resObj.resId;\r
-\r
- /*\r
- * Search for the next Link channel place-holder available,\r
- * starting from EDMA3_RM_LINK_CH_MIN_VAL.\r
- * It will be used for future operations on the Link channel.\r
- */\r
- while ((edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId != -1)\r
- && (linkCh <= EDMA3_RM_LINK_CH_MAX_VAL))\r
- {\r
- /* Move to the next place-holder. */\r
- linkCh++;\r
- }\r
-\r
- /* Verify the returned handle, it should lie in the correct range */\r
- if (linkCh > EDMA3_RM_LINK_CH_MAX_VAL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
-\r
- /* Free the PaRAM Set now. */\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- resObj.resId = chObj->resId;\r
- result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- else\r
- {\r
- /* Save the PaRAM Id for the Link Channel. */\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId = (int)(chObj->resId);\r
-\r
- /**\r
- * Remove any linking. Before doing that, check\r
- * whether it is permitted or not.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- *((&gblRegs->PARAMENTRY[chObj->resId].OPT)\r
- + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /**\r
- * For DMA/QDMA channels, we still have to allocate more resources like\r
- * TCC, PaRAM Set etc.\r
- * For Link channel, only the PaRAMSet is required and that has been\r
- * allocated so no further operations required.\r
- */\r
-\r
- /* Further resources' allocation for DMA channel. */\r
- if (chObj->type == EDMA3_RM_RES_DMA_CHANNEL)\r
- {\r
- /* First allocate a PaRAM Set */\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- /* Use the saved param id now. */\r
- resObj.resId = (unsigned int)paRAMId;\r
- result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /**\r
- * PaRAM Set allocation succeeded.\r
- * Save the PaRAM Set first.\r
- */\r
- *pParam = resObj.resId;\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].paRAMId = (int)(resObj.resId);\r
-\r
- /* Allocate the TCC now. */\r
- resObj.type = EDMA3_RM_RES_TCC;\r
- if ((*pTcc) == EDMA3_RM_TCC_ANY)\r
- {\r
- if (mappedTcc == EDMA3_RM_CH_NO_TCC_MAP)\r
- {\r
- resObj.resId = EDMA3_RM_RES_ANY;\r
- }\r
- else\r
- {\r
- resObj.resId = mappedTcc;\r
- }\r
- }\r
- else\r
- {\r
- resObj.resId = *pTcc;\r
- }\r
-\r
- result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* TCC allocation succeeded. Save it first. */\r
- *pTcc = resObj.resId;\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].tcc = resObj.resId;\r
-\r
- /**\r
- * Check first whether the global registers and the allocated\r
- * PaRAM Set can be modified or not. If yes, do the needful.\r
- * Else leave this for the user.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- /* Set TCC of the allocated Param Set. */\r
- gblRegs->PARAMENTRY[*pParam].OPT &= EDMA3_RM_OPT_TCC_CLR_MASK;\r
- gblRegs->PARAMENTRY[*pParam].OPT |= EDMA3_RM_OPT_TCC_SET_MASK(*pTcc);\r
-\r
- /**\r
- * Do the mapping between DMA channel and PaRAM Set.\r
- * Do this for the EDMA3 Controllers which have a register for mapping\r
- * DMA Channel to a particular PaRAM Set.\r
- */\r
- if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)\r
- {\r
- gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- /* Map Parameter RAM Set Number for specified channelId */\r
- gblRegs->DCHMAP[chObj->resId] &= EDMA3_RM_DCH_PARAM_CLR_MASK;\r
- gblRegs->DCHMAP[chObj->resId] |= EDMA3_RM_DCH_PARAM_SET_MASK(*pParam);\r
- }\r
-\r
- /* Remove any linking */\r
- *((&gblRegs->PARAMENTRY[*pParam].OPT)\r
- + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;\r
- }\r
- }\r
- else\r
- {\r
- /**\r
- * TCC allocation failed, free the previously allocated\r
- * PaRAM Set and DMA channel.\r
- */\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- resObj.resId = *pParam;\r
- EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- /* Reset the book-keeping data structure also. */\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].paRAMId = -1;\r
-\r
- resObj.type = chObj->type;\r
- resObj.resId = chObj->resId;\r
- EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- }\r
- else\r
- {\r
- /**\r
- * PaRAM Set allocation failed, free the previously allocated\r
- * DMA channel also.\r
- */\r
- resObj.type = chObj->type;\r
- resObj.resId = chObj->resId;\r
- EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- }\r
-\r
-\r
- /* Further resources' allocation for QDMA channel. */\r
- if (chObj->type == EDMA3_RM_RES_QDMA_CHANNEL)\r
- {\r
- /* First allocate a PaRAM Set */\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- /* Use the saved param id now. */\r
- resObj.resId = (unsigned int)paRAMId;\r
- result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /**\r
- * PaRAM Set allocation succeeded.\r
- * Save the PaRAM Set first.\r
- */\r
- *pParam = resObj.resId;\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = (int)(resObj.resId);\r
-\r
- /* Allocate the TCC now. */\r
- resObj.type = EDMA3_RM_RES_TCC;\r
- if ((*pTcc) == EDMA3_RM_TCC_ANY)\r
- {\r
- if (mappedTcc == EDMA3_RM_CH_NO_TCC_MAP)\r
- {\r
- resObj.resId = EDMA3_RM_RES_ANY;\r
- }\r
- else\r
- {\r
- resObj.resId = mappedTcc;\r
- }\r
- }\r
- else\r
- {\r
- resObj.resId = *pTcc;\r
- }\r
-\r
- result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* TCC allocation succeeded. Save it first. */\r
- *pTcc = resObj.resId;\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].tcc = resObj.resId;\r
-\r
- /**\r
- * Check first whether the global registers and the allocated\r
- * PaRAM Set can be modified or not. If yes, do the needful.\r
- * Else leave this for the user.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- /* Set TCC of the allocated Param Set. */\r
- gblRegs->PARAMENTRY[*pParam].OPT &= EDMA3_RM_OPT_TCC_CLR_MASK;\r
- gblRegs->PARAMENTRY[*pParam].OPT |= EDMA3_RM_OPT_TCC_SET_MASK(*pTcc);\r
-\r
- /* Do the mapping between QDMA channel and PaRAM Set. */\r
- /* Map Parameter RAM Set Number for specified channelId */\r
- gblRegs->QCHMAP[chObj->resId]\r
- &= EDMA3_RM_QCH_PARAM_CLR_MASK;\r
- gblRegs->QCHMAP[chObj->resId]\r
- |= EDMA3_RM_QCH_PARAM_SET_MASK(*pParam);\r
-\r
- /* Set the Trigger Word */\r
- gblRegs->QCHMAP[chObj->resId]\r
- &= EDMA3_RM_QCH_TRWORD_CLR_MASK;\r
- gblRegs->QCHMAP[chObj->resId]\r
- |= EDMA3_RM_QCH_TRWORD_SET_MASK(EDMA3_RM_QDMA_TRIG_DEFAULT);\r
-\r
- /* Remove any linking */\r
- *((&gblRegs->PARAMENTRY[*pParam].OPT)\r
- + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;\r
-\r
- /* Enable the transfer also. */\r
- rmInstance->shadowRegs->QEESR = (1u << chObj->resId);\r
- }\r
- }\r
- else\r
- {\r
- /**\r
- * TCC allocation failed, free the previously allocated\r
- * PaRAM Set and QDMA channel.\r
- */\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- resObj.resId = *pParam;\r
- EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
-\r
- /* Reset the book-keeping data structure also. */\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = -1;\r
-\r
- resObj.type = chObj->type;\r
- resObj.resId = chObj->resId;\r
- EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- }\r
- else\r
- {\r
- /**\r
- * PaRAM Set allocation failed, free the previously allocated\r
- * QDMA channel also.\r
- */\r
- resObj.type = chObj->type;\r
- resObj.resId = chObj->resId;\r
- EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- }\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- return result;\r
- }\r
-\r
-\r
-/** \fn EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle\r
- * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj)\r
- * \brief This API is used to free the specified channel (DMA/QDMA/Link) and\r
- * its associated resources (PaRAM Set, TCC etc).\r
- *\r
- * This API internally uses EDMA3_RM_freeResource () to free the desired\r
- * resources.\r
- *\r
- * For DMA/QDMA channels, it also clears the DCHMAP/QCHMAP registers\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param lChObj [IN] Handle to the logical channel object,\r
- * which needs to be freed\r
- *\r
- * \return EDMA3_RM_SOK or EDMA_RM Error Code\r
- *\r
- * \note This is a re-entrant function which internally calls\r
- * EDMA3_RM_freeResource () for resource de-allocation.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_ResDesc *lChObj)\r
- {\r
- EDMA3_RM_ResDesc *chObj;\r
- EDMA3_RM_ResDesc resObj;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- int paRAMId;\r
- unsigned int tcc;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
- unsigned int qdmaChId;\r
- unsigned int dmaChId;\r
- EDMA3_RM_InstanceInitConfig *rmConfig = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((lChObj == NULL) || (hEdmaResMgr == NULL))\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- chObj = lChObj;\r
-\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
-\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmConfig = rmInstance->initParam.rmInstInitConfig;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- if (rmObj->gblCfgParams.globalRegs == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
- }\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- switch (chObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL:\r
- {\r
- /* Save the DMA channel first. */\r
- dmaChId = chObj->resId;\r
-\r
- /**\r
- * Validate DMA channel id first.\r
- * It should be a valid channel id.\r
- */\r
- if (dmaChId >= EDMA3_MAX_DMA_CH)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-\r
- /* It should be owned and allocated by this RM only. */\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- if (((rmConfig->ownDmaChannels[dmaChId/32u])\r
- &\r
- (~(rmInstance->avlblDmaChannels[dmaChId/32u]))\r
- &\r
- (1u << (dmaChId%32u))) != FALSE)\r
- {\r
- /** Perfectly valid channel id.\r
- * Clear some channel specific registers, if it is permitted.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- if (dmaChId < 32u)\r
- {\r
- if((rmInstance->shadowRegs->SER & (1u<<dmaChId))!=FALSE)\r
- {\r
- rmInstance->shadowRegs->SECR = (1u<<dmaChId);\r
- }\r
- if((globalRegs->EMR & (1u<<dmaChId))!=FALSE)\r
- {\r
- globalRegs->EMCR = (1u<<dmaChId);\r
- }\r
- }\r
- else\r
- {\r
- if((rmInstance->shadowRegs->SERH & (1u<<(dmaChId-32u)))!=FALSE)\r
- {\r
- rmInstance->shadowRegs->SECRH = (1u<<(dmaChId-32u));\r
- }\r
- if((globalRegs->EMRH & (1u<<(dmaChId-32u)))!=FALSE)\r
- {\r
- globalRegs->EMCRH = (1u<<(dmaChId-32u));\r
- }\r
- }\r
-\r
- /* Clear DCHMAP register also. */\r
- if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)\r
- {\r
- globalRegs->DCHMAP[dmaChId] &=\r
- EDMA3_RM_DCH_PARAM_CLR_MASK;\r
- }\r
- }\r
-\r
- /* Free the PaRAM Set Now. */\r
- paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].paRAMId;\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- resObj.resId = (unsigned int)paRAMId;\r
- result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- else\r
- {\r
- /* Channel id has some problem. */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* PaRAM Set Freed */\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].paRAMId = -1;\r
-\r
- /* Free the TCC */\r
- tcc = edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].tcc;\r
- resObj.type = EDMA3_RM_RES_TCC;\r
- resObj.resId = tcc;\r
- result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* TCC Freed */\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].tcc = EDMA3_MAX_TCC;\r
-\r
- /**\r
- * Try to free the DMA Channel now. DMA Channel should\r
- * be freed only in the end because while freeing, DRAE\r
- * registers will be RESET.\r
- * After that, no shadow region specific DMA channel\r
- * register can be modified. So reset that DRAE register\r
- * ONLY in the end.\r
- */\r
- resObj.type = EDMA3_RM_RES_DMA_CHANNEL;\r
- resObj.resId = dmaChId;\r
- result = EDMA3_RM_freeResource(hEdmaResMgr,\r
- (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- }\r
- break;\r
-\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL:\r
- {\r
- /**\r
- * Calculate QDMA Logical Channel Id first.\r
- * User has given the actual QDMA channel id.\r
- * So we have to convert it to make the logical\r
- * QDMA channel id first.\r
- */\r
- qdmaChId = chObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL;\r
-\r
- /**\r
- * Validate QDMA channel id first.\r
- * It should be a valid channel id.\r
- */\r
- if (chObj->resId >= EDMA3_MAX_QDMA_CH)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-\r
- /* It should be owned and allocated by this RM only. */\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- if (((rmConfig->ownQdmaChannels[0u])\r
- &\r
- (~(rmInstance->avlblQdmaChannels[0u]))\r
- &\r
- (1u << chObj->resId)) != FALSE)\r
- {\r
- /** Perfectly valid channel id.\r
- * Clear some channel specific registers, if\r
- * it is permitted.\r
- */\r
- if (TRUE == rmInstance->regModificationRequired)\r
- {\r
- rmInstance->shadowRegs->QEECR = (1u<<chObj->resId);\r
-\r
- if((globalRegs->QEMR & (1u<<chObj->resId))!=FALSE)\r
- {\r
- globalRegs->QEMCR = (1u<<chObj->resId);\r
- }\r
-\r
- /* Unmap PARAM Set Number for specified channelId */\r
- globalRegs->QCHMAP[chObj->resId] &=\r
- EDMA3_RM_QCH_PARAM_CLR_MASK;\r
-\r
- /* Reset the Trigger Word */\r
- globalRegs->QCHMAP[chObj->resId] &=\r
- EDMA3_RM_QCH_TRWORD_CLR_MASK;\r
- }\r
-\r
- /* Free the PaRAM Set now */\r
- paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- resObj.resId = (int)paRAMId;\r
- result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- else\r
- {\r
- /* Channel id has some problem. */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* PaRAM Set Freed */\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = -1;\r
-\r
- /* Free the TCC */\r
- tcc = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].tcc;\r
- resObj.type = EDMA3_RM_RES_TCC;\r
- resObj.resId = tcc;\r
- result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* TCC Freed */\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].tcc = EDMA3_MAX_TCC;\r
-\r
- /**\r
- * Try to free the QDMA Channel now. QDMA Channel should\r
- * be freed only in the end because while freeing, QRAE\r
- * registers will be RESET.\r
- * After that, no shadow region specific QDMA channel\r
- * register can be modified. So reset that QDRAE register\r
- * ONLY in the end.\r
- */\r
- resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;\r
- resObj.resId = chObj->resId;\r
- result = EDMA3_RM_freeResource(hEdmaResMgr,\r
- (EDMA3_RM_ResDesc *)&resObj);\r
- }\r
- }\r
- break;\r
-\r
-\r
- case EDMA3_RM_RES_PARAM_SET:\r
- {\r
- /* Link Channel */\r
- if (chObj->resId < edma3NumPaRAMSets)\r
- {\r
- resObj.type = EDMA3_RM_RES_PARAM_SET;\r
- resObj.resId = chObj->resId;\r
-\r
- result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* PaRAM Set freed successfully. */\r
- unsigned int linkCh = EDMA3_RM_LINK_CH_MIN_VAL;\r
-\r
- /* Reset the Logical-Link channel */\r
- /* Search for the Logical-Link channel first */\r
- for (linkCh = EDMA3_RM_LINK_CH_MIN_VAL;\r
- linkCh < EDMA3_RM_LINK_CH_MAX_VAL;\r
- linkCh++)\r
- {\r
- if (edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId == chObj->resId)\r
- {\r
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId = -1;\r
- break;\r
- }\r
- }\r
- }\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle\r
- * hEdmaResMgr, unsigned int channelId, unsigned int paRAMId)\r
- * \brief Bind the resources DMA Channel and PaRAM Set. Both the DMA channel\r
- * and the PaRAM set should be previously allocated. If they are not,\r
- * this API will result in error.\r
- *\r
- * This API sets the DCHMAP register for a specific DMA channel. This register\r
- * is used to specify the PaRAM Set associated with that particular DMA Channel.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param channelId [IN] Previously allocated DMA Channel on which\r
- * Transfer will occur.\r
- * \param paRAMId [IN] Previously allocated PaRAM Set which\r
- * needs to be associated with the dma channel.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA_RM Error Code\r
- *\r
- * \note This API is useful only for the EDMA3 Controllers which have a\r
- * register for mapping a DMA Channel to a particular PaRAM Set\r
- * (DCHMAP register).\r
- * On platforms where this feature is not supported, this API\r
- * returns error code: EDMA3_RM_E_FEATURE_UNSUPPORTED.\r
- * This function is re-entrant for unique channelId. It is\r
- * non-re-entrant for same channelId values.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr,\r
- unsigned int channelId,\r
- unsigned int paRAMId)\r
- {\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- volatile EDMA3_CCRL_Regs *gblRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (hEdmaResMgr == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
-\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- if (rmObj->gblCfgParams.globalRegs == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((paRAMId >= rmObj->gblCfgParams.numPaRAMSets)\r
- || (channelId >= rmObj->gblCfgParams.numDmaChannels))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
- }\r
-\r
- /* DMA channel and PaRAM Set should be previously allocated. */\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[channelId/32u])\r
- &\r
- (~(rmInstance->avlblDmaChannels[channelId/32u]))\r
- &\r
- (1u << (channelId%32u))) != FALSE)\r
- {\r
- /* DMA channel allocated, check for the PaRAM Set */\r
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32u])\r
- &\r
- (~(rmInstance->avlblPaRAMSets[paRAMId/32u]))\r
- &\r
- (1u << (paRAMId%32u))) == FALSE)\r
- {\r
- /* PaRAM Set NOT allocated, return error */\r
- result = EDMA3_RM_E_RES_NOT_ALLOCATED;\r
- }\r
- }\r
- else\r
- {\r
- /* DMA channel NOT allocated, return error */\r
- result = EDMA3_RM_E_RES_NOT_ALLOCATED;\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* Map the Dma Channel to the PaRAM Set corresponding to paramId */\r
- /**\r
- * Do this for the EDMA3 Controllers which have a register for mapping\r
- * DMA Channel to a particular PaRAM Set. So check\r
- * dmaChPaRAMMapExists first.\r
- */\r
- if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)\r
- {\r
- /* Map Parameter RAM Set Number for specified channelId */\r
- gblRegs->DCHMAP[channelId] &= EDMA3_RM_DCH_PARAM_CLR_MASK;\r
- gblRegs->DCHMAP[channelId] |= EDMA3_RM_DCH_PARAM_SET_MASK(paRAMId);\r
- }\r
- else\r
- {\r
- /* Feature NOT supported on the current platform, return error. */\r
- result = EDMA3_RM_E_FEATURE_UNSUPPORTED;\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle\r
- * hEdmaResMgr, unsigned int channelId,\r
- * unsigned int paRAMId,\r
- * EDMA3_RM_QdmaTrigWord trigWord)\r
- * \brief Bind the resources QDMA Channel and PaRAM Set. Also, Set the\r
- * trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set\r
- * should be previously allocated. If they are not, this API will result in error.\r
- *\r
- * This API sets the QCHMAP register for a specific QDMA channel. This register\r
- * is used to specify the PaRAM Set associated with that particular QDMA\r
- * Channel along with the trigger word.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param channelId [IN] Previously allocated QDMA Channel on which\r
- * Transfer will occur.\r
- * \param paRAMId [IN] Previously allocated PaRAM Set, which needs to\r
- * be associated with channelId\r
- * \param trigWord [IN] The Trigger Word for the channel.\r
- * Trigger Word is the word in the PaRAM\r
- * Register Set which - when written to by CPU\r
- * -will start the QDMA transfer automatically\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant for unique channelId. It is non-re-entrant\r
- * for same channelId values.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr,\r
- unsigned int channelId,\r
- unsigned int paRAMId,\r
- EDMA3_RM_QdmaTrigWord trigWord)\r
- {\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- volatile EDMA3_CCRL_Regs *gblRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((hEdmaResMgr == NULL)\r
- || ((trigWord < EDMA3_RM_QDMA_TRIG_OPT)\r
- || (trigWord > EDMA3_RM_QDMA_TRIG_CCNT)))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
-\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- if (rmObj->gblCfgParams.globalRegs == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((paRAMId >= rmObj->gblCfgParams.numPaRAMSets)\r
- || (channelId >= rmObj->gblCfgParams.numQdmaChannels))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
- }\r
-\r
- /* QDMA channel and PaRAM Set should be previously allocated. */\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[channelId/32u])\r
- &\r
- (~(rmInstance->avlblQdmaChannels[channelId/32u]))\r
- &\r
- (1u << (channelId%32u))) != FALSE)\r
- {\r
- /* QDMA channel allocated, check for the PaRAM Set */\r
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32u])\r
- &\r
- (~(rmInstance->avlblPaRAMSets[paRAMId/32u]))\r
- &\r
- (1u << (paRAMId%32u))) == FALSE)\r
- {\r
- /* PaRAM Set NOT allocated, return error */\r
- result = EDMA3_RM_E_RES_NOT_ALLOCATED;\r
- }\r
- }\r
- else\r
- {\r
- /* QDMA channel NOT allocated, return error */\r
- result = EDMA3_RM_E_RES_NOT_ALLOCATED;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* Map Parameter RAM Set Number for specified channelId */\r
- gblRegs->QCHMAP[channelId] &= EDMA3_RM_QCH_PARAM_CLR_MASK;\r
- gblRegs->QCHMAP[channelId] |= EDMA3_RM_QCH_PARAM_SET_MASK(paRAMId);\r
-\r
- /* Set the Trigger Word */\r
- gblRegs->QCHMAP[channelId] &= EDMA3_RM_QCH_TRWORD_CLR_MASK;\r
- gblRegs->QCHMAP[channelId] |= EDMA3_RM_QCH_TRWORD_SET_MASK(trigWord);\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\r
- * \fn EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr,\r
- * const EDMA3_RM_ResDesc *channelObj, unsigned int tcc,\r
- * EDMA3_RM_TccCallback tccCb, void *cbData);\r
- * \brief Register Interrupt / Completion Handler for a given TCC.\r
- *\r
- * This function enables the interrupts in IESR/IESRH, only if the callback\r
- * function provided by the user is NON-NULL. Moreover, if a call-back function\r
- * is already registered against that TCC, the API fails with the error code\r
- * EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED. For a NULL callback function,\r
- * this API returns error.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened\r
- * EDMA3 Resource Manager Instance\r
- * \param channelObj [IN] Channel ID and type (DMA or QDMA\r
- * Channel), allocated earlier, and\r
- * corresponding to which a callback\r
- * function needs to be registered\r
- * against the associated TCC.\r
- * \param tcc [IN] TCC against which the handler needs to\r
- * be registered.\r
- * \param tccCb [IN] The Callback function to be registered\r
- * against the TCC.\r
- * \param cbData [IN] Callback data to be passed while calling\r
- * the callback function.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant for unique tcc values. It is non-\r
- * re-entrant for same tcc value.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr,\r
- const EDMA3_RM_ResDesc *channelObj,\r
- unsigned int tcc,\r
- EDMA3_RM_TccCallback tccCb,\r
- void *cbData)\r
- {\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((NULL == hEdmaResMgr) || (NULL == channelObj))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-\r
- /* Callback function should NOT be NULL */\r
- if (NULL == tccCb)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((EDMA3_RM_SOK == result) && (tcc >= rmObj->gblCfgParams.numTccs))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /* Check whether the callback has already registered. */\r
- if (NULL != edma3IntrParams[tcc].tccCb)\r
- {\r
- result = EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED;\r
- }\r
- else\r
- {\r
- /* Store the mapping b/w DMA/QDMA channel and TCC first. */\r
- if (channelObj->type == EDMA3_RM_RES_DMA_CHANNEL)\r
- {\r
- /* DMA channel */\r
- if (channelObj->resId < rmObj->gblCfgParams.numDmaChannels)\r
- {\r
- /* Save the TCC */\r
- edma3DmaChTccMapping[channelObj->resId] = tcc;\r
- }\r
- else\r
- {\r
- /* Error!!! */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- else\r
- {\r
- if (channelObj->type == EDMA3_RM_RES_QDMA_CHANNEL)\r
- {\r
- /* QDMA channel */\r
- if (channelObj->resId < rmObj->gblCfgParams.numQdmaChannels)\r
- {\r
- /* Save the TCC */\r
- edma3QdmaChTccMapping[channelObj->resId] = tcc;\r
- }\r
- else\r
- {\r
- /* Error!!! */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- else\r
- {\r
- /* Error!!! */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /**\r
- * Enable the interrupts in IESR/IESRH, only if the Callback\r
- * function is NOT NULL.\r
- */\r
- if (tcc < 32u)\r
- {\r
- rmInstance->shadowRegs->IESR = (1UL << tcc);\r
- }\r
- else\r
- {\r
- rmInstance->shadowRegs->IESRH = (1UL << (tcc-32u));\r
- }\r
-\r
- /* Save the callback functions also */\r
- edma3IntrParams[tcc].cbData = cbData;\r
- edma3IntrParams[tcc].tccCb = tccCb;\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-\r
-/**\r
- * \fn EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle\r
- * hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj);\r
- * \brief Unregister the previously registered callback function against a\r
- * DMA/QDMA channel.\r
- *\r
- * This function unregisters the previously registered callback function against\r
- * a DMA/QDMA channel by removing any stored callback function. Moreover, it\r
- * clears the interrupt enable register (IESR/IESRH) by writing to the IECR/\r
- * IECRH register, for the TCC associated with that particular channel.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened\r
- * EDMA3 Resource Manager Instance\r
- * \param channelObj [IN] Channel ID and type, allocated earlier\r
- * (DMA or QDMA Channel ONLY), and\r
- * corresponding to which a TCC is there.\r
- * Against that TCC, the callback needs\r
- * to be un-registered.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code.\r
- *\r
- * \note This function is re-entrant for unique (channelObj->type +\r
- * channelObj->resId) combination. It is non-re-entrant for same\r
- * channelObj Resource.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle hEdmaResMgr,\r
- const EDMA3_RM_ResDesc *channelObj)\r
- {\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- unsigned int mappedTcc = EDMA3_MAX_TCC;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((NULL == hEdmaResMgr) || (NULL == channelObj))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- if (channelObj->type == EDMA3_RM_RES_DMA_CHANNEL)\r
- {\r
- /* DMA channel */\r
- if (channelObj->resId < rmObj->gblCfgParams.numDmaChannels)\r
- {\r
- /* Save the mapped TCC */\r
- mappedTcc = edma3DmaChTccMapping[channelObj->resId];\r
-\r
- /* Remove the mapping now. */\r
- edma3DmaChTccMapping[channelObj->resId] = EDMA3_MAX_TCC;\r
- }\r
- else\r
- {\r
- /* Error!!! */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- else\r
- {\r
- if (channelObj->type == EDMA3_RM_RES_QDMA_CHANNEL)\r
- {\r
- /* QDMA channel */\r
- if (channelObj->resId < rmObj->gblCfgParams.numQdmaChannels)\r
- {\r
- /* Save the mapped TCC */\r
- mappedTcc = edma3QdmaChTccMapping[channelObj->resId];\r
-\r
- /* Remove the mapping now. */\r
- edma3QdmaChTccMapping[channelObj->resId] = EDMA3_MAX_TCC;\r
- }\r
- else\r
- {\r
- /* Error!!! */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- else\r
- {\r
- /* Error!!! */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /* Remove the callback function too */\r
- if (mappedTcc < 32u)\r
- {\r
- rmInstance->shadowRegs->IECR = (1UL << mappedTcc);\r
- }\r
- else\r
- {\r
- rmInstance->shadowRegs->IECRH = (1UL << (mappedTcc-32u));\r
- }\r
-\r
- edma3IntrParams[mappedTcc].cbData = NULL;\r
- edma3IntrParams[mappedTcc].tccCb = NULL;\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle\r
- * hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj,\r
- * unsigned int numResources)\r
- * \brief Allocate a contiguous region of specified EDMA3 Resource\r
- * like DMA channel, QDMA channel, PaRAM Set or TCC.\r
- *\r
- * This API is used to allocate a contiguous region of specified EDMA3\r
- * Resources like DMA channel, QDMA channel, PaRAM Set or TCC.\r
- *\r
- * User can specify a particular resource Id to start with and go up to the\r
- * number of resources requested. The specific resource id to start from could\r
- * be passed in 'firstResIdObject->resId' and the number of resources requested\r
- * in 'numResources'.\r
- *\r
- * User can also request ANY available resource(s) of the type\r
- * 'firstResIdObject->type' by specifying 'firstResIdObject->resId' as\r
- * EDMA3_RM_RES_ANY.\r
- *\r
- * ANY types of resources are those resources when user doesn't care about the\r
- * actual resource allocated; user just wants a resource of the type specified.\r
- * One use-case is to perform memory-to-memory data transfer operation. This\r
- * operation can be performed using any available DMA or QDMA channel. User\r
- * doesn't need any specific channel for the same.\r
- *\r
- * To allocate specific contiguous resources, first this API checks whether\r
- * those requested resources are OWNED by the Resource Manager instance. Then\r
- * it checks the current availability of those resources.\r
- *\r
- * To allocate ANY available contiguous resources, this API tries to allocate\r
- * resources from the pool of (owned && non_reserved && available_right_now)\r
- * resources.\r
- *\r
- * After allocating DMA/QDMA channels or TCCs, the same resources are enabled in\r
- * the shadow region specific register (DRAE/DRAEH/QRAE). Allocated PaRAM Sets\r
- * are initialized to NULL before this API returns.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param firstResIdObj [IN] Handle to the first resource descriptor\r
- * object, which needs to be allocated.\r
- * firstResIdObject->resId could be a valid\r
- * resource id in case user wants to\r
- * allocate specific resources OR it could\r
- * be EDMA3_RM_RES_ANY in case user wants\r
- * only the required number of resources\r
- * and doesn't care about which resources\r
- * were allocated.\r
- * \param numResources [IN] Number of contiguous resources user\r
- * wants to allocate.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function acquires a RM Instance specific semaphore\r
- * to prevent simultaneous access to the global pool of resources.\r
- * It is re-entrant, but should not be called from the user callback\r
- * function (ISR context).\r
- */\r
-EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_ResDesc *firstResIdObj,\r
- unsigned int numResources)\r
- {\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_ResDesc *resObj = NULL;\r
- unsigned int resAllocIdx = 0u;\r
- unsigned int firstResId;\r
- unsigned int lastResId = 0u;\r
- unsigned int maxNumResources = 0u;\r
- EDMA3_RM_Result semResult = EDMA3_RM_SOK;\r
- unsigned int resIdClr = 0x0;\r
- unsigned int resIdSet = 0x0;\r
- volatile EDMA3_CCRL_Regs *gblRegs = NULL;\r
- unsigned int i = 0u;\r
- unsigned int position = 0u;\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((hEdmaResMgr == NULL) || (firstResIdObj == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- if (rmInstance->initParam.rmSemHandle == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- resObj = firstResIdObj;\r
- if (resObj != NULL)\r
- {\r
- firstResId = resObj->resId;\r
- }\r
-\r
- switch (resObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL :\r
- maxNumResources = rmObj->gblCfgParams.numDmaChannels;\r
- break;\r
- case EDMA3_RM_RES_QDMA_CHANNEL :\r
- maxNumResources = rmObj->gblCfgParams.numQdmaChannels;\r
- break;\r
- case EDMA3_RM_RES_TCC :\r
- maxNumResources = rmObj->gblCfgParams.numTccs;\r
- break;\r
- case EDMA3_RM_RES_PARAM_SET :\r
- maxNumResources = rmObj->gblCfgParams.numPaRAMSets;\r
- break;\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- break;\r
- }\r
- }\r
-\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /* First resource id (firstResId) can be a valid Resource ID as well as\r
- * 'EDMA3_RM_RES_ANY', in case user does not want to\r
- * start from a specific resource. For eg, user allocating link channels.\r
- */\r
- if (firstResId != EDMA3_RM_RES_ANY)\r
- {\r
- /* User want specific resources. */\r
- lastResId = firstResId + numResources;\r
-\r
- if (((firstResId >= maxNumResources) || (firstResId > lastResId))\r
- || (lastResId > maxNumResources))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- else\r
- {\r
- /* (firstResId == EDMA3_RM_RES_ANY)\r
- * So just check whether the number of resources\r
- * requested does not cross the limit.\r
- */\r
- if (numResources > maxNumResources)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* Now try to allocate resources for the first case */\r
- if (firstResId != EDMA3_RM_RES_ANY)\r
- {\r
- /* Request for specific resources */\r
-\r
- /**\r
- * Take the instance specific semaphore, to prevent simultaneous\r
- * access to the shared resources.\r
- */\r
- semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,\r
- EDMA3_OSSEM_NO_TIMEOUT);\r
-\r
- if (EDMA3_RM_SOK == semResult)\r
- {\r
- switch (resObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL :\r
- {\r
- for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)\r
- {\r
- resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u)));\r
- resIdSet = (1u << (resAllocIdx%32u));\r
-\r
- /* Check whether it is owned or not */\r
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resAllocIdx/32u])&(resIdSet)) != FALSE)\r
- {\r
- /* Now check if specified resource is available presently*/\r
- if (((rmInstance->avlblDmaChannels[resAllocIdx/32u])&(resIdSet)) != FALSE)\r
- {\r
- /*\r
- * Mark the specified resource as "Not Available"\r
- * for future requests\r
- */\r
- rmInstance->avlblDmaChannels[resAllocIdx/32u] &= resIdClr;\r
-\r
- if (resAllocIdx < 32u)\r
- {\r
- rmInstance->shadowRegs->EECR = (1UL << resAllocIdx);\r
-\r
- /**\r
- * Enable the DMA channel in the\r
- * DRAE registers also.\r
- */\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE\r
- |= (0x1u << resAllocIdx);\r
- }\r
- else\r
- {\r
- rmInstance->shadowRegs->EECRH = (1UL << (resAllocIdx - 32u));\r
-\r
- /**\r
- * Enable the DMA channel in the\r
- * DRAEH registers also.\r
- */\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH\r
- |= (0x1u << (resAllocIdx - 32u));\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- /* Specified resource is owned but is already booked */\r
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- break;\r
- }\r
- }\r
-\r
- break;\r
- }\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL:\r
- {\r
- for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)\r
- {\r
- resIdClr = (unsigned int)(~(1u << resAllocIdx));\r
- resIdSet = (1u << resAllocIdx);\r
-\r
- /* Check whether it is owned or not */\r
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u])&(resIdSet))!=FALSE)\r
- {\r
- /* Now check if specified resource is available presently*/\r
- if (((rmInstance->avlblQdmaChannels[0u])&(resIdSet))!=FALSE)\r
- {\r
- /*\r
- * Mark the specified resource as "Not Available"\r
- * for future requests\r
- */\r
- rmInstance->avlblQdmaChannels[0u] &= resIdClr;\r
-\r
- /**\r
- * Enable the QDMA channel in the\r
- * QRAE register also.\r
- */\r
- gblRegs->QRAE[rmInstance->initParam.regionId]\r
- |= (0x1u << resAllocIdx);\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- /* Specified resource is owned but is already booked */\r
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- break;\r
- }\r
- }\r
-\r
- break;\r
- }\r
-\r
- case EDMA3_RM_RES_TCC:\r
- {\r
- for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)\r
- {\r
- resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u)));\r
- resIdSet = (1u << (resAllocIdx%32u));\r
-\r
- /* Check whether it is owned or not */\r
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs[resAllocIdx/32u])&(resIdSet))!=FALSE)\r
- {\r
- /* Now check if specified resource is available presently*/\r
- if (((rmInstance->avlblTccs[resAllocIdx/32u])&(resIdSet))!=FALSE)\r
- {\r
- /*\r
- * Mark the specified resource as "Not Available"\r
- * for future requests\r
- */\r
- rmInstance->avlblTccs[resAllocIdx/32u] &= resIdClr;\r
-\r
- /**\r
- * Enable the Interrupt channel in the\r
- * DRAE/DRAEH registers also.\r
- * Also, If the region id coming from this\r
- * RM instance is same as the Master RM\r
- * Instance's region id, only then we will be\r
- * getting the interrupts on the same side.\r
- * So save the TCC in the allocatedTCCs[] array.\r
- */\r
- if (resAllocIdx < 32u)\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE\r
- |= (0x1u << resAllocIdx);\r
-\r
- if (edma3RegionId == rmInstance->initParam.regionId)\r
- {\r
- allocatedTCCs[0u] |= (0x1u << resAllocIdx);\r
- }\r
- }\r
- else\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH\r
- |= (0x1u << (resAllocIdx - 32u));\r
-\r
- if (edma3RegionId == rmInstance->initParam.regionId)\r
- {\r
- allocatedTCCs[1u] |= (0x1u << (resAllocIdx - 32u));\r
- }\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- /* Specified resource is owned but is already booked */\r
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- break;\r
- }\r
- }\r
-\r
- break;\r
- }\r
-\r
- case EDMA3_RM_RES_PARAM_SET:\r
- {\r
- for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)\r
- {\r
- resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u)));\r
- resIdSet = (1u << (resAllocIdx%32u));\r
-\r
- /* Check whether it is owned or not */\r
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resAllocIdx/32u])&(resIdSet))!=FALSE)\r
- {\r
- /* Now check if specified resource is available presently*/\r
- if (((rmInstance->avlblPaRAMSets[resAllocIdx/32u])&(resIdSet))!=FALSE)\r
- {\r
- /*\r
- * Mark the specified resource as "Not Available"\r
- * for future requests\r
- */\r
- rmInstance->avlblPaRAMSets[resAllocIdx/32u] &= resIdClr;\r
-\r
- /**\r
- * Also, make the actual PARAM Set NULL, checking the flag\r
- * whether it is required or not.\r
- */\r
- if (TRUE == rmInstance->paramInitRequired)\r
- {\r
- edma3MemSet((void *)(&gblRegs->PARAMENTRY[resAllocIdx]),\r
- 0x00u,\r
- sizeof(gblRegs->PARAMENTRY[resAllocIdx]));\r
- }\r
-\r
- result = EDMA3_RM_SOK;\r
- }\r
- else\r
- {\r
- /* Specified resource is owned but is already booked */\r
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- /*\r
- * Specified resource is not owned by this instance\r
- * of the Resource Manager\r
- */\r
- result = EDMA3_RM_E_RES_NOT_OWNED;\r
- break;\r
- }\r
- }\r
-\r
- break;\r
- }\r
-\r
- default:\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- break;\r
- }\r
- }\r
-\r
- /* resource allocation completed, release the semaphore first */\r
- semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);\r
- }\r
-\r
- }\r
- else\r
- {\r
- /* (firstResId == EDMA3_RM_RES_ANY) */\r
- /**\r
- * Take the instance specific semaphore, to prevent simultaneous\r
- * access to the shared resources.\r
- */\r
- semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,\r
- EDMA3_OSSEM_NO_TIMEOUT);\r
-\r
- if (EDMA3_RM_SOK == semResult)\r
- {\r
- /**\r
- * We have to search three different arrays, namely ownedResoures,\r
- * avlblResources and resvdResources, to find the 'common' contiguous\r
- * resources. For this, take an 'AND' of all three arrays in one single\r
- * array and use your algorithm on that array.\r
- */\r
- switch (resObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL:\r
- {\r
- /* AND all the arrays to look into */\r
- contiguousDmaRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0u]\r
- & rmInstance->avlblDmaChannels[0u])\r
- & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[0u]))\r
- );\r
- contiguousDmaRes[1u] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1u]\r
- & rmInstance->avlblDmaChannels[1u])\r
- & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[1u]))\r
- );\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL:\r
- {\r
- /* AND all the arrays to look into */\r
- contiguousQdmaRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u]\r
- & rmInstance->avlblQdmaChannels[0u])\r
- & (~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[0u]))\r
- );\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_TCC:\r
- {\r
- /* AND all the arrays to look into */\r
- contiguousTccRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[0u]\r
- & rmInstance->avlblTccs[0u])\r
- & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[0u]))\r
- );\r
- contiguousTccRes[1u] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[1u]\r
- & rmInstance->avlblTccs[1u])\r
- & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[1u]))\r
- );\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_PARAM_SET:\r
- {\r
- /* AND all the arrays to look into */\r
- for (i = 0u; i < (maxNumResources/32u); ++i)\r
- {\r
- contiguousParamRes[i] = ((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[i]\r
- & rmInstance->avlblPaRAMSets[i])\r
- & (~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[i]))\r
- );\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- break;\r
- }\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /**\r
- * Try to allocate 'numResources' contiguous resources\r
- * of type RES_ANY.\r
- */\r
- result = allocAnyContigRes (resObj->type, numResources, &position);\r
-\r
- /**\r
- * If result != EDMA3_RM_SOK, resource allocation failed.\r
- * Else resources successfully allocated.\r
- */\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* Update the first resource id with the position returned. */\r
- resObj->resId = position;\r
-\r
- /*\r
- * Do some further changes in the book-keeping\r
- * data structures and global registers accordingly.\r
- */\r
- result = gblChngAllocContigRes(rmInstance, resObj, numResources);\r
- }\r
- }\r
-\r
- /* resource allocation completed, release the semaphore first */\r
- semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);\r
- }\r
- }\r
- }\r
-\r
-\r
- /**\r
- * Check the Resource Allocation Result 'result' first. If Resource\r
- * Allocation has resulted in an error, return it (having more priority than\r
- * semResult. Else, return semResult.\r
- */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /**\r
- * Resource Allocation successful, return semResult for returning\r
- * semaphore.\r
- */\r
- result = semResult;\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\r
- * \fn EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle\r
- * hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj,\r
- * unsigned int numResources)\r
- * \brief Free a contiguous region of specified EDMA3 Resource\r
- * like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated.\r
- *\r
- * This API frees a contiguous region of specified EDMA3 Resources\r
- * like DMA channel, QDMA channel, PaRAM Set or TCC, which have been previously\r
- * allocated. In case of an error during the freeing of any specific resource,\r
- * user can check the 'firstResIdObj' object to know the last resource id\r
- * whose freeing has failed. In case of success, there is no need to check this\r
- * object.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened\r
- * Resource Manager Instance.\r
- * \param firstResIdObj [IN/OUT] Handle to the first resource\r
- * descriptor object, which needs to be\r
- * freed. In case of an error while\r
- * freeing any particular resource,\r
- * the last resource id whose freeing has\r
- * failed is returned in this resource\r
- * descriptor object.\r
- * \param numResources [IN] Number of contiguous resources allocated\r
- * previously which user wants to release\r
- *\r
- * \note This is a re-entrant function which internally calls\r
- * EDMA3_RM_freeResource() for resource de-allocation.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_ResDesc *firstResIdObj,\r
- unsigned int numResources)\r
- {\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_ResDesc *resObj;\r
- unsigned int resFreeIdx = 0u;\r
- unsigned int firstResId;\r
- unsigned int lastResId;\r
- unsigned int maxNumResources = 0u;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((hEdmaResMgr == NULL) || (firstResIdObj == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- resObj = firstResIdObj;\r
- if (resObj != NULL)\r
- {\r
- firstResId = resObj->resId;\r
- lastResId = firstResId + (numResources - 1u);\r
- }\r
-\r
- switch (resObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL :\r
- maxNumResources = rmObj->gblCfgParams.numDmaChannels;\r
- break;\r
- case EDMA3_RM_RES_QDMA_CHANNEL :\r
- maxNumResources = rmObj->gblCfgParams.numQdmaChannels;\r
- break;\r
- case EDMA3_RM_RES_TCC :\r
- maxNumResources = rmObj->gblCfgParams.numTccs;\r
- break;\r
- case EDMA3_RM_RES_PARAM_SET :\r
- maxNumResources = rmObj->gblCfgParams.numPaRAMSets;\r
- break;\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- break;\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- if ((firstResId > lastResId) || (lastResId >= maxNumResources))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- for (resFreeIdx = firstResId; resFreeIdx <= lastResId; ++resFreeIdx)\r
- {\r
- resObj->resId = resFreeIdx;\r
- result = EDMA3_RM_freeResource(rmInstance, resObj);\r
-\r
- if (result != EDMA3_RM_SOK)\r
- {\r
- break;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr,\r
- * unsigned int regOffset,\r
- * unsigned int newRegValue)\r
- * \brief Set the Channel Controller (CC) Register value\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param regOffset [IN] CC Register offset whose value needs to be\r
- * set. It should be word-aligned.\r
- * \param newRegValue [IN] New CC Register Value\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is non re-entrant for users using the same\r
- * Resource Manager handle.\r
- * Before modifying a register, it tries to acquire a semaphore\r
- * (RM instance specific), to protect simultaneous\r
- * modification of the same register by two different users.\r
- * After the successful change, it releases the semaphore.\r
- * For users using different RM handles, this function is re-entrant.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr,\r
- unsigned int regOffset,\r
- unsigned int newRegValue)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- volatile unsigned int regPhyAddr = 0x0u;\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((hEdmaResMgr == NULL) || ((regOffset % 4u) != 0))\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
- else\r
- {\r
- if (rmObj->gblCfgParams.globalRegs != NULL)\r
- {\r
- /**\r
- * Take the instance specific semaphore, to prevent simultaneous\r
- * access to the shared resources.\r
- */\r
- result = edma3OsSemTake(rmInstance->initParam.rmSemHandle,\r
- EDMA3_OSSEM_NO_TIMEOUT);\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /* Semaphore taken successfully, modify the registers. */\r
- regPhyAddr = (unsigned int)(rmObj->gblCfgParams.globalRegs) + regOffset;\r
-\r
- *(unsigned int *)regPhyAddr = newRegValue;\r
-\r
- /* Return the semaphore back */\r
- result = edma3OsSemGive(rmInstance->initParam.rmSemHandle);\r
- }\r
- }\r
- }\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr,\r
- * unsigned int regOffset,\r
- * unsigned int *regValue)\r
- * \brief Get the Channel Controller (CC) Register value\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param regOffset [IN] CC Register offset whose value is\r
- * needed. It should be word-aligned.\r
- * \param regValue [IN/OUT] Fetched CC Register Value\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr,\r
- unsigned int regOffset,\r
- unsigned int *regValue)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- volatile unsigned int regPhyAddr = 0x0u;\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (((hEdmaResMgr == NULL) || (regValue == NULL))\r
- || ((regOffset % 4u) != 0))\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
- else\r
- {\r
- if (rmObj->gblCfgParams.globalRegs != NULL)\r
- {\r
- regPhyAddr = (unsigned int)(rmObj->gblCfgParams.globalRegs) + regOffset;\r
-\r
- *regValue = *(unsigned int *)regPhyAddr;\r
- }\r
- }\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle\r
- * hEdmaResMgr, unsigned int tccNo)\r
- * \brief Wait for a transfer completion interrupt to occur and clear it.\r
- *\r
- * This is a blocking function that returns when the IPR/IPRH bit corresponding\r
- * to the tccNo specified, is SET. It clears the corresponding bit while\r
- * returning also.\r
- *\r
- * This function waits for the specific bit indefinitely in a tight loop, with\r
- * out any delay in between. USE IT CAUTIOUSLY.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param tccNo [IN] TCC, specific to which the function\r
- * waits on a IPR/IPRH bit.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant for different tccNo.\r
- *\r
- */\r
-EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,\r
- unsigned int tccNo)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
- volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;\r
- unsigned int tccBitMask = 0x0u;\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (hEdmaResMgr == NULL)\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if ((rmObj == NULL) || (rmObj->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
- else\r
- {\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (tccNo >= rmObj->gblCfgParams.numTccs)\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
- shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)\r
- (&globalRegs->SHADOW[rmInstance->initParam.regionId]);\r
-\r
-\r
- if (shadowRegs != NULL)\r
- {\r
- if(tccNo < 32u)\r
- {\r
- tccBitMask = (1u << tccNo);\r
-\r
- /* Check the status of the IPR[tccNo] bit. */\r
- while (FALSE == (shadowRegs->IPR & tccBitMask))\r
- {\r
- /* Transfer not yet completed, bit not SET */\r
- }\r
-\r
- /**\r
- * Bit found SET, transfer is completed,\r
- * clear the pending interrupt and return.\r
- */\r
- shadowRegs->ICR = tccBitMask;\r
- }\r
- else\r
- {\r
- tccBitMask = (1u << (tccNo - 32u));\r
-\r
- /* Check the status of the IPRH[tccNo-32] bit. */\r
- while (FALSE == (shadowRegs->IPRH & tccBitMask))\r
- {\r
- /* Transfer not yet completed, bit not SET */\r
- }\r
-\r
- /**\r
- * Bit found SET, transfer is completed,\r
- * clear the pending interrupt and return.\r
- */\r
- shadowRegs->ICRH = tccBitMask;\r
- }\r
- }\r
- }\r
- }\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle\r
- * hEdmaResMgr, unsigned int tccNo,\r
- * unsigned short *tccStatus)\r
- * \brief Returns the status of a previously initiated transfer.\r
- *\r
- * This is a non-blocking function that returns the status of a previously\r
- * initiated transfer, based on the IPR/IPRH bit. This bit corresponds to\r
- * the tccNo specified by the user. It clears the corresponding bit, if SET,\r
- * while returning also.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param tccNo [IN] TCC, specific to which the function\r
- * checks the status of the IPR/IPRH bit.\r
- * \param tccStatus [IN/OUT] Status of the transfer is returned here.\r
- * Returns "TRUE" if the transfer has\r
- * completed (IPR/IPRH bit SET),\r
- * "FALSE" if the transfer has not\r
- * completed successfully (IPR/IPRH bit\r
- * NOT SET).\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant for different tccNo.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,\r
- unsigned int tccNo,\r
- unsigned short *tccStatus)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
- volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;\r
- unsigned int tccBitMask = 0x0u;\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((hEdmaResMgr == NULL) || (tccStatus == NULL))\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if ((rmObj == NULL) || (rmObj->gblCfgParams.globalRegs == NULL))\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
- else\r
- {\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (tccNo >= rmObj->gblCfgParams.numTccs)\r
- {\r
- result = (EDMA3_RM_E_INVALID_PARAM);\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
- shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)\r
- (&globalRegs->SHADOW[rmInstance->initParam.regionId]);\r
-\r
- /* Reset the tccStatus */\r
- *tccStatus = FALSE;\r
-\r
- if (shadowRegs != NULL)\r
- {\r
- if(tccNo < 32u)\r
- {\r
- tccBitMask = (1u << tccNo);\r
-\r
- /* Check the status of the IPR[tccNo] bit. */\r
- if ((shadowRegs->IPR & tccBitMask) != FALSE)\r
- {\r
- /* Transfer completed, bit found SET */\r
- *tccStatus = TRUE;\r
-\r
- /* Clear the pending interrupt also. */\r
- shadowRegs->ICR = tccBitMask;\r
- }\r
- }\r
- else\r
- {\r
- tccBitMask = (1u << (tccNo - 32u));\r
-\r
- /* Check the status of the IPRH[tccNo-32] bit. */\r
- if ((shadowRegs->IPRH & tccBitMask) != FALSE)\r
- {\r
- /* Transfer completed, bit found SET */\r
- *tccStatus = TRUE;\r
-\r
- /* Clear the pending interrupt also. */\r
- shadowRegs->ICRH = tccBitMask;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,\r
- * EDMA3_RM_ResDesc *lChObj,\r
- * const EDMA3_RM_PaRAMRegs *newPaRAM)\r
- * \brief Copy the user specified PaRAM Set onto the PaRAM Set\r
- * associated with the logical channel (DMA/QDMA/Link).\r
- *\r
- * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set\r
- * associated with the logical channel. OPT field of the PaRAM Set is written\r
- * first and the CCNT field is written last.\r
- *\r
- * Caution: It should be used carefully when programming the QDMA channels whose\r
- * trigger words are not CCNT field.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param lChObj [IN] Logical Channel object for which new\r
- * PaRAM set is specified. User should pass\r
- * the resource type and id in this object.\r
- * \param newPaRAM [IN] PaRAM set to be copied onto existing one\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant for unique lChObj values. It is non-\r
- * re-entrant for same lChObj value.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_ResDesc *lChObj,\r
- const EDMA3_RM_PaRAMRegs *newPaRAM)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- int paRAMId = 0u;\r
- unsigned int qdmaChId = 0u;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (hEdmaResMgr == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-\r
- if ((lChObj == NULL) || (newPaRAM == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
-\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- if (rmObj->gblCfgParams.globalRegs == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- switch (lChObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL:\r
- {\r
- if (lChObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL)\r
- {\r
- paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][lChObj->resId].paRAMId;\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL:\r
- {\r
- if (lChObj->resId < EDMA3_MAX_QDMA_CH)\r
- {\r
- qdmaChId = lChObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL;\r
- paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_PARAM_SET:\r
- {\r
- if (lChObj->resId < edma3NumPaRAMSets)\r
- {\r
- /**\r
- * User has passed the actual param set value here.\r
- * Use this value only\r
- */\r
- paRAMId = (int)(lChObj->resId);\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* Check the param id first. */\r
- if ((paRAMId != -1) && ((unsigned int)paRAMId < edma3NumPaRAMSets))\r
- {\r
- /* Set the PaRAM Set now. */\r
- edma3MemCpy ((void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)),\r
- (const void *)newPaRAM,\r
- sizeof(EDMA3_CCRL_ParamentryRegs));\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,\r
- * EDMA3_RM_ResDesc *lChObj,\r
- * EDMA3_RM_PaRAMRegs *currPaRAM)\r
- * \brief Retrieve existing PaRAM set associated with specified logical\r
- * channel (DMA/QDMA/Link).\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param lChObj [IN] Logical Channel object for which the\r
- * PaRAM set is requested. User should pass\r
- * the resource type and id in this object.\r
- * \param currPaRAM [IN/OUT] User gets the existing PaRAM here.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_ResDesc *lChObj,\r
- EDMA3_RM_PaRAMRegs *currPaRAM)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- int paRAMId = 0u;\r
- unsigned int qdmaChId = 0u;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (hEdmaResMgr == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-\r
- if ((lChObj == NULL) || (currPaRAM == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
-\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- if (rmObj->gblCfgParams.globalRegs == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- switch (lChObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL:\r
- {\r
- if (lChObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL)\r
- {\r
- paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][lChObj->resId].paRAMId;\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL:\r
- {\r
- if (lChObj->resId < EDMA3_MAX_QDMA_CH)\r
- {\r
- qdmaChId = lChObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL;\r
- paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_PARAM_SET:\r
- {\r
- if (lChObj->resId < edma3NumPaRAMSets)\r
- {\r
- /**\r
- * User has passed the actual param set value here.\r
- * Use this value only\r
- */\r
- paRAMId = (int)(lChObj->resId);\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* Check the param id first. */\r
- if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets))\r
- {\r
- /* Get the PaRAM Set now. */\r
- edma3MemCpy ((void *)currPaRAM ,\r
- (const void *)(&(globalRegs->PARAMENTRY [paRAMId].OPT)),\r
- sizeof(EDMA3_CCRL_ParamentryRegs));\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle\r
- * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj,\r
- * unsigned int *paramPhyAddr)\r
- * \brief Get the PaRAM Set Physical Address associated with a logical channel\r
- *\r
- * This function returns the PaRAM Set Phy Address (unsigned 32 bits).\r
- * The returned address could be used by the advanced users to program the\r
- * PaRAM Set directly without using any APIs.\r
- *\r
- * Least significant 16 bits of this address could be used to program\r
- * the LINK field in the PaRAM Set.\r
- * Users which program the LINK field directly SHOULD use this API\r
- * to get the associated PaRAM Set address with the LINK channel.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param lChObj [IN] Logical Channel object for which the\r
- * PaRAM set physical address is required.\r
- * User should pass the resource type and\r
- * id in this object.\r
- * \param paramPhyAddr [IN/OUT] PaRAM Set physical address is returned\r
- * here.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_ResDesc *lChObj,\r
- unsigned int *paramPhyAddr)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- int paRAMId = 0u;\r
- unsigned int qdmaChId = 0u;\r
- volatile EDMA3_CCRL_Regs *globalRegs = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (hEdmaResMgr == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-\r
- if ((lChObj == NULL) || (paramPhyAddr == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
-\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- else\r
- {\r
- if (rmObj->gblCfgParams.globalRegs == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- switch (lChObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL:\r
- {\r
- if (lChObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL)\r
- {\r
- paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][lChObj->resId].paRAMId;\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL:\r
- {\r
- if (lChObj->resId < EDMA3_MAX_QDMA_CH)\r
- {\r
- qdmaChId = lChObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL;\r
- paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_PARAM_SET:\r
- {\r
- if (lChObj->resId < edma3NumPaRAMSets)\r
- {\r
- /**\r
- * User has passed the actual param set value here.\r
- * Use this value only\r
- */\r
- paRAMId = (int)(lChObj->resId);\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* Check the param id first. */\r
- if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets))\r
- {\r
- /* Get the PaRAM Set Address now. */\r
- *paramPhyAddr = (unsigned int)(&(globalRegs->PARAMENTRY [paRAMId].OPT));\r
- }\r
- else\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle\r
- * hEdmaResMgr, EDMA3_RM_Cntrlr_PhyAddr controllerId,\r
- * unsigned int *phyAddress)\r
- * \brief Get the Channel Controller or Transfer Controller (n) Physical\r
- * Address.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param controllerId [IN] Channel Controller or Transfer\r
- * Controller (n) for which the physical\r
- * address is required.\r
- * \param phyAddress [IN/OUT] Physical address is returned here.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_Cntrlr_PhyAddr controllerId,\r
- unsigned int *phyAddress)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((hEdmaResMgr == NULL) || (phyAddress == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
-\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- /* Verify the 'controllerId' */\r
- if ((controllerId < ((EDMA3_RM_Cntrlr_PhyAddr)(EDMA3_RM_CC_PHY_ADDR)))\r
- || (controllerId > (EDMA3_RM_Cntrlr_PhyAddr)(rmObj->gblCfgParams.numTcs)))\r
- {\r
- /* Invalid controllerId */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- if (controllerId == EDMA3_RM_CC_PHY_ADDR)\r
- {\r
- /* EDMA3 Channel Controller Address */\r
- *phyAddress = (unsigned int)(rmObj->gblCfgParams.globalRegs);\r
- }\r
- else\r
- {\r
- /**\r
- * Since the TCs enum start from 1, and TCs start from 0,\r
- * subtract 1 from the enum to get the actual address.\r
- */\r
- *phyAddress = (unsigned int)(rmObj->gblCfgParams.tcRegs[controllerId-1u]);\r
- }\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int phyCtrllerInstId,\r
- * EDMA3_RM_GblConfigParams *gblCfgParams)\r
- * \brief Get the SoC specific configuration structure for the EDMA3 Hardware.\r
- *\r
- * This API is used to fetch the global SoC specific configuration structure\r
- * for the EDMA3 Hardware. It is useful for the user who has not passed\r
- * this information during EDMA3_RM_create() and taken the default configuration\r
- * coming along with the package.\r
- *\r
- * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id\r
- * (Hardware instance id, starting from 0).\r
- * \param gblCfgParams [IN/OUT] SoC specific configuration structure for the\r
- * EDMA3 Hardware will be returned here.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_getGblConfigParams (\r
- unsigned int phyCtrllerInstId,\r
- EDMA3_RM_GblConfigParams *gblCfgParams)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES)\r
- || (NULL == gblCfgParams))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /* Return the previously saved global config information for the EDMA3 HW */\r
- edma3MemCpy((void *)(gblCfgParams),\r
- (const void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams),\r
- sizeof (EDMA3_RM_GblConfigParams));\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\fn EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr,\r
- * EDMA3_RM_InstanceInitConfig *instanceInitConfig)\r
- * \brief Get the RM Instance specific configuration structure for different\r
- * EDMA3 resources' usage (owned resources, reserved resources etc).\r
- *\r
- * This API is used to fetch the Resource Manager Instance specific configuration\r
- * structure, for a specific shadow region. It is useful for the user who has not passed\r
- * this information during EDMA3_RM_opn() and taken the default configuration\r
- * coming along with the package. EDMA3 resources, owned and reserved by this RM\r
- * instance, will be returned from this API.\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param instanceInitConfig [IN/OUT] RM Instance specific configuration\r
- * structure will be returned here.\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- *\r
- * \note This function is re-entrant.\r
- */\r
-EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (\r
- EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_InstanceInitConfig *instanceInitConfig)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- unsigned int resMgrIdx = 0u;\r
- unsigned int hwId;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((hEdmaResMgr == NULL) || (instanceInitConfig == NULL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
-\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- hwId = rmObj->phyCtrllerInstId;\r
-\r
- for (resMgrIdx = 0u; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)\r
- {\r
- if (rmInstance == ((EDMA3_RM_Instance *)(ptrRMIArray) +\r
- (hwId*EDMA3_MAX_RM_INSTANCES) +\r
- resMgrIdx))\r
- {\r
- /* RM Id found. Return the specific config info to the user. */\r
- edma3MemCpy((void *)(instanceInitConfig),\r
- (const void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) +\r
- (hwId*EDMA3_MAX_RM_INSTANCES) +\r
- resMgrIdx),\r
- sizeof (EDMA3_RM_InstanceInitConfig));\r
- break;\r
- }\r
- }\r
-\r
- if (EDMA3_MAX_RM_INSTANCES == resMgrIdx)\r
- {\r
- /* RM Id not found, report error... */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\r
- * \brief EDMA3 Resource Manager IOCTL\r
- *\r
- * This function provides IOCTL functionality for EDMA3 Resource Manager\r
- *\r
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource\r
- * Manager Instance.\r
- * \param cmd [IN] IOCTL command to be performed\r
- * \param cmdArg [IN/OUT] IOCTL command argument (if any)\r
- * \param param [IN/OUT] Device/Cmd specific argument\r
- *\r
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code\r
- */\r
-EDMA3_RM_Result EDMA3_RM_Ioctl(\r
- EDMA3_RM_Handle hEdmaResMgr,\r
- EDMA3_RM_IoctlCmd cmd,\r
- void *cmdArg,\r
- void *param\r
- )\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- unsigned int paramInitRequired = 0xFFu;\r
- unsigned int regModificationRequired = 0xFFu;\r
- unsigned int *ret_val = NULL;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (hEdmaResMgr == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-\r
- if ((cmd <= EDMA3_RM_IOCTL_MIN_IOCTL)\r
- || (cmd >= EDMA3_RM_IOCTL_MAX_IOCTL))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;\r
-\r
- if (rmInstance == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- /* To remove CCS warnings */\r
- (void)param;\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- switch (cmd)\r
- {\r
- case EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION:\r
- {\r
- paramInitRequired = (unsigned int)cmdArg;\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((paramInitRequired != 0u)\r
- && (paramInitRequired != 1u))\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /* Set/Reset the flag which is being used to do the PaRAM clearing. */\r
- rmInstance->paramInitRequired = paramInitRequired;\r
- }\r
-\r
- break;\r
- }\r
-\r
- case EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION:\r
- {\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (NULL == cmdArg)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- ret_val = (unsigned int *)cmdArg;\r
-\r
- /* Get the flag which is being used to do the PaRAM clearing. */\r
- *ret_val = rmInstance->paramInitRequired;\r
- }\r
-\r
- break;\r
- }\r
-\r
- case EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION:\r
- {\r
- regModificationRequired = (unsigned int)cmdArg;\r
-\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if ((regModificationRequired == 0u)\r
- || (regModificationRequired == 1u))\r
- {\r
- /* All other values are invalid. */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- /**\r
- * Set/Reset the flag which is being used to do the global\r
- * registers and PaRAM modification.\r
- */\r
- rmInstance->regModificationRequired = regModificationRequired;\r
- }\r
-\r
- break;\r
- }\r
-\r
- case EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION:\r
- {\r
- /* If parameter checking is enabled... */\r
-#ifndef EDMA3_RM_PARAM_CHECK_DISABLE\r
- if (NULL == cmdArg)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-#endif\r
-\r
- /* Check if the parameters are OK. */\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- ret_val = (unsigned int *)cmdArg;\r
-\r
- /**\r
- * Get the flag which is being used to do the global\r
- * registers and PaRAM modification.\r
- */\r
- *ret_val = rmInstance->regModificationRequired;\r
- }\r
-\r
- break;\r
- }\r
-\r
- default:\r
- /* Hey dude! you passed invalid IOCTL cmd */\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
-\r
- }\r
- }\r
-\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,\r
- EDMA3_DVT_dCOUNTER,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- return result;\r
-\r
- }\r
-\r
-\r
-\r
-/**\r
- * edma3ComplHandler\r
- * \brief Interrupt handler for successful transfer completion.\r
- *\r
- * \note This function first disables its own interrupt to make it non-\r
- * entrant. Later, after calling all the callback functions, it\r
- * re-enables its own interrupt.\r
- *\r
- * \return None.\r
- */\r
-static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)\r
- {\r
- unsigned int Cnt;\r
- volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;\r
- volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;\r
- volatile unsigned int pendingIrqs;\r
- unsigned int indexl;\r
- unsigned int indexh;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eINT_START,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- assert (NULL != rmObj);\r
-\r
- ptrEdmaccRegs =\r
- (volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs;\r
- if (ptrEdmaccRegs != NULL)\r
- {\r
- shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)\r
- (&ptrEdmaccRegs->SHADOW[edma3RegionId]);\r
- }\r
-\r
- Cnt = 0u;\r
- pendingIrqs = 0u;\r
- indexl = 1u;\r
- indexh = 1u;\r
-\r
- if((shadowRegs->IPR !=0 ) || (shadowRegs->IPRH !=0 ))\r
- {\r
- /**\r
- * Since an interrupt has found, we have to make sure that this\r
- * interrupt (TCC) belongs to the TCCs allocated by us only.\r
- * It might happen that someone else, who is using EDMA3 also,\r
- * is the owner of this interrupt channel i.e. the TCC.\r
- * For this, use the allocatedTCCs[], to check which all interrupt\r
- * channels are owned by the EDMA3 RM Instances.\r
- */\r
-\r
- edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION, NULL);\r
-\r
- /* Loop for EDMA3_RM_COMPL_HANDLER_RETRY_COUNT number of time,\r
- breaks when no pending interrupt is found */\r
- while ((Cnt < EDMA3_RM_COMPL_HANDLER_RETRY_COUNT)\r
- && ((indexl != 0u) || (indexh != 0u)))\r
- {\r
- indexl = 0u;\r
- pendingIrqs = shadowRegs->IPR;\r
-\r
- /**\r
- * Choose interrupts coming from our allocated TCCs\r
- * and MASK remaining ones.\r
- */\r
- pendingIrqs = (pendingIrqs & allocatedTCCs[0u]);\r
-\r
- while (pendingIrqs)\r
- {\r
- /*Process all the pending interrupts*/\r
- if((pendingIrqs & 1u) == TRUE)\r
- {\r
- /**\r
- * If the user has not given any callback function\r
- * while requesting the TCC, its TCC specific bit\r
- * in the IPR register will NOT be cleared.\r
- */\r
- if(edma3IntrParams[indexl].tccCb != NULL)\r
- {\r
- /* here write to ICR to clear the corresponding IPR bits*/\r
- shadowRegs->ICR = (1u << indexl);\r
-\r
- edma3IntrParams[indexl].tccCb (indexl,\r
- EDMA3_RM_XFER_COMPLETE,\r
- edma3IntrParams[indexl].cbData);\r
- }\r
- }\r
- ++indexl;\r
- pendingIrqs >>= 1u;\r
- }\r
-\r
- indexh = 0u;\r
- pendingIrqs = shadowRegs->IPRH;\r
-\r
- /**\r
- * Choose interrupts coming from our allocated TCCs\r
- * and MASK remaining ones.\r
- */\r
- pendingIrqs = (pendingIrqs & allocatedTCCs[1u]);\r
-\r
- while (pendingIrqs)\r
- {\r
- /*Process all the pending interrupts*/\r
- if((pendingIrqs & 1u)==TRUE)\r
- {\r
- /**\r
- * If the user has not given any callback function\r
- * while requesting the TCC, its TCC specific bit\r
- * in the IPRH register will NOT be cleared.\r
- */\r
- if(edma3IntrParams[32u+indexh].tccCb!=NULL)\r
- {\r
- /* here write to ICR to clear the corresponding IPR bits*/\r
- shadowRegs->ICRH = (1u << indexh);\r
-\r
- edma3IntrParams[32u+indexh].tccCb(32u+indexh,\r
- EDMA3_RM_XFER_COMPLETE,\r
- edma3IntrParams[32u+indexh].cbData);\r
- }\r
- }\r
- ++indexh;\r
- pendingIrqs >>= 1u;\r
- }\r
-\r
- Cnt++;\r
- }\r
-\r
- indexl = (shadowRegs->IPR & allocatedTCCs[0u]);\r
- indexh = (shadowRegs->IPRH & allocatedTCCs[1u]);\r
-\r
- if((indexl !=0 ) || (indexh !=0 ))\r
- {\r
- shadowRegs->IEVAL=0x1u;\r
- }\r
-\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION, NULL);\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eINT_END,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
- }\r
-\r
-/* ARGSUSED */\r
-void lisrEdma3ComplHandler0(unsigned int arg)\r
- {\r
- /* Invoke Completion Handler ISR */\r
- edma3ComplHandler(&resMgrObj[0]);\r
- }\r
-\r
-\r
-/**\r
- * \brief Interrupt handler for Channel Controller Error.\r
- *\r
- * \note This function first disables its own interrupt to make it non-\r
- * entrant. Later, after calling all the callback functions, it\r
- * re-enables its own interrupt.\r
- *\r
- * \return None.\r
- */\r
-static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)\r
- {\r
- unsigned int Cnt = 0u;\r
- unsigned int resMgrInstIdx = 0u;\r
- volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;\r
- volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;\r
- volatile unsigned int pendingIrqs;\r
- unsigned int index;\r
- unsigned int evtqueNum;\r
- EDMA3_RM_Instance *rm_instance = NULL;\r
- unsigned int hwId;\r
- unsigned int num_rm_instances_opened;\r
- EDMA3_RM_Instance *rmInstance = NULL;\r
- unsigned int ownedDmaError = 0;\r
- unsigned int ownedDmaHError = 0;\r
- unsigned int ownedQdmaError = 0;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_CCERR",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eINT_START,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- assert (rmObj != NULL);\r
-\r
- ptrEdmaccRegs = (volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs;\r
- if (ptrEdmaccRegs != NULL)\r
- {\r
- shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)&ptrEdmaccRegs->SHADOW[edma3RegionId];\r
- hwId = rmObj->phyCtrllerInstId;\r
- rmInstance = ((EDMA3_RM_Instance *)(ptrRMIArray)\r
- + ((rmObj->phyCtrllerInstId)*EDMA3_MAX_RM_INSTANCES)\r
- + edma3RegionId);\r
-\r
- pendingIrqs = 0u;\r
- index = 1u;\r
-\r
- if(((ptrEdmaccRegs->EMR != 0 )\r
- || (ptrEdmaccRegs->EMRH != 0 ))\r
- || ((ptrEdmaccRegs->QEMR != 0)\r
- || (ptrEdmaccRegs->CCERR != 0)))\r
- {\r
- edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, NULL);\r
-\r
- /* Loop for EDMA3_RM_CCERR_HANDLER_RETRY_COUNT number of time,\r
- breaks when no pending interrupt is found */\r
- while ((Cnt < EDMA3_RM_CCERR_HANDLER_RETRY_COUNT)\r
- && (index != 0u))\r
- {\r
- index = 0u;\r
- pendingIrqs = ptrEdmaccRegs->EMR;\r
-\r
- while (pendingIrqs)\r
- {\r
- /*Process all the pending interrupts*/\r
- if((pendingIrqs & 1u)==TRUE)\r
- {\r
- unsigned int mappedTcc = 0u;\r
-\r
- /**\r
- * Using the 'index' value (basically the DMA\r
- * channel), fetch the corresponding TCC\r
- * value, mapped to this DMA channel.\r
- */\r
- mappedTcc = edma3DmaChTccMapping[index];\r
-\r
- /**\r
- * Ensure that the mapped tcc is valid and the call\r
- * back is not NULL\r
- */\r
- if (mappedTcc < EDMA3_MAX_TCC)\r
- {\r
- /**\r
- * TCC owned and allocated by RM.\r
- * Write to EMCR to clear the corresponding EMR bits.\r
- */\r
- ptrEdmaccRegs->EMCR = (1u<<index);\r
- /*Clear any SER*/\r
- shadowRegs->SECR = (1u<<index);\r
-\r
- /* Call the callback function if registered earlier. */\r
- if((edma3IntrParams[mappedTcc].tccCb) != NULL)\r
- {\r
- edma3IntrParams[mappedTcc].tccCb (\r
- mappedTcc,\r
- EDMA3_RM_E_CC_DMA_EVT_MISS,\r
- edma3IntrParams[mappedTcc].cbData\r
- );\r
- }\r
- }\r
- else\r
- {\r
- /**\r
- * DMA channel not owned by the RM instance.\r
- * Check the global error interrupt clearing option.\r
- * If it is TRUE, clear the error interupt else leave\r
- * it like that.\r
- */\r
-#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)\r
- /* here write to EMCR to clear the corresponding EMR bits. */\r
- ptrEdmaccRegs->EMCR = (1u<<index);\r
- /*Clear any SER*/\r
- ptrEdmaccRegs->SECR = (1u<<index);\r
-#endif\r
- }\r
- }\r
- ++index;\r
- pendingIrqs >>= 1u;\r
- }\r
-\r
- index = 0u;\r
- pendingIrqs = ptrEdmaccRegs->EMRH;\r
- while (pendingIrqs)\r
- {\r
- /*Process all the pending interrupts*/\r
- if((pendingIrqs & 1u)==TRUE)\r
- {\r
- unsigned int mappedTcc = 0u;\r
-\r
- /**\r
- * Using the 'index' value (basically the DMA\r
- * channel), fetch the corresponding TCC\r
- * value, mapped to this DMA channel.\r
- */\r
- mappedTcc = edma3DmaChTccMapping[32u+index];\r
-\r
- /**\r
- * Ensure that the mapped tcc is valid and the call\r
- * back is not NULL\r
- */\r
- if (mappedTcc < EDMA3_MAX_TCC)\r
- {\r
- /**\r
- * TCC owned and allocated by RM.\r
- * Write to EMCR to clear the corresponding EMR bits.\r
- */\r
- ptrEdmaccRegs->EMCRH = (1u<<index);\r
- /*Clear any SERH*/\r
- shadowRegs->SECRH = (1u<<index);\r
-\r
- /* Call the callback function if registered earlier. */\r
- if((edma3IntrParams[mappedTcc].tccCb) != NULL)\r
- {\r
- edma3IntrParams[mappedTcc].tccCb (\r
- mappedTcc,\r
- EDMA3_RM_E_CC_DMA_EVT_MISS,\r
- edma3IntrParams[mappedTcc].cbData\r
- );\r
- }\r
- }\r
- else\r
- {\r
- /**\r
- * DMA channel not owned by the RM instance.\r
- * Check the global error interrupt clearing option.\r
- * If it is TRUE, clear the error interupt else leave\r
- * it like that.\r
- */\r
-#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)\r
- /**\r
- * TCC NOT owned by RM.\r
- * Write to EMCRH to clear the corresponding EMRH bits.\r
- */\r
- ptrEdmaccRegs->EMCRH = (1u<<index);\r
- /*Clear any SERH*/\r
- shadowRegs->SECRH = (1u<<index);\r
-#endif\r
- }\r
- }\r
- ++index;\r
- pendingIrqs >>= 1u;\r
- }\r
-\r
- index = 0u;\r
- pendingIrqs = ptrEdmaccRegs->QEMR;\r
- while (pendingIrqs)\r
- {\r
- /*Process all the pending interrupts*/\r
- if((pendingIrqs & 1u)==TRUE)\r
- {\r
- unsigned int mappedTcc = 0u;\r
-\r
- /**\r
- * Using the 'index' value (basically the QDMA\r
- * channel), fetch the corresponding TCC\r
- * value, mapped to this QDMA channel.\r
- */\r
- mappedTcc = edma3QdmaChTccMapping[index];\r
-\r
- if (mappedTcc < EDMA3_MAX_TCC)\r
- {\r
- /* here write to QEMCR to clear the corresponding QEMR bits*/\r
- ptrEdmaccRegs->QEMCR = (1u<<index);\r
- /*Clear any QSER*/\r
- shadowRegs->QSECR = (1u<<index);\r
-\r
- if((edma3IntrParams[mappedTcc].tccCb) != NULL)\r
- {\r
- edma3IntrParams[mappedTcc].tccCb (\r
- mappedTcc,\r
- EDMA3_RM_E_CC_QDMA_EVT_MISS,\r
- edma3IntrParams[mappedTcc].cbData\r
- );\r
- }\r
- }\r
- else\r
- {\r
- /**\r
- * QDMA channel not owned by the RM instance.\r
- * Check the global error interrupt clearing option.\r
- * If it is TRUE, clear the error interupt else leave\r
- * the ISR.\r
- */\r
-#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)\r
- /* here write to QEMCR to clear the corresponding QEMR bits*/\r
- ptrEdmaccRegs->QEMCR = (1u<<index);\r
-\r
- /*Clear any QSER*/\r
- ptrEdmaccRegs->QSECR = (1u<<index);\r
-#endif\r
- }\r
- }\r
- ++index;\r
- pendingIrqs >>= 1u;\r
- }\r
-\r
- index = 0u;\r
- pendingIrqs = ptrEdmaccRegs->CCERR;\r
- if (pendingIrqs!=NULL)\r
- {\r
- /* Process all the pending CC error interrupts. */\r
-\r
- /* Queue threshold error for different event queues.*/\r
- for (evtqueNum = 0u; evtqueNum < rmObj->gblCfgParams.numEvtQueue; evtqueNum++)\r
- {\r
- if((pendingIrqs & (1u << evtqueNum)) != NULL)\r
- {\r
- /**\r
- * Queue threshold error for queue 'evtqueNum' raised.\r
- * Inform all the RM instances working on this region\r
- * about the error by calling their global callback functions.\r
- */\r
- num_rm_instances_opened = resMgrObj[hwId].numOpens;\r
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)\r
- {\r
- /* Check whether the RM instance opened working on this region */\r
- rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);\r
- if (NULL != rm_instance)\r
- {\r
- if (rm_instance->initParam.regionId == edma3RegionId)\r
- {\r
- /* Region id matches, call the callback function */\r
- if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)\r
- {\r
- rm_instance->initParam.gblerrCbParams.gblerrCb(\r
- EDMA3_RM_E_CC_QUE_THRES_EXCEED,\r
- evtqueNum,\r
- rm_instance->initParam.gblerrCbParams.gblerrData);\r
- }\r
- }\r
- }\r
-\r
- /* Check next opened instance */\r
- num_rm_instances_opened--;\r
- }\r
-\r
- /* Clear the error interrupt. */\r
- ptrEdmaccRegs->CCERRCLR = (1u << evtqueNum);\r
- }\r
- }\r
-\r
-\r
- /* Transfer completion code error. */\r
- if ((pendingIrqs & (1 << EDMA3_CCRL_CCERR_TCCERR_SHIFT))!=NULL)\r
- {\r
- /**\r
- * Transfer completion code error raised.\r
- * Inform all the RM instances working on this region\r
- * about the error by calling their global callback functions.\r
- */\r
- num_rm_instances_opened = resMgrObj[hwId].numOpens;\r
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)\r
- {\r
- /* Check whether the RM instance opened working on this region */\r
- rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);\r
- if (NULL != rm_instance)\r
- {\r
- if (rm_instance->initParam.regionId == edma3RegionId)\r
- {\r
- /* Region id matches, call the callback function */\r
- if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)\r
- {\r
- rm_instance->initParam.gblerrCbParams.gblerrCb(\r
- EDMA3_RM_E_CC_TCC,\r
- NULL,\r
- rm_instance->initParam.gblerrCbParams.gblerrData);\r
- }\r
- }\r
- }\r
-\r
- /* Check next opened instance */\r
- num_rm_instances_opened--;\r
- }\r
-\r
- ptrEdmaccRegs->CCERRCLR = (1<<EDMA3_CCRL_CCERR_TCCERR_SHIFT);\r
- }\r
-\r
- ++index;\r
- }\r
-\r
- Cnt++;\r
- }\r
-\r
-\r
- /**\r
- * Read the error registers again. If any interrupt is pending,\r
- * write the EEVAL register.\r
- * Moreover, according to the global error interrupt clearing\r
- * option, check either error bits associated with all the\r
- * DMA/QDMA channels (option is SET) OR check error bits\r
- * associated with owned DMA/QDMA channels.\r
- */\r
-#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)\r
- /* To remove warning. */\r
- rmInstance = rmInstance;\r
-\r
- /* Check all the error bits. */\r
- ownedDmaError = ptrEdmaccRegs->EMR;\r
- ownedDmaHError = ptrEdmaccRegs->EMRH;\r
- ownedQdmaError = ptrEdmaccRegs->QEMR;\r
-#else\r
- /* Check ONLY owned error bits. */\r
- ownedDmaError = (ptrEdmaccRegs->EMR & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0u]);\r
- ownedDmaHError = (ptrEdmaccRegs->EMRH & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1u]);\r
- ownedQdmaError = (ptrEdmaccRegs->QEMR & rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u]);\r
-#endif\r
-\r
- if (((ownedDmaError != 0 ) || (ownedDmaHError != 0 ))\r
- || ((ownedQdmaError != 0) || (ptrEdmaccRegs->CCERR != 0)))\r
- {\r
- ptrEdmaccRegs->EEVAL=0x1u;\r
- }\r
-\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, NULL);\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_CCERR",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eINT_END,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
- }\r
-\r
-/* ARGSUSED */\r
-void lisrEdma3CCErrHandler0(unsigned int arg)\r
- {\r
- /* Invoke CC Error Handler ISR */\r
- edma3CCErrHandler(&resMgrObj[0]);\r
- }\r
-\r
-\r
-\r
-/**\r
- * \brief Interrupt handler for Transfer Controller Error.\r
- *\r
- * \note This function first disables its own interrupt to make it non-\r
- * entrant. Later, after calling all the callback functions, it\r
- * re-enables its own interrupt.\r
- *\r
- * \return None.\r
- */\r
-static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)\r
- {\r
- volatile EDMA3_TCRL_Regs *tcRegs = NULL;\r
- unsigned int tcMemErrRdWr = 0u;\r
- unsigned int resMgrInstIdx = 0u;\r
- EDMA3_RM_Instance *rm_instance = NULL;\r
- unsigned int hwId;\r
- unsigned int num_rm_instances_opened;\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_TCERR",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eINT_START,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
-\r
- assert ((rmObj != NULL) && (tcNum < rmObj->gblCfgParams.numTcs));\r
-\r
- if (rmObj->gblCfgParams.tcRegs[tcNum] != NULL)\r
- {\r
- tcRegs = (volatile EDMA3_TCRL_Regs *)(rmObj->gblCfgParams.tcRegs[tcNum]);\r
- hwId = rmObj->phyCtrllerInstId;\r
- }\r
-\r
- if (tcRegs != NULL)\r
- {\r
- if(tcRegs->ERRSTAT != 0)\r
- {\r
- edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, &tcNum);\r
-\r
- if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT))!=NULL)\r
- {\r
- /* Bus error event. */\r
- /**\r
- * EDMA3TC has detected an error at source or destination\r
- * address. Error information can be read from the error\r
- * details register (ERRDET).\r
- */\r
- tcMemErrRdWr = tcRegs->ERRDET & (EDMA3_TCRL_ERRDET_STAT_MASK);\r
- if ((tcMemErrRdWr > 0u) && (tcMemErrRdWr < 8u))\r
- {\r
- /**\r
- * Inform all the RM instances working on this region\r
- * about the error by calling their global callback functions.\r
- */\r
- num_rm_instances_opened = resMgrObj[hwId].numOpens;\r
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)\r
- {\r
- /* Check whether the RM instance opened working on this region */\r
- rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);\r
- if (NULL != rm_instance)\r
- {\r
- if (rm_instance->initParam.regionId == edma3RegionId)\r
- {\r
- /* Region id matches, call the callback function */\r
- if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)\r
- {\r
- rm_instance->initParam.gblerrCbParams.gblerrCb(\r
- EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR,\r
- tcNum,\r
- rm_instance->initParam.gblerrCbParams.gblerrData);\r
- }\r
- }\r
- }\r
-\r
- /* Check next opened instance */\r
- num_rm_instances_opened--;\r
- }\r
- }\r
- else\r
- {\r
- if ((tcMemErrRdWr >= 8u) && (tcMemErrRdWr <= 0xFu))\r
- {\r
- /**\r
- * Inform all the RM instances working on this region\r
- * about the error by calling their global callback functions.\r
- */\r
- num_rm_instances_opened = resMgrObj[hwId].numOpens;\r
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)\r
- {\r
- /* Check whether the RM instance opened working on this region */\r
- rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);\r
- if (NULL != rm_instance)\r
- {\r
- if (rm_instance->initParam.regionId == edma3RegionId)\r
- {\r
- /* Region id matches, call the callback function */\r
- if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)\r
- {\r
- rm_instance->initParam.gblerrCbParams.gblerrCb(\r
- EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR,\r
- tcNum,\r
- rm_instance->initParam.gblerrCbParams.gblerrData);\r
- }\r
- }\r
- }\r
-\r
- /* Check next opened instance */\r
- num_rm_instances_opened--;\r
- }\r
- }\r
- }\r
- tcRegs->ERRCLR = (1<<EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT);\r
- }\r
- else\r
- {\r
- /* Transfer request (TR) error event. */\r
- if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_TRERR_SHIFT))!=NULL)\r
- {\r
- num_rm_instances_opened = resMgrObj[hwId].numOpens;\r
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)\r
- {\r
- /* Check whether the RM instance opened working on this region */\r
- rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);\r
- if (NULL != rm_instance)\r
- {\r
- if (rm_instance->initParam.regionId == edma3RegionId)\r
- {\r
- /* Region id matches, call the callback function */\r
- if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)\r
- {\r
- rm_instance->initParam.gblerrCbParams.gblerrCb(\r
- EDMA3_RM_E_TC_TR_ERROR,\r
- tcNum,\r
- rm_instance->initParam.gblerrCbParams.gblerrData);\r
- }\r
- }\r
- }\r
-\r
- /* Check next opened instance */\r
- num_rm_instances_opened--;\r
- }\r
-\r
- tcRegs->ERRCLR = (1<<EDMA3_TCRL_ERRSTAT_TRERR_SHIFT);\r
- }\r
- else\r
- {\r
- if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT))!=NULL)\r
- {\r
- num_rm_instances_opened = resMgrObj[hwId].numOpens;\r
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)\r
- {\r
- /* Check whether the RM instance opened working on this region */\r
- rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);\r
- if (NULL != rm_instance)\r
- {\r
- if (rm_instance->initParam.regionId == edma3RegionId)\r
- {\r
- /* Region id matches, call the callback function */\r
- if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)\r
- {\r
- rm_instance->initParam.gblerrCbParams.gblerrCb(\r
- EDMA3_RM_E_TC_INVALID_ADDR,\r
- tcNum,\r
- rm_instance->initParam.gblerrCbParams.gblerrData);\r
- }\r
- }\r
- }\r
-\r
- /* Check next opened instance */\r
- num_rm_instances_opened--;\r
- }\r
-\r
- tcRegs->ERRCLR = (1<<EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT);\r
- }\r
- }\r
- }\r
-\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, tcNum);\r
- }\r
- }\r
-\r
-#ifdef EDMA3_INSTRUMENTATION_ENABLED\r
- EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_TCERR",\r
- EDMA3_DVT_DESC(EDMA3_DVT_eINT_END,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE,\r
- EDMA3_DVT_dNONE));\r
-#endif /* EDMA3_INSTRUMENTATION_ENABLED */\r
- }\r
-\r
-\r
-\r
-/*\r
- * ======== lisrEdma3TC0ErrHandler0 ========\r
- * EDMA3 instance 0 TC0 Error Interrupt Service Routine\r
- */\r
-/* ARGSUSED */\r
-void lisrEdma3TC0ErrHandler0(unsigned int arg)\r
- {\r
- /* Invoke Error Handler ISR for TC0*/\r
- edma3TCErrHandler(&resMgrObj[0u], 0u);\r
- }\r
-\r
-\r
-/*\r
- * ======== lisrEdma3TC1ErrHandler0 ========\r
- * EDMA3 instance 0 TC1 Error Interrupt Service Routine\r
- */\r
-/* ARGSUSED */\r
-void lisrEdma3TC1ErrHandler0(unsigned int arg)\r
- {\r
- /* Invoke Error Handler ISR for TC1*/\r
- edma3TCErrHandler(&resMgrObj[0u], 1u);\r
- }\r
-\r
-/*\r
- * ======== lisrEdma3TC2ErrHandler0 ========\r
- * EDMA3 instance 0 TC2 Error Interrupt Service Routine\r
- */\r
-/* ARGSUSED */\r
-void lisrEdma3TC2ErrHandler0(unsigned int arg)\r
- {\r
- /* Invoke Error Handler ISR for TC2*/\r
- edma3TCErrHandler(&resMgrObj[0u], 2u);\r
- }\r
-\r
-/*\r
- * ======== lisrEdma3TC3ErrHandler0 ========\r
- * EDMA3 instance 0 TC3 Error Interrupt Service Routine\r
- */\r
-/* ARGSUSED */\r
-void lisrEdma3TC3ErrHandler0(unsigned int arg)\r
- {\r
- /* Invoke Error Handler ISR for TC3*/\r
- edma3TCErrHandler(&resMgrObj[0u], 3u);\r
- }\r
-\r
-/*\r
- * ======== lisrEdma3TC4ErrHandler0 ========\r
- * EDMA3 instance 0 TC4 Error Interrupt Service Routine\r
- */\r
-/* ARGSUSED */\r
-void lisrEdma3TC4ErrHandler0(unsigned int arg)\r
- {\r
- /* Invoke Error Handler ISR for TC4*/\r
- edma3TCErrHandler(&resMgrObj[0u], 4u);\r
- }\r
-\r
-\r
-/*\r
- * ======== lisrEdma3TC5ErrHandler0 ========\r
- * EDMA3 instance 0 TC5 Error Interrupt Service Routine\r
- */\r
-/* ARGSUSED */\r
-void lisrEdma3TC5ErrHandler0(unsigned int arg)\r
- {\r
- /* Invoke Error Handler ISR for TC5*/\r
- edma3TCErrHandler(&resMgrObj[0u], 5u);\r
- }\r
-\r
-/*\r
- * ======== lisrEdma3TC6ErrHandler0 ========\r
- * EDMA3 instance 0 TC6 Error Interrupt Service Routine\r
- */\r
-/* ARGSUSED */\r
-void lisrEdma3TC6ErrHandler0(unsigned int arg)\r
- {\r
- /* Invoke Error Handler ISR for TC6*/\r
- edma3TCErrHandler(&resMgrObj[0u], 6u);\r
- }\r
-\r
-/*\r
- * ======== lisrEdma3TC7ErrHandler0 ========\r
- * EDMA3 instance 0 TC7 Error Interrupt Service Routine\r
- */\r
-/* ARGSUSED */\r
-void lisrEdma3TC7ErrHandler0(unsigned int arg)\r
- {\r
- /* Invoke Error Handler ISR for TC7*/\r
- edma3TCErrHandler(&resMgrObj[0u], 7u);\r
- }\r
-\r
-\r
-\r
-/* Resource Manager Internal functions - Start */\r
-\r
-/** Initialization of the Global region registers of the EDMA3 Controller */\r
-static void edma3GlobalRegionInit (unsigned int phyCtrllerInstId)\r
- {\r
- unsigned int evtQNum = 0u;\r
- volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;\r
-\r
- assert (phyCtrllerInstId < EDMA3_MAX_EDMA3_INSTANCES);\r
-\r
- ptrEdmaccRegs = (volatile EDMA3_CCRL_Regs *)\r
- (resMgrObj[phyCtrllerInstId].gblCfgParams.globalRegs);\r
-\r
- if (ptrEdmaccRegs != NULL)\r
- {\r
- ptrEdmaccRegs->EMCR = EDMA3_RM_SET_ALL_BITS;\r
- ptrEdmaccRegs->EMCRH = EDMA3_RM_SET_ALL_BITS;\r
- ptrEdmaccRegs->QEMCR = EDMA3_RM_SET_ALL_BITS;\r
-\r
- /*\r
- * Set all Instance-wide EDMA3 parameters (not channel-specific)\r
- */\r
-\r
- /**\r
- * Set TC Priority among system-wide bus-masters and Queue\r
- * Watermark Level\r
- */\r
- while (evtQNum <\r
- resMgrObj[phyCtrllerInstId].gblCfgParams.numEvtQueue)\r
- {\r
- ptrEdmaccRegs->QUEPRI &= EDMA3_RM_QUEPRI_CLR_MASK(evtQNum);\r
- ptrEdmaccRegs->QUEPRI |= EDMA3_RM_QUEPRI_SET_MASK(evtQNum,\r
- resMgrObj[phyCtrllerInstId].gblCfgParams.evtQPri[evtQNum]);\r
-\r
- ptrEdmaccRegs->QWMTHRA |= EDMA3_RM_QUEWMTHR_SET_MASK(evtQNum,\r
- resMgrObj[phyCtrllerInstId].gblCfgParams.evtQueueWaterMarkLvl[evtQNum]);\r
-\r
- evtQNum++;\r
- }\r
-\r
- /* Clear CCERR register */\r
- ptrEdmaccRegs ->CCERRCLR = 0xFFFFu;\r
- }\r
-\r
- return;\r
- }\r
-\r
-\r
-\r
-\r
-/** Initialization of the Shadow region registers of the EDMA3 Controller */\r
-static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance)\r
- {\r
- unsigned int intState = 0u;\r
- volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;\r
- volatile EDMA3_CCRL_ShadowRegs *ptrEdmaShadowRegs = NULL;\r
- unsigned int phyCtrllerInstId;\r
- unsigned int regionId;\r
- const EDMA3_RM_InstanceInitConfig *rmInstInitConfig = pRMInstance->initParam.rmInstInitConfig;\r
-\r
- assert (pRMInstance != NULL);\r
-\r
- if (rmInstInitConfig != NULL)\r
- {\r
- phyCtrllerInstId = pRMInstance->pResMgrObjHandle->phyCtrllerInstId;\r
- regionId = pRMInstance->initParam.regionId;\r
-\r
- ptrEdmaccRegs = (volatile EDMA3_CCRL_Regs *)\r
- (resMgrObj[phyCtrllerInstId].gblCfgParams.globalRegs);\r
-\r
- if (ptrEdmaccRegs != NULL)\r
- {\r
- ptrEdmaShadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)\r
- (&ptrEdmaccRegs->SHADOW[regionId]);\r
-\r
- ptrEdmaShadowRegs->ECR = (rmInstInitConfig->ownDmaChannels[0u]\r
- | rmInstInitConfig->ownTccs[0u]);\r
- ptrEdmaShadowRegs->ECRH = (rmInstInitConfig->ownDmaChannels[1u]\r
- | rmInstInitConfig->ownTccs[1u]);\r
- ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0u]\r
- | rmInstInitConfig->ownTccs[0u]);\r
- ptrEdmaShadowRegs->SECR = (rmInstInitConfig->ownDmaChannels[0u]\r
- | rmInstInitConfig->ownTccs[0u]);\r
- ptrEdmaShadowRegs->SECRH = (rmInstInitConfig->ownDmaChannels[1u]\r
- | rmInstInitConfig->ownTccs[1u]);\r
- ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0u]\r
- | rmInstInitConfig->ownTccs[0u]);\r
- ptrEdmaShadowRegs->EECRH = (rmInstInitConfig->ownDmaChannels[1u]\r
- | rmInstInitConfig->ownTccs[1u]);\r
-\r
- ptrEdmaShadowRegs->QEECR = rmInstInitConfig->ownQdmaChannels[0u];\r
-\r
- ptrEdmaShadowRegs->IECR = (rmInstInitConfig->ownDmaChannels[0u]\r
- | rmInstInitConfig->ownTccs[0u]);\r
- ptrEdmaShadowRegs->IECRH = (rmInstInitConfig->ownDmaChannels[1u]\r
- | rmInstInitConfig->ownTccs[1u]);\r
- ptrEdmaShadowRegs->ICR = (rmInstInitConfig->ownDmaChannels[0u]\r
- | rmInstInitConfig->ownTccs[0u]);\r
- ptrEdmaShadowRegs->ICRH = (rmInstInitConfig->ownDmaChannels[1u]\r
- | rmInstInitConfig->ownTccs[1u]);\r
-\r
- ptrEdmaShadowRegs->QSECR = rmInstInitConfig->ownQdmaChannels[0u];\r
-\r
- /*\r
- * Set all EDMA3 Resource<->Region mapping parameters\r
- */\r
-\r
- /* 1. Dma Channel (and TCC) <-> Region */\r
-#ifdef EDMA3_RM_DEBUG\r
- EDMA3_RM_PRINTF("DRAE=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAE);\r
- EDMA3_RM_PRINTF("DRAEH=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAEH);\r
-#endif\r
-\r
- edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);\r
- ptrEdmaccRegs->DRA[regionId].DRAE = 0u;\r
- ptrEdmaccRegs->DRA[regionId].DRAEH = 0u;\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);\r
-\r
-#ifdef EDMA3_RM_DEBUG\r
- EDMA3_RM_PRINTF("DRAE=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAE);\r
- EDMA3_RM_PRINTF("DRAEH=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAEH);\r
-#endif\r
-\r
- /* 2. Qdma Channel <-> Region */\r
-#ifdef EDMA3_RM_DEBUG\r
- EDMA3_RM_PRINTF("QRAE=%x\r\n",ptrEdmaccRegs->QRAE[regionId]);\r
-#endif\r
-\r
- edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);\r
- ptrEdmaccRegs->QRAE[regionId] = 0u;\r
- edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);\r
-\r
-#ifdef EDMA3_RM_DEBUG\r
- EDMA3_RM_PRINTF("QRAE=%x\r\n",ptrEdmaccRegs->QRAE[regionId]);\r
-#endif\r
-\r
- }\r
- }\r
-\r
- return;\r
- }\r
-\r
-\r
-\r
-/** Local MemSet function */\r
-void edma3MemSet(void *dst, unsigned char data, unsigned int len)\r
- {\r
- unsigned int i=0u;\r
- unsigned char *ds=NULL;\r
-\r
- assert (dst != NULL);\r
-\r
- ds = (unsigned char *)dst;\r
-\r
- for( i=0;i<len;i++)\r
- {\r
- *ds=data;\r
- ds++;\r
- }\r
-\r
- return;\r
- }\r
-\r
-\r
-/* Local MemCopy function */\r
-void edma3MemCpy(void *dst, const void *src, unsigned int len)\r
- {\r
- unsigned int i=0u;\r
- const unsigned char *sr;\r
- unsigned char *ds;\r
-\r
- assert ((src != NULL) && (dst != NULL));\r
-\r
- sr = (const unsigned char *)src;\r
- ds = (unsigned char *)dst;\r
-\r
- for( i=0;i<len;i++)\r
- {\r
- *ds=*sr;\r
- ds++;\r
- sr++;\r
- }\r
-\r
- return;\r
- }\r
-\r
-\r
-/**\r
- * Finds a particular bit ('0' or '1') in the particular word from 'start'.\r
- * If found, returns the position, else return -1.\r
- */\r
-static int findBitInWord (int source, unsigned int start, unsigned short bit)\r
- {\r
- unsigned int position = start;\r
- unsigned short found = 0;\r
- unsigned int iterations_left = 0;\r
-\r
- switch (bit)\r
- {\r
- case 1:\r
- {\r
- source >>= (start%32u);\r
-\r
- while ((found==0u) && (source!=0))\r
- {\r
- if ((source & 0x1) == 0x1)\r
- {\r
- /* 1 */\r
- found++;\r
- }\r
- else\r
- {\r
- /* 0 */\r
- source >>= 1;\r
- position++;\r
- }\r
- }\r
-\r
- }\r
- break;\r
-\r
- case 0:\r
- {\r
- source >>= (start%32u);\r
- iterations_left = 32u - (start%32u);\r
-\r
- while ((found==0u) && (iterations_left>0u))\r
- {\r
- if ((source & 0x1) == 0x1)\r
- {\r
- /* 1 */\r
- source >>= 1;\r
- position++;\r
- iterations_left--;\r
- }\r
- else\r
- {\r
- /* 0 */\r
- found++;\r
- }\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- return (found ? (int)position : -1);\r
- }\r
-\r
-\r
-/**\r
- * Finds a particular bit ('0' or '1') in the specified resources' array\r
- * from 'start' to 'end'. If found, returns the position, else return -1.\r
- */\r
-static int findBit (EDMA3_RM_ResType resType,\r
- unsigned int start,\r
- unsigned int end,\r
- unsigned short bit)\r
- {\r
- int position = -1;\r
- unsigned int start_index = start / 32u;\r
- unsigned int end_index = end / 32u;\r
- int i;\r
- unsigned int *resPtr = 0x0;\r
- int ret = -1;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
-\r
- assert (start <= end);\r
-\r
- /**\r
- * job is to find 'bit' in an array[start_index:end_index]\r
- * algo used:\r
- * first search in array[start_index]\r
- * then search in array[start_index + 1 : end_index - 1]\r
- * then search in array[end_index]\r
- */\r
- switch (resType)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL:\r
- resPtr = &contiguousDmaRes[0];\r
- break;\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL:\r
- resPtr = &contiguousQdmaRes[0];\r
- break;\r
-\r
- case EDMA3_RM_RES_TCC:\r
- resPtr = &contiguousTccRes[0];\r
- break;\r
-\r
- case EDMA3_RM_RES_PARAM_SET:\r
- resPtr = &contiguousParamRes[0];\r
- break;\r
-\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- break;\r
- }\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- switch (bit)\r
- {\r
- case 1:\r
- {\r
- /* Find '1' in first word. */\r
- position = findBitInWord (resPtr[start_index], start, 1u);\r
-\r
- if (position != -1)\r
- {\r
- ret = position;\r
- }\r
- else\r
- {\r
- /* '1' NOT found, look into other words. */\r
- for (i = (int)(start_index + 1u); i <= (int)(end_index - 1u); i++)\r
- {\r
- position = findBitInWord (resPtr[i], 0u, 1u);\r
- if (position != -1)\r
- {\r
- /* '1' Found... */\r
- ret = (position + (i*32));\r
- break;\r
- }\r
- }\r
-\r
- /* First check whether we have found '1' or not. */\r
- if (ret == -1)\r
- {\r
- /* Still not found, look in the last word. */\r
- position = findBitInWord(resPtr[end_index], 0u, 1u);\r
- if (position != -1)\r
- {\r
- /* Finally got it. */\r
- ret = (position + (end_index*32u));\r
- }\r
- else\r
- {\r
- /* Sorry, could not find it, return -1. */\r
- ret = -1;\r
- }\r
- }\r
- }\r
- }\r
- break;\r
-\r
- case 0:\r
- {\r
- /* Find '0' in first word. */\r
- position = findBitInWord(resPtr[start_index], start, 0u);\r
- if (position != -1)\r
- {\r
- ret = position;\r
- }\r
- else\r
- {\r
- /* '0' NOT found, look into other words. */\r
- for (i = (start_index + 1u); i <= (end_index - 1u); i++)\r
- {\r
- position = findBitInWord(resPtr[i], 0u, 0u);\r
- if (position != -1)\r
- {\r
- /* '0' found... */\r
- ret = (position + (i*32));\r
- break;\r
- }\r
- }\r
-\r
- /* First check whether we have found '0' or not. */\r
- if (ret == -1)\r
- {\r
- position = findBitInWord(resPtr[end_index], 0u, 0u);\r
- if (position != -1)\r
- {\r
- /* Finally got it. */\r
- ret = (position + (end_index*32u));\r
- }\r
- else\r
- {\r
- /* Sorry, could not find it, return -1. */\r
- ret = -1;\r
- }\r
- }\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- }\r
-\r
-\r
-\r
- return ((ret >= start) ? ret : -1);\r
-}\r
-\r
-\r
-\r
-/**\r
- * If successful, this function returns EDMA3_RM_SOK and the position\r
- * of first available resource in 'positionRes'. Else returns error.\r
- */\r
-static EDMA3_RM_Result allocAnyContigRes(EDMA3_RM_ResType resType,\r
- unsigned int numResources,\r
- unsigned int *positionRes)\r
- {\r
- unsigned short found = 0u;\r
- int first_one, next_zero;\r
- unsigned int num_available;\r
- int ret = -1;\r
- unsigned int start = 0;\r
- unsigned int end;\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
-\r
- assert (positionRes != NULL);\r
-\r
- switch (resType)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL:\r
- end = EDMA3_MAX_DMA_CH - 1u;\r
- break;\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL:\r
- end = EDMA3_MAX_QDMA_CH - 1u;\r
- break;\r
-\r
- case EDMA3_RM_RES_TCC:\r
- end = EDMA3_MAX_TCC - 1u;\r
- break;\r
-\r
- case EDMA3_RM_RES_PARAM_SET:\r
- end = edma3NumPaRAMSets - 1u;\r
- break;\r
-\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- break;\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- /**\r
- * Algorithm used for finding N contiguous resources.\r
- * In the resources' array, '1' means available and '0' means\r
- * not-available.\r
- * Step a) Find first '1' starting from 'start'. If successful,\r
- * store it in first_one, else return error.\r
- * Step b) Find first '0' starting from (first_one+1) to 'end'.\r
- * If successful, store returned value in next_zero. If '0' could\r
- * not be located, it means all the resources are available.\r
- * Store 'end' (i.e. the last resource id) in next_zero.\r
- * Step c) Count the number of contiguous resources available\r
- * by subtracting first_one from next_zero.\r
- * Step d) If result < N, do the whole process again untill you\r
- * reach end. Else you have found enough resources, return success.\r
- */\r
- while((found == 0) && (((end-start)+1u) >= numResources))\r
- {\r
- /* Find first '1' starting from 'start' till 'end'. */\r
- first_one = findBit (resType, start, end, 1u);\r
- if (first_one != -1)\r
- {\r
- /* Got first 1, search for first '0' now. */\r
- next_zero = findBit (resType, first_one+1, end, 0u);\r
- if (next_zero == -1)\r
- {\r
- /* Unable to find next zero, all 1' are there */\r
- next_zero = end + 1u;\r
- }\r
-\r
- /* check no of resources available */\r
- num_available = next_zero - first_one;\r
- if (num_available >= numResources)\r
- {\r
- /* hurrah..., we have found enough resources. */\r
- found = 1u;\r
- ret = first_one;\r
- }\r
- else\r
- {\r
- /* Not enough resources, try again */\r
- start = next_zero + 1;\r
- }\r
- }\r
- else\r
- {\r
- /* do nothing, first 1 is not there, return. */\r
- break;\r
- }\r
- }\r
- }\r
-\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- if (found == 1u)\r
- {\r
- /* required resources found, retrun the first available res id. */\r
- *positionRes = (unsigned int)ret;\r
- }\r
- else\r
- {\r
- /* No resources allocated */\r
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;\r
- }\r
- }\r
-\r
- return result;\r
- }\r
-\r
-\r
-\r
-/**\r
- * Starting from 'firstResIdObj', this function makes the next 'numResources'\r
- * Resources non-available for future. Also, it does some global resisters'\r
- * setting also.\r
- */\r
-static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,\r
- const EDMA3_RM_ResDesc *firstResIdObj,\r
- unsigned int numResources)\r
- {\r
- EDMA3_RM_Result result = EDMA3_RM_SOK;\r
- volatile EDMA3_CCRL_Regs *gblRegs = NULL;\r
- EDMA3_RM_Obj *rmObj = NULL;\r
- unsigned int avlblIdx = 0u;\r
- unsigned int firstResId=0u;\r
- unsigned int lastResId=0u;\r
-\r
- assert ((rmInstance != NULL) && (firstResIdObj != NULL));\r
-\r
- rmObj = rmInstance->pResMgrObjHandle;\r
-\r
- if (rmObj == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
-\r
- if (EDMA3_RM_SOK == result)\r
- {\r
- gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);\r
-\r
- if (gblRegs == NULL)\r
- {\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- }\r
- }\r
-\r
- if (result == EDMA3_RM_SOK)\r
- {\r
- switch (firstResIdObj->type)\r
- {\r
- case EDMA3_RM_RES_DMA_CHANNEL:\r
- {\r
- firstResId = firstResIdObj->resId;\r
- lastResId = firstResId + (numResources - 1u);\r
-\r
- for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)\r
- {\r
- rmInstance->avlblDmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));\r
-\r
- /**\r
- * Enable the DMA channel in the DRAE/DRAEH registers also.\r
- */\r
- if (avlblIdx < 32u)\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE\r
- |= (0x1u << avlblIdx);\r
- }\r
- else\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH\r
- |= (0x1u << (avlblIdx - 32u));\r
- }\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_QDMA_CHANNEL:\r
- {\r
- firstResId = firstResIdObj->resId;\r
- lastResId = firstResId + (numResources - 1u);\r
-\r
- for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)\r
- {\r
- rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));\r
-\r
- /**\r
- * Enable the QDMA channel in the QRAE register also.\r
- */\r
- gblRegs->QRAE[rmInstance->initParam.regionId]\r
- |= (0x1u << avlblIdx);\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_TCC:\r
- {\r
- firstResId = firstResIdObj->resId;\r
- lastResId = firstResId + (numResources - 1u);\r
-\r
- for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)\r
- {\r
- rmInstance->avlblTccs[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));\r
-\r
- /**\r
- * Enable the Interrupt channel in the DRAE/DRAEH registers.\r
- * Also, If the region id coming from this\r
- * RM instance is same as the Master RM\r
- * Instance's region id, only then we will be\r
- * getting the interrupts on the same side.\r
- * So save the TCC in the allocatedTCCs[] array.\r
- */\r
- if (avlblIdx < 32u)\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE\r
- |= (0x1u << avlblIdx);\r
-\r
- if (edma3RegionId == rmInstance->initParam.regionId)\r
- {\r
- allocatedTCCs[0u] |= (0x1u << avlblIdx);\r
- }\r
- }\r
- else\r
- {\r
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH\r
- |= (0x1u << (avlblIdx - 32u));\r
-\r
- if (edma3RegionId == rmInstance->initParam.regionId)\r
- {\r
- allocatedTCCs[1u] |= (0x1u << (avlblIdx - 32u));\r
- }\r
- }\r
- }\r
- }\r
- break;\r
-\r
- case EDMA3_RM_RES_PARAM_SET:\r
- {\r
- firstResId = firstResIdObj->resId;\r
- lastResId = firstResId + (numResources - 1u);\r
-\r
- for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)\r
- {\r
- rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));\r
-\r
- /**\r
- * Also, make the actual PARAM Set NULL, checking the flag\r
- * whether it is required or not.\r
- */\r
- if (TRUE == rmInstance->paramInitRequired)\r
- {\r
- edma3MemSet((void *)(&gblRegs->PARAMENTRY[avlblIdx]),\r
- 0x00u,\r
- sizeof(gblRegs->PARAMENTRY[avlblIdx]));\r
- }\r
- }\r
- }\r
- break;\r
-\r
- default:\r
- result = EDMA3_RM_E_INVALID_PARAM;\r
- break;\r
- }\r
- }\r
-\r
-\r
- return result;\r
- }\r
-\r
-/* Resource Manager Internal functions - End */\r
-\r
-/* End of File */\r
+/*
+ * edma3resmgr.c
+ *
+ * EDMA3 Controller Resource Manager Interface Implementation
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/* Resource Manager Internal Header Files */
+#include <ti/sdo/edma3/rm/src/edma3resmgr.h>
+
+/* Instrumentation Header File */
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+#include <ti/sdo/edma3/rm/src/edma3_log.h>
+#endif
+
+/* For assert() */
+/**
+ * Define NDEBUG to ignore assert().
+ * NDEBUG should be defined before including assert.h header file.
+ */
+#include <assert.h>
+
+
+/* Global Defines, need to re-compile if values are changed */
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief EDMA3 Resource Manager behaviour of clearing CC ERROR interrupts.
+ * This macro controls the driver to enable/disable clearing of error
+ * status of all channels.
+ *
+ * On disabling this (with value 0x0), the channels owned by the region
+ * is cleared and its expected that some other entity is responsible for
+ * clearing the error status for channels not owned.
+ *
+ * Its recomended that this flag is a positive value, to ensure that
+ * error flags are cleared for all the channels.
+ */
+#define EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS (TRUE)
+
+/**
+ * \brief EDMA3 Resource Manager retry count to check the pending interrupts inside ISR.
+ * This macro controls the driver to check the pending interrupt for
+ * 'n' number of times.
+ * Minumum value is 1.
+ */
+#define EDMA3_RM_COMPL_HANDLER_RETRY_COUNT (10U)
+
+/**
+ * \brief EDMA3 Resource Manager retry count to check the pending CC Error Interrupt inside ISR
+ * This macro controls the driver to check the pending CC Error
+ * interrupt for 'n' number of times.
+ * Minumum value is 1.
+ */
+#define EDMA3_RM_CCERR_HANDLER_RETRY_COUNT (10U)
+
+
+
+/* Externel Variables */
+/*---------------------------------------------------------------------------*/
+/**
+ * Maximum Resource Manager Instances supported by the EDMA3 Package.
+ */
+extern const uint32_t EDMA3_MAX_RM_INSTANCES;
+
+
+#ifndef GENERIC
+/**
+ * \brief Static Configuration structure for EDMA3
+ * controller, to provide Global SoC specific Information.
+ *
+ * This configuration info can also be provided by the user at run-time,
+ * while calling EDMA3_RM_create (). If not provided at run-time,
+ * this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",
+ * for the specified platform.
+ */
+extern EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES];
+
+/**
+ * \brief Default Static Region Specific Configuration structure for
+ * EDMA3 controller, to provide region specific Information.
+ */
+extern EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+
+#endif
+
+
+/**
+ * \brief Region Specific Configuration structure for
+ * EDMA3 controller, to provide region specific Information.
+ *
+ * This configuration info can also be provided by the user at run-time,
+ * while calling EDMA3_RM_open (). If not provided at run-time,
+ * this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",
+ * for the specified platform.
+ */
+#ifdef BUILD_C6XDSP
+extern far EDMA3_RM_InstanceInitConfig *userInitConfig;
+extern far EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
+#else
+extern EDMA3_RM_InstanceInitConfig *userInitConfig;
+extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
+#endif
+
+/**
+ * Handles of EDMA3 Resource Manager Instances.
+ *
+ * Used to maintain information of the EDMA3 RM Instances
+ * for each HW controller.
+ * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per
+ * EDMA3 HW.
+ */
+#ifdef BUILD_C6XDSP
+extern far EDMA3_RM_Instance *resMgrInstance;
+extern far EDMA3_RM_Instance *ptrRMIArray;
+#else
+extern EDMA3_RM_Instance *ptrRMIArray;
+extern EDMA3_RM_Instance *resMgrInstance;
+
+#endif
+/** Max of DMA Channels */
+uint32_t edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Min of Link Channels */
+uint32_t edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Max of Link Channels */
+uint32_t edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Min of QDMA Channels */
+uint32_t edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Max of QDMA Channels */
+uint32_t edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Max of Logical Channels */
+uint32_t edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+
+/* Globals */
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief EDMA3 Resource Manager Objects, tied to each EDMA3 HW Controller.
+ *
+ * Typically one RM object will cater to one EDMA3 HW controller
+ * and will have all the global config information.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(resMgrObj, ".fardata:.edma3Globals");
+#endif
+EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];
+
+
+/**
+ * Global Array to store the mapping between DMA channels and Interrupt
+ * channels i.e. TCCs.
+ * DMA channel X can use any TCC Y. Transfer completion
+ * interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error
+ * interrupt will occur on DMA channel X (EMR/EMRH register, bit X). In that
+ * scenario, this DMA channel <-> TCC mapping will be used to point to
+ * the correct callback function.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3DmaChTccMapping, ".fardata:.edma3Globals");
+#endif
+static uint32_t edma3DmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_DMA_CH];
+
+
+/**
+ * Global Array to store the mapping between QDMA channels and Interrupt
+ * channels i.e. TCCs.
+ * QDMA channel X can use any TCC Y. Transfer completion
+ * interrupt will occur on the TCC Y (IPR/IPRH Register, bit Y), but error
+ * interrupt will occur on QDMA channel X (QEMR register, bit X). In that
+ * scenario, this QDMA channel <-> TCC mapping will be used to point to
+ * the correct callback function.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3QdmaChTccMapping, ".fardata:.edma3Globals");
+#endif
+static uint32_t edma3QdmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_QDMA_CH];
+
+
+/**
+ * Global Array to maintain the Callback details registered
+ * against a particular TCC. Used to call the callback
+ * functions linked to the particular channel.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3IntrParams, ".fardata:.edma3Globals");
+#endif
+static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TCC];
+
+
+/** edma3RegionId will be updated ONCE using the parameter regionId passed to
+ * the EDMA3_RM_open() function, for the Master RM instance (one who
+ * configures the Global Registers).
+ * This global variable will be used within the Interrupt handlers to know
+ * which shadow region registers to access. All other interrupts coming
+ * from other shadow regions will not be handled.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3RegionId, ".fardata:.edma3Globals");
+#endif
+static EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS;
+
+/** masterExists[] will be updated when the Master RM Instance modifies the
+ * Global EDMA3 configuration registers. It is used to prevent any other
+ * Master RM Instance creation.
+ * masterExists[] is per EDMA3 hardware, hence it is created
+ * as an array.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(masterExists, ".fardata:.edma3Globals");
+#endif
+static uint32_t masterExists [EDMA3_MAX_EDMA3_INSTANCES] = {FALSE,FALSE,FALSE,FALSE,FALSE};
+
+/**
+ * Number of PaRAM Sets actually present on the SoC. This will be updated
+ * while creating the Resource Manager Object.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3NumPaRAMSets, ".fardata:.edma3Globals");
+#endif
+uint32_t edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS;
+
+
+/**
+ * The list of Interrupt Channels which get allocated while requesting the
+ * TCC. It will be used while checking the IPR/IPRH bits in the RM ISR.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(allocatedTCCs, ".fardata:.edma3Globals");
+#endif
+static uint32_t allocatedTCCs[EDMA3_MAX_EDMA3_INSTANCES][2U] =
+ {
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
+ };
+
+
+/**
+ * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
+ * and stored in this array. It will be referenced in
+ * EDMA3_RM_allocContiguousResource () to look for contiguous resources.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(contiguousDmaRes, ".fardata:.edma3Globals");
+#endif
+static uint32_t contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0U, 0x0U};
+
+/**
+ * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
+ * and stored in this array. It will be referenced in
+ * EDMA3_RM_allocContiguousResource () to look for contiguous resources.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(contiguousQdmaRes, ".fardata:.edma3Globals");
+#endif
+static uint32_t contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0U};
+
+/**
+ * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
+ * and stored in this array. It will be referenced in
+ * EDMA3_RM_allocContiguousResource () to look for contiguous resources.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(contiguousTccRes, ".fardata:.edma3Globals");
+#endif
+static uint32_t contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0U, 0x0U};
+
+/**
+ * Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
+ * and stored in this array. It will be referenced in
+ * EDMA3_RM_allocContiguousResource () to look for contiguous resources.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(contiguousParamRes, ".fardata:.edma3Globals");
+#endif
+static uint32_t contiguousParamRes[EDMA3_MAX_PARAM_DWRDS];
+
+
+/**
+ * \brief Resources bound to a Channel
+ *
+ * When a request for a channel is made, the resources PaRAM Set and TCC
+ * get bound to that channel. This information is needed internally by the
+ * resource manager, when a request is made to free the channel,
+ * to free up the channel-associated resources.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3RmChBoundRes, ".fardata:.edma3Globals");
+#endif
+static EDMA3_RM_ChBoundResources edma3RmChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
+
+/**
+ * Used to reset the Internal EDMA3 Resource Manager Data Structures for the first time.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(rmInitDone, ".fardata:.edma3Globals");
+#endif
+ static uint16_t rmInitDone = FALSE;
+
+/*---------------------------------------------------------------------------*/
+
+/* Local functions prototypes */
+/*---------------------------------------------------------------------------*/
+/** EDMA3 Instance 0 Completion Handler Interrupt Service Routine */
+void lisrEdma3ComplHandler0(uint32_t edma3InstanceId);
+/** EDMA3 Instance 0 CC Error Interrupt Service Routine */
+void lisrEdma3CCErrHandler0(uint32_t edma3InstanceId);
+/**
+ * EDMA3 Instance 0 TC[0-7] Error Interrupt Service Routines
+ * for a maximum of 8 TCs (Transfer Controllers).
+ */
+void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId);
+
+
+/** Interrupt Handler for the Transfer Completion interrupt */
+static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj);
+/** Interrupt Handler for the Channel Controller Error interrupt */
+static void edma3CCErrHandler (const EDMA3_RM_Obj *rmObj);
+/** Interrupt Handler for the Transfer Controller Error interrupt */
+static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, uint32_t tcNum);
+
+
+/** Local MemZero function */
+void edma3MemZero(void *dst, uint32_t len);
+/** Local MemCpy function */
+void edma3MemCpy(void *dst, const void *src, uint32_t len);
+/* Local MemCopy function to copy Param Set ONLY */
+void edma3ParamCpy(volatile void *dst, const volatile void *src);
+
+/** Initialization of the Global region registers of the EDMA3 Controller */
+static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId, uint32_t numDmaChannels);
+/** Initialization of the Shadow region registers of the EDMA3 Controller */
+static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance);
+
+
+
+/* Internal functions for contiguous resource allocation */
+/**
+ * Finds a particular bit ('0' or '1') in the particular word from 'start'.
+ * If found, returns the position, else return -1.
+ */
+static int32_t findBitInWord (int32_t source, uint32_t start, uint16_t bit);
+
+/**
+ * Finds a particular bit ('0' or '1') in the specified resources' array
+ * from 'start' to 'end'. If found, returns the position, else return -1.
+ */
+static int32_t findBit (EDMA3_RM_ResType resType,
+ uint32_t start,
+ uint32_t end,
+ uint16_t bit);
+
+/**
+ * If successful, this function returns EDMA3_RM_SOK and the position
+ * of first available resource in 'positionRes'. Else returns error.
+ */
+static EDMA3_RM_Result allocAnyContigRes(EDMA3_RM_ResType resType,
+ uint32_t numResources,
+ uint32_t *positionRes);
+
+/**
+ * Starting from 'firstResIdObj', this function makes the next 'numResources'
+ * Resources non-available for future. Also, it does some global resisters'
+ * setting also.
+ */
+static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,
+ const EDMA3_RM_ResDesc *firstResIdObj,
+ uint32_t numResources);
+
+/*---------------------------------------------------------------------------*/
+
+EDMA3_RM_Result EDMA3_RM_create (uint32_t phyCtrllerInstId,
+ const EDMA3_RM_GblConfigParams *gblCfgParams,
+ const void *miscParam)
+ {
+ uint32_t count = 0U;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ const EDMA3_RM_MiscParam *miscOpt = (const EDMA3_RM_MiscParam *)miscParam;
+
+#ifdef GENERIC
+ /* GENERIC libraries don't come with a default confifguration, always
+ needs to be supplied with a parameter */
+ if (gblCfgParams == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /**
+ * We are NOT checking 'gblCfgParams' for NULL.
+ * If user has passed NULL, default config info will be
+ * taken from config file.
+ * 'param' is also not being checked because it could be
+ * NULL also.
+ */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ /* Initialize the global variables for the first time */
+ if (FALSE == rmInitDone)
+ {
+ edma3MemZero((void *)&(resMgrObj[count]),
+ sizeof(resMgrObj));
+ edma3MemZero((void *)(&(edma3IntrParams[0U])),
+ sizeof(edma3IntrParams));
+
+ rmInitDone = TRUE;
+ }
+
+ /* Initialization has been done */
+ if (resMgrObj[phyCtrllerInstId].state != EDMA3_RM_DELETED)
+ {
+ result = EDMA3_RM_E_OBJ_NOT_DELETED;
+ }
+ else
+ {
+ /**
+ * Check whether user has passed the Global Config Info.
+ * If yes, copy it to the driver data structures. Else, use the
+ * info from the config file edma3Cfg.c
+ */
+#ifndef GENERIC
+ if (NULL == gblCfgParams)
+ {
+ /* Take info from the specific config file */
+ edma3MemCpy((void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams),
+ (const void *)(&edma3GblCfgParams[phyCtrllerInstId]),
+ sizeof (EDMA3_RM_GblConfigParams));
+ }
+ else
+ {
+#endif
+ /* User passed the info, save it in the RM object first */
+ edma3MemCpy((void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams),
+ (const void *)(gblCfgParams),
+ sizeof (EDMA3_RM_GblConfigParams));
+#ifndef GENERIC
+ }
+#endif
+
+
+ /**
+ * Check whether DMA channel to PaRAM Set mapping exists or not.
+ * If it does not exist, set the mapping array as 1-to-1 mapped.
+ */
+ if (FALSE == resMgrObj[phyCtrllerInstId].gblCfgParams.dmaChPaRAMMapExists)
+ {
+ for (count = 0U; count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels; count++)
+ {
+ resMgrObj[phyCtrllerInstId].gblCfgParams.dmaChannelPaRAMMap[count] = count;
+ }
+ }
+
+
+ /**
+ * Update the actual number of PaRAM sets and
+ * Initialize Boundary Values for Logical Channel Ranges.
+ */
+ edma3NumPaRAMSets = resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets;
+ edma3_dma_ch_max_val[phyCtrllerInstId] = resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels - 1U;
+ edma3_link_ch_min_val[phyCtrllerInstId] = edma3_dma_ch_max_val[phyCtrllerInstId] + 1U;
+ edma3_link_ch_max_val[phyCtrllerInstId] = edma3_link_ch_min_val[phyCtrllerInstId] + (resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets - 1U);
+ edma3_qdma_ch_min_val[phyCtrllerInstId] = edma3_link_ch_max_val[phyCtrllerInstId] + 1U;
+ edma3_qdma_ch_max_val[phyCtrllerInstId] = edma3_qdma_ch_min_val[phyCtrllerInstId] + (resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels - 1U);
+ edma3_log_ch_max_val[phyCtrllerInstId] = edma3_qdma_ch_max_val[phyCtrllerInstId];
+
+ resMgrObj[phyCtrllerInstId].phyCtrllerInstId = phyCtrllerInstId;
+ resMgrObj[phyCtrllerInstId].state = EDMA3_RM_CREATED;
+ resMgrObj[phyCtrllerInstId].numOpens = 0U;
+
+ /* Make all the RM instances for this EDMA3 HW NULL */
+ for (count = 0U; count < EDMA3_MAX_RM_INSTANCES; count++)
+ {
+ edma3MemZero((void *)((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count),
+ sizeof(EDMA3_RM_Instance));
+
+ /* Also make this data structure NULL */
+ edma3MemZero((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count),
+ sizeof(EDMA3_RM_InstanceInitConfig));
+ }
+
+ /* Initialize the global edma3DmaChTccMapping array with EDMA3_MAX_TCC */
+ for ( count = 0U;
+ count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels;
+ count++
+ )
+ {
+ edma3DmaChTccMapping[phyCtrllerInstId][count] = EDMA3_MAX_TCC;
+ }
+
+ /* Initialize the global edma3QdmaChTccMapping array with EDMA3_MAX_TCC */
+ for ( count = 0U;
+ count < resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels;
+ count++
+ )
+ {
+ edma3QdmaChTccMapping[phyCtrllerInstId][count] = EDMA3_MAX_TCC;
+ }
+
+ /* Reset edma3RmChBoundRes Array*/
+ for (count = 0U; count < EDMA3_MAX_LOGICAL_CH; count++)
+ {
+ edma3RmChBoundRes[phyCtrllerInstId][count].paRAMId = -1;
+ edma3RmChBoundRes[phyCtrllerInstId][count].tcc = EDMA3_MAX_TCC;
+ }
+
+ /* Make the contiguousParamRes array NULL */
+ edma3MemZero((void *)(&(contiguousParamRes[0U])),
+ sizeof(contiguousParamRes));
+
+
+ /**
+ * Check the misc configuration options structure.
+ * Check whether the global registers' initialization
+ * is required or not.
+ * It is required ONLY if RM is running on the Master Processor.
+ */
+ if (NULL != miscOpt)
+ {
+ if (miscOpt->isSlave == FALSE)
+ {
+ /* It is a master. */
+ edma3GlobalRegionInit(phyCtrllerInstId, (resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels));
+ }
+ }
+ else
+ {
+ /* By default, global registers will be initialized. */
+ edma3GlobalRegionInit(phyCtrllerInstId, (resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels));
+ }
+ }
+ }
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_delete (uint32_t phyCtrllerInstId,
+ const void *param)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ /**
+ * If number of RM Instances is 0, then state should be
+ * EDMA3_RM_CLOSED OR EDMA3_RM_CREATED.
+ */
+ if ((0 == resMgrObj[phyCtrllerInstId].numOpens)
+ && ((resMgrObj[phyCtrllerInstId].state != EDMA3_RM_CLOSED)
+ && (resMgrObj[phyCtrllerInstId].state != EDMA3_RM_CREATED)))
+ {
+ result = EDMA3_RM_E_OBJ_NOT_CLOSED;
+ }
+ else
+ {
+ /**
+ * If number of RM Instances is NOT 0, then this function
+ * SHOULD NOT be called by anybody.
+ */
+ if (0 != resMgrObj[phyCtrllerInstId].numOpens)
+ {
+ result = EDMA3_RM_E_INVALID_STATE;
+ }
+ else
+ {
+ /** Change state to EDMA3_RM_DELETED */
+ resMgrObj[phyCtrllerInstId].state = EDMA3_RM_DELETED;
+
+ /* Reset the Allocated TCCs Array also. */
+ allocatedTCCs[phyCtrllerInstId][0U] = 0x0U;
+ allocatedTCCs[phyCtrllerInstId][1U] = 0x0U;
+
+ /* Also, reset the RM Object Global Config Info */
+ edma3MemZero((void *)&(resMgrObj[phyCtrllerInstId].gblCfgParams),
+ sizeof(EDMA3_RM_GblConfigParams));
+ }
+ }
+ }
+
+ return result;
+ }
+
+EDMA3_RM_Handle EDMA3_RM_open (uint32_t phyCtrllerInstId,
+ const EDMA3_RM_Param *initParam,
+ EDMA3_RM_Result *errorCode)
+ {
+ uint32_t intState = 0U;
+ uint32_t resMgrIdx = 0U;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Obj *rmObj = NULL;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Instance *temp_ptr_rm_inst = NULL;
+ EDMA3_RM_Handle retVal = NULL;
+ uint32_t dmaChDwrds = 0U;
+ uint32_t paramSetDwrds = 0U;
+ uint32_t tccDwrds = 0U;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+
+#ifdef GENERIC
+ /* GENERIC libraries don't come with a default confifguration, always
+ needs to be supplied with a parameter */
+ if ((initParam == NULL) || (initParam->rmInstInitConfig == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (((initParam == NULL)
+ || (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES))
+ || (errorCode == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ /* Check whether the semaphore handle is null or not */
+ if (NULL == initParam->rmSemHandle)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ rmObj = &resMgrObj[phyCtrllerInstId];
+ if (
+ (NULL == rmObj)
+ || (initParam->regionId >=
+ resMgrObj[phyCtrllerInstId].gblCfgParams.numRegions)
+ )
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3OsProtectEntry (phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ &intState);
+
+ /** Check state of RM Object.
+ * If no RM instance is opened and this is the first one,
+ * then state should be created/closed.
+ */
+ if ((rmObj->numOpens == 0) &&
+ ((rmObj->state != EDMA3_RM_CREATED) &&
+ (rmObj->state != EDMA3_RM_CLOSED)))
+ {
+ result = EDMA3_RM_E_INVALID_STATE;
+ edma3OsProtectExit (phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+ }
+ else
+ {
+ /**
+ * If num of instances opened is more than 0 and less than
+ * max allowed, then state should be opened.
+ */
+ if (((rmObj->numOpens > 0) &&
+ (rmObj->numOpens < EDMA3_MAX_RM_INSTANCES))
+ && (rmObj->state != EDMA3_RM_OPENED))
+ {
+ result = EDMA3_RM_E_INVALID_STATE;
+ edma3OsProtectExit (phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+ }
+ else
+ {
+ /* Check if max opens have passed */
+ if (rmObj->numOpens >= EDMA3_MAX_RM_INSTANCES)
+ {
+ result = EDMA3_RM_E_MAX_RM_INST_OPENED;
+ edma3OsProtectExit (phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+ }
+ }
+ }
+ }
+ }
+ }
+
+ if (EDMA3_RM_SOK == result)
+ {
+ /*
+ * Check whether the RM instance is Master or not.
+ * If it is master, check whether a master already exists
+ * or not. There should NOT be more than 1 master.
+ * Return error code if master already exists
+ */
+ if ((TRUE == masterExists[phyCtrllerInstId]) && (TRUE == initParam->isMaster))
+ {
+ /* No two masters should exist, return error */
+ result = EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS;
+ edma3OsProtectExit (phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+ }
+ else
+ {
+ /* Create Res Mgr Instance */
+ for (resMgrIdx = 0U; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)
+ {
+ temp_ptr_rm_inst = ((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);
+
+ if (NULL != temp_ptr_rm_inst)
+ {
+ if (NULL == temp_ptr_rm_inst->pResMgrObjHandle)
+ {
+ /* Handle to the EDMA3 HW Object */
+ temp_ptr_rm_inst->pResMgrObjHandle = rmObj;
+ /* Handle of the Res Mgr Instance */
+ rmInstance = temp_ptr_rm_inst;
+
+ /* Also make this data structure NULL, just for safety. */
+ edma3MemZero((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx),
+ sizeof(EDMA3_RM_InstanceInitConfig));
+
+ break;
+ }
+ }
+ }
+
+ /* Check whether a RM instance has been created or not */
+ if (NULL == rmInstance)
+ {
+ result = EDMA3_RM_E_MAX_RM_INST_OPENED;
+ edma3OsProtectExit (phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+ }
+ else
+ {
+ /* Copy the InitPaRAM first */
+ edma3MemCpy((void *)(&rmInstance->initParam),
+ (const void *)(initParam),
+ sizeof (EDMA3_RM_Param));
+
+ if (rmObj->gblCfgParams.globalRegs != NULL)
+ {
+ globalRegs = (volatile EDMA3_CCRL_Regs *)
+ (rmObj->gblCfgParams.globalRegs);
+ rmInstance->shadowRegs = (EDMA3_CCRL_ShadowRegs *)
+ &(globalRegs->SHADOW[rmInstance->initParam.regionId]);
+
+ /* copy the instance specific semaphore handle */
+ rmInstance->initParam.rmSemHandle = initParam->rmSemHandle;
+
+ /**
+ * Check whether user has passed information about resources
+ * owned and reserved by this instance. This is region specific
+ * information. If he has not passed, dafault static config info will be taken
+ * from the config file edma3Cfg.c, according to the regionId specified.
+ *
+ * resMgrIdx specifies the RM instance number created just now.
+ * Use it to populate the userInitConfig [].
+ */
+#ifndef GENERIC
+ if (NULL == initParam->rmInstInitConfig)
+ {
+ /* Take the info from the specific config file */
+ edma3MemCpy((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx),
+ (const void *)(&defInstInitConfig[phyCtrllerInstId][initParam->regionId]),
+ sizeof (EDMA3_RM_InstanceInitConfig));
+ }
+ else
+ {
+#endif
+ /* User has passed the region specific info. */
+ edma3MemCpy((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx),
+ (const void *)(initParam->rmInstInitConfig),
+ sizeof (EDMA3_RM_InstanceInitConfig));
+#ifndef GENERIC
+ }
+#endif
+
+ rmInstance->initParam.rmInstInitConfig =
+ ((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);
+
+ dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / (uint32_t)32U;
+ if (dmaChDwrds == 0)
+ {
+ /* In case DMA channels are < 32 */
+ dmaChDwrds = 1U;
+ }
+
+ paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / (uint32_t)32U;
+ if (paramSetDwrds == 0)
+ {
+ /* In case PaRAM Sets are < 32 */
+ paramSetDwrds = 1U;
+ }
+
+ tccDwrds = rmObj->gblCfgParams.numTccs / (uint32_t)32U;
+ if (tccDwrds == 0)
+ {
+ /* In case TCCs are < 32 */
+ tccDwrds = 1U;
+ }
+
+ for (resMgrIdx = 0U; resMgrIdx < dmaChDwrds; ++resMgrIdx)
+ {
+ rmInstance->avlblDmaChannels[resMgrIdx]
+ = rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resMgrIdx];
+ }
+
+ rmInstance->avlblQdmaChannels[0U]
+ = rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U];
+
+ for (resMgrIdx = 0U; resMgrIdx < paramSetDwrds; ++resMgrIdx)
+ {
+ rmInstance->avlblPaRAMSets[resMgrIdx]
+ = rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resMgrIdx];
+ }
+
+ for (resMgrIdx = 0U; resMgrIdx < tccDwrds; ++resMgrIdx)
+ {
+ rmInstance->avlblTccs [resMgrIdx]
+ = rmInstance->initParam.rmInstInitConfig->ownTccs[resMgrIdx];
+ }
+
+ /*
+ * Mark the PaRAM Sets corresponding to DMA channels as RESERVED.
+ * For e.g. on a platform where only 32 DMA channels exist,
+ * mark the first 32 PaRAM Sets as reserved. These param sets
+ * will not be returned in case user requests for ANY link
+ * channel.
+ */
+ for (resMgrIdx = 0U; resMgrIdx < rmObj->gblCfgParams.numDmaChannels; ++resMgrIdx)
+ {
+ rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[resMgrIdx/32U] |= ((uint32_t)1U<<(resMgrIdx%32U));
+ }
+
+ /*
+ * If the EDMA RM instance is MASTER (ie. initParam->isMaster
+ * is TRUE), save the region ID.
+ * Only this shadow region will receive the
+ * EDMA3 interrupts, if enabled.
+ */
+ if (TRUE == initParam->isMaster)
+ {
+ /* Store the region id to use it in the ISRs */
+ edma3RegionId = rmInstance->initParam.regionId;
+ masterExists[phyCtrllerInstId] = TRUE;
+ }
+
+ if (TRUE == initParam->regionInitEnable)
+ {
+ edma3ShadowRegionInit (rmInstance);
+ }
+
+ /**
+ * By default, PaRAM Sets allocated using this RM Instance
+ * will get cleared during their allocation.
+ * User can stop their clearing by calling specific IOCTL
+ * command.
+ */
+ rmInstance->paramInitRequired = TRUE;
+
+
+ /**
+ * By default, during the EDMA3_RM_allocLogicalChannel (),
+ * global EDMA3 registers (DCHMAP/QCHMAP) and the allocated
+ * PaRAM Set will be programmed accordingly, for users using this
+ * RM Instance.
+ * User can stop their pre-programming by calling
+ * EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION
+ * IOCTL command.
+ */
+ rmInstance->regModificationRequired = TRUE;
+
+
+ if (EDMA3_RM_SOK == result)
+ {
+ rmObj->state = EDMA3_RM_OPENED;
+ /* Increase the Instance count */
+ resMgrObj[phyCtrllerInstId].numOpens++;
+ retVal = rmInstance;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+
+ edma3OsProtectExit (phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+ }
+ }
+ }
+
+ *errorCode = result;
+ return (EDMA3_RM_Handle)retVal;
+ }
+
+EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr,
+ const void *param)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ uint32_t intState = 0U;
+ uint32_t resMgrIdx = 0U;
+ EDMA3_RM_Obj *rmObj = NULL;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ uint32_t dmaChDwrds;
+ uint32_t paramSetDwrds;
+ uint32_t tccDwrds;
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (NULL == hEdmaResMgr)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+ else
+ {
+ /* Check state of driver, state should be opened */
+ if (rmObj->state != EDMA3_RM_OPENED)
+ {
+ result = (EDMA3_RM_E_OBJ_NOT_OPENED);
+ }
+ else
+ {
+ dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / (uint32_t)32U;
+ paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / (uint32_t)32U;
+ tccDwrds = rmObj->gblCfgParams.numTccs / (uint32_t)32U;
+
+ /* Set the instance config as NULL*/
+ for (resMgrIdx = 0U; resMgrIdx < dmaChDwrds; ++resMgrIdx)
+ {
+ rmInstance->avlblDmaChannels[resMgrIdx] = 0x0U;
+ }
+ for (resMgrIdx = 0U; resMgrIdx < paramSetDwrds; ++resMgrIdx)
+ {
+ rmInstance->avlblPaRAMSets[resMgrIdx] = 0x0U;
+ }
+ rmInstance->avlblQdmaChannels[0U] = 0x0U;
+ for (resMgrIdx = 0U; resMgrIdx < tccDwrds; ++resMgrIdx)
+ {
+ rmInstance->avlblTccs[resMgrIdx] = 0x0U;
+ }
+
+ /**
+ * If this is the Master Instance, reset the static variable
+ * 'masterExists[]'.
+ */
+ if (TRUE == rmInstance->initParam.isMaster)
+ {
+ masterExists[rmObj->phyCtrllerInstId] = FALSE;
+ edma3RegionId = EDMA3_MAX_REGIONS;
+ }
+
+ /* Reset the Initparam for this RM Instance */
+ edma3MemZero((void *)&(rmInstance->initParam),
+ sizeof(EDMA3_RM_Param));
+
+ /* Critical section starts */
+ edma3OsProtectEntry (rmObj->phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ &intState);
+
+ /* Decrease the Number of Opens */
+ --rmObj->numOpens;
+ if (0 == rmObj->numOpens)
+ {
+ edma3MemZero((void *)&(edma3RmChBoundRes[rmObj->phyCtrllerInstId]),
+ sizeof(edma3RmChBoundRes[rmObj->phyCtrllerInstId]));
+
+ rmObj->state = EDMA3_RM_CLOSED;
+ }
+
+ /* Critical section ends */
+ edma3OsProtectExit (rmObj->phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+
+ rmInstance->pResMgrObjHandle = NULL;
+ rmInstance->shadowRegs = NULL;
+ rmInstance = NULL;
+ }
+ }
+ }
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_allocResource(EDMA3_RM_Handle hEdmaResMgr,
+ EDMA3_RM_ResDesc *resObj)
+ {
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Result semResult = EDMA3_RM_SOK;
+ uint32_t avlblIdx = 0U;
+ uint32_t resIdClr = 0x0;
+ uint32_t resIdSet = 0x0;
+ uint32_t resId;
+ volatile EDMA3_CCRL_Regs *gblRegs = NULL;
+ uint32_t mapXbarEvtToChanFlag = FALSE;
+ uint32_t xBarEvtBeforeMap = 0;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((hEdmaResMgr == NULL) || (resObj == NULL))
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if ((rmObj == NULL) ||
+ (rmObj->gblCfgParams.globalRegs == NULL))
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+ else
+ {
+ gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+ edma3Id = rmObj->phyCtrllerInstId;
+ resId = resObj->resId;
+
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resId%32U)));
+ resIdSet = (1U << (resId%32U));
+
+ if ( rmInstance->mapXbarToChan != NULL)
+ {
+ xBarEvtBeforeMap = resId;
+ if ((resId > rmObj->gblCfgParams.numDmaChannels) &&
+ (resId != EDMA3_RM_RES_ANY) &&
+ (resObj->type == EDMA3_RM_RES_DMA_CHANNEL))
+ {
+ result = rmInstance->mapXbarToChan(xBarEvtBeforeMap,
+ &resObj->resId,
+ &rmInstance->rmXbarToEvtMapConfig);
+ if (EDMA3_RM_SOK == result)
+ {
+ resId = resObj->resId;
+ mapXbarEvtToChanFlag = TRUE;
+ }
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /**
+ * Take the instance specific semaphore, to prevent simultaneous
+ * access to the shared resources.
+ */
+ semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,
+ EDMA3_OSSEM_NO_TIMEOUT);
+ if (EDMA3_RM_SOK == semResult)
+ {
+ switch (resObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0U;
+ avlblIdx <
+ rmObj->gblCfgParams.numDmaChannels;
+ ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[avlblIdx/32U])
+ &
+ (rmInstance->avlblDmaChannels[avlblIdx/32U])
+ &
+ ~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[avlblIdx/32U])
+ &
+ ((uint32_t)1U << (avlblIdx%32U))) != FALSE)
+ {
+ /*
+ * Match found.
+ * A resource which is owned by this instance of the
+ * Resource Manager and which is presently available
+ * and which has not been reserved - is found.
+ */
+ resObj->resId = avlblIdx;
+ /*
+ * Mark the 'match found' resource as "Not Available"
+ * for future requests
+ */
+ rmInstance->avlblDmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the DMA channel in the
+ * DRAE/DRAEH registers also.
+ */
+ if (avlblIdx < 32U)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= ((uint32_t)0x1U << avlblIdx);
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= ((uint32_t)0x1U << (avlblIdx - 32U));
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if (avlblIdx == rmObj->gblCfgParams.numDmaChannels)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numDmaChannels)
+ {
+ /*
+ * Check if specified resource is owned
+ * by this instance of the resource manager
+ */
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resId/32U])&(resIdSet))!=FALSE)
+ {
+ /* Now check if specified resource is available presently*/
+ if (((rmInstance->avlblDmaChannels[resId/32U])&(resIdSet))!=FALSE)
+ {
+ /*
+ * Mark the specified channel as "Not Available"
+ * for future requests
+ */
+ rmInstance->avlblDmaChannels[resId/32U] &= resIdClr;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ if (resId < 32U)
+ {
+ rmInstance->shadowRegs->EECR = (1UL << resId);
+
+ /**
+ * Enable the DMA channel in the
+ * DRAE registers also.
+ */
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= ((uint32_t)0x1U << resId);
+ }
+ else
+ {
+ rmInstance->shadowRegs->EECRH = (1UL << resId);
+
+ /**
+ * Enable the DMA channel in the
+ * DRAEH registers also.
+ */
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= ((uint32_t)0x1U << (resId - 32U));
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0U; avlblIdx<rmObj->gblCfgParams.numQdmaChannels; ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[avlblIdx/32U])
+ &
+ (rmInstance->avlblQdmaChannels[avlblIdx/32U])
+ &
+ ~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[avlblIdx/32U])
+ &
+ ((uint32_t)1U << (avlblIdx%32U))) != FALSE)
+ {
+ resObj->resId = avlblIdx;
+ rmInstance->avlblQdmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the QDMA channel in the
+ * QRAE register also.
+ */
+ gblRegs->QRAE[rmInstance->initParam.regionId]
+ |= ((uint32_t)0x1U << avlblIdx);
+ }
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if (avlblIdx == rmObj->gblCfgParams.numQdmaChannels)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numQdmaChannels)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32U])&(resIdSet))!=FALSE)
+ {
+ if (((rmInstance->avlblQdmaChannels [resId/32U])&(resIdSet))!=FALSE)
+ {
+ rmInstance->avlblQdmaChannels [resId/32U] &= resIdClr;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the QDMA channel in the
+ * QRAE register also.
+ */
+ gblRegs->QRAE[rmInstance->initParam.regionId]
+ |= ((uint32_t)0x1U << resId);
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_TCC :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0U; avlblIdx<rmObj->gblCfgParams.numTccs; ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [avlblIdx/32U])
+ & (rmInstance->avlblTccs [avlblIdx/32U])
+ & ~(rmInstance->initParam.rmInstInitConfig->resvdTccs [avlblIdx/32U])
+ & ((uint32_t)1U << (avlblIdx%32U)))!=FALSE)
+ {
+ resObj->resId = avlblIdx;
+ rmInstance->avlblTccs [avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the Interrupt channel in the
+ * DRAE/DRAEH registers also.
+ * Also, If the region id coming from this
+ * RM instance is same as the Master RM
+ * Instance's region id, only then we will be
+ * getting the interrupts on the same side.
+ * So save the TCC in the allocatedTCCs[] array.
+ */
+ if (avlblIdx < 32U)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= ((uint32_t)0x1U << avlblIdx);
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << avlblIdx);
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= ((uint32_t)0x1U << (avlblIdx - 32U));
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (avlblIdx - 32U));
+ }
+ }
+ }
+
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if ( avlblIdx == rmObj->gblCfgParams.numTccs)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numTccs)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32U])&(resIdSet))!=FALSE)
+ {
+ if (((rmInstance->avlblTccs [resId/32U])&(resIdSet))!=FALSE)
+ {
+ rmInstance->avlblTccs [resId/32U] &= resIdClr;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the Interrupt channel in the
+ * DRAE/DRAEH registers also.
+ * Also, If the region id coming from this
+ * RM instance is same as the Master RM
+ * Instance's region id, only then we will be
+ * getting the interrupts on the same side.
+ * So save the TCC in the allocatedTCCs[] array.
+ */
+ if (resId < 32U)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= ((uint32_t)0x1U << resId);
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << resId);
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= ((uint32_t)0x1U << (resId - 32U));
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (resId - 32U));
+ }
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0U; avlblIdx<rmObj->gblCfgParams.numPaRAMSets; ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [avlblIdx/32U])
+ &
+ (rmInstance->avlblPaRAMSets [avlblIdx/32U])
+ &
+ ~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets [avlblIdx/32U])
+ &
+ ((uint32_t)1U << (avlblIdx%32U)))!=FALSE)
+ {
+ resObj->resId = avlblIdx;
+ rmInstance->avlblPaRAMSets [avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Also, make the actual PARAM Set NULL, checking the flag
+ * whether it is required or not.
+ */
+ if ((TRUE == rmInstance->regModificationRequired)
+ && (TRUE == rmInstance->paramInitRequired))
+ {
+ edma3MemZero((void *)(&gblRegs->PARAMENTRY[avlblIdx]),
+ sizeof(gblRegs->PARAMENTRY[avlblIdx]));
+ }
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if ( avlblIdx == rmObj->gblCfgParams.numPaRAMSets)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numPaRAMSets)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32U])&(resIdSet))!=FALSE)
+ {
+ if (((rmInstance->avlblPaRAMSets [resId/32U])&(resIdSet)) !=FALSE)
+ {
+ rmInstance->avlblPaRAMSets [resId/32U] &= resIdClr;
+
+ /**
+ * Also, make the actual PARAM Set NULL, checking the flag
+ * whether it is required or not.
+ */
+ if ((TRUE == rmInstance->regModificationRequired)
+ && (TRUE == rmInstance->paramInitRequired))
+ {
+ edma3MemZero((void *)(&gblRegs->PARAMENTRY[resId]),
+ sizeof(gblRegs->PARAMENTRY[resId]));
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ default:
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+
+ /* Return the semaphore back */
+ semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
+ }
+ }
+ }
+ }
+
+ /**
+ * Check the Resource Allocation Result 'result' first. If Resource
+ * Allocation has resulted in an error, return it (having more priority than
+ * semResult.
+ * Else, return semResult.
+ */
+ if (EDMA3_RM_SOK == result)
+ {
+ /**
+ * Resource Allocation successful, return semResult for returning
+ * semaphore.
+ */
+ result = semResult;
+ if ((rmInstance->configScrMapXbarToEvt != NULL) &&
+ (mapXbarEvtToChanFlag == TRUE))
+ {
+ rmInstance->configScrMapXbarToEvt(xBarEvtBeforeMap, resObj->resId);
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr,
+ const EDMA3_RM_ResDesc *resObj)
+ {
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Result semResult = EDMA3_RM_SOK;
+ uint32_t resId;
+ uint32_t resIdSet = 0x0;
+ volatile EDMA3_CCRL_Regs *gblRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((hEdmaResMgr == NULL) || (resObj == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if ((rmObj == NULL) ||
+ (rmObj->gblCfgParams.globalRegs == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+ edma3Id = rmObj->phyCtrllerInstId;
+ resId = resObj->resId;
+
+ resIdSet = 1U << (resId%32U);
+
+ /**
+ * Take the instance specific semaphore, to prevent simultaneous
+ * access to the shared resources.
+ */
+ semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,
+ EDMA3_OSSEM_NO_TIMEOUT);
+
+ if (EDMA3_RM_SOK == semResult)
+ {
+ switch (resObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL :
+ {
+ if (resId < rmObj->gblCfgParams.numDmaChannels)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels [resId/32U]) & (resIdSet))!=FALSE)
+ {
+ if (((~(rmInstance->avlblDmaChannels[resId/32U]))&(resIdSet))!=FALSE)
+ {
+ /*
+ * Mark the specified channel as "Available"
+ * for future requests
+ */
+ rmInstance->avlblDmaChannels[resId/32U] |= resIdSet;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * DMA Channel is freed.
+ * Reset the bit specific to the DMA channel
+ * in the DRAE/DRAEH register also.
+ */
+ if (resId < 32U)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ &= (~((uint32_t)0x1U << resId));
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ &= (~((uint32_t)0x1U << (resId-32U)));
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ result = EDMA3_RM_E_RES_ALREADY_FREE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL :
+ {
+ if (resId < rmObj->gblCfgParams.numQdmaChannels)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32U]) & (resIdSet))!=FALSE)
+ {
+ if (((~(rmInstance->avlblQdmaChannels [resId/32U])) & (resIdSet))!=FALSE)
+ {
+ rmInstance->avlblQdmaChannels [resId/32U] |= resIdSet;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * QDMA Channel is freed.
+ * Reset the bit specific to the QDMA channel
+ * in the QRAE register also.
+ */
+ gblRegs->QRAE[rmInstance->initParam.regionId]
+ &= (~((uint32_t)0x1U << resId));
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ result = EDMA3_RM_E_RES_ALREADY_FREE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_TCC :
+ {
+ if (resId < rmObj->gblCfgParams.numTccs)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32U]) & (resIdSet))!=FALSE)
+ {
+ if (((~(rmInstance->avlblTccs [resId/32U])) & (resIdSet))!=FALSE)
+ {
+ rmInstance->avlblTccs [resId/32U] |= resIdSet;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Interrupt Channel is freed.
+ * Reset the bit specific to the Interrupt
+ * channel in the DRAE/DRAEH register also.
+ * Also, if we have earlier saved this
+ * TCC in allocatedTCCs[] array,
+ * remove it from there too.
+ */
+ if (resId < 32U)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ &= (~((uint32_t)0x1U << resId));
+
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0U] &= (~((uint32_t)0x1U << resId));
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ &= (~((uint32_t)0x1U << (resId-32U)));
+
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1U] &= (~((uint32_t)0x1U << (resId -32U)));
+ }
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ result = EDMA3_RM_E_RES_ALREADY_FREE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET :
+ {
+ if (resId < rmObj->gblCfgParams.numPaRAMSets)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32U])&(resIdSet))!=FALSE)
+ {
+ if (((~(rmInstance->avlblPaRAMSets [resId/32U]))&(resIdSet))!=FALSE)
+ {
+ rmInstance->avlblPaRAMSets [resId/32U] |= resIdSet;
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ result = EDMA3_RM_E_RES_ALREADY_FREE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ default:
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+ semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
+ }
+ }
+ }
+
+ /**
+ * Check the Free Resource Result 'result' first. If Free Resource
+ * has resulted in an error, return it (having more priority than
+ * semResult.
+ * Else, return semResult.
+ */
+ if (EDMA3_RM_SOK == result)
+ {
+ /**
+ * Free Resource successful, return semResult for returning
+ * semaphore.
+ */
+ result = semResult;
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
+ EDMA3_RM_ResDesc *lChObj,
+ uint32_t *pParam,
+ uint32_t *pTcc)
+ {
+ EDMA3_RM_ResDesc *chObj;
+ EDMA3_RM_ResDesc resObj;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ uint32_t mappedPaRAMId=0U;
+ uint32_t mappedTcc = EDMA3_RM_CH_NO_TCC_MAP;
+ int32_t paRAMId = (int32_t)EDMA3_RM_RES_ANY;
+ volatile EDMA3_CCRL_Regs *gblRegs = NULL;
+ uint32_t qdmaChId = EDMA3_MAX_PARAM_SETS;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((lChObj == NULL) || (hEdmaResMgr == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ chObj = lChObj;
+
+ if ((chObj->type == EDMA3_RM_RES_DMA_CHANNEL)
+ || (chObj->type == EDMA3_RM_RES_QDMA_CHANNEL))
+ {
+ /**
+ * If the request is for a DMA or QDMA channel, check the
+ * pParam and pTcc objects also.
+ * For the Link channel request, they could be NULL.
+ */
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((pParam == NULL) || (pTcc == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ if (rmObj->gblCfgParams.globalRegs == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ edma3Id = rmObj->phyCtrllerInstId;
+ gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+
+ switch (chObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL:
+ {
+ if ((chObj->resId == EDMA3_RM_DMA_CHANNEL_ANY)
+ || (chObj->resId == EDMA3_RM_RES_ANY))
+ {
+ /* Request for ANY DMA channel. */
+ resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+ resObj.resId = EDMA3_RM_RES_ANY;
+ result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* DMA channel allocated successfully. */
+ chObj->resId = resObj.resId;
+
+ /**
+ * Check the PaRAM Set user has specified for this DMA channel.
+ * Two cases exist:
+ * a) DCHMAP exists: Any PaRAM Set can be used
+ * b) DCHMAP does not exist: Should not be possible
+ * only if the channel allocated (ANY) and PaRAM requested
+ * are same.
+ */
+ if ((*pParam) == EDMA3_RM_PARAM_ANY)
+ {
+ /* User specified ANY PaRAM Set; Check the mapping. */
+ mappedPaRAMId = rmObj->gblCfgParams.dmaChannelPaRAMMap[resObj.resId];
+ if (mappedPaRAMId != EDMA3_RM_CH_NO_PARAM_MAP)
+ {
+ /** If some PaRAM set is statically mapped to the returned
+ * channel number, use that.
+ */
+ paRAMId = (int32_t)mappedPaRAMId;
+ }
+ }
+ else
+ {
+ /* User specified some PaRAM Set; check that can be used or not. */
+ if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)
+ {
+ paRAMId = (int32_t)(*pParam);
+ }
+ else
+ {
+ /**
+ * Channel mapping does not exist. If the PaRAM Set requested
+ * is the same as dma channel allocated (coincidentally), it is fine.
+ * Else return error.
+ */
+ if ((*pParam) != (resObj.resId))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+
+ /**
+ * Free the previously allocated DMA channel also.
+ */
+ EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+ else
+ {
+ paRAMId = (int32_t)(*pParam);
+ }
+ }
+ }
+
+ mappedTcc = rmObj->gblCfgParams.dmaChannelTccMap[resObj.resId];
+ }
+ }
+ else
+ {
+ if (chObj->resId <= edma3_dma_ch_max_val[edma3Id])
+ {
+ /* Request for a specific DMA channel */
+ resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+ resObj.resId = chObj->resId;
+ result = EDMA3_RM_allocResource(hEdmaResMgr,
+ (EDMA3_RM_ResDesc *)&resObj);
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /**
+ * Check the PaRAM Set user has specified for this DMA channel.
+ * Two cases exist:
+ * a) DCHMAP exists: Any PaRAM Set can be used
+ * b) DCHMAP does not exist: Should not be possible
+ * only if the channel allocated (ANY) and PaRAM requested
+ * are same.
+ */
+ if ((*pParam) == EDMA3_RM_PARAM_ANY)
+ {
+ /* User specified ANY PaRAM Set; Check the mapping. */
+ mappedPaRAMId = rmObj->gblCfgParams.dmaChannelPaRAMMap[resObj.resId];
+ if (mappedPaRAMId != EDMA3_RM_CH_NO_PARAM_MAP)
+ {
+ /** If some PaRAM set is statically mapped to the returned
+ * channel number, use that.
+ */
+ paRAMId = (int32_t)mappedPaRAMId;
+ }
+ }
+ else
+ {
+ /* User specified some PaRAM Set; check that can be used or not. */
+ if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)
+ {
+ paRAMId = (int32_t)(*pParam);
+ }
+ else
+ {
+ /**
+ * Channel mapping does not exist. If the PaRAM Set requested
+ * is the same as dma channel allocated (coincidentally), it is fine.
+ * Else return error.
+ */
+ if ((*pParam) != (resObj.resId))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+
+ /**
+ * Free the previously allocated DMA channel also.
+ */
+ EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+ else
+ {
+ paRAMId = (int32_t)(*pParam);
+ }
+ }
+ }
+
+ mappedTcc = rmObj->gblCfgParams.dmaChannelTccMap[chObj->resId];
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+
+ case EDMA3_RM_RES_QDMA_CHANNEL:
+ {
+ if ((chObj->resId == EDMA3_RM_QDMA_CHANNEL_ANY)
+ || (chObj->resId == EDMA3_RM_RES_ANY))
+ {
+ /* First request for any available QDMA channel */
+ resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+ resObj.resId = EDMA3_RM_RES_ANY;
+ result = EDMA3_RM_allocResource(hEdmaResMgr,
+ (EDMA3_RM_ResDesc *)&resObj);
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* Return the actual QDMA channel id. */
+ chObj->resId = resObj.resId;
+
+ /* Save the Logical-QDMA channel id for future use. */
+ qdmaChId = resObj.resId + edma3_qdma_ch_min_val[edma3Id];
+
+ /**
+ * Check the PaRAM Set user has specified for this QDMA channel.
+ * If he has specified any particular PaRAM Set, use that.
+ */
+ if ((*pParam) != EDMA3_RM_PARAM_ANY)
+ {
+ /* User specified ANY PaRAM Set; Check the mapping. */
+ paRAMId = (int32_t)(*pParam);
+ }
+ }
+ }
+ else
+ {
+ if (chObj->resId < rmObj->gblCfgParams.numQdmaChannels)
+ {
+ /* Request for a specific QDMA channel */
+ resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+ resObj.resId = chObj->resId;
+ result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* Save the Logical-QDMA channel id for future use. */
+ qdmaChId = chObj->resId + edma3_qdma_ch_min_val[edma3Id];
+
+ /**
+ * Check the PaRAM Set user has specified for this QDMA channel.
+ * If he has specified any particular PaRAM Set, use that.
+ */
+ if ((*pParam) != EDMA3_RM_PARAM_ANY)
+ {
+ /* User specified ANY PaRAM Set; Check the mapping. */
+ paRAMId = (int32_t)(*pParam);
+ }
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET:
+ {
+ /* Request for a LINK channel. */
+ if ((chObj->resId == EDMA3_RM_PARAM_ANY)
+ || (chObj->resId == EDMA3_RM_RES_ANY))
+ {
+ /* Request for ANY LINK channel. */
+ paRAMId = (int32_t)EDMA3_RM_RES_ANY;
+ }
+ else
+ {
+ if (chObj->resId < edma3NumPaRAMSets)
+ {
+ /* Request for a Specific LINK channel. */
+ paRAMId = (int32_t)(chObj->resId);
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* Try to allocate the link channel */
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ resObj.resId = (uint32_t)paRAMId;
+ result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+
+ if (result == EDMA3_RM_SOK)
+ {
+ uint32_t linkCh = edma3_link_ch_min_val[edma3Id];
+
+ /* Return the actual PaRAM Id. */
+ chObj->resId = resObj.resId;
+
+ /*
+ * Search for the next Link channel place-holder available,
+ * starting from EDMA3_RM_LINK_CH_MIN_VAL.
+ * It will be used for future operations on the Link channel.
+ */
+ while ((edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId != -1)
+ && (linkCh <= edma3_link_ch_max_val[edma3Id]))
+ {
+ /* Move to the next place-holder. */
+ linkCh++;
+ }
+
+ /* Verify the returned handle, it should lie in the correct range */
+ if (linkCh > edma3_link_ch_max_val[edma3Id])
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+
+ /* Free the PaRAM Set now. */
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ resObj.resId = chObj->resId;
+ result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+ else
+ {
+ /* Save the PaRAM Id for the Link Channel. */
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId = (int32_t)(chObj->resId);
+
+ /**
+ * Remove any linking. Before doing that, check
+ * whether it is permitted or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ *((&gblRegs->PARAMENTRY[chObj->resId].OPT)
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFU;
+ }
+ }
+ }
+ }
+ }
+ break;
+
+ default:
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+ }
+ }
+
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /**
+ * For DMA/QDMA channels, we still have to allocate more resources like
+ * TCC, PaRAM Set etc.
+ * For Link channel, only the PaRAMSet is required and that has been
+ * allocated so no further operations required.
+ */
+
+ /* Further resources' allocation for DMA channel. */
+ if (chObj->type == EDMA3_RM_RES_DMA_CHANNEL)
+ {
+ /* First allocate a PaRAM Set */
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ /* Use the saved param id now. */
+ resObj.resId = (uint32_t)paRAMId;
+ result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ if (result == EDMA3_RM_SOK)
+ {
+ /**
+ * PaRAM Set allocation succeeded.
+ * Save the PaRAM Set first.
+ */
+ *pParam = resObj.resId;
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].paRAMId = (int32_t)(resObj.resId);
+
+ /* Allocate the TCC now. */
+ resObj.type = EDMA3_RM_RES_TCC;
+ if ((*pTcc) == EDMA3_RM_TCC_ANY)
+ {
+ if (mappedTcc == EDMA3_RM_CH_NO_TCC_MAP)
+ {
+ resObj.resId = EDMA3_RM_RES_ANY;
+ }
+ else
+ {
+ resObj.resId = mappedTcc;
+ }
+ }
+ else
+ {
+ resObj.resId = *pTcc;
+ }
+
+ result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ if (result == EDMA3_RM_SOK)
+ {
+ /* TCC allocation succeeded. Save it first. */
+ *pTcc = resObj.resId;
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].tcc = resObj.resId;
+
+ /**
+ * Check first whether the global registers and the allocated
+ * PaRAM Set can be modified or not. If yes, do the needful.
+ * Else leave this for the user.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /* Set TCC of the allocated Param Set. */
+ gblRegs->PARAMENTRY[*pParam].OPT &= EDMA3_RM_OPT_TCC_CLR_MASK;
+ gblRegs->PARAMENTRY[*pParam].OPT |= EDMA3_RM_OPT_TCC_SET_MASK(*pTcc);
+
+ /**
+ * Do the mapping between DMA channel and PaRAM Set.
+ * Do this for the EDMA3 Controllers which have a register for mapping
+ * DMA Channel to a particular PaRAM Set.
+ */
+ if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)
+ {
+ gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+
+ /* Map Parameter RAM Set Number for specified channelId */
+ gblRegs->DCHMAP[chObj->resId] &= EDMA3_RM_DCH_PARAM_CLR_MASK;
+ gblRegs->DCHMAP[chObj->resId] |= EDMA3_RM_DCH_PARAM_SET_MASK(*pParam);
+ }
+
+ /* Remove any linking */
+ *((&gblRegs->PARAMENTRY[*pParam].OPT)
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFU;
+ }
+ }
+ else
+ {
+ /**
+ * TCC allocation failed, free the previously allocated
+ * PaRAM Set and DMA channel.
+ */
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ resObj.resId = *pParam;
+ EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+
+ /* Reset the book-keeping data structure also. */
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].paRAMId = -1;
+
+ resObj.type = chObj->type;
+ resObj.resId = chObj->resId;
+ EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+ }
+ else
+ {
+ /**
+ * PaRAM Set allocation failed, free the previously allocated
+ * DMA channel also.
+ */
+ resObj.type = chObj->type;
+ resObj.resId = chObj->resId;
+ EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+ }
+
+
+ /* Further resources' allocation for QDMA channel. */
+ if (chObj->type == EDMA3_RM_RES_QDMA_CHANNEL)
+ {
+ /* First allocate a PaRAM Set */
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ /* Use the saved param id now. */
+ resObj.resId = (uint32_t)paRAMId;
+ result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ if (result == EDMA3_RM_SOK)
+ {
+ /**
+ * PaRAM Set allocation succeeded.
+ * Save the PaRAM Set first.
+ */
+ *pParam = resObj.resId;
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = (int32_t)(resObj.resId);
+
+ /* Allocate the TCC now. */
+ resObj.type = EDMA3_RM_RES_TCC;
+ if ((*pTcc) == EDMA3_RM_TCC_ANY)
+ {
+ if (mappedTcc == EDMA3_RM_CH_NO_TCC_MAP)
+ {
+ resObj.resId = EDMA3_RM_RES_ANY;
+ }
+ else
+ {
+ resObj.resId = mappedTcc;
+ }
+ }
+ else
+ {
+ resObj.resId = *pTcc;
+ }
+
+ result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ if (result == EDMA3_RM_SOK)
+ {
+ /* TCC allocation succeeded. Save it first. */
+ *pTcc = resObj.resId;
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].tcc = resObj.resId;
+
+ /**
+ * Check first whether the global registers and the allocated
+ * PaRAM Set can be modified or not. If yes, do the needful.
+ * Else leave this for the user.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /* Set TCC of the allocated Param Set. */
+ gblRegs->PARAMENTRY[*pParam].OPT &= EDMA3_RM_OPT_TCC_CLR_MASK;
+ gblRegs->PARAMENTRY[*pParam].OPT |= EDMA3_RM_OPT_TCC_SET_MASK(*pTcc);
+
+ /* Do the mapping between QDMA channel and PaRAM Set. */
+ /* Map Parameter RAM Set Number for specified channelId */
+ gblRegs->QCHMAP[chObj->resId]
+ &= EDMA3_RM_QCH_PARAM_CLR_MASK;
+ gblRegs->QCHMAP[chObj->resId]
+ |= EDMA3_RM_QCH_PARAM_SET_MASK(*pParam);
+
+ /* Set the Trigger Word */
+ gblRegs->QCHMAP[chObj->resId]
+ &= EDMA3_RM_QCH_TRWORD_CLR_MASK;
+ gblRegs->QCHMAP[chObj->resId]
+ |= EDMA3_RM_QCH_TRWORD_SET_MASK(EDMA3_RM_QDMA_TRIG_DEFAULT);
+
+ /* Remove any linking */
+ *((&gblRegs->PARAMENTRY[*pParam].OPT)
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFU;
+
+ /* Enable the transfer also. */
+ rmInstance->shadowRegs->QEESR = (1U << chObj->resId);
+ }
+ }
+ else
+ {
+ /**
+ * TCC allocation failed, free the previously allocated
+ * PaRAM Set and QDMA channel.
+ */
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ resObj.resId = *pParam;
+ EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+
+ /* Reset the book-keeping data structure also. */
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = -1;
+
+ resObj.type = chObj->type;
+ resObj.resId = chObj->resId;
+ EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+ }
+ else
+ {
+ /**
+ * PaRAM Set allocation failed, free the previously allocated
+ * QDMA channel also.
+ */
+ resObj.type = chObj->type;
+ resObj.resId = chObj->resId;
+ EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+ }
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr,
+ EDMA3_RM_ResDesc *lChObj)
+ {
+ EDMA3_RM_ResDesc *chObj;
+ EDMA3_RM_ResDesc resObj;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ int32_t paRAMId;
+ uint32_t tcc;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t qdmaChId;
+ uint32_t dmaChId;
+ EDMA3_RM_InstanceInitConfig *rmConfig = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((lChObj == NULL) || (hEdmaResMgr == NULL))
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (result == EDMA3_RM_SOK)
+ {
+ chObj = lChObj;
+
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmConfig = rmInstance->initParam.rmInstInitConfig;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ if (rmObj->gblCfgParams.globalRegs == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = rmObj->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+ }
+ }
+ }
+
+
+ if (result == EDMA3_RM_SOK)
+ {
+ switch (chObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL:
+ {
+ /* Save the DMA channel first. */
+ dmaChId = chObj->resId;
+
+ /**
+ * Validate DMA channel id first.
+ * It should be a valid channel id.
+ */
+ if (dmaChId >= EDMA3_MAX_DMA_CH)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+
+ /* It should be owned and allocated by this RM only. */
+ if (result == EDMA3_RM_SOK)
+ {
+ if (((rmConfig->ownDmaChannels[dmaChId/32U])
+ &
+ (~(rmInstance->avlblDmaChannels[dmaChId/32U]))
+ &
+ ((uint32_t)1U << (dmaChId%32U))) != FALSE)
+ {
+ /** Perfectly valid channel id.
+ * Clear some channel specific registers, if it is permitted.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ if (dmaChId < 32U)
+ {
+ if((rmInstance->shadowRegs->SER & ((uint32_t)1U<<dmaChId))!=FALSE)
+ {
+ rmInstance->shadowRegs->SECR = (1U<<dmaChId);
+ }
+ if((globalRegs->EMR & ((uint32_t)1U<<dmaChId))!=FALSE)
+ {
+ globalRegs->EMCR = (1U<<dmaChId);
+ }
+ }
+ else
+ {
+ if((rmInstance->shadowRegs->SERH & ((uint32_t)1U<<(dmaChId-32U)))!=FALSE)
+ {
+ rmInstance->shadowRegs->SECRH = (1U<<(dmaChId-32U));
+ }
+ if((globalRegs->EMRH & ((uint32_t)1U<<(dmaChId-32U)))!=FALSE)
+ {
+ globalRegs->EMCRH = (1U<<(dmaChId-32U));
+ }
+ }
+
+ /* Clear DCHMAP register also. */
+ if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)
+ {
+ globalRegs->DCHMAP[dmaChId] &=
+ EDMA3_RM_DCH_PARAM_CLR_MASK;
+ }
+ }
+
+ /* Free the PaRAM Set Now. */
+ paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].paRAMId;
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ resObj.resId = (uint32_t)paRAMId;
+ result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+ else
+ {
+ /* Channel id has some problem. */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* PaRAM Set Freed */
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].paRAMId = -1;
+
+ /* Free the TCC */
+ tcc = edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].tcc;
+ resObj.type = EDMA3_RM_RES_TCC;
+ resObj.resId = tcc;
+ result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* TCC Freed */
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].tcc = EDMA3_MAX_TCC;
+
+ /**
+ * Try to free the DMA Channel now. DMA Channel should
+ * be freed only in the end because while freeing, DRAE
+ * registers will be RESET.
+ * After that, no shadow region specific DMA channel
+ * register can be modified. So reset that DRAE register
+ * ONLY in the end.
+ */
+ resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+ resObj.resId = dmaChId;
+ result = EDMA3_RM_freeResource(hEdmaResMgr,
+ (EDMA3_RM_ResDesc *)&resObj);
+ }
+ }
+ break;
+
+
+ case EDMA3_RM_RES_QDMA_CHANNEL:
+ {
+ /**
+ * Calculate QDMA Logical Channel Id first.
+ * User has given the actual QDMA channel id.
+ * So we have to convert it to make the logical
+ * QDMA channel id first.
+ */
+ qdmaChId = chObj->resId + edma3_qdma_ch_min_val[edma3Id];
+
+ /**
+ * Validate QDMA channel id first.
+ * It should be a valid channel id.
+ */
+ if (chObj->resId >= EDMA3_MAX_QDMA_CH)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+
+ /* It should be owned and allocated by this RM only. */
+ if (result == EDMA3_RM_SOK)
+ {
+ if (((rmConfig->ownQdmaChannels[0U])
+ &
+ (~(rmInstance->avlblQdmaChannels[0U]))
+ &
+ ((uint32_t)1U << chObj->resId)) != FALSE)
+ {
+ /** Perfectly valid channel id.
+ * Clear some channel specific registers, if
+ * it is permitted.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ rmInstance->shadowRegs->QEECR = (1U<<chObj->resId);
+
+ if((globalRegs->QEMR & ((uint32_t)1U<<chObj->resId))!=FALSE)
+ {
+ globalRegs->QEMCR = (1U<<chObj->resId);
+ }
+
+ /* Unmap PARAM Set Number for specified channelId */
+ globalRegs->QCHMAP[chObj->resId] &=
+ EDMA3_RM_QCH_PARAM_CLR_MASK;
+
+ /* Reset the Trigger Word */
+ globalRegs->QCHMAP[chObj->resId] &=
+ EDMA3_RM_QCH_TRWORD_CLR_MASK;
+ }
+
+ /* Free the PaRAM Set now */
+ paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ resObj.resId = (int32_t)paRAMId;
+ result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+ else
+ {
+ /* Channel id has some problem. */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* PaRAM Set Freed */
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = -1;
+
+ /* Free the TCC */
+ tcc = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].tcc;
+ resObj.type = EDMA3_RM_RES_TCC;
+ resObj.resId = tcc;
+ result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* TCC Freed */
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].tcc = EDMA3_MAX_TCC;
+
+ /**
+ * Try to free the QDMA Channel now. QDMA Channel should
+ * be freed only in the end because while freeing, QRAE
+ * registers will be RESET.
+ * After that, no shadow region specific QDMA channel
+ * register can be modified. So reset that QDRAE register
+ * ONLY in the end.
+ */
+ resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+ resObj.resId = chObj->resId;
+ result = EDMA3_RM_freeResource(hEdmaResMgr,
+ (EDMA3_RM_ResDesc *)&resObj);
+ }
+ }
+ break;
+
+
+ case EDMA3_RM_RES_PARAM_SET:
+ {
+ /* Link Channel */
+ if (chObj->resId < edma3NumPaRAMSets)
+ {
+ resObj.type = EDMA3_RM_RES_PARAM_SET;
+ resObj.resId = chObj->resId;
+
+ result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
+ if (result == EDMA3_RM_SOK)
+ {
+ /* PaRAM Set freed successfully. */
+ uint32_t linkCh = edma3_link_ch_min_val[edma3Id];
+
+ /* Reset the Logical-Link channel */
+ /* Search for the Logical-Link channel first */
+ for (linkCh = edma3_link_ch_min_val[edma3Id];
+ linkCh < edma3_link_ch_max_val[edma3Id];
+ linkCh++)
+ {
+ if (edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId == chObj->resId)
+ {
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId = -1;
+ break;
+ }
+ }
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ default:
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+ }
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
+ uint32_t channelId,
+ uint32_t paRAMId)
+ {
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ volatile EDMA3_CCRL_Regs *gblRegs = NULL;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (hEdmaResMgr == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ if (rmObj->gblCfgParams.globalRegs == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((paRAMId >= rmObj->gblCfgParams.numPaRAMSets)
+ || (channelId >= rmObj->gblCfgParams.numDmaChannels))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ /* DMA channel and PaRAM Set should be previously allocated. */
+ if (result == EDMA3_RM_SOK)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[channelId/32U])
+ &
+ (~(rmInstance->avlblDmaChannels[channelId/32U]))
+ &
+ ((uint32_t)1U << (channelId%32U))) != FALSE)
+ {
+ /* DMA channel allocated, check for the PaRAM Set */
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32U])
+ &
+ (~(rmInstance->avlblPaRAMSets[paRAMId/32U]))
+ &
+ ((uint32_t)1U << (paRAMId%32U))) == FALSE)
+ {
+ /* PaRAM Set NOT allocated, return error */
+ result = EDMA3_RM_E_RES_NOT_ALLOCATED;
+ }
+ }
+ else
+ {
+ /* DMA channel NOT allocated, return error */
+ result = EDMA3_RM_E_RES_NOT_ALLOCATED;
+ }
+ }
+
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* Map the Dma Channel to the PaRAM Set corresponding to paramId */
+ /**
+ * Do this for the EDMA3 Controllers which have a register for mapping
+ * DMA Channel to a particular PaRAM Set. So check
+ * dmaChPaRAMMapExists first.
+ */
+ if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)
+ {
+ /* Map Parameter RAM Set Number for specified channelId */
+ gblRegs->DCHMAP[channelId] &= EDMA3_RM_DCH_PARAM_CLR_MASK;
+ gblRegs->DCHMAP[channelId] |= EDMA3_RM_DCH_PARAM_SET_MASK(paRAMId);
+ }
+ else
+ {
+ /* Feature NOT supported on the current platform, return error. */
+ result = EDMA3_RM_E_FEATURE_UNSUPPORTED;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
+ uint32_t channelId,
+ uint32_t paRAMId,
+ EDMA3_RM_QdmaTrigWord trigWord)
+ {
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ volatile EDMA3_CCRL_Regs *gblRegs = NULL;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((hEdmaResMgr == NULL)
+ || (((int32_t)trigWord < (int32_t)EDMA3_RM_QDMA_TRIG_OPT)
+ || (trigWord > EDMA3_RM_QDMA_TRIG_CCNT)))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ if (rmObj->gblCfgParams.globalRegs == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((paRAMId >= rmObj->gblCfgParams.numPaRAMSets)
+ || (channelId >= rmObj->gblCfgParams.numQdmaChannels))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+ }
+
+ /* QDMA channel and PaRAM Set should be previously allocated. */
+ if (result == EDMA3_RM_SOK)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[channelId/32U])
+ &
+ (~(rmInstance->avlblQdmaChannels[channelId/32U]))
+ &
+ ((uint32_t)1U << (channelId%32U))) != FALSE)
+ {
+ /* QDMA channel allocated, check for the PaRAM Set */
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32U])
+ &
+ (~(rmInstance->avlblPaRAMSets[paRAMId/32U]))
+ &
+ ((uint32_t)1U << (paRAMId%32U))) == FALSE)
+ {
+ /* PaRAM Set NOT allocated, return error */
+ result = EDMA3_RM_E_RES_NOT_ALLOCATED;
+ }
+ }
+ else
+ {
+ /* QDMA channel NOT allocated, return error */
+ result = EDMA3_RM_E_RES_NOT_ALLOCATED;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* Map Parameter RAM Set Number for specified channelId */
+ gblRegs->QCHMAP[channelId] &= EDMA3_RM_QCH_PARAM_CLR_MASK;
+ gblRegs->QCHMAP[channelId] |= EDMA3_RM_QCH_PARAM_SET_MASK(paRAMId);
+
+ /* Set the Trigger Word */
+ gblRegs->QCHMAP[channelId] &= EDMA3_RM_QCH_TRWORD_CLR_MASK;
+ gblRegs->QCHMAP[channelId] |= EDMA3_RM_QCH_TRWORD_SET_MASK(trigWord);
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr,
+ const EDMA3_RM_ResDesc *channelObj,
+ uint32_t tcc,
+ EDMA3_RM_TccCallback tccCb,
+ void *cbData)
+ {
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ uint32_t edma3Id;
+ volatile EDMA3_CCRL_Regs *gblRegs = NULL;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((NULL == hEdmaResMgr) || (NULL == channelObj))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+
+ /* Callback function should NOT be NULL */
+ if (NULL == tccCb)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = rmObj->phyCtrllerInstId;
+ gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ if ((gblRegs == NULL) || (tcc >= rmObj->gblCfgParams.numTccs))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ /* Check whether the callback has already registered. */
+ if (NULL != edma3IntrParams[edma3Id][tcc].tccCb)
+ {
+ result = EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED;
+ }
+ else
+ {
+ /* Store the mapping b/w DMA/QDMA channel and TCC first. */
+ if (channelObj->type == EDMA3_RM_RES_DMA_CHANNEL)
+ {
+ /* DMA channel */
+ if (channelObj->resId < rmObj->gblCfgParams.numDmaChannels)
+ {
+ /* Save the TCC */
+ edma3DmaChTccMapping[edma3Id][channelObj->resId] = tcc;
+ }
+ else
+ {
+ /* Error!!! */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ if (channelObj->type == EDMA3_RM_RES_QDMA_CHANNEL)
+ {
+ /* QDMA channel */
+ if (channelObj->resId < rmObj->gblCfgParams.numQdmaChannels)
+ {
+ /* Save the TCC */
+ edma3QdmaChTccMapping[edma3Id][channelObj->resId] = tcc;
+ }
+ else
+ {
+ /* Error!!! */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ /* Error!!! */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ }
+
+ if (EDMA3_RM_SOK == result)
+ {
+
+ /* Enable the interrupts in IESR/IESRH */
+ if (tcc < 32U)
+ {
+ rmInstance->shadowRegs->IESR = (1UL << tcc);
+ }
+ else
+ {
+ rmInstance->shadowRegs->IESRH = (1UL << (tcc-32U));
+ }
+
+ /* Save the callback functions also */
+ edma3IntrParams[edma3Id][tcc].cbData = cbData;
+ edma3IntrParams[edma3Id][tcc].tccCb = tccCb;
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle hEdmaResMgr,
+ const EDMA3_RM_ResDesc *channelObj)
+ {
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ uint32_t mappedTcc = EDMA3_MAX_TCC;
+ uint32_t edma3Id;
+ volatile EDMA3_CCRL_Regs *gblRegs = NULL;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((NULL == hEdmaResMgr) || (NULL == channelObj))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ edma3Id = rmObj->phyCtrllerInstId;
+ gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ if (gblRegs == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ if (channelObj->type == EDMA3_RM_RES_DMA_CHANNEL)
+ {
+ /* DMA channel */
+ if (channelObj->resId < rmObj->gblCfgParams.numDmaChannels)
+ {
+ /* Save the mapped TCC */
+ mappedTcc = edma3DmaChTccMapping[edma3Id][channelObj->resId];
+
+ /* Remove the mapping now. */
+ edma3DmaChTccMapping[edma3Id][channelObj->resId] = EDMA3_MAX_TCC;
+ }
+ else
+ {
+ /* Error!!! */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ if (channelObj->type == EDMA3_RM_RES_QDMA_CHANNEL)
+ {
+ /* QDMA channel */
+ if (channelObj->resId < rmObj->gblCfgParams.numQdmaChannels)
+ {
+ /* Save the mapped TCC */
+ mappedTcc = edma3QdmaChTccMapping[edma3Id][channelObj->resId];
+
+ /* Remove the mapping now. */
+ edma3QdmaChTccMapping[edma3Id][channelObj->resId] = EDMA3_MAX_TCC;
+ }
+ else
+ {
+ /* Error!!! */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ /* Error!!! */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ }
+
+ if (EDMA3_RM_SOK == result)
+ {
+
+ /* Remove the callback function too */
+ if (mappedTcc < 32U)
+ {
+ rmInstance->shadowRegs->IECR = (1UL << mappedTcc);
+ }
+ else if(mappedTcc < 64U)
+ {
+ rmInstance->shadowRegs->IECRH = (1UL << (mappedTcc-32U));
+ }
+ else
+ {
+ /* To Comply MISRA C warning */
+ result = EDMA3_RM_SOK;
+ }
+
+ if(mappedTcc < EDMA3_MAX_TCC)
+ {
+ edma3IntrParams[edma3Id][mappedTcc].cbData = NULL;
+ edma3IntrParams[edma3Id][mappedTcc].tccCb = NULL;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
+ EDMA3_RM_ResDesc *firstResIdObj,
+ uint32_t numResources)
+ {
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_ResDesc *resObj = NULL;
+ uint32_t resAllocIdx = 0U;
+ uint32_t firstResId;
+ uint32_t lastResId = 0U;
+ uint32_t maxNumResources = 0U;
+ EDMA3_RM_Result semResult = EDMA3_RM_SOK;
+ uint32_t resIdClr = 0x0;
+ uint32_t resIdSet = 0x0;
+ volatile EDMA3_CCRL_Regs *gblRegs = NULL;
+ uint32_t i = 0U;
+ uint32_t position = 0U;
+ uint32_t edma3Id;
+ uint32_t errFlag=0U;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((hEdmaResMgr == NULL) || (firstResIdObj == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ if (EDMA3_RM_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (EDMA3_RM_SOK == result)
+ {
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (EDMA3_RM_SOK == result)
+ {
+ edma3Id = rmObj->phyCtrllerInstId;
+ gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+
+ if (rmInstance->initParam.rmSemHandle == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (EDMA3_RM_SOK == result)
+ {
+ resObj = firstResIdObj;
+ if (resObj != NULL)
+ {
+ firstResId = resObj->resId;
+ }
+
+ switch (resObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL :
+ maxNumResources = rmObj->gblCfgParams.numDmaChannels;
+ break;
+ case EDMA3_RM_RES_QDMA_CHANNEL :
+ maxNumResources = rmObj->gblCfgParams.numQdmaChannels;
+ break;
+ case EDMA3_RM_RES_TCC :
+ maxNumResources = rmObj->gblCfgParams.numTccs;
+ break;
+ case EDMA3_RM_RES_PARAM_SET :
+ maxNumResources = rmObj->gblCfgParams.numPaRAMSets;
+ break;
+ default:
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+ }
+
+
+ if (EDMA3_RM_SOK == result)
+ {
+ /* First resource id (firstResId) can be a valid Resource ID as well as
+ * 'EDMA3_RM_RES_ANY', in case user does not want to
+ * start from a specific resource. For eg, user allocating link channels.
+ */
+ if (firstResId != EDMA3_RM_RES_ANY)
+ {
+ /* User want specific resources. */
+ lastResId = firstResId + numResources;
+
+ if (((firstResId >= maxNumResources) || (firstResId > lastResId))
+ || (lastResId > maxNumResources))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ /* (firstResId == EDMA3_RM_RES_ANY)
+ * So just check whether the number of resources
+ * requested does not cross the limit.
+ */
+ if (numResources > maxNumResources)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* Now try to allocate resources for the first case */
+ if (firstResId != EDMA3_RM_RES_ANY)
+ {
+ /* Request for specific resources */
+
+ /**
+ * Take the instance specific semaphore, to prevent simultaneous
+ * access to the shared resources.
+ */
+ semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,
+ EDMA3_OSSEM_NO_TIMEOUT);
+
+ if (EDMA3_RM_SOK == semResult)
+ {
+ switch (resObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL :
+ {
+ for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
+ {
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resAllocIdx%32U)));
+ resIdSet = (1U << (resAllocIdx%32U));
+
+ /* Check whether it is owned or not */
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resAllocIdx/32U])&(resIdSet)) != FALSE)
+ {
+ /* Now check if specified resource is available presently*/
+ if (((rmInstance->avlblDmaChannels[resAllocIdx/32U])&(resIdSet)) != FALSE)
+ {
+ /*
+ * Mark the specified resource as "Not Available"
+ * for future requests
+ */
+ rmInstance->avlblDmaChannels[resAllocIdx/32U] &= resIdClr;
+
+ if (resAllocIdx < 32U)
+ {
+ rmInstance->shadowRegs->EECR = (1UL << resAllocIdx);
+
+ /**
+ * Enable the DMA channel in the
+ * DRAE registers also.
+ */
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= ((uint32_t)0x1U << resAllocIdx);
+ }
+ else
+ {
+ rmInstance->shadowRegs->EECRH = (1UL << (resAllocIdx - 32U));
+
+ /**
+ * Enable the DMA channel in the
+ * DRAEH registers also.
+ */
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= ((uint32_t)0x1U << (resAllocIdx - 32U));
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ errFlag = 1U;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
+ }
+ }
+
+ break;
+ }
+
+ case EDMA3_RM_RES_QDMA_CHANNEL:
+ {
+ for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
+ {
+ resIdClr = (uint32_t)(~((uint32_t)1U << resAllocIdx));
+ resIdSet = (1U << resAllocIdx);
+
+ /* Check whether it is owned or not */
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U])&(resIdSet))!=FALSE)
+ {
+ /* Now check if specified resource is available presently*/
+ if (((rmInstance->avlblQdmaChannels[0U])&(resIdSet))!=FALSE)
+ {
+ /*
+ * Mark the specified resource as "Not Available"
+ * for future requests
+ */
+ rmInstance->avlblQdmaChannels[0U] &= resIdClr;
+
+ /**
+ * Enable the QDMA channel in the
+ * QRAE register also.
+ */
+ gblRegs->QRAE[rmInstance->initParam.regionId]
+ |= ((uint32_t)0x1U << resAllocIdx);
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ errFlag = 1U;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
+ }
+ }
+
+ break;
+ }
+
+ case EDMA3_RM_RES_TCC:
+ {
+ for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
+ {
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resAllocIdx%32U)));
+ resIdSet = (1U << (resAllocIdx%32U));
+
+ /* Check whether it is owned or not */
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs[resAllocIdx/32U])&(resIdSet))!=FALSE)
+ {
+ /* Now check if specified resource is available presently*/
+ if (((rmInstance->avlblTccs[resAllocIdx/32U])&(resIdSet))!=FALSE)
+ {
+ /*
+ * Mark the specified resource as "Not Available"
+ * for future requests
+ */
+ rmInstance->avlblTccs[resAllocIdx/32U] &= resIdClr;
+
+ /**
+ * If the region id coming from this
+ * RM instance is same as the Master RM
+ * Instance's region id, only then we will be
+ * getting the interrupts on the same side.
+ * So save the TCC in the allocatedTCCs[] array.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ if (resAllocIdx < 32U)
+ {
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << resAllocIdx);
+ }
+ else
+ {
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (resAllocIdx - 32U));
+ }
+ }
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ errFlag = 1U;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
+ }
+ }
+
+ break;
+ }
+
+ case EDMA3_RM_RES_PARAM_SET:
+ {
+ for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
+ {
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resAllocIdx%32U)));
+ resIdSet = (1U << (resAllocIdx%32U));
+
+ /* Check whether it is owned or not */
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resAllocIdx/32U])&(resIdSet))!=FALSE)
+ {
+ /* Now check if specified resource is available presently*/
+ if (((rmInstance->avlblPaRAMSets[resAllocIdx/32U])&(resIdSet))!=FALSE)
+ {
+ /*
+ * Mark the specified resource as "Not Available"
+ * for future requests
+ */
+ rmInstance->avlblPaRAMSets[resAllocIdx/32U] &= resIdClr;
+
+ /**
+ * Also, make the actual PARAM Set NULL, checking the flag
+ * whether it is required or not.
+ */
+ if (TRUE == rmInstance->paramInitRequired)
+ {
+ edma3MemZero((void *)(&gblRegs->PARAMENTRY[resAllocIdx]),
+ sizeof(gblRegs->PARAMENTRY[resAllocIdx]));
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ errFlag = 1U;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
+ }
+ }
+
+ break;
+ }
+
+ default:
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+ }
+
+ /* resource allocation completed, release the semaphore first */
+ semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
+ }
+
+ }
+ else
+ {
+ /* (firstResId == EDMA3_RM_RES_ANY) */
+ /**
+ * Take the instance specific semaphore, to prevent simultaneous
+ * access to the shared resources.
+ */
+ semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,
+ EDMA3_OSSEM_NO_TIMEOUT);
+
+ if (EDMA3_RM_SOK == semResult)
+ {
+ /**
+ * We have to search three different arrays, namely ownedResoures,
+ * avlblResources and resvdResources, to find the 'common' contiguous
+ * resources. For this, take an 'AND' of all three arrays in one single
+ * array and use your algorithm on that array.
+ */
+ switch (resObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL:
+ {
+ /* AND all the arrays to look into */
+ contiguousDmaRes[0U] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0U]
+ & rmInstance->avlblDmaChannels[0U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[0U]))
+ );
+ contiguousDmaRes[1U] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1U]
+ & rmInstance->avlblDmaChannels[1U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[1U]))
+ );
+ }
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL:
+ {
+ /* AND all the arrays to look into */
+ contiguousQdmaRes[0U] = ((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U]
+ & rmInstance->avlblQdmaChannels[0U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[0U]))
+ );
+ }
+ break;
+
+ case EDMA3_RM_RES_TCC:
+ {
+ /* AND all the arrays to look into */
+ contiguousTccRes[0U] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[0U]
+ & rmInstance->avlblTccs[0U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[0U]))
+ );
+ contiguousTccRes[1U] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[1U]
+ & rmInstance->avlblTccs[1U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[1U]))
+ );
+ }
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET:
+ {
+ /* AND all the arrays to look into */
+ for (i = 0U; i < (maxNumResources/32U); ++i)
+ {
+ contiguousParamRes[i] = ((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[i]
+ & rmInstance->avlblPaRAMSets[i])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[i]))
+ );
+ }
+ }
+ break;
+
+ default:
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ break;
+ }
+
+ if (EDMA3_RM_SOK == result)
+ {
+ /**
+ * Try to allocate 'numResources' contiguous resources
+ * of type RES_ANY.
+ */
+ result = allocAnyContigRes (resObj->type, numResources, &position);
+
+ /**
+ * If result != EDMA3_RM_SOK, resource allocation failed.
+ * Else resources successfully allocated.
+ */
+ if (result == EDMA3_RM_SOK)
+ {
+ /* Update the first resource id with the position returned. */
+ resObj->resId = position;
+
+ /*
+ * Do some further changes in the book-keeping
+ * data structures and global registers accordingly.
+ */
+ result = gblChngAllocContigRes(rmInstance, resObj, numResources);
+ }
+ }
+
+ /* resource allocation completed, release the semaphore first */
+ semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
+ }
+ }
+ }
+
+
+ /**
+ * Check the Resource Allocation Result 'result' first. If Resource
+ * Allocation has resulted in an error, return it (having more priority than
+ * semResult. Else, return semResult.
+ */
+ if (EDMA3_RM_SOK == result)
+ {
+ /**
+ * Resource Allocation successful, return semResult for returning
+ * semaphore.
+ */
+ result = semResult;
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
+ EDMA3_RM_ResDesc *firstResIdObj,
+ uint32_t numResources)
+ {
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_ResDesc *resObj;
+ uint32_t resFreeIdx = 0U;
+ uint32_t firstResId;
+ uint32_t lastResId;
+ uint32_t maxNumResources = 0U;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((hEdmaResMgr == NULL) || (firstResIdObj == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ resObj = firstResIdObj;
+ if (resObj != NULL)
+ {
+ firstResId = resObj->resId;
+ lastResId = firstResId + (numResources - 1U);
+ }
+
+ switch (resObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL :
+ maxNumResources = rmObj->gblCfgParams.numDmaChannels;
+ break;
+ case EDMA3_RM_RES_QDMA_CHANNEL :
+ maxNumResources = rmObj->gblCfgParams.numQdmaChannels;
+ break;
+ case EDMA3_RM_RES_TCC :
+ maxNumResources = rmObj->gblCfgParams.numTccs;
+ break;
+ case EDMA3_RM_RES_PARAM_SET :
+ maxNumResources = rmObj->gblCfgParams.numPaRAMSets;
+ break;
+ default:
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ if ((firstResId > lastResId) || (lastResId >= maxNumResources))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ for (resFreeIdx = firstResId; resFreeIdx <= lastResId; ++resFreeIdx)
+ {
+ resObj->resId = resFreeIdx;
+ result = EDMA3_RM_freeResource(rmInstance, resObj);
+
+ if (result != EDMA3_RM_SOK)
+ {
+ break;
+ }
+ }
+ }
+ }
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr,
+ uint32_t regOffset,
+ uint32_t newRegValue)
+ {
+ uint32_t intState;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ volatile uint32_t regPhyAddr = 0x0U;
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((hEdmaResMgr == NULL) || ((regOffset % 4U) != 0))
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+ else
+ {
+ if (rmObj->gblCfgParams.globalRegs != NULL)
+ {
+ /**
+ * Take the instance specific semaphore, to prevent simultaneous
+ * access to the shared resources.
+ */
+ result = edma3OsSemTake(rmInstance->initParam.rmSemHandle,
+ EDMA3_OSSEM_NO_TIMEOUT);
+
+ if (EDMA3_RM_SOK == result)
+ {
+ /* Semaphore taken successfully, modify the registers. */
+ edma3OsProtectEntry (rmObj->phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ &intState);
+ /* Global interrupts disabled, modify the registers. */
+ regPhyAddr = (uint32_t)(rmObj->gblCfgParams.globalRegs) + regOffset;
+
+ *(uint32_t *)regPhyAddr = newRegValue;
+ edma3OsProtectExit (rmObj->phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
+
+ /* Return the semaphore back */
+ result = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
+ }
+ }
+ }
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr,
+ uint32_t regOffset,
+ uint32_t *regValue)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ volatile uint32_t regPhyAddr = 0x0U;
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (((hEdmaResMgr == NULL) || (regValue == NULL))
+ || ((regOffset % 4U) != 0))
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+ else
+ {
+ if (rmObj->gblCfgParams.globalRegs != NULL)
+ {
+ regPhyAddr = (uint32_t)(rmObj->gblCfgParams.globalRegs) + regOffset;
+
+ *regValue = *(uint32_t *)regPhyAddr;
+ }
+ }
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
+ uint32_t tccNo)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
+ uint32_t tccBitMask = 0x0U;
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (hEdmaResMgr == NULL)
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if ((rmObj == NULL) || (rmObj->gblCfgParams.globalRegs == NULL))
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+ else
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (tccNo >= rmObj->gblCfgParams.numTccs)
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+ shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)
+ (&globalRegs->SHADOW[rmInstance->initParam.regionId]);
+
+
+ if (shadowRegs != NULL)
+ {
+ if(tccNo < 32U)
+ {
+ tccBitMask = (1U << tccNo);
+
+ /* Check the status of the IPR[tccNo] bit. */
+ while ((uint32_t)FALSE == (shadowRegs->IPR & tccBitMask))
+ {
+ /* Transfer not yet completed, bit not SET */
+ }
+
+ /**
+ * Bit found SET, transfer is completed,
+ * clear the pending interrupt and return.
+ */
+ shadowRegs->ICR = tccBitMask;
+ }
+ else
+ {
+ tccBitMask = (1U << (tccNo - 32U));
+
+ /* Check the status of the IPRH[tccNo-32] bit. */
+ while ((uint32_t)FALSE == (shadowRegs->IPRH & tccBitMask))
+ {
+ /* Transfer not yet completed, bit not SET */
+ }
+
+ /**
+ * Bit found SET, transfer is completed,
+ * clear the pending interrupt and return.
+ */
+ shadowRegs->ICRH = tccBitMask;
+ }
+ }
+ }
+ }
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
+ uint32_t tccNo,
+ uint16_t *tccStatus)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
+ uint32_t tccBitMask = 0x0U;
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((hEdmaResMgr == NULL) || (tccStatus == NULL))
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if ((rmObj == NULL) || (rmObj->gblCfgParams.globalRegs == NULL))
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+ else
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (tccNo >= rmObj->gblCfgParams.numTccs)
+ {
+ result = (EDMA3_RM_E_INVALID_PARAM);
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+ shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)
+ (&globalRegs->SHADOW[rmInstance->initParam.regionId]);
+
+ /* Reset the tccStatus */
+ *tccStatus = FALSE;
+
+ if (shadowRegs != NULL)
+ {
+ if(tccNo < 32U)
+ {
+ tccBitMask = (1U << tccNo);
+
+ /* Check the status of the IPR[tccNo] bit. */
+ if ((shadowRegs->IPR & tccBitMask) != FALSE)
+ {
+ /* Transfer completed, bit found SET */
+ *tccStatus = TRUE;
+
+ /* Clear the pending interrupt also. */
+ shadowRegs->ICR = tccBitMask;
+ }
+ }
+ else
+ {
+ tccBitMask = (1U << (tccNo - 32U));
+
+ /* Check the status of the IPRH[tccNo-32] bit. */
+ if ((shadowRegs->IPRH & tccBitMask) != FALSE)
+ {
+ /* Transfer completed, bit found SET */
+ *tccStatus = TRUE;
+
+ /* Clear the pending interrupt also. */
+ shadowRegs->ICRH = tccBitMask;
+ }
+ }
+ }
+ }
+ }
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
+ const EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_PaRAMRegs *newPaRAM)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ int32_t paRAMId = 0;
+ uint32_t qdmaChId = 0U;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (hEdmaResMgr == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+
+ if ((lChObj == NULL) || (newPaRAM == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (result == EDMA3_RM_SOK)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ if (rmObj->gblCfgParams.globalRegs == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ edma3Id = rmObj->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+
+ switch (lChObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL:
+ {
+ if (lChObj->resId <= edma3_dma_ch_max_val[edma3Id])
+ {
+ paRAMId = edma3RmChBoundRes[edma3Id][lChObj->resId].paRAMId;
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL:
+ {
+ if (lChObj->resId < EDMA3_MAX_QDMA_CH)
+ {
+ qdmaChId = lChObj->resId + edma3_qdma_ch_min_val[edma3Id];
+ paRAMId = edma3RmChBoundRes[edma3Id][qdmaChId].paRAMId;
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET:
+ {
+ if (lChObj->resId < edma3NumPaRAMSets)
+ {
+ /**
+ * User has passed the actual param set value here.
+ * Use this value only
+ */
+ paRAMId = (int32_t)(lChObj->resId);
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ default:
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+ }
+ }
+
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* Check the param id first. */
+ if ((paRAMId != -1) && ((uint32_t)paRAMId < edma3NumPaRAMSets))
+ {
+ /* Set the PaRAM Set now. */
+ edma3ParamCpy ((volatile void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)),
+ (const void *)newPaRAM);
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
+ const EDMA3_RM_ResDesc *lChObj,
+ EDMA3_RM_PaRAMRegs *currPaRAM)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ int32_t paRAMId = 0;
+ uint32_t qdmaChId = 0U;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (hEdmaResMgr == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+
+ if ((lChObj == NULL) || (currPaRAM == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (result == EDMA3_RM_SOK)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ if (rmObj->gblCfgParams.globalRegs == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ edma3Id = rmObj->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+
+ switch (lChObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL:
+ {
+ if (lChObj->resId <= edma3_dma_ch_max_val[edma3Id])
+ {
+ paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][lChObj->resId].paRAMId;
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL:
+ {
+ if (lChObj->resId < EDMA3_MAX_QDMA_CH)
+ {
+ qdmaChId = lChObj->resId + edma3_qdma_ch_min_val[edma3Id];
+ paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET:
+ {
+ if (lChObj->resId < edma3NumPaRAMSets)
+ {
+ /**
+ * User has passed the actual param set value here.
+ * Use this value only
+ */
+ paRAMId = (int32_t)(lChObj->resId);
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ default:
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+ }
+ }
+
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* Check the param id first. */
+ if ((paRAMId != -1) && ((uint32_t)paRAMId < edma3NumPaRAMSets))
+ {
+ /* Get the PaRAM Set now. */
+ edma3ParamCpy ((void *)currPaRAM ,
+ (const volatile void *)(&(globalRegs->PARAMENTRY [paRAMId].OPT)));
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
+ const EDMA3_RM_ResDesc *lChObj,
+ uint32_t *paramPhyAddr)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ int32_t paRAMId = 0;
+ uint32_t qdmaChId = 0U;
+ volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+ uint32_t edma3Id;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (hEdmaResMgr == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+
+ if ((lChObj == NULL) || (paramPhyAddr == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ else
+ {
+ if (rmObj->gblCfgParams.globalRegs == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ edma3Id = rmObj->phyCtrllerInstId;
+ globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+
+ switch (lChObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL:
+ {
+ if (lChObj->resId <= edma3_dma_ch_max_val[edma3Id])
+ {
+ paRAMId = edma3RmChBoundRes[edma3Id][lChObj->resId].paRAMId;
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL:
+ {
+ if (lChObj->resId < EDMA3_MAX_QDMA_CH)
+ {
+ qdmaChId = lChObj->resId + edma3_qdma_ch_min_val[edma3Id];
+ paRAMId = edma3RmChBoundRes[edma3Id][qdmaChId].paRAMId;
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET:
+ {
+ if (lChObj->resId < edma3NumPaRAMSets)
+ {
+ /**
+ * User has passed the actual param set value here.
+ * Use this value only
+ */
+ paRAMId = (int32_t)(lChObj->resId);
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ break;
+
+ default:
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* Check the param id first. */
+ if ((paRAMId != -1) && (paRAMId < (int32_t)edma3NumPaRAMSets))
+ {
+ /* Get the PaRAM Set Address now. */
+ *paramPhyAddr = (uint32_t)(&(globalRegs->PARAMENTRY [paRAMId].OPT));
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr,
+ EDMA3_RM_Cntrlr_PhyAddr controllerId,
+ uint32_t *phyAddress)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((hEdmaResMgr == NULL) || (phyAddress == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ /* Verify the 'controllerId' */
+ if (((int32_t)controllerId < (int32_t)((EDMA3_RM_Cntrlr_PhyAddr)(EDMA3_RM_CC_PHY_ADDR)))
+ || (controllerId > (EDMA3_RM_Cntrlr_PhyAddr)(rmObj->gblCfgParams.numTcs)))
+ {
+ /* Invalid controllerId */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ if (controllerId == EDMA3_RM_CC_PHY_ADDR)
+ {
+ /* EDMA3 Channel Controller Address */
+ *phyAddress = (uint32_t)(rmObj->gblCfgParams.globalRegs);
+ }
+ else
+ {
+ /**
+ * Since the TCs enum start from 1, and TCs start from 0,
+ * subtract 1 from the enum to get the actual address.
+ */
+ *phyAddress = (uint32_t)(rmObj->gblCfgParams.tcRegs[controllerId-1U]);
+ }
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_getGblConfigParams (
+ uint32_t phyCtrllerInstId,
+ EDMA3_RM_GblConfigParams *gblCfgParams)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES)
+ || (NULL == gblCfgParams))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ if (EDMA3_RM_SOK == result)
+ {
+ /* Return the previously saved global config information for the EDMA3 HW */
+ edma3MemCpy((void *)(gblCfgParams),
+ (const void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams),
+ sizeof (EDMA3_RM_GblConfigParams));
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (
+ EDMA3_RM_Handle hEdmaResMgr,
+ EDMA3_RM_InstanceInitConfig *instanceInitConfig)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ uint32_t resMgrIdx = 0U;
+ uint32_t hwId;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((hEdmaResMgr == NULL) || (instanceInitConfig == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ hwId = rmObj->phyCtrllerInstId;
+
+ for (resMgrIdx = 0U; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)
+ {
+ if (rmInstance == ((EDMA3_RM_Instance *)(ptrRMIArray) +
+ (hwId*EDMA3_MAX_RM_INSTANCES) +
+ resMgrIdx))
+ {
+ /* RM Id found. Return the specific config info to the user. */
+ edma3MemCpy((void *)(instanceInitConfig),
+ (const void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) +
+ (hwId*EDMA3_MAX_RM_INSTANCES) +
+ resMgrIdx),
+ sizeof (EDMA3_RM_InstanceInitConfig));
+ break;
+ }
+ }
+
+ if (EDMA3_MAX_RM_INSTANCES == resMgrIdx)
+ {
+ /* RM Id not found, report error... */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+ }
+
+EDMA3_RM_Result EDMA3_RM_Ioctl(
+ EDMA3_RM_Handle hEdmaResMgr,
+ EDMA3_RM_IoctlCmd cmd,
+ void *cmdArg,
+ void *param
+ )
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ uint32_t paramInitRequired = 0xFFU;
+ uint32_t regModificationRequired = 0xFFU;
+ uint32_t *ret_val = NULL;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (hEdmaResMgr == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+
+ if ((cmd <= EDMA3_RM_IOCTL_MIN_IOCTL)
+ || (cmd >= EDMA3_RM_IOCTL_MAX_IOCTL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ if (result == EDMA3_RM_SOK)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (rmInstance == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ switch (cmd)
+ {
+ case EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION:
+ {
+ paramInitRequired = (uint32_t)cmdArg;
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((paramInitRequired != 0U)
+ && (paramInitRequired != 1U))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ /* Set/Reset the flag which is being used to do the PaRAM clearing. */
+ rmInstance->paramInitRequired = paramInitRequired;
+ }
+
+ break;
+ }
+
+ case EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION:
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (NULL == cmdArg)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ ret_val = (uint32_t *)cmdArg;
+
+ /* Get the flag which is being used to do the PaRAM clearing. */
+ *ret_val = rmInstance->paramInitRequired;
+ }
+
+ break;
+ }
+
+ case EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION:
+ {
+ regModificationRequired = (uint32_t)cmdArg;
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if ((regModificationRequired != 0U)
+ && (regModificationRequired != 1U))
+ {
+ /* All other values are invalid. */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ /**
+ * Set/Reset the flag which is being used to do the global
+ * registers and PaRAM modification.
+ */
+ rmInstance->regModificationRequired = regModificationRequired;
+ }
+
+ break;
+ }
+
+ case EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION:
+ {
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
+ if (NULL == cmdArg)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_RM_SOK == result)
+ {
+ ret_val = (uint32_t *)cmdArg;
+
+ /**
+ * Get the flag which is being used to do the global
+ * registers and PaRAM modification.
+ */
+ *ret_val = rmInstance->regModificationRequired;
+ }
+
+ break;
+ }
+
+ default:
+ {
+ /* Hey dude! you passed invalid IOCTL cmd */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+
+ }
+ }
+
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+ EDMA3_DVT_dCOUNTER,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ return result;
+
+ }
+
+/**
+ * edma3ComplHandler
+ * \brief Interrupt handler for successful transfer completion.
+ *
+ * \note This function first disables its own interrupt to make it non-
+ * entrant. Later, after calling all the callback functions, it
+ * re-enables its own interrupt.
+ *
+ * \return None.
+ */
+static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
+ {
+ uint32_t Cnt;
+ volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
+ volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
+ volatile uint32_t pendingIrqs;
+ volatile uint32_t isIPR = 0;
+
+ uint32_t indexl;
+ uint32_t indexh;
+ uint32_t edma3Id;
+ uint32_t numTCCs;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eINT_START,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ assert (NULL != rmObj);
+
+ edma3Id = rmObj->phyCtrllerInstId;
+ numTCCs = rmObj->gblCfgParams.numTccs;
+ ptrEdmaccRegs =
+ (volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs;
+ if (ptrEdmaccRegs != NULL)
+ {
+ shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)
+ (&ptrEdmaccRegs->SHADOW[edma3RegionId]);
+ }
+
+ Cnt = 0U;
+ pendingIrqs = 0U;
+ indexl = 1U;
+ indexh = 1U;
+
+ if (numTCCs > 32U)
+ {
+ isIPR = shadowRegs->IPR | shadowRegs->IPRH;
+ }
+ else
+ {
+ isIPR = shadowRegs->IPR;
+ }
+ if(isIPR)
+ {
+ /**
+ * Since an interrupt has found, we have to make sure that this
+ * interrupt (TCC) belongs to the TCCs allocated by us only.
+ * It might happen that someone else, who is using EDMA3 also,
+ * is the owner of this interrupt channel i.e. the TCC.
+ * For this, use the allocatedTCCs[], to check which all interrupt
+ * channels are owned by the EDMA3 RM Instances.
+ */
+
+ edma3OsProtectEntry (edma3Id,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
+ NULL);
+
+ /* Loop for EDMA3_RM_COMPL_HANDLER_RETRY_COUNT number of time,
+ breaks when no pending interrupt is found */
+ while ((Cnt < EDMA3_RM_COMPL_HANDLER_RETRY_COUNT)
+ && ((indexl != 0U) || (indexh != 0U)))
+ {
+ indexl = 0U;
+ pendingIrqs = shadowRegs->IPR;
+
+ /**
+ * Choose interrupts coming from our allocated TCCs
+ * and MASK remaining ones.
+ */
+ pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][0U]);
+
+ while (pendingIrqs)
+ {
+ /*Process all the pending interrupts*/
+ if((pendingIrqs & 1U) == TRUE)
+ {
+ /**
+ * If the user has not given any callback function
+ * while requesting the TCC, its TCC specific bit
+ * in the IPR register will NOT be cleared.
+ */
+ if(edma3IntrParams[edma3Id][indexl].tccCb != NULL)
+ {
+ /* here write to ICR to clear the corresponding IPR bits*/
+ shadowRegs->ICR = (1U << indexl);
+
+ edma3IntrParams[edma3Id][indexl].tccCb (indexl,
+ EDMA3_RM_XFER_COMPLETE,
+ edma3IntrParams[edma3Id][indexl].cbData);
+ }
+ }
+ ++indexl;
+ pendingIrqs >>= 1U;
+ }
+
+ if(numTCCs > 32U)
+ {
+ indexh = 0U;
+ pendingIrqs = shadowRegs->IPRH;
+
+ /**
+ * Choose interrupts coming from our allocated TCCs
+ * and MASK remaining ones.
+ */
+ pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][1U]);
+
+ while (pendingIrqs)
+ {
+ /*Process all the pending interrupts*/
+ if((pendingIrqs & 1U)==TRUE)
+ {
+ /**
+ * If the user has not given any callback function
+ * while requesting the TCC, its TCC specific bit
+ * in the IPRH register will NOT be cleared.
+ */
+ if(edma3IntrParams[edma3Id][32U+indexh].tccCb!=NULL)
+ {
+ /* here write to ICR to clear the corresponding IPR bits*/
+ shadowRegs->ICRH = (1U << indexh);
+
+ edma3IntrParams[edma3Id][32U+indexh].tccCb(32U+indexh,
+ EDMA3_RM_XFER_COMPLETE,
+ edma3IntrParams[edma3Id][32U+indexh].cbData);
+ }
+ }
+ ++indexh;
+ pendingIrqs >>= 1U;
+ }
+ }
+
+ Cnt++;
+ }
+
+ indexl = (shadowRegs->IPR & allocatedTCCs[edma3Id][0U]);
+ if (numTCCs > 32U)
+ {
+ indexh = (shadowRegs->IPRH & allocatedTCCs[edma3Id][1U]);
+ }
+
+ if((indexl !=0 ) || (indexh !=0 ))
+ {
+ shadowRegs->IEVAL=0x1U;
+ }
+
+ edma3OsProtectExit (rmObj->phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
+ 0);
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+ EDMA3_DVT_DESC(EDMA3_DVT_eINT_END,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+ }
+
+
+void lisrEdma3ComplHandler0(uint32_t edma3InstanceId)
+ {
+ /* Invoke Completion Handler ISR */
+ edma3ComplHandler(&resMgrObj[edma3InstanceId]);
+ }
+
+
+/**
+ * \brief Interrupt handler for Channel Controller Error.
+ *
+ * \note This function first disables its own interrupt to make it non-
+ * entrant. Later, after calling all the callback functions, it
+ * re-enables its own interrupt.
+ *
+ * \return None.
+ */
+static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
+ {
+ uint32_t Cnt = 0U;
+ uint32_t resMgrInstIdx = 0U;
+ volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
+ volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
+ volatile uint32_t pendingIrqs = 0;
+ uint32_t index;
+ uint32_t evtqueNum;
+ EDMA3_RM_Instance *rm_instance = NULL;
+ uint32_t edma3Id;
+ uint32_t num_rm_instances_opened;
+ EDMA3_RM_Instance *rmInstance = NULL;
+ uint32_t ownedDmaError = 0;
+ uint32_t ownedDmaHError = 0;
+ uint32_t ownedQdmaError = 0;
+ uint32_t numTCCs;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_CCERR",
+ EDMA3_DVT_DESC(EDMA3_DVT_eINT_START,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ assert (rmObj != NULL);
+
+ edma3Id = rmObj->phyCtrllerInstId;
+ ptrEdmaccRegs = (volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs;
+ numTCCs = rmObj->gblCfgParams.numTccs;
+ if (ptrEdmaccRegs != NULL)
+ {
+ shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)&ptrEdmaccRegs->SHADOW[edma3RegionId];
+ rmInstance = ((EDMA3_RM_Instance *)(ptrRMIArray)
+ + (edma3Id*EDMA3_MAX_RM_INSTANCES)
+ + edma3RegionId);
+
+ if((ptrEdmaccRegs->EMR != 0 )
+ || (ptrEdmaccRegs->QEMR != 0)
+ || (ptrEdmaccRegs->CCERR != 0))
+ {
+ pendingIrqs = 1U;
+ }
+ if (numTCCs > 32U)
+ {
+ if((pendingIrqs != 0) || (ptrEdmaccRegs->EMRH != 0))
+ {
+ pendingIrqs = 1U;
+ }
+ }
+ index = 1U;
+
+ if(pendingIrqs)
+ {
+ edma3OsProtectEntry (edma3Id,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
+ NULL);
+
+ /* Loop for EDMA3_RM_CCERR_HANDLER_RETRY_COUNT number of time,
+ breaks when no pending interrupt is found */
+ while ((Cnt < EDMA3_RM_CCERR_HANDLER_RETRY_COUNT)
+ && (index != 0U))
+ {
+ index = 0U;
+ pendingIrqs = ptrEdmaccRegs->EMR;
+
+ while (pendingIrqs)
+ {
+ /*Process all the pending interrupts*/
+ if((pendingIrqs & 1U)==TRUE)
+ {
+ uint32_t mappedTcc = 0U;
+
+ /**
+ * Using the 'index' value (basically the DMA
+ * channel), fetch the corresponding TCC
+ * value, mapped to this DMA channel.
+ */
+ mappedTcc = edma3DmaChTccMapping[edma3Id][index];
+
+ /**
+ * Ensure that the mapped tcc is valid and the call
+ * back is not NULL
+ */
+ if (mappedTcc < EDMA3_MAX_TCC)
+ {
+ /**
+ * TCC owned and allocated by RM.
+ * Write to EMCR to clear the corresponding EMR bits.
+ */
+ ptrEdmaccRegs->EMCR = (1U<<index);
+ /*Clear any SER*/
+ shadowRegs->SECR = (1U<<index);
+
+ /* Call the callback function if registered earlier. */
+ if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
+ {
+ edma3IntrParams[edma3Id][mappedTcc].tccCb (
+ mappedTcc,
+ EDMA3_RM_E_CC_DMA_EVT_MISS,
+ edma3IntrParams[edma3Id][mappedTcc].cbData
+ );
+ }
+ }
+ else
+ {
+ /**
+ * DMA channel not owned by the RM instance.
+ * Check the global error interrupt clearing option.
+ * If it is TRUE, clear the error interupt else leave
+ * it like that.
+ */
+#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)
+ /* here write to EMCR to clear the corresponding EMR bits. */
+ ptrEdmaccRegs->EMCR = (1U<<index);
+ /*Clear any SER*/
+ ptrEdmaccRegs->SECR = (1U<<index);
+#endif
+ }
+ }
+ ++index;
+ pendingIrqs >>= 1U;
+ }
+
+ if(numTCCs > 32U)
+ {
+ index = 0U;
+ pendingIrqs = ptrEdmaccRegs->EMRH;
+ while (pendingIrqs)
+ {
+ /*Process all the pending interrupts*/
+ if((pendingIrqs & 1U)==TRUE)
+ {
+ uint32_t mappedTcc = 0U;
+
+ /**
+ * Using the 'index' value (basically the DMA
+ * channel), fetch the corresponding TCC
+ * value, mapped to this DMA channel.
+ */
+ mappedTcc = edma3DmaChTccMapping[edma3Id][32U+index];
+
+ /**
+ * Ensure that the mapped tcc is valid and the call
+ * back is not NULL
+ */
+ if (mappedTcc < EDMA3_MAX_TCC)
+ {
+ /**
+ * TCC owned and allocated by RM.
+ * Write to EMCR to clear the corresponding EMR bits.
+ */
+ ptrEdmaccRegs->EMCRH = (1U<<index);
+ /*Clear any SERH*/
+ shadowRegs->SECRH = (1U<<index);
+
+ /* Call the callback function if registered earlier. */
+ if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
+ {
+ edma3IntrParams[edma3Id][mappedTcc].tccCb (
+ mappedTcc,
+ EDMA3_RM_E_CC_DMA_EVT_MISS,
+ edma3IntrParams[edma3Id][mappedTcc].cbData
+ );
+ }
+ }
+ else
+ {
+ /**
+ * DMA channel not owned by the RM instance.
+ * Check the global error interrupt clearing option.
+ * If it is TRUE, clear the error interupt else leave
+ * it like that.
+ */
+#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)
+ /**
+ * TCC NOT owned by RM.
+ * Write to EMCRH to clear the corresponding EMRH bits.
+ */
+ ptrEdmaccRegs->EMCRH = (1U<<index);
+ /*Clear any SERH*/
+ shadowRegs->SECRH = (1U<<index);
+#endif
+ }
+ }
+ ++index;
+ pendingIrqs >>= 1U;
+ }
+ }
+
+ index = 0U;
+ pendingIrqs = ptrEdmaccRegs->QEMR;
+ while (pendingIrqs)
+ {
+ /*Process all the pending interrupts*/
+ if((pendingIrqs & 1U)==TRUE)
+ {
+ uint32_t mappedTcc = 0U;
+
+ /**
+ * Using the 'index' value (basically the QDMA
+ * channel), fetch the corresponding TCC
+ * value, mapped to this QDMA channel.
+ */
+ mappedTcc = edma3QdmaChTccMapping[edma3Id][index];
+
+ if (mappedTcc < EDMA3_MAX_TCC)
+ {
+ /* here write to QEMCR to clear the corresponding QEMR bits*/
+ ptrEdmaccRegs->QEMCR = (1U<<index);
+ /*Clear any QSER*/
+ shadowRegs->QSECR = (1U<<index);
+
+ if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
+ {
+ edma3IntrParams[edma3Id][mappedTcc].tccCb (
+ mappedTcc,
+ EDMA3_RM_E_CC_QDMA_EVT_MISS,
+ edma3IntrParams[edma3Id][mappedTcc].cbData
+ );
+ }
+ }
+ else
+ {
+ /**
+ * QDMA channel not owned by the RM instance.
+ * Check the global error interrupt clearing option.
+ * If it is TRUE, clear the error interupt else leave
+ * the ISR.
+ */
+#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)
+ /* here write to QEMCR to clear the corresponding QEMR bits*/
+ ptrEdmaccRegs->QEMCR = (1U<<index);
+
+ /*Clear any QSER*/
+ ptrEdmaccRegs->QSECR = (1U<<index);
+#endif
+ }
+ }
+ ++index;
+ pendingIrqs >>= 1U;
+ }
+
+ index = 0U;
+ pendingIrqs = ptrEdmaccRegs->CCERR;
+ if (pendingIrqs!=0)
+ {
+ /* Process all the pending CC error interrupts. */
+
+ /* Queue threshold error for different event queues.*/
+ for (evtqueNum = 0U; evtqueNum < rmObj->gblCfgParams.numEvtQueue; evtqueNum++)
+ {
+ if((pendingIrqs & ((uint32_t)1U << evtqueNum)) != 0)
+ {
+ /**
+ * Queue threshold error for queue 'evtqueNum' raised.
+ * Inform all the RM instances working on this region
+ * about the error by calling their global callback functions.
+ */
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
+ {
+ /* Check whether the RM instance opened working on this region */
+ rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+ if (NULL != rm_instance)
+ {
+ if (rm_instance->initParam.regionId == edma3RegionId)
+ {
+ /* Region id matches, call the callback function */
+ if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)
+ {
+ rm_instance->initParam.gblerrCbParams.gblerrCb(
+ EDMA3_RM_E_CC_QUE_THRES_EXCEED,
+ evtqueNum,
+ rm_instance->initParam.gblerrCbParams.gblerrData);
+ }
+ }
+ }
+
+ ++resMgrInstIdx;
+ /* Check next opened instance */
+ }
+
+ /* Clear the error interrupt. */
+ ptrEdmaccRegs->CCERRCLR = (1U << evtqueNum);
+ }
+ }
+
+
+ /* Transfer completion code error. */
+ if ((pendingIrqs & ((uint32_t)1 << EDMA3_CCRL_CCERR_TCCERR_SHIFT))!=0)
+ {
+ /**
+ * Transfer completion code error raised.
+ * Inform all the RM instances working on this region
+ * about the error by calling their global callback functions.
+ */
+
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
+ {
+ /* Check whether the RM instance opened working on this region */
+ rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+ if (NULL != rm_instance)
+ {
+ if (rm_instance->initParam.regionId == edma3RegionId)
+ {
+ /* Region id matches, call the callback function */
+ if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)
+ {
+ rm_instance->initParam.gblerrCbParams.gblerrCb(
+ EDMA3_RM_E_CC_TCC,
+ 0,
+ rm_instance->initParam.gblerrCbParams.gblerrData);
+ }
+ }
+ }
+
+ ++resMgrInstIdx;
+ /* Check next opened instance */
+ }
+
+ ptrEdmaccRegs->CCERRCLR = ((uint32_t)1<<EDMA3_CCRL_CCERR_TCCERR_SHIFT);
+ }
+
+ ++index;
+ }
+
+ Cnt++;
+ }
+
+
+ /**
+ * Read the error registers again. If any interrupt is pending,
+ * write the EEVAL register.
+ * Moreover, according to the global error interrupt clearing
+ * option, check either error bits associated with all the
+ * DMA/QDMA channels (option is SET) OR check error bits
+ * associated with owned DMA/QDMA channels.
+ */
+#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)
+ /* To remove warning. */
+ rmInstance = rmInstance;
+
+ /* Check all the error bits. */
+ ownedDmaError = ptrEdmaccRegs->EMR;
+ if (numTCCs > 32U)
+ {
+ ownedDmaHError = ptrEdmaccRegs->EMRH;
+ }
+ ownedQdmaError = ptrEdmaccRegs->QEMR;
+#else
+ /* Check ONLY owned error bits. */
+ ownedDmaError = (ptrEdmaccRegs->EMR & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0U]);
+ if (numTCCs > 32)
+ ownedDmaHError = (ptrEdmaccRegs->EMRH & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1U]);
+ ownedQdmaError = (ptrEdmaccRegs->QEMR & rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U]);
+#endif
+
+ if (((ownedDmaError != 0 ) || (ownedDmaHError != 0 ))
+ || ((ownedQdmaError != 0) || (ptrEdmaccRegs->CCERR != 0)))
+ {
+ ptrEdmaccRegs->EEVAL=0x1U;
+ }
+
+ edma3OsProtectExit (rmObj->phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
+ 0);
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_CCERR",
+ EDMA3_DVT_DESC(EDMA3_DVT_eINT_END,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+ }
+
+void lisrEdma3CCErrHandler0(uint32_t edma3InstanceId)
+ {
+ /* Invoke CC Error Handler ISR */
+ edma3CCErrHandler(&resMgrObj[edma3InstanceId]);
+ }
+
+
+
+/**
+ * \brief Interrupt handler for Transfer Controller Error.
+ *
+ * \note This function first disables its own interrupt to make it non-
+ * entrant. Later, after calling all the callback functions, it
+ * re-enables its own interrupt.
+ *
+ * \return None.
+ */
+static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, uint32_t tcNum)
+ {
+ volatile EDMA3_TCRL_Regs *tcRegs = NULL;
+ uint32_t tcMemErrRdWr = 0U;
+ uint32_t resMgrInstIdx = 0U;
+ EDMA3_RM_Instance *rm_instance = NULL;
+ uint32_t edma3Id;
+ uint32_t num_rm_instances_opened;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_TCERR",
+ EDMA3_DVT_DESC(EDMA3_DVT_eINT_START,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+ assert ((rmObj != NULL) && (tcNum < rmObj->gblCfgParams.numTcs));
+
+ if (rmObj->gblCfgParams.tcRegs[tcNum] != NULL)
+ {
+ tcRegs = (volatile EDMA3_TCRL_Regs *)(rmObj->gblCfgParams.tcRegs[tcNum]);
+ edma3Id = rmObj->phyCtrllerInstId;
+ }
+
+ if (tcRegs != NULL)
+ {
+ if(tcRegs->ERRSTAT != 0)
+ {
+ edma3OsProtectEntry (rmObj->phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
+ &tcNum);
+
+ if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT))!= 0)
+ {
+ /* Bus error event. */
+ /**
+ * EDMA3TC has detected an error at source or destination
+ * address. Error information can be read from the error
+ * details register (ERRDET).
+ */
+ tcMemErrRdWr = tcRegs->ERRDET & ((uint32_t)EDMA3_TCRL_ERRDET_STAT_MASK);
+ if ((tcMemErrRdWr > 0U) && (tcMemErrRdWr < 8U))
+ {
+ /**
+ * Inform all the RM instances working on this region
+ * about the error by calling their global callback functions.
+ */
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
+ {
+ /* Check whether the RM instance opened working on this region */
+ rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+ if (NULL != rm_instance)
+ {
+ if (rm_instance->initParam.regionId == edma3RegionId)
+ {
+ /* Region id matches, call the callback function */
+ if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)
+ {
+ rm_instance->initParam.gblerrCbParams.gblerrCb(
+ EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR,
+ tcNum,
+ rm_instance->initParam.gblerrCbParams.gblerrData);
+ }
+ }
+ }
+
+ ++resMgrInstIdx;
+ /* Check next opened instance */
+ }
+ }
+ else
+ {
+ if ((tcMemErrRdWr >= 8U) && (tcMemErrRdWr <= 0xFU))
+ {
+ /**
+ * Inform all the RM instances working on this region
+ * about the error by calling their global callback functions.
+ */
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
+ {
+ /* Check whether the RM instance opened working on this region */
+ rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+ if (NULL != rm_instance)
+ {
+ if (rm_instance->initParam.regionId == edma3RegionId)
+ {
+ /* Region id matches, call the callback function */
+ if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)
+ {
+ rm_instance->initParam.gblerrCbParams.gblerrCb(
+ EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR,
+ tcNum,
+ rm_instance->initParam.gblerrCbParams.gblerrData);
+ }
+ }
+ }
+
+ ++resMgrInstIdx;
+ /* Check next opened instance */
+ }
+ }
+ }
+ tcRegs->ERRCLR = ((uint32_t)1<<EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT);
+ }
+ else
+ {
+ /* Transfer request (TR) error event. */
+ if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_TRERR_SHIFT))!= 0)
+ {
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
+ {
+ /* Check whether the RM instance opened working on this region */
+ rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+ if (NULL != rm_instance)
+ {
+ if (rm_instance->initParam.regionId == edma3RegionId)
+ {
+ /* Region id matches, call the callback function */
+ if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)
+ {
+ rm_instance->initParam.gblerrCbParams.gblerrCb(
+ EDMA3_RM_E_TC_TR_ERROR,
+ tcNum,
+ rm_instance->initParam.gblerrCbParams.gblerrData);
+ }
+ }
+ }
+
+ ++resMgrInstIdx;
+ /* Check next opened instance */
+ }
+
+ tcRegs->ERRCLR = ((uint32_t)1<<EDMA3_TCRL_ERRSTAT_TRERR_SHIFT);
+ }
+ else
+ {
+ if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT))!= 0)
+ {
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
+ {
+ /* Check whether the RM instance opened working on this region */
+ rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+ if (NULL != rm_instance)
+ {
+ if (rm_instance->initParam.regionId == edma3RegionId)
+ {
+ /* Region id matches, call the callback function */
+ if (rm_instance->initParam.gblerrCbParams.gblerrCb != NULL)
+ {
+ rm_instance->initParam.gblerrCbParams.gblerrCb(
+ EDMA3_RM_E_TC_INVALID_ADDR,
+ tcNum,
+ rm_instance->initParam.gblerrCbParams.gblerrData);
+ }
+ }
+ }
+
+ ++resMgrInstIdx;
+ /* Check next opened instance */
+ }
+
+ tcRegs->ERRCLR = ((uint32_t)1<<EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT);
+ }
+ }
+ }
+
+ edma3OsProtectExit (rmObj->phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
+ tcNum);
+ }
+ }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+ EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_TCERR",
+ EDMA3_DVT_DESC(EDMA3_DVT_eINT_END,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE,
+ EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+ }
+
+
+
+/*
+ * ======== lisrEdma3TC0ErrHandler0 ========
+ * EDMA3 instance 0 TC0 Error Interrupt Service Routine
+ */
+void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId)
+ {
+ /* Invoke Error Handler ISR for TC0*/
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)0U);
+ }
+
+
+/*
+ * ======== lisrEdma3TC1ErrHandler0 ========
+ * EDMA3 instance 0 TC1 Error Interrupt Service Routine
+ */
+void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId)
+ {
+ /* Invoke Error Handler ISR for TC1*/
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)1U);
+ }
+
+/*
+ * ======== lisrEdma3TC2ErrHandler0 ========
+ * EDMA3 instance 0 TC2 Error Interrupt Service Routine
+ */
+void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId)
+ {
+ /* Invoke Error Handler ISR for TC2*/
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)2U);
+ }
+
+/*
+ * ======== lisrEdma3TC3ErrHandler0 ========
+ * EDMA3 instance 0 TC3 Error Interrupt Service Routine
+ */
+void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId)
+ {
+ /* Invoke Error Handler ISR for TC3*/
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)3U);
+ }
+
+/*
+ * ======== lisrEdma3TC4ErrHandler0 ========
+ * EDMA3 instance 0 TC4 Error Interrupt Service Routine
+ */
+void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId)
+ {
+ /* Invoke Error Handler ISR for TC4*/
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)4U);
+ }
+
+
+/*
+ * ======== lisrEdma3TC5ErrHandler0 ========
+ * EDMA3 instance 0 TC5 Error Interrupt Service Routine
+ */
+void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId)
+ {
+ /* Invoke Error Handler ISR for TC5*/
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)5U);
+ }
+
+/*
+ * ======== lisrEdma3TC6ErrHandler0 ========
+ * EDMA3 instance 0 TC6 Error Interrupt Service Routine
+ */
+/* ARGSUSED */
+void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId)
+ {
+ /* Invoke Error Handler ISR for TC6*/
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)6U);
+ }
+
+/*
+ * ======== lisrEdma3TC7ErrHandler0 ========
+ * EDMA3 instance 0 TC7 Error Interrupt Service Routine
+ */
+void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId)
+ {
+ /* Invoke Error Handler ISR for TC7*/
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)7U);
+ }
+
+
+
+/* Resource Manager Internal functions - Start */
+
+/** Initialization of the Global region registers of the EDMA3 Controller */
+static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId, uint32_t numDmaChannels)
+ {
+ uint32_t evtQNum = 0U;
+ volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
+
+ assert (phyCtrllerInstId < EDMA3_MAX_EDMA3_INSTANCES);
+
+ ptrEdmaccRegs = (volatile EDMA3_CCRL_Regs *)
+ (resMgrObj[phyCtrllerInstId].gblCfgParams.globalRegs);
+
+ if (ptrEdmaccRegs != NULL)
+ {
+ ptrEdmaccRegs->EMCR = EDMA3_RM_SET_ALL_BITS;
+ if ( numDmaChannels > 32U)
+ {
+ /* Clear the EMCRH only if available channels are more than 32 */
+ ptrEdmaccRegs->EMCRH = EDMA3_RM_SET_ALL_BITS;
+ }
+ ptrEdmaccRegs->QEMCR = EDMA3_RM_SET_ALL_BITS;
+
+ /*
+ * Set all Instance-wide EDMA3 parameters (not channel-specific)
+ */
+
+ /**
+ * Set TC Priority among system-wide bus-masters and Queue
+ * Watermark Level
+ */
+ while (evtQNum <
+ resMgrObj[phyCtrllerInstId].gblCfgParams.numEvtQueue)
+ {
+ ptrEdmaccRegs->QUEPRI &= EDMA3_RM_QUEPRI_CLR_MASK(evtQNum);
+ ptrEdmaccRegs->QUEPRI |= EDMA3_RM_QUEPRI_SET_MASK(evtQNum,
+ resMgrObj[phyCtrllerInstId].gblCfgParams.evtQPri[evtQNum]);
+
+ ptrEdmaccRegs->QWMTHRA |= EDMA3_RM_QUEWMTHR_SET_MASK(evtQNum,
+ resMgrObj[phyCtrllerInstId].gblCfgParams.evtQueueWaterMarkLvl[evtQNum]);
+
+ evtQNum++;
+ }
+
+ /* Clear CCERR register */
+ ptrEdmaccRegs ->CCERRCLR = 0xFFFFU;
+ }
+
+ return;
+ }
+
+
+
+
+/** Initialization of the Shadow region registers of the EDMA3 Controller */
+static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance)
+ {
+ volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
+ volatile EDMA3_CCRL_ShadowRegs *ptrEdmaShadowRegs = NULL;
+ uint32_t phyCtrllerInstId;
+ uint32_t regionId;
+ const EDMA3_RM_InstanceInitConfig *rmInstInitConfig = pRMInstance->initParam.rmInstInitConfig;
+
+ assert (pRMInstance != NULL);
+
+ if (rmInstInitConfig != NULL)
+ {
+ phyCtrllerInstId = pRMInstance->pResMgrObjHandle->phyCtrllerInstId;
+ regionId = pRMInstance->initParam.regionId;
+
+ ptrEdmaccRegs = (volatile EDMA3_CCRL_Regs *)
+ (resMgrObj[phyCtrllerInstId].gblCfgParams.globalRegs);
+
+ if (ptrEdmaccRegs != NULL)
+ {
+ ptrEdmaShadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)
+ (&ptrEdmaccRegs->SHADOW[regionId]);
+
+ ptrEdmaShadowRegs->ECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->ECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+ ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->SECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->SECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+ ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->EECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+
+ ptrEdmaShadowRegs->QEECR = rmInstInitConfig->ownQdmaChannels[0U];
+
+ ptrEdmaShadowRegs->IECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->IECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+ ptrEdmaShadowRegs->ICR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->ICRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+
+ ptrEdmaShadowRegs->QSECR = rmInstInitConfig->ownQdmaChannels[0U];
+
+ /*
+ * Set all EDMA3 Resource<->Region mapping parameters
+ */
+
+ /* 1. Dma Channel (and TCC) <-> Region */
+ ptrEdmaccRegs->DRA[regionId].DRAE = 0U;
+ ptrEdmaccRegs->DRA[regionId].DRAEH = 0U;
+
+ /* 2. Qdma Channel <-> Region */
+ ptrEdmaccRegs->QRAE[regionId] = 0U;
+ }
+ }
+
+ return;
+ }
+
+
+
+/** Local MemZero function */
+void edma3MemZero(void *dst, uint32_t len)
+ {
+ uint32_t i = 0U;
+ uint32_t *ds = NULL;
+
+ assert (dst != NULL);
+
+ ds = (uint32_t *)dst;
+
+ for (i = 0U ; i < (len/4U) ; i++)
+ {
+ *ds = 0x0;
+ ds++;
+ }
+
+ return;
+ }
+
+
+/* Local MemCopy function */
+void edma3MemCpy(void *dst, const void *src, uint32_t len)
+ {
+ uint32_t i=0U;
+ const uint32_t *sr;
+ uint32_t *ds;
+
+ assert ((src != NULL) && (dst != NULL) && ((len%4) == 0));
+
+ sr = (const uint32_t *)src;
+ ds = (uint32_t *)dst;
+
+ for (i = 0U ; i < (len/4U) ; i++)
+ {
+ *ds = *sr;
+ ds++;
+ sr++;
+ }
+
+ return;
+ }
+
+
+/* Local MemCopy function to copy Param Set ONLY */
+void edma3ParamCpy(volatile void *dst, const volatile void *src)
+ {
+ uint32_t i = 0U;
+ const volatile uint32_t *sr;
+ volatile uint32_t *ds;
+
+ assert ((src != NULL) && (dst != NULL));
+
+ sr = (const volatile uint32_t *)src;
+ ds = (volatile uint32_t *)dst;
+
+ for (i = 0U; i < 8U; i++)
+ {
+ *ds = *sr;
+ ds++;
+ sr++;
+ }
+
+ return;
+ }
+
+
+/**
+ * Finds a particular bit ('0' or '1') in the particular word from 'start'.
+ * If found, returns the position, else return -1.
+ */
+static int32_t findBitInWord (int32_t source, uint32_t start, uint16_t bit)
+ {
+ uint32_t position = start;
+ uint16_t found = 0;
+ uint32_t iterations_left = 0;
+ uint32_t sourceTmp=0;
+
+ switch (bit)
+ {
+ case 1U:
+ {
+ sourceTmp = (uint32_t)source >> (start%32U);
+ source = (int32_t)sourceTmp;
+
+ while ((found==0U) && (source!=0))
+ {
+ if (((uint32_t)source & 0x1U) == 0x1U)
+ {
+ /* 1 */
+ found++;
+ }
+ else
+ {
+ /* 0 */
+ sourceTmp = (uint32_t)source >> 1;
+ source = (int32_t)sourceTmp;
+ position++;
+ }
+ }
+
+ }
+ break;
+
+ case 0:
+ {
+ sourceTmp = (uint32_t)source >> (start%32U);
+ source = (int32_t)sourceTmp;
+ iterations_left = (uint32_t)32U - (start%32U);
+
+ while ((found==0U) && (iterations_left>0U))
+ {
+ if (((uint32_t)source & 0x1U) == 0x1U)
+ {
+ /* 1 */
+ sourceTmp = (uint32_t)source >> 1;
+ source = (int32_t)sourceTmp;
+ position++;
+ iterations_left--;
+ }
+ else
+ {
+ /* 0 */
+ found++;
+ }
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return (found ? (int32_t)position : -1);
+ }
+
+
+/**
+ * Finds a particular bit ('0' or '1') in the specified resources' array
+ * from 'start' to 'end'. If found, returns the position, else return -1.
+ */
+static int32_t findBit (EDMA3_RM_ResType resType,
+ uint32_t start,
+ uint32_t end,
+ uint16_t bit)
+ {
+ int32_t position = -1;
+ uint32_t start_index = start / 32U;
+ uint32_t end_index = end / 32U;
+ int32_t i;
+ uint32_t *resPtr = 0x0;
+ int32_t ret = -1;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+
+ assert (start <= end);
+
+ /**
+ * job is to find 'bit' in an array[start_index:end_index]
+ * algo used:
+ * first search in array[start_index]
+ * then search in array[start_index + 1 : end_index - 1]
+ * then search in array[end_index]
+ */
+ switch (resType)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL:
+ resPtr = &contiguousDmaRes[0];
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL:
+ resPtr = &contiguousQdmaRes[0];
+ break;
+
+ case EDMA3_RM_RES_TCC:
+ resPtr = &contiguousTccRes[0];
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET:
+ resPtr = &contiguousParamRes[0];
+ break;
+
+ default:
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+
+ if (EDMA3_RM_SOK == result)
+ {
+ switch (bit)
+ {
+ case 1U:
+ {
+ /* Find '1' in first word. */
+ position = findBitInWord (resPtr[start_index], start, (uint16_t)1U);
+
+ if (position != -1)
+ {
+ ret = position;
+ }
+ else
+ {
+ /* '1' NOT found, look into other words. */
+ for (i = ((int32_t)start_index + (int32_t)1U); i <= ((int32_t)end_index - (int32_t)1U); i++)
+ {
+ position = findBitInWord (resPtr[i], (uint32_t)0U, (uint16_t)1U);
+ if (position != -1)
+ {
+ /* '1' Found... */
+ ret = (position + (i*32));
+ break;
+ }
+ }
+
+ /* First check whether we have found '1' or not. */
+ if (ret == -1)
+ {
+ /* Still not found, look in the last word. */
+ position = findBitInWord(resPtr[end_index], (uint32_t)0U, (uint16_t)1U);
+ if (position != -1)
+ {
+ /* Finally got it. */
+ ret = (position + ((int32_t)end_index*(int32_t)32U));
+ }
+ else
+ {
+ /* Sorry, could not find it, return -1. */
+ ret = -1;
+ }
+ }
+ }
+ }
+ break;
+
+ case 0U:
+ {
+ /* Find '0' in first word. */
+ position = findBitInWord(resPtr[start_index], start, (uint16_t)0U);
+ if (position != -1)
+ {
+ ret = position;
+ }
+ else
+ {
+ /* '0' NOT found, look into other words. */
+ for (i = ((int32_t)start_index + (int32_t)1U); i <= ((int32_t)end_index - (int32_t)1U); i++)
+ {
+ position = findBitInWord(resPtr[i], (uint32_t)0U, (uint16_t)0U);
+ if (position != -1)
+ {
+ /* '0' found... */
+ ret = (position + (i*32));
+ break;
+ }
+ }
+
+ /* First check whether we have found '0' or not. */
+ if (ret == -1)
+ {
+ position = findBitInWord(resPtr[end_index], (uint32_t)0U, (uint16_t)0U);
+ if (position != -1)
+ {
+ /* Finally got it. */
+ ret = (position + ((int32_t)end_index*(int32_t)32U));
+ }
+ else
+ {
+ /* Sorry, could not find it, return -1. */
+ ret = -1;
+ }
+ }
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+
+
+ return ((ret >= (int32_t)start) ? ret : -1);
+ }
+
+
+
+/**
+ * If successful, this function returns EDMA3_RM_SOK and the position
+ * of first available resource in 'positionRes'. Else returns error.
+ */
+static EDMA3_RM_Result allocAnyContigRes(EDMA3_RM_ResType resType,
+ uint32_t numResources,
+ uint32_t *positionRes)
+ {
+ uint16_t found = 0U;
+ int32_t first_one, next_zero;
+ uint32_t num_available;
+ int32_t ret = -1;
+ uint32_t start = 0;
+ uint32_t end;
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+
+ assert (positionRes != NULL);
+
+ switch (resType)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL:
+ end = EDMA3_MAX_DMA_CH - 1U;
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL:
+ end = EDMA3_MAX_QDMA_CH - 1U;
+ break;
+
+ case EDMA3_RM_RES_TCC:
+ end = EDMA3_MAX_TCC - 1U;
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET:
+ end = edma3NumPaRAMSets - 1U;
+ break;
+
+ default:
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /**
+ * Algorithm used for finding N contiguous resources.
+ * In the resources' array, '1' means available and '0' means
+ * not-available.
+ * Step a) Find first '1' starting from 'start'. If successful,
+ * store it in first_one, else return error.
+ * Step b) Find first '0' starting from (first_one+1) to 'end'.
+ * If successful, store returned value in next_zero. If '0' could
+ * not be located, it means all the resources are available.
+ * Store 'end' (i.e. the last resource id) in next_zero.
+ * Step c) Count the number of contiguous resources available
+ * by subtracting first_one from next_zero.
+ * Step d) If result < N, do the whole process again untill you
+ * reach end. Else you have found enough resources, return success.
+ */
+ while((found == 0) && (start<=end) && (((end-start)+1U) >= numResources))
+ {
+ /* Find first '1' starting from 'start' till 'end'. */
+ first_one = findBit (resType, start, end, (uint16_t)1U);
+ if (first_one != -1)
+ {
+ /* Got first 1, search for first '0' now. */
+ next_zero = findBit (resType, (uint32_t)first_one+(uint32_t)1, end, (uint16_t)0U);
+ if (next_zero == -1)
+ {
+ /* Unable to find next zero, all 1' are there */
+ next_zero = (int32_t)end + (int32_t)1U;
+ }
+
+ /* check no of resources available */
+ num_available = (uint32_t)next_zero - (uint32_t)first_one;
+ if (num_available >= numResources)
+ {
+ /* hurrah..., we have found enough resources. */
+ found = 1U;
+ ret = first_one;
+ }
+ else
+ {
+ /* Not enough resources, try again */
+ start = (uint32_t)next_zero + (uint32_t)1;
+ }
+ }
+ else
+ {
+ /* do nothing, first 1 is not there, return. */
+ break;
+ }
+ }
+ }
+
+
+ if (result == EDMA3_RM_SOK)
+ {
+ if (found == 1U)
+ {
+ /* required resources found, retrun the first available res id. */
+ *positionRes = (uint32_t)ret;
+ }
+ else
+ {
+ /* No resources allocated */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+
+ return result;
+ }
+
+
+
+/**
+ * Starting from 'firstResIdObj', this function makes the next 'numResources'
+ * Resources non-available for future. Also, it does some global resisters'
+ * setting also.
+ */
+static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,
+ const EDMA3_RM_ResDesc *firstResIdObj,
+ uint32_t numResources)
+ {
+ EDMA3_RM_Result result = EDMA3_RM_SOK;
+ volatile EDMA3_CCRL_Regs *gblRegs = NULL;
+ EDMA3_RM_Obj *rmObj = NULL;
+ uint32_t avlblIdx = 0U;
+ uint32_t firstResId=0U;
+ uint32_t lastResId=0U;
+ uint32_t edma3Id;
+
+ assert ((rmInstance != NULL) && (firstResIdObj != NULL));
+
+ rmObj = rmInstance->pResMgrObjHandle;
+
+ if (rmObj == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+
+ if (EDMA3_RM_SOK == result)
+ {
+ edma3Id = rmObj->phyCtrllerInstId;
+ gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+
+ if (gblRegs == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ switch (firstResIdObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL:
+ {
+ firstResId = firstResIdObj->resId;
+ lastResId = firstResId + (numResources - 1U);
+
+ for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
+ {
+ rmInstance->avlblDmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Enable the DMA channel in the DRAE/DRAEH registers also.
+ */
+ if (avlblIdx < 32U)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= ((uint32_t)0x1U << avlblIdx);
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= ((uint32_t)0x1U << (avlblIdx - 32U));
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL:
+ {
+ firstResId = firstResIdObj->resId;
+ lastResId = firstResId + (numResources - 1U);
+
+ for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
+ {
+ rmInstance->avlblQdmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Enable the QDMA channel in the QRAE register also.
+ */
+ gblRegs->QRAE[rmInstance->initParam.regionId]
+ |= ((uint32_t)0x1U << avlblIdx);
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_TCC:
+ {
+ firstResId = firstResIdObj->resId;
+ lastResId = firstResId + (numResources - 1U);
+
+ for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
+ {
+ rmInstance->avlblTccs[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * If the region id coming from this
+ * RM instance is same as the Master RM
+ * Instance's region id, only then we will be
+ * getting the interrupts on the same side.
+ * So save the TCC in the allocatedTCCs[] array.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ if (avlblIdx < 32U)
+ {
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << avlblIdx);
+ }
+ else
+ {
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (avlblIdx - 32U));
+ }
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET:
+ {
+ firstResId = firstResIdObj->resId;
+ lastResId = firstResId + (numResources - 1U);
+
+ for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
+ {
+ rmInstance->avlblPaRAMSets [avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Also, make the actual PARAM Set NULL, checking the flag
+ * whether it is required or not.
+ */
+ if (TRUE == rmInstance->paramInitRequired)
+ {
+ edma3MemZero((void *)(&gblRegs->PARAMENTRY[avlblIdx]),
+ sizeof(gblRegs->PARAMENTRY[avlblIdx]));
+ }
+ }
+ }
+ break;
+
+ default:
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+ }
+
+
+ return result;
+ }
+
+
+EDMA3_RM_Result EDMA3_RM_initXbarEventMap (EDMA3_RM_Handle hEdma,
+ const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig,
+ EDMA3_RM_mapXbarEvtToChan mapXbarEvtFunc,
+ EDMA3_RM_xbarConfigScr configXbarScr)
+ {
+ EDMA3_RM_Result result = EDMA3_DRV_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdma;
+
+ if (mapXbarEvtFunc != NULL)
+ {
+ rmInstance->mapXbarToChan = mapXbarEvtFunc;
+ }
+ if (configXbarScr != NULL)
+ {
+ rmInstance->configScrMapXbarToEvt = configXbarScr;
+ }
+ if (edmaGblXbarConfig != NULL)
+ {
+ edma3MemCpy((void *)(&rmInstance->rmXbarToEvtMapConfig),
+ (const void *)(edmaGblXbarConfig),
+ sizeof (EDMA3_RM_GblXbarToChanConfigParams));
+ }
+ }
+
+ return (result);
+ }
+
+/* Resource Manager Internal functions - End */
+
+/* End of File */