diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.c b/packages/ti/sdo/edma3/rm/src/edma3resmgr.c
index c8a61e04ce86f77bc1530525d59c1580fdf2f480..186d7e48499ef4a6bb5751a802f7730ba19fc4ec 100755 (executable)
* 'n' number of times.
* Minumum value is 1.
*/
-#define EDMA3_RM_COMPL_HANDLER_RETRY_COUNT (10u)
+#define EDMA3_RM_COMPL_HANDLER_RETRY_COUNT (10U)
/**
* \brief EDMA3 Resource Manager retry count to check the pending CC Error Interrupt inside ISR
* interrupt for 'n' number of times.
* Minumum value is 1.
*/
-#define EDMA3_RM_CCERR_HANDLER_RETRY_COUNT (10u)
+#define EDMA3_RM_CCERR_HANDLER_RETRY_COUNT (10U)
#ifdef BUILD_C6XDSP
#pragma DATA_SECTION(masterExists, ".fardata:.edma3Globals");
#endif
-static uint32_t masterExists [EDMA3_MAX_EDMA3_INSTANCES] = {FALSE,FALSE,FALSE};
+static uint32_t masterExists [EDMA3_MAX_EDMA3_INSTANCES] = {FALSE,FALSE,FALSE,FALSE,FALSE};
/**
* Number of PaRAM Sets actually present on the SoC. This will be updated
#ifdef BUILD_C6XDSP
#pragma DATA_SECTION(allocatedTCCs, ".fardata:.edma3Globals");
#endif
-static uint32_t allocatedTCCs[EDMA3_MAX_EDMA3_INSTANCES][2u] =
+static uint32_t allocatedTCCs[EDMA3_MAX_EDMA3_INSTANCES][2U] =
{
- {0x0u, 0x0u},
- {0x0u, 0x0u},
- {0x0u, 0x0u},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
};
#ifdef BUILD_C6XDSP
#pragma DATA_SECTION(contiguousDmaRes, ".fardata:.edma3Globals");
#endif
-static uint32_t contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u};
+static uint32_t contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0U, 0x0U};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
#ifdef BUILD_C6XDSP
#pragma DATA_SECTION(contiguousQdmaRes, ".fardata:.edma3Globals");
#endif
-static uint32_t contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u};
+static uint32_t contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0U};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
#ifdef BUILD_C6XDSP
#pragma DATA_SECTION(contiguousTccRes, ".fardata:.edma3Globals");
#endif
-static uint32_t contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u};
+static uint32_t contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0U, 0x0U};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
@@ -324,28 +326,28 @@ static EDMA3_RM_ChBoundResources edma3RmChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][E
#ifdef BUILD_C6XDSP
#pragma DATA_SECTION(rmInitDone, ".fardata:.edma3Globals");
#endif
- static unsigned short rmInitDone = FALSE;
+ static uint16_t rmInitDone = FALSE;
/*---------------------------------------------------------------------------*/
/* Local functions prototypes */
/*---------------------------------------------------------------------------*/
/** EDMA3 Instance 0 Completion Handler Interrupt Service Routine */
-void lisrEdma3ComplHandler0(uint32_t arg);
+void lisrEdma3ComplHandler0(uint32_t edma3InstanceId);
/** EDMA3 Instance 0 CC Error Interrupt Service Routine */
-void lisrEdma3CCErrHandler0(uint32_t arg);
+void lisrEdma3CCErrHandler0(uint32_t edma3InstanceId);
/**
* EDMA3 Instance 0 TC[0-7] Error Interrupt Service Routines
* for a maximum of 8 TCs (Transfer Controllers).
*/
-void lisrEdma3TC0ErrHandler0(uint32_t arg);
-void lisrEdma3TC1ErrHandler0(uint32_t arg);
-void lisrEdma3TC2ErrHandler0(uint32_t arg);
-void lisrEdma3TC3ErrHandler0(uint32_t arg);
-void lisrEdma3TC4ErrHandler0(uint32_t arg);
-void lisrEdma3TC5ErrHandler0(uint32_t arg);
-void lisrEdma3TC6ErrHandler0(uint32_t arg);
-void lisrEdma3TC7ErrHandler0(uint32_t arg);
+void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId);
/** Interrupt Handler for the Transfer Completion interrupt */
/** Local MemCpy function */
void edma3MemCpy(void *dst, const void *src, uint32_t len);
/* Local MemCopy function to copy Param Set ONLY */
-void edma3ParamCpy(void *dst, const void *src);
+void edma3ParamCpy(volatile void *dst, const volatile void *src);
/** Initialization of the Global region registers of the EDMA3 Controller */
static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId, uint32_t numDmaChannels);
const EDMA3_RM_GblConfigParams *gblCfgParams,
const void *miscParam)
{
- uint32_t count = 0u;
+ uint32_t count = 0U;
EDMA3_RM_Result result = EDMA3_RM_SOK;
const EDMA3_RM_MiscParam *miscOpt = (const EDMA3_RM_MiscParam *)miscParam;
{
edma3MemZero((void *)&(resMgrObj[count]),
sizeof(resMgrObj));
- edma3MemZero((void *)(&(edma3IntrParams[0u])),
+ edma3MemZero((void *)(&(edma3IntrParams[0U])),
sizeof(edma3IntrParams));
rmInitDone = TRUE;
*/
if (FALSE == resMgrObj[phyCtrllerInstId].gblCfgParams.dmaChPaRAMMapExists)
{
- for (count = 0u; count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels; count++)
+ for (count = 0U; count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels; count++)
{
resMgrObj[phyCtrllerInstId].gblCfgParams.dmaChannelPaRAMMap[count] = count;
}
* Initialize Boundary Values for Logical Channel Ranges.
*/
edma3NumPaRAMSets = resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets;
- edma3_dma_ch_max_val[phyCtrllerInstId] = resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels - 1u;
- edma3_link_ch_min_val[phyCtrllerInstId] = edma3_dma_ch_max_val[phyCtrllerInstId] + 1u;
- edma3_link_ch_max_val[phyCtrllerInstId] = edma3_link_ch_min_val[phyCtrllerInstId] + resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets - 1u;
- edma3_qdma_ch_min_val[phyCtrllerInstId] = edma3_link_ch_max_val[phyCtrllerInstId] + 1u;
- edma3_qdma_ch_max_val[phyCtrllerInstId] = edma3_qdma_ch_min_val[phyCtrllerInstId] + resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels - 1u;
+ edma3_dma_ch_max_val[phyCtrllerInstId] = resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels - 1U;
+ edma3_link_ch_min_val[phyCtrllerInstId] = edma3_dma_ch_max_val[phyCtrllerInstId] + 1U;
+ edma3_link_ch_max_val[phyCtrllerInstId] = edma3_link_ch_min_val[phyCtrllerInstId] + (resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets - 1U);
+ edma3_qdma_ch_min_val[phyCtrllerInstId] = edma3_link_ch_max_val[phyCtrllerInstId] + 1U;
+ edma3_qdma_ch_max_val[phyCtrllerInstId] = edma3_qdma_ch_min_val[phyCtrllerInstId] + (resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels - 1U);
edma3_log_ch_max_val[phyCtrllerInstId] = edma3_qdma_ch_max_val[phyCtrllerInstId];
resMgrObj[phyCtrllerInstId].phyCtrllerInstId = phyCtrllerInstId;
resMgrObj[phyCtrllerInstId].state = EDMA3_RM_CREATED;
- resMgrObj[phyCtrllerInstId].numOpens = 0u;
+ resMgrObj[phyCtrllerInstId].numOpens = 0U;
/* Make all the RM instances for this EDMA3 HW NULL */
- for (count = 0u; count < EDMA3_MAX_RM_INSTANCES; count++)
+ for (count = 0U; count < EDMA3_MAX_RM_INSTANCES; count++)
{
edma3MemZero((void *)((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count),
sizeof(EDMA3_RM_Instance));
}
/* Initialize the global edma3DmaChTccMapping array with EDMA3_MAX_TCC */
- for ( count = 0u;
+ for ( count = 0U;
count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels;
count++
)
}
/* Initialize the global edma3QdmaChTccMapping array with EDMA3_MAX_TCC */
- for ( count = 0u;
+ for ( count = 0U;
count < resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels;
count++
)
}
/* Reset edma3RmChBoundRes Array*/
- for (count = 0u; count < EDMA3_MAX_LOGICAL_CH; count++)
+ for (count = 0U; count < EDMA3_MAX_LOGICAL_CH; count++)
{
edma3RmChBoundRes[phyCtrllerInstId][count].paRAMId = -1;
edma3RmChBoundRes[phyCtrllerInstId][count].tcc = EDMA3_MAX_TCC;
}
/* Make the contiguousParamRes array NULL */
- edma3MemZero((void *)(&(contiguousParamRes[0u])),
+ edma3MemZero((void *)(&(contiguousParamRes[0U])),
sizeof(contiguousParamRes));
/* Check if the parameters are OK. */
if (EDMA3_RM_SOK == result)
{
- /*to remove CCS remark: parameter "param" was never referenced */
- (void)param;
-
/**
* If number of RM Instances is 0, then state should be
* EDMA3_RM_CLOSED OR EDMA3_RM_CREATED.
*/
- if ((NULL == resMgrObj[phyCtrllerInstId].numOpens)
+ if ((0 == resMgrObj[phyCtrllerInstId].numOpens)
&& ((resMgrObj[phyCtrllerInstId].state != EDMA3_RM_CLOSED)
&& (resMgrObj[phyCtrllerInstId].state != EDMA3_RM_CREATED)))
{
* If number of RM Instances is NOT 0, then this function
* SHOULD NOT be called by anybody.
*/
- if (NULL != resMgrObj[phyCtrllerInstId].numOpens)
+ if (0 != resMgrObj[phyCtrllerInstId].numOpens)
{
result = EDMA3_RM_E_INVALID_STATE;
}
resMgrObj[phyCtrllerInstId].state = EDMA3_RM_DELETED;
/* Reset the Allocated TCCs Array also. */
- allocatedTCCs[phyCtrllerInstId][0u] = 0x0u;
- allocatedTCCs[phyCtrllerInstId][1u] = 0x0u;
+ allocatedTCCs[phyCtrllerInstId][0U] = 0x0U;
+ allocatedTCCs[phyCtrllerInstId][1U] = 0x0U;
/* Also, reset the RM Object Global Config Info */
edma3MemZero((void *)&(resMgrObj[phyCtrllerInstId].gblCfgParams),
const EDMA3_RM_Param *initParam,
EDMA3_RM_Result *errorCode)
{
- uint32_t intState = 0u;
- uint32_t resMgrIdx = 0u;
+ uint32_t intState = 0U;
+ uint32_t resMgrIdx = 0U;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Instance *temp_ptr_rm_inst = NULL;
EDMA3_RM_Handle retVal = NULL;
- uint32_t dmaChDwrds = 0u;
- uint32_t paramSetDwrds = 0u;
- uint32_t tccDwrds = 0u;
+ uint32_t dmaChDwrds = 0U;
+ uint32_t paramSetDwrds = 0U;
+ uint32_t tccDwrds = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
#ifdef GENERIC
else
{
edma3OsProtectEntry (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
&intState);
/** Check state of RM Object.
* If no RM instance is opened and this is the first one,
* then state should be created/closed.
*/
- if ((rmObj->numOpens == NULL) &&
+ if ((rmObj->numOpens == 0) &&
((rmObj->state != EDMA3_RM_CREATED) &&
(rmObj->state != EDMA3_RM_CLOSED)))
{
result = EDMA3_RM_E_INVALID_STATE;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
{
result = EDMA3_RM_E_INVALID_STATE;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
{
result = EDMA3_RM_E_MAX_RM_INST_OPENED;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
}
/* No two masters should exist, return error */
result = EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
{
/* Create Res Mgr Instance */
- for (resMgrIdx = 0u; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)
+ for (resMgrIdx = 0U; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)
{
temp_ptr_rm_inst = ((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);
{
result = EDMA3_RM_E_MAX_RM_INST_OPENED;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
rmInstance->initParam.rmInstInitConfig =
((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);
- dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32u;
+ dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / (uint32_t)32U;
if (dmaChDwrds == 0)
{
/* In case DMA channels are < 32 */
- dmaChDwrds = 1;
+ dmaChDwrds = 1U;
}
- paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32u;
+ paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / (uint32_t)32U;
if (paramSetDwrds == 0)
{
/* In case PaRAM Sets are < 32 */
- paramSetDwrds = 1;
+ paramSetDwrds = 1U;
}
- tccDwrds = rmObj->gblCfgParams.numTccs / 32u;
+ tccDwrds = rmObj->gblCfgParams.numTccs / (uint32_t)32U;
if (tccDwrds == 0)
{
/* In case TCCs are < 32 */
- tccDwrds = 1;
+ tccDwrds = 1U;
}
- for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < dmaChDwrds; ++resMgrIdx)
{
rmInstance->avlblDmaChannels[resMgrIdx]
= rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resMgrIdx];
}
- rmInstance->avlblQdmaChannels[0u]
- = rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u];
+ rmInstance->avlblQdmaChannels[0U]
+ = rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U];
- for (resMgrIdx = 0u; resMgrIdx < paramSetDwrds; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < paramSetDwrds; ++resMgrIdx)
{
rmInstance->avlblPaRAMSets[resMgrIdx]
= rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resMgrIdx];
}
- for (resMgrIdx = 0u; resMgrIdx < tccDwrds; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < tccDwrds; ++resMgrIdx)
{
rmInstance->avlblTccs [resMgrIdx]
= rmInstance->initParam.rmInstInitConfig->ownTccs[resMgrIdx];
* will not be returned in case user requests for ANY link
* channel.
*/
- for (resMgrIdx = 0u; resMgrIdx < rmObj->gblCfgParams.numDmaChannels; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < rmObj->gblCfgParams.numDmaChannels; ++resMgrIdx)
{
- rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[resMgrIdx/32u] |= (1u<<(resMgrIdx%32u));
+ rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[resMgrIdx/32U] |= ((uint32_t)1U<<(resMgrIdx%32U));
}
/*
}
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
}
const void *param)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
- uint32_t intState = 0u;
- uint32_t resMgrIdx = 0u;
+ uint32_t intState = 0U;
+ uint32_t resMgrIdx = 0U;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Instance *rmInstance = NULL;
uint32_t dmaChDwrds;
uint32_t paramSetDwrds;
uint32_t tccDwrds;
- /*to remove CCS remark: parameter "param" was never referenced */
- (void)param;
-
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
if (NULL == hEdmaResMgr)
}
else
{
- dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32u;
- paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32u;
- tccDwrds = rmObj->gblCfgParams.numTccs / 32u;
+ dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / (uint32_t)32U;
+ paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / (uint32_t)32U;
+ tccDwrds = rmObj->gblCfgParams.numTccs / (uint32_t)32U;
/* Set the instance config as NULL*/
- for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < dmaChDwrds; ++resMgrIdx)
{
- rmInstance->avlblDmaChannels[resMgrIdx] = 0x0u;
+ rmInstance->avlblDmaChannels[resMgrIdx] = 0x0U;
}
- for (resMgrIdx = 0u; resMgrIdx < paramSetDwrds; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < paramSetDwrds; ++resMgrIdx)
{
- rmInstance->avlblPaRAMSets[resMgrIdx] = 0x0u;
+ rmInstance->avlblPaRAMSets[resMgrIdx] = 0x0U;
}
- rmInstance->avlblQdmaChannels[0u] = 0x0u;
- for (resMgrIdx = 0u; resMgrIdx < tccDwrds; ++resMgrIdx)
+ rmInstance->avlblQdmaChannels[0U] = 0x0U;
+ for (resMgrIdx = 0U; resMgrIdx < tccDwrds; ++resMgrIdx)
{
- rmInstance->avlblTccs[resMgrIdx] = 0x0u;
+ rmInstance->avlblTccs[resMgrIdx] = 0x0U;
}
/**
/* Critical section starts */
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
&intState);
/* Decrease the Number of Opens */
--rmObj->numOpens;
- if (NULL == rmObj->numOpens)
+ if (0 == rmObj->numOpens)
{
edma3MemZero((void *)&(edma3RmChBoundRes[rmObj->phyCtrllerInstId]),
sizeof(edma3RmChBoundRes[rmObj->phyCtrllerInstId]));
/* Critical section ends */
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
rmInstance->pResMgrObjHandle = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Result semResult = EDMA3_RM_SOK;
- uint32_t avlblIdx = 0u;
+ uint32_t avlblIdx = 0U;
uint32_t resIdClr = 0x0;
uint32_t resIdSet = 0x0;
uint32_t resId;
edma3Id = rmObj->phyCtrllerInstId;
resId = resObj->resId;
- resIdClr = (uint32_t)(~(1u << (resId%32u)));
- resIdSet = (1u << (resId%32u));
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resId%32U)));
+ resIdSet = (1U << (resId%32U));
if ( rmInstance->mapXbarToChan != NULL)
{
{
if (resId == EDMA3_RM_RES_ANY)
{
- for (avlblIdx=0u;
+ for (avlblIdx=0U;
avlblIdx <
rmObj->gblCfgParams.numDmaChannels;
++avlblIdx)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[avlblIdx/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[avlblIdx/32U])
&
- (rmInstance->avlblDmaChannels[avlblIdx/32u])
+ (rmInstance->avlblDmaChannels[avlblIdx/32U])
&
- ~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[avlblIdx/32u])
+ ~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[avlblIdx/32U])
&
- (1u << (avlblIdx%32u))) != FALSE)
+ ((uint32_t)1U << (avlblIdx%32U))) != FALSE)
{
/*
* Match found.
* Mark the 'match found' resource as "Not Available"
* for future requests
*/
- rmInstance->avlblDmaChannels[avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblDmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* Check if the register modification flag is
* Enable the DMA channel in the
* DRAE/DRAEH registers also.
*/
- if (avlblIdx < 32u)
+ if (avlblIdx < 32U)
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << avlblIdx);
+ |= ((uint32_t)0x1U << avlblIdx);
}
else
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (avlblIdx - 32u));
+ |= ((uint32_t)0x1U << (avlblIdx - 32U));
}
}
* Check if specified resource is owned
* by this instance of the resource manager
*/
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resId/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resId/32U])&(resIdSet))!=FALSE)
{
/* Now check if specified resource is available presently*/
- if (((rmInstance->avlblDmaChannels[resId/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->avlblDmaChannels[resId/32U])&(resIdSet))!=FALSE)
{
/*
* Mark the specified channel as "Not Available"
* for future requests
*/
- rmInstance->avlblDmaChannels[resId/32u] &= resIdClr;
+ rmInstance->avlblDmaChannels[resId/32U] &= resIdClr;
/**
* Check if the register modification flag is
*/
if (TRUE == rmInstance->regModificationRequired)
{
- if (resId < 32u)
+ if (resId < 32U)
{
rmInstance->shadowRegs->EECR = (1UL << resId);
* DRAE registers also.
*/
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << resId);
+ |= ((uint32_t)0x1U << resId);
}
else
{
* DRAEH registers also.
*/
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (resId - 32u));
+ |= ((uint32_t)0x1U << (resId - 32U));
}
}
{
if (resId == EDMA3_RM_RES_ANY)
{
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numQdmaChannels; ++avlblIdx)
+ for (avlblIdx=0U; avlblIdx<rmObj->gblCfgParams.numQdmaChannels; ++avlblIdx)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[avlblIdx/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[avlblIdx/32U])
&
- (rmInstance->avlblQdmaChannels[avlblIdx/32u])
+ (rmInstance->avlblQdmaChannels[avlblIdx/32U])
&
- ~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[avlblIdx/32u])
+ ~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[avlblIdx/32U])
&
- (1u << (avlblIdx%32u))) != FALSE)
+ ((uint32_t)1U << (avlblIdx%32U))) != FALSE)
{
resObj->resId = avlblIdx;
- rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblQdmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* Check if the register modification flag is
* QRAE register also.
*/
gblRegs->QRAE[rmInstance->initParam.regionId]
- |= (0x1u << avlblIdx);
+ |= ((uint32_t)0x1U << avlblIdx);
}
result = EDMA3_RM_SOK;
{
if (resId < rmObj->gblCfgParams.numQdmaChannels)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32U])&(resIdSet))!=FALSE)
{
- if (((rmInstance->avlblQdmaChannels [resId/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->avlblQdmaChannels [resId/32U])&(resIdSet))!=FALSE)
{
- rmInstance->avlblQdmaChannels [resId/32u] &= resIdClr;
+ rmInstance->avlblQdmaChannels [resId/32U] &= resIdClr;
/**
* Check if the register modification flag is
* QRAE register also.
*/
gblRegs->QRAE[rmInstance->initParam.regionId]
- |= (0x1u << resId);
+ |= ((uint32_t)0x1U << resId);
}
result = EDMA3_RM_SOK;
{
if (resId == EDMA3_RM_RES_ANY)
{
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numTccs; ++avlblIdx)
+ for (avlblIdx=0U; avlblIdx<rmObj->gblCfgParams.numTccs; ++avlblIdx)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [avlblIdx/32u])
- & (rmInstance->avlblTccs [avlblIdx/32u])
- & ~(rmInstance->initParam.rmInstInitConfig->resvdTccs [avlblIdx/32u])
- & (1u << (avlblIdx%32u)))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [avlblIdx/32U])
+ & (rmInstance->avlblTccs [avlblIdx/32U])
+ & ~(rmInstance->initParam.rmInstInitConfig->resvdTccs [avlblIdx/32U])
+ & ((uint32_t)1U << (avlblIdx%32U)))!=FALSE)
{
resObj->resId = avlblIdx;
- rmInstance->avlblTccs [avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblTccs [avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* Check if the register modification flag is
* getting the interrupts on the same side.
* So save the TCC in the allocatedTCCs[] array.
*/
- if (avlblIdx < 32u)
+ if (avlblIdx < 32U)
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << avlblIdx);
+ |= ((uint32_t)0x1U << avlblIdx);
/**
* Do not modify this global array if the register
*/
if (edma3RegionId == rmInstance->initParam.regionId)
{
- allocatedTCCs[edma3Id][0u] |= (0x1u << avlblIdx);
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << avlblIdx);
}
}
else
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (avlblIdx - 32u));
+ |= ((uint32_t)0x1U << (avlblIdx - 32U));
/**
* Do not modify this global array if the register
*/
if (edma3RegionId == rmInstance->initParam.regionId)
{
- allocatedTCCs[edma3Id][1u] |= (0x1u << (avlblIdx - 32u));
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (avlblIdx - 32U));
}
}
}
{
if (resId < rmObj->gblCfgParams.numTccs)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32U])&(resIdSet))!=FALSE)
{
- if (((rmInstance->avlblTccs [resId/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->avlblTccs [resId/32U])&(resIdSet))!=FALSE)
{
- rmInstance->avlblTccs [resId/32u] &= resIdClr;
+ rmInstance->avlblTccs [resId/32U] &= resIdClr;
/**
* Check if the register modification flag is
* getting the interrupts on the same side.
* So save the TCC in the allocatedTCCs[] array.
*/
- if (resId < 32u)
+ if (resId < 32U)
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << resId);
+ |= ((uint32_t)0x1U << resId);
/**
* Do not modify this global array if the register
*/
if (edma3RegionId == rmInstance->initParam.regionId)
{
- allocatedTCCs[edma3Id][0u] |= (0x1u << resId);
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << resId);
}
}
else
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (resId - 32u));
+ |= ((uint32_t)0x1U << (resId - 32U));
/**
* Do not modify this global array if the register
*/
if (edma3RegionId == rmInstance->initParam.regionId)
{
- allocatedTCCs[edma3Id][1u] |= (0x1u << (resId - 32u));
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (resId - 32U));
}
}
}
{
if (resId == EDMA3_RM_RES_ANY)
{
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numPaRAMSets; ++avlblIdx)
+ for (avlblIdx=0U; avlblIdx<rmObj->gblCfgParams.numPaRAMSets; ++avlblIdx)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [avlblIdx/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [avlblIdx/32U])
&
- (rmInstance->avlblPaRAMSets [avlblIdx/32u])
+ (rmInstance->avlblPaRAMSets [avlblIdx/32U])
&
- ~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets [avlblIdx/32u])
+ ~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets [avlblIdx/32U])
&
- (1u << (avlblIdx%32u)))!=FALSE)
+ ((uint32_t)1U << (avlblIdx%32U)))!=FALSE)
{
resObj->resId = avlblIdx;
- rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblPaRAMSets [avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* Also, make the actual PARAM Set NULL, checking the flag
{
if (resId < rmObj->gblCfgParams.numPaRAMSets)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32U])&(resIdSet))!=FALSE)
{
- if (((rmInstance->avlblPaRAMSets [resId/32u])&(resIdSet)) !=FALSE)
+ if (((rmInstance->avlblPaRAMSets [resId/32U])&(resIdSet)) !=FALSE)
{
- rmInstance->avlblPaRAMSets [resId/32u] &= resIdClr;
+ rmInstance->avlblPaRAMSets [resId/32U] &= resIdClr;
/**
* Also, make the actual PARAM Set NULL, checking the flag
edma3Id = rmObj->phyCtrllerInstId;
resId = resObj->resId;
- resIdSet = 1u << (resId%32u);
+ resIdSet = 1U << (resId%32U);
/**
* Take the instance specific semaphore, to prevent simultaneous
{
if (resId < rmObj->gblCfgParams.numDmaChannels)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels [resId/32u]) & (resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels [resId/32U]) & (resIdSet))!=FALSE)
{
- if (((~(rmInstance->avlblDmaChannels[resId/32u]))&(resIdSet))!=FALSE)
+ if (((~(rmInstance->avlblDmaChannels[resId/32U]))&(resIdSet))!=FALSE)
{
/*
* Mark the specified channel as "Available"
* for future requests
*/
- rmInstance->avlblDmaChannels[resId/32u] |= resIdSet;
+ rmInstance->avlblDmaChannels[resId/32U] |= resIdSet;
/**
* Check if the register modification flag is
* Reset the bit specific to the DMA channel
* in the DRAE/DRAEH register also.
*/
- if (resId < 32u)
+ if (resId < 32U)
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- &= (~(0x1u << resId));
+ &= (~((uint32_t)0x1U << resId));
}
else
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- &= (~(0x1u << (resId-32u)));
+ &= (~((uint32_t)0x1U << (resId-32U)));
}
}
{
if (resId < rmObj->gblCfgParams.numQdmaChannels)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32u]) & (resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32U]) & (resIdSet))!=FALSE)
{
- if (((~(rmInstance->avlblQdmaChannels [resId/32u])) & (resIdSet))!=FALSE)
+ if (((~(rmInstance->avlblQdmaChannels [resId/32U])) & (resIdSet))!=FALSE)
{
- rmInstance->avlblQdmaChannels [resId/32u] |= resIdSet;
+ rmInstance->avlblQdmaChannels [resId/32U] |= resIdSet;
/**
* Check if the register modification flag is
* in the QRAE register also.
*/
gblRegs->QRAE[rmInstance->initParam.regionId]
- &= (~(0x1u << resId));
+ &= (~((uint32_t)0x1U << resId));
}
result = EDMA3_RM_SOK;
{
if (resId < rmObj->gblCfgParams.numTccs)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32u]) & (resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32U]) & (resIdSet))!=FALSE)
{
- if (((~(rmInstance->avlblTccs [resId/32u])) & (resIdSet))!=FALSE)
+ if (((~(rmInstance->avlblTccs [resId/32U])) & (resIdSet))!=FALSE)
{
- rmInstance->avlblTccs [resId/32u] |= resIdSet;
+ rmInstance->avlblTccs [resId/32U] |= resIdSet;
/**
* Check if the register modification flag is
* TCC in allocatedTCCs[] array,
* remove it from there too.
*/
- if (resId < 32u)
+ if (resId < 32U)
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- &= (~(0x1u << resId));
+ &= (~((uint32_t)0x1U << resId));
if (edma3RegionId == rmInstance->initParam.regionId)
{
- allocatedTCCs[edma3Id][0u] &= (~(0x1u << resId));
+ allocatedTCCs[edma3Id][0U] &= (~((uint32_t)0x1U << resId));
}
}
else
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- &= (~(0x1u << (resId-32u)));
+ &= (~((uint32_t)0x1U << (resId-32U)));
if (edma3RegionId == rmInstance->initParam.regionId)
{
- allocatedTCCs[edma3Id][1u] &= (~(0x1u << (resId -32u)));
+ allocatedTCCs[edma3Id][1U] &= (~((uint32_t)0x1U << (resId -32U)));
}
}
}
{
if (resId < rmObj->gblCfgParams.numPaRAMSets)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32U])&(resIdSet))!=FALSE)
{
- if (((~(rmInstance->avlblPaRAMSets [resId/32u]))&(resIdSet))!=FALSE)
+ if (((~(rmInstance->avlblPaRAMSets [resId/32U]))&(resIdSet))!=FALSE)
{
- rmInstance->avlblPaRAMSets [resId/32u] |= resIdSet;
+ rmInstance->avlblPaRAMSets [resId/32U] |= resIdSet;
result = EDMA3_RM_SOK;
}
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- uint32_t mappedPaRAMId=0u;
+ uint32_t mappedPaRAMId=0U;
uint32_t mappedTcc = EDMA3_RM_CH_NO_TCC_MAP;
int32_t paRAMId = (int32_t)EDMA3_RM_RES_ANY;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
if (TRUE == rmInstance->regModificationRequired)
{
*((&gblRegs->PARAMENTRY[chObj->resId].OPT)
- + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFU;
}
}
}
break;
default:
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
/* Remove any linking */
*((&gblRegs->PARAMENTRY[*pParam].OPT)
- + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFU;
}
}
else
/* Remove any linking */
*((&gblRegs->PARAMENTRY[*pParam].OPT)
- + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFU;
/* Enable the transfer also. */
- rmInstance->shadowRegs->QEESR = (1u << chObj->resId);
+ rmInstance->shadowRegs->QEESR = (1U << chObj->resId);
}
}
else
/* It should be owned and allocated by this RM only. */
if (result == EDMA3_RM_SOK)
{
- if (((rmConfig->ownDmaChannels[dmaChId/32u])
+ if (((rmConfig->ownDmaChannels[dmaChId/32U])
&
- (~(rmInstance->avlblDmaChannels[dmaChId/32u]))
+ (~(rmInstance->avlblDmaChannels[dmaChId/32U]))
&
- (1u << (dmaChId%32u))) != FALSE)
+ ((uint32_t)1U << (dmaChId%32U))) != FALSE)
{
/** Perfectly valid channel id.
* Clear some channel specific registers, if it is permitted.
*/
if (TRUE == rmInstance->regModificationRequired)
{
- if (dmaChId < 32u)
+ if (dmaChId < 32U)
{
- if((rmInstance->shadowRegs->SER & (1u<<dmaChId))!=FALSE)
+ if((rmInstance->shadowRegs->SER & ((uint32_t)1U<<dmaChId))!=FALSE)
{
- rmInstance->shadowRegs->SECR = (1u<<dmaChId);
+ rmInstance->shadowRegs->SECR = (1U<<dmaChId);
}
- if((globalRegs->EMR & (1u<<dmaChId))!=FALSE)
+ if((globalRegs->EMR & ((uint32_t)1U<<dmaChId))!=FALSE)
{
- globalRegs->EMCR = (1u<<dmaChId);
+ globalRegs->EMCR = (1U<<dmaChId);
}
}
else
{
- if((rmInstance->shadowRegs->SERH & (1u<<(dmaChId-32u)))!=FALSE)
+ if((rmInstance->shadowRegs->SERH & ((uint32_t)1U<<(dmaChId-32U)))!=FALSE)
{
- rmInstance->shadowRegs->SECRH = (1u<<(dmaChId-32u));
+ rmInstance->shadowRegs->SECRH = (1U<<(dmaChId-32U));
}
- if((globalRegs->EMRH & (1u<<(dmaChId-32u)))!=FALSE)
+ if((globalRegs->EMRH & ((uint32_t)1U<<(dmaChId-32U)))!=FALSE)
{
- globalRegs->EMCRH = (1u<<(dmaChId-32u));
+ globalRegs->EMCRH = (1U<<(dmaChId-32U));
}
}
/* It should be owned and allocated by this RM only. */
if (result == EDMA3_RM_SOK)
{
- if (((rmConfig->ownQdmaChannels[0u])
+ if (((rmConfig->ownQdmaChannels[0U])
&
- (~(rmInstance->avlblQdmaChannels[0u]))
+ (~(rmInstance->avlblQdmaChannels[0U]))
&
- (1u << chObj->resId)) != FALSE)
+ ((uint32_t)1U << chObj->resId)) != FALSE)
{
/** Perfectly valid channel id.
* Clear some channel specific registers, if
*/
if (TRUE == rmInstance->regModificationRequired)
{
- rmInstance->shadowRegs->QEECR = (1u<<chObj->resId);
+ rmInstance->shadowRegs->QEECR = (1U<<chObj->resId);
- if((globalRegs->QEMR & (1u<<chObj->resId))!=FALSE)
+ if((globalRegs->QEMR & ((uint32_t)1U<<chObj->resId))!=FALSE)
{
- globalRegs->QEMCR = (1u<<chObj->resId);
+ globalRegs->QEMCR = (1U<<chObj->resId);
}
/* Unmap PARAM Set Number for specified channelId */
break;
default:
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
/* DMA channel and PaRAM Set should be previously allocated. */
if (result == EDMA3_RM_SOK)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[channelId/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[channelId/32U])
&
- (~(rmInstance->avlblDmaChannels[channelId/32u]))
+ (~(rmInstance->avlblDmaChannels[channelId/32U]))
&
- (1u << (channelId%32u))) != FALSE)
+ ((uint32_t)1U << (channelId%32U))) != FALSE)
{
/* DMA channel allocated, check for the PaRAM Set */
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32U])
&
- (~(rmInstance->avlblPaRAMSets[paRAMId/32u]))
+ (~(rmInstance->avlblPaRAMSets[paRAMId/32U]))
&
- (1u << (paRAMId%32u))) == FALSE)
+ ((uint32_t)1U << (paRAMId%32U))) == FALSE)
{
/* PaRAM Set NOT allocated, return error */
result = EDMA3_RM_E_RES_NOT_ALLOCATED;
/* QDMA channel and PaRAM Set should be previously allocated. */
if (result == EDMA3_RM_SOK)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[channelId/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[channelId/32U])
&
- (~(rmInstance->avlblQdmaChannels[channelId/32u]))
+ (~(rmInstance->avlblQdmaChannels[channelId/32U]))
&
- (1u << (channelId%32u))) != FALSE)
+ ((uint32_t)1U << (channelId%32U))) != FALSE)
{
/* QDMA channel allocated, check for the PaRAM Set */
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32U])
&
- (~(rmInstance->avlblPaRAMSets[paRAMId/32u]))
+ (~(rmInstance->avlblPaRAMSets[paRAMId/32U]))
&
- (1u << (paRAMId%32u))) == FALSE)
+ ((uint32_t)1U << (paRAMId%32U))) == FALSE)
{
/* PaRAM Set NOT allocated, return error */
result = EDMA3_RM_E_RES_NOT_ALLOCATED;
{
/* Enable the interrupts in IESR/IESRH */
- if (tcc < 32u)
+ if (tcc < 32U)
{
rmInstance->shadowRegs->IESR = (1UL << tcc);
}
else
{
- rmInstance->shadowRegs->IESRH = (1UL << (tcc-32u));
+ rmInstance->shadowRegs->IESRH = (1UL << (tcc-32U));
}
/* Save the callback functions also */
{
/* Remove the callback function too */
- if (mappedTcc < 32u)
+ if (mappedTcc < 32U)
{
rmInstance->shadowRegs->IECR = (1UL << mappedTcc);
}
- else if(mappedTcc < 64)
+ else if(mappedTcc < 64U)
+ {
+ rmInstance->shadowRegs->IECRH = (1UL << (mappedTcc-32U));
+ }
+ else
{
- rmInstance->shadowRegs->IECRH = (1UL << (mappedTcc-32u));
+ /* To Comply MISRA C warning */
+ result = EDMA3_RM_SOK;
}
if(mappedTcc < EDMA3_MAX_TCC)
@@ -3430,17 +3437,18 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_ResDesc *resObj = NULL;
- uint32_t resAllocIdx = 0u;
+ uint32_t resAllocIdx = 0U;
uint32_t firstResId;
- uint32_t lastResId = 0u;
- uint32_t maxNumResources = 0u;
+ uint32_t lastResId = 0U;
+ uint32_t maxNumResources = 0U;
EDMA3_RM_Result semResult = EDMA3_RM_SOK;
uint32_t resIdClr = 0x0;
uint32_t resIdSet = 0x0;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
- uint32_t i = 0u;
- uint32_t position = 0u;
+ uint32_t i = 0U;
+ uint32_t position = 0U;
uint32_t edma3Id;
+ uint32_t errFlag=0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -3571,22 +3579,22 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (uint32_t)(~(1u << (resAllocIdx%32u)));
- resIdSet = (1u << (resAllocIdx%32u));
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resAllocIdx%32U)));
+ resIdSet = (1U << (resAllocIdx%32U));
/* Check whether it is owned or not */
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resAllocIdx/32u])&(resIdSet)) != FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resAllocIdx/32U])&(resIdSet)) != FALSE)
{
/* Now check if specified resource is available presently*/
- if (((rmInstance->avlblDmaChannels[resAllocIdx/32u])&(resIdSet)) != FALSE)
+ if (((rmInstance->avlblDmaChannels[resAllocIdx/32U])&(resIdSet)) != FALSE)
{
/*
* Mark the specified resource as "Not Available"
* for future requests
*/
- rmInstance->avlblDmaChannels[resAllocIdx/32u] &= resIdClr;
+ rmInstance->avlblDmaChannels[resAllocIdx/32U] &= resIdClr;
- if (resAllocIdx < 32u)
+ if (resAllocIdx < 32U)
{
rmInstance->shadowRegs->EECR = (1UL << resAllocIdx);
@@ -3595,18 +3603,18 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* DRAE registers also.
*/
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << resAllocIdx);
+ |= ((uint32_t)0x1U << resAllocIdx);
}
else
{
- rmInstance->shadowRegs->EECRH = (1UL << (resAllocIdx - 32u));
+ rmInstance->shadowRegs->EECRH = (1UL << (resAllocIdx - 32U));
/**
* Enable the DMA channel in the
* DRAEH registers also.
*/
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (resAllocIdx - 32u));
+ |= ((uint32_t)0x1U << (resAllocIdx - 32U));
}
result = EDMA3_RM_SOK;
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
@@ -3625,7 +3633,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
@@ -3636,27 +3648,27 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (uint32_t)(~(1u << resAllocIdx));
- resIdSet = (1u << resAllocIdx);
+ resIdClr = (uint32_t)(~((uint32_t)1U << resAllocIdx));
+ resIdSet = (1U << resAllocIdx);
/* Check whether it is owned or not */
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U])&(resIdSet))!=FALSE)
{
/* Now check if specified resource is available presently*/
- if (((rmInstance->avlblQdmaChannels[0u])&(resIdSet))!=FALSE)
+ if (((rmInstance->avlblQdmaChannels[0U])&(resIdSet))!=FALSE)
{
/*
* Mark the specified resource as "Not Available"
* for future requests
*/
- rmInstance->avlblQdmaChannels[0u] &= resIdClr;
+ rmInstance->avlblQdmaChannels[0U] &= resIdClr;
/**
* Enable the QDMA channel in the
* QRAE register also.
*/
gblRegs->QRAE[rmInstance->initParam.regionId]
- |= (0x1u << resAllocIdx);
+ |= ((uint32_t)0x1U << resAllocIdx);
result = EDMA3_RM_SOK;
}
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
@@ -3674,7 +3686,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
@@ -3685,20 +3701,20 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (uint32_t)(~(1u << (resAllocIdx%32u)));
- resIdSet = (1u << (resAllocIdx%32u));
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resAllocIdx%32U)));
+ resIdSet = (1U << (resAllocIdx%32U));
/* Check whether it is owned or not */
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs[resAllocIdx/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs[resAllocIdx/32U])&(resIdSet))!=FALSE)
{
/* Now check if specified resource is available presently*/
- if (((rmInstance->avlblTccs[resAllocIdx/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->avlblTccs[resAllocIdx/32U])&(resIdSet))!=FALSE)
{
/*
* Mark the specified resource as "Not Available"
* for future requests
*/
- rmInstance->avlblTccs[resAllocIdx/32u] &= resIdClr;
+ rmInstance->avlblTccs[resAllocIdx/32U] &= resIdClr;
/**
* If the region id coming from this
@@ -3709,13 +3725,13 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
*/
if (edma3RegionId == rmInstance->initParam.regionId)
{
- if (resAllocIdx < 32u)
+ if (resAllocIdx < 32U)
{
- allocatedTCCs[edma3Id][0u] |= (0x1u << resAllocIdx);
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << resAllocIdx);
}
else
{
- allocatedTCCs[edma3Id][1u] |= (0x1u << (resAllocIdx - 32u));
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (resAllocIdx - 32U));
}
}
result = EDMA3_RM_SOK;
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
@@ -3734,7 +3750,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
@@ -3745,20 +3765,20 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (uint32_t)(~(1u << (resAllocIdx%32u)));
- resIdSet = (1u << (resAllocIdx%32u));
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resAllocIdx%32U)));
+ resIdSet = (1U << (resAllocIdx%32U));
/* Check whether it is owned or not */
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resAllocIdx/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resAllocIdx/32U])&(resIdSet))!=FALSE)
{
/* Now check if specified resource is available presently*/
- if (((rmInstance->avlblPaRAMSets[resAllocIdx/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->avlblPaRAMSets[resAllocIdx/32U])&(resIdSet))!=FALSE)
{
/*
* Mark the specified resource as "Not Available"
* for future requests
*/
- rmInstance->avlblPaRAMSets[resAllocIdx/32u] &= resIdClr;
+ rmInstance->avlblPaRAMSets[resAllocIdx/32U] &= resIdClr;
/**
* Also, make the actual PARAM Set NULL, checking the flag
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
@@ -3786,7 +3806,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
@@ -3828,13 +3852,13 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
case EDMA3_RM_RES_DMA_CHANNEL:
{
/* AND all the arrays to look into */
- contiguousDmaRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0u]
- & rmInstance->avlblDmaChannels[0u])
- & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[0u]))
+ contiguousDmaRes[0U] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0U]
+ & rmInstance->avlblDmaChannels[0U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[0U]))
);
- contiguousDmaRes[1u] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1u]
- & rmInstance->avlblDmaChannels[1u])
- & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[1u]))
+ contiguousDmaRes[1U] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1U]
+ & rmInstance->avlblDmaChannels[1U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[1U]))
);
}
break;
case EDMA3_RM_RES_QDMA_CHANNEL:
{
/* AND all the arrays to look into */
- contiguousQdmaRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u]
- & rmInstance->avlblQdmaChannels[0u])
- & (~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[0u]))
+ contiguousQdmaRes[0U] = ((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U]
+ & rmInstance->avlblQdmaChannels[0U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[0U]))
);
}
break;
@@ -3852,13 +3876,13 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
case EDMA3_RM_RES_TCC:
{
/* AND all the arrays to look into */
- contiguousTccRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[0u]
- & rmInstance->avlblTccs[0u])
- & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[0u]))
+ contiguousTccRes[0U] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[0U]
+ & rmInstance->avlblTccs[0U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[0U]))
);
- contiguousTccRes[1u] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[1u]
- & rmInstance->avlblTccs[1u])
- & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[1u]))
+ contiguousTccRes[1U] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[1U]
+ & rmInstance->avlblTccs[1U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[1U]))
);
}
break;
case EDMA3_RM_RES_PARAM_SET:
{
/* AND all the arrays to look into */
- for (i = 0u; i < (maxNumResources/32u); ++i)
+ for (i = 0U; i < (maxNumResources/32U); ++i)
{
contiguousParamRes[i] = ((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[i]
& rmInstance->avlblPaRAMSets[i])
@@ -3949,10 +3973,10 @@ EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_ResDesc *resObj;
- uint32_t resFreeIdx = 0u;
+ uint32_t resFreeIdx = 0U;
uint32_t firstResId;
uint32_t lastResId;
- uint32_t maxNumResources = 0u;
+ uint32_t maxNumResources = 0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
if (resObj != NULL)
{
firstResId = resObj->resId;
- lastResId = firstResId + (numResources - 1u);
+ lastResId = firstResId + (numResources - 1U);
}
switch (resObj->type)
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- volatile uint32_t regPhyAddr = 0x0u;
+ volatile uint32_t regPhyAddr = 0x0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
- if ((hEdmaResMgr == NULL) || ((regOffset % 4u) != 0))
+ if ((hEdmaResMgr == NULL) || ((regOffset % 4U) != 0))
{
result = (EDMA3_RM_E_INVALID_PARAM);
}
{
/* Semaphore taken successfully, modify the registers. */
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
&intState);
/* Global interrupts disabled, modify the registers. */
regPhyAddr = (uint32_t)(rmObj->gblCfgParams.globalRegs) + regOffset;
*(uint32_t *)regPhyAddr = newRegValue;
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
/* Return the semaphore back */
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- volatile uint32_t regPhyAddr = 0x0u;
+ volatile uint32_t regPhyAddr = 0x0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
if (((hEdmaResMgr == NULL) || (regValue == NULL))
- || ((regOffset % 4u) != 0))
+ || ((regOffset % 4U) != 0))
{
result = (EDMA3_RM_E_INVALID_PARAM);
}
EDMA3_RM_Obj *rmObj = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- uint32_t tccBitMask = 0x0u;
+ uint32_t tccBitMask = 0x0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
if (shadowRegs != NULL)
{
- if(tccNo < 32u)
+ if(tccNo < 32U)
{
- tccBitMask = (1u << tccNo);
+ tccBitMask = (1U << tccNo);
/* Check the status of the IPR[tccNo] bit. */
- while (FALSE == (shadowRegs->IPR & tccBitMask))
+ while ((uint32_t)FALSE == (shadowRegs->IPR & tccBitMask))
{
/* Transfer not yet completed, bit not SET */
}
}
else
{
- tccBitMask = (1u << (tccNo - 32u));
+ tccBitMask = (1U << (tccNo - 32U));
/* Check the status of the IPRH[tccNo-32] bit. */
- while (FALSE == (shadowRegs->IPRH & tccBitMask))
+ while ((uint32_t)FALSE == (shadowRegs->IPRH & tccBitMask))
{
/* Transfer not yet completed, bit not SET */
}
EDMA3_RM_Obj *rmObj = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- uint32_t tccBitMask = 0x0u;
+ uint32_t tccBitMask = 0x0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
if (shadowRegs != NULL)
{
- if(tccNo < 32u)
+ if(tccNo < 32U)
{
- tccBitMask = (1u << tccNo);
+ tccBitMask = (1U << tccNo);
/* Check the status of the IPR[tccNo] bit. */
if ((shadowRegs->IPR & tccBitMask) != FALSE)
}
else
{
- tccBitMask = (1u << (tccNo - 32u));
+ tccBitMask = (1U << (tccNo - 32U));
/* Check the status of the IPRH[tccNo-32] bit. */
if ((shadowRegs->IPRH & tccBitMask) != FALSE)
}
EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
const EDMA3_RM_PaRAMRegs *newPaRAM)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int32_t paRAMId = 0u;
- uint32_t qdmaChId = 0u;
+ int32_t paRAMId = 0;
+ uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
uint32_t edma3Id;
break;
default:
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
if ((paRAMId != -1) && ((uint32_t)paRAMId < edma3NumPaRAMSets))
{
/* Set the PaRAM Set now. */
- edma3ParamCpy ((void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)),
+ edma3ParamCpy ((volatile void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)),
(const void *)newPaRAM);
}
else
}
EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
EDMA3_RM_PaRAMRegs *currPaRAM)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int32_t paRAMId = 0u;
- uint32_t qdmaChId = 0u;
+ int32_t paRAMId = 0;
+ uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
uint32_t edma3Id;
break;
default:
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
if (result == EDMA3_RM_SOK)
{
/* Check the param id first. */
- if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets))
+ if ((paRAMId != -1) && ((uint32_t)paRAMId < edma3NumPaRAMSets))
{
/* Get the PaRAM Set now. */
edma3ParamCpy ((void *)currPaRAM ,
- (const void *)(&(globalRegs->PARAMENTRY [paRAMId].OPT)));
+ (const volatile void *)(&(globalRegs->PARAMENTRY [paRAMId].OPT)));
}
else
{
}
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
uint32_t *paramPhyAddr)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int32_t paRAMId = 0u;
- uint32_t qdmaChId = 0u;
+ int32_t paRAMId = 0;
+ uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
uint32_t edma3Id;
break;
default:
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
if (result == EDMA3_RM_SOK)
{
/* Check the param id first. */
- if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets))
+ if ((paRAMId != -1) && (paRAMId < (int32_t)edma3NumPaRAMSets))
{
/* Get the PaRAM Set Address now. */
*paramPhyAddr = (uint32_t)(&(globalRegs->PARAMENTRY [paRAMId].OPT));
* Since the TCs enum start from 1, and TCs start from 0,
* subtract 1 from the enum to get the actual address.
*/
- *phyAddress = (uint32_t)(rmObj->gblCfgParams.tcRegs[controllerId-1u]);
+ *phyAddress = (uint32_t)(rmObj->gblCfgParams.tcRegs[controllerId-1U]);
}
}
}
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- uint32_t resMgrIdx = 0u;
+ uint32_t resMgrIdx = 0U;
uint32_t hwId;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
{
hwId = rmObj->phyCtrllerInstId;
- for (resMgrIdx = 0u; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)
+ for (resMgrIdx = 0U; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)
{
if (rmInstance == ((EDMA3_RM_Instance *)(ptrRMIArray) +
(hwId*EDMA3_MAX_RM_INSTANCES) +
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
- uint32_t paramInitRequired = 0xFFu;
- uint32_t regModificationRequired = 0xFFu;
+ uint32_t paramInitRequired = 0xFFU;
+ uint32_t regModificationRequired = 0xFFU;
uint32_t *ret_val = NULL;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
}
}
- /* To remove CCS warnings */
- (void)param;
-
if (result == EDMA3_RM_SOK)
{
switch (cmd)
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
- if ((paramInitRequired != 0u)
- && (paramInitRequired != 1u))
+ if ((paramInitRequired != 0U)
+ && (paramInitRequired != 1U))
{
result = EDMA3_RM_E_INVALID_PARAM;
}
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
- if ((regModificationRequired != 0u)
- && (regModificationRequired != 1u))
+ if ((regModificationRequired != 0U)
+ && (regModificationRequired != 1U))
{
/* All other values are invalid. */
result = EDMA3_RM_E_INVALID_PARAM;
}
default:
- /* Hey dude! you passed invalid IOCTL cmd */
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ /* Hey dude! you passed invalid IOCTL cmd */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
(&ptrEdmaccRegs->SHADOW[edma3RegionId]);
}
- Cnt = 0u;
- pendingIrqs = 0u;
- indexl = 1u;
- indexh = 1u;
+ Cnt = 0U;
+ pendingIrqs = 0U;
+ indexl = 1U;
+ indexh = 1U;
- if (numTCCs > 32)
+ if (numTCCs > 32U)
+ {
isIPR = shadowRegs->IPR | shadowRegs->IPRH;
+ }
else
- isIPR = shadowRegs->IPR;
-
+ {
+ isIPR = shadowRegs->IPR;
+ }
if(isIPR)
{
/**
*/
edma3OsProtectEntry (edma3Id,
- EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
NULL);
/* Loop for EDMA3_RM_COMPL_HANDLER_RETRY_COUNT number of time,
breaks when no pending interrupt is found */
while ((Cnt < EDMA3_RM_COMPL_HANDLER_RETRY_COUNT)
- && ((indexl != 0u) || (indexh != 0u)))
+ && ((indexl != 0U) || (indexh != 0U)))
{
- indexl = 0u;
+ indexl = 0U;
pendingIrqs = shadowRegs->IPR;
/**
* Choose interrupts coming from our allocated TCCs
* and MASK remaining ones.
*/
- pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][0u]);
+ pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][0U]);
while (pendingIrqs)
{
/*Process all the pending interrupts*/
- if((pendingIrqs & 1u) == TRUE)
+ if((pendingIrqs & 1U) == TRUE)
{
/**
* If the user has not given any callback function
if(edma3IntrParams[edma3Id][indexl].tccCb != NULL)
{
/* here write to ICR to clear the corresponding IPR bits*/
- shadowRegs->ICR = (1u << indexl);
+ shadowRegs->ICR = (1U << indexl);
edma3IntrParams[edma3Id][indexl].tccCb (indexl,
EDMA3_RM_XFER_COMPLETE,
}
}
++indexl;
- pendingIrqs >>= 1u;
+ pendingIrqs >>= 1U;
}
- if(numTCCs > 32)
+ if(numTCCs > 32U)
{
- indexh = 0u;
+ indexh = 0U;
pendingIrqs = shadowRegs->IPRH;
/**
* Choose interrupts coming from our allocated TCCs
* and MASK remaining ones.
*/
- pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][1u]);
+ pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][1U]);
while (pendingIrqs)
{
/*Process all the pending interrupts*/
- if((pendingIrqs & 1u)==TRUE)
+ if((pendingIrqs & 1U)==TRUE)
{
/**
* If the user has not given any callback function
* while requesting the TCC, its TCC specific bit
* in the IPRH register will NOT be cleared.
*/
- if(edma3IntrParams[edma3Id][32u+indexh].tccCb!=NULL)
+ if(edma3IntrParams[edma3Id][32U+indexh].tccCb!=NULL)
{
/* here write to ICR to clear the corresponding IPR bits*/
- shadowRegs->ICRH = (1u << indexh);
-
- edma3IntrParams[edma3Id][32u+indexh].tccCb(32u+indexh,
+ shadowRegs->ICRH = (1U << indexh);
+
+ edma3IntrParams[edma3Id][32U+indexh].tccCb(32U+indexh,
EDMA3_RM_XFER_COMPLETE,
- edma3IntrParams[edma3Id][32u+indexh].cbData);
+ edma3IntrParams[edma3Id][32U+indexh].cbData);
}
}
++indexh;
- pendingIrqs >>= 1u;
+ pendingIrqs >>= 1U;
}
}
Cnt++;
}
- indexl = (shadowRegs->IPR & allocatedTCCs[edma3Id][0u]);
- if (numTCCs > 32)
- indexh = (shadowRegs->IPRH & allocatedTCCs[edma3Id][1u]);
+ indexl = (shadowRegs->IPR & allocatedTCCs[edma3Id][0U]);
+ if (numTCCs > 32U)
+ {
+ indexh = (shadowRegs->IPRH & allocatedTCCs[edma3Id][1U]);
+ }
if((indexl !=0 ) || (indexh !=0 ))
{
- shadowRegs->IEVAL=0x1u;
+ shadowRegs->IEVAL=0x1U;
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
- NULL);
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
+ 0);
}
#ifdef EDMA3_INSTRUMENTATION_ENABLED
*/
static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
{
- uint32_t Cnt = 0u;
- uint32_t resMgrInstIdx = 0u;
+ uint32_t Cnt = 0U;
+ uint32_t resMgrInstIdx = 0U;
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
volatile uint32_t pendingIrqs = 0;
+ (edma3Id*EDMA3_MAX_RM_INSTANCES)
+ edma3RegionId);
- pendingIrqs = ((ptrEdmaccRegs->EMR != 0 )
- || (ptrEdmaccRegs->QEMR != 0)
- || (ptrEdmaccRegs->CCERR != 0));
- if (numTCCs > 32)
+ if((ptrEdmaccRegs->EMR != 0 )
+ || (ptrEdmaccRegs->QEMR != 0)
+ || (ptrEdmaccRegs->CCERR != 0))
{
- pendingIrqs = pendingIrqs || (ptrEdmaccRegs->EMRH != 0 );
+ pendingIrqs = 1U;
}
- index = 1u;
+ if (numTCCs > 32U)
+ {
+ if((pendingIrqs != 0) || (ptrEdmaccRegs->EMRH != 0))
+ {
+ pendingIrqs = 1U;
+ }
+ }
+ index = 1U;
if(pendingIrqs)
{
edma3OsProtectEntry (edma3Id,
- EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
NULL);
/* Loop for EDMA3_RM_CCERR_HANDLER_RETRY_COUNT number of time,
breaks when no pending interrupt is found */
while ((Cnt < EDMA3_RM_CCERR_HANDLER_RETRY_COUNT)
- && (index != 0u))
+ && (index != 0U))
{
- index = 0u;
+ index = 0U;
pendingIrqs = ptrEdmaccRegs->EMR;
while (pendingIrqs)
{
/*Process all the pending interrupts*/
- if((pendingIrqs & 1u)==TRUE)
+ if((pendingIrqs & 1U)==TRUE)
{
- uint32_t mappedTcc = 0u;
+ uint32_t mappedTcc = 0U;
/**
* Using the 'index' value (basically the DMA
* TCC owned and allocated by RM.
* Write to EMCR to clear the corresponding EMR bits.
*/
- ptrEdmaccRegs->EMCR = (1u<<index);
+ ptrEdmaccRegs->EMCR = (1U<<index);
/*Clear any SER*/
- shadowRegs->SECR = (1u<<index);
+ shadowRegs->SECR = (1U<<index);
/* Call the callback function if registered earlier. */
if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
*/
#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)
/* here write to EMCR to clear the corresponding EMR bits. */
- ptrEdmaccRegs->EMCR = (1u<<index);
+ ptrEdmaccRegs->EMCR = (1U<<index);
/*Clear any SER*/
- ptrEdmaccRegs->SECR = (1u<<index);
+ ptrEdmaccRegs->SECR = (1U<<index);
#endif
}
}
++index;
- pendingIrqs >>= 1u;
+ pendingIrqs >>= 1U;
}
- if(numTCCs > 32)
+ if(numTCCs > 32U)
{
- index = 0u;
+ index = 0U;
pendingIrqs = ptrEdmaccRegs->EMRH;
while (pendingIrqs)
{
/*Process all the pending interrupts*/
- if((pendingIrqs & 1u)==TRUE)
+ if((pendingIrqs & 1U)==TRUE)
{
- uint32_t mappedTcc = 0u;
+ uint32_t mappedTcc = 0U;
/**
* Using the 'index' value (basically the DMA
* channel), fetch the corresponding TCC
* value, mapped to this DMA channel.
*/
- mappedTcc = edma3DmaChTccMapping[edma3Id][32u+index];
+ mappedTcc = edma3DmaChTccMapping[edma3Id][32U+index];
/**
* Ensure that the mapped tcc is valid and the call
* TCC owned and allocated by RM.
* Write to EMCR to clear the corresponding EMR bits.
*/
- ptrEdmaccRegs->EMCRH = (1u<<index);
+ ptrEdmaccRegs->EMCRH = (1U<<index);
/*Clear any SERH*/
- shadowRegs->SECRH = (1u<<index);
+ shadowRegs->SECRH = (1U<<index);
/* Call the callback function if registered earlier. */
if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
* TCC NOT owned by RM.
* Write to EMCRH to clear the corresponding EMRH bits.
*/
- ptrEdmaccRegs->EMCRH = (1u<<index);
+ ptrEdmaccRegs->EMCRH = (1U<<index);
/*Clear any SERH*/
- shadowRegs->SECRH = (1u<<index);
+ shadowRegs->SECRH = (1U<<index);
#endif
}
}
++index;
- pendingIrqs >>= 1u;
+ pendingIrqs >>= 1U;
}
}
- index = 0u;
+ index = 0U;
pendingIrqs = ptrEdmaccRegs->QEMR;
while (pendingIrqs)
{
/*Process all the pending interrupts*/
- if((pendingIrqs & 1u)==TRUE)
+ if((pendingIrqs & 1U)==TRUE)
{
- uint32_t mappedTcc = 0u;
+ uint32_t mappedTcc = 0U;
/**
* Using the 'index' value (basically the QDMA
if (mappedTcc < EDMA3_MAX_TCC)
{
/* here write to QEMCR to clear the corresponding QEMR bits*/
- ptrEdmaccRegs->QEMCR = (1u<<index);
+ ptrEdmaccRegs->QEMCR = (1U<<index);
/*Clear any QSER*/
- shadowRegs->QSECR = (1u<<index);
+ shadowRegs->QSECR = (1U<<index);
if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
{
*/
#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)
/* here write to QEMCR to clear the corresponding QEMR bits*/
- ptrEdmaccRegs->QEMCR = (1u<<index);
+ ptrEdmaccRegs->QEMCR = (1U<<index);
/*Clear any QSER*/
- ptrEdmaccRegs->QSECR = (1u<<index);
+ ptrEdmaccRegs->QSECR = (1U<<index);
#endif
}
}
++index;
- pendingIrqs >>= 1u;
+ pendingIrqs >>= 1U;
}
- index = 0u;
+ index = 0U;
pendingIrqs = ptrEdmaccRegs->CCERR;
- if (pendingIrqs!=NULL)
+ if (pendingIrqs!=0)
{
/* Process all the pending CC error interrupts. */
/* Queue threshold error for different event queues.*/
- for (evtqueNum = 0u; evtqueNum < rmObj->gblCfgParams.numEvtQueue; evtqueNum++)
+ for (evtqueNum = 0U; evtqueNum < rmObj->gblCfgParams.numEvtQueue; evtqueNum++)
{
- if((pendingIrqs & (1u << evtqueNum)) != NULL)
+ if((pendingIrqs & ((uint32_t)1U << evtqueNum)) != 0)
{
/**
* Queue threshold error for queue 'evtqueNum' raised.
* Inform all the RM instances working on this region
* about the error by calling their global callback functions.
*/
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
/* Clear the error interrupt. */
- ptrEdmaccRegs->CCERRCLR = (1u << evtqueNum);
+ ptrEdmaccRegs->CCERRCLR = (1U << evtqueNum);
}
}
/* Transfer completion code error. */
- if ((pendingIrqs & (1 << EDMA3_CCRL_CCERR_TCCERR_SHIFT))!=NULL)
+ if ((pendingIrqs & ((uint32_t)1 << EDMA3_CCRL_CCERR_TCCERR_SHIFT))!=0)
{
/**
* Transfer completion code error raised.
* Inform all the RM instances working on this region
* about the error by calling their global callback functions.
*/
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
{
rm_instance->initParam.gblerrCbParams.gblerrCb(
EDMA3_RM_E_CC_TCC,
- NULL,
+ 0,
rm_instance->initParam.gblerrCbParams.gblerrData);
}
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
- ptrEdmaccRegs->CCERRCLR = (1<<EDMA3_CCRL_CCERR_TCCERR_SHIFT);
+ ptrEdmaccRegs->CCERRCLR = ((uint32_t)1<<EDMA3_CCRL_CCERR_TCCERR_SHIFT);
}
++index;
/* Check all the error bits. */
ownedDmaError = ptrEdmaccRegs->EMR;
- if (numTCCs > 32)
+ if (numTCCs > 32U)
+ {
ownedDmaHError = ptrEdmaccRegs->EMRH;
+ }
ownedQdmaError = ptrEdmaccRegs->QEMR;
#else
/* Check ONLY owned error bits. */
- ownedDmaError = (ptrEdmaccRegs->EMR & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0u]);
+ ownedDmaError = (ptrEdmaccRegs->EMR & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0U]);
if (numTCCs > 32)
- ownedDmaHError = (ptrEdmaccRegs->EMRH & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1u]);
- ownedQdmaError = (ptrEdmaccRegs->QEMR & rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u]);
+ ownedDmaHError = (ptrEdmaccRegs->EMRH & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1U]);
+ ownedQdmaError = (ptrEdmaccRegs->QEMR & rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U]);
#endif
if (((ownedDmaError != 0 ) || (ownedDmaHError != 0 ))
|| ((ownedQdmaError != 0) || (ptrEdmaccRegs->CCERR != 0)))
{
- ptrEdmaccRegs->EEVAL=0x1u;
+ ptrEdmaccRegs->EEVAL=0x1U;
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
- NULL);
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
+ 0);
}
}
static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, uint32_t tcNum)
{
volatile EDMA3_TCRL_Regs *tcRegs = NULL;
- uint32_t tcMemErrRdWr = 0u;
- uint32_t resMgrInstIdx = 0u;
+ uint32_t tcMemErrRdWr = 0U;
+ uint32_t resMgrInstIdx = 0U;
EDMA3_RM_Instance *rm_instance = NULL;
uint32_t edma3Id;
uint32_t num_rm_instances_opened;
if(tcRegs->ERRSTAT != 0)
{
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
&tcNum);
- if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT))!=NULL)
+ if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT))!= 0)
{
/* Bus error event. */
/**
* address. Error information can be read from the error
* details register (ERRDET).
*/
- tcMemErrRdWr = tcRegs->ERRDET & (EDMA3_TCRL_ERRDET_STAT_MASK);
- if ((tcMemErrRdWr > 0u) && (tcMemErrRdWr < 8u))
+ tcMemErrRdWr = tcRegs->ERRDET & ((uint32_t)EDMA3_TCRL_ERRDET_STAT_MASK);
+ if ((tcMemErrRdWr > 0U) && (tcMemErrRdWr < 8U))
{
/**
* Inform all the RM instances working on this region
* about the error by calling their global callback functions.
*/
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
}
else
{
- if ((tcMemErrRdWr >= 8u) && (tcMemErrRdWr <= 0xFu))
+ if ((tcMemErrRdWr >= 8U) && (tcMemErrRdWr <= 0xFU))
{
/**
* Inform all the RM instances working on this region
* about the error by calling their global callback functions.
*/
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
}
}
- tcRegs->ERRCLR = (1<<EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT);
+ tcRegs->ERRCLR = ((uint32_t)1<<EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT);
}
else
{
/* Transfer request (TR) error event. */
- if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_TRERR_SHIFT))!=NULL)
+ if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_TRERR_SHIFT))!= 0)
{
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
- tcRegs->ERRCLR = (1<<EDMA3_TCRL_ERRSTAT_TRERR_SHIFT);
+ tcRegs->ERRCLR = ((uint32_t)1<<EDMA3_TCRL_ERRSTAT_TRERR_SHIFT);
}
else
{
- if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT))!=NULL)
+ if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT))!= 0)
{
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
- tcRegs->ERRCLR = (1<<EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT);
+ tcRegs->ERRCLR = ((uint32_t)1<<EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT);
}
}
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
tcNum);
}
}
void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC0*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 0u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)0U);
}
void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC1*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 1u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)1U);
}
/*
void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC2*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 2u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)2U);
}
/*
void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC3*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 3u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)3U);
}
/*
void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC4*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 4u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)4U);
}
void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC5*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 5u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)5U);
}
/*
void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC6*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 6u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)6U);
}
/*
void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC7*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 7u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)7U);
}
/** Initialization of the Global region registers of the EDMA3 Controller */
static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId, uint32_t numDmaChannels)
{
- uint32_t evtQNum = 0u;
+ uint32_t evtQNum = 0U;
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
assert (phyCtrllerInstId < EDMA3_MAX_EDMA3_INSTANCES);
@@ -6081,7 +6128,7 @@ static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId, uint32_t numDmaCha
if (ptrEdmaccRegs != NULL)
{
ptrEdmaccRegs->EMCR = EDMA3_RM_SET_ALL_BITS;
- if ( numDmaChannels > 32)
+ if ( numDmaChannels > 32U)
{
/* Clear the EMCRH only if available channels are more than 32 */
ptrEdmaccRegs->EMCRH = EDMA3_RM_SET_ALL_BITS;
@@ -6110,7 +6157,7 @@ static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId, uint32_t numDmaCha
}
/* Clear CCERR register */
- ptrEdmaccRegs ->CCERRCLR = 0xFFFFu;
+ ptrEdmaccRegs ->CCERRCLR = 0xFFFFU;
}
return;
ptrEdmaShadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)
(&ptrEdmaccRegs->SHADOW[regionId]);
- ptrEdmaShadowRegs->ECR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->ECRH = (rmInstInitConfig->ownDmaChannels[1u]
- | rmInstInitConfig->ownTccs[1u]);
- ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->SECR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->SECRH = (rmInstInitConfig->ownDmaChannels[1u]
- | rmInstInitConfig->ownTccs[1u]);
- ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->EECRH = (rmInstInitConfig->ownDmaChannels[1u]
- | rmInstInitConfig->ownTccs[1u]);
-
- ptrEdmaShadowRegs->QEECR = rmInstInitConfig->ownQdmaChannels[0u];
-
- ptrEdmaShadowRegs->IECR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->IECRH = (rmInstInitConfig->ownDmaChannels[1u]
- | rmInstInitConfig->ownTccs[1u]);
- ptrEdmaShadowRegs->ICR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->ICRH = (rmInstInitConfig->ownDmaChannels[1u]
- | rmInstInitConfig->ownTccs[1u]);
-
- ptrEdmaShadowRegs->QSECR = rmInstInitConfig->ownQdmaChannels[0u];
+ ptrEdmaShadowRegs->ECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->ECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+ ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->SECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->SECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+ ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->EECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+
+ ptrEdmaShadowRegs->QEECR = rmInstInitConfig->ownQdmaChannels[0U];
+
+ ptrEdmaShadowRegs->IECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->IECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+ ptrEdmaShadowRegs->ICR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->ICRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+
+ ptrEdmaShadowRegs->QSECR = rmInstInitConfig->ownQdmaChannels[0U];
/*
* Set all EDMA3 Resource<->Region mapping parameters
*/
/* 1. Dma Channel (and TCC) <-> Region */
- ptrEdmaccRegs->DRA[regionId].DRAE = 0u;
- ptrEdmaccRegs->DRA[regionId].DRAEH = 0u;
+ ptrEdmaccRegs->DRA[regionId].DRAE = 0U;
+ ptrEdmaccRegs->DRA[regionId].DRAEH = 0U;
/* 2. Qdma Channel <-> Region */
- ptrEdmaccRegs->QRAE[regionId] = 0u;
+ ptrEdmaccRegs->QRAE[regionId] = 0U;
}
}
/** Local MemZero function */
void edma3MemZero(void *dst, uint32_t len)
{
- uint32_t i = 0u;
+ uint32_t i = 0U;
uint32_t *ds = NULL;
assert (dst != NULL);
ds = (uint32_t *)dst;
- for (i = 0 ; i < len/4 ; i++)
+ for (i = 0U ; i < (len/4U) ; i++)
{
*ds = 0x0;
ds++;
/* Local MemCopy function */
void edma3MemCpy(void *dst, const void *src, uint32_t len)
{
- uint32_t i=0u;
+ uint32_t i=0U;
const uint32_t *sr;
uint32_t *ds;
- assert ((src != NULL) && (dst != NULL) && ((len)%4 == 0));
+ assert ((src != NULL) && (dst != NULL) && ((len%4) == 0));
sr = (const uint32_t *)src;
ds = (uint32_t *)dst;
- for (i = 0 ; i < len/4 ; i++)
+ for (i = 0U ; i < (len/4U) ; i++)
{
*ds = *sr;
ds++;
/* Local MemCopy function to copy Param Set ONLY */
-void edma3ParamCpy(void *dst, const void *src)
+void edma3ParamCpy(volatile void *dst, const volatile void *src)
{
- uint32_t i = 0u;
- const uint32_t *sr;
- uint32_t *ds;
+ uint32_t i = 0U;
+ const volatile uint32_t *sr;
+ volatile uint32_t *ds;
assert ((src != NULL) && (dst != NULL));
- sr = (const uint32_t *)src;
- ds = (uint32_t *)dst;
+ sr = (const volatile uint32_t *)src;
+ ds = (volatile uint32_t *)dst;
- for (i = 0; i < 8; i++)
+ for (i = 0U; i < 8U; i++)
{
*ds = *sr;
ds++;
uint32_t position = start;
uint16_t found = 0;
uint32_t iterations_left = 0;
+ uint32_t sourceTmp=0;
switch (bit)
{
- case 1:
+ case 1U:
{
- source >>= (start%32u);
+ sourceTmp = (uint32_t)source >> (start%32U);
+ source = (int32_t)sourceTmp;
- while ((found==0u) && (source!=0))
+ while ((found==0U) && (source!=0))
{
- if ((source & 0x1) == 0x1)
+ if (((uint32_t)source & 0x1U) == 0x1U)
{
/* 1 */
found++;
else
{
/* 0 */
- source >>= 1;
+ sourceTmp = (uint32_t)source >> 1;
+ source = (int32_t)sourceTmp;
position++;
}
}
case 0:
{
- source >>= (start%32u);
- iterations_left = 32u - (start%32u);
+ sourceTmp = (uint32_t)source >> (start%32U);
+ source = (int32_t)sourceTmp;
+ iterations_left = (uint32_t)32U - (start%32U);
- while ((found==0u) && (iterations_left>0u))
+ while ((found==0U) && (iterations_left>0U))
{
- if ((source & 0x1) == 0x1)
+ if (((uint32_t)source & 0x1U) == 0x1U)
{
/* 1 */
- source >>= 1;
+ sourceTmp = (uint32_t)source >> 1;
+ source = (int32_t)sourceTmp;
position++;
iterations_left--;
}
uint16_t bit)
{
int32_t position = -1;
- uint32_t start_index = start / 32u;
- uint32_t end_index = end / 32u;
+ uint32_t start_index = start / 32U;
+ uint32_t end_index = end / 32U;
int32_t i;
uint32_t *resPtr = 0x0;
int32_t ret = -1;
{
switch (bit)
{
- case 1:
+ case 1U:
{
/* Find '1' in first word. */
- position = findBitInWord (resPtr[start_index], start, 1u);
+ position = findBitInWord (resPtr[start_index], start, (uint16_t)1U);
if (position != -1)
{
else
{
/* '1' NOT found, look into other words. */
- for (i = (int32_t)(start_index + 1u); i <= (int32_t)(end_index - 1u); i++)
+ for (i = ((int32_t)start_index + (int32_t)1U); i <= ((int32_t)end_index - (int32_t)1U); i++)
{
- position = findBitInWord (resPtr[i], 0u, 1u);
+ position = findBitInWord (resPtr[i], (uint32_t)0U, (uint16_t)1U);
if (position != -1)
{
/* '1' Found... */
if (ret == -1)
{
/* Still not found, look in the last word. */
- position = findBitInWord(resPtr[end_index], 0u, 1u);
+ position = findBitInWord(resPtr[end_index], (uint32_t)0U, (uint16_t)1U);
if (position != -1)
{
/* Finally got it. */
- ret = (position + (end_index*32u));
+ ret = (position + ((int32_t)end_index*(int32_t)32U));
}
else
{
}
break;
- case 0:
+ case 0U:
{
/* Find '0' in first word. */
- position = findBitInWord(resPtr[start_index], start, 0u);
+ position = findBitInWord(resPtr[start_index], start, (uint16_t)0U);
if (position != -1)
{
ret = position;
else
{
/* '0' NOT found, look into other words. */
- for (i = (start_index + 1u); i <= (end_index - 1u); i++)
+ for (i = ((int32_t)start_index + (int32_t)1U); i <= ((int32_t)end_index - (int32_t)1U); i++)
{
- position = findBitInWord(resPtr[i], 0u, 0u);
+ position = findBitInWord(resPtr[i], (uint32_t)0U, (uint16_t)0U);
if (position != -1)
{
/* '0' found... */
/* First check whether we have found '0' or not. */
if (ret == -1)
{
- position = findBitInWord(resPtr[end_index], 0u, 0u);
+ position = findBitInWord(resPtr[end_index], (uint32_t)0U, (uint16_t)0U);
if (position != -1)
{
/* Finally got it. */
- ret = (position + (end_index*32u));
+ ret = (position + ((int32_t)end_index*(int32_t)32U));
}
else
{
- return ((ret >= start) ? ret : -1);
-}
+ return ((ret >= (int32_t)start) ? ret : -1);
+ }
uint32_t numResources,
uint32_t *positionRes)
{
- uint16_t found = 0u;
+ uint16_t found = 0U;
int32_t first_one, next_zero;
uint32_t num_available;
int32_t ret = -1;
switch (resType)
{
case EDMA3_RM_RES_DMA_CHANNEL:
- end = EDMA3_MAX_DMA_CH - 1u;
+ end = EDMA3_MAX_DMA_CH - 1U;
break;
case EDMA3_RM_RES_QDMA_CHANNEL:
- end = EDMA3_MAX_QDMA_CH - 1u;
+ end = EDMA3_MAX_QDMA_CH - 1U;
break;
case EDMA3_RM_RES_TCC:
- end = EDMA3_MAX_TCC - 1u;
+ end = EDMA3_MAX_TCC - 1U;
break;
case EDMA3_RM_RES_PARAM_SET:
- end = edma3NumPaRAMSets - 1u;
+ end = edma3NumPaRAMSets - 1U;
break;
default:
* Step d) If result < N, do the whole process again untill you
* reach end. Else you have found enough resources, return success.
*/
- while((found == 0) && (start<=end) && (((end-start)+1u) >= numResources))
+ while((found == 0) && (start<=end) && (((end-start)+1U) >= numResources))
{
/* Find first '1' starting from 'start' till 'end'. */
- first_one = findBit (resType, start, end, 1u);
+ first_one = findBit (resType, start, end, (uint16_t)1U);
if (first_one != -1)
{
/* Got first 1, search for first '0' now. */
- next_zero = findBit (resType, first_one+1, end, 0u);
+ next_zero = findBit (resType, (uint32_t)first_one+(uint32_t)1, end, (uint16_t)0U);
if (next_zero == -1)
{
/* Unable to find next zero, all 1' are there */
- next_zero = end + 1u;
+ next_zero = (int32_t)end + (int32_t)1U;
}
/* check no of resources available */
- num_available = next_zero - first_one;
+ num_available = (uint32_t)next_zero - (uint32_t)first_one;
if (num_available >= numResources)
{
/* hurrah..., we have found enough resources. */
- found = 1u;
+ found = 1U;
ret = first_one;
}
else
{
/* Not enough resources, try again */
- start = next_zero + 1;
+ start = (uint32_t)next_zero + (uint32_t)1;
}
}
else
if (result == EDMA3_RM_SOK)
{
- if (found == 1u)
+ if (found == 1U)
{
/* required resources found, retrun the first available res id. */
*positionRes = (uint32_t)ret;
EDMA3_RM_Result result = EDMA3_RM_SOK;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- uint32_t avlblIdx = 0u;
- uint32_t firstResId=0u;
- uint32_t lastResId=0u;
+ uint32_t avlblIdx = 0U;
+ uint32_t firstResId=0U;
+ uint32_t lastResId=0U;
uint32_t edma3Id;
assert ((rmInstance != NULL) && (firstResIdObj != NULL));
case EDMA3_RM_RES_DMA_CHANNEL:
{
firstResId = firstResIdObj->resId;
- lastResId = firstResId + (numResources - 1u);
+ lastResId = firstResId + (numResources - 1U);
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblDmaChannels[avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblDmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* Enable the DMA channel in the DRAE/DRAEH registers also.
*/
- if (avlblIdx < 32u)
+ if (avlblIdx < 32U)
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << avlblIdx);
+ |= ((uint32_t)0x1U << avlblIdx);
}
else
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (avlblIdx - 32u));
+ |= ((uint32_t)0x1U << (avlblIdx - 32U));
}
}
}
case EDMA3_RM_RES_QDMA_CHANNEL:
{
firstResId = firstResIdObj->resId;
- lastResId = firstResId + (numResources - 1u);
+ lastResId = firstResId + (numResources - 1U);
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblQdmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* Enable the QDMA channel in the QRAE register also.
*/
gblRegs->QRAE[rmInstance->initParam.regionId]
- |= (0x1u << avlblIdx);
+ |= ((uint32_t)0x1U << avlblIdx);
}
}
break;
case EDMA3_RM_RES_TCC:
{
firstResId = firstResIdObj->resId;
- lastResId = firstResId + (numResources - 1u);
+ lastResId = firstResId + (numResources - 1U);
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblTccs[avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblTccs[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* If the region id coming from this
*/
if (edma3RegionId == rmInstance->initParam.regionId)
{
- if (avlblIdx < 32u)
+ if (avlblIdx < 32U)
{
- allocatedTCCs[edma3Id][0u] |= (0x1u << avlblIdx);
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << avlblIdx);
}
else
{
- allocatedTCCs[edma3Id][1u] |= (0x1u << (avlblIdx - 32u));
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (avlblIdx - 32U));
}
}
}
case EDMA3_RM_RES_PARAM_SET:
{
firstResId = firstResIdObj->resId;
- lastResId = firstResId + (numResources - 1u);
+ lastResId = firstResId + (numResources - 1U);
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblPaRAMSets [avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* Also, make the actual PARAM Set NULL, checking the flag
}
-EDMA3_RM_Result EDMA3_RM_initXbarEventMap (EDMA3_RM_Handle hEdmaResMgr,
+EDMA3_RM_Result EDMA3_RM_initXbarEventMap (EDMA3_RM_Handle hEdma,
const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig,
EDMA3_RM_mapXbarEvtToChan mapXbarEvtFunc,
EDMA3_RM_xbarConfigScr configXbarScr)
/* If parameter checking is enabled... */
#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
- if (hEdmaResMgr == NULL)
+ if (hEdma == NULL)
{
result = EDMA3_RM_E_INVALID_PARAM;
}
/* Check if the parameters are OK. */
if (EDMA3_DRV_SOK == result)
{
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmInstance = (EDMA3_RM_Instance *)hEdma;
if (mapXbarEvtFunc != NULL)
{