diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.c b/packages/ti/sdo/edma3/rm/src/edma3resmgr.c
index 324377944563ab1df7a980abe2b20febd12cda93..e3f67e1f528235eaea0c15d61b5d949ab67669e3 100755 (executable)
* 'n' number of times.
* Minumum value is 1.
*/
-#define EDMA3_RM_COMPL_HANDLER_RETRY_COUNT (10u)
+#define EDMA3_RM_COMPL_HANDLER_RETRY_COUNT (10U)
/**
* \brief EDMA3 Resource Manager retry count to check the pending CC Error Interrupt inside ISR
* interrupt for 'n' number of times.
* Minumum value is 1.
*/
-#define EDMA3_RM_CCERR_HANDLER_RETRY_COUNT (10u)
+#define EDMA3_RM_CCERR_HANDLER_RETRY_COUNT (10U)
/**
* Maximum Resource Manager Instances supported by the EDMA3 Package.
*/
-extern const unsigned int EDMA3_MAX_RM_INSTANCES;
+extern const uint32_t EDMA3_MAX_RM_INSTANCES;
+#ifndef GENERIC
/**
* \brief Static Configuration structure for EDMA3
* controller, to provide Global SoC specific Information.
*/
extern EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+#endif
+
/**
* \brief Region Specific Configuration structure for
@@ -121,9 +124,13 @@ extern EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES]
* this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",
* for the specified platform.
*/
+#ifdef BUILD_C6XDSP
+extern far EDMA3_RM_InstanceInitConfig *userInitConfig;
+extern far EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
+#else
extern EDMA3_RM_InstanceInitConfig *userInitConfig;
extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
-
+#endif
/**
* Handles of EDMA3 Resource Manager Instances.
* There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per
* EDMA3 HW.
*/
-extern EDMA3_RM_Instance *resMgrInstance;
+#ifdef BUILD_C6XDSP
+extern far EDMA3_RM_Instance *resMgrInstance;
+extern far EDMA3_RM_Instance *ptrRMIArray;
+#else
extern EDMA3_RM_Instance *ptrRMIArray;
+extern EDMA3_RM_Instance *resMgrInstance;
+#endif
/** Max of DMA Channels */
-unsigned int edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
/** Min of Link Channels */
-unsigned int edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
/** Max of Link Channels */
-unsigned int edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
/** Min of QDMA Channels */
-unsigned int edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
/** Max of QDMA Channels */
-unsigned int edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
/** Max of Logical Channels */
-unsigned int edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
/* Globals */
/*---------------------------------------------------------------------------*/
* Typically one RM object will cater to one EDMA3 HW controller
* and will have all the global config information.
*/
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(resMgrObj, ".fardata:.edma3Globals");
+#endif
EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];
* scenario, this DMA channel <-> TCC mapping will be used to point to
* the correct callback function.
*/
-static unsigned int edma3DmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_DMA_CH];
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3DmaChTccMapping, ".fardata:.edma3Globals");
+#endif
+static uint32_t edma3DmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_DMA_CH];
/**
@@ -181,7 +199,10 @@ static unsigned int edma3DmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_D
* scenario, this QDMA channel <-> TCC mapping will be used to point to
* the correct callback function.
*/
-static unsigned int edma3QdmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_QDMA_CH];
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3QdmaChTccMapping, ".fardata:.edma3Globals");
+#endif
+static uint32_t edma3QdmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_QDMA_CH];
/**
@@ -189,6 +210,9 @@ static unsigned int edma3QdmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_
* against a particular TCC. Used to call the callback
* functions linked to the particular channel.
*/
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3IntrParams, ".fardata:.edma3Globals");
+#endif
static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TCC];
@@ -199,6 +223,9 @@ static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_EDMA3_INSTANCES][ED
* which shadow region registers to access. All other interrupts coming
* from other shadow regions will not be handled.
*/
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3RegionId, ".fardata:.edma3Globals");
+#endif
static EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS;
/** masterExists[] will be updated when the Master RM Instance modifies the
* masterExists[] is per EDMA3 hardware, hence it is created
* as an array.
*/
-static unsigned short masterExists [EDMA3_MAX_EDMA3_INSTANCES] = {FALSE,FALSE,FALSE};
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(masterExists, ".fardata:.edma3Globals");
+#endif
+static uint32_t masterExists [EDMA3_MAX_EDMA3_INSTANCES] = {FALSE,FALSE,FALSE,FALSE,FALSE};
/**
* Number of PaRAM Sets actually present on the SoC. This will be updated
* while creating the Resource Manager Object.
*/
-unsigned int edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS;
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3NumPaRAMSets, ".fardata:.edma3Globals");
+#endif
+uint32_t edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS;
/**
* The list of Interrupt Channels which get allocated while requesting the
* TCC. It will be used while checking the IPR/IPRH bits in the RM ISR.
*/
-static unsigned int allocatedTCCs[EDMA3_MAX_EDMA3_INSTANCES][2u] =
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(allocatedTCCs, ".fardata:.edma3Globals");
+#endif
+static uint32_t allocatedTCCs[EDMA3_MAX_EDMA3_INSTANCES][2U] =
{
- {0x0u, 0x0u},
- {0x0u, 0x0u},
- {0x0u, 0x0u},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
+ {0x0U, 0x0U},
};
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
-static unsigned int contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u};
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(contiguousDmaRes, ".fardata:.edma3Globals");
+#endif
+static uint32_t contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0U, 0x0U};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
-static unsigned int contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u};
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(contiguousQdmaRes, ".fardata:.edma3Globals");
+#endif
+static uint32_t contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0U};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
-static unsigned int contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u};
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(contiguousTccRes, ".fardata:.edma3Globals");
+#endif
+static uint32_t contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0U, 0x0U};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
-static unsigned int contiguousParamRes[EDMA3_MAX_PARAM_DWRDS];
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(contiguousParamRes, ".fardata:.edma3Globals");
+#endif
+static uint32_t contiguousParamRes[EDMA3_MAX_PARAM_DWRDS];
/**
* resource manager, when a request is made to free the channel,
* to free up the channel-associated resources.
*/
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(edma3RmChBoundRes, ".fardata:.edma3Globals");
+#endif
static EDMA3_RM_ChBoundResources edma3RmChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
-
+/**
+ * Used to reset the Internal EDMA3 Resource Manager Data Structures for the first time.
+ */
+#ifdef BUILD_C6XDSP
+#pragma DATA_SECTION(rmInitDone, ".fardata:.edma3Globals");
+#endif
+ static uint16_t rmInitDone = FALSE;
/*---------------------------------------------------------------------------*/
/* Local functions prototypes */
/*---------------------------------------------------------------------------*/
/** EDMA3 Instance 0 Completion Handler Interrupt Service Routine */
-void lisrEdma3ComplHandler0(unsigned int arg);
+void lisrEdma3ComplHandler0(uint32_t edma3InstanceId);
/** EDMA3 Instance 0 CC Error Interrupt Service Routine */
-void lisrEdma3CCErrHandler0(unsigned int arg);
+void lisrEdma3CCErrHandler0(uint32_t edma3InstanceId);
/**
* EDMA3 Instance 0 TC[0-7] Error Interrupt Service Routines
* for a maximum of 8 TCs (Transfer Controllers).
*/
-void lisrEdma3TC0ErrHandler0(unsigned int arg);
-void lisrEdma3TC1ErrHandler0(unsigned int arg);
-void lisrEdma3TC2ErrHandler0(unsigned int arg);
-void lisrEdma3TC3ErrHandler0(unsigned int arg);
-void lisrEdma3TC4ErrHandler0(unsigned int arg);
-void lisrEdma3TC5ErrHandler0(unsigned int arg);
-void lisrEdma3TC6ErrHandler0(unsigned int arg);
-void lisrEdma3TC7ErrHandler0(unsigned int arg);
+void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId);
/** Interrupt Handler for the Transfer Completion interrupt */
/** Interrupt Handler for the Channel Controller Error interrupt */
static void edma3CCErrHandler (const EDMA3_RM_Obj *rmObj);
/** Interrupt Handler for the Transfer Controller Error interrupt */
-static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum);
+static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, uint32_t tcNum);
/** Local MemZero function */
-void edma3MemZero(void *dst, unsigned int len);
+void edma3MemZero(void *dst, uint32_t len);
/** Local MemCpy function */
-void edma3MemCpy(void *dst, const void *src, unsigned int len);
+void edma3MemCpy(void *dst, const void *src, uint32_t len);
/* Local MemCopy function to copy Param Set ONLY */
-void edma3ParamCpy(void *dst, const void *src);
+void edma3ParamCpy(volatile void *dst, const volatile void *src);
/** Initialization of the Global region registers of the EDMA3 Controller */
-static void edma3GlobalRegionInit (unsigned int phyCtrllerInstId);
+static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId, uint32_t numDmaChannels);
/** Initialization of the Shadow region registers of the EDMA3 Controller */
static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance);
* Finds a particular bit ('0' or '1') in the particular word from 'start'.
* If found, returns the position, else return -1.
*/
-static int findBitInWord (int source, unsigned int start, unsigned short bit);
+static int32_t findBitInWord (int32_t source, uint32_t start, uint16_t bit);
/**
* Finds a particular bit ('0' or '1') in the specified resources' array
* from 'start' to 'end'. If found, returns the position, else return -1.
*/
-static int findBit (EDMA3_RM_ResType resType,
- unsigned int start,
- unsigned int end,
- unsigned short bit);
+static int32_t findBit (EDMA3_RM_ResType resType,
+ uint32_t start,
+ uint32_t end,
+ uint16_t bit);
/**
* If successful, this function returns EDMA3_RM_SOK and the position
* of first available resource in 'positionRes'. Else returns error.
*/
static EDMA3_RM_Result allocAnyContigRes(EDMA3_RM_ResType resType,
- unsigned int numResources,
- unsigned int *positionRes);
+ uint32_t numResources,
+ uint32_t *positionRes);
/**
* Starting from 'firstResIdObj', this function makes the next 'numResources'
*/
static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,
const EDMA3_RM_ResDesc *firstResIdObj,
- unsigned int numResources);
+ uint32_t numResources);
/*---------------------------------------------------------------------------*/
-/**\fn EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
- * const EDMA3_RM_GblConfigParams *gblCfgParams,
- * const void *miscParam)
- * \brief Create EDMA3 Resource Manager Object
- *
- * This API is used to create the EDMA3 Resource Manager Object. It should be
- * called only ONCE for each EDMA3 hardware instance.
- *
- * Init-time Configuration structure for EDMA3 hardware is provided to pass the
- * SoC specific information. This configuration information could be provided
- * by the user at init-time. In case user doesn't provide it, this information
- * could be taken from the SoC specific configuration file
- * edma3_<SOC_NAME>_cfg.c, in case it is available.
- *
- * This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR)
- * and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam'
- * argument is NULL. User can avoid these registers' programming (in some specific
- * use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration
- * structure and passing this structure as the third argument (miscParam).
- *
- * After successful completion of this API, Resource Manager Object's state
- * changes to EDMA3_RM_CREATED from EDMA3_RM_DELETED.
- *
- * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id
- * (Hardware instance id, starting from 0).
- * \param gblCfgParams [IN] SoC specific configuration structure for the
- * EDMA3 Hardware.
- * \param miscParam [IN] Misc configuration options provided in the
- * structure 'EDMA3_RM_MiscParam'.
- * For default options, user can pass NULL
- * in this argument.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- */
-EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
+EDMA3_RM_Result EDMA3_RM_create (uint32_t phyCtrllerInstId,
const EDMA3_RM_GblConfigParams *gblCfgParams,
const void *miscParam)
{
- unsigned int count = 0u;
+ uint32_t count = 0U;
EDMA3_RM_Result result = EDMA3_RM_SOK;
- /**
- * Used to reset the Internal EDMA3 Resource Manager Data Structures for the first time.
- */
- static unsigned short rmInitDone = FALSE;
const EDMA3_RM_MiscParam *miscOpt = (const EDMA3_RM_MiscParam *)miscParam;
+#ifdef GENERIC
+ /* GENERIC libraries don't come with a default confifguration, always
+ needs to be supplied with a parameter */
+ if (gblCfgParams == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
/**
* We are NOT checking 'gblCfgParams' for NULL.
* If user has passed NULL, default config info will be
{
edma3MemZero((void *)&(resMgrObj[count]),
sizeof(resMgrObj));
- edma3MemZero((void *)(&(edma3IntrParams[0u])),
+ edma3MemZero((void *)(&(edma3IntrParams[0U])),
sizeof(edma3IntrParams));
rmInitDone = TRUE;
* If yes, copy it to the driver data structures. Else, use the
* info from the config file edma3Cfg.c
*/
+#ifndef GENERIC
if (NULL == gblCfgParams)
{
/* Take info from the specific config file */
}
else
{
+#endif
/* User passed the info, save it in the RM object first */
edma3MemCpy((void *)(&resMgrObj[phyCtrllerInstId].gblCfgParams),
(const void *)(gblCfgParams),
sizeof (EDMA3_RM_GblConfigParams));
+#ifndef GENERIC
}
+#endif
/**
*/
if (FALSE == resMgrObj[phyCtrllerInstId].gblCfgParams.dmaChPaRAMMapExists)
{
- for (count = 0u; count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels; count++)
+ for (count = 0U; count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels; count++)
{
resMgrObj[phyCtrllerInstId].gblCfgParams.dmaChannelPaRAMMap[count] = count;
}
* Initialize Boundary Values for Logical Channel Ranges.
*/
edma3NumPaRAMSets = resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets;
- edma3_dma_ch_max_val[phyCtrllerInstId] = resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels - 1u;
- edma3_link_ch_min_val[phyCtrllerInstId] = edma3_dma_ch_max_val[phyCtrllerInstId] + 1u;
- edma3_link_ch_max_val[phyCtrllerInstId] = edma3_link_ch_min_val[phyCtrllerInstId] + resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets - 1u;
- edma3_qdma_ch_min_val[phyCtrllerInstId] = edma3_link_ch_max_val[phyCtrllerInstId] + 1u;
- edma3_qdma_ch_max_val[phyCtrllerInstId] = edma3_qdma_ch_min_val[phyCtrllerInstId] + resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels - 1u;
+ edma3_dma_ch_max_val[phyCtrllerInstId] = resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels - 1U;
+ edma3_link_ch_min_val[phyCtrllerInstId] = edma3_dma_ch_max_val[phyCtrllerInstId] + 1U;
+ edma3_link_ch_max_val[phyCtrllerInstId] = edma3_link_ch_min_val[phyCtrllerInstId] + (resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets - 1U);
+ edma3_qdma_ch_min_val[phyCtrllerInstId] = edma3_link_ch_max_val[phyCtrllerInstId] + 1U;
+ edma3_qdma_ch_max_val[phyCtrllerInstId] = edma3_qdma_ch_min_val[phyCtrllerInstId] + (resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels - 1U);
edma3_log_ch_max_val[phyCtrllerInstId] = edma3_qdma_ch_max_val[phyCtrllerInstId];
resMgrObj[phyCtrllerInstId].phyCtrllerInstId = phyCtrllerInstId;
resMgrObj[phyCtrllerInstId].state = EDMA3_RM_CREATED;
- resMgrObj[phyCtrllerInstId].numOpens = 0u;
+ resMgrObj[phyCtrllerInstId].numOpens = 0U;
/* Make all the RM instances for this EDMA3 HW NULL */
- for (count = 0u; count < EDMA3_MAX_RM_INSTANCES; count++)
+ for (count = 0U; count < EDMA3_MAX_RM_INSTANCES; count++)
{
edma3MemZero((void *)((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count),
sizeof(EDMA3_RM_Instance));
}
/* Initialize the global edma3DmaChTccMapping array with EDMA3_MAX_TCC */
- for ( count = 0u;
+ for ( count = 0U;
count < resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels;
count++
)
}
/* Initialize the global edma3QdmaChTccMapping array with EDMA3_MAX_TCC */
- for ( count = 0u;
+ for ( count = 0U;
count < resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels;
count++
)
}
/* Reset edma3RmChBoundRes Array*/
- for (count = 0u; count < EDMA3_MAX_LOGICAL_CH; count++)
+ for (count = 0U; count < EDMA3_MAX_LOGICAL_CH; count++)
{
edma3RmChBoundRes[phyCtrllerInstId][count].paRAMId = -1;
edma3RmChBoundRes[phyCtrllerInstId][count].tcc = EDMA3_MAX_TCC;
}
/* Make the contiguousParamRes array NULL */
- edma3MemZero((void *)(&(contiguousParamRes[0u])),
+ edma3MemZero((void *)(&(contiguousParamRes[0U])),
sizeof(contiguousParamRes));
if (miscOpt->isSlave == FALSE)
{
/* It is a master. */
- edma3GlobalRegionInit(phyCtrllerInstId);
+ edma3GlobalRegionInit(phyCtrllerInstId, (resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels));
}
}
else
{
/* By default, global registers will be initialized. */
- edma3GlobalRegionInit(phyCtrllerInstId);
+ edma3GlobalRegionInit(phyCtrllerInstId, (resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels));
}
}
}
return result;
}
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId,
- * const void *param)
- * \brief Delete EDMA3 Resource Manager Object
- *
- * This API is used to delete the EDMA3 RM Object. It should be called
- * once for each EDMA3 hardware instance, ONLY after closing all the
- * previously opened EDMA3 RM Instances.
- *
- * After successful completion of this API, Resource Manager Object's state
- * changes to EDMA3_RM_DELETED.
- *
- * \param phyCtrllerInstId [IN] EDMA3 Phy Controller Instance Id (Hardware
- * instance id, starting from 0).
- * \param param [IN] For possible future use.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- */
-EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId,
+EDMA3_RM_Result EDMA3_RM_delete (uint32_t phyCtrllerInstId,
const void *param)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
/* Check if the parameters are OK. */
if (EDMA3_RM_SOK == result)
{
- /*to remove CCS remark: parameter "param" was never referenced */
- (void)param;
-
/**
* If number of RM Instances is 0, then state should be
* EDMA3_RM_CLOSED OR EDMA3_RM_CREATED.
*/
- if ((NULL == resMgrObj[phyCtrllerInstId].numOpens)
+ if ((0 == resMgrObj[phyCtrllerInstId].numOpens)
&& ((resMgrObj[phyCtrllerInstId].state != EDMA3_RM_CLOSED)
&& (resMgrObj[phyCtrllerInstId].state != EDMA3_RM_CREATED)))
{
* If number of RM Instances is NOT 0, then this function
* SHOULD NOT be called by anybody.
*/
- if (NULL != resMgrObj[phyCtrllerInstId].numOpens)
+ if (0 != resMgrObj[phyCtrllerInstId].numOpens)
{
result = EDMA3_RM_E_INVALID_STATE;
}
resMgrObj[phyCtrllerInstId].state = EDMA3_RM_DELETED;
/* Reset the Allocated TCCs Array also. */
- allocatedTCCs[phyCtrllerInstId][0u] = 0x0u;
- allocatedTCCs[phyCtrllerInstId][1u] = 0x0u;
+ allocatedTCCs[phyCtrllerInstId][0U] = 0x0U;
+ allocatedTCCs[phyCtrllerInstId][1U] = 0x0U;
/* Also, reset the RM Object Global Config Info */
edma3MemZero((void *)&(resMgrObj[phyCtrllerInstId].gblCfgParams),
return result;
}
-
-/**\fn EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
- * const EDMA3_RM_Param *initParam,
- * EDMA3_RM_Result *errorCode)
- * \brief Open EDMA3 Resource Manager Instance
- *
- * This API is used to open an EDMA3 Resource Manager Instance. It could be
- * called multiple times, for each possible EDMA3 shadow region. Maximum
- * EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware
- * instance.
- *
- * Also, only ONE Master Resource Manager Instance is permitted. This master
- * instance (and hence the region to which it belongs) will only receive the
- * EDMA3 interrupts, if enabled.
- *
- * User could pass the instance specific configuration structure
- * (initParam->rmInstInitConfig) as a part of the 'initParam' structure,
- * during init-time. In case user doesn't provide it, this information could
- * be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c,
- * in case it is available.
- *
- * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id (Hardware
- * instance id, starting from 0).
- * \param initParam [IN] Used to Initialize the Resource Manager
- * Instance (Master or Slave).
- * \param errorCode [OUT] Error code while opening RM instance.
- *
- * \return Handle to the opened Resource Manager instance Or NULL in case of
- * error.
- *
- * \note This function disables the global interrupts (by calling API
- * edma3OsProtectEntry with protection level
- * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data
- * structures, to make it re-entrant.
- */
-EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
+EDMA3_RM_Handle EDMA3_RM_open (uint32_t phyCtrllerInstId,
const EDMA3_RM_Param *initParam,
EDMA3_RM_Result *errorCode)
{
- unsigned int intState = 0u;
- unsigned int resMgrIdx = 0u;
+ uint32_t intState = 0U;
+ uint32_t resMgrIdx = 0U;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Instance *temp_ptr_rm_inst = NULL;
EDMA3_RM_Handle retVal = NULL;
- unsigned int dmaChDwrds = 0u;
- unsigned int paramSetDwrds = 0u;
- unsigned int tccDwrds = 0u;
+ uint32_t dmaChDwrds = 0U;
+ uint32_t paramSetDwrds = 0U;
+ uint32_t tccDwrds = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+#ifdef GENERIC
+ /* GENERIC libraries don't come with a default confifguration, always
+ needs to be supplied with a parameter */
+ if ((initParam == NULL) || (initParam->rmInstInitConfig == NULL))
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
if (((initParam == NULL)
else
{
edma3OsProtectEntry (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
&intState);
/** Check state of RM Object.
* If no RM instance is opened and this is the first one,
* then state should be created/closed.
*/
- if ((rmObj->numOpens == NULL) &&
+ if ((rmObj->numOpens == 0) &&
((rmObj->state != EDMA3_RM_CREATED) &&
(rmObj->state != EDMA3_RM_CLOSED)))
{
result = EDMA3_RM_E_INVALID_STATE;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
{
result = EDMA3_RM_E_INVALID_STATE;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
{
result = EDMA3_RM_E_MAX_RM_INST_OPENED;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
}
/* No two masters should exist, return error */
result = EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
{
/* Create Res Mgr Instance */
- for (resMgrIdx = 0u; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)
+ for (resMgrIdx = 0U; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)
{
temp_ptr_rm_inst = ((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);
{
result = EDMA3_RM_E_MAX_RM_INST_OPENED;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
* resMgrIdx specifies the RM instance number created just now.
* Use it to populate the userInitConfig [].
*/
+#ifndef GENERIC
if (NULL == initParam->rmInstInitConfig)
{
/* Take the info from the specific config file */
}
else
{
+#endif
/* User has passed the region specific info. */
edma3MemCpy((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx),
(const void *)(initParam->rmInstInitConfig),
sizeof (EDMA3_RM_InstanceInitConfig));
+#ifndef GENERIC
}
+#endif
rmInstance->initParam.rmInstInitConfig =
((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);
- dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32u;
+ dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / (uint32_t)32U;
if (dmaChDwrds == 0)
{
/* In case DMA channels are < 32 */
- dmaChDwrds = 1;
+ dmaChDwrds = 1U;
}
- paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32u;
+ paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / (uint32_t)32U;
if (paramSetDwrds == 0)
{
/* In case PaRAM Sets are < 32 */
- paramSetDwrds = 1;
+ paramSetDwrds = 1U;
}
- tccDwrds = rmObj->gblCfgParams.numTccs / 32u;
+ tccDwrds = rmObj->gblCfgParams.numTccs / (uint32_t)32U;
if (tccDwrds == 0)
{
/* In case TCCs are < 32 */
- tccDwrds = 1;
+ tccDwrds = 1U;
}
- for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < dmaChDwrds; ++resMgrIdx)
{
rmInstance->avlblDmaChannels[resMgrIdx]
= rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resMgrIdx];
}
- rmInstance->avlblQdmaChannels[0u]
- = rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u];
+ rmInstance->avlblQdmaChannels[0U]
+ = rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U];
- for (resMgrIdx = 0u; resMgrIdx < paramSetDwrds; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < paramSetDwrds; ++resMgrIdx)
{
rmInstance->avlblPaRAMSets[resMgrIdx]
= rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resMgrIdx];
}
- for (resMgrIdx = 0u; resMgrIdx < tccDwrds; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < tccDwrds; ++resMgrIdx)
{
rmInstance->avlblTccs [resMgrIdx]
= rmInstance->initParam.rmInstInitConfig->ownTccs[resMgrIdx];
* will not be returned in case user requests for ANY link
* channel.
*/
- for (resMgrIdx = 0u; resMgrIdx < rmObj->gblCfgParams.numDmaChannels; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < rmObj->gblCfgParams.numDmaChannels; ++resMgrIdx)
{
- rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[resMgrIdx/32u] |= (1u<<(resMgrIdx%32u));
+ rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[resMgrIdx/32U] |= ((uint32_t)1U<<(resMgrIdx%32U));
}
/*
}
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
}
return (EDMA3_RM_Handle)retVal;
}
-
-/**\fn EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr,
- * const void *param)
- * \brief Close EDMA3 Resource Manager Instance
- *
- * This API is used to close a previously opened EDMA3 RM Instance.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param param [IN] For possible future use.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function disables the global interrupts (by calling API
- * edma3OsProtectEntry with protection level
- * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data
- * structures, to make it re-entrant.
- */
EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr,
const void *param)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
- unsigned int intState = 0u;
- unsigned int resMgrIdx = 0u;
+ uint32_t intState = 0U;
+ uint32_t resMgrIdx = 0U;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Instance *rmInstance = NULL;
- unsigned int dmaChDwrds;
- unsigned int paramSetDwrds;
- unsigned int tccDwrds;
-
- /*to remove CCS remark: parameter "param" was never referenced */
- (void)param;
+ uint32_t dmaChDwrds;
+ uint32_t paramSetDwrds;
+ uint32_t tccDwrds;
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
}
else
{
- dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32u;
- paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32u;
- tccDwrds = rmObj->gblCfgParams.numTccs / 32u;
+ dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / (uint32_t)32U;
+ paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / (uint32_t)32U;
+ tccDwrds = rmObj->gblCfgParams.numTccs / (uint32_t)32U;
/* Set the instance config as NULL*/
- for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < dmaChDwrds; ++resMgrIdx)
{
- rmInstance->avlblDmaChannels[resMgrIdx] = 0x0u;
+ rmInstance->avlblDmaChannels[resMgrIdx] = 0x0U;
}
- for (resMgrIdx = 0u; resMgrIdx < paramSetDwrds; ++resMgrIdx)
+ for (resMgrIdx = 0U; resMgrIdx < paramSetDwrds; ++resMgrIdx)
{
- rmInstance->avlblPaRAMSets[resMgrIdx] = 0x0u;
+ rmInstance->avlblPaRAMSets[resMgrIdx] = 0x0U;
}
- rmInstance->avlblQdmaChannels[0u] = 0x0u;
- for (resMgrIdx = 0u; resMgrIdx < tccDwrds; ++resMgrIdx)
+ rmInstance->avlblQdmaChannels[0U] = 0x0U;
+ for (resMgrIdx = 0U; resMgrIdx < tccDwrds; ++resMgrIdx)
{
- rmInstance->avlblTccs[resMgrIdx] = 0x0u;
+ rmInstance->avlblTccs[resMgrIdx] = 0x0U;
}
/**
/* Critical section starts */
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
&intState);
/* Decrease the Number of Opens */
--rmObj->numOpens;
- if (NULL == rmObj->numOpens)
+ if (0 == rmObj->numOpens)
{
edma3MemZero((void *)&(edma3RmChBoundRes[rmObj->phyCtrllerInstId]),
sizeof(edma3RmChBoundRes[rmObj->phyCtrllerInstId]));
/* Critical section ends */
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
rmInstance->pResMgrObjHandle = NULL;
return result;
}
-
-/**\fn EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr,
- * EDMA3_RM_ResDesc *resObj)
- * \brief This API is used to allocate specified EDMA3 Resources like
- * DMA/QDMA channel, PaRAM Set or TCC.
- *
- * Note: To free the resources allocated by this API, user should call
- * EDMA3_RM_freeResource () ONLY to de-allocate all the allocated resources.
- *
- * User can either request a specific resource by passing the resource id
- * in 'resObj->resId' OR request ANY available resource of the type
- * 'resObj->type'.
- *
- * ANY types of resources are those resources when user doesn't care about the
- * actual resource allocated; user just wants a resource of the type specified.
- * One use-case is to perform memory-to-memory data transfer operation. This
- * operation can be performed using any available DMA or QDMA channel.
- * User doesn't need any specific channel for the same.
- *
- * To allocate a specific resource, first this API checks whether that resource
- * is OWNED by the Resource Manager instance. Then it checks the current
- * availability of that resource.
- *
- * To allocate ANY available resource, this API tries to allocate a resource
- * from the pool of (owned && non_reserved && available_right_now) resources.
- *
- * After allocating a DMA/QDMA channel or TCC, the same resource is enabled in
- * the shadow region specific register (DRAE/DRAEH/QRAE).
- *
- * Allocated PaRAM Set is initialized to NULL before this API returns if user
- * has requested for one.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param resObj [IN/OUT] Handle to the resource descriptor
- * object, which needs to be allocated.
- * In case user passes a specific resource
- * Id, resObj value is left unchanged.
- * In case user requests ANY available
- * resource, the allocated resource id is
- * returned in resObj.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function acquires a RM Instance specific semaphore
- * to prevent simultaneous access to the global pool of resources.
- * It is re-entrant, but should not be called from the user callback
- * function (ISR context).
- */
EDMA3_RM_Result EDMA3_RM_allocResource(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *resObj)
{
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Result semResult = EDMA3_RM_SOK;
- unsigned int avlblIdx = 0u;
- unsigned int resIdClr = 0x0;
- unsigned int resIdSet = 0x0;
- unsigned int resId;
+ uint32_t avlblIdx = 0U;
+ uint32_t resIdClr = 0x0;
+ uint32_t resIdSet = 0x0;
+ uint32_t resId;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
-
+ uint32_t mapXbarEvtToChanFlag = FALSE;
+ uint32_t xBarEvtBeforeMap = 0;
+ uint32_t edma3Id;
+
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
else
{
gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
-
+ edma3Id = rmObj->phyCtrllerInstId;
resId = resObj->resId;
- resIdClr = (unsigned int)(~(1u << (resId%32u)));
- resIdSet = (1u << (resId%32u));
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resId%32U)));
+ resIdSet = (1U << (resId%32U));
- /**
- * Take the instance specific semaphore, to prevent simultaneous
- * access to the shared resources.
- */
- semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,
- EDMA3_OSSEM_NO_TIMEOUT);
- if (EDMA3_RM_SOK == semResult)
+ if ( rmInstance->mapXbarToChan != NULL)
{
- switch (resObj->type)
+ xBarEvtBeforeMap = resId;
+ if ((resId > rmObj->gblCfgParams.numDmaChannels) &&
+ (resId != EDMA3_RM_RES_ANY) &&
+ (resObj->type == EDMA3_RM_RES_DMA_CHANNEL))
{
- case EDMA3_RM_RES_DMA_CHANNEL :
- {
- if (resId == EDMA3_RM_RES_ANY)
- {
- for (avlblIdx=0u;
- avlblIdx <
- rmObj->gblCfgParams.numDmaChannels;
- ++avlblIdx)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[avlblIdx/32u])
- &
- (rmInstance->avlblDmaChannels[avlblIdx/32u])
- &
- ~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[avlblIdx/32u])
- &
- (1u << (avlblIdx%32u))) != FALSE)
- {
- /*
- * Match found.
- * A resource which is owned by this instance of the
- * Resource Manager and which is presently available
- * and which has not been reserved - is found.
- */
- resObj->resId = avlblIdx;
- /*
- * Mark the 'match found' resource as "Not Available"
- * for future requests
- */
- rmInstance->avlblDmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
-
- /**
- * Check if the register modification flag is
- * set or not.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- /**
- * Enable the DMA channel in the
- * DRAE/DRAEH registers also.
- */
- if (avlblIdx < 32u)
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << avlblIdx);
- }
- else
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (avlblIdx - 32u));
- }
- }
-
- result = EDMA3_RM_SOK;
- break;
- }
- }
- /*
- * If none of the owned resources of this type is available
- * then report "All Resources of this type not available" error
- */
- if (avlblIdx == rmObj->gblCfgParams.numDmaChannels)
- {
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- if (resId < rmObj->gblCfgParams.numDmaChannels)
- {
- /*
- * Check if specified resource is owned
- * by this instance of the resource manager
- */
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resId/32u])&(resIdSet))!=FALSE)
- {
- /* Now check if specified resource is available presently*/
- if (((rmInstance->avlblDmaChannels[resId/32u])&(resIdSet))!=FALSE)
- {
- /*
- * Mark the specified channel as "Not Available"
- * for future requests
- */
- rmInstance->avlblDmaChannels[resId/32u] &= resIdClr;
-
- /**
- * Check if the register modification flag is
- * set or not.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- if (resId < 32u)
- {
- rmInstance->shadowRegs->EECR = (1UL << resId);
-
- /**
- * Enable the DMA channel in the
- * DRAE registers also.
- */
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << resId);
- }
- else
- {
- rmInstance->shadowRegs->EECRH = (1UL << resId);
-
- /**
- * Enable the DMA channel in the
- * DRAEH registers also.
- */
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (resId - 32u));
- }
- }
-
- result = EDMA3_RM_SOK;
- }
- else
- {
- /* Specified resource is owned but is already booked */
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- /*
- * Specified resource is not owned by this instance
- * of the Resource Manager
- */
- result = EDMA3_RM_E_RES_NOT_OWNED;
- }
- }
- else
- {
- result = EDMA3_RM_E_INVALID_PARAM;
- }
- }
- }
- break;
-
- case EDMA3_RM_RES_QDMA_CHANNEL :
- {
- if (resId == EDMA3_RM_RES_ANY)
- {
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numQdmaChannels; ++avlblIdx)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[avlblIdx/32u])
- &
- (rmInstance->avlblQdmaChannels[avlblIdx/32u])
- &
- ~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[avlblIdx/32u])
- &
- (1u << (avlblIdx%32u))) != FALSE)
- {
- resObj->resId = avlblIdx;
- rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
-
- /**
- * Check if the register modification flag is
- * set or not.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- /**
- * Enable the QDMA channel in the
- * QRAE register also.
- */
- gblRegs->QRAE[rmInstance->initParam.regionId]
- |= (0x1u << avlblIdx);
- }
-
- result = EDMA3_RM_SOK;
- break;
- }
- }
- /*
- * If none of the owned resources of this type is available
- * then report "All Resources of this type not available" error
- */
- if (avlblIdx == rmObj->gblCfgParams.numQdmaChannels)
- {
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- if (resId < rmObj->gblCfgParams.numQdmaChannels)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32u])&(resIdSet))!=FALSE)
- {
- if (((rmInstance->avlblQdmaChannels [resId/32u])&(resIdSet))!=FALSE)
- {
- rmInstance->avlblQdmaChannels [resId/32u] &= resIdClr;
-
- /**
- * Check if the register modification flag is
- * set or not.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- /**
- * Enable the QDMA channel in the
- * QRAE register also.
- */
- gblRegs->QRAE[rmInstance->initParam.regionId]
- |= (0x1u << resId);
- }
-
- result = EDMA3_RM_SOK;
- }
- else
- {
- /* Specified resource is owned but is already booked */
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- /*
- * Specified resource is not owned by this instance
- * of the Resource Manager
- */
- result = EDMA3_RM_E_RES_NOT_OWNED;
- }
- }
- else
- {
- result = EDMA3_RM_E_INVALID_PARAM;
- }
- }
- }
- break;
-
- case EDMA3_RM_RES_TCC :
- {
- if (resId == EDMA3_RM_RES_ANY)
- {
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numTccs; ++avlblIdx)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [avlblIdx/32u])
- & (rmInstance->avlblTccs [avlblIdx/32u])
- & ~(rmInstance->initParam.rmInstInitConfig->resvdTccs [avlblIdx/32u])
- & (1u << (avlblIdx%32u)))!=FALSE)
- {
- resObj->resId = avlblIdx;
- rmInstance->avlblTccs [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
- result = EDMA3_RM_SOK;
- break;
- }
- }
- /*
- * If none of the owned resources of this type is available
- * then report "All Resources of this type not available" error
- */
- if ( avlblIdx == rmObj->gblCfgParams.numTccs)
- {
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- if (resId < rmObj->gblCfgParams.numTccs)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32u])&(resIdSet))!=FALSE)
- {
- if (((rmInstance->avlblTccs [resId/32u])&(resIdSet))!=FALSE)
- {
- rmInstance->avlblTccs [resId/32u] &= resIdClr;
- result = EDMA3_RM_SOK;
- }
- else
- {
- /* Specified resource is owned but is already booked */
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- /*
- * Specified resource is not owned by this instance
- * of the Resource Manager
- */
- result = EDMA3_RM_E_RES_NOT_OWNED;
- }
- }
- else
- {
- result = EDMA3_RM_E_INVALID_PARAM;
- }
- }
- }
- break;
-
- case EDMA3_RM_RES_PARAM_SET :
- {
- if (resId == EDMA3_RM_RES_ANY)
- {
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numPaRAMSets; ++avlblIdx)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [avlblIdx/32u])
- &
- (rmInstance->avlblPaRAMSets [avlblIdx/32u])
- &
- ~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets [avlblIdx/32u])
- &
- (1u << (avlblIdx%32u)))!=FALSE)
- {
- resObj->resId = avlblIdx;
- rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
-
- /**
- * Also, make the actual PARAM Set NULL, checking the flag
- * whether it is required or not.
- */
- if ((TRUE == rmInstance->regModificationRequired)
- && (TRUE == rmInstance->paramInitRequired))
- {
- edma3MemZero((void *)(&gblRegs->PARAMENTRY[avlblIdx]),
- sizeof(gblRegs->PARAMENTRY[avlblIdx]));
- }
-
- result = EDMA3_RM_SOK;
- break;
- }
- }
- /*
- * If none of the owned resources of this type is available
- * then report "All Resources of this type not available" error
- */
- if ( avlblIdx == rmObj->gblCfgParams.numPaRAMSets)
- {
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- if (resId < rmObj->gblCfgParams.numPaRAMSets)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32u])&(resIdSet))!=FALSE)
- {
- if (((rmInstance->avlblPaRAMSets [resId/32u])&(resIdSet)) !=FALSE)
- {
- rmInstance->avlblPaRAMSets [resId/32u] &= resIdClr;
-
- /**
- * Also, make the actual PARAM Set NULL, checking the flag
- * whether it is required or not.
- */
- if ((TRUE == rmInstance->regModificationRequired)
- && (TRUE == rmInstance->paramInitRequired))
- {
- edma3MemZero((void *)(&gblRegs->PARAMENTRY[resId]),
- sizeof(gblRegs->PARAMENTRY[resId]));
- }
-
- result = EDMA3_RM_SOK;
- }
- else
- {
- /* Specified resource is owned but is already booked */
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- /*
- * Specified resource is not owned by this instance
- * of the Resource Manager
- */
- result = EDMA3_RM_E_RES_NOT_OWNED;
- }
- }
- else
- {
- result = EDMA3_RM_E_INVALID_PARAM;
- }
- }
- }
- break;
-
- default:
- result = EDMA3_RM_E_INVALID_PARAM;
- break;
+ result = rmInstance->mapXbarToChan(xBarEvtBeforeMap,
+ &resObj->resId,
+ &rmInstance->rmXbarToEvtMapConfig);
+ if (EDMA3_RM_SOK == result)
+ {
+ resId = resObj->resId;
+ mapXbarEvtToChanFlag = TRUE;
+ }
}
-
- /* Return the semaphore back */
- semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
}
- }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /**
+ * Take the instance specific semaphore, to prevent simultaneous
+ * access to the shared resources.
+ */
+ semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,
+ EDMA3_OSSEM_NO_TIMEOUT);
+ if (EDMA3_RM_SOK == semResult)
+ {
+ switch (resObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0U;
+ avlblIdx <
+ rmObj->gblCfgParams.numDmaChannels;
+ ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[avlblIdx/32U])
+ &
+ (rmInstance->avlblDmaChannels[avlblIdx/32U])
+ &
+ ~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[avlblIdx/32U])
+ &
+ ((uint32_t)1U << (avlblIdx%32U))) != FALSE)
+ {
+ /*
+ * Match found.
+ * A resource which is owned by this instance of the
+ * Resource Manager and which is presently available
+ * and which has not been reserved - is found.
+ */
+ resObj->resId = avlblIdx;
+ /*
+ * Mark the 'match found' resource as "Not Available"
+ * for future requests
+ */
+ rmInstance->avlblDmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the DMA channel in the
+ * DRAE/DRAEH registers also.
+ */
+ if (avlblIdx < 32U)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= ((uint32_t)0x1U << avlblIdx);
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= ((uint32_t)0x1U << (avlblIdx - 32U));
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if (avlblIdx == rmObj->gblCfgParams.numDmaChannels)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numDmaChannels)
+ {
+ /*
+ * Check if specified resource is owned
+ * by this instance of the resource manager
+ */
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resId/32U])&(resIdSet))!=FALSE)
+ {
+ /* Now check if specified resource is available presently*/
+ if (((rmInstance->avlblDmaChannels[resId/32U])&(resIdSet))!=FALSE)
+ {
+ /*
+ * Mark the specified channel as "Not Available"
+ * for future requests
+ */
+ rmInstance->avlblDmaChannels[resId/32U] &= resIdClr;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ if (resId < 32U)
+ {
+ rmInstance->shadowRegs->EECR = (1UL << resId);
+
+ /**
+ * Enable the DMA channel in the
+ * DRAE registers also.
+ */
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= ((uint32_t)0x1U << resId);
+ }
+ else
+ {
+ rmInstance->shadowRegs->EECRH = (1UL << resId);
+
+ /**
+ * Enable the DMA channel in the
+ * DRAEH registers also.
+ */
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= ((uint32_t)0x1U << (resId - 32U));
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0U; avlblIdx<rmObj->gblCfgParams.numQdmaChannels; ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[avlblIdx/32U])
+ &
+ (rmInstance->avlblQdmaChannels[avlblIdx/32U])
+ &
+ ~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[avlblIdx/32U])
+ &
+ ((uint32_t)1U << (avlblIdx%32U))) != FALSE)
+ {
+ resObj->resId = avlblIdx;
+ rmInstance->avlblQdmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the QDMA channel in the
+ * QRAE register also.
+ */
+ gblRegs->QRAE[rmInstance->initParam.regionId]
+ |= ((uint32_t)0x1U << avlblIdx);
+ }
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if (avlblIdx == rmObj->gblCfgParams.numQdmaChannels)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numQdmaChannels)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32U])&(resIdSet))!=FALSE)
+ {
+ if (((rmInstance->avlblQdmaChannels [resId/32U])&(resIdSet))!=FALSE)
+ {
+ rmInstance->avlblQdmaChannels [resId/32U] &= resIdClr;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the QDMA channel in the
+ * QRAE register also.
+ */
+ gblRegs->QRAE[rmInstance->initParam.regionId]
+ |= ((uint32_t)0x1U << resId);
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_TCC :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0U; avlblIdx<rmObj->gblCfgParams.numTccs; ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [avlblIdx/32U])
+ & (rmInstance->avlblTccs [avlblIdx/32U])
+ & ~(rmInstance->initParam.rmInstInitConfig->resvdTccs [avlblIdx/32U])
+ & ((uint32_t)1U << (avlblIdx%32U)))!=FALSE)
+ {
+ resObj->resId = avlblIdx;
+ rmInstance->avlblTccs [avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the Interrupt channel in the
+ * DRAE/DRAEH registers also.
+ * Also, If the region id coming from this
+ * RM instance is same as the Master RM
+ * Instance's region id, only then we will be
+ * getting the interrupts on the same side.
+ * So save the TCC in the allocatedTCCs[] array.
+ */
+ if (avlblIdx < 32U)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= ((uint32_t)0x1U << avlblIdx);
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << avlblIdx);
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= ((uint32_t)0x1U << (avlblIdx - 32U));
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (avlblIdx - 32U));
+ }
+ }
+ }
+
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if ( avlblIdx == rmObj->gblCfgParams.numTccs)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numTccs)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32U])&(resIdSet))!=FALSE)
+ {
+ if (((rmInstance->avlblTccs [resId/32U])&(resIdSet))!=FALSE)
+ {
+ rmInstance->avlblTccs [resId/32U] &= resIdClr;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the Interrupt channel in the
+ * DRAE/DRAEH registers also.
+ * Also, If the region id coming from this
+ * RM instance is same as the Master RM
+ * Instance's region id, only then we will be
+ * getting the interrupts on the same side.
+ * So save the TCC in the allocatedTCCs[] array.
+ */
+ if (resId < 32U)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= ((uint32_t)0x1U << resId);
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << resId);
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= ((uint32_t)0x1U << (resId - 32U));
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (resId - 32U));
+ }
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0U; avlblIdx<rmObj->gblCfgParams.numPaRAMSets; ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [avlblIdx/32U])
+ &
+ (rmInstance->avlblPaRAMSets [avlblIdx/32U])
+ &
+ ~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets [avlblIdx/32U])
+ &
+ ((uint32_t)1U << (avlblIdx%32U)))!=FALSE)
+ {
+ resObj->resId = avlblIdx;
+ rmInstance->avlblPaRAMSets [avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
+
+ /**
+ * Also, make the actual PARAM Set NULL, checking the flag
+ * whether it is required or not.
+ */
+ if ((TRUE == rmInstance->regModificationRequired)
+ && (TRUE == rmInstance->paramInitRequired))
+ {
+ edma3MemZero((void *)(&gblRegs->PARAMENTRY[avlblIdx]),
+ sizeof(gblRegs->PARAMENTRY[avlblIdx]));
+ }
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if ( avlblIdx == rmObj->gblCfgParams.numPaRAMSets)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numPaRAMSets)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32U])&(resIdSet))!=FALSE)
+ {
+ if (((rmInstance->avlblPaRAMSets [resId/32U])&(resIdSet)) !=FALSE)
+ {
+ rmInstance->avlblPaRAMSets [resId/32U] &= resIdClr;
+
+ /**
+ * Also, make the actual PARAM Set NULL, checking the flag
+ * whether it is required or not.
+ */
+ if ((TRUE == rmInstance->regModificationRequired)
+ && (TRUE == rmInstance->paramInitRequired))
+ {
+ edma3MemZero((void *)(&gblRegs->PARAMENTRY[resId]),
+ sizeof(gblRegs->PARAMENTRY[resId]));
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ default:
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+
+ /* Return the semaphore back */
+ semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
+ }
+ }
+ }
}
/**
* Else, return semResult.
*/
if (EDMA3_RM_SOK == result)
- {
- /**
- * Resource Allocation successful, return semResult for returning
- * semaphore.
- */
- result = semResult;
- }
+ {
+ /**
+ * Resource Allocation successful, return semResult for returning
+ * semaphore.
+ */
+ result = semResult;
+ if ((rmInstance->configScrMapXbarToEvt != NULL) &&
+ (mapXbarEvtToChanFlag == TRUE))
+ {
+ rmInstance->configScrMapXbarToEvt(xBarEvtBeforeMap, resObj->resId);
+ }
+ }
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
return result;
}
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr,
- * const EDMA3_RM_ResDesc *resObj)
- * \brief This API is used to free previously allocated EDMA3 Resources like
- * DMA/QDMA channel, PaRAM Set or TCC.
- *
- * To free a specific resource, first this API checks whether that resource is
- * OWNED by the Resource Manager Instance. Then it checks whether that resource
- * has been allocated by the Resource Manager instance or not.
- *
- * After freeing a DMA/QDMA channel or TCC, the same resource is disabled in
- * the shadow region specific register (DRAE/DRAEH/QRAE).
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param resObj [IN] Handle to the resource descriptor
- * object, which needs to be freed.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function disables the global interrupts to prevent
- * simultaneous access to the global pool of resources.
- * It is re-entrant.
- */
EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr,
const EDMA3_RM_ResDesc *resObj)
{
- unsigned int intState;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
- unsigned int resId;
- unsigned int resIdSet = 0x0;
+ EDMA3_RM_Result semResult = EDMA3_RM_SOK;
+ uint32_t resId;
+ uint32_t resIdSet = 0x0;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
-
+ uint32_t edma3Id;
+
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
else
{
gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
-
+ edma3Id = rmObj->phyCtrllerInstId;
resId = resObj->resId;
- resIdSet = 1u << (resId%32u);
+ resIdSet = 1U << (resId%32U);
- edma3OsProtectEntry (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
- &intState);
+ /**
+ * Take the instance specific semaphore, to prevent simultaneous
+ * access to the shared resources.
+ */
+ semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,
+ EDMA3_OSSEM_NO_TIMEOUT);
- if (EDMA3_RM_SOK == result)
+ if (EDMA3_RM_SOK == semResult)
{
switch (resObj->type)
{
{
if (resId < rmObj->gblCfgParams.numDmaChannels)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels [resId/32u]) & (resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels [resId/32U]) & (resIdSet))!=FALSE)
{
- if (((~(rmInstance->avlblDmaChannels[resId/32u]))&(resIdSet))!=FALSE)
+ if (((~(rmInstance->avlblDmaChannels[resId/32U]))&(resIdSet))!=FALSE)
{
/*
* Mark the specified channel as "Available"
* for future requests
*/
- rmInstance->avlblDmaChannels[resId/32u] |= resIdSet;
+ rmInstance->avlblDmaChannels[resId/32U] |= resIdSet;
/**
* Check if the register modification flag is
* Reset the bit specific to the DMA channel
* in the DRAE/DRAEH register also.
*/
- if (resId < 32u)
+ if (resId < 32U)
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- &= (~(0x1u << resId));
+ &= (~((uint32_t)0x1U << resId));
}
else
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- &= (~(0x1u << (resId-32u)));
+ &= (~((uint32_t)0x1U << (resId-32U)));
}
}
{
if (resId < rmObj->gblCfgParams.numQdmaChannels)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32u]) & (resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32U]) & (resIdSet))!=FALSE)
{
- if (((~(rmInstance->avlblQdmaChannels [resId/32u])) & (resIdSet))!=FALSE)
+ if (((~(rmInstance->avlblQdmaChannels [resId/32U])) & (resIdSet))!=FALSE)
{
- rmInstance->avlblQdmaChannels [resId/32u] |= resIdSet;
+ rmInstance->avlblQdmaChannels [resId/32U] |= resIdSet;
/**
* Check if the register modification flag is
* in the QRAE register also.
*/
gblRegs->QRAE[rmInstance->initParam.regionId]
- &= (~(0x1u << resId));
+ &= (~((uint32_t)0x1U << resId));
}
result = EDMA3_RM_SOK;
{
if (resId < rmObj->gblCfgParams.numTccs)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32u]) & (resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32U]) & (resIdSet))!=FALSE)
{
- if (((~(rmInstance->avlblTccs [resId/32u])) & (resIdSet))!=FALSE)
+ if (((~(rmInstance->avlblTccs [resId/32U])) & (resIdSet))!=FALSE)
{
- rmInstance->avlblTccs [resId/32u] |= resIdSet;
+ rmInstance->avlblTccs [resId/32U] |= resIdSet;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Interrupt Channel is freed.
+ * Reset the bit specific to the Interrupt
+ * channel in the DRAE/DRAEH register also.
+ * Also, if we have earlier saved this
+ * TCC in allocatedTCCs[] array,
+ * remove it from there too.
+ */
+ if (resId < 32U)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ &= (~((uint32_t)0x1U << resId));
+
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0U] &= (~((uint32_t)0x1U << resId));
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ &= (~((uint32_t)0x1U << (resId-32U)));
+
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1U] &= (~((uint32_t)0x1U << (resId -32U)));
+ }
+ }
+ }
result = EDMA3_RM_SOK;
}
{
if (resId < rmObj->gblCfgParams.numPaRAMSets)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32U])&(resIdSet))!=FALSE)
{
- if (((~(rmInstance->avlblPaRAMSets [resId/32u]))&(resIdSet))!=FALSE)
+ if (((~(rmInstance->avlblPaRAMSets [resId/32U]))&(resIdSet))!=FALSE)
{
- rmInstance->avlblPaRAMSets [resId/32u] |= resIdSet;
+ rmInstance->avlblPaRAMSets [resId/32U] |= resIdSet;
result = EDMA3_RM_SOK;
}
result = EDMA3_RM_E_INVALID_PARAM;
break;
}
-
+ semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
}
-
- edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
- intState);
}
}
+ /**
+ * Check the Free Resource Result 'result' first. If Free Resource
+ * has resulted in an error, return it (having more priority than
+ * semResult.
+ * Else, return semResult.
+ */
+ if (EDMA3_RM_SOK == result)
+ {
+ /**
+ * Free Resource successful, return semResult for returning
+ * semaphore.
+ */
+ result = semResult;
+ }
+
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
return result;
}
-
-
-/**
- * \fn EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle
- * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj,
- * unsigned int *pParam, unsigned int *pTcc)
- * \brief Request a DMA/QDMA/Link channel.
- *
- * This API is used to allocate a logical channel (DMA/QDMA/Link) along with
- * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are
- * also allocated along with the requested channel. For Link channel, ONLY a
- * PaRAM Set is allocated.
- *
- * Note: To free the logical channel allocated by this API, user should call
- * EDMA3_RM_freeLogicalChannel () ONLY to de-allocate all the allocated resources
- * and remove certain mappings.
- *
- * User can request a specific logical channel by passing the channel id in
- * 'lChObj->resId' and channel type in 'lChObj->type'. Note that the channel
- * id is the same as the actual resource id. For e.g. in the case of QDMA
- * channels, valid channel ids are from 0 to 7 only.
- *
- * User can also request ANY available logical channel of the type
- * 'lChObj->type' by specifying 'lChObj->resId' as:
- * a) EDMA3_RM_DMA_CHANNEL_ANY: For DMA channels
- * b) EDMA3_RM_QDMA_CHANNEL_ANY: For QDMA channels, and
- * c) EDMA3_RM_PARAM_ANY: For Link channels. Normally user should use this
- * value to request link channels (PaRAM Sets used for linking purpose
- * only), unless he wants to use some specific link channels (PaRAM Sets)
- * which is also allowed.
- *
- * This API internally uses EDMA3_RM_allocResource () to allocate the desired
- * resources (DMA/QDMA channel, PaRAM Set and TCC).
- *
- * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API
- * sets the TCC field of the OPT PaRAM Word with the allocated TCC.
- *
- * For DMA channel, it also sets the DCHMAP register, if required.
- *
- * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and
- * enables the QDMA channel by writing to the QEESR register.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param lChObj [IN/OUT] Handle to the requested logical channel
- * object, which needs to be allocated.
- * It could be a specific logical channel
- * or ANY available logical channel of the
- * requested type.
- * In case user passes a specific resource
- * Id, lChObj value is left unchanged. In
- * case user requests ANY available
- * resource, the allocated resource id is
- * returned in lChObj->resId.
- *
- * \param pParam [IN/OUT] PaRAM Set for a particular logical
- * (DMA/QDMA) channel. Not used if user
- * requested for a Link channel.
- * In case user passes a specific PaRAM
- * Set value, pParam value is left
- * unchanged. In case user requests ANY
- * available PaRAM Set, the allocated one
- * is returned in pParam.
- *
- * \param pTcc [IN/OUT] TCC for a particular logical (DMA/QDMA)
- * channel. Not used if user requested for
- * a Link channel.
- * In case user passes a specific TCC
- * value, pTcc value is left unchanged.
- * In case user requests ANY available TCC,
- * the allocated one is returned in pTcc
- *
- * \return EDMA3_RM_SOK or EDMA_RM Error Code
- *
- * \note This function internally calls EDMA3_RM_allocResource (), which
- * acquires a RM Instance specific semaphore to prevent simultaneous
- * access to the global pool of resources. It is re-entrant for unique
- * logical channel values, but SHOULD NOT be called from the user
- * callback function (ISR context).
- */
EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *lChObj,
- unsigned int *pParam,
- unsigned int *pTcc)
+ uint32_t *pParam,
+ uint32_t *pTcc)
{
EDMA3_RM_ResDesc *chObj;
EDMA3_RM_ResDesc resObj;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- unsigned int mappedPaRAMId=0u;
- unsigned int mappedTcc = EDMA3_RM_CH_NO_TCC_MAP;
- int paRAMId = (int)EDMA3_RM_RES_ANY;
+ uint32_t mappedPaRAMId=0U;
+ uint32_t mappedTcc = EDMA3_RM_CH_NO_TCC_MAP;
+ int32_t paRAMId = (int32_t)EDMA3_RM_RES_ANY;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
- unsigned int qdmaChId = EDMA3_MAX_PARAM_SETS;
- unsigned int edma3Id;
+ uint32_t qdmaChId = EDMA3_MAX_PARAM_SETS;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
/** If some PaRAM set is statically mapped to the returned
* channel number, use that.
*/
- paRAMId = (int)mappedPaRAMId;
+ paRAMId = (int32_t)mappedPaRAMId;
}
}
else
/* User specified some PaRAM Set; check that can be used or not. */
if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)
{
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
else
{
}
else
{
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
}
}
/** If some PaRAM set is statically mapped to the returned
* channel number, use that.
*/
- paRAMId = (int)mappedPaRAMId;
+ paRAMId = (int32_t)mappedPaRAMId;
}
}
else
/* User specified some PaRAM Set; check that can be used or not. */
if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)
{
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
else
{
}
else
{
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
}
}
if ((*pParam) != EDMA3_RM_PARAM_ANY)
{
/* User specified ANY PaRAM Set; Check the mapping. */
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
}
}
if ((*pParam) != EDMA3_RM_PARAM_ANY)
{
/* User specified ANY PaRAM Set; Check the mapping. */
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
}
}
|| (chObj->resId == EDMA3_RM_RES_ANY))
{
/* Request for ANY LINK channel. */
- paRAMId = (int)EDMA3_RM_RES_ANY;
+ paRAMId = (int32_t)EDMA3_RM_RES_ANY;
}
else
{
if (chObj->resId < edma3NumPaRAMSets)
{
/* Request for a Specific LINK channel. */
- paRAMId = (int)(chObj->resId);
+ paRAMId = (int32_t)(chObj->resId);
}
else
{
{
/* Try to allocate the link channel */
resObj.type = EDMA3_RM_RES_PARAM_SET;
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
if (result == EDMA3_RM_SOK)
{
- unsigned int linkCh = edma3_link_ch_min_val[edma3Id];
+ uint32_t linkCh = edma3_link_ch_min_val[edma3Id];
/* Return the actual PaRAM Id. */
chObj->resId = resObj.resId;
else
{
/* Save the PaRAM Id for the Link Channel. */
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId = (int)(chObj->resId);
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId = (int32_t)(chObj->resId);
/**
* Remove any linking. Before doing that, check
if (TRUE == rmInstance->regModificationRequired)
{
*((&gblRegs->PARAMENTRY[chObj->resId].OPT)
- + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFU;
}
}
}
break;
default:
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
/* First allocate a PaRAM Set */
resObj.type = EDMA3_RM_RES_PARAM_SET;
/* Use the saved param id now. */
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
if (result == EDMA3_RM_SOK)
{
* Save the PaRAM Set first.
*/
*pParam = resObj.resId;
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].paRAMId = (int)(resObj.resId);
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].paRAMId = (int32_t)(resObj.resId);
/* Allocate the TCC now. */
resObj.type = EDMA3_RM_RES_TCC;
/* Remove any linking */
*((&gblRegs->PARAMENTRY[*pParam].OPT)
- + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFU;
}
}
else
/* First allocate a PaRAM Set */
resObj.type = EDMA3_RM_RES_PARAM_SET;
/* Use the saved param id now. */
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
if (result == EDMA3_RM_SOK)
{
* Save the PaRAM Set first.
*/
*pParam = resObj.resId;
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = (int)(resObj.resId);
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = (int32_t)(resObj.resId);
/* Allocate the TCC now. */
resObj.type = EDMA3_RM_RES_TCC;
/* Remove any linking */
*((&gblRegs->PARAMENTRY[*pParam].OPT)
- + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFU;
/* Enable the transfer also. */
- rmInstance->shadowRegs->QEESR = (1u << chObj->resId);
+ rmInstance->shadowRegs->QEESR = (1U << chObj->resId);
}
}
else
return result;
}
-
-/** \fn EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle
- * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj)
- * \brief This API is used to free the specified channel (DMA/QDMA/Link) and
- * its associated resources (PaRAM Set, TCC etc).
- *
- * This API internally uses EDMA3_RM_freeResource () to free the desired
- * resources.
- *
- * For DMA/QDMA channels, it also clears the DCHMAP/QCHMAP registers
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param lChObj [IN] Handle to the logical channel object,
- * which needs to be freed
- *
- * \return EDMA3_RM_SOK or EDMA_RM Error Code
- *
- * \note This is a re-entrant function which internally calls
- * EDMA3_RM_freeResource () for resource de-allocation.
- */
EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *lChObj)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int paRAMId;
- unsigned int tcc;
+ int32_t paRAMId;
+ uint32_t tcc;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int qdmaChId;
- unsigned int dmaChId;
+ uint32_t qdmaChId;
+ uint32_t dmaChId;
EDMA3_RM_InstanceInitConfig *rmConfig = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
/* It should be owned and allocated by this RM only. */
if (result == EDMA3_RM_SOK)
{
- if (((rmConfig->ownDmaChannels[dmaChId/32u])
+ if (((rmConfig->ownDmaChannels[dmaChId/32U])
&
- (~(rmInstance->avlblDmaChannels[dmaChId/32u]))
+ (~(rmInstance->avlblDmaChannels[dmaChId/32U]))
&
- (1u << (dmaChId%32u))) != FALSE)
+ ((uint32_t)1U << (dmaChId%32U))) != FALSE)
{
/** Perfectly valid channel id.
* Clear some channel specific registers, if it is permitted.
*/
if (TRUE == rmInstance->regModificationRequired)
{
- if (dmaChId < 32u)
+ if (dmaChId < 32U)
{
- if((rmInstance->shadowRegs->SER & (1u<<dmaChId))!=FALSE)
+ if((rmInstance->shadowRegs->SER & ((uint32_t)1U<<dmaChId))!=FALSE)
{
- rmInstance->shadowRegs->SECR = (1u<<dmaChId);
+ rmInstance->shadowRegs->SECR = (1U<<dmaChId);
}
- if((globalRegs->EMR & (1u<<dmaChId))!=FALSE)
+ if((globalRegs->EMR & ((uint32_t)1U<<dmaChId))!=FALSE)
{
- globalRegs->EMCR = (1u<<dmaChId);
+ globalRegs->EMCR = (1U<<dmaChId);
}
}
else
{
- if((rmInstance->shadowRegs->SERH & (1u<<(dmaChId-32u)))!=FALSE)
+ if((rmInstance->shadowRegs->SERH & ((uint32_t)1U<<(dmaChId-32U)))!=FALSE)
{
- rmInstance->shadowRegs->SECRH = (1u<<(dmaChId-32u));
+ rmInstance->shadowRegs->SECRH = (1U<<(dmaChId-32U));
}
- if((globalRegs->EMRH & (1u<<(dmaChId-32u)))!=FALSE)
+ if((globalRegs->EMRH & ((uint32_t)1U<<(dmaChId-32U)))!=FALSE)
{
- globalRegs->EMCRH = (1u<<(dmaChId-32u));
+ globalRegs->EMCRH = (1U<<(dmaChId-32U));
}
}
/* Free the PaRAM Set Now. */
paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].paRAMId;
resObj.type = EDMA3_RM_RES_PARAM_SET;
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
}
else
/* It should be owned and allocated by this RM only. */
if (result == EDMA3_RM_SOK)
{
- if (((rmConfig->ownQdmaChannels[0u])
+ if (((rmConfig->ownQdmaChannels[0U])
&
- (~(rmInstance->avlblQdmaChannels[0u]))
+ (~(rmInstance->avlblQdmaChannels[0U]))
&
- (1u << chObj->resId)) != FALSE)
+ ((uint32_t)1U << chObj->resId)) != FALSE)
{
/** Perfectly valid channel id.
* Clear some channel specific registers, if
*/
if (TRUE == rmInstance->regModificationRequired)
{
- rmInstance->shadowRegs->QEECR = (1u<<chObj->resId);
+ rmInstance->shadowRegs->QEECR = (1U<<chObj->resId);
- if((globalRegs->QEMR & (1u<<chObj->resId))!=FALSE)
+ if((globalRegs->QEMR & ((uint32_t)1U<<chObj->resId))!=FALSE)
{
- globalRegs->QEMCR = (1u<<chObj->resId);
+ globalRegs->QEMCR = (1U<<chObj->resId);
}
/* Unmap PARAM Set Number for specified channelId */
/* Free the PaRAM Set now */
paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;
resObj.type = EDMA3_RM_RES_PARAM_SET;
- resObj.resId = (int)paRAMId;
+ resObj.resId = (int32_t)paRAMId;
result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
}
else
if (result == EDMA3_RM_SOK)
{
/* PaRAM Set freed successfully. */
- unsigned int linkCh = edma3_link_ch_min_val[edma3Id];
+ uint32_t linkCh = edma3_link_ch_min_val[edma3Id];
/* Reset the Logical-Link channel */
/* Search for the Logical-Link channel first */
break;
default:
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
return result;
}
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle
- * hEdmaResMgr, unsigned int channelId, unsigned int paRAMId)
- * \brief Bind the resources DMA Channel and PaRAM Set. Both the DMA channel
- * and the PaRAM set should be previously allocated. If they are not,
- * this API will result in error.
- *
- * This API sets the DCHMAP register for a specific DMA channel. This register
- * is used to specify the PaRAM Set associated with that particular DMA Channel.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param channelId [IN] Previously allocated DMA Channel on which
- * Transfer will occur.
- * \param paRAMId [IN] Previously allocated PaRAM Set which
- * needs to be associated with the dma channel.
- *
- * \return EDMA3_RM_SOK or EDMA_RM Error Code
- *
- * \note This API is useful only for the EDMA3 Controllers which have a
- * register for mapping a DMA Channel to a particular PaRAM Set
- * (DCHMAP register).
- * On platforms where this feature is not supported, this API
- * returns error code: EDMA3_RM_E_FEATURE_UNSUPPORTED.
- * This function is re-entrant for unique channelId. It is
- * non-re-entrant for same channelId values.
- */
EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int channelId,
- unsigned int paRAMId)
+ uint32_t channelId,
+ uint32_t paRAMId)
{
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
/* DMA channel and PaRAM Set should be previously allocated. */
if (result == EDMA3_RM_SOK)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[channelId/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[channelId/32U])
&
- (~(rmInstance->avlblDmaChannels[channelId/32u]))
+ (~(rmInstance->avlblDmaChannels[channelId/32U]))
&
- (1u << (channelId%32u))) != FALSE)
+ ((uint32_t)1U << (channelId%32U))) != FALSE)
{
/* DMA channel allocated, check for the PaRAM Set */
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32U])
&
- (~(rmInstance->avlblPaRAMSets[paRAMId/32u]))
+ (~(rmInstance->avlblPaRAMSets[paRAMId/32U]))
&
- (1u << (paRAMId%32u))) == FALSE)
+ ((uint32_t)1U << (paRAMId%32U))) == FALSE)
{
/* PaRAM Set NOT allocated, return error */
result = EDMA3_RM_E_RES_NOT_ALLOCATED;
return result;
}
-
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle
- * hEdmaResMgr, unsigned int channelId,
- * unsigned int paRAMId,
- * EDMA3_RM_QdmaTrigWord trigWord)
- * \brief Bind the resources QDMA Channel and PaRAM Set. Also, Set the
- * trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set
- * should be previously allocated. If they are not, this API will result in error.
- *
- * This API sets the QCHMAP register for a specific QDMA channel. This register
- * is used to specify the PaRAM Set associated with that particular QDMA
- * Channel along with the trigger word.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param channelId [IN] Previously allocated QDMA Channel on which
- * Transfer will occur.
- * \param paRAMId [IN] Previously allocated PaRAM Set, which needs to
- * be associated with channelId
- * \param trigWord [IN] The Trigger Word for the channel.
- * Trigger Word is the word in the PaRAM
- * Register Set which - when written to by CPU
- * -will start the QDMA transfer automatically
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant for unique channelId. It is non-re-entrant
- * for same channelId values.
- */
EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int channelId,
- unsigned int paRAMId,
+ uint32_t channelId,
+ uint32_t paRAMId,
EDMA3_RM_QdmaTrigWord trigWord)
{
EDMA3_RM_Instance *rmInstance = NULL;
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
if ((hEdmaResMgr == NULL)
- || ((trigWord < EDMA3_RM_QDMA_TRIG_OPT)
+ || (((int32_t)trigWord < (int32_t)EDMA3_RM_QDMA_TRIG_OPT)
|| (trigWord > EDMA3_RM_QDMA_TRIG_CCNT)))
{
result = EDMA3_RM_E_INVALID_PARAM;
/* QDMA channel and PaRAM Set should be previously allocated. */
if (result == EDMA3_RM_SOK)
{
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[channelId/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[channelId/32U])
&
- (~(rmInstance->avlblQdmaChannels[channelId/32u]))
+ (~(rmInstance->avlblQdmaChannels[channelId/32U]))
&
- (1u << (channelId%32u))) != FALSE)
+ ((uint32_t)1U << (channelId%32U))) != FALSE)
{
/* QDMA channel allocated, check for the PaRAM Set */
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32u])
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[paRAMId/32U])
&
- (~(rmInstance->avlblPaRAMSets[paRAMId/32u]))
+ (~(rmInstance->avlblPaRAMSets[paRAMId/32U]))
&
- (1u << (paRAMId%32u))) == FALSE)
+ ((uint32_t)1U << (paRAMId%32U))) == FALSE)
{
/* PaRAM Set NOT allocated, return error */
result = EDMA3_RM_E_RES_NOT_ALLOCATED;
return result;
}
-
-
-/**
- * \fn EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr,
- * const EDMA3_RM_ResDesc *channelObj, unsigned int tcc,
- * EDMA3_RM_TccCallback tccCb, void *cbData);
- * \brief Register Interrupt / Completion Handler for a given TCC.
- *
- * This function enables the interrupts in IESR/IESRH, only if the callback
- * function provided by the user is NON-NULL. Moreover, if a call-back function
- * is already registered against that TCC, the API fails with the error code
- * EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED. For a NULL callback function,
- * this API returns error.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened
- * EDMA3 Resource Manager Instance
- * \param channelObj [IN] Channel ID and type (DMA or QDMA
- * Channel), allocated earlier, and
- * corresponding to which a callback
- * function needs to be registered
- * against the associated TCC.
- * \param tcc [IN] TCC against which the handler needs to
- * be registered.
- * \param tccCb [IN] The Callback function to be registered
- * against the TCC.
- * \param cbData [IN] Callback data to be passed while calling
- * the callback function.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant for unique tcc values. It is non-
- * re-entrant for same tcc value.
- */
EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr,
const EDMA3_RM_ResDesc *channelObj,
- unsigned int tcc,
+ uint32_t tcc,
EDMA3_RM_TccCallback tccCb,
void *cbData)
{
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
- unsigned int edma3Id;
+ uint32_t edma3Id;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
if (EDMA3_RM_SOK == result)
{
- /**
- * Enable the Interrupt channel in the DRAE/DRAEH registers also.
- * Also, If the region id coming from this RM instance is same as the
- * Master RM Instance's region id, only then we will be getting the
- * interrupts on the same side.
- * So save the TCC in the allocatedTCCs[] array.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- if (tcc < 32u)
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << tcc);
-
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][0u] |= (0x1u << tcc);
- }
- }
- else
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (tcc - 32u));
-
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][1u] |= (0x1u << (tcc - 32u));
- }
- }
- }
/* Enable the interrupts in IESR/IESRH */
- if (tcc < 32u)
+ if (tcc < 32U)
{
rmInstance->shadowRegs->IESR = (1UL << tcc);
}
else
{
- rmInstance->shadowRegs->IESRH = (1UL << (tcc-32u));
+ rmInstance->shadowRegs->IESRH = (1UL << (tcc-32U));
}
/* Save the callback functions also */
return result;
}
-/**
- * \fn EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle
- * hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj);
- * \brief Unregister the previously registered callback function against a
- * DMA/QDMA channel.
- *
- * This function unregisters the previously registered callback function against
- * a DMA/QDMA channel by removing any stored callback function. Moreover, it
- * clears the interrupt enable register (IESR/IESRH) by writing to the IECR/
- * IECRH register, for the TCC associated with that particular channel.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened
- * EDMA3 Resource Manager Instance
- * \param channelObj [IN] Channel ID and type, allocated earlier
- * (DMA or QDMA Channel ONLY), and
- * corresponding to which a TCC is there.
- * Against that TCC, the callback needs
- * to be un-registered.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code.
- *
- * \note This function is re-entrant for unique (channelObj->type +
- * channelObj->resId) combination. It is non-re-entrant for same
- * channelObj Resource.
- */
EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle hEdmaResMgr,
const EDMA3_RM_ResDesc *channelObj)
{
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
- unsigned int mappedTcc = EDMA3_MAX_TCC;
- unsigned int edma3Id;
+ uint32_t mappedTcc = EDMA3_MAX_TCC;
+ uint32_t edma3Id;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
if (EDMA3_RM_SOK == result)
{
- if (TRUE == rmInstance->regModificationRequired)
- {
- /**
- * Interrupt Channel is freed. Reset the bit specific to the Interrupt
- * channel in the DRAE/DRAEH register also. Also, if we have earlier
- * saved this TCC in allocatedTCCs[] array, remove it from there too.
- */
- if (mappedTcc < 32u)
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- &= (~(0x1u << mappedTcc));
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][0u] &= (~(0x1u << mappedTcc));
- }
- }
- else
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- &= (~(0x1u << (mappedTcc-32u)));
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][1u] &= (~(0x1u << (mappedTcc-32u)));
- }
- }
- }
/* Remove the callback function too */
- if (mappedTcc < 32u)
+ if (mappedTcc < 32U)
{
rmInstance->shadowRegs->IECR = (1UL << mappedTcc);
}
+ else if(mappedTcc < 64U)
+ {
+ rmInstance->shadowRegs->IECRH = (1UL << (mappedTcc-32U));
+ }
else
{
- rmInstance->shadowRegs->IECRH = (1UL << (mappedTcc-32u));
+ /* To Comply MISRA C warning */
+ result = EDMA3_RM_SOK;
}
- edma3IntrParams[edma3Id][mappedTcc].cbData = NULL;
- edma3IntrParams[edma3Id][mappedTcc].tccCb = NULL;
+ if(mappedTcc < EDMA3_MAX_TCC)
+ {
+ edma3IntrParams[edma3Id][mappedTcc].cbData = NULL;
+ edma3IntrParams[edma3Id][mappedTcc].tccCb = NULL;
+ }
}
#ifdef EDMA3_INSTRUMENTATION_ENABLED
return result;
}
-
-/**\fn EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle
- * hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj,
- * unsigned int numResources)
- * \brief Allocate a contiguous region of specified EDMA3 Resource
- * like DMA channel, QDMA channel, PaRAM Set or TCC.
- *
- * This API is used to allocate a contiguous region of specified EDMA3
- * Resources like DMA channel, QDMA channel, PaRAM Set or TCC.
- *
- * User can specify a particular resource Id to start with and go up to the
- * number of resources requested. The specific resource id to start from could
- * be passed in 'firstResIdObject->resId' and the number of resources requested
- * in 'numResources'.
- *
- * User can also request ANY available resource(s) of the type
- * 'firstResIdObject->type' by specifying 'firstResIdObject->resId' as
- * EDMA3_RM_RES_ANY.
- *
- * ANY types of resources are those resources when user doesn't care about the
- * actual resource allocated; user just wants a resource of the type specified.
- * One use-case is to perform memory-to-memory data transfer operation. This
- * operation can be performed using any available DMA or QDMA channel. User
- * doesn't need any specific channel for the same.
- *
- * To allocate specific contiguous resources, first this API checks whether
- * those requested resources are OWNED by the Resource Manager instance. Then
- * it checks the current availability of those resources.
- *
- * To allocate ANY available contiguous resources, this API tries to allocate
- * resources from the pool of (owned && non_reserved && available_right_now)
- * resources.
- *
- * After allocating DMA/QDMA channels or TCCs, the same resources are enabled in
- * the shadow region specific register (DRAE/DRAEH/QRAE). Allocated PaRAM Sets
- * are initialized to NULL before this API returns.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param firstResIdObj [IN] Handle to the first resource descriptor
- * object, which needs to be allocated.
- * firstResIdObject->resId could be a valid
- * resource id in case user wants to
- * allocate specific resources OR it could
- * be EDMA3_RM_RES_ANY in case user wants
- * only the required number of resources
- * and doesn't care about which resources
- * were allocated.
- * \param numResources [IN] Number of contiguous resources user
- * wants to allocate.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function acquires a RM Instance specific semaphore
- * to prevent simultaneous access to the global pool of resources.
- * It is re-entrant, but should not be called from the user callback
- * function (ISR context).
- */
EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *firstResIdObj,
- unsigned int numResources)
+ uint32_t numResources)
{
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_ResDesc *resObj = NULL;
- unsigned int resAllocIdx = 0u;
- unsigned int firstResId;
- unsigned int lastResId = 0u;
- unsigned int maxNumResources = 0u;
+ uint32_t resAllocIdx = 0U;
+ uint32_t firstResId;
+ uint32_t lastResId = 0U;
+ uint32_t maxNumResources = 0U;
EDMA3_RM_Result semResult = EDMA3_RM_SOK;
- unsigned int resIdClr = 0x0;
- unsigned int resIdSet = 0x0;
+ uint32_t resIdClr = 0x0;
+ uint32_t resIdSet = 0x0;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
- unsigned int i = 0u;
- unsigned int position = 0u;
- unsigned int edma3Id;
+ uint32_t i = 0U;
+ uint32_t position = 0U;
+ uint32_t edma3Id;
+ uint32_t errFlag=0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -3815,22 +3579,22 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u)));
- resIdSet = (1u << (resAllocIdx%32u));
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resAllocIdx%32U)));
+ resIdSet = (1U << (resAllocIdx%32U));
/* Check whether it is owned or not */
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resAllocIdx/32u])&(resIdSet)) != FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resAllocIdx/32U])&(resIdSet)) != FALSE)
{
/* Now check if specified resource is available presently*/
- if (((rmInstance->avlblDmaChannels[resAllocIdx/32u])&(resIdSet)) != FALSE)
+ if (((rmInstance->avlblDmaChannels[resAllocIdx/32U])&(resIdSet)) != FALSE)
{
/*
* Mark the specified resource as "Not Available"
* for future requests
*/
- rmInstance->avlblDmaChannels[resAllocIdx/32u] &= resIdClr;
+ rmInstance->avlblDmaChannels[resAllocIdx/32U] &= resIdClr;
- if (resAllocIdx < 32u)
+ if (resAllocIdx < 32U)
{
rmInstance->shadowRegs->EECR = (1UL << resAllocIdx);
@@ -3839,18 +3603,18 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* DRAE registers also.
*/
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << resAllocIdx);
+ |= ((uint32_t)0x1U << resAllocIdx);
}
else
{
- rmInstance->shadowRegs->EECRH = (1UL << (resAllocIdx - 32u));
+ rmInstance->shadowRegs->EECRH = (1UL << (resAllocIdx - 32U));
/**
* Enable the DMA channel in the
* DRAEH registers also.
*/
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (resAllocIdx - 32u));
+ |= ((uint32_t)0x1U << (resAllocIdx - 32U));
}
result = EDMA3_RM_SOK;
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
@@ -3869,7 +3633,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
@@ -3880,27 +3648,27 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (unsigned int)(~(1u << resAllocIdx));
- resIdSet = (1u << resAllocIdx);
+ resIdClr = (uint32_t)(~((uint32_t)1U << resAllocIdx));
+ resIdSet = (1U << resAllocIdx);
/* Check whether it is owned or not */
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U])&(resIdSet))!=FALSE)
{
/* Now check if specified resource is available presently*/
- if (((rmInstance->avlblQdmaChannels[0u])&(resIdSet))!=FALSE)
+ if (((rmInstance->avlblQdmaChannels[0U])&(resIdSet))!=FALSE)
{
/*
* Mark the specified resource as "Not Available"
* for future requests
*/
- rmInstance->avlblQdmaChannels[0u] &= resIdClr;
+ rmInstance->avlblQdmaChannels[0U] &= resIdClr;
/**
* Enable the QDMA channel in the
* QRAE register also.
*/
gblRegs->QRAE[rmInstance->initParam.regionId]
- |= (0x1u << resAllocIdx);
+ |= ((uint32_t)0x1U << resAllocIdx);
result = EDMA3_RM_SOK;
}
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
@@ -3918,7 +3686,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
@@ -3929,20 +3701,20 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u)));
- resIdSet = (1u << (resAllocIdx%32u));
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resAllocIdx%32U)));
+ resIdSet = (1U << (resAllocIdx%32U));
/* Check whether it is owned or not */
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs[resAllocIdx/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs[resAllocIdx/32U])&(resIdSet))!=FALSE)
{
/* Now check if specified resource is available presently*/
- if (((rmInstance->avlblTccs[resAllocIdx/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->avlblTccs[resAllocIdx/32U])&(resIdSet))!=FALSE)
{
/*
* Mark the specified resource as "Not Available"
* for future requests
*/
- rmInstance->avlblTccs[resAllocIdx/32u] &= resIdClr;
+ rmInstance->avlblTccs[resAllocIdx/32U] &= resIdClr;
/**
* If the region id coming from this
@@ -3953,13 +3725,13 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
*/
if (edma3RegionId == rmInstance->initParam.regionId)
{
- if (resAllocIdx < 32u)
+ if (resAllocIdx < 32U)
{
- allocatedTCCs[edma3Id][0u] |= (0x1u << resAllocIdx);
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << resAllocIdx);
}
else
{
- allocatedTCCs[edma3Id][1u] |= (0x1u << (resAllocIdx - 32u));
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (resAllocIdx - 32U));
}
}
result = EDMA3_RM_SOK;
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
@@ -3978,7 +3750,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
@@ -3989,20 +3765,20 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u)));
- resIdSet = (1u << (resAllocIdx%32u));
+ resIdClr = (uint32_t)(~((uint32_t)1U << (resAllocIdx%32U)));
+ resIdSet = (1U << (resAllocIdx%32U));
/* Check whether it is owned or not */
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resAllocIdx/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[resAllocIdx/32U])&(resIdSet))!=FALSE)
{
/* Now check if specified resource is available presently*/
- if (((rmInstance->avlblPaRAMSets[resAllocIdx/32u])&(resIdSet))!=FALSE)
+ if (((rmInstance->avlblPaRAMSets[resAllocIdx/32U])&(resIdSet))!=FALSE)
{
/*
* Mark the specified resource as "Not Available"
* for future requests
*/
- rmInstance->avlblPaRAMSets[resAllocIdx/32u] &= resIdClr;
+ rmInstance->avlblPaRAMSets[resAllocIdx/32U] &= resIdClr;
/**
* Also, make the actual PARAM Set NULL, checking the flag
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
@@ -4030,7 +3806,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
@@ -4072,13 +3852,13 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
case EDMA3_RM_RES_DMA_CHANNEL:
{
/* AND all the arrays to look into */
- contiguousDmaRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0u]
- & rmInstance->avlblDmaChannels[0u])
- & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[0u]))
+ contiguousDmaRes[0U] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0U]
+ & rmInstance->avlblDmaChannels[0U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[0U]))
);
- contiguousDmaRes[1u] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1u]
- & rmInstance->avlblDmaChannels[1u])
- & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[1u]))
+ contiguousDmaRes[1U] = ((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1U]
+ & rmInstance->avlblDmaChannels[1U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[1U]))
);
}
break;
case EDMA3_RM_RES_QDMA_CHANNEL:
{
/* AND all the arrays to look into */
- contiguousQdmaRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u]
- & rmInstance->avlblQdmaChannels[0u])
- & (~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[0u]))
+ contiguousQdmaRes[0U] = ((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U]
+ & rmInstance->avlblQdmaChannels[0U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[0U]))
);
}
break;
@@ -4096,13 +3876,13 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
case EDMA3_RM_RES_TCC:
{
/* AND all the arrays to look into */
- contiguousTccRes[0u] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[0u]
- & rmInstance->avlblTccs[0u])
- & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[0u]))
+ contiguousTccRes[0U] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[0U]
+ & rmInstance->avlblTccs[0U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[0U]))
);
- contiguousTccRes[1u] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[1u]
- & rmInstance->avlblTccs[1u])
- & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[1u]))
+ contiguousTccRes[1U] = ((rmInstance->initParam.rmInstInitConfig->ownTccs[1U]
+ & rmInstance->avlblTccs[1U])
+ & (~(rmInstance->initParam.rmInstInitConfig->resvdTccs[1U]))
);
}
break;
case EDMA3_RM_RES_PARAM_SET:
{
/* AND all the arrays to look into */
- for (i = 0u; i < (maxNumResources/32u); ++i)
+ for (i = 0U; i < (maxNumResources/32U); ++i)
{
contiguousParamRes[i] = ((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets[i]
& rmInstance->avlblPaRAMSets[i])
@@ -4185,49 +3965,18 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
return result;
}
-
-
-/**
- * \fn EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle
- * hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj,
- * unsigned int numResources)
- * \brief Free a contiguous region of specified EDMA3 Resource
- * like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated.
- *
- * This API frees a contiguous region of specified EDMA3 Resources
- * like DMA channel, QDMA channel, PaRAM Set or TCC, which have been previously
- * allocated. In case of an error during the freeing of any specific resource,
- * user can check the 'firstResIdObj' object to know the last resource id
- * whose freeing has failed. In case of success, there is no need to check this
- * object.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened
- * Resource Manager Instance.
- * \param firstResIdObj [IN/OUT] Handle to the first resource
- * descriptor object, which needs to be
- * freed. In case of an error while
- * freeing any particular resource,
- * the last resource id whose freeing has
- * failed is returned in this resource
- * descriptor object.
- * \param numResources [IN] Number of contiguous resources allocated
- * previously which user wants to release
- *
- * \note This is a re-entrant function which internally calls
- * EDMA3_RM_freeResource() for resource de-allocation.
- */
EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *firstResIdObj,
- unsigned int numResources)
+ uint32_t numResources)
{
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_ResDesc *resObj;
- unsigned int resFreeIdx = 0u;
- unsigned int firstResId;
- unsigned int lastResId;
- unsigned int maxNumResources = 0u;
+ uint32_t resFreeIdx = 0U;
+ uint32_t firstResId;
+ uint32_t lastResId;
+ uint32_t maxNumResources = 0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
if (resObj != NULL)
{
firstResId = resObj->resId;
- lastResId = firstResId + (numResources - 1u);
+ lastResId = firstResId + (numResources - 1U);
}
switch (resObj->type)
@@ -4317,38 +4066,15 @@ EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
return result;
}
-
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr,
- * unsigned int regOffset,
- * unsigned int newRegValue)
- * \brief Set the Channel Controller (CC) Register value
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param regOffset [IN] CC Register offset whose value needs to be
- * set. It should be word-aligned.
- * \param newRegValue [IN] New CC Register Value
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is non re-entrant for users using the same
- * Resource Manager handle.
- * Before modifying a register, it tries to acquire a semaphore
- * (RM instance specific), to protect simultaneous
- * modification of the same register by two different users.
- * After the successful change, it releases the semaphore.
- * For users using different RM handles, this function is re-entrant.
- */
EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int regOffset,
- unsigned int newRegValue)
+ uint32_t regOffset,
+ uint32_t newRegValue)
{
+ uint32_t intState;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- volatile unsigned int regPhyAddr = 0x0u;
+ volatile uint32_t regPhyAddr = 0x0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
- if ((hEdmaResMgr == NULL) || ((regOffset % 4u) != 0))
+ if ((hEdmaResMgr == NULL) || ((regOffset % 4U) != 0))
{
result = (EDMA3_RM_E_INVALID_PARAM);
}
if (EDMA3_RM_SOK == result)
{
/* Semaphore taken successfully, modify the registers. */
- regPhyAddr = (unsigned int)(rmObj->gblCfgParams.globalRegs) + regOffset;
+ edma3OsProtectEntry (rmObj->phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ &intState);
+ /* Global interrupts disabled, modify the registers. */
+ regPhyAddr = (uint32_t)(rmObj->gblCfgParams.globalRegs) + regOffset;
- *(unsigned int *)regPhyAddr = newRegValue;
+ *(uint32_t *)regPhyAddr = newRegValue;
+ edma3OsProtectExit (rmObj->phyCtrllerInstId,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
+ intState);
/* Return the semaphore back */
result = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
return result;
}
-
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr,
- * unsigned int regOffset,
- * unsigned int *regValue)
- * \brief Get the Channel Controller (CC) Register value
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param regOffset [IN] CC Register offset whose value is
- * needed. It should be word-aligned.
- * \param regValue [IN/OUT] Fetched CC Register Value
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant.
- */
EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int regOffset,
- unsigned int *regValue)
+ uint32_t regOffset,
+ uint32_t *regValue)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- volatile unsigned int regPhyAddr = 0x0u;
+ volatile uint32_t regPhyAddr = 0x0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
if (((hEdmaResMgr == NULL) || (regValue == NULL))
- || ((regOffset % 4u) != 0))
+ || ((regOffset % 4U) != 0))
{
result = (EDMA3_RM_E_INVALID_PARAM);
}
{
if (rmObj->gblCfgParams.globalRegs != NULL)
{
- regPhyAddr = (unsigned int)(rmObj->gblCfgParams.globalRegs) + regOffset;
+ regPhyAddr = (uint32_t)(rmObj->gblCfgParams.globalRegs) + regOffset;
- *regValue = *(unsigned int *)regPhyAddr;
+ *regValue = *(uint32_t *)regPhyAddr;
}
}
}
return result;
}
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle
- * hEdmaResMgr, unsigned int tccNo)
- * \brief Wait for a transfer completion interrupt to occur and clear it.
- *
- * This is a blocking function that returns when the IPR/IPRH bit corresponding
- * to the tccNo specified, is SET. It clears the corresponding bit while
- * returning also.
- *
- * This function waits for the specific bit indefinitely in a tight loop, with
- * out any delay in between. USE IT CAUTIOUSLY.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param tccNo [IN] TCC, specific to which the function
- * waits on a IPR/IPRH bit.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant for different tccNo.
- *
- */
EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int tccNo)
+ uint32_t tccNo)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- unsigned int tccBitMask = 0x0u;
+ uint32_t tccBitMask = 0x0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
if (shadowRegs != NULL)
{
- if(tccNo < 32u)
+ if(tccNo < 32U)
{
- tccBitMask = (1u << tccNo);
+ tccBitMask = (1U << tccNo);
/* Check the status of the IPR[tccNo] bit. */
- while (FALSE == (shadowRegs->IPR & tccBitMask))
+ while ((uint32_t)FALSE == (shadowRegs->IPR & tccBitMask))
{
/* Transfer not yet completed, bit not SET */
}
}
else
{
- tccBitMask = (1u << (tccNo - 32u));
+ tccBitMask = (1U << (tccNo - 32U));
/* Check the status of the IPRH[tccNo-32] bit. */
- while (FALSE == (shadowRegs->IPRH & tccBitMask))
+ while ((uint32_t)FALSE == (shadowRegs->IPRH & tccBitMask))
{
/* Transfer not yet completed, bit not SET */
}
return result;
}
-
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle
- * hEdmaResMgr, unsigned int tccNo,
- * unsigned short *tccStatus)
- * \brief Returns the status of a previously initiated transfer.
- *
- * This is a non-blocking function that returns the status of a previously
- * initiated transfer, based on the IPR/IPRH bit. This bit corresponds to
- * the tccNo specified by the user. It clears the corresponding bit, if SET,
- * while returning also.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param tccNo [IN] TCC, specific to which the function
- * checks the status of the IPR/IPRH bit.
- * \param tccStatus [IN/OUT] Status of the transfer is returned here.
- * Returns "TRUE" if the transfer has
- * completed (IPR/IPRH bit SET),
- * "FALSE" if the transfer has not
- * completed successfully (IPR/IPRH bit
- * NOT SET).
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant for different tccNo.
- */
EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int tccNo,
- unsigned short *tccStatus)
+ uint32_t tccNo,
+ uint16_t *tccStatus)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- unsigned int tccBitMask = 0x0u;
+ uint32_t tccBitMask = 0x0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
if (shadowRegs != NULL)
{
- if(tccNo < 32u)
+ if(tccNo < 32U)
{
- tccBitMask = (1u << tccNo);
+ tccBitMask = (1U << tccNo);
/* Check the status of the IPR[tccNo] bit. */
if ((shadowRegs->IPR & tccBitMask) != FALSE)
}
else
{
- tccBitMask = (1u << (tccNo - 32u));
+ tccBitMask = (1U << (tccNo - 32U));
/* Check the status of the IPRH[tccNo-32] bit. */
if ((shadowRegs->IPRH & tccBitMask) != FALSE)
return result;
}
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
- * EDMA3_RM_ResDesc *lChObj,
- * const EDMA3_RM_PaRAMRegs *newPaRAM)
- * \brief Copy the user specified PaRAM Set onto the PaRAM Set
- * associated with the logical channel (DMA/QDMA/Link).
- *
- * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set
- * associated with the logical channel. OPT field of the PaRAM Set is written
- * first and the CCNT field is written last.
- *
- * Caution: It should be used carefully when programming the QDMA channels whose
- * trigger words are not CCNT field.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param lChObj [IN] Logical Channel object for which new
- * PaRAM set is specified. User should pass
- * the resource type and id in this object.
- * \param newPaRAM [IN] PaRAM set to be copied onto existing one
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant for unique lChObj values. It is non-
- * re-entrant for same lChObj value.
- */
EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
const EDMA3_RM_PaRAMRegs *newPaRAM)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int paRAMId = 0u;
- unsigned int qdmaChId = 0u;
+ int32_t paRAMId = 0;
+ uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
* User has passed the actual param set value here.
* Use this value only
*/
- paRAMId = (int)(lChObj->resId);
+ paRAMId = (int32_t)(lChObj->resId);
}
else
{
break;
default:
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
if (result == EDMA3_RM_SOK)
{
/* Check the param id first. */
- if ((paRAMId != -1) && ((unsigned int)paRAMId < edma3NumPaRAMSets))
+ if ((paRAMId != -1) && ((uint32_t)paRAMId < edma3NumPaRAMSets))
{
/* Set the PaRAM Set now. */
- edma3ParamCpy ((void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)),
+ edma3ParamCpy ((volatile void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)),
(const void *)newPaRAM);
}
else
return result;
}
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
- * EDMA3_RM_ResDesc *lChObj,
- * EDMA3_RM_PaRAMRegs *currPaRAM)
- * \brief Retrieve existing PaRAM set associated with specified logical
- * channel (DMA/QDMA/Link).
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param lChObj [IN] Logical Channel object for which the
- * PaRAM set is requested. User should pass
- * the resource type and id in this object.
- * \param currPaRAM [IN/OUT] User gets the existing PaRAM here.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant.
- */
EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
EDMA3_RM_PaRAMRegs *currPaRAM)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int paRAMId = 0u;
- unsigned int qdmaChId = 0u;
+ int32_t paRAMId = 0;
+ uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
* User has passed the actual param set value here.
* Use this value only
*/
- paRAMId = (int)(lChObj->resId);
+ paRAMId = (int32_t)(lChObj->resId);
}
else
{
break;
default:
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
if (result == EDMA3_RM_SOK)
{
/* Check the param id first. */
- if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets))
+ if ((paRAMId != -1) && ((uint32_t)paRAMId < edma3NumPaRAMSets))
{
/* Get the PaRAM Set now. */
edma3ParamCpy ((void *)currPaRAM ,
- (const void *)(&(globalRegs->PARAMENTRY [paRAMId].OPT)));
+ (const volatile void *)(&(globalRegs->PARAMENTRY [paRAMId].OPT)));
}
else
{
return result;
}
-
-/**\fn EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle
- * hEdmaResMgr, EDMA3_RM_ResDesc *lChObj,
- * unsigned int *paramPhyAddr)
- * \brief Get the PaRAM Set Physical Address associated with a logical channel
- *
- * This function returns the PaRAM Set Phy Address (unsigned 32 bits).
- * The returned address could be used by the advanced users to program the
- * PaRAM Set directly without using any APIs.
- *
- * Least significant 16 bits of this address could be used to program
- * the LINK field in the PaRAM Set.
- * Users which program the LINK field directly SHOULD use this API
- * to get the associated PaRAM Set address with the LINK channel.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param lChObj [IN] Logical Channel object for which the
- * PaRAM set physical address is required.
- * User should pass the resource type and
- * id in this object.
- * \param paramPhyAddr [IN/OUT] PaRAM Set physical address is returned
- * here.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant.
- */
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
- unsigned int *paramPhyAddr)
+ const EDMA3_RM_ResDesc *lChObj,
+ uint32_t *paramPhyAddr)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int paRAMId = 0u;
- unsigned int qdmaChId = 0u;
+ int32_t paRAMId = 0;
+ uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
* User has passed the actual param set value here.
* Use this value only
*/
- paRAMId = (int)(lChObj->resId);
+ paRAMId = (int32_t)(lChObj->resId);
}
else
{
break;
default:
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
-
-
if (result == EDMA3_RM_SOK)
{
/* Check the param id first. */
- if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets))
+ if ((paRAMId != -1) && (paRAMId < (int32_t)edma3NumPaRAMSets))
{
/* Get the PaRAM Set Address now. */
- *paramPhyAddr = (unsigned int)(&(globalRegs->PARAMENTRY [paRAMId].OPT));
+ *paramPhyAddr = (uint32_t)(&(globalRegs->PARAMENTRY [paRAMId].OPT));
}
else
{
return result;
}
-
-/**\fn EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle
- * hEdmaResMgr, EDMA3_RM_Cntrlr_PhyAddr controllerId,
- * unsigned int *phyAddress)
- * \brief Get the Channel Controller or Transfer Controller (n) Physical
- * Address.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param controllerId [IN] Channel Controller or Transfer
- * Controller (n) for which the physical
- * address is required.
- * \param phyAddress [IN/OUT] Physical address is returned here.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant.
- */
EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_Cntrlr_PhyAddr controllerId,
- unsigned int *phyAddress)
+ uint32_t *phyAddress)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
/* Verify the 'controllerId' */
- if ((controllerId < ((EDMA3_RM_Cntrlr_PhyAddr)(EDMA3_RM_CC_PHY_ADDR)))
+ if (((int32_t)controllerId < (int32_t)((EDMA3_RM_Cntrlr_PhyAddr)(EDMA3_RM_CC_PHY_ADDR)))
|| (controllerId > (EDMA3_RM_Cntrlr_PhyAddr)(rmObj->gblCfgParams.numTcs)))
{
/* Invalid controllerId */
if (controllerId == EDMA3_RM_CC_PHY_ADDR)
{
/* EDMA3 Channel Controller Address */
- *phyAddress = (unsigned int)(rmObj->gblCfgParams.globalRegs);
+ *phyAddress = (uint32_t)(rmObj->gblCfgParams.globalRegs);
}
else
{
* Since the TCs enum start from 1, and TCs start from 0,
* subtract 1 from the enum to get the actual address.
*/
- *phyAddress = (unsigned int)(rmObj->gblCfgParams.tcRegs[controllerId-1u]);
+ *phyAddress = (uint32_t)(rmObj->gblCfgParams.tcRegs[controllerId-1U]);
}
}
}
return result;
}
-
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int phyCtrllerInstId,
- * EDMA3_RM_GblConfigParams *gblCfgParams)
- * \brief Get the SoC specific configuration structure for the EDMA3 Hardware.
- *
- * This API is used to fetch the global SoC specific configuration structure
- * for the EDMA3 Hardware. It is useful for the user who has not passed
- * this information during EDMA3_RM_create() and taken the default configuration
- * coming along with the package.
- *
- * \param phyCtrllerInstId [IN] EDMA3 Controller Instance Id
- * (Hardware instance id, starting from 0).
- * \param gblCfgParams [IN/OUT] SoC specific configuration structure for the
- * EDMA3 Hardware will be returned here.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant.
- */
EDMA3_RM_Result EDMA3_RM_getGblConfigParams (
- unsigned int phyCtrllerInstId,
+ uint32_t phyCtrllerInstId,
EDMA3_RM_GblConfigParams *gblCfgParams)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
return result;
}
-
-
-/**\fn EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr,
- * EDMA3_RM_InstanceInitConfig *instanceInitConfig)
- * \brief Get the RM Instance specific configuration structure for different
- * EDMA3 resources' usage (owned resources, reserved resources etc).
- *
- * This API is used to fetch the Resource Manager Instance specific configuration
- * structure, for a specific shadow region. It is useful for the user who has not passed
- * this information during EDMA3_RM_opn() and taken the default configuration
- * coming along with the package. EDMA3 resources, owned and reserved by this RM
- * instance, will be returned from this API.
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param instanceInitConfig [IN/OUT] RM Instance specific configuration
- * structure will be returned here.
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- *
- * \note This function is re-entrant.
- */
EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (
EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_InstanceInitConfig *instanceInitConfig)
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- unsigned int resMgrIdx = 0u;
- unsigned int hwId;
+ uint32_t resMgrIdx = 0U;
+ uint32_t hwId;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
{
hwId = rmObj->phyCtrllerInstId;
- for (resMgrIdx = 0u; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)
+ for (resMgrIdx = 0U; resMgrIdx < EDMA3_MAX_RM_INSTANCES; resMgrIdx++)
{
if (rmInstance == ((EDMA3_RM_Instance *)(ptrRMIArray) +
(hwId*EDMA3_MAX_RM_INSTANCES) +
return result;
}
-
-
-/**
- * \brief EDMA3 Resource Manager IOCTL
- *
- * This function provides IOCTL functionality for EDMA3 Resource Manager
- *
- * \param hEdmaResMgr [IN] Handle to the previously opened Resource
- * Manager Instance.
- * \param cmd [IN] IOCTL command to be performed
- * \param cmdArg [IN/OUT] IOCTL command argument (if any)
- * \param param [IN/OUT] Device/Cmd specific argument
- *
- * \return EDMA3_RM_SOK or EDMA3_RM Error Code
- */
EDMA3_RM_Result EDMA3_RM_Ioctl(
EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_IoctlCmd cmd,
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
- unsigned int paramInitRequired = 0xFFu;
- unsigned int regModificationRequired = 0xFFu;
- unsigned int *ret_val = NULL;
+ uint32_t paramInitRequired = 0xFFU;
+ uint32_t regModificationRequired = 0xFFU;
+ uint32_t *ret_val = NULL;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
}
- /* To remove CCS warnings */
- (void)param;
-
if (result == EDMA3_RM_SOK)
{
switch (cmd)
{
case EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION:
{
- paramInitRequired = (unsigned int)cmdArg;
+ paramInitRequired = (uint32_t)cmdArg;
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
- if ((paramInitRequired != 0u)
- && (paramInitRequired != 1u))
+ if ((paramInitRequired != 0U)
+ && (paramInitRequired != 1U))
{
result = EDMA3_RM_E_INVALID_PARAM;
}
/* Check if the parameters are OK. */
if (EDMA3_RM_SOK == result)
{
- ret_val = (unsigned int *)cmdArg;
+ ret_val = (uint32_t *)cmdArg;
/* Get the flag which is being used to do the PaRAM clearing. */
*ret_val = rmInstance->paramInitRequired;
case EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION:
{
- regModificationRequired = (unsigned int)cmdArg;
+ regModificationRequired = (uint32_t)cmdArg;
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
- if ((regModificationRequired != 0u)
- && (regModificationRequired != 1u))
+ if ((regModificationRequired != 0U)
+ && (regModificationRequired != 1U))
{
/* All other values are invalid. */
result = EDMA3_RM_E_INVALID_PARAM;
/* Check if the parameters are OK. */
if (EDMA3_RM_SOK == result)
{
- ret_val = (unsigned int *)cmdArg;
+ ret_val = (uint32_t *)cmdArg;
/**
* Get the flag which is being used to do the global
}
default:
- /* Hey dude! you passed invalid IOCTL cmd */
- result = EDMA3_RM_E_INVALID_PARAM;
+ {
+ /* Hey dude! you passed invalid IOCTL cmd */
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
}
}
}
-
-
/**
* edma3ComplHandler
* \brief Interrupt handler for successful transfer completion.
*/
static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
{
- unsigned int Cnt;
+ uint32_t Cnt;
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- volatile unsigned int pendingIrqs;
- unsigned int indexl;
- unsigned int indexh;
- unsigned int edma3Id;
+ volatile uint32_t pendingIrqs;
+ volatile uint32_t isIPR = 0;
+
+ uint32_t indexl;
+ uint32_t indexh;
+ uint32_t edma3Id;
+ uint32_t numTCCs;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
assert (NULL != rmObj);
edma3Id = rmObj->phyCtrllerInstId;
+ numTCCs = rmObj->gblCfgParams.numTccs;
ptrEdmaccRegs =
(volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs;
if (ptrEdmaccRegs != NULL)
(&ptrEdmaccRegs->SHADOW[edma3RegionId]);
}
- Cnt = 0u;
- pendingIrqs = 0u;
- indexl = 1u;
- indexh = 1u;
+ Cnt = 0U;
+ pendingIrqs = 0U;
+ indexl = 1U;
+ indexh = 1U;
- if((shadowRegs->IPR !=0 ) || (shadowRegs->IPRH !=0 ))
+ if (numTCCs > 32U)
+ {
+ isIPR = shadowRegs->IPR | shadowRegs->IPRH;
+ }
+ else
+ {
+ isIPR = shadowRegs->IPR;
+ }
+ if(isIPR)
{
/**
* Since an interrupt has found, we have to make sure that this
*/
edma3OsProtectEntry (edma3Id,
- EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
NULL);
/* Loop for EDMA3_RM_COMPL_HANDLER_RETRY_COUNT number of time,
breaks when no pending interrupt is found */
while ((Cnt < EDMA3_RM_COMPL_HANDLER_RETRY_COUNT)
- && ((indexl != 0u) || (indexh != 0u)))
+ && ((indexl != 0U) || (indexh != 0U)))
{
- indexl = 0u;
+ indexl = 0U;
pendingIrqs = shadowRegs->IPR;
/**
* Choose interrupts coming from our allocated TCCs
* and MASK remaining ones.
*/
- pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][0u]);
+ pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][0U]);
while (pendingIrqs)
{
/*Process all the pending interrupts*/
- if((pendingIrqs & 1u) == TRUE)
+ if((pendingIrqs & 1U) == TRUE)
{
/**
* If the user has not given any callback function
if(edma3IntrParams[edma3Id][indexl].tccCb != NULL)
{
/* here write to ICR to clear the corresponding IPR bits*/
- shadowRegs->ICR = (1u << indexl);
+ shadowRegs->ICR = (1U << indexl);
edma3IntrParams[edma3Id][indexl].tccCb (indexl,
EDMA3_RM_XFER_COMPLETE,
}
}
++indexl;
- pendingIrqs >>= 1u;
+ pendingIrqs >>= 1U;
}
- indexh = 0u;
- pendingIrqs = shadowRegs->IPRH;
-
- /**
- * Choose interrupts coming from our allocated TCCs
- * and MASK remaining ones.
- */
- pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][1u]);
-
- while (pendingIrqs)
- {
- /*Process all the pending interrupts*/
- if((pendingIrqs & 1u)==TRUE)
- {
- /**
- * If the user has not given any callback function
- * while requesting the TCC, its TCC specific bit
- * in the IPRH register will NOT be cleared.
- */
- if(edma3IntrParams[edma3Id][32u+indexh].tccCb!=NULL)
- {
- /* here write to ICR to clear the corresponding IPR bits*/
- shadowRegs->ICRH = (1u << indexh);
+ if(numTCCs > 32U)
+ {
+ indexh = 0U;
+ pendingIrqs = shadowRegs->IPRH;
+
+ /**
+ * Choose interrupts coming from our allocated TCCs
+ * and MASK remaining ones.
+ */
+ pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][1U]);
+
+ while (pendingIrqs)
+ {
+ /*Process all the pending interrupts*/
+ if((pendingIrqs & 1U)==TRUE)
+ {
+ /**
+ * If the user has not given any callback function
+ * while requesting the TCC, its TCC specific bit
+ * in the IPRH register will NOT be cleared.
+ */
+ if(edma3IntrParams[edma3Id][32U+indexh].tccCb!=NULL)
+ {
+ /* here write to ICR to clear the corresponding IPR bits*/
+ shadowRegs->ICRH = (1U << indexh);
- edma3IntrParams[edma3Id][32u+indexh].tccCb(32u+indexh,
- EDMA3_RM_XFER_COMPLETE,
- edma3IntrParams[edma3Id][32u+indexh].cbData);
- }
- }
- ++indexh;
- pendingIrqs >>= 1u;
- }
+ edma3IntrParams[edma3Id][32U+indexh].tccCb(32U+indexh,
+ EDMA3_RM_XFER_COMPLETE,
+ edma3IntrParams[edma3Id][32U+indexh].cbData);
+ }
+ }
+ ++indexh;
+ pendingIrqs >>= 1U;
+ }
+ }
Cnt++;
}
- indexl = (shadowRegs->IPR & allocatedTCCs[edma3Id][0u]);
- indexh = (shadowRegs->IPRH & allocatedTCCs[edma3Id][1u]);
+ indexl = (shadowRegs->IPR & allocatedTCCs[edma3Id][0U]);
+ if (numTCCs > 32U)
+ {
+ indexh = (shadowRegs->IPRH & allocatedTCCs[edma3Id][1U]);
+ }
if((indexl !=0 ) || (indexh !=0 ))
{
- shadowRegs->IEVAL=0x1u;
+ shadowRegs->IEVAL=0x1U;
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
- NULL);
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
+ 0);
}
#ifdef EDMA3_INSTRUMENTATION_ENABLED
}
-void lisrEdma3ComplHandler0(unsigned int edma3InstanceId)
+void lisrEdma3ComplHandler0(uint32_t edma3InstanceId)
{
/* Invoke Completion Handler ISR */
edma3ComplHandler(&resMgrObj[edma3InstanceId]);
*/
static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
{
- unsigned int Cnt = 0u;
- unsigned int resMgrInstIdx = 0u;
+ uint32_t Cnt = 0U;
+ uint32_t resMgrInstIdx = 0U;
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- volatile unsigned int pendingIrqs;
- unsigned int index;
- unsigned int evtqueNum;
+ volatile uint32_t pendingIrqs = 0;
+ uint32_t index;
+ uint32_t evtqueNum;
EDMA3_RM_Instance *rm_instance = NULL;
- unsigned int edma3Id;
- unsigned int num_rm_instances_opened;
+ uint32_t edma3Id;
+ uint32_t num_rm_instances_opened;
EDMA3_RM_Instance *rmInstance = NULL;
- unsigned int ownedDmaError = 0;
- unsigned int ownedDmaHError = 0;
- unsigned int ownedQdmaError = 0;
+ uint32_t ownedDmaError = 0;
+ uint32_t ownedDmaHError = 0;
+ uint32_t ownedQdmaError = 0;
+ uint32_t numTCCs;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_CCERR",
edma3Id = rmObj->phyCtrllerInstId;
ptrEdmaccRegs = (volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs;
+ numTCCs = rmObj->gblCfgParams.numTccs;
if (ptrEdmaccRegs != NULL)
{
shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)&ptrEdmaccRegs->SHADOW[edma3RegionId];
+ (edma3Id*EDMA3_MAX_RM_INSTANCES)
+ edma3RegionId);
- pendingIrqs = 0u;
- index = 1u;
+ pendingIrqs = ((ptrEdmaccRegs->EMR != 0 )
+ || (ptrEdmaccRegs->QEMR != 0)
+ || (ptrEdmaccRegs->CCERR != 0));
+ if (numTCCs > 32U)
+ {
+ pendingIrqs = pendingIrqs || (ptrEdmaccRegs->EMRH != 0 );
+ }
+ index = 1U;
- if(((ptrEdmaccRegs->EMR != 0 )
- || (ptrEdmaccRegs->EMRH != 0 ))
- || ((ptrEdmaccRegs->QEMR != 0)
- || (ptrEdmaccRegs->CCERR != 0)))
+ if(pendingIrqs)
{
edma3OsProtectEntry (edma3Id,
- EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
NULL);
/* Loop for EDMA3_RM_CCERR_HANDLER_RETRY_COUNT number of time,
breaks when no pending interrupt is found */
while ((Cnt < EDMA3_RM_CCERR_HANDLER_RETRY_COUNT)
- && (index != 0u))
+ && (index != 0U))
{
- index = 0u;
+ index = 0U;
pendingIrqs = ptrEdmaccRegs->EMR;
while (pendingIrqs)
{
/*Process all the pending interrupts*/
- if((pendingIrqs & 1u)==TRUE)
+ if((pendingIrqs & 1U)==TRUE)
{
- unsigned int mappedTcc = 0u;
+ uint32_t mappedTcc = 0U;
/**
* Using the 'index' value (basically the DMA
* TCC owned and allocated by RM.
* Write to EMCR to clear the corresponding EMR bits.
*/
- ptrEdmaccRegs->EMCR = (1u<<index);
+ ptrEdmaccRegs->EMCR = (1U<<index);
/*Clear any SER*/
- shadowRegs->SECR = (1u<<index);
+ shadowRegs->SECR = (1U<<index);
/* Call the callback function if registered earlier. */
if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
*/
#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)
/* here write to EMCR to clear the corresponding EMR bits. */
- ptrEdmaccRegs->EMCR = (1u<<index);
+ ptrEdmaccRegs->EMCR = (1U<<index);
/*Clear any SER*/
- ptrEdmaccRegs->SECR = (1u<<index);
+ ptrEdmaccRegs->SECR = (1U<<index);
#endif
}
}
++index;
- pendingIrqs >>= 1u;
+ pendingIrqs >>= 1U;
}
- index = 0u;
+ if(numTCCs > 32U)
+ {
+ index = 0U;
pendingIrqs = ptrEdmaccRegs->EMRH;
while (pendingIrqs)
{
/*Process all the pending interrupts*/
- if((pendingIrqs & 1u)==TRUE)
+ if((pendingIrqs & 1U)==TRUE)
{
- unsigned int mappedTcc = 0u;
+ uint32_t mappedTcc = 0U;
/**
* Using the 'index' value (basically the DMA
* channel), fetch the corresponding TCC
* value, mapped to this DMA channel.
*/
- mappedTcc = edma3DmaChTccMapping[edma3Id][32u+index];
+ mappedTcc = edma3DmaChTccMapping[edma3Id][32U+index];
/**
* Ensure that the mapped tcc is valid and the call
* TCC owned and allocated by RM.
* Write to EMCR to clear the corresponding EMR bits.
*/
- ptrEdmaccRegs->EMCRH = (1u<<index);
+ ptrEdmaccRegs->EMCRH = (1U<<index);
/*Clear any SERH*/
- shadowRegs->SECRH = (1u<<index);
+ shadowRegs->SECRH = (1U<<index);
/* Call the callback function if registered earlier. */
if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
* TCC NOT owned by RM.
* Write to EMCRH to clear the corresponding EMRH bits.
*/
- ptrEdmaccRegs->EMCRH = (1u<<index);
+ ptrEdmaccRegs->EMCRH = (1U<<index);
/*Clear any SERH*/
- shadowRegs->SECRH = (1u<<index);
+ shadowRegs->SECRH = (1U<<index);
#endif
}
}
++index;
- pendingIrqs >>= 1u;
+ pendingIrqs >>= 1U;
}
+ }
- index = 0u;
+ index = 0U;
pendingIrqs = ptrEdmaccRegs->QEMR;
while (pendingIrqs)
{
/*Process all the pending interrupts*/
- if((pendingIrqs & 1u)==TRUE)
+ if((pendingIrqs & 1U)==TRUE)
{
- unsigned int mappedTcc = 0u;
+ uint32_t mappedTcc = 0U;
/**
* Using the 'index' value (basically the QDMA
if (mappedTcc < EDMA3_MAX_TCC)
{
/* here write to QEMCR to clear the corresponding QEMR bits*/
- ptrEdmaccRegs->QEMCR = (1u<<index);
+ ptrEdmaccRegs->QEMCR = (1U<<index);
/*Clear any QSER*/
- shadowRegs->QSECR = (1u<<index);
+ shadowRegs->QSECR = (1U<<index);
if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
{
*/
#if (EDMA3_RM_RES_CLEAR_ERROR_STATUS_FOR_ALL_CHANNELS == TRUE)
/* here write to QEMCR to clear the corresponding QEMR bits*/
- ptrEdmaccRegs->QEMCR = (1u<<index);
+ ptrEdmaccRegs->QEMCR = (1U<<index);
/*Clear any QSER*/
- ptrEdmaccRegs->QSECR = (1u<<index);
+ ptrEdmaccRegs->QSECR = (1U<<index);
#endif
}
}
++index;
- pendingIrqs >>= 1u;
+ pendingIrqs >>= 1U;
}
- index = 0u;
+ index = 0U;
pendingIrqs = ptrEdmaccRegs->CCERR;
- if (pendingIrqs!=NULL)
+ if (pendingIrqs!=0)
{
/* Process all the pending CC error interrupts. */
/* Queue threshold error for different event queues.*/
- for (evtqueNum = 0u; evtqueNum < rmObj->gblCfgParams.numEvtQueue; evtqueNum++)
+ for (evtqueNum = 0U; evtqueNum < rmObj->gblCfgParams.numEvtQueue; evtqueNum++)
{
- if((pendingIrqs & (1u << evtqueNum)) != NULL)
+ if((pendingIrqs & ((uint32_t)1U << evtqueNum)) != 0)
{
/**
* Queue threshold error for queue 'evtqueNum' raised.
* Inform all the RM instances working on this region
* about the error by calling their global callback functions.
*/
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
/* Clear the error interrupt. */
- ptrEdmaccRegs->CCERRCLR = (1u << evtqueNum);
+ ptrEdmaccRegs->CCERRCLR = (1U << evtqueNum);
}
}
/* Transfer completion code error. */
- if ((pendingIrqs & (1 << EDMA3_CCRL_CCERR_TCCERR_SHIFT))!=NULL)
+ if ((pendingIrqs & ((uint32_t)1 << EDMA3_CCRL_CCERR_TCCERR_SHIFT))!=0)
{
/**
* Transfer completion code error raised.
* Inform all the RM instances working on this region
* about the error by calling their global callback functions.
*/
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
{
rm_instance->initParam.gblerrCbParams.gblerrCb(
EDMA3_RM_E_CC_TCC,
- NULL,
+ 0,
rm_instance->initParam.gblerrCbParams.gblerrData);
}
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
- ptrEdmaccRegs->CCERRCLR = (1<<EDMA3_CCRL_CCERR_TCCERR_SHIFT);
+ ptrEdmaccRegs->CCERRCLR = ((uint32_t)1<<EDMA3_CCRL_CCERR_TCCERR_SHIFT);
}
++index;
/* Check all the error bits. */
ownedDmaError = ptrEdmaccRegs->EMR;
- ownedDmaHError = ptrEdmaccRegs->EMRH;
+ if (numTCCs > 32U)
+ {
+ ownedDmaHError = ptrEdmaccRegs->EMRH;
+ }
ownedQdmaError = ptrEdmaccRegs->QEMR;
#else
/* Check ONLY owned error bits. */
- ownedDmaError = (ptrEdmaccRegs->EMR & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0u]);
- ownedDmaHError = (ptrEdmaccRegs->EMRH & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1u]);
- ownedQdmaError = (ptrEdmaccRegs->QEMR & rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0u]);
+ ownedDmaError = (ptrEdmaccRegs->EMR & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[0U]);
+ if (numTCCs > 32)
+ ownedDmaHError = (ptrEdmaccRegs->EMRH & rmInstance->initParam.rmInstInitConfig->ownDmaChannels[1U]);
+ ownedQdmaError = (ptrEdmaccRegs->QEMR & rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[0U]);
#endif
if (((ownedDmaError != 0 ) || (ownedDmaHError != 0 ))
|| ((ownedQdmaError != 0) || (ptrEdmaccRegs->CCERR != 0)))
{
- ptrEdmaccRegs->EEVAL=0x1u;
+ ptrEdmaccRegs->EEVAL=0x1U;
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
- NULL);
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
+ 0);
}
}
#endif /* EDMA3_INSTRUMENTATION_ENABLED */
}
-void lisrEdma3CCErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3CCErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke CC Error Handler ISR */
edma3CCErrHandler(&resMgrObj[edma3InstanceId]);
*
* \return None.
*/
-static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
+static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, uint32_t tcNum)
{
volatile EDMA3_TCRL_Regs *tcRegs = NULL;
- unsigned int tcMemErrRdWr = 0u;
- unsigned int resMgrInstIdx = 0u;
+ uint32_t tcMemErrRdWr = 0U;
+ uint32_t resMgrInstIdx = 0U;
EDMA3_RM_Instance *rm_instance = NULL;
- unsigned int edma3Id;
- unsigned int num_rm_instances_opened;
+ uint32_t edma3Id;
+ uint32_t num_rm_instances_opened;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_TCERR",
@@ -6313,10 +5863,10 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
if(tcRegs->ERRSTAT != 0)
{
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
&tcNum);
- if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT))!=NULL)
+ if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT))!= 0)
{
/* Bus error event. */
/**
@@ -6324,15 +5874,15 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
* address. Error information can be read from the error
* details register (ERRDET).
*/
- tcMemErrRdWr = tcRegs->ERRDET & (EDMA3_TCRL_ERRDET_STAT_MASK);
- if ((tcMemErrRdWr > 0u) && (tcMemErrRdWr < 8u))
+ tcMemErrRdWr = tcRegs->ERRDET & ((uint32_t)EDMA3_TCRL_ERRDET_STAT_MASK);
+ if ((tcMemErrRdWr > 0U) && (tcMemErrRdWr < 8U))
{
/**
* Inform all the RM instances working on this region
* about the error by calling their global callback functions.
*/
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
@@ -6351,20 +5901,20 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
}
else
{
- if ((tcMemErrRdWr >= 8u) && (tcMemErrRdWr <= 0xFu))
+ if ((tcMemErrRdWr >= 8U) && (tcMemErrRdWr <= 0xFU))
{
/**
* Inform all the RM instances working on this region
* about the error by calling their global callback functions.
*/
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
@@ -6383,20 +5933,20 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
}
}
- tcRegs->ERRCLR = (1<<EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT);
+ tcRegs->ERRCLR = ((uint32_t)1<<EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT);
}
else
{
/* Transfer request (TR) error event. */
- if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_TRERR_SHIFT))!=NULL)
+ if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_TRERR_SHIFT))!= 0)
{
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
@@ -6415,18 +5965,18 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
- tcRegs->ERRCLR = (1<<EDMA3_TCRL_ERRSTAT_TRERR_SHIFT);
+ tcRegs->ERRCLR = ((uint32_t)1<<EDMA3_TCRL_ERRSTAT_TRERR_SHIFT);
}
else
{
- if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT))!=NULL)
+ if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT))!= 0)
{
- num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
- for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
+ resMgrInstIdx = 0U;
+ for (num_rm_instances_opened = resMgrObj[edma3Id].numOpens; num_rm_instances_opened != 0; num_rm_instances_opened--)
{
/* Check whether the RM instance opened working on this region */
rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
@@ -6445,17 +5995,17 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
}
}
+ ++resMgrInstIdx;
/* Check next opened instance */
- num_rm_instances_opened--;
}
- tcRegs->ERRCLR = (1<<EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT);
+ tcRegs->ERRCLR = ((uint32_t)1<<EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT);
}
}
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
tcNum);
}
}
@@ -6475,10 +6025,10 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
* ======== lisrEdma3TC0ErrHandler0 ========
* EDMA3 instance 0 TC0 Error Interrupt Service Routine
*/
-void lisrEdma3TC0ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC0*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 0u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)0U);
}
* ======== lisrEdma3TC1ErrHandler0 ========
* EDMA3 instance 0 TC1 Error Interrupt Service Routine
*/
-void lisrEdma3TC1ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC1*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 1u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)1U);
}
/*
* ======== lisrEdma3TC2ErrHandler0 ========
* EDMA3 instance 0 TC2 Error Interrupt Service Routine
*/
-void lisrEdma3TC2ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC2*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 2u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)2U);
}
/*
* ======== lisrEdma3TC3ErrHandler0 ========
* EDMA3 instance 0 TC3 Error Interrupt Service Routine
*/
-void lisrEdma3TC3ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC3*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 3u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)3U);
}
/*
* ======== lisrEdma3TC4ErrHandler0 ========
* EDMA3 instance 0 TC4 Error Interrupt Service Routine
*/
-void lisrEdma3TC4ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC4*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 4u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)4U);
}
* ======== lisrEdma3TC5ErrHandler0 ========
* EDMA3 instance 0 TC5 Error Interrupt Service Routine
*/
-void lisrEdma3TC5ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC5*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 5u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)5U);
}
/*
* EDMA3 instance 0 TC6 Error Interrupt Service Routine
*/
/* ARGSUSED */
-void lisrEdma3TC6ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC6*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 6u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)6U);
}
/*
* ======== lisrEdma3TC7ErrHandler0 ========
* EDMA3 instance 0 TC7 Error Interrupt Service Routine
*/
-void lisrEdma3TC7ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC7*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 7u);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)7U);
}
/* Resource Manager Internal functions - Start */
/** Initialization of the Global region registers of the EDMA3 Controller */
-static void edma3GlobalRegionInit (unsigned int phyCtrllerInstId)
+static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId, uint32_t numDmaChannels)
{
- unsigned int evtQNum = 0u;
+ uint32_t evtQNum = 0U;
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
assert (phyCtrllerInstId < EDMA3_MAX_EDMA3_INSTANCES);
if (ptrEdmaccRegs != NULL)
{
ptrEdmaccRegs->EMCR = EDMA3_RM_SET_ALL_BITS;
- ptrEdmaccRegs->EMCRH = EDMA3_RM_SET_ALL_BITS;
+ if ( numDmaChannels > 32U)
+ {
+ /* Clear the EMCRH only if available channels are more than 32 */
+ ptrEdmaccRegs->EMCRH = EDMA3_RM_SET_ALL_BITS;
+ }
ptrEdmaccRegs->QEMCR = EDMA3_RM_SET_ALL_BITS;
/*
}
/* Clear CCERR register */
- ptrEdmaccRegs ->CCERRCLR = 0xFFFFu;
+ ptrEdmaccRegs ->CCERRCLR = 0xFFFFU;
}
return;
/** Initialization of the Shadow region registers of the EDMA3 Controller */
static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance)
{
- unsigned int intState = 0u;
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *ptrEdmaShadowRegs = NULL;
- unsigned int phyCtrllerInstId;
- unsigned int regionId;
+ uint32_t phyCtrllerInstId;
+ uint32_t regionId;
const EDMA3_RM_InstanceInitConfig *rmInstInitConfig = pRMInstance->initParam.rmInstInitConfig;
assert (pRMInstance != NULL);
ptrEdmaShadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)
(&ptrEdmaccRegs->SHADOW[regionId]);
- ptrEdmaShadowRegs->ECR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->ECRH = (rmInstInitConfig->ownDmaChannels[1u]
- | rmInstInitConfig->ownTccs[1u]);
- ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->SECR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->SECRH = (rmInstInitConfig->ownDmaChannels[1u]
- | rmInstInitConfig->ownTccs[1u]);
- ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->EECRH = (rmInstInitConfig->ownDmaChannels[1u]
- | rmInstInitConfig->ownTccs[1u]);
-
- ptrEdmaShadowRegs->QEECR = rmInstInitConfig->ownQdmaChannels[0u];
-
- ptrEdmaShadowRegs->IECR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->IECRH = (rmInstInitConfig->ownDmaChannels[1u]
- | rmInstInitConfig->ownTccs[1u]);
- ptrEdmaShadowRegs->ICR = (rmInstInitConfig->ownDmaChannels[0u]
- | rmInstInitConfig->ownTccs[0u]);
- ptrEdmaShadowRegs->ICRH = (rmInstInitConfig->ownDmaChannels[1u]
- | rmInstInitConfig->ownTccs[1u]);
-
- ptrEdmaShadowRegs->QSECR = rmInstInitConfig->ownQdmaChannels[0u];
+ ptrEdmaShadowRegs->ECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->ECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+ ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->SECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->SECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+ ptrEdmaShadowRegs->EECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->EECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+
+ ptrEdmaShadowRegs->QEECR = rmInstInitConfig->ownQdmaChannels[0U];
+
+ ptrEdmaShadowRegs->IECR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->IECRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+ ptrEdmaShadowRegs->ICR = (rmInstInitConfig->ownDmaChannels[0U]
+ | rmInstInitConfig->ownTccs[0U]);
+ ptrEdmaShadowRegs->ICRH = (rmInstInitConfig->ownDmaChannels[1U]
+ | rmInstInitConfig->ownTccs[1U]);
+
+ ptrEdmaShadowRegs->QSECR = rmInstInitConfig->ownQdmaChannels[0U];
/*
* Set all EDMA3 Resource<->Region mapping parameters
*/
/* 1. Dma Channel (and TCC) <-> Region */
- edma3OsProtectEntry (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
- &intState);
- ptrEdmaccRegs->DRA[regionId].DRAE = 0u;
- ptrEdmaccRegs->DRA[regionId].DRAEH = 0u;
- edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
- intState);
+ ptrEdmaccRegs->DRA[regionId].DRAE = 0U;
+ ptrEdmaccRegs->DRA[regionId].DRAEH = 0U;
/* 2. Qdma Channel <-> Region */
- edma3OsProtectEntry (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
- &intState);
- ptrEdmaccRegs->QRAE[regionId] = 0u;
- edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
- intState);
+ ptrEdmaccRegs->QRAE[regionId] = 0U;
}
}
/** Local MemZero function */
-void edma3MemZero(void *dst, unsigned int len)
+void edma3MemZero(void *dst, uint32_t len)
{
- unsigned int i = 0u;
- unsigned int *ds = NULL;
+ uint32_t i = 0U;
+ uint32_t *ds = NULL;
assert (dst != NULL);
- ds = (unsigned int *)dst;
+ ds = (uint32_t *)dst;
- for (i = 0 ; i < len/4 ; i++)
+ for (i = 0U ; i < (len/4U) ; i++)
{
*ds = 0x0;
ds++;
/* Local MemCopy function */
-void edma3MemCpy(void *dst, const void *src, unsigned int len)
+void edma3MemCpy(void *dst, const void *src, uint32_t len)
{
- unsigned int i=0u;
- const unsigned int *sr;
- unsigned int *ds;
+ uint32_t i=0U;
+ const uint32_t *sr;
+ uint32_t *ds;
- assert ((src != NULL) && (dst != NULL) && ((len)%4 == 0));
+ assert ((src != NULL) && (dst != NULL) && ((len%4) == 0));
- sr = (const unsigned int *)src;
- ds = (unsigned int *)dst;
+ sr = (const uint32_t *)src;
+ ds = (uint32_t *)dst;
- for (i = 0 ; i < len/4 ; i++)
+ for (i = 0U ; i < (len/4U) ; i++)
{
*ds = *sr;
ds++;
/* Local MemCopy function to copy Param Set ONLY */
-void edma3ParamCpy(void *dst, const void *src)
+void edma3ParamCpy(volatile void *dst, const volatile void *src)
{
- unsigned int i = 0u;
- const unsigned int *sr;
- unsigned int *ds;
+ uint32_t i = 0U;
+ const volatile uint32_t *sr;
+ volatile uint32_t *ds;
assert ((src != NULL) && (dst != NULL));
- sr = (const unsigned int *)src;
- ds = (unsigned int *)dst;
+ sr = (const volatile uint32_t *)src;
+ ds = (volatile uint32_t *)dst;
- for (i = 0; i < 8; i++)
+ for (i = 0U; i < 8U; i++)
{
*ds = *sr;
ds++;
* Finds a particular bit ('0' or '1') in the particular word from 'start'.
* If found, returns the position, else return -1.
*/
-static int findBitInWord (int source, unsigned int start, unsigned short bit)
+static int32_t findBitInWord (int32_t source, uint32_t start, uint16_t bit)
{
- unsigned int position = start;
- unsigned short found = 0;
- unsigned int iterations_left = 0;
+ uint32_t position = start;
+ uint16_t found = 0;
+ uint32_t iterations_left = 0;
+ uint32_t sourceTmp=0;
switch (bit)
{
- case 1:
+ case 1U:
{
- source >>= (start%32u);
+ sourceTmp = (uint32_t)source >> (start%32U);
+ source = (int32_t)sourceTmp;
- while ((found==0u) && (source!=0))
+ while ((found==0U) && (source!=0))
{
- if ((source & 0x1) == 0x1)
+ if (((uint32_t)source & 0x1U) == 0x1U)
{
/* 1 */
found++;
else
{
/* 0 */
- source >>= 1;
+ sourceTmp = (uint32_t)source >> 1;
+ source = (int32_t)sourceTmp;
position++;
}
}
@@ -6791,15 +6335,17 @@ static int findBitInWord (int source, unsigned int start, unsigned short bit)
case 0:
{
- source >>= (start%32u);
- iterations_left = 32u - (start%32u);
+ sourceTmp = (uint32_t)source >> (start%32U);
+ source = (int32_t)sourceTmp;
+ iterations_left = (uint32_t)32U - (start%32U);
- while ((found==0u) && (iterations_left>0u))
+ while ((found==0U) && (iterations_left>0U))
{
- if ((source & 0x1) == 0x1)
+ if (((uint32_t)source & 0x1U) == 0x1U)
{
/* 1 */
- source >>= 1;
+ sourceTmp = (uint32_t)source >> 1;
+ source = (int32_t)sourceTmp;
position++;
iterations_left--;
}
break;
}
- return (found ? (int)position : -1);
+ return (found ? (int32_t)position : -1);
}
@@ -6824,17 +6370,17 @@ static int findBitInWord (int source, unsigned int start, unsigned short bit)
* Finds a particular bit ('0' or '1') in the specified resources' array
* from 'start' to 'end'. If found, returns the position, else return -1.
*/
-static int findBit (EDMA3_RM_ResType resType,
- unsigned int start,
- unsigned int end,
- unsigned short bit)
+static int32_t findBit (EDMA3_RM_ResType resType,
+ uint32_t start,
+ uint32_t end,
+ uint16_t bit)
{
- int position = -1;
- unsigned int start_index = start / 32u;
- unsigned int end_index = end / 32u;
- int i;
- unsigned int *resPtr = 0x0;
- int ret = -1;
+ int32_t position = -1;
+ uint32_t start_index = start / 32U;
+ uint32_t end_index = end / 32U;
+ int32_t i;
+ uint32_t *resPtr = 0x0;
+ int32_t ret = -1;
EDMA3_RM_Result result = EDMA3_RM_SOK;
assert (start <= end);
{
switch (bit)
{
- case 1:
+ case 1U:
{
/* Find '1' in first word. */
- position = findBitInWord (resPtr[start_index], start, 1u);
+ position = findBitInWord (resPtr[start_index], start, (uint16_t)1U);
if (position != -1)
{
else
{
/* '1' NOT found, look into other words. */
- for (i = (int)(start_index + 1u); i <= (int)(end_index - 1u); i++)
+ for (i = ((int32_t)start_index + (int32_t)1U); i <= ((int32_t)end_index - (int32_t)1U); i++)
{
- position = findBitInWord (resPtr[i], 0u, 1u);
+ position = findBitInWord (resPtr[i], (uint32_t)0U, (uint16_t)1U);
if (position != -1)
{
/* '1' Found... */
if (ret == -1)
{
/* Still not found, look in the last word. */
- position = findBitInWord(resPtr[end_index], 0u, 1u);
+ position = findBitInWord(resPtr[end_index], (uint32_t)0U, (uint16_t)1U);
if (position != -1)
{
/* Finally got it. */
- ret = (position + (end_index*32u));
+ ret = (position + ((int32_t)end_index*(int32_t)32U));
}
else
{
}
break;
- case 0:
+ case 0U:
{
/* Find '0' in first word. */
- position = findBitInWord(resPtr[start_index], start, 0u);
+ position = findBitInWord(resPtr[start_index], start, (uint16_t)0U);
if (position != -1)
{
ret = position;
else
{
/* '0' NOT found, look into other words. */
- for (i = (start_index + 1u); i <= (end_index - 1u); i++)
+ for (i = ((int32_t)start_index + (int32_t)1U); i <= ((int32_t)end_index - (int32_t)1U); i++)
{
- position = findBitInWord(resPtr[i], 0u, 0u);
+ position = findBitInWord(resPtr[i], (uint32_t)0U, (uint16_t)0U);
if (position != -1)
{
/* '0' found... */
/* First check whether we have found '0' or not. */
if (ret == -1)
{
- position = findBitInWord(resPtr[end_index], 0u, 0u);
+ position = findBitInWord(resPtr[end_index], (uint32_t)0U, (uint16_t)0U);
if (position != -1)
{
/* Finally got it. */
- ret = (position + (end_index*32u));
+ ret = (position + ((int32_t)end_index*(int32_t)32U));
}
else
{
- return ((ret >= start) ? ret : -1);
-}
+ return ((ret >= (int32_t)start) ? ret : -1);
+ }
* of first available resource in 'positionRes'. Else returns error.
*/
static EDMA3_RM_Result allocAnyContigRes(EDMA3_RM_ResType resType,
- unsigned int numResources,
- unsigned int *positionRes)
+ uint32_t numResources,
+ uint32_t *positionRes)
{
- unsigned short found = 0u;
- int first_one, next_zero;
- unsigned int num_available;
- int ret = -1;
- unsigned int start = 0;
- unsigned int end;
+ uint16_t found = 0U;
+ int32_t first_one, next_zero;
+ uint32_t num_available;
+ int32_t ret = -1;
+ uint32_t start = 0;
+ uint32_t end;
EDMA3_RM_Result result = EDMA3_RM_SOK;
assert (positionRes != NULL);
switch (resType)
{
case EDMA3_RM_RES_DMA_CHANNEL:
- end = EDMA3_MAX_DMA_CH - 1u;
+ end = EDMA3_MAX_DMA_CH - 1U;
break;
case EDMA3_RM_RES_QDMA_CHANNEL:
- end = EDMA3_MAX_QDMA_CH - 1u;
+ end = EDMA3_MAX_QDMA_CH - 1U;
break;
case EDMA3_RM_RES_TCC:
- end = EDMA3_MAX_TCC - 1u;
+ end = EDMA3_MAX_TCC - 1U;
break;
case EDMA3_RM_RES_PARAM_SET:
- end = edma3NumPaRAMSets - 1u;
+ end = edma3NumPaRAMSets - 1U;
break;
default:
* Step d) If result < N, do the whole process again untill you
* reach end. Else you have found enough resources, return success.
*/
- while((found == 0) && (((end-start)+1u) >= numResources))
+ while((found == 0) && (start<=end) && (((end-start)+1U) >= numResources))
{
/* Find first '1' starting from 'start' till 'end'. */
- first_one = findBit (resType, start, end, 1u);
+ first_one = findBit (resType, start, end, (uint16_t)1U);
if (first_one != -1)
{
/* Got first 1, search for first '0' now. */
- next_zero = findBit (resType, first_one+1, end, 0u);
+ next_zero = findBit (resType, (uint32_t)first_one+(uint32_t)1, end, (uint16_t)0U);
if (next_zero == -1)
{
/* Unable to find next zero, all 1' are there */
- next_zero = end + 1u;
+ next_zero = (int32_t)end + (int32_t)1U;
}
/* check no of resources available */
- num_available = next_zero - first_one;
+ num_available = (uint32_t)next_zero - (uint32_t)first_one;
if (num_available >= numResources)
{
/* hurrah..., we have found enough resources. */
- found = 1u;
+ found = 1U;
ret = first_one;
}
else
{
/* Not enough resources, try again */
- start = next_zero + 1;
+ start = (uint32_t)next_zero + (uint32_t)1;
}
}
else
if (result == EDMA3_RM_SOK)
{
- if (found == 1u)
+ if (found == 1U)
{
/* required resources found, retrun the first available res id. */
- *positionRes = (unsigned int)ret;
+ *positionRes = (uint32_t)ret;
}
else
{
*/
static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,
const EDMA3_RM_ResDesc *firstResIdObj,
- unsigned int numResources)
+ uint32_t numResources)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- unsigned int avlblIdx = 0u;
- unsigned int firstResId=0u;
- unsigned int lastResId=0u;
- unsigned int edma3Id;
+ uint32_t avlblIdx = 0U;
+ uint32_t firstResId=0U;
+ uint32_t lastResId=0U;
+ uint32_t edma3Id;
assert ((rmInstance != NULL) && (firstResIdObj != NULL));
case EDMA3_RM_RES_DMA_CHANNEL:
{
firstResId = firstResIdObj->resId;
- lastResId = firstResId + (numResources - 1u);
+ lastResId = firstResId + (numResources - 1U);
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblDmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblDmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* Enable the DMA channel in the DRAE/DRAEH registers also.
*/
- if (avlblIdx < 32u)
+ if (avlblIdx < 32U)
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << avlblIdx);
+ |= ((uint32_t)0x1U << avlblIdx);
}
else
{
gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (avlblIdx - 32u));
+ |= ((uint32_t)0x1U << (avlblIdx - 32U));
}
}
}
case EDMA3_RM_RES_QDMA_CHANNEL:
{
firstResId = firstResIdObj->resId;
- lastResId = firstResId + (numResources - 1u);
+ lastResId = firstResId + (numResources - 1U);
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblQdmaChannels[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* Enable the QDMA channel in the QRAE register also.
*/
gblRegs->QRAE[rmInstance->initParam.regionId]
- |= (0x1u << avlblIdx);
+ |= ((uint32_t)0x1U << avlblIdx);
}
}
break;
case EDMA3_RM_RES_TCC:
{
firstResId = firstResIdObj->resId;
- lastResId = firstResId + (numResources - 1u);
+ lastResId = firstResId + (numResources - 1U);
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblTccs[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblTccs[avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* If the region id coming from this
*/
if (edma3RegionId == rmInstance->initParam.regionId)
{
- if (avlblIdx < 32u)
+ if (avlblIdx < 32U)
{
- allocatedTCCs[edma3Id][0u] |= (0x1u << avlblIdx);
+ allocatedTCCs[edma3Id][0U] |= ((uint32_t)0x1U << avlblIdx);
}
else
{
- allocatedTCCs[edma3Id][1u] |= (0x1u << (avlblIdx - 32u));
+ allocatedTCCs[edma3Id][1U] |= ((uint32_t)0x1U << (avlblIdx - 32U));
}
}
}
case EDMA3_RM_RES_PARAM_SET:
{
firstResId = firstResIdObj->resId;
- lastResId = firstResId + (numResources - 1u);
+ lastResId = firstResId + (numResources - 1U);
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblPaRAMSets [avlblIdx/32U] &= (uint32_t)(~((uint32_t)1U << (avlblIdx%32U)));
/**
* Also, make the actual PARAM Set NULL, checking the flag
return result;
}
+
+EDMA3_RM_Result EDMA3_RM_initXbarEventMap (EDMA3_RM_Handle hEdma,
+ const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig,
+ EDMA3_RM_mapXbarEvtToChan mapXbarEvtFunc,
+ EDMA3_RM_xbarConfigScr configXbarScr)
+ {
+ EDMA3_RM_Result result = EDMA3_DRV_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdma;
+
+ if (mapXbarEvtFunc != NULL)
+ {
+ rmInstance->mapXbarToChan = mapXbarEvtFunc;
+ }
+ if (configXbarScr != NULL)
+ {
+ rmInstance->configScrMapXbarToEvt = configXbarScr;
+ }
+ if (edmaGblXbarConfig != NULL)
+ {
+ edma3MemCpy((void *)(&rmInstance->rmXbarToEvtMapConfig),
+ (const void *)(edmaGblXbarConfig),
+ sizeof (EDMA3_RM_GblXbarToChanConfigParams));
+ }
+ }
+
+ return (result);
+ }
+
/* Resource Manager Internal functions - End */
/* End of File */