Misra C Fixes
authorSunil MS <x0190988@ti.com>
Tue, 26 Aug 2014 07:22:32 +0000 (12:52 +0530)
committerSunil MS <x0190988@ti.com>
Thu, 9 Oct 2014 14:11:24 +0000 (19:41 +0530)
Misra C rules 8.12,10.1,10.3,10.6,14.9 have been fixed.
Signed-off-by: Sunil MS <x0190988@ti.com>
Change-Id: I3193f355e0051f2d92896b48affb5faf6b5ced2d

packages/ti/sdo/edma3/drv/edma3_drv.h
packages/ti/sdo/edma3/drv/src/edma3.h
packages/ti/sdo/edma3/drv/src/edma3_drv_adv.c
packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c

index 9b58113c0403857ff3708d980326a40b7a147b68..d9b137bb8a6df76347dbc6a369941faa338c3261 100755 (executable)
@@ -102,7 +102,7 @@ extern "C" {
   * format:
   *  0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD) 
   */
-#define EDMA3_LLD_DRV_VERSION_ID                   (0x020B0E13)
+#define EDMA3_LLD_DRV_VERSION_ID                   (0x020B0E13U)
 
 /**
  * @brief   This is the version string which describes the EDMA3 LLD along with the
index 4bcf4c0db0f8536d2e1b67b03dc2f9872de9503c..c2339c7958c91114411e5738009a63e99e7e4188 100755 (executable)
@@ -109,25 +109,25 @@ extern "C" {
 /** OPT-SAM bit Get */
 #define EDMA3_DRV_OPT_SAM_GET_MASK(mode)            ((mode)&1U)
 /** OPT-DAM bit Get */
-#define EDMA3_DRV_OPT_DAM_GET_MASK(mode)            (((mode)&(1U<<1U))>>1U)
+#define EDMA3_DRV_OPT_DAM_GET_MASK(mode)            (((mode)&((uint32_t)1U<<1U))>>1U)
 /** OPT-SYNCDIM bit Get */
-#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)    (((synctype)&(1U<<2U))>>2U)
+#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)    (((synctype)&((uint32_t)1U<<2U))>>2U)
 /** OPT-STATIC bit Get */
-#define EDMA3_DRV_OPT_STATIC_GET_MASK(en)           (((en)&(1U<<3U))>>3U)
+#define EDMA3_DRV_OPT_STATIC_GET_MASK(en)           (((en)&((uint32_t)1U<<3U))>>3U)
 /** OPT-FWID bitfield Get */
-#define EDMA3_DRV_OPT_FWID_GET_MASK(width)          (((width)&(0x7U<<8U))>>8U)
+#define EDMA3_DRV_OPT_FWID_GET_MASK(width)          (((width)&((uint32_t)0x7U<<8U))>>8U)
 /** OPT-TCCMODE bit Get */
-#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)       (((early)&(1U<<11U))>>11U)
+#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)       (((early)&((uint32_t)1U<<11U))>>11U)
 /** OPT-TCC bitfield Get */
 #define EDMA3_DRV_OPT_TCC_GET_MASK(tcc)             (((tcc)&((uint32_t)0x3fU<<12U))>>12U)
 /** OPT-TCINTEN bit Get */
-#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)     (((tcinten)&(1U<<20U))>>20U)
+#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)     (((tcinten)&((uint32_t)1U<<20U))>>20U)
 /** OPT-ITCINTEN bit Get */
-#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)   (((itcinten)&(1U<<21U))>>21U)
+#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)   (((itcinten)&((uint32_t)1U<<21U))>>21U)
 /** OPT-TCCHEN bit Get */
-#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)       (((tcchen)&(1U<<22U))>>22U)
+#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)       (((tcchen)&((uint32_t)1U<<22U))>>22U)
 /** OPT-ITCCHEN bit Get */
-#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)     (((itcchen)&(1U<<23U))>>23U)
+#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)     (((itcchen)&((uint32_t)1U<<23U))>>23U)
 
 /** DMAQNUM bits Clear */
 #define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum)           (~((uint32_t)0x7U<<(((chNum)%8U)*4U)))
index 8b3ef70029b867cd001c7885b267f4625bbc2993..258758968c498802f5942193fb2b3a579347a575 100755 (executable)
@@ -106,7 +106,7 @@ extern EDMA3_RM_Instance *ptrRMIArray;
 /** Local MemZero function */
 extern void edma3MemZero(void *dst, uint32_t len);
 /** Local MemCpy function to copy PaRAM Set ONLY */
-extern void edma3ParamCpy(void *dst, const void *src);
+extern void edma3ParamCpy(volatile void *dst, const volatile void *src);
 
 /**
  * \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller.
@@ -140,17 +140,17 @@ extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGI
 extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
 
 /** Max of DMA Channels */
-extern uint32_t edma3_dma_ch_max_val[];
+extern uint32_t edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
 /** Min of Link Channels */
-extern uint32_t edma3_link_ch_min_val[];
+extern uint32_t edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
 /** Max of Link Channels */
-extern uint32_t edma3_link_ch_max_val[];
+extern uint32_t edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
 /** Min of QDMA Channels */
-extern uint32_t edma3_qdma_ch_min_val[];
+extern uint32_t edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
 /** Max of QDMA Channels */
-extern uint32_t edma3_qdma_ch_max_val[];
+extern uint32_t edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
 /** Max of Logical Channels */
-extern uint32_t edma3_log_ch_max_val[];
+extern uint32_t edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
 
 
 EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma,
@@ -233,7 +233,7 @@ EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma,
                             EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
         linkBcntReld &= 0xFFFF0000U;
         /* Update the Link field with lch2 PaRAM set */
-        linkBcntReld |= (0xFFFFU & (uint32_t)(&(globalRegs->PARAMENTRY [paRAM2Id].OPT)));
+        linkBcntReld |= ((uint32_t)0xFFFFU & (uint32_t)(&(globalRegs->PARAMENTRY [paRAM2Id].OPT)));
 
         /* Store it back */
         *((&globalRegs->PARAMENTRY[paRAM1Id].OPT)
@@ -705,7 +705,7 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma,
 
     if (result == EDMA3_DRV_SOK)
         {
-               edma3ParamCpy ((void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)),
+               edma3ParamCpy ((volatile void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)),
             (const void *)newPaRAM);
         }
 
@@ -783,7 +783,7 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
     if (result == EDMA3_DRV_SOK)
         {
                edma3ParamCpy ((void *)currPaRAM,
-                                       (const void *)(&(globalRegs->PARAMENTRY [paRAMId].OPT)));
+                                       (const volatile void *)(&(globalRegs->PARAMENTRY [paRAMId].OPT)));
         }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
@@ -1348,21 +1348,21 @@ EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,
             if (result == EDMA3_DRV_SOK)
                 {
                 edma3OsProtectEntry (drvObject->phyCtrllerInstId,
-                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                                        &intState);
 
                 /* Set TC Priority among system-wide bus-masters and Queue Watermark Level */
                 evtQNum = 0;
                 while (evtQNum < drvObject->gblCfgParams.numEvtQueue)
                     {
-                    globalRegs->QUEPRI = globalRegs->QUEPRI & (uint32_t)EDMA3_RM_QUEPRI_CLR_MASK(evtQNum);
+                    globalRegs->QUEPRI = globalRegs->QUEPRI &  EDMA3_RM_QUEPRI_CLR_MASK(evtQNum);
                     globalRegs->QUEPRI |= EDMA3_RM_QUEPRI_SET_MASK(evtQNum, evtQPriObj->evtQPri[evtQNum]);
 
                     evtQNum++;
                     }
 
                 edma3OsProtectExit (drvObject->phyCtrllerInstId,
-                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                                        intState);
                 }
             }
@@ -1442,7 +1442,7 @@ EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ(EDMA3_DRV_Handle hEdma,
             {
             /* DMA channel */
             edma3OsProtectEntry (edma3Id,
-                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                               (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                &intState);
 
             globalRegs->DMAQNUM[channelId >> 3U] &=
@@ -1451,7 +1451,7 @@ EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ(EDMA3_DRV_Handle hEdma,
                                 EDMA3_DRV_DMAQNUM_SET_MASK(channelId, eventQ);
 
             edma3OsProtectExit(edma3Id,
-                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                               (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                                intState);
             }
         else
@@ -1461,7 +1461,7 @@ EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ(EDMA3_DRV_Handle hEdma,
                 {
                 /* QDMA channel */
                 edma3OsProtectEntry (edma3Id,
-                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                       (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                        &intState);
 
                 globalRegs->QDMAQNUM &=
@@ -1470,7 +1470,7 @@ EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ(EDMA3_DRV_Handle hEdma,
                                        EDMA3_DRV_QDMAQNUM_SET_MASK(channelId-edma3_qdma_ch_min_val[edma3Id], eventQ);
 
                 edma3OsProtectExit(edma3Id,
-                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                                        intState);
                 }
             else
@@ -1621,7 +1621,7 @@ EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
                     {
                                        /* Semaphore taken successfully, modify the registers. */
                     edma3OsProtectEntry (drvObject->phyCtrllerInstId,
-                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                                        &intState);
                     /* Global interrupts disabled, modify the registers. */
                     regPhyAddr = (uint32_t)drvObject->gblCfgParams.globalRegs + regOffset;
@@ -1629,7 +1629,7 @@ EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
                     *(uint32_t *)regPhyAddr = newRegValue;
 
                     edma3OsProtectExit (drvObject->phyCtrllerInstId,
-                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                                        intState);
                     /* Return the semaphore back */
                     result = edma3OsSemGive(drvInst->drvSemHandle);
@@ -1767,7 +1767,7 @@ EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
                         tccBitMask = 1U << tccNo;
 
                         /* Check the status of the IPR[tccNo] bit. */
-                        while (FALSE == (shadowRegs->IPR & tccBitMask))
+                        while ((uint32_t)FALSE == (shadowRegs->IPR & tccBitMask))
                             {
                             /* Transfer not yet completed, bit not SET */
                             }
@@ -1783,7 +1783,7 @@ EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
                         tccBitMask = 1U << (tccNo - 32U);
 
                         /* Check the status of the IPRH[tccNo-32] bit. */
-                        while (FALSE == (shadowRegs->IPRH & tccBitMask))
+                        while ((uint32_t)FALSE == (shadowRegs->IPRH & tccBitMask))
                             {
                             /* Transfer not yet completed, bit not SET */
                             }
index 0bfbef571e334bbebad1094ce4f5ed17be194b82..519880c31c90f3c895eb0f98eba96da97f6fc391 100755 (executable)
@@ -147,17 +147,17 @@ extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGI
 extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
 
 /** Max of DMA Channels */
-extern uint32_t edma3_dma_ch_max_val[];
+extern uint32_t edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
 /** Min of Link Channels */
-extern uint32_t edma3_link_ch_min_val[];
+extern uint32_t edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
 /** Max of Link Channels */
-extern uint32_t edma3_link_ch_max_val[];
+extern uint32_t edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
 /** Min of QDMA Channels */
-extern uint32_t edma3_qdma_ch_min_val[];
+extern uint32_t edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
 /** Max of QDMA Channels */
-extern uint32_t edma3_qdma_ch_max_val[];
+extern uint32_t edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
 /** Max of Logical Channels */
-extern uint32_t edma3_log_ch_max_val[];
+extern uint32_t edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
 
 /* Local functions prototypes */
 /*---------------------------------------------------------------------------*/
@@ -391,7 +391,7 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
                     *pLCh = resObj.resId;
 
                     mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];
-                    if (mappedPaRAMId != EDMA3_DRV_CH_NO_PARAM_MAP)
+                    if (mappedPaRAMId != (int32_t)EDMA3_DRV_CH_NO_PARAM_MAP)
                         {
                         paRAMId = mappedPaRAMId;
                         }
@@ -497,8 +497,8 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
                /* PaRAM allocation failed, free the previously allocated DMA/QDMA
                 * channel, if required
                 */
-               if ((chType == EDMA3_DRV_CHANNEL_TYPE_DMA
-                       || chType == EDMA3_DRV_CHANNEL_TYPE_QDMA) &&
+               if (((chType == EDMA3_DRV_CHANNEL_TYPE_DMA)
+                       || (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)) &&
                        (TRUE == freeDmaQdmaChannel))
                        {
                EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
@@ -507,7 +507,7 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
 
        /* Step 3: Allocate TCC only for DMA/QDMA channels */
        if ((EDMA3_DRV_SOK == result) &&
-               (chType == EDMA3_DRV_CHANNEL_TYPE_DMA || chType == EDMA3_DRV_CHANNEL_TYPE_QDMA))
+               ((chType == EDMA3_DRV_CHANNEL_TYPE_DMA) || (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)))
         {
         resObj.type = EDMA3_RM_RES_TCC;
         resObj.resId = mappedTcc;
@@ -541,13 +541,13 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
                                                {
 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
                                                uint32_t intState = 0;
-                        edma3OsProtectEntry(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
+                        edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                                                        &intState);
                         /* Step 5: Associate DMA Channel to Event Queue */
-                        globalRegs->DMAQNUM[(*pLCh) >> 3u] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh);
-                        globalRegs->DMAQNUM[(*pLCh) >> 3u] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh), evtQueue);
+                        globalRegs->DMAQNUM[(*pLCh) >> 3U] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh);
+                        globalRegs->DMAQNUM[(*pLCh) >> 3U] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh), evtQueue);
 
-                        edma3OsProtectExit(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
+                        edma3OsProtectExit(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                                                        intState);
 #endif
 
@@ -555,7 +555,7 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
                                                if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
                                {
                                            globalRegs->DCHMAP[*pLCh] &= EDMA3_DRV_DCH_PARAM_CLR_MASK;
-                                           globalRegs->DCHMAP[*pLCh] |= EDMA3_DRV_DCH_PARAM_SET_MASK(paRAMId);
+                                           globalRegs->DCHMAP[*pLCh] |= EDMA3_DRV_DCH_PARAM_SET_MASK((uint32_t)paRAMId);
                             }
 
                         /* Step 7: Set TCC in ParamSet.OPT field */
@@ -599,7 +599,7 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
 
                         /* Step 6: Map PaRAM Set to DMA Channel and set the Default Trigger Word */
                                        globalRegs->QCHMAP[qdmaChannel] &= EDMA3_DRV_QCH_PARAM_TRWORD_CLR_MASK;
-                                       globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_PARAM_SET_MASK(paRAMId);
+                                       globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_PARAM_SET_MASK((uint32_t)paRAMId);
                                        globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_TRWORD_SET_MASK(EDMA3_RM_QDMA_TRIG_DEFAULT);
 
                         /* Step 7: Set TCC in ParamSet.OPT field */
@@ -609,7 +609,7 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
                                                edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;
 
                                                /* Step 8: Enable the QDMA Channel */
-                                               drvInst->shadowRegs->QEESR = 1u << qdmaChannel;
+                                               drvInst->shadowRegs->QEESR = 1U << qdmaChannel;
                                                }
                                        }
                                        break;
@@ -873,14 +873,14 @@ EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
 #ifdef EDMA3_DRV_DEBUG
             EDMA3_DRV_PRINTF("EMR =%l\r\n", globalRegs->EMR);
 #endif
-                if(channelId < 32u)
+                if(channelId < 32U)
                     {
                     /* Disables the DMA channels */
-                    drvInst->shadowRegs->EECR = (1u << channelId);
+                    drvInst->shadowRegs->EECR = (1U << channelId);
                     /* Write to EMCR to clear the corresponding EMR bit */
-                    globalRegs->EMCR = (1u << channelId);
+                    globalRegs->EMCR = (1U << channelId);
                     /* Clears the SER */
-                    drvInst->shadowRegs->SECR = (1u << channelId);
+                    drvInst->shadowRegs->SECR = (1U << channelId);
                     }
                 else
                     {
@@ -888,17 +888,17 @@ EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
                     EDMA3_DRV_PRINTF("EMRH =%l\r\n", globalRegs->EMRH);
 #endif
                     /* Disables the DMA channels */
-                    drvInst->shadowRegs->EECRH = (1u << (channelId - 32u));
+                    drvInst->shadowRegs->EECRH = (1U << (channelId - 32U));
                     /* Write to EMCR to clear the corresponding EMR bit */
-                    globalRegs->EMCRH = (1u << (channelId - 32u));
+                    globalRegs->EMCRH = (1U << (channelId - 32U));
                     /* Clears the SER */
-                    drvInst->shadowRegs->SECRH = (1u << (channelId - 32u));
+                    drvInst->shadowRegs->SECRH = (1U << (channelId - 32U));
                     }
 
                 /* Clear the global CC Error Register */
                 for (count = 0; count < drvObject->gblCfgParams.numEvtQueue; count++)
                     {
-                    value |= (1u << count);
+                    value |= (((uint32_t)1U) << count);
                     }
 
                 globalRegs->CCERRCLR = (EDMA3_CCRL_CCERR_TCCERR_MASK | value);
@@ -1217,7 +1217,7 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
 
     /** In FIFO Addressing mode, memory location must be 32 bytes aligned */
     if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
-        && ((srcAddr & 0x1Fu) != NULL))
+        && ((srcAddr & 0x1FU) != NULL))
         {
         /** Memory is not 32 bytes aligned */
         result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;
@@ -1269,9 +1269,9 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
             {
             if (lCh <= edma3_dma_ch_max_val [edma3Id])
                 {
-                mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u])
+                mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3U])
                                 & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
-                                  >> ((lCh%8u)*4u);
+                                  >> ((lCh%8U)*4U);
                 }
             else
                 {
@@ -1280,7 +1280,7 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
                     {
                     mappedEvtQ = ((globalRegs->QDMAQNUM)
                                     & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
-                                   >> (lCh*4u);
+                                   >> (lCh*4U);
                     }
                 }
 
@@ -1289,7 +1289,7 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
                * process this transfer request. Check whether this TC supports the
                * FIFO size or not.
                */
-            defaultBurstSize = 1u << fifoWidth;
+            defaultBurstSize = (uint32_t)1U << fifoWidth;
             if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
                 {
                 result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
@@ -1362,7 +1362,7 @@ EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
 
     /** In FIFO Addressing mode, memory location must be 32 bytes aligned */
     if ((addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
-        && ((destAddr & 0x1Fu)!=NULL))
+        && ((destAddr & 0x1FU)!=NULL))
         {
         /** Memory is not 32 bytes aligned */
         result = EDMA3_DRV_E_ADDRESS_NOT_ALIGNED;
@@ -1414,9 +1414,9 @@ EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
             {
             if (lCh <= edma3_dma_ch_max_val [edma3Id])
                 {
-                mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u])
+                mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3U])
                                 & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
-                                  >> ((lCh%8u)*4u);
+                                  >> ((lCh%8U)*4U);
                 }
             else
                 {
@@ -1425,7 +1425,7 @@ EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
                     {
                     mappedEvtQ = ((globalRegs->QDMAQNUM)
                                     & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
-                                   >> (lCh*4u);
+                                   >> (lCh*4U);
                     }
                 }
 
@@ -1434,7 +1434,7 @@ EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
                * process this transfer request. Check whether this TC supports the
                * FIFO size or not.
                */
-            defaultBurstSize = 1u << fifoWidth;
+            defaultBurstSize = (uint32_t)1U << fifoWidth;
             if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
                 {
                 result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
@@ -1547,9 +1547,9 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,
                srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
                                                        + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
 
-               srcDstBidx &= 0xFFFF0000u;
+               srcDstBidx &= 0xFFFF0000U;
                /* Update it */
-               srcDstBidx |= (uint32_t)(srcBIdx & 0xFFFF);
+               srcDstBidx |= ((uint32_t)srcBIdx & (uint32_t)0xFFFF);
 
                /* Store it back */
                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
@@ -1559,9 +1559,9 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,
                srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
                                                        + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
 
-               srcDstCidx &= 0xFFFF0000u;
+               srcDstCidx &= 0xFFFF0000U;
                /* Update it */
-               srcDstCidx |= (uint32_t)(srcCIdx & 0xFFFF);
+               srcDstCidx |= ((uint32_t)srcCIdx & (uint32_t)0xFFFF);
 
                /* Store it back */
                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
@@ -1654,9 +1654,9 @@ EDMA3_DRV_Result  EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, uint32_t lCh,
             srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
                                                        + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
 
-            srcDstBidx &= 0xFFFFu;
+            srcDstBidx &= 0xFFFFU;
             /* Update it */
-            srcDstBidx |= (uint32_t)((destBIdx & 0xFFFF) << 16u);
+            srcDstBidx |= (((uint32_t)destBIdx & (uint32_t)0xFFFF) << 16U);
 
             /* Store it back */
             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
@@ -1666,9 +1666,9 @@ EDMA3_DRV_Result  EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, uint32_t lCh,
             srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
                                                        + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
 
-            srcDstCidx &= 0xFFFFu;
+            srcDstCidx &= 0xFFFFU;
             /* Update it */
-            srcDstCidx |= (uint32_t)((destCIdx & 0xFFFF) << 16u);
+            srcDstCidx |= (((uint32_t)destCIdx & (uint32_t)0xFFFF) << 16U);
 
             /* Store it back */
             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
@@ -1760,7 +1760,7 @@ EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,
             }
                else
                {
-               abCnt = aCnt | ((bCnt&0xFFFFu) << 16u);
+               abCnt = aCnt | ((bCnt&0xFFFFU) << 16U);
 
             /* Set aCnt and bCnt */
             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
@@ -1774,7 +1774,7 @@ EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,
             linkBCntReld = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
                                                        + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
 
-            linkBCntReld |= ((bCntReload & 0xFFFFu) << 16u);
+            linkBCntReld |= ((bCntReload & 0xFFFFU) << 16U);
 
             /* Set bCntReload */
             *((&globalRegs->PARAMENTRY[paRAMId].OPT)
@@ -1869,8 +1869,8 @@ EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
 
        /* Trigger type is Event */
     if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
-       && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
-         & (1u<<(lCh%32u))) == FALSE))
+       && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
+         & ((uint32_t)1U<<(lCh%32U))) == FALSE))
        {
         /* Channel was not mapped to any Hw Event. */
         result = EDMA3_DRV_E_INVALID_PARAM;
@@ -1883,13 +1883,13 @@ EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
             {
             case EDMA3_DRV_TRIG_MODE_MANUAL :
                 {
-                if (lCh < 32u)
+                if (lCh < 32U)
                     {
                     drvInst->shadowRegs->ESR = (1UL << lCh);
                     }
                 else
                     {
-                    drvInst->shadowRegs->ESRH = (1UL << (lCh-32u));
+                    drvInst->shadowRegs->ESRH = (1UL << (lCh-32U));
                     }
                 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
                                                                                                        EDMA3_DRV_TRIG_MODE_MANUAL;
@@ -1898,7 +1898,7 @@ EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
 
             case EDMA3_DRV_TRIG_MODE_QDMA :
                 {
-                drvInst->shadowRegs->QEESR = (1u<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
+                drvInst->shadowRegs->QEESR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
                 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
                                                                                                                EDMA3_DRV_TRIG_MODE_QDMA;
                 }
@@ -1906,7 +1906,7 @@ EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
 
             case EDMA3_DRV_TRIG_MODE_EVENT :
                 {
-                if (lCh < 32u)
+                if (lCh < 32U)
                    {
                     /*clear SECR to clean any previous NULL request */
                     drvInst->shadowRegs->SECR = (1UL << lCh);
@@ -1919,12 +1919,12 @@ EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
                 else
                     {
                     /*clear SECR to clean any previous NULL request */
-                    drvInst->shadowRegs->SECRH = (1UL << (lCh-32u));
+                    drvInst->shadowRegs->SECRH = (1UL << (lCh-32U));
 
                     /*clear EMCR to clean any previous NULL request */
-                    globalRegs->EMCRH = (1UL << (lCh-32u));
+                    globalRegs->EMCRH = (1UL << (lCh-32U));
 
-                    drvInst->shadowRegs->EESRH = (1UL << (lCh-32u));
+                    drvInst->shadowRegs->EESRH = (1UL << (lCh-32U));
                     }
 
                 edma3DrvChBoundRes[edma3Id][lCh].trigMode =
@@ -2017,8 +2017,8 @@ EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
 
        /* Trigger type is Event */
     if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
-       && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
-         & (1u<<(lCh%32u))) == FALSE))
+       && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
+         & ((uint32_t)1U<<(lCh%32U))) == FALSE))
        {
         /* Channel was not mapped to any Hw Event. */
         result = EDMA3_DRV_E_INVALID_PARAM;
@@ -2031,27 +2031,27 @@ EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
             {
             case EDMA3_DRV_TRIG_MODE_MANUAL :
                 {
-                if (lCh < 32u)
+                if (lCh < 32U)
                     {
-                    if((drvInst->shadowRegs->SER & (1u<<lCh))!=FALSE)
+                    if((drvInst->shadowRegs->SER & ((uint32_t)1U<<lCh))!=FALSE)
                         {
-                        drvInst->shadowRegs->SECR = (1u<<lCh);
+                        drvInst->shadowRegs->SECR = (1U<<lCh);
                         }
-                    if((globalRegs->EMR & (1u<<lCh))!=FALSE)
+                    if((globalRegs->EMR & ((uint32_t)1U<<lCh))!=FALSE)
                         {
-                        globalRegs->EMCR = (1u<<lCh);
+                        globalRegs->EMCR = (1U<<lCh);
                         }
                     }
                 else
                     {
-                    if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE)
+                    if((drvInst->shadowRegs->SERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
                         {
-                        drvInst->shadowRegs->SECRH = (1u<<(lCh-32u));
+                        drvInst->shadowRegs->SECRH = (1U<<(lCh-32U));
                         }
 
-                    if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE)
+                    if((globalRegs->EMRH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
                         {
-                        globalRegs->EMCRH = (1u<<(lCh-32u));
+                        globalRegs->EMCRH = (1U<<(lCh-32U));
                         }
                     }
                 }
@@ -2059,45 +2059,45 @@ EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
 
             case EDMA3_DRV_TRIG_MODE_QDMA :
                 {
-                drvInst->shadowRegs->QEECR = (1u<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
+                drvInst->shadowRegs->QEECR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
                 }
                 break;
 
             case EDMA3_DRV_TRIG_MODE_EVENT :
                 {
-                if (lCh < 32u)
+                if (lCh < 32U)
                     {
-                    drvInst->shadowRegs->EECR = (1u << lCh);
+                    drvInst->shadowRegs->EECR = (1U << lCh);
 
-                    if((drvInst->shadowRegs->ER & (1u<<lCh))!=FALSE)
+                    if((drvInst->shadowRegs->ER & ((uint32_t)1U<<lCh))!=FALSE)
                         {
-                        drvInst->shadowRegs->ECR = (1u<<lCh);
+                        drvInst->shadowRegs->ECR = (1U<<lCh);
                         }
-                    if((drvInst->shadowRegs->SER & (1u<<lCh))!=FALSE)
+                    if((drvInst->shadowRegs->SER & ((uint32_t)1U<<lCh))!=FALSE)
                         {
-                        drvInst->shadowRegs->SECR = (1u<<lCh);
+                        drvInst->shadowRegs->SECR = (1U<<lCh);
                         }
-                    if((globalRegs->EMR & (1u<<lCh))!=FALSE)
+                    if((globalRegs->EMR & ((uint32_t)1U<<lCh))!=FALSE)
                         {
-                        globalRegs->EMCR = (1u<<lCh);
+                        globalRegs->EMCR = (1U<<lCh);
                         }
                     }
                 else
                     {
-                    drvInst->shadowRegs->EECRH = (1u << (lCh-32u));
-                    if((drvInst->shadowRegs->ERH & (1u<<(lCh-32u)))!=FALSE)
+                    drvInst->shadowRegs->EECRH = (1U << (lCh-32U));
+                    if((drvInst->shadowRegs->ERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
                         {
-                        drvInst->shadowRegs->ECRH = (1u<<(lCh-32u));
+                        drvInst->shadowRegs->ECRH = (1U<<(lCh-32U));
                         }
 
-                    if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE)
+                    if((drvInst->shadowRegs->SERH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
                         {
-                        drvInst->shadowRegs->SECRH = (1u<<(lCh-32u));
+                        drvInst->shadowRegs->SECRH = (1U<<(lCh-32U));
                         }
 
-                    if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE)
+                    if((globalRegs->EMRH & ((uint32_t)1U<<(lCh-32U)))!=FALSE)
                         {
-                        globalRegs->EMCRH = (1u<<(lCh-32u));
+                        globalRegs->EMCRH = (1U<<(lCh-32U));
                         }
                     }
                 }
@@ -2178,8 +2178,8 @@ EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
 
        /* Trigger type is Event */
     if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
-       && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
-         & (1u<<(lCh%32u))) == FALSE))
+       && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32U]
+         & ((uint32_t)1U<<(lCh%32U))) == FALSE))
        {
         /* Channel was not mapped to any Hw Event. */
         result = EDMA3_DRV_E_INVALID_PARAM;
@@ -2192,16 +2192,20 @@ EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
             {
             case EDMA3_DRV_TRIG_MODE_QDMA:
                 {
-                drvInst->shadowRegs->QEECR = (1u<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
+                drvInst->shadowRegs->QEECR = (1U<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
                 }
                 break;
 
             case EDMA3_DRV_TRIG_MODE_EVENT:
                 {
-                if (lCh < 32u)
-                    drvInst->shadowRegs->EECR = (1u << lCh);
+                if (lCh < 32U)
+                    {
+                        drvInst->shadowRegs->EECR = (1U << lCh);
+                    }
                 else
-                    drvInst->shadowRegs->EECRH = (1u << (lCh-32u));
+                    {
+                        drvInst->shadowRegs->EECRH = (1U << (lCh-32U));
+                    }
                 }
                 break;
 
@@ -2289,14 +2293,14 @@ static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
 
     if (result == EDMA3_RM_SOK)
         {
-        edma3OsProtectEntry(edma3Id, EDMA3_OS_PROTECT_INTERRUPT, &intState);
+        edma3OsProtectEntry(edma3Id, (int32_t)EDMA3_OS_PROTECT_INTERRUPT, &intState);
 
         if (channelId <= edma3_dma_ch_max_val [edma3Id])
             {
             /* DMA channel */
 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
             /* Remove the channel to Event Queue mapping */
-            globalRegs->DMAQNUM[channelId >> 3u] &=
+            globalRegs->DMAQNUM[channelId >> 3U] &=
                             EDMA3_DRV_DMAQNUM_CLR_MASK(channelId);
 #endif
             /**
@@ -2328,7 +2332,7 @@ static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
             }
 
         edma3OsProtectExit(edma3Id,
-                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                       (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
                                                        intState);
         }