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raw | patch | inline | side by side (parent: e58475a)
raw | patch | inline | side by side (parent: e58475a)
author | Sundaram Raju <sundaram@ti.com> | |
Mon, 28 Jun 2010 08:32:06 +0000 (14:02 +0530) | ||
committer | Sundaram Raju <sundaram@ti.com> | |
Thu, 15 Jul 2010 12:34:10 +0000 (18:04 +0530) |
- Refer to IR# SDOCM00069906 for more details
Signed-off-by: Sundaram Raju <sundaram@ti.com>
Signed-off-by: Sundaram Raju <sundaram@ti.com>
packages/ti/sdo/edma3/rm/src/edma3resmgr.c | patch | blob | history |
diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.c b/packages/ti/sdo/edma3/rm/src/edma3resmgr.c
index dad4a44dd1470bc09a2ccd63182a00e4e75def93..fef972f0d69e154dd9825525e2478e14018930c9 100755 (executable)
unsigned int resIdSet = 0x0;
unsigned int resId;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
-
+ unsigned int edma3Id;
+
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
else
{
gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
-
+ edma3Id = rmObj->phyCtrllerInstId;
resId = resObj->resId;
resIdClr = (unsigned int)(~(1u << (resId%32u)));
{
resObj->resId = avlblIdx;
rmInstance->avlblTccs [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the Interrupt channel in the
+ * DRAE/DRAEH registers also.
+ * Also, If the region id coming from this
+ * RM instance is same as the Master RM
+ * Instance's region id, only then we will be
+ * getting the interrupts on the same side.
+ * So save the TCC in the allocatedTCCs[] array.
+ */
+ if (avlblIdx < 32u)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= (0x1u << avlblIdx);
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0u] |= (0x1u << avlblIdx);
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= (0x1u << (avlblIdx - 32u));
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1u] |= (0x1u << (avlblIdx - 32u));
+ }
+ }
+ }
+
+
result = EDMA3_RM_SOK;
break;
}
if (((rmInstance->avlblTccs [resId/32u])&(resIdSet))!=FALSE)
{
rmInstance->avlblTccs [resId/32u] &= resIdClr;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the Interrupt channel in the
+ * DRAE/DRAEH registers also.
+ * Also, If the region id coming from this
+ * RM instance is same as the Master RM
+ * Instance's region id, only then we will be
+ * getting the interrupts on the same side.
+ * So save the TCC in the allocatedTCCs[] array.
+ */
+ if (resId < 32u)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= (0x1u << resId);
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0u] |= (0x1u << resId);
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= (0x1u << (resId - 32u));
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1u] |= (0x1u << (resId - 32u));
+ }
+ }
+ }
+
result = EDMA3_RM_SOK;
}
else
unsigned int resId;
unsigned int resIdSet = 0x0;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
-
+ unsigned int edma3Id;
+
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
else
{
gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
-
+ edma3Id = rmObj->phyCtrllerInstId;
resId = resObj->resId;
resIdSet = 1u << (resId%32u);
{
rmInstance->avlblTccs [resId/32u] |= resIdSet;
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Interrupt Channel is freed.
+ * Reset the bit specific to the Interrupt
+ * channel in the DRAE/DRAEH register also.
+ * Also, if we have earlier saved this
+ * TCC in allocatedTCCs[] array,
+ * remove it from there too.
+ */
+ if (resId < 32u)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ &= (~(0x1u << resId));
+
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0u] &= (~(0x1u << resId));
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ &= (~(0x1u << (resId-32u)));
+
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1u] &= (~(0x1u << (resId -32u)));
+ }
+ }
+ }
+
result = EDMA3_RM_SOK;
}
else
if (EDMA3_RM_SOK == result)
{
- /**
- * Enable the Interrupt channel in the DRAE/DRAEH registers also.
- * Also, If the region id coming from this RM instance is same as the
- * Master RM Instance's region id, only then we will be getting the
- * interrupts on the same side.
- * So save the TCC in the allocatedTCCs[] array.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- if (tcc < 32u)
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << tcc);
-
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][0u] |= (0x1u << tcc);
- }
- }
- else
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (tcc - 32u));
-
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][1u] |= (0x1u << (tcc - 32u));
- }
- }
- }
/* Enable the interrupts in IESR/IESRH */
if (tcc < 32u)
if (EDMA3_RM_SOK == result)
{
- if (TRUE == rmInstance->regModificationRequired)
- {
- /**
- * Interrupt Channel is freed. Reset the bit specific to the Interrupt
- * channel in the DRAE/DRAEH register also. Also, if we have earlier
- * saved this TCC in allocatedTCCs[] array, remove it from there too.
- */
- if (mappedTcc < 32u)
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- &= (~(0x1u << mappedTcc));
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][0u] &= (~(0x1u << mappedTcc));
- }
- }
- else
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- &= (~(0x1u << (mappedTcc-32u)));
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][1u] &= (~(0x1u << (mappedTcc-32u)));
- }
- }
- }
/* Remove the callback function too */
if (mappedTcc < 32u)