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raw | patch | inline | side by side (parent: 4945d57)
raw | patch | inline | side by side (parent: 4945d57)
author | Sunil MS <x0190988@ti.com> | |
Tue, 30 Sep 2014 14:35:50 +0000 (20:05 +0530) | ||
committer | Sunil MS <x0190988@ti.com> | |
Tue, 14 Oct 2014 09:12:06 +0000 (14:42 +0530) |
MISRA.ASM.ENCAPS
MISRA.BITS.NOT_UNSIGNED
MISRA.BUILTIN_NUMERIC
MISRA.CVALUE.IMPL.CAST
MISRA.DECL.ARRAY_SIZE
MISRA.DEFINE.BADEXP
MISRA.EXPR.PARENS
MISRA.FUNC.NOPROT.DEF
MISRA.FUNC.UNNAMED.PARAMS
MISRA.IF.NO_COMPOUND
MISRA.IF.NO_ELSE
MISRA.INIT.BRACES
MISRA.VAR.UNIQUE.STATIC
Signed-off-by: Sunil MS <x0190988@ti.com>
Change-Id: I1ebca5c908ab6ba6370d81fa1351099028aae2df
Signed-off-by: Sunil MS <x0190988@ti.com>
MISRA.BITS.NOT_UNSIGNED
MISRA.BUILTIN_NUMERIC
MISRA.CVALUE.IMPL.CAST
MISRA.DECL.ARRAY_SIZE
MISRA.DEFINE.BADEXP
MISRA.EXPR.PARENS
MISRA.FUNC.NOPROT.DEF
MISRA.FUNC.UNNAMED.PARAMS
MISRA.IF.NO_COMPOUND
MISRA.IF.NO_ELSE
MISRA.INIT.BRACES
MISRA.VAR.UNIQUE.STATIC
Signed-off-by: Sunil MS <x0190988@ti.com>
Change-Id: I1ebca5c908ab6ba6370d81fa1351099028aae2df
Signed-off-by: Sunil MS <x0190988@ti.com>
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c
index e806f1212712a5b1c74bf0a3cbe38d97e17a017f..ba2e01154f96c93763af31548532e4c2cd495dd9 100644 (file)
*/\r
void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =\r
{\r
- (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,\r
- (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,\r
- (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,\r
- (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,\r
- (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,\r
- (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,\r
- (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,\r
- (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,\r
+ &lisrEdma3TC0ErrHandler0,\r
+ &lisrEdma3TC1ErrHandler0,\r
+ &lisrEdma3TC2ErrHandler0,\r
+ &lisrEdma3TC3ErrHandler0,\r
+ &lisrEdma3TC4ErrHandler0,\r
+ &lisrEdma3TC5ErrHandler0,\r
+ &lisrEdma3TC6ErrHandler0,\r
+ &lisrEdma3TC7ErrHandler0,\r
};\r
\r
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];\r
-extern unsigned int ccErrorInt[];\r
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];\r
-extern unsigned int numEdma3Tc[];\r
-extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];\r
-extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];\r
-extern unsigned int ccErrorIntXbarInstNo[];\r
-extern unsigned int ccErrEdmaXbarIndex[];\r
-extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];\r
-extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];\r
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];\r
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t ccXferCompIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
+extern uint32_t ccCompEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
+extern uint32_t ccErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t ccErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t tcErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];\r
+extern uint32_t tcErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];\r
\r
/**\r
* Variables which will be used internally for referring the hardware interrupt\r
* for various EDMA3 interrupts.\r
*/\r
-extern unsigned int hwIntXferComp[];\r
-extern unsigned int hwIntCcErr[];\r
-extern unsigned int hwIntTcErr[];\r
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];\r
\r
-extern unsigned int dsp_num;\r
+extern uint32_t dsp_num;\r
/* This variable has to be used as an extern */\r
-unsigned int gpp_num = 0;\r
+uint32_t gpp_num = 0;\r
\r
Hwi_Handle hwiCCXferCompInt;\r
Hwi_Handle hwiCCErrInt;\r
\r
/* External Instance Specific Configuration Structure */\r
extern EDMA3_DRV_GblXbarToChanConfigParams \r
- sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];\r
+ sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
\r
typedef struct {\r
volatile Uint32 TPCC_EVTMUX[32];\r
/*\r
* Forward decleration\r
*/\r
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
- unsigned int *chanNum,\r
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,\r
+ uint32_t *chanNum,\r
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);\r
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
- unsigned int chanNum);\r
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,\r
+ uint32_t chanNum);\r
\r
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
+ uint32_t edma3Id);\r
\r
/** To Register the ISRs with the underlying OS, if required. */\r
-void registerEdma3Interrupts (unsigned int edma3Id)\r
+void registerEdma3Interrupts (uint32_t edma3Id);\r
+/** To Unregister the ISRs with the underlying OS, if previously registered. */\r
+void unregisterEdma3Interrupts (uint32_t edma3Id);\r
+\r
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId);\r
+\r
+/** To Register the ISRs with the underlying OS, if required. */\r
+void registerEdma3Interrupts (uint32_t edma3Id)\r
{\r
static UInt32 cookie = 0;\r
- unsigned int numTc = 0;\r
+ uint32_t numTc = 0;\r
\r
/*\r
* Skip these interrupt xbar configuration.\r
* if it is accessing EVE internal edma instance ie edma3id = 2 and dsp_num = 1.\r
*/\r
- if (edma3Id != 2 && dsp_num != 1)\r
+ if ((edma3Id != 2U) && (dsp_num != 1U))\r
{\r
IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);\r
IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);\r
/* argument for the ISR */\r
hwiParams.arg = edma3Id;\r
/* set the priority ID */\r
- //hwiParams.priority = hwIntXferComp[edma3Id];\r
+ /* hwiParams.priority = hwIntXferComp[edma3Id]; */\r
\r
hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],\r
((Hwi_FuncPtr)&lisrEdma3ComplHandler0),\r
(const Hwi_Params *) (&hwiParams),\r
&eb);\r
- if (TRUE == Error_check(&eb))\r
+ if ((bool)TRUE == Error_check(&eb))\r
{\r
System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
}\r
/* argument for the ISR */\r
hwiParams.arg = edma3Id;\r
/* set the priority ID */\r
- //hwiParams.priority = hwIntCcErr[edma3Id];\r
+ /* hwiParams.priority = hwIntCcErr[edma3Id]; */\r
\r
hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],\r
((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),\r
(const Hwi_Params *) (&hwiParams),\r
&eb);\r
\r
- if (TRUE == Error_check(&eb))\r
+ if ((bool)TRUE == Error_check(&eb))\r
{\r
System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
}\r
/* argument for the ISR */\r
hwiParams.arg = edma3Id;\r
/* set the priority ID */\r
- //hwiParams.priority = hwIntTcErr[edma3Id];\r
+ /* hwiParams.priority = hwIntTcErr[edma3Id]; */\r
\r
hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],\r
(ptrEdma3TcIsrHandler[numTc]),\r
(const Hwi_Params *) (&hwiParams),\r
&eb);\r
- if (TRUE == Error_check(&eb))\r
+ if ((bool)TRUE == Error_check(&eb))\r
{\r
System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
}\r
}\r
\r
/** To Unregister the ISRs with the underlying OS, if previously registered. */\r
-void unregisterEdma3Interrupts (unsigned int edma3Id)\r
+void unregisterEdma3Interrupts (uint32_t edma3Id)\r
{\r
- static UInt32 cookie = 0;\r
- unsigned int numTc = 0;\r
+ static UInt32 cookiee = 0;\r
+ uint32_t numTc = 0;\r
\r
/* Disabling the global interrupts */\r
- cookie = Hwi_disable();\r
+ cookiee = Hwi_disable();\r
\r
Hwi_delete(&hwiCCXferCompInt);\r
Hwi_delete(&hwiCCErrInt);\r
numTc++;\r
}\r
/* Restore interrupts */\r
- Hwi_restore(cookie);\r
+ Hwi_restore(cookiee);\r
}\r
\r
/**\r
*\r
* \return EDMA3_DRV_SOK if success, else error code\r
*/\r
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
- unsigned int *chanNum,\r
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,\r
+ uint32_t *chanNum,\r
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)\r
{\r
EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
- unsigned int xbarEvtNum = 0;\r
- int edmaChanNum = 0;\r
+ uint32_t xbarEvtNum = 0;\r
+ int32_t edmaChanNum = 0;\r
\r
if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&\r
(chanNum != NULL) &&\r
*\r
* \return EDMA3_DRV_SOK if success, else error code\r
*/\r
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
- unsigned int chanNum)\r
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,\r
+ uint32_t chanNum)\r
{\r
EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;\r
- unsigned int scrChanOffset = 0;\r
- unsigned int scrRegOffset = 0;\r
- unsigned int xBarEvtNum = 0;\r
+ uint32_t scrChanOffset = 0;\r
+ uint32_t scrRegOffset = 0;\r
+ uint32_t xBarEvtNum = 0;\r
CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);\r
\r
\r
if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&\r
(chanNum < EDMA3_NUM_TCC))\r
{\r
- scrRegOffset = chanNum / 2;\r
- scrChanOffset = chanNum - (scrRegOffset * 2);\r
- xBarEvtNum = eventNum + 1;\r
+ scrRegOffset = chanNum / 2U;\r
+ scrChanOffset = chanNum - (scrRegOffset * 2U);\r
+ xBarEvtNum = eventNum + 1U;\r
\r
switch(scrChanOffset)\r
{\r
scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
(xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);\r
break;\r
- case 1:\r
+ case 1U:\r
scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
}\r
\r
EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
- unsigned int edma3Id)\r
+ uint32_t edma3Id)\r
{\r
EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;\r
const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =\r
return retVal;\r
}\r
\r
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId)\r
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId)\r
{\r
+#ifdef EDMA3_DRV_DEBUG\r
+ /* Added to fix Misra C error */\r
printf("memory Protection error");\r
+#endif\r
}\r
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c
index 24c35e29032ca43c7ebcdf93786ce3797a6b81a2..31fa4e739fe942a8b03e7178d9e8ed8910cd9e65 100644 (file)
#endif\r
\r
/* Number of EDMA3 controllers present in the system */\r
-#define NUM_EDMA3_INSTANCES 3u\r
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
+#define NUM_EDMA3_INSTANCES 3U\r
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;\r
\r
/* Number of DSPs present in the system */\r
-#define NUM_DSPS 1u\r
-const unsigned int numDsps = NUM_DSPS;\r
+#define NUM_DSPS 1U\r
+const uint32_t numDsps = NUM_DSPS;\r
\r
/* Determine the processor id by reading DNUM register. */\r
/* Statically allocate the region numbers with cores. */\r
-int myCoreNum;\r
-#define PID0_ADDRESS 0xE00FFFE0\r
-#define CORE_ID_C0 0x0\r
-#define CORE_ID_C1 0x1\r
-\r
-unsigned short determineProcId()\r
-{\r
- unsigned short regionNo = numEdma3Instances;\r
-#ifdef BUILD_TDA2XX_DSP\r
- extern __cregister volatile unsigned int DNUM;\r
-#endif\r
-\r
- myCoreNum = numDsps;\r
+int32_t myCoreNum;\r
+#define PID0_ADDRESS 0xE00FFFE0U\r
+#define CORE_ID_C0 0x0U\r
+#define CORE_ID_C1 0x1U\r
\r
#ifdef BUILD_TDA2XX_MPU\r
+void __inline readProcFeatureReg(void);\r
+void __inline readProcFeatureReg(void)\r
+{\r
asm (" push {r0-r2} \n\t"\r
" MRC p15, 0, r0, c0, c0, 5\n\t"\r
" LDR r1, =myCoreNum\n\t"\r
" STR r0, [r1]\n\t"\r
" pop {r0-r2}\n\t");\r
- if((myCoreNum & 0x03) == 1)\r
- regionNo = 1;\r
- else\r
- regionNo = 0;\r
+}\r
+#endif\r
+\r
+uint16_t determineProcId(void);\r
+\r
+int8_t* getGlobalAddr(int8_t* addr);\r
+\r
+uint16_t isGblConfigRequired(uint32_t dspNum);\r
+\r
+uint16_t determineProcId(void)\r
+{\r
+ uint16_t regionNo = (uint16_t)numEdma3Instances;\r
+#ifdef BUILD_TDA2XX_DSP\r
+ extern __cregister volatile uint32_t DNUM;\r
+#endif\r
+\r
+ myCoreNum = (int32_t)numDsps;\r
+\r
+#ifdef BUILD_TDA2XX_MPU\r
+ readProcFeatureReg();\r
+/* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */\r
+ regionNo = 0U;\r
+ if(((uint32_t)myCoreNum & 0x03U) == 1U)\r
+ {\r
+ regionNo = 1U;\r
+ }\r
#elif defined(BUILD_TDA2XX_IPU)\r
- myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
- if(Core_getIpuId() == 1){\r
- if(myCoreNum == CORE_ID_C0)\r
- regionNo = 4;\r
- else if (myCoreNum == CORE_ID_C1)\r
- regionNo = 5;\r
+ myCoreNum = (*(uint32_t *)(PID0_ADDRESS));\r
+ if(Core_getIpuId() == 1U){\r
+ if(myCoreNum == (int32_t)CORE_ID_C0)\r
+ {\r
+ regionNo = 4U;\r
+ }\r
+ else if (myCoreNum == (int32_t)CORE_ID_C1)\r
+ {\r
+ regionNo = 5U;\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to be done here*/\r
+ }\r
}\r
- if(Core_getIpuId() == 2){\r
- if(myCoreNum == CORE_ID_C0)\r
- regionNo = 6;\r
- else if (myCoreNum == CORE_ID_C1)\r
- regionNo = 7;\r
+ if(Core_getIpuId() == 2U){\r
+ if(myCoreNum == (int32_t)CORE_ID_C0)\r
+ {\r
+ regionNo = 6U;\r
+ }\r
+ else if (myCoreNum == (int32_t)CORE_ID_C1)\r
+ {\r
+ regionNo = 7U;\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to be done here*/\r
+ }\r
}\r
#elif defined(BUILD_TDA2XX_DSP)\r
\r
- myCoreNum = DNUM;\r
+ myCoreNum = (int32_t)DNUM;\r
if(myCoreNum == 0)\r
- regionNo = 2;\r
+ {\r
+ regionNo = 2U;\r
+ }\r
else\r
- regionNo = 3;\r
+ {\r
+ regionNo = 3U;\r
+ }\r
#elif defined(BUILD_TDA2XX_EVE)\r
- regionNo = 1;\r
+ regionNo = 1U;\r
#endif\r
return regionNo;\r
}\r
\r
-signed char* getGlobalAddr(signed char* addr)\r
+int8_t* getGlobalAddr(int8_t* addr)\r
{\r
return (addr); /* The address is already a global address */\r
}\r
-unsigned short isGblConfigRequired(unsigned int dspNum)\r
+uint16_t isGblConfigRequired(uint32_t dspNum)\r
{\r
(void) dspNum;\r
- return 1;\r
+ return 1U;\r
}\r
\r
/* Semaphore handles */\r
#define TC1_ERROR_INT_IPU_XBAR_INST_NO (15u)\r
\r
#ifdef BUILD_TDA2XX_MPU\r
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15\r
-#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_A15\r
-#define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_A15_XBAR_INST_NO\r
-#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_A15\r
-#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_A15\r
-#define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
-#define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_A15)\r
+#define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_A15)\r
+#define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_A15_XBAR_INST_NO)\r
+#define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_A15)\r
+#define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_A15)\r
+#define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
\r
#elif defined BUILD_TDA2XX_DSP\r
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP\r
-#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_DSP\r
-#define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_DSP_XBAR_INST_NO\r
-#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_DSP\r
-#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_DSP\r
-#define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_DSP_XBAR_INST_NO\r
-#define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_DSP_XBAR_INST_NO\r
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_DSP)\r
+#define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_DSP)\r
+#define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_DSP_XBAR_INST_NO)\r
+#define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_DSP)\r
+#define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_DSP)\r
+#define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_DSP_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_DSP_XBAR_INST_NO)\r
\r
#elif defined BUILD_TDA2XX_IPU\r
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_IPU_C0\r
-#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_IPU\r
-#define CC_ERROR_INT_XBAR_INST_NO CC_ERROR_INT_IPU_XBAR_INST_NO\r
-#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_IPU\r
-#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_IPU\r
-#define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_IPU_XBAR_INST_NO\r
-#define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_IPU_XBAR_INST_NO\r
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)\r
+#define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_IPU)\r
+#define CC_ERROR_INT_XBAR_INST_NO (CC_ERROR_INT_IPU_XBAR_INST_NO)\r
+#define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_IPU)\r
+#define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_IPU)\r
+#define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_IPU_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_IPU_XBAR_INST_NO)\r
\r
#elif defined BUILD_TDA2XX_EVE\r
-#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_EVE\r
-#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_EVE\r
-#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_EVE\r
-#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_EVE\r
+#define EDMA3_CC_XFER_COMPLETION_INT (EDMA3_CC_XFER_COMPLETION_INT_EVE)\r
+#define EDMA3_CC_ERROR_INT (EDMA3_CC_ERROR_INT_EVE)\r
+#define EDMA3_TC0_ERROR_INT (EDMA3_TC0_ERROR_INT_EVE)\r
+#define EDMA3_TC1_ERROR_INT (EDMA3_TC1_ERROR_INT_EVE)\r
/* For accessing EVE internal edma, there is no need to configure Xbar */\r
-#define CC_ERROR_INT_XBAR_INST_NO 0u\r
-#define TC0_ERROR_INT_XBAR_INST_NO 0u\r
-#define TC1_ERROR_INT_XBAR_INST_NO 0u\r
+#define CC_ERROR_INT_XBAR_INST_NO (0u)\r
+#define TC0_ERROR_INT_XBAR_INST_NO (0u)\r
+#define TC1_ERROR_INT_XBAR_INST_NO (0u)\r
\r
#else\r
#define EDMA3_CC_XFER_COMPLETION_INT (0u)\r
#define CC_ERROR_INT_XBAR_INST_NO (0u)\r
#define EDMA3_TC0_ERROR_INT (0u)\r
#define EDMA3_TC1_ERROR_INT (0u)\r
-#define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO\r
-#define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO\r
+#define TC0_ERROR_INT_XBAR_INST_NO (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
#endif\r
\r
#define EDMA3_TC2_ERROR_INT (0u)\r
\r
\r
/* Variable which will be used internally for referring number of Event Queues*/\r
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {\r
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {\r
+ EDMA3_NUM_EVTQUE,\r
EDMA3_NUM_EVTQUE,\r
+ EDMA3_NUM_EVTQUE\r
};\r
\r
/* Variable which will be used internally for referring number of TCs. */\r
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {\r
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] = {\r
EDMA3_NUM_TC,\r
EDMA3_NUM_TC,\r
EDMA3_NUM_TC\r
* Variable which will be used internally for referring transfer completion\r
* interrupt.\r
*/\r
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
/* EDMA3 INSTANCE# 0 */\r
{\r
}\r
};\r
/** These are the Xbar instance numbers corresponding to interrupt numbers */\r
-unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
/* EDMA3 INSTANCE# 0 */\r
{\r
};\r
\r
/** These are the Interrupt Crossbar Index For EDMA Completion for different regions */\r
-unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
/* EDMA3 INSTANCE# 0 */\r
{\r
* Variable which will be used internally for referring channel controller's\r
* error interrupt.\r
*/\r
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = \r
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = \r
{\r
EDMA3_CC_ERROR_INT,\r
DSP1_EDMA3_CC_ERROR_INT,\r
EDMA3_CC_ERROR_INT\r
};\r
-unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =\r
+uint32_t ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =\r
{\r
CC_ERROR_INT_XBAR_INST_NO,\r
CC_ERROR_INT_XBAR_INST_NO,\r
CC_ERROR_INT_XBAR_INST_NO\r
};\r
-unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
+uint32_t ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
{\r
XBAR_EDMA_TPCC_IRQ_ERR,\r
XBAR_EDMA_TPCC_IRQ_ERR,\r
* Variable which will be used internally for referring transfer controllers'\r
* error interrupts.\r
*/\r
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
/* EDMA3 INSTANCE# 0 */\r
{\r
EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
}\r
};\r
-unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
/* EDMA3 INSTANCE# 0 */\r
{\r
}\r
};\r
\r
-unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
/* EDMA3 INSTANCE# 0 */\r
{\r
* Variables which will be used internally for referring the hardware interrupt\r
* for various EDMA3 interrupts.\r
*/\r
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] =\r
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =\r
{\r
EDMA3_HWI_INT_XFER_COMP,\r
EDMA3_HWI_INT_XFER_COMP,\r
EDMA3_CC_XFER_COMPLETION_INT\r
};\r
\r
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] =\r
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =\r
{\r
EDMA3_HWI_INT_CC_ERR,\r
EDMA3_HWI_INT_CC_ERR,\r
EDMA3_CC_ERROR_INT\r
};\r
\r
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
/* EDMA3 INSTANCE# 0 */\r
{\r
- EDMA3_HWI_INT_TC0_ERR,\r
- EDMA3_HWI_INT_TC1_ERR,\r
- EDMA3_HWI_INT_TC2_ERR,\r
- EDMA3_HWI_INT_TC3_ERR\r
+ EDMA3_HWI_INT_TC0_ERR ,\r
+ EDMA3_HWI_INT_TC1_ERR ,\r
+ EDMA3_HWI_INT_TC2_ERR ,\r
+ EDMA3_HWI_INT_TC3_ERR ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U \r
},\r
/* EDMA3 INSTANCE# 1 */\r
{\r
- EDMA3_HWI_INT_TC0_ERR,\r
- EDMA3_HWI_INT_TC1_ERR,\r
- EDMA3_HWI_INT_TC2_ERR,\r
- EDMA3_HWI_INT_TC3_ERR\r
+ EDMA3_HWI_INT_TC0_ERR ,\r
+ EDMA3_HWI_INT_TC1_ERR ,\r
+ EDMA3_HWI_INT_TC2_ERR ,\r
+ EDMA3_HWI_INT_TC3_ERR ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U \r
},\r
/* EDMA3 INSTANCE# 2 */\r
{\r
- EDMA3_TC0_ERROR_INT,\r
- EDMA3_TC1_ERROR_INT,\r
- EDMA3_TC2_ERROR_INT,\r
- EDMA3_TC3_ERROR_INT\r
+ EDMA3_TC0_ERROR_INT ,\r
+ EDMA3_TC1_ERROR_INT ,\r
+ EDMA3_TC2_ERROR_INT ,\r
+ EDMA3_TC3_ERROR_INT ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U ,\r
+ 0U \r
}\r
};\r
\r
@@ -2349,6 +2399,190 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
/* EDMA3 INSTANCE# 0 */\r
+ {\r
+ /* Event to channel map for region 0 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 1 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 2 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 3 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 4 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 5 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 6 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 7 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ },\r
+ \r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ /* Event to channel map for region 0 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 1 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 2 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 3 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 4 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 5 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 6 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ /* Event to channel map for region 7 */\r
+ {\r
+ {-1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1, -1,\r
+ -1, -1, -1, -1, -1, -1, -1}\r
+ },\r
+ },\r
+ \r
+ /* EDMA3 INSTANCE# 2 */\r
{\r
/* Event to channel map for region 0 */\r
{\r
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_int_reg.c
index 1318019b93a44c659d774a1f58188ce1d8776a19..a21cfec2d002423baa510492cfcd843e2d1c1997 100644 (file)
&lisrEdma3TC7ErrHandler0,
};
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
-extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
-extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorIntXbarInstNo[];
-extern unsigned int ccErrEdmaXbarIndex[];
-extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
-extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t ccXferCompIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccCompEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t ccErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t tcErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
/**
* Variables which will be used internally for referring the hardware interrupt
* for various EDMA3 interrupts.
*/
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
/* External Instance Specific Configuration Structure */
extern EDMA3_DRV_GblXbarToChanConfigParams
- sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+ sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
typedef struct {
volatile Uint32 TPCC_EVTMUX[32];
/*
* Forward decleration
*/
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
- unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+ uint32_t *chanNum,
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
- unsigned int chanNum);
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+ uint32_t chanNum);
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
+ uint32_t edma3Id);
/** To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id);
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (uint32_t edma3Id);
+
+
+/** To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (uint32_t edma3Id)
{
static UInt32 cookie = 0;
- unsigned int numTc = 0;
+ uint32_t numTc = 0;
/* Do the xbar configuration only for edma inst 0 */
/* EDMA inst 1 is for DSP1 EDMA which has direct interrupt mapping */
if(edma3Id == 0)
/* Enable the Xfer Completion Event Interrupt */
EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
(EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
- edma3Id, 1);
+ edma3Id, (Bool)1);
EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
/* Enable the CC Error Event Interrupt */
EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
(EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
- edma3Id, 1);
+ edma3Id, (Bool)1);
EventCombiner_enableEvent(ccErrorInt[edma3Id]);
/* Enable the TC Error Event Interrupt, according to the number of TCs. */
{
EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
(EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
- edma3Id, 1);
+ edma3Id, (Bool)1);
EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
numTc++;
}
}
/** To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
{
- static UInt32 cookie = 0;
- unsigned int numTc = 0;
+ static UInt32 cookiee = 0;
+ uint32_t numTc = 0;
/* Disabling the global interrupts */
- cookie = Hwi_disable();
+ cookiee = Hwi_disable();
/* Disable the Xfer Completion Event Interrupt */
EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
}
/* Restore interrupts */
- Hwi_restore(cookie);
+ Hwi_restore(cookiee);
}
/**
*
* \return EDMA3_DRV_SOK if success, else error code
*/
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
- unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+ uint32_t *chanNum,
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
{
EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
- unsigned int xbarEvtNum = 0;
- int edmaChanNum = 0;
+ uint32_t xbarEvtNum = 0;
+ int32_t edmaChanNum = 0;
if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&
(chanNum != NULL) &&
*
* \return EDMA3_DRV_SOK if success, else error code
*/
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
- unsigned int chanNum)
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+ uint32_t chanNum)
{
EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
- unsigned int scrChanOffset = 0;
- unsigned int scrRegOffset = 0;
- unsigned int xBarEvtNum = 0;
+ uint32_t scrChanOffset = 0;
+ uint32_t scrRegOffset = 0;
+ uint32_t xBarEvtNum = 0;
CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&
(chanNum < EDMA3_NUM_TCC))
{
- scrRegOffset = chanNum / 2;
- scrChanOffset = chanNum - (scrRegOffset * 2);
- xBarEvtNum = eventNum + 1;
+ scrRegOffset = chanNum / 2U;
+ scrChanOffset = chanNum - (scrRegOffset * 2U);
+ xBarEvtNum = eventNum + 1U;
switch(scrChanOffset)
{
scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
(xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
break;
- case 1:
+ case 1U:
scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
}
EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
- unsigned int edma3Id)
+ uint32_t edma3Id)
{
EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =