summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 8b13c77)
raw | patch | inline | side by side (parent: 8b13c77)
author | Hongmei Gou <h-gou@ti.com> | |
Fri, 3 Sep 2010 04:09:11 +0000 (09:39 +0530) | ||
committer | Sundaram Raju <sundaram@ti.com> | |
Tue, 7 Sep 2010 16:02:31 +0000 (21:32 +0530) |
Signed-off-by: Hongmei Gou <h-gou@ti.com>
packages/ti/sdo/edma3/rm/src/configs/edma3_c6472_cfg.c | patch | blob | history | |
packages/ti/sdo/edma3/rm/src/configs/edma3_tci6486_cfg.c | patch | blob | history |
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_c6472_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_c6472_cfg.c
index a7bf85350901d1e1235195501d17efb075699a7d..27d44db1dcc843c5ee59c47eb333962934335056 100644 (file)
4u, 5u, 6u, 7u,
8u, 9u, 10u, 11u,
12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u,
- 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u,
- 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
* All channels need not be mapped, some can be free also.
*/
{
- 0xFFFFFFFFu,
+ 0x0000FFFFu,
0x00000000u
}
}
@@ -236,7 +236,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* Resources owned by Region 0 */
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x0000FFFFu, 0x00000000u,
+ {0xFFFF0000u, 0x00FFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -246,7 +246,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0000003Fu},
+ {0x00FF0000u, 0x00000000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -254,7 +254,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0000003Fu},
+ {0x00FF0000u, 0x00000000u},
/* Resources reserved by Region 0 */
/* resvdPaRAMSets */
@@ -269,7 +269,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -277,14 +277,14 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
/* Resources owned by Region 1 */
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0xFFFF0000u, 0x00000000u,
+ {0x00000000u, 0xFF000000u, 0xFFFFFFFFu, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -294,7 +294,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000FC0u},
+ {0xFF000000u, 0x00000000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -302,7 +302,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000FC0u},
+ {0xFF000000u, 0x00000000u},
/* Resources reserved by Region 1 */
/* resvdPaRAMSets */
@@ -317,7 +317,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -325,7 +325,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
@@ -334,7 +334,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
/* 159 128 191 160 223 192 255 224 */
- 0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x000000FFu, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -342,7 +342,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0003F000u},
+ {0x00000000u, 0x000000FFu},
/* ownQdmaChannels */
/* 31 0 */
@@ -350,7 +350,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0003F000u},
+ {0x00000000u, 0x000000FFu},
/* Resources reserved by Region 2 */
/* resvdPaRAMSets */
@@ -365,7 +365,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -373,7 +373,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
@@ -382,7 +382,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFCu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ 0xFFFFFF00u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -390,7 +390,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00FC0000u},
+ {0x00000000u, 0x0000FF00u},
/* ownQdmaChannels */
/* 31 0 */
@@ -398,7 +398,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00FC0000u},
+ {0x00000000u, 0x0000FF00u},
/* Resources reserved by Region 3 */
/* resvdPaRAMSets */
@@ -413,7 +413,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -421,7 +421,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
@@ -430,7 +430,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0xFFFFF000u, 0x003FFFFFu, 0x00000000u,
+ 0x00000000u, 0xFFFF0000u, 0x00FFFFFFu, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -438,7 +438,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0F000000u},
+ {0x00000000u, 0x00FF0000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -446,7 +446,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0F000000u},
+ {0x00000000u, 0x00FF0000u},
/* Resources reserved by Region 4 */
/* resvdPaRAMSets */
@@ -461,7 +461,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -469,7 +469,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
@@ -478,7 +478,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0xFFC00000u, 0xFFFFFFFFu,
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -486,7 +486,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0xF0000000u},
+ {0x00000000u, 0xFF000000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -494,7 +494,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0xF0000000u},
+ {0x00000000u, 0xFF000000u},
/* Resources reserved by Region 5 */
/* resvdPaRAMSets */
@@ -509,7 +509,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -517,7 +517,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6486_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6486_cfg.c
index 73dd36f8d5e54c636cfa6981e31b7188774fa6b0..fd459ab27bf5585eada8e60c3789618274258da7 100644 (file)
4u, 5u, 6u, 7u,
8u, 9u, 10u, 11u,
12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u,
- 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u,
- 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
* All channels need not be mapped, some can be free also.
*/
{
- 0xFFFFFFFFu,
+ 0x0000FFFFu,
0x00000000u
}
}
@@ -236,7 +236,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* Resources owned by Region 0 */
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x0000FFFFu, 0x00000000u,
+ {0xFFFF0000u, 0x00FFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -246,7 +246,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0000003Fu},
+ {0x00FF0000u, 0x00000000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -254,7 +254,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0000003Fu},
+ {0x00FF0000u, 0x00000000u},
/* Resources reserved by Region 0 */
/* resvdPaRAMSets */
@@ -269,7 +269,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -277,14 +277,14 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
/* Resources owned by Region 1 */
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0xFFFF0000u, 0x00000000u,
+ {0x00000000u, 0xFF000000u, 0xFFFFFFFFu, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -294,7 +294,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000FC0u},
+ {0xFF000000u, 0x00000000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -302,7 +302,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000FC0u},
+ {0xFF000000u, 0x00000000u},
/* Resources reserved by Region 1 */
/* resvdPaRAMSets */
@@ -317,7 +317,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -325,7 +325,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
@@ -334,7 +334,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
/* 159 128 191 160 223 192 255 224 */
- 0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x000000FFu, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -342,7 +342,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0003F000u},
+ {0x00000000u, 0x000000FFu},
/* ownQdmaChannels */
/* 31 0 */
@@ -350,7 +350,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0003F000u},
+ {0x00000000u, 0x000000FFu},
/* Resources reserved by Region 2 */
/* resvdPaRAMSets */
@@ -365,7 +365,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -373,7 +373,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
@@ -382,7 +382,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFCu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ 0xFFFFFF00u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -390,7 +390,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00FC0000u},
+ {0x00000000u, 0x0000FF00u},
/* ownQdmaChannels */
/* 31 0 */
@@ -398,7 +398,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00FC0000u},
+ {0x00000000u, 0x0000FF00u},
/* Resources reserved by Region 3 */
/* resvdPaRAMSets */
@@ -413,7 +413,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -421,7 +421,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
@@ -430,7 +430,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0xFFFFF000u, 0x003FFFFFu, 0x00000000u,
+ 0x00000000u, 0xFFFF0000u, 0x00FFFFFFu, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -438,7 +438,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0F000000u},
+ {0x00000000u, 0x00FF0000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -446,7 +446,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0F000000u},
+ {0x00000000u, 0x00FF0000u},
/* Resources reserved by Region 4 */
/* resvdPaRAMSets */
@@ -461,7 +461,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -469,7 +469,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{
@@ -478,7 +478,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* 31 0 63 32 95 64 127 96 */
{0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0xFFC00000u, 0xFFFFFFFFu,
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -486,7 +486,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0xF0000000u},
+ {0x00000000u, 0xFF000000u},
/* ownQdmaChannels */
/* 31 0 */
@@ -494,7 +494,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0xF0000000u},
+ {0x00000000u, 0xFF000000u},
/* Resources reserved by Region 5 */
/* resvdPaRAMSets */
@@ -509,7 +509,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -517,7 +517,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x0000FFFFu, 0x00000000u},
},
{