PRSDK-415 Address review comments
authorSinthu Raja M <x0257345@ti.com>
Mon, 26 Feb 2018 19:25:32 +0000 (00:55 +0530)
committerSinthu Raja M <x0257345@ti.com>
Mon, 26 Feb 2018 19:25:32 +0000 (00:55 +0530)
 Removed #ifdef EDMA3_RES_USER_REQ enclosures in EDMA3 driver and
 examples.
 Add API in EDMA3 examples to validate the paRAM id allocated is
 same as the requested DMA channel number.

examples/edma3_driver/src/dma_poll_test.c
examples/edma3_driver/src/main.c
packages/ti/sdo/edma3/drv/edma3_drv.h
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_am335x_cfg.c
packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_am335x_cfg.c

index b531919766b8de7e0468436901eea2bbb80554e4..fc0f037af4ed414a63c4de61ad0804fe5a0b7dc0 100644 (file)
@@ -141,12 +141,262 @@ EDMA3_DRV_Result edma3_test_poll_mode(
 
     /* Setup for Channel 1*/
     tcc = EDMA3_DRV_TCC_ANY;
-#ifdef EDMA3_RES_USER_REQ
-    chId = EDMA3_DRV_DMA_CHANNEL_USR_REQ;
-#else
     chId = EDMA3_DRV_DMA_CHANNEL_ANY;
-#endif
 
+    /* Request any DMA channel and any TCC */
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
+            (EDMA3_RM_EventQueue)0,
+            NULL, NULL);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_setSrcParams (hEdma, chId, (uint32_t)(srcBuff1),
+            EDMA3_DRV_ADDR_MODE_INCR,
+            EDMA3_DRV_W8BIT);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_setDestParams (hEdma, chId, (uint32_t)(dstBuff1),
+            EDMA3_DRV_ADDR_MODE_INCR,
+            EDMA3_DRV_W8BIT);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result =  EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        if (syncType == EDMA3_DRV_SYNC_A)
+        {
+            result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
+                BRCnt, EDMA3_DRV_SYNC_A);
+        }
+        else
+        {
+            result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
+                BRCnt, EDMA3_DRV_SYNC_AB);
+        }
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_setOptField (hEdma, chId,
+            EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+    }
+
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = EDMA3_DRV_setOptField (hEdma, chId,
+            EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+    }
+
+    /*
+    * Since the transfer is going to happen in Manual mode of EDMA3
+    * operation, we have to 'Enable the Transfer' multiple times.
+    * Number of times depends upon the Mode (A/AB Sync)
+    * and the different counts.
+    */
+    if (result == EDMA3_DRV_SOK)
+    {
+        /*Need to activate next param*/
+        if (syncType == EDMA3_DRV_SYNC_A)
+        {
+            numenabled = bcnt * ccnt;
+        }
+        else
+        {
+            /* AB Sync Transfer Mode */
+            numenabled = ccnt;
+        }
+
+
+        for (i = 0; i < numenabled; i++)
+        {
+            /*
+            * Now enable the transfer as many times as calculated above.
+            */
+            result = EDMA3_DRV_enableTransfer (hEdma, chId,
+                EDMA3_DRV_TRIG_MODE_MANUAL);
+            if (result != EDMA3_DRV_SOK)
+            {
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_enableTransfer " \
+                    "Failed, error code: %d\r\n", result);
+#endif  /* EDMA3_DRV_DEBUG */
+                break;
+            }
+
+
+            /* Wait for the Completion Bit to be SET in the IPR/IPRH register. */
+            result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc);
+            if (result != EDMA3_DRV_SOK)
+            {
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_waitAndClearTcc " \
+                    "Failed, error code: %d\r\n", result);
+#endif  /* EDMA3_DRV_DEBUG */
+                break;
+            }
+        }
+    }
+
+
+    /* Match the Source and Destination Buffers. */
+    if (EDMA3_DRV_SOK == result)
+    {
+        for (i = 0; i < (acnt*bcnt*ccnt); i++)
+        {
+            if (srcBuff1[i] != dstBuff1[i])
+            {
+                Istestpassed = 0u;
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF("edma3_test_poll_mode: Data write-read matching" \
+                    "FAILED at i = %d\r\n", i);
+#endif  /* EDMA3_DRV_DEBUG */
+                break;
+            }
+        }
+        if (i == (acnt*bcnt*ccnt))
+        {
+            Istestpassed = 1u;
+        }
+
+
+        /* Free the previously allocated channel. */
+        result = EDMA3_DRV_freeChannel (hEdma, chId);
+        if (result != EDMA3_DRV_SOK)
+        {
+#ifdef EDMA3_DRV_DEBUG
+            EDMA3_DRV_PRINTF("edma3_test_poll_mode: EDMA3_DRV_freeChannel() FAILED, " \
+                "error code: %d\r\n", result);
+#endif  /* EDMA3_DRV_DEBUG */
+        }
+    }
+
+
+    if(Istestpassed == 1u)
+    {
+#ifdef EDMA3_DRV_DEBUG
+        EDMA3_DRV_PRINTF("edma3_test_poll_mode PASSED\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+    }
+    else
+    {
+#ifdef EDMA3_DRV_DEBUG
+        EDMA3_DRV_PRINTF("edma3_test_poll_mode FAILED\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+        result = ((EDMA3_DRV_SOK == result) ?
+                    EDMA3_DATA_MISMATCH_ERROR : result);
+    }
+    return result;
+}
+
+
+/**
+*  \brief   EDMA3 mem-to-mem data copy test case with user requested paRAMId
+*           using a DMA channel.
+*           This test case doesnot rely on the callback mechanism.
+*           Instead, it Polls the IPR register to check the transfer
+*           completion status.
+*
+*  \param  edma3Instance [IN]    EDMA3 Instance number
+*  \param  acnt        [IN]      Number of bytes in an array
+*  \param  bcnt        [IN]      Number of arrays in a frame
+*  \param  ccnt        [IN]      Number of frames in a block
+*  \param  syncType    [IN]      Synchronization type (A/AB Sync)
+*
+*  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
+EDMA3_DRV_Result edma3_test_user_req_paRAMId(
+                                      EDMA3_DRV_Handle hEdma,
+                                      uint32_t edmaInstance,
+                                      uint32_t acnt,
+                                      uint32_t bcnt,
+                                      uint32_t ccnt,
+                                      EDMA3_DRV_SyncType syncType)
+{
+    EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    uint32_t chId = 0;
+    uint32_t tcc = 0;
+    int i;
+    uint32_t count;
+    uint32_t Istestpassed = 0u;
+    uint32_t numenabled = 0;
+    uint32_t BRCnt = 0;
+    int srcbidx = 0, desbidx = 0;
+    int srccidx = 0, descidx = 0;
+    uint32_t paRAMId = 0;
+
+
+    srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
+    dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
+
+    /* Initalize source and destination buffers */
+    for (count = 0u; count < (acnt*bcnt*ccnt); count++)
+    {
+        srcBuff1[count] = (int)count+5;
+        /**
+        * No need to initialize the destination buffer as it is being invalidated.
+        dstBuff1[count] = initval;
+        */
+    }
+
+#ifdef EDMA3_ENABLE_DCACHE
+    /*
+    * Note: These functions are required if the buffer is in DDR.
+    * For other cases, where buffer is NOT in DDR, user
+    * may or may not require the below functions.
+    */
+    /* Flush the Source Buffer */
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
+    }
+
+    /* Invalidate the Destination Buffer */
+    if (result == EDMA3_DRV_SOK)
+    {
+        result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
+    }
+#endif  /* EDMA3_ENABLE_DCACHE */
+
+
+    /* Set B count reload as B count. */
+    BRCnt = bcnt;
+
+    /* Setting up the SRC/DES Index */
+    srcbidx = (int)acnt;
+    desbidx = (int)acnt;
+
+    if (syncType == EDMA3_DRV_SYNC_A)
+    {
+        /* A Sync Transfer Mode */
+        srccidx = (int)acnt;
+        descidx = (int)acnt;
+    }
+    else
+    {
+        /* AB Sync Transfer Mode */
+        srccidx = ((int)acnt * (int)bcnt);
+        descidx = ((int)acnt * (int)bcnt);
+    }
+
+
+    /* Setup for Channel 1*/
+    tcc = EDMA3_DRV_TCC_ANY;
+
+    chId = EDMA3_DRV_DMA_CHANNEL_USR_REQ;
 
     /* Request any DMA channel and any TCC */
     if (result == EDMA3_DRV_SOK)
@@ -154,7 +404,7 @@ EDMA3_DRV_Result edma3_test_poll_mode(
         result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
             (EDMA3_RM_EventQueue)0,
             NULL, NULL);
-#ifdef EDMA3_RES_USER_REQ
+
         result = EDMA3_DRV_getAllocatedPARAMId(hEdma, chId, &paRAMId);
         if(result == EDMA3_DRV_SOK)
         {
@@ -165,9 +415,13 @@ EDMA3_DRV_Result edma3_test_poll_mode(
             {
                 printf("The Requested Param ID is allocated for the given Channel\n");
             }
+            else
+            {
+                printf("The Requested Param ID is not allocated as same as the DMA channel\n");
+                result = EDMA3_DATA_MISMATCH_ERROR;
+            }
             printf("\n");
         }
-#endif
     }
 
     if (result == EDMA3_DRV_SOK)
@@ -250,7 +504,7 @@ EDMA3_DRV_Result edma3_test_poll_mode(
             if (result != EDMA3_DRV_SOK)
             {
 #ifdef EDMA3_DRV_DEBUG
-                EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_enableTransfer " \
+                EDMA3_DRV_PRINTF ("edma3_test_user_req_paRAMId: EDMA3_DRV_enableTransfer " \
                     "Failed, error code: %d\r\n", result);
 #endif  /* EDMA3_DRV_DEBUG */
                 break;
@@ -262,7 +516,7 @@ EDMA3_DRV_Result edma3_test_poll_mode(
             if (result != EDMA3_DRV_SOK)
             {
 #ifdef EDMA3_DRV_DEBUG
-                EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_waitAndClearTcc " \
+                EDMA3_DRV_PRINTF ("edma3_test_user_req_paRAMId: EDMA3_DRV_waitAndClearTcc " \
                     "Failed, error code: %d\r\n", result);
 #endif  /* EDMA3_DRV_DEBUG */
                 break;
@@ -280,7 +534,7 @@ EDMA3_DRV_Result edma3_test_poll_mode(
             {
                 Istestpassed = 0u;
 #ifdef EDMA3_DRV_DEBUG
-                EDMA3_DRV_PRINTF("edma3_test_poll_mode: Data write-read matching" \
+                EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId: Data write-read matching" \
                     "FAILED at i = %d\r\n", i);
 #endif  /* EDMA3_DRV_DEBUG */
                 break;
@@ -297,7 +551,7 @@ EDMA3_DRV_Result edma3_test_poll_mode(
         if (result != EDMA3_DRV_SOK)
         {
 #ifdef EDMA3_DRV_DEBUG
-            EDMA3_DRV_PRINTF("edma3_test_poll_mode: EDMA3_DRV_freeChannel() FAILED, " \
+            EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId: EDMA3_DRV_freeChannel() FAILED, " \
                 "error code: %d\r\n", result);
 #endif  /* EDMA3_DRV_DEBUG */
         }
@@ -307,13 +561,13 @@ EDMA3_DRV_Result edma3_test_poll_mode(
     if(Istestpassed == 1u)
     {
 #ifdef EDMA3_DRV_DEBUG
-        EDMA3_DRV_PRINTF("edma3_test_poll_mode PASSED\r\n");
+        EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId PASSED\r\n");
 #endif  /* EDMA3_DRV_DEBUG */
     }
     else
     {
 #ifdef EDMA3_DRV_DEBUG
-        EDMA3_DRV_PRINTF("edma3_test_poll_mode FAILED\r\n");
+        EDMA3_DRV_PRINTF("edma3_test_user_req_paRAMId FAILED\r\n");
 #endif  /* EDMA3_DRV_DEBUG */
         result = ((EDMA3_DRV_SOK == result) ?
                     EDMA3_DATA_MISMATCH_ERROR : result);
index a8b8910756e681f6bc0cb393b9119ab6bf5e21fa..37796a698bcec45a6c773bb79dab03d476e2a152 100644 (file)
@@ -169,7 +169,9 @@ void echo()
     EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;
     uint32_t i, bypass;
     uint32_t count=0;
+    uint32_t edmaInstance = 0;
     EDMA3_DRV_Handle hEdma[MAX_NUM_EDMA_INSTANCES];
+    EDMA3_DRV_Handle hndEdma = NULL;
     Semaphore_Params semParams;
 
     memset(hEdma,0,sizeof(hEdma));
@@ -318,6 +320,51 @@ void echo()
         }
     }
 
+    /* Mapping DMA channels to corresponding paRAM Id. The user can request for 
+     * any DAM channel to map with the paRAM Id as same as the channel number
+     */
+    for (count = 0u; count < EDMA3_MAX_DMA_CH; count++)
+    {
+        sampleEdma3GblCfgParams[edmaInstance].dmaChannelPaRAMMap[count] = count;
+    }
+
+    /*EDMA3 Initialization*/
+    hndEdma = edma3init(edmaInstance, &edmaResult);
+    if (hndEdma)
+    {
+        printf("edma3init() Passed\n");
+    }
+    else
+    {
+        printf("edma3init() Failed, error code: %d\n", (int)edmaResult);
+    }
+
+    /* User request PaRAMId test */
+    if (edmaResult == EDMA3_DRV_SOK)
+    {
+        edmaResult = edma3_test_user_req_paRAMId(hndEdma, edmaInstance,
+                      MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
+    }
+
+    if (edmaResult == EDMA3_DRV_SOK)
+    {
+        printf ("edma3_test_user_req_paRAMId Passed\r\n");
+    }
+    else
+    {
+        printf ("edma3_test_user_req_paRAMId Failed\r\n");
+    }
+
+    /*EDMA3 deinitialization */
+    edmaResult = edma3deinit(edmaInstance, hndEdma);
+    if (edmaResult != EDMA3_DRV_SOK)
+    {
+        printf("edma3deinit() Failed, error code: %d\n", (int)edmaResult);
+    }
+    else
+    {
+        printf("edma3deinit() Passed\n");
+    }
     /* Start the Heart Beat Print */
     tskHeartBit();
 
index 0a3f8e9979699bd71be64ef70b9644b368e8769e..a6040c59eabbc34d01acc68295053a7bfbd8a505 100755 (executable)
@@ -3152,7 +3152,6 @@ EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap (EDMA3_DRV_Handle hEdma,
                  EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc,
                  EDMA3_DRV_xbarConfigScr configXbarScr);
 
-#ifdef EDMA3_RES_USER_REQ
 /**
  * \brief   Returns the PARAM ID recently allocated for an EDMA channel
  *
@@ -3179,7 +3178,6 @@ EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap (EDMA3_DRV_Handle hEdma,
  */
 EDMA3_DRV_Result EDMA3_DRV_getAllocatedPARAMId(EDMA3_DRV_Handle hEdma,
                  uint32_t channelId, uint32_t *paRAMId);
-#endif
 
 
                                                 
index 459b97f2cc6129361e564764b4c25f71745b11c0..8f6683c2ce80c9613937c0de4f478a847e1c9018 100644 (file)
@@ -362,18 +362,6 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
      * \brief Mapping from each DMA channel to a Parameter RAM set,
      * if it exists, otherwise of no use.
      */
-#ifdef EDMA3_RES_USER_REQ
-        {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
-        },
-#else
         {
         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
@@ -408,7 +396,6 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP
         },
-#endif
 
      /**
       * \brief Mapping from each DMA channel to a TCC. This specific
index 96d9bb0937171e132a25c729d354c4c26b3e9b17..a88a73fa5df8758cec7c0eb53165df0a7412d6bf 100755 (executable)
@@ -2264,8 +2264,6 @@ EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
     return result;
     }
 
-#ifdef EDMA3_RES_USER_REQ
-/*Only for Testing purpose*/
 /** Return the Param ID recently allocated for an EDMA request*/
 EDMA3_DRV_Result EDMA3_DRV_getAllocatedPARAMId(EDMA3_DRV_Handle hEdma,
                                 uint32_t channelId, uint32_t *paRAMId)
@@ -2296,7 +2294,6 @@ EDMA3_DRV_Result EDMA3_DRV_getAllocatedPARAMId(EDMA3_DRV_Handle hEdma,
 
        return result;
 }
-#endif
 
 /* Definitions of Local functions - Start */
 /** Remove various mappings and do cleanup for DMA/QDMA channels */
index b810963dad49a5a266439bb6ae7b83612585a9fd..3fdf93632e70c9303b994328283358613e823517 100644 (file)
@@ -362,18 +362,6 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
      * \brief Mapping from each DMA channel to a Parameter RAM set,
      * if it exists, otherwise of no use.
      */
-#ifdef EDMA3_RES_USER_REQ
-        {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
-        },
-#else
         {
         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
@@ -408,7 +396,6 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
         },
-#endif
 
      /**
       * \brief Mapping from each DMA channel to a TCC. This specific
@@ -502,16 +489,6 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM
           {
             /* Resources owned by Region 1 */
             /* ownPaRAMSets */
-#ifdef EDMA3_RES_USER_REQ
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
-            /* 159  128     191  160     223  192     255  224 */
-            0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-#else
             /* 31     0     63    32     95    64     127   96 */
             {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
             /* 159  128     191  160     223  192     255  224 */
@@ -520,7 +497,6 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM
              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
             /* 415  384     447  416     479  448     511  480 */
              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-#endif
 
             /* ownDmaChannels */
             /* 31     0     63    32 */