summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: ad08ccf)
raw | patch | inline | side by side (parent: ad08ccf)
| author | U-ENT\x0153534 <x0153534@BD-HWAPPSPC07.india.ti.com> | |
| Wed, 6 Apr 2011 13:35:08 +0000 (19:05 +0530) | ||
| committer | Prasad Konnur <x0153534@palin02.india.ti.com> | |
| Mon, 16 May 2011 13:05:08 +0000 (18:35 +0530) |
25 files changed:
diff --git a/examples/edma3_driver/evmTI816x_ARM/makefile b/examples/edma3_driver/evmTI816x_ARM/makefile
--- /dev/null
@@ -0,0 +1,37 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_arm_ti816x_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_m3vpss = edma3_lld_drv edma3_lld_rm
+COMP_LIST_m3video = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_m3vpss = rtsc_config/edma3_drv_bios6_ti816x_m3vpss_st_sample.cfg
+XDC_CFG_FILE_m3video = rtsc_config/edma3_drv_bios6_ti816x_m3video_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+ dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \
+ qdma_link_test.c
+CFLAGS_LOCAL_COMMON =
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.ccsproject b/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.ccsproject
--- /dev/null
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.TMS470.GenericARM9Device"/>
+<deviceEndianness value="little"/>
+<codegenToolVersion value="4.6.1"/>
+<linkerCommandFile value=""/>
+<rts value="libc.a"/>
+<defaultAssemblyOnly value="false"/>
+<isElfFormat value="true"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.cdtbuild b/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.cdtbuild
--- /dev/null
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma_drv_bios6_arm_ti816x_st_sample_configuration.com.ti.ccstudio.buildDefinitions.TMS470.ProjectType.331799526" name="ARM" projectType="com.ti.ccstudio.buildDefinitions.TMS470.ProjectType">
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" id="com.ti.ccstudio.buildDefinitions.TMS470.Default.1173147605" name="Default" parent="com.ti.ccstudio.buildDefinitions.TMS470.Default">
+<toolChain id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.DebugToolchain.1466041174" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.1395223190">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1301736440" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="4.6.3" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.222490533" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.TMS470.GenericCortexA8Device"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="IS_ELF=true"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.1"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.20.02.59"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.30.02.42;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.1395223190" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR.1008605599" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET.1585495188" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET" value="ti.targets.arm.elf.A8F" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM.63469973" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM" value="ti.platforms.generic:DucatiPlatform_Core1" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE.276741146" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE" value="whole_program_debug" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR.1093021954" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH.1553744672" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+</option>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.cdtproject b/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.cdtproject
--- /dev/null
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.rtsc.xdctools.buildDefinitions.XDC.XDCROOT_CONTAINER"/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+<pathentry kind="con" path="com.ti.ccstudio.managedbuild.core.CCS_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.project b/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.project
--- /dev/null
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma_drv_bios6_arm_ti816x_st_sample_configuration</name>
+ <comment></comment>
+ <projects>
+ <project>ti.sdo.edma3.drv</project>
+ <project>ti.sdo.edma3.drv.sample</project>
+ <project>ti.sdo.edma3.rm</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature</nature>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>com.ti.ccstudio.managedbuild.core.ccsNature</nature>
+ </natures>
+</projectDescription>
diff --git a/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Thu Aug 13 11:05:45 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/evmTI816x_ARM/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,28 @@
+#Mon Jan 24 19:41:13 IST 2011
+com.ti.ccstudio.buildDefinitions.C6000.Default.1041023276/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1041023276/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.1164666266/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1164666266/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.1800299584/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1800299584/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.1879506303/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1879506303/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.31004543/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.31004543/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.359282260/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.359282260/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.497143829/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.497143829/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.507384710/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.507384710/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.TMS470.Default.1173147605/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.TMS470.Default.1173147605/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.TMS470.Default.1406052921/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.TMS470.Default.1406052921/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.TMS470.Default.1497482439/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.TMS470.Default.1497482439/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.TMS470.Default.2019945117/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.TMS470.Default.2019945117/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.TMS470.Default.1173147605=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/evmTI816x_ARM/rtsc_config/AmmuCfg.cfg b/examples/edma3_driver/evmTI816x_ARM/rtsc_config/AmmuCfg.cfg
--- /dev/null
@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2009, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * ======== DucatiAmmu.cfg ========
+ *
+ * An example configuration script used by both the server and client
+ * applications running on either Bios6 or Linux.
+ */
+function init()
+{
+
+var Program = xdc.useModule('xdc.cfg.Program');
+{
+ var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+
+
+ var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+ Cache.enableCache = true;
+
+
+ /*********************** Small Pages *************************/
+ /* smallPages[0] & smallPages[1] are auto-programmed by h/w */
+ /* Overwrite smallPage[1] so that 16K is covered. H/w reset value configures
+ * only 4K */
+ AMMU.smallPages[0].pageEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[0].logicalAddress = 0x00000000;
+ AMMU.smallPages[0].translatedAddress = 0x55020000;
+ AMMU.smallPages[0].translationEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[0].size = AMMU.Small_16K;
+ AMMU.smallPages[0].volatileQualifier = AMMU.Volatile_FOLLOW;
+ AMMU.smallPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+
+ /* Overwrite smallPage[1] so that 16K is covered. H/w reset value configures
+ * only 4K */
+ AMMU.smallPages[1].pageEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[1].logicalAddress = 0x40000000;
+ AMMU.smallPages[1].translatedAddress = 0x55080000;
+ AMMU.smallPages[1].translationEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[1].size = AMMU.Small_16K;
+ AMMU.smallPages[1].volatileQualifier = AMMU.Volatile_FOLLOW;
+
+/*
+ AMMU.smallPages[2].pageEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[2].logicalAddress = 0x00004000;
+ AMMU.smallPages[2].translatedAddress = 0x55024000;
+ AMMU.smallPages[2].translationEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[2].size = AMMU.Small_16K;
+ AMMU.smallPages[2].volatileQualifier = AMMU.Volatile_FOLLOW;
+ AMMU.smallPages[2].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.smallPages[2].L1_posted = AMMU.PostedPolicy_POSTED;
+
+ AMMU.smallPages[3].pageEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[3].logicalAddress = 0x00008000;
+ AMMU.smallPages[3].translatedAddress = 0x55028000;
+ AMMU.smallPages[3].translationEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[3].size = AMMU.Small_16K;
+ AMMU.smallPages[3].volatileQualifier = AMMU.Volatile_FOLLOW;
+ AMMU.smallPages[3].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.smallPages[3].L1_posted = AMMU.PostedPolicy_POSTED;
+
+ AMMU.smallPages[4].pageEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[4].logicalAddress = 0x0000C000;
+ AMMU.smallPages[4].translatedAddress = 0x5502C000;
+ AMMU.smallPages[4].translationEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[4].size = AMMU.Small_16K;
+ AMMU.smallPages[4].volatileQualifier = AMMU.Volatile_FOLLOW;
+ AMMU.smallPages[4].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.smallPages[4].L1_posted = AMMU.PostedPolicy_POSTED;
+
+ AMMU.smallPages[5].pageEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[5].logicalAddress = 0x00010000;
+ AMMU.smallPages[5].translatedAddress = 0x55030000;
+ AMMU.smallPages[5].translationEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[5].size = AMMU.Small_16K;
+ AMMU.smallPages[5].volatileQualifier = AMMU.Volatile_FOLLOW;
+ AMMU.smallPages[5].endianism = AMMU.Endianism_BIG;
+ AMMU.smallPages[5].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.smallPages[5].L1_posted = AMMU.PostedPolicy_POSTED;
+
+ AMMU.smallPages[6].pageEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[6].logicalAddress = 0x00014000;
+ AMMU.smallPages[6].translatedAddress = 0x55034000;
+ AMMU.smallPages[6].translationEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[6].size = AMMU.Small_16K;
+ AMMU.smallPages[6].volatileQualifier = AMMU.Volatile_FOLLOW;
+ AMMU.smallPages[6].endianism = AMMU.Endianism_BIG;
+ AMMU.smallPages[6].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.smallPages[6].L1_posted = AMMU.PostedPolicy_POSTED;
+
+ AMMU.smallPages[7].pageEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[7].logicalAddress = 0x00018000;
+ AMMU.smallPages[7].translatedAddress = 0x55038000;
+ AMMU.smallPages[7].translationEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[7].size = AMMU.Small_16K;
+ AMMU.smallPages[7].volatileQualifier = AMMU.Volatile_FOLLOW;
+ AMMU.smallPages[7].endianism = AMMU.Endianism_BIG;
+ AMMU.smallPages[7].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.smallPages[7].L1_posted = AMMU.PostedPolicy_POSTED;
+
+ AMMU.smallPages[8].pageEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[8].logicalAddress = 0x0001C000;
+ AMMU.smallPages[8].translatedAddress = 0x5503C000;
+ AMMU.smallPages[8].translationEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[8].size = AMMU.Small_16K;
+ AMMU.smallPages[8].volatileQualifier = AMMU.Volatile_FOLLOW;
+ AMMU.smallPages[8].endianism = AMMU.Endianism_BIG;
+ AMMU.smallPages[8].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.smallPages[8].L1_posted = AMMU.PostedPolicy_POSTED;
+
+ AMMU.smallPages[9].pageEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[9].logicalAddress = 0x00020000;
+ AMMU.smallPages[9].translatedAddress = 0x55040000;
+ AMMU.smallPages[9].translationEnabled = AMMU.Enable_YES;
+ AMMU.smallPages[9].size = AMMU.Small_16K;
+ AMMU.smallPages[9].volatileQualifier = AMMU.Volatile_FOLLOW;
+ AMMU.smallPages[9].endianism = AMMU.Endianism_BIG;
+ AMMU.smallPages[9].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.smallPages[9].L1_posted = AMMU.PostedPolicy_POSTED;
+*/
+
+ /*********************** Medium Pages *************************/
+ /* L2 space is mapped to virtual address 0 */
+ /* config medium page[0] to map 256K VA 0x00000000 to PA 0x55020000 - L2 SRAM */
+ /* Make it L1 cacheable */
+ AMMU.mediumPages[0].pageEnabled = AMMU.Enable_YES;
+ AMMU.mediumPages[0].logicalAddress = 0x00300000;
+ AMMU.mediumPages[0].translatedAddress = 0x40300000;
+ AMMU.mediumPages[0].translationEnabled = AMMU.Enable_YES;
+ AMMU.mediumPages[0].size = AMMU.Medium_256K;
+ AMMU.mediumPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+ AMMU.mediumPages[0].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+ AMMU.mediumPages[0].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
+ AMMU.mediumPages[0].L1_posted = AMMU.PostedPolicy_POSTED;
+
+
+ AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
+ AMMU.mediumPages[1].logicalAddress = 0x00400000;
+ AMMU.mediumPages[1].translatedAddress = 0x40400000;
+ AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
+ AMMU.mediumPages[1].size = AMMU.Medium_256K;
+ AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+ AMMU.mediumPages[1].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+ AMMU.mediumPages[1].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
+ AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_POSTED;
+
+
+ /*********************** Large Pages *************************/
+ /* Instruction Code: Large page (512M); cacheable */
+ AMMU.largePages[0].pageEnabled = AMMU.Enable_YES;
+ AMMU.largePages[0].logicalAddress = 0x60000000;
+ AMMU.largePages[0].translationEnabled = AMMU.Enable_NO;
+ AMMU.largePages[0].size = AMMU.Large_512M;
+ AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_NON_POSTED;
+ AMMU.largePages[0].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.largePages[0].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+
+
+ /* config large page[0] to map 512MB VA 0x40000000 to Config space */
+ AMMU.largePages[1].pageEnabled = AMMU.Enable_YES;
+ AMMU.largePages[1].logicalAddress = 0x40000000;
+ AMMU.largePages[1].translationEnabled = AMMU.Enable_NO;
+ AMMU.largePages[1].size = AMMU.Large_512M;
+ AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
+ AMMU.largePages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.largePages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+
+
+ /* V_M3/D_M3 code and data regions */
+ /* config large page[1] to map 512MB VA 0x80000000 to DDR 0x80000000 - Non cached */
+ AMMU.largePages[2].pageEnabled = AMMU.Enable_YES;
+ AMMU.largePages[2].logicalAddress = 0x80000000;
+ AMMU.largePages[2].translationEnabled = AMMU.Enable_NO;
+ AMMU.largePages[2].size = AMMU.Large_512M;
+ AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+ AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_POSTED;
+ AMMU.largePages[2].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.largePages[2].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+
+
+ AMMU.largePages[3].pageEnabled = AMMU.Enable_YES;
+ AMMU.largePages[3].logicalAddress = 0xA0000000;
+ AMMU.largePages[3].translationEnabled = AMMU.Enable_NO;
+ AMMU.largePages[3].size = AMMU.Large_512M;
+ AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.largePages[3].L1_posted = AMMU.PostedPolicy_POSTED;
+ AMMU.largePages[3].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+ AMMU.largePages[3].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+
+ var GateDualCore = xdc.useModule ('ti.sysbios.family.arm.ducati.GateDualCore');
+ GateDualCore.initGates = true;
+}
+}
\ No newline at end of file
diff --git a/examples/edma3_driver/evmTI816x_ARM/rtsc_config/edma3_drv_bios6_ti816x_m3video_st_sample.cfg b/examples/edma3_driver/evmTI816x_ARM/rtsc_config/edma3_drv_bios6_ti816x_m3video_st_sample.cfg
--- /dev/null
@@ -0,0 +1,41 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Log = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
+var Error = xdc.useModule('xdc.runtime.Error');
+var HwiM3 = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+var Program = xdc.useModule("xdc.cfg.Program");
+
+
+/* ISR/SWI stack */
+Program.stack = 0x4000;
+
+/* Heap used when creating semaphore's, TSK's or malloc() ... */
+Program.heap = 0x15000;
+
+/* enable print of exception handing info */
+HwiM3.enableException = true;
+
+/* DSP/BIOS expects this to set to 1 */
+var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.id = 0;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+/* MMU/Cache related configurations */
+
+var Cache1 = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+var Mmu = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+var AmmuCfg = xdc.loadCapsule("AmmuCfg.cfg");
+AmmuCfg.init();
+
+Program.sectMap[".my_sect_ddr"] = "DDR3_RAM";
+
+/* Enable the cache */
+Cache1.enableCache = true;
diff --git a/examples/edma3_driver/evmTI816x_ARM/rtsc_config/edma3_drv_bios6_ti816x_m3vpss_st_sample.cfg b/examples/edma3_driver/evmTI816x_ARM/rtsc_config/edma3_drv_bios6_ti816x_m3vpss_st_sample.cfg
--- /dev/null
@@ -0,0 +1,41 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Log = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
+var Error = xdc.useModule('xdc.runtime.Error');
+var HwiM3 = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+var Program = xdc.useModule("xdc.cfg.Program");
+
+
+/* ISR/SWI stack */
+Program.stack = 0x4000;
+
+/* Heap used when creating semaphore's, TSK's or malloc() ... */
+Program.heap = 0x15000;
+
+/* enable print of exception handing info */
+HwiM3.enableException = true;
+
+/* DSP/BIOS expects this to set to 1 */
+var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.id = 1;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+/* MMU/Cache related configurations */
+
+var Cache1 = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+var Mmu = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+var AmmuCfg = xdc.loadCapsule("AmmuCfg.cfg");
+AmmuCfg.init();
+
+Program.sectMap[".my_sect_ddr"] = "DDR3_RAM";
+
+/* Enable the cache */
+Cache1.enableCache = true;
diff --git a/examples/edma3_driver/evmTI816x_ARM/sample_app/.ccsproject b/examples/edma3_driver/evmTI816x_ARM/sample_app/.ccsproject
--- /dev/null
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.TMS470.GenericARM9Device"/>
+<deviceEndianness value="little"/>
+<codegenToolVersion value="4.6.1"/>
+<linkerCommandFile value=""/>
+<rts value="libc.a"/>
+<defaultAssemblyOnly value="false"/>
+<isElfFormat value="true"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evmTI816x_ARM/sample_app/.cdtbuild b/examples/edma3_driver/evmTI816x_ARM/sample_app/.cdtbuild
--- /dev/null
@@ -0,0 +1,130 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma_drv_bios6_arm_ti816x_st_sample.com.ti.ccstudio.buildDefinitions.TMS470.ProjectType.353412728" name="ARM" projectType="com.ti.ccstudio.buildDefinitions.TMS470.ProjectType">
+<configuration artifactExtension="out" artifactName="edma_drv_bios6_arm_ti816x_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.TMS470.Debug.2132888941" name="Debug" parent="com.ti.ccstudio.buildDefinitions.TMS470.Debug">
+<toolChain id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.DebugToolchain.1575627220" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.linkerDebug.1143113299">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1381501379" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="4.6.3" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1244753765" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.TMS470.GenericCortexA8Device"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="IS_ELF=true"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.1"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.compilerDebug.974544162" name="TMS470 Compiler" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.compilerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.SILICON_VERSION.1402922879" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.SILICON_VERSION" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.SILICON_VERSION.7A8" valueType="enumerated"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.INCLUDE_PATH.1845904153" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.INCLUDE_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.DIAG_WARNING.1681046940" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.DIAG_WARNING" valueType="stringList">
+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.LITTLE_ENDIAN.252470806" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.LITTLE_ENDIAN" value="true" valueType="boolean"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ABI.553333823" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ABI" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ABI.eabi" valueType="enumerated"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.CODE_STATE.879414083" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.CODE_STATE" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.CODE_STATE.32" valueType="enumerated"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ENUM_TYPE.1186648609" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ENUM_TYPE" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ENUM_TYPE.packed" valueType="enumerated"/>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.linkerDebug.1143113299" name="TMS470 Linker" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.linkerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.OUTPUT_FILE.1408637372" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.OUTPUT_FILE" value=""edma_drv_bios6_arm_ti816x_st_sample.out"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.MAP_FILE.149978193" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.MAP_FILE" value=""edma_drv_bios6_arm_ti816x_st_sample.map"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.SEARCH_PATH.2107647116" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.LIBRARY.499207234" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value=""libc.a""/>
+</option>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="out" artifactName="edma_drv_bios6_arm_ti816x_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.TMS470.Release.2011776262" name="Release" parent="com.ti.ccstudio.buildDefinitions.TMS470.Release">
+<toolChain id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.ReleaseToolchain.1618434348" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.ReleaseToolchain" targetTool="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.linkerRelease.2001454963">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.728690361" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="4.6.3" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1370211143" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.TMS470.GenericCortexA8Device"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="IS_ELF=true"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.1"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.compilerRelease.499705605" name="TMS470 Compiler" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.compilerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.SILICON_VERSION.1433894781" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.SILICON_VERSION" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.SILICON_VERSION.7A8" valueType="enumerated"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.INCLUDE_PATH.1603401981" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.INCLUDE_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.DIAG_WARNING.479475999" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.DIAG_WARNING" valueType="stringList">
+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.LITTLE_ENDIAN.1336831558" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.LITTLE_ENDIAN" value="true" valueType="boolean"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ABI.747170383" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ABI" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ABI.eabi" valueType="enumerated"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.CODE_STATE.16610505" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.CODE_STATE" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.CODE_STATE.32" valueType="enumerated"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ENUM_TYPE.217773197" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ENUM_TYPE" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ENUM_TYPE.packed" valueType="enumerated"/>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.linkerRelease.2001454963" name="TMS470 Linker" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.linkerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.OUTPUT_FILE.1693387231" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.OUTPUT_FILE" value=""edma_drv_bios6_arm_ti816x_st_sample.out"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.MAP_FILE.295794237" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.MAP_FILE" value=""edma_drv_bios6_arm_ti816x_st_sample.map"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.SEARCH_PATH.1838721817" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.LIBRARY.293160107" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value=""libc.a""/>
+</option>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="out" artifactName="edma_drv_bios6_arm_ti816x_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.TMS470.Debug.266155286" name="ARM-DEBUG" parent="com.ti.ccstudio.buildDefinitions.TMS470.Debug">
+<toolChain id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.DebugToolchain.27795009" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.linkerDebug.157597064">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1777656317" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="4.6.3" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.772582471" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.TMS470.GenericCortexA8Device"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="IS_ELF=true"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.1"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.compilerDebug.1358150459" name="TMS470 Compiler" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.compilerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.SILICON_VERSION.842615345" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.SILICON_VERSION" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.SILICON_VERSION.7A8" valueType="enumerated"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.INCLUDE_PATH.858171937" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.INCLUDE_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.DIAG_WARNING.1223514291" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.DIAG_WARNING" valueType="stringList">
+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.LITTLE_ENDIAN.599328452" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.LITTLE_ENDIAN" value="true" valueType="boolean"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ABI.1826966522" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ABI" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ABI.eabi" valueType="enumerated"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.CODE_STATE.1720886422" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.CODE_STATE" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.CODE_STATE.32" valueType="enumerated"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ENUM_TYPE.1714887203" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ENUM_TYPE" value="com.ti.ccstudio.buildDefinitions.TMS470_4.6.compilerID.ENUM_TYPE.packed" valueType="enumerated"/>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.linkerDebug.157597064" name="TMS470 Linker" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.exe.linkerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.OUTPUT_FILE.1125844531" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.OUTPUT_FILE" value=""edma_drv_bios6_arm_ti816x_st_sample.out"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.MAP_FILE.1923289830" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.MAP_FILE" value=""edma_drv_bios6_arm_ti816x_st_sample.map"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.generatedLinkerCommandFiles.851277363" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.generatedLinkerCommandFiles" valueType="libs">
+<listOptionValue builtIn="false" value=""$(GEN_CMDS_QUOTED)""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.SEARCH_PATH.570056910" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.LIBRARY.848676481" superClass="com.ti.ccstudio.buildDefinitions.TMS470_4.6.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value=""libc.a""/>
+</option>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/evmTI816x_ARM/sample_app/.cdtproject b/examples/edma3_driver/evmTI816x_ARM/sample_app/.cdtproject
--- /dev/null
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+<pathentry kind="con" path="com.ti.ccstudio.managedbuild.core.CCS_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/evmTI816x_ARM/sample_app/.project b/examples/edma3_driver/evmTI816x_ARM/sample_app/.project
--- /dev/null
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma_drv_bios6_arm_ti816x_st_sample</name>
+ <comment></comment>
+ <projects>
+ <project>edma_drv_bios6_arm_ti816x_st_sample_configuration</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>com.ti.ccstudio.managedbuild.core.ccsNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>dma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_poll_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>
+ </link>
+ <link>
+ <name>main.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>
+ </link>
+ <link>
+ <name>dma_misc_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_ping_pong_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>common.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>
+ </link>
+ <link>
+ <name>dma_chain_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/examples/edma3_driver/evmTI816x_ARM/sample_app/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evmTI816x_ARM/sample_app/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Thu Aug 13 11:05:45 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/evmTI816x_ARM/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evmTI816x_ARM/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/evmTI816x_ARM/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,34 @@
+#Mon Jan 24 19:45:03 IST 2011
+com.ti.ccstudio.buildDefinitions.C6000.Default.1041023276/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1041023276/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.1164666266/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1164666266/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.1800299584/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1800299584/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.1879506303/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1879506303/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.31004543/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.31004543/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.359282260/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.359282260/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.497143829/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.497143829/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.507384710/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.507384710/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.TMS470.Debug.1514122377/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.TMS470.Debug.1514122377/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.TMS470.Debug.2132888941/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.TMS470.Debug.2132888941/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.TMS470.Debug.266155286/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.TMS470.Debug.266155286/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.TMS470.Debug.382821947/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.TMS470.Debug.382821947/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.TMS470.Release.1103754139/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.TMS470.Release.1103754139/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.TMS470.Release.2011776262/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.TMS470.Release.2011776262/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.TMS470.Debug.2132888941=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.TMS470.Debug.266155286=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.TMS470.Release.2011776262=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/evmTI816x_ARM/sample_app/linker.cmd b/examples/edma3_driver/evmTI816x_ARM/sample_app/linker.cmd
--- /dev/null
@@ -0,0 +1,5 @@
+SECTIONS
+{
+ .my_sect_iram > DDR3_RAM
+ .my_sect_ddr > DDR3_RAM
+}
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3video_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3video_cfg.c
--- /dev/null
@@ -0,0 +1,762 @@
+/*
+ * sample_dm740_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+#if 0
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+#endif
+ return 4;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ return (addr); /* The address is already a global address */
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ (void) dspNum;
+
+ return 0;
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET (512u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC (64u)
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE (4u)
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC (4u)
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT (62)
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT (46u)
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT (0u)
+#define EDMA3_TC1_ERROR_INT (0u)
+#define EDMA3_TC2_ERROR_INT (0u)
+#define EDMA3_TC3_ERROR_INT (0u)
+#define EDMA3_TC4_ERROR_INT (0u)
+#define EDMA3_TC5_ERROR_INT (0u)
+#define EDMA3_TC6_ERROR_INT (0u)
+#define EDMA3_TC7_ERROR_INT (0u)
+
+/**
+* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+* ECM events (SoC specific). These ECM events come
+* under ECM block XXX (handling those specific ECM events). Normally, block
+* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+* is mapped to a specific HWI_INT YYY in the tcf file.
+* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+* to transfer completion interrupt.
+* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+* to CC error interrupts.
+* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+* to TC error interrupts.
+*/
+#define EDMA3_HWI_INT_XFER_COMP (7u)
+#define EDMA3_HWI_INT_CC_ERR (11u)
+#define EDMA3_HWI_INT_TC_ERR (11u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+ /* 31 0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFFFFFFF0u)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+ /* 63 32 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x3C7FFFFFu)
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+ EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
+ {
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+ }
+ };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+
+
+/* Driver Object Initialization Configuration */
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 6u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x49000000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x49800000u,
+ (void *)0x49900000u,
+ (void *)0x49A00000u,
+ (void *)0x49B00000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ EDMA3_CC_XFER_COMPLETION_INT,
+ /** Interrupt no. for CC Error */
+ EDMA3_CC_ERROR_INT,
+ /** Interrupt no. for TCs Error */
+ {
+ EDMA3_TC0_ERROR_INT,
+ EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT,
+ EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT,
+ EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT,
+ EDMA3_TC7_ERROR_INT
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u,
+ 4u, 5u, 6u, 7u,
+ 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u,
+ 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u,
+ 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u,
+ 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u,
+ 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u,
+ 60u, 61u, 62u, 63u
+ },
+
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ },
+ },
+ };
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+
+ /* Resources reserved by Region 0 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 1 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 2 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 3 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 4 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 5 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
+
+
+
+/* End of File */
+
+
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3video_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3video_int_reg.c
--- /dev/null
@@ -0,0 +1,203 @@
+/*
+ * sample_dm740_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+// #include <stdio.h>
+/**
+ * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+ * (Not all TC error ISRs need to be registered, register only for the
+ * available Transfer Controllers).
+ */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp;
+extern unsigned int hwIntCcErr;
+extern unsigned int hwIntTcErr;
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+//unsigned int gpp_num = 4;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/** To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ unsigned int numTc = 0;
+ Hwi_Params hwiParams;
+ Error_Block eb;
+
+ /* Initialize the Error Block */
+ Error_init(&eb);
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ //hwiParams.priority = hwIntXferComp;
+ //hwiParams.enableInt = TRUE;
+
+ hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
+ (&lisrEdma3ComplHandler0),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+
+
+ #if 0
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ hwiParams.priority = hwIntCcErr;
+ //hwiParams.enableInt = TRUE;
+
+ hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+ (&lisrEdma3CCErrHandler0),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ hwiParams.priority = hwIntTcErr;
+ //hwiParams.enableInt = TRUE;
+
+ hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+ (ptrEdma3TcIsrHandler[numTc]),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+ numTc++;
+ }
+ /**
+ * Enabling the HWI_ID.
+ * EDMA3 interrupts (transfer completion, CC error etc.)
+ * correspond to different ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+ * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+ * API C64_enableIER(), in which the YYY bit is SET.
+ */
+ Hwi_enableInterrupt(ccErrorInt[edma3Id]);
+ Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
+ numTc = 0;
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
+ numTc++;
+ }
+
+ #endif
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ unsigned int numTc = 0;
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ Hwi_delete(&hwiCCXferCompInt);
+ Hwi_delete(&hwiCCErrInt);
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ Hwi_delete(&hwiTCErrInt[numTc]);
+ numTc++;
+ }
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3vpss_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3vpss_cfg.c
--- /dev/null
@@ -0,0 +1,762 @@
+/*
+ * sample_dm740_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+#if 0
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+#endif
+ return 5;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ return (addr); /* The address is already a global address */
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ (void) dspNum;
+
+ return 0;
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET (512u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC (64u)
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE (4u)
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC (4u)
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT (63)
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT (46u)
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT (0u)
+#define EDMA3_TC1_ERROR_INT (0u)
+#define EDMA3_TC2_ERROR_INT (0u)
+#define EDMA3_TC3_ERROR_INT (0u)
+#define EDMA3_TC4_ERROR_INT (0u)
+#define EDMA3_TC5_ERROR_INT (0u)
+#define EDMA3_TC6_ERROR_INT (0u)
+#define EDMA3_TC7_ERROR_INT (0u)
+
+/**
+* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+* ECM events (SoC specific). These ECM events come
+* under ECM block XXX (handling those specific ECM events). Normally, block
+* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+* is mapped to a specific HWI_INT YYY in the tcf file.
+* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+* to transfer completion interrupt.
+* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+* to CC error interrupts.
+* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+* to TC error interrupts.
+*/
+#define EDMA3_HWI_INT_XFER_COMP (7u)
+#define EDMA3_HWI_INT_CC_ERR (11u)
+#define EDMA3_HWI_INT_TC_ERR (11u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+ /* 31 0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFFFFFFF0u)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+ /* 63 32 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x3C7FFFFFu)
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+ EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
+ {
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+ }
+ };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+
+
+/* Driver Object Initialization Configuration */
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 6u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x49000000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x49800000u,
+ (void *)0x49900000u,
+ (void *)0x49A00000u,
+ (void *)0x49B00000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ EDMA3_CC_XFER_COMPLETION_INT,
+ /** Interrupt no. for CC Error */
+ EDMA3_CC_ERROR_INT,
+ /** Interrupt no. for TCs Error */
+ {
+ EDMA3_TC0_ERROR_INT,
+ EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT,
+ EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT,
+ EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT,
+ EDMA3_TC7_ERROR_INT
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u,
+ 4u, 5u, 6u, 7u,
+ 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u,
+ 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u,
+ 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u,
+ 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u,
+ 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u,
+ 60u, 61u, 62u, 63u
+ },
+
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ },
+ },
+ };
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+
+ /* Resources reserved by Region 0 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 1 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 2 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 3 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 4 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 5 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
+
+
+
+/* End of File */
+
+
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3vpss_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3vpss_int_reg.c
--- /dev/null
@@ -0,0 +1,203 @@
+/*
+ * sample_dm740_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+// #include <stdio.h>
+/**
+ * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+ * (Not all TC error ISRs need to be registered, register only for the
+ * available Transfer Controllers).
+ */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp;
+extern unsigned int hwIntCcErr;
+extern unsigned int hwIntTcErr;
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+//unsigned int gpp_num = 4;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/** To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ unsigned int numTc = 0;
+ Hwi_Params hwiParams;
+ Error_Block eb;
+
+ /* Initialize the Error Block */
+ Error_init(&eb);
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ //hwiParams.priority = hwIntXferComp;
+ //hwiParams.enableInt = TRUE;
+
+ hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
+ (&lisrEdma3ComplHandler0),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+
+
+ #if 0
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ hwiParams.priority = hwIntCcErr;
+ //hwiParams.enableInt = TRUE;
+
+ hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+ (&lisrEdma3CCErrHandler0),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ hwiParams.priority = hwIntTcErr;
+ //hwiParams.enableInt = TRUE;
+
+ hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+ (ptrEdma3TcIsrHandler[numTc]),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+ numTc++;
+ }
+ /**
+ * Enabling the HWI_ID.
+ * EDMA3 interrupts (transfer completion, CC error etc.)
+ * correspond to different ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+ * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+ * API C64_enableIER(), in which the YYY bit is SET.
+ */
+ Hwi_enableInterrupt(ccErrorInt[edma3Id]);
+ Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
+ numTc = 0;
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
+ numTc++;
+ }
+
+ #endif
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ unsigned int numTc = 0;
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ Hwi_delete(&hwiCCXferCompInt);
+ Hwi_delete(&hwiCCErrInt);
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ Hwi_delete(&hwiTCErrInt[numTc]);
+ numTc++;
+ }
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti816x_m3video_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti816x_m3video_cfg.c
--- /dev/null
@@ -0,0 +1,762 @@
+/*
+ * sample_dm740_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+#if 0
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+#endif
+ return 4;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ return (addr); /* The address is already a global address */
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ (void) dspNum;
+
+ return 0;
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET (512u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC (64u)
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE (4u)
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC (4u)
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT (62)
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT (46u)
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT (0u)
+#define EDMA3_TC1_ERROR_INT (0u)
+#define EDMA3_TC2_ERROR_INT (0u)
+#define EDMA3_TC3_ERROR_INT (0u)
+#define EDMA3_TC4_ERROR_INT (0u)
+#define EDMA3_TC5_ERROR_INT (0u)
+#define EDMA3_TC6_ERROR_INT (0u)
+#define EDMA3_TC7_ERROR_INT (0u)
+
+/**
+* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+* ECM events (SoC specific). These ECM events come
+* under ECM block XXX (handling those specific ECM events). Normally, block
+* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+* is mapped to a specific HWI_INT YYY in the tcf file.
+* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+* to transfer completion interrupt.
+* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+* to CC error interrupts.
+* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+* to TC error interrupts.
+*/
+#define EDMA3_HWI_INT_XFER_COMP (7u)
+#define EDMA3_HWI_INT_CC_ERR (11u)
+#define EDMA3_HWI_INT_TC_ERR (11u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_rm_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_rm_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+ /* 31 0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFFFFFFF0u)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_rm_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_rm_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+ /* 63 32 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x3C7FFFFFu)
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+ EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
+ {
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+ }
+ };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 5u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x49000000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x49800000u,
+ (void *)0x49900000u,
+ (void *)0x49A00000u,
+ (void *)0x49B00000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ EDMA3_CC_XFER_COMPLETION_INT,
+ /** Interrupt no. for CC Error */
+ EDMA3_CC_ERROR_INT,
+ /** Interrupt no. for TCs Error */
+ {
+ EDMA3_TC0_ERROR_INT,
+ EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT,
+ EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT,
+ EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT,
+ EDMA3_TC7_ERROR_INT
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u,
+ 4u, 5u, 6u, 7u,
+ 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u,
+ 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u,
+ 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u,
+ 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u,
+ 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u,
+ 60u, 61u, 62u, 63u
+ },
+
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ },
+ },
+ };
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+
+ /* Resources reserved by Region 0 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 1 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 2 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 3 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 4 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 5 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
+
+
+
+/* End of File */
+
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti816x_m3video_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti816x_m3video_int_reg.c
--- /dev/null
@@ -0,0 +1,204 @@
+/*
+ * sample_dm740_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+// #include <stdio.h>
+/**
+ * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+ * (Not all TC error ISRs need to be registered, register only for the
+ * available Transfer Controllers).
+ */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp;
+extern unsigned int hwIntCcErr;
+extern unsigned int hwIntTcErr;
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+//unsigned int gpp_num = 4;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/** To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ unsigned int numTc = 0;
+ Hwi_Params hwiParams;
+ Error_Block eb;
+
+ /* Initialize the Error Block */
+ Error_init(&eb);
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ hwiParams.priority = hwIntXferComp;
+ //hwiParams.enableInt = TRUE;
+
+ hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
+ (&lisrEdma3ComplHandler0),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+
+ #if 0
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ hwiParams.priority = hwIntCcErr;
+ //hwiParams.enableInt = TRUE;
+
+ hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+ (&lisrEdma3CCErrHandler0),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ hwiParams.priority = hwIntTcErr;
+ //hwiParams.enableInt = TRUE;
+
+ hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+ (ptrEdma3TcIsrHandler[numTc]),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+ numTc++;
+ }
+ /**
+ * Enabling the HWI_ID.
+ * EDMA3 interrupts (transfer completion, CC error etc.)
+ * correspond to different ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+ * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+ * API C64_enableIER(), in which the YYY bit is SET.
+ */
+ Hwi_enableInterrupt(ccErrorInt[edma3Id]);
+#if 0
+ Hwi_enableInterrupt(13);
+#endif
+ Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
+ numTc = 0;
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
+ numTc++;
+ }
+ #endif
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ unsigned int numTc = 0;
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ Hwi_delete(&hwiCCXferCompInt);
+ Hwi_delete(&hwiCCErrInt);
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ Hwi_delete(&hwiTCErrInt[numTc]);
+ numTc++;
+ }
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti816x_m3vpss_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti816x_m3vpss_cfg.c
--- /dev/null
@@ -0,0 +1,762 @@
+/*
+ * sample_dm740_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+#if 0
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+#endif
+ return 4;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ return (addr); /* The address is already a global address */
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ (void) dspNum;
+
+ return 0;
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET (512u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC (64u)
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE (4u)
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC (4u)
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT (63)
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT (46u)
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT (0u)
+#define EDMA3_TC1_ERROR_INT (0u)
+#define EDMA3_TC2_ERROR_INT (0u)
+#define EDMA3_TC3_ERROR_INT (0u)
+#define EDMA3_TC4_ERROR_INT (0u)
+#define EDMA3_TC5_ERROR_INT (0u)
+#define EDMA3_TC6_ERROR_INT (0u)
+#define EDMA3_TC7_ERROR_INT (0u)
+
+/**
+* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+* ECM events (SoC specific). These ECM events come
+* under ECM block XXX (handling those specific ECM events). Normally, block
+* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+* is mapped to a specific HWI_INT YYY in the tcf file.
+* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+* to transfer completion interrupt.
+* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+* to CC error interrupts.
+* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+* to TC error interrupts.
+*/
+#define EDMA3_HWI_INT_XFER_COMP (7u)
+#define EDMA3_HWI_INT_CC_ERR (11u)
+#define EDMA3_HWI_INT_TC_ERR (11u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_rm_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_rm_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+ /* 31 0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFFFFFFF0u)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_rm_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_rm_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+ /* 63 32 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x3C7FFFFFu)
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+ EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
+ {
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+ }
+ };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 5u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x49000000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x49800000u,
+ (void *)0x49900000u,
+ (void *)0x49A00000u,
+ (void *)0x49B00000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ EDMA3_CC_XFER_COMPLETION_INT,
+ /** Interrupt no. for CC Error */
+ EDMA3_CC_ERROR_INT,
+ /** Interrupt no. for TCs Error */
+ {
+ EDMA3_TC0_ERROR_INT,
+ EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT,
+ EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT,
+ EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT,
+ EDMA3_TC7_ERROR_INT
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u,
+ 4u, 5u, 6u, 7u,
+ 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u,
+ 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u,
+ 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u,
+ 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u,
+ 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u,
+ 60u, 61u, 62u, 63u
+ },
+
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ },
+ },
+ };
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+
+ /* Resources reserved by Region 0 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 1 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 2 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 3 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 4 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* Resources reserved by Region 5 */
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
+
+
+
+/* End of File */
+
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti816x_m3vpss_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti816x_m3vpss_int_reg.c
--- /dev/null
@@ -0,0 +1,204 @@
+/*
+ * sample_dm740_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+// #include <stdio.h>
+/**
+ * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+ * (Not all TC error ISRs need to be registered, register only for the
+ * available Transfer Controllers).
+ */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp;
+extern unsigned int hwIntCcErr;
+extern unsigned int hwIntTcErr;
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+//unsigned int gpp_num = 4;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/** To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ unsigned int numTc = 0;
+ Hwi_Params hwiParams;
+ Error_Block eb;
+
+ /* Initialize the Error Block */
+ Error_init(&eb);
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ hwiParams.priority = hwIntXferComp;
+ //hwiParams.enableInt = TRUE;
+
+ hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
+ (&lisrEdma3ComplHandler0),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+
+ #if 0
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ hwiParams.priority = hwIntCcErr;
+ //hwiParams.enableInt = TRUE;
+
+ hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+ (&lisrEdma3CCErrHandler0),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ /* Initialize the HWI parameters with user specified values */
+ Hwi_Params_init(&hwiParams);
+ /* argument for the ISR */
+ hwiParams.arg = edma3Id;
+ /* set the priority ID */
+ hwiParams.priority = hwIntTcErr;
+ //hwiParams.enableInt = TRUE;
+
+ hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+ (ptrEdma3TcIsrHandler[numTc]),
+ (const Hwi_Params *) (&hwiParams),
+ &eb);
+ if (TRUE == Error_check(&eb))
+ {
+ System_printf("HWI Create Failed\n",Error_getCode(&eb));
+ }
+ numTc++;
+ }
+ /**
+ * Enabling the HWI_ID.
+ * EDMA3 interrupts (transfer completion, CC error etc.)
+ * correspond to different ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+ * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+ * API C64_enableIER(), in which the YYY bit is SET.
+ */
+ Hwi_enableInterrupt(ccErrorInt[edma3Id]);
+#if 0
+ Hwi_enableInterrupt(13);
+#endif
+ Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
+ numTc = 0;
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
+ numTc++;
+ }
+ #endif
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ unsigned int numTc = 0;
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ Hwi_delete(&hwiCCXferCompInt);
+ Hwi_delete(&hwiCCErrInt);
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ Hwi_delete(&hwiTCErrInt[numTc]);
+ numTc++;
+ }
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+