Misra C Fixes: TI814x Platform Files
authorSunil MS <x0190988@ti.com>
Wed, 15 Oct 2014 06:06:17 +0000 (11:36 +0530)
committerSunil MS <x0190988@ti.com>
Thu, 16 Oct 2014 05:03:16 +0000 (10:33 +0530)
MISRA.BUILTIN_NUMERIC
MISRA.LITERAL.UNSIGNED.SUFFIX

Change-Id: Iedfa43a373e4e76913b580a769611b13b5fae0da
Signed-off-by: Sunil MS <x0190988@ti.com>
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_int_reg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_int_reg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_int_reg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_int_reg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_int_reg.c
packages/ti/sdo/edma3/rm/src/configs/edma3_ti814x_cfg.c

index ba4c7b922804d4f07e98e9f33cb8ee0e5a70001f..e49a4b622701c0461492f4123852719766a1a698 100755 (executable)
@@ -60,22 +60,22 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[];
+extern uint32_t hwIntCcErr[];
+extern uint32_t hwIntTcErr[];
 
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
 /* This variable has to be used as an extern */
-unsigned int gpp_num = 0;
+uint32_t gpp_num = 0;
 
 Hwi_Handle hwiCCXferCompInt;
 Hwi_Handle hwiCCErrInt;
@@ -96,46 +96,46 @@ typedef struct  {
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003FU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
 
 
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)
-#define EDMA3_NUM_TCC                     (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95U)
+#define EDMA3_NUM_TCC                     (64U)
 
 /*
  * Forward decleration
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum);
 
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
 
 /**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
     {
     static UInt32 cookie = 0;
 #ifdef BUILD_CENTAURUS_A8
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 #endif
     Hwi_Params hwiParams; 
     Error_Block      eb;
@@ -227,11 +227,11 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     }
 
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
        static UInt32 cookie = 0;
 #ifdef BUILD_CENTAURUS_A8
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 #endif /* BUILD_CENTAURUS_A8 */
 
     /* Disabling the global interrupts */
@@ -260,13 +260,13 @@ void unregisterEdma3Interrupts (unsigned int edma3Id)
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
+    uint32_t xbarEvtNum = 0;
+    int32_t          edmaChanNum = 0;
 
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
                (chanNum != NULL) &&
@@ -292,13 +292,13 @@ EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
+    uint32_t scrChanOffset = 0;
+    uint32_t scrRegOffset  = 0;
+    uint32_t xBarEvtNum    = 0;
     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);
 
 
@@ -343,7 +343,7 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
        }
 
 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
-                                   unsigned int edma3Id)
+                                   uint32_t edma3Id)
     {
     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
@@ -359,7 +359,7 @@ EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
     return retVal;
     }
 
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
     {
     printf("memory Protection error");
     }
index 3f73ff449c78eb54379dc8c0cd63e255988bf0e1..49a4471012ee7bc667e4b0085346cf12f41511f4 100755 (executable)
 #include <ti/sdo/edma3/drv/edma3_drv.h>
 
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         1u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+#define NUM_EDMA3_INSTANCES         1U
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 /* Number of DSPs present in the system */
-#define NUM_DSPS                    1u
-const unsigned int numDsps = NUM_DSPS;
+#define NUM_DSPS                    1U
+const uint32_t numDsps = NUM_DSPS;
 
 /* Determine the processor id by reading DNUM register. */
-unsigned short determineProcId()
+uint16_t determineProcId()
 {
 #ifdef BUILD_CENTAURUS_A8
        return 0;
@@ -64,11 +64,11 @@ unsigned short determineProcId()
 #endif
 }
 
-signed char*  getGlobalAddr(signed char* addr)
+int8_t*  getGlobalAddr(int8_t* addr)
 {
      return (addr); /* The address is already a global address */
 }
-unsigned short isGblConfigRequired(unsigned int dspNum)
+uint16_t isGblConfigRequired(uint32_t dspNum)
 {
     (void) dspNum;
 #ifdef BUILD_CENTAURUS_DSP
@@ -82,32 +82,32 @@ unsigned short isGblConfigRequired(unsigned int dspNum)
 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 
 /** Number of PaRAM Sets available                                            */
-#define EDMA3_NUM_PARAMSET                              (512u)
+#define EDMA3_NUM_PARAMSET                              (512U)
 
 /** Number of TCCS available                                                  */
-#define EDMA3_NUM_TCC                                   (64u)
+#define EDMA3_NUM_TCC                                   (64U)
 
 /** Number of DMA Channels available                                          */
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+#define EDMA3_NUM_DMA_CHANNELS                          (64U)
 
 /** Number of QDMA Channels available                                         */
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+#define EDMA3_NUM_QDMA_CHANNELS                         (8U)
 
 /** Number of Event Queues available                                          */
-#define EDMA3_NUM_EVTQUE                              (4u)
+#define EDMA3_NUM_EVTQUE                              (4U)
 
 /** Number of Transfer Controllers available                                  */
-#define EDMA3_NUM_TC                                  (4u)
+#define EDMA3_NUM_TC                                  (4U)
 
 /** Number of Regions                                                         */
-#define EDMA3_NUM_REGIONS                             (6u)
+#define EDMA3_NUM_REGIONS                             (6U)
 
 
 /** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT_A8                 (12u)
-#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (20u)
-#define EDMA3_CC_XFER_COMPLETION_INT_M3VPSS             (63u)
-#define EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO            (62u)
+#define EDMA3_CC_XFER_COMPLETION_INT_A8                 (12U)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (20U)
+#define EDMA3_CC_XFER_COMPLETION_INT_M3VPSS             (63U)
+#define EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO            (62U)
 
 #ifdef BUILD_CENTAURUS_A8
 #define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A8
@@ -118,30 +118,30 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #elif defined BUILD_CENTAURUS_M3VPSS
 #define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_M3VPSS
 #else
-#define EDMA3_CC_XFER_COMPLETION_INT                    {0u}
+#define EDMA3_CC_XFER_COMPLETION_INT                    {0U}
 #endif
 
 /** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT_A8                           (14u)
-#define EDMA3_CC_ERROR_INT_DSP                          (21u)
+#define EDMA3_CC_ERROR_INT_A8                           (14U)
+#define EDMA3_CC_ERROR_INT_DSP                          (21U)
 
 #ifdef BUILD_CENTAURUS_A8
 #define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A8
 #elif defined BUILD_CENTAURUS_DSP
 #define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP
 #else
-#define EDMA3_CC_ERROR_INT                              (0u)
+#define EDMA3_CC_ERROR_INT                              (0U)
 #endif
 
 /** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT_DSP                         (22u)
-#define EDMA3_TC1_ERROR_INT_DSP                         (27u)
-#define EDMA3_TC2_ERROR_INT_DSP                         (28u)
-#define EDMA3_TC3_ERROR_INT_DSP                         (29u)
-#define EDMA3_TC0_ERROR_INT_A8                          (112u)
-#define EDMA3_TC1_ERROR_INT_A8                          (113u)
-#define EDMA3_TC2_ERROR_INT_A8                          (114u)
-#define EDMA3_TC3_ERROR_INT_A8                          (115u)
+#define EDMA3_TC0_ERROR_INT_DSP                         (22U)
+#define EDMA3_TC1_ERROR_INT_DSP                         (27U)
+#define EDMA3_TC2_ERROR_INT_DSP                         (28U)
+#define EDMA3_TC3_ERROR_INT_DSP                         (29U)
+#define EDMA3_TC0_ERROR_INT_A8                          (112U)
+#define EDMA3_TC1_ERROR_INT_A8                          (113U)
+#define EDMA3_TC2_ERROR_INT_A8                          (114U)
+#define EDMA3_TC3_ERROR_INT_A8                          (115U)
 
 #ifdef BUILD_CENTAURUS_A8
 #define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A8
@@ -154,16 +154,16 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_TC2_ERROR_INT                             EDMA3_TC2_ERROR_INT_DSP
 #define EDMA3_TC3_ERROR_INT                             EDMA3_TC3_ERROR_INT_DSP
 #else
-#define EDMA3_TC0_ERROR_INT                             (0u)
-#define EDMA3_TC1_ERROR_INT                             (0u)
-#define EDMA3_TC2_ERROR_INT                             (0u)
-#define EDMA3_TC3_ERROR_INT                             (0u)
+#define EDMA3_TC0_ERROR_INT                             (0U)
+#define EDMA3_TC1_ERROR_INT                             (0U)
+#define EDMA3_TC2_ERROR_INT                             (0U)
+#define EDMA3_TC3_ERROR_INT                             (0U)
 #endif
 
-#define EDMA3_TC4_ERROR_INT                             (0u)
-#define EDMA3_TC5_ERROR_INT                             (0u)
-#define EDMA3_TC6_ERROR_INT                             (0u)
-#define EDMA3_TC7_ERROR_INT                             (0u)
+#define EDMA3_TC4_ERROR_INT                             (0U)
+#define EDMA3_TC5_ERROR_INT                             (0U)
+#define EDMA3_TC6_ERROR_INT                             (0U)
+#define EDMA3_TC7_ERROR_INT                             (0U)
 
 /**
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
@@ -181,12 +181,12 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  */
 /* EDMA 0 */
 
-#define EDMA3_HWI_INT_XFER_COMP                           (7u)
-#define EDMA3_HWI_INT_CC_ERR                              (7u)
-#define EDMA3_HWI_INT_TC0_ERR                             (10u)
-#define EDMA3_HWI_INT_TC1_ERR                             (10u)
-#define EDMA3_HWI_INT_TC2_ERR                             (10u)
-#define EDMA3_HWI_INT_TC3_ERR                             (10u)
+#define EDMA3_HWI_INT_XFER_COMP                           (7U)
+#define EDMA3_HWI_INT_CC_ERR                              (7U)
+#define EDMA3_HWI_INT_TC0_ERR                             (10U)
+#define EDMA3_HWI_INT_TC1_ERR                             (10U)
+#define EDMA3_HWI_INT_TC2_ERR                             (10U)
+#define EDMA3_HWI_INT_TC3_ERR                             (10U)
 
 
 /**
@@ -204,7 +204,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                       /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F0Cu)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F0CU)  /* TBD */
 
 
 /**
@@ -222,16 +222,16 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
 /* DMA channels 32-63 DOES NOT exist in omapl138. */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF003C00u) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF003C00U) /* TBD */
 
 
 /* Variable which will be used internally for referring number of Event Queues*/
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
                                                         EDMA3_NUM_EVTQUE,
                                                     };
 
 /* Variable which will be used internally for referring number of TCs.        */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
                                                     EDMA3_NUM_TC,
                                                 };
 
@@ -239,11 +239,11 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
  * Variable which will be used internally for referring transfer completion
  * interrupt.
  */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     {
-        EDMA3_CC_XFER_COMPLETION_INT_A8, EDMA3_CC_XFER_COMPLETION_INT_DSP, 0u, 0u,
-        EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO, EDMA3_CC_XFER_COMPLETION_INT_M3VPSS, 0u, 0u,
+        EDMA3_CC_XFER_COMPLETION_INT_A8, EDMA3_CC_XFER_COMPLETION_INT_DSP, 0U, 0U,
+        EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO, EDMA3_CC_XFER_COMPLETION_INT_M3VPSS, 0U, 0U,
     },
 };
 
@@ -251,7 +251,7 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
  * Variable which will be used internally for referring channel controller's
  * error interrupt.
  */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {
                                                     EDMA3_CC_ERROR_INT,
                                                };
 
@@ -259,7 +259,7 @@ unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
  * Variable which will be used internally for referring transfer controllers'
  * error interrupts.
  */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][8] =
 {
    {
        EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
@@ -273,15 +273,15 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] = {
                                                     EDMA3_HWI_INT_XFER_COMP
                                                   };
 
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] = {
                                                    EDMA3_HWI_INT_CC_ERR
                                                };
 
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
                                                      {
                                                         EDMA3_HWI_INT_TC0_ERR,
                                                         EDMA3_HWI_INT_TC1_ERR,
@@ -334,10 +334,10 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,
          * PaRAM entry n corresponds to channel n.
          */
-        1u,
+        1U,
 
         /** Existence of memory protection feature */
-        0u,
+        0U,
 
         /** Global Register Region of CC Registers */
         EDMA3_CC_BASE_ADDR,
@@ -378,14 +378,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)
          */
         {
-            0u,
-            1u,
-            2u,
-            3u,
-            0u,
-            0u,
-            0u,
-            0u
+            0U,
+            1U,
+            2U,
+            3U,
+            0U,
+            0U,
+            0U,
+            0U
         },
         /**
          * \brief To Configure the Threshold level of number of events
@@ -396,14 +396,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).
          */
         {
-            16u,
-            16u,
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U
         },
 
         /**
@@ -413,14 +413,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.
          */
             {
-            16u,
-            16u,
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U
             },
 
         /**
@@ -428,14 +428,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * if it exists, otherwise of no use.
          */
             {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
+            8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
+            16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,
+            24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,
+            32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U
+            40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,
+            48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,
+            56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U
             },
 
          /**
@@ -444,22 +444,22 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
           * on the mapped channel.
           */
             {
-            0u, 1u, 2u, 3u,
-            4u, 5u, 6u, 7u,
-            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u,
-            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            24u, 25u, 26u, 27u,
-            28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
+            0U, 1U, 2U, 3U,
+            4U, 5U, 6U, 7U,
+            8U, 9U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12U, 13U, 14U, 15U,
+            16U, 17U, 18U, 19U,
+            20U, 21U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24U, 25U, 26U, 27U,
+            28U, 29U, 30U, 31U,
+            32U, 33U, 34U, 35U,
+            36U, 37U, 38U, 39U,
+            40U, 41U, 42U, 43U,
+            44U, 45U, 46U, 47U,
+            48U, 49U, 50U, 51U,
+            52U, 53U, 54U, 55U,
+            56U, 57U, 58U, 59U,
+            60U, 61U, 62U, 63U
             },
 
         /**
@@ -486,61 +486,61 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
  
 /* Defines for Own DMA channels For different cores */
 /* channels  0 to 31 */
-#define EDMA3_OWN_DMA_CHANNELS_0_A8    (0xFFFFFFFFu)
-#define EDMA3_OWN_DMA_CHANNELS_0_DSP   (0xFFFFFFFFu)
-#define EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO    (0xFFFFFFFFu)
-#define EDMA3_OWN_DMA_CHANNELS_0_M3VPSS    (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_0_A8    (0xFFFFFFFFU)
+#define EDMA3_OWN_DMA_CHANNELS_0_DSP   (0xFFFFFFFFU)
+#define EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO    (0xFFFFFFFFU)
+#define EDMA3_OWN_DMA_CHANNELS_0_M3VPSS    (0xFFFFFFFFU)
 /* Channels 32 to 63 */
-#define EDMA3_OWN_DMA_CHANNELS_1_A8    (0xFFFFFFFFu)
-#define EDMA3_OWN_DMA_CHANNELS_1_DSP   (0xFFFFFFFFu)
-#define EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO    (0xFFFFFFFFu)
-#define EDMA3_OWN_DMA_CHANNELS_1_M3VPSS    (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_1_A8    (0xFFFFFFFFU)
+#define EDMA3_OWN_DMA_CHANNELS_1_DSP   (0xFFFFFFFFU)
+#define EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO    (0xFFFFFFFFU)
+#define EDMA3_OWN_DMA_CHANNELS_1_M3VPSS    (0xFFFFFFFFU)
 
 /* Defines for Own QDMA channels For different cores */
-#define EDMA3_OWN_QDMA_CHANNELS_0_A8    (0x000000FFu)
-#define EDMA3_OWN_QDMA_CHANNELS_0_DSP   (0x000000FFu)
-#define EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO    (0x000000FFu)
-#define EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS    (0x000000FFu)
+#define EDMA3_OWN_QDMA_CHANNELS_0_A8    (0x000000FFU)
+#define EDMA3_OWN_QDMA_CHANNELS_0_DSP   (0x000000FFU)
+#define EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO    (0x000000FFU)
+#define EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS    (0x000000FFU)
 
 /* Defines for Own TCCs For different cores */
-#define EDMA3_OWN_TCC_0_A8    (0xFFFFFFFFu)
-#define EDMA3_OWN_TCC_0_DSP   (0xFFFFFFFFu)
-#define EDMA3_OWN_TCC_0_M3VIDEO    (0xFFFFFFFFu)
-#define EDMA3_OWN_TCC_0_M3VPSS    (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_0_A8    (0xFFFFFFFFU)
+#define EDMA3_OWN_TCC_0_DSP   (0xFFFFFFFFU)
+#define EDMA3_OWN_TCC_0_M3VIDEO    (0xFFFFFFFFU)
+#define EDMA3_OWN_TCC_0_M3VPSS    (0xFFFFFFFFU)
 /* Channels 32 to 63 */
-#define EDMA3_OWN_TCC_1_A8    (0xFFFFFFFFu)
-#define EDMA3_OWN_TCC_1_DSP   (0xFFFFFFFFu)
-#define EDMA3_OWN_TCC_1_M3VIDEO    (0xFFFFFFFFu)
-#define EDMA3_OWN_TCC_1_M3VPSS    (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_1_A8    (0xFFFFFFFFU)
+#define EDMA3_OWN_TCC_1_DSP   (0xFFFFFFFFU)
+#define EDMA3_OWN_TCC_1_M3VIDEO    (0xFFFFFFFFU)
+#define EDMA3_OWN_TCC_1_M3VPSS    (0xFFFFFFFFU)
 
 /* Defines for Reserved DMA channels For different cores */
 /* channels  0 to 31 */
 #define EDMA3_RESERVED_DMA_CHANNELS_0_A8    (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
 #define EDMA3_RESERVED_DMA_CHANNELS_0_DSP   (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
-#define EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO    (0x00u)
-#define EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS    (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO    (0x00U)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS    (0x00U)
 /* Channels 32 to 63 */
 #define EDMA3_RESERVED_DMA_CHANNELS_1_A8    (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
 #define EDMA3_RESERVED_DMA_CHANNELS_1_DSP   (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
-#define EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO    (0x00u)
-#define EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS    (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO    (0x00U)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS    (0x00U)
 
 /* Defines for RESERVED QDMA channels For different cores */
-#define EDMA3_RESERVED_QDMA_CHANNELS_0_A8    (0x00u)
-#define EDMA3_RESERVED_QDMA_CHANNELS_0_DSP   (0x00u)
-#define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO    (0x00u)
-#define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS    (0x00u)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_A8    (0x00U)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_DSP   (0x00U)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO    (0x00U)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS    (0x00U)
 
 /* Defines for RESERVED TCCs For different cores */
 #define EDMA3_RESERVED_TCC_0_A8    (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
 #define EDMA3_RESERVED_TCC_0_DSP   (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
-#define EDMA3_RESERVED_TCC_0_M3VIDEO    (0x00u)
-#define EDMA3_RESERVED_TCC_0_M3VPSS    (0x00u)
+#define EDMA3_RESERVED_TCC_0_M3VIDEO    (0x00U)
+#define EDMA3_RESERVED_TCC_0_M3VPSS    (0x00U)
 /* Channels 32 to 63 */
 #define EDMA3_RESERVED_TCC_1_A8    (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
 #define EDMA3_RESERVED_TCC_1_DSP   (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
-#define EDMA3_RESERVED_TCC_1_M3VIDEO    (0x00u)
-#define EDMA3_RESERVED_TCC_1_M3VPSS    (0x00u)
+#define EDMA3_RESERVED_TCC_1_M3VIDEO    (0x00U)
+#define EDMA3_RESERVED_TCC_1_M3VPSS    (0x00U)
 
 /* Driver Instance Initialization Configuration */
 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
@@ -551,13 +551,13 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
@@ -573,13 +573,13 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -598,13 +598,13 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                    {
                        /* ownPaRAMSets */
                        /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                        /* ownDmaChannels */
                        /* 31     0     63    32 */
@@ -620,13 +620,13 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                        /* resvdPaRAMSets */
                        /* 31     0     63    32     95    64     127   96 */
-                       {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                       {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                        /* 159  128     191  160     223  192     255  224 */
-                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                        0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                        /* 287  256     319  288     351  320     383  352 */
-                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                        0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                        /* 415  384     447  416     479  448     511  480 */
-                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                        0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                        /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -645,107 +645,107 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 4 (Configuration for Centaurus M3VIDEO Core)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
@@ -761,13 +761,13 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -786,13 +786,13 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
@@ -808,13 +808,13 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -833,94 +833,94 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
            },
     };
index 78048fcde75687b20c14dac91b06a48af77220dc..14273a5757bf0fa40e67c448644169a1f9b05be2 100755 (executable)
@@ -47,7 +47,7 @@
   * (Not all TC error ISRs need to be registered, register only for the
   * available Transfer Controllers).
   */
-void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 {
                                                 &lisrEdma3TC0ErrHandler0,
                                                 &lisrEdma3TC1ErrHandler0,
@@ -59,20 +59,20 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
                                                 &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[];
+extern uint32_t hwIntCcErr[];
+extern uint32_t hwIntTcErr[];
 
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
 
 /* External Instance Specific Configuration Structure */
 extern EDMA3_DRV_GblXbarToChanConfigParams 
@@ -89,44 +89,44 @@ typedef struct  {
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003FU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
 
 
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (94u)
-#define EDMA3_NUM_TCC                     (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (94U)
+#define EDMA3_NUM_TCC                     (64U)
 
 /*
  * Forward decleration
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum);
 
 
 /**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
     {
     static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
@@ -173,10 +173,10 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     }
 
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
        static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
@@ -206,13 +206,13 @@ void unregisterEdma3Interrupts (unsigned int edma3Id)
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
+    uint32_t xbarEvtNum = 0;
+    int32_t          edmaChanNum = 0;
 
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
                (chanNum != NULL) &&
@@ -238,13 +238,13 @@ EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
+    uint32_t scrChanOffset = 0;
+    uint32_t scrRegOffset  = 0;
+    uint32_t xBarEvtNum    = 0;
     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x08140F00);
 
 
@@ -289,7 +289,7 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
        }
 
 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
-                                   unsigned int edma3Id)
+                                   uint32_t edma3Id)
     {
     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
index 28b6b169c56e04c77af5c36a23a6ff6d0a8815e3..9c76005e3d75e4d5bbb985c2029d381e709408f2 100755 (executable)
 #include <ti/sdo/edma3/rm/edma3_rm.h>
 
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         1u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+#define NUM_EDMA3_INSTANCES         1U
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 /* Number of DSPs present in the system */
-#define NUM_DSPS                    0u
-const unsigned int numDsps = NUM_DSPS;
+#define NUM_DSPS                    0U
+const uint32_t numDsps = NUM_DSPS;
 
 /* Determine the processor id by reading DNUM register. */
-unsigned short determineProcId()
+uint16_t determineProcId()
 {
     return 0;
 }
 
-signed char*  getGlobalAddr(signed char* addr)
+int8_t*  getGlobalAddr(int8_t* addr)
 {
      return (addr); /* The address is already a global address */
 }
-unsigned short isGblConfigRequired(unsigned int dspNum)
+uint16_t isGblConfigRequired(uint32_t dspNum)
 {
     (void) dspNum;
     return 0;
@@ -68,40 +68,40 @@ unsigned short isGblConfigRequired(unsigned int dspNum)
 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 
 /** Number of PaRAM Sets available                                            */
-#define EDMA3_NUM_PARAMSET                              (512u)
+#define EDMA3_NUM_PARAMSET                              (512U)
 
 /** Number of TCCS available                                                  */
-#define EDMA3_NUM_TCC                                   (64u)
+#define EDMA3_NUM_TCC                                   (64U)
 
 /** Number of DMA Channels available                                          */
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+#define EDMA3_NUM_DMA_CHANNELS                          (64U)
 
 /** Number of QDMA Channels available                                         */
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+#define EDMA3_NUM_QDMA_CHANNELS                         (8U)
 
 /** Number of Event Queues available                                          */
-#define EDMA3_0_NUM_EVTQUE                              (4u)
+#define EDMA3_0_NUM_EVTQUE                              (4U)
 
 /** Number of Transfer Controllers available                                  */
-#define EDMA3_0_NUM_TC                                  (4u)
+#define EDMA3_0_NUM_TC                                  (4U)
 
 /** Number of Regions                                                         */
-#define EDMA3_0_NUM_REGIONS                             (4u)
+#define EDMA3_0_NUM_REGIONS                             (4U)
 
 
 /** Interrupt no. for Transfer Completion                                     */
-#define EDMA3_0_CC_XFER_COMPLETION_INT                  (12u)
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (12U)
 /** Interrupt no. for CC Error                                                */
-#define EDMA3_0_CC_ERROR_INT                            (14u)
+#define EDMA3_0_CC_ERROR_INT                            (14U)
 /** Interrupt no. for TCs Error                                               */
-#define EDMA3_0_TC0_ERROR_INT                           (112u)
-#define EDMA3_0_TC1_ERROR_INT                           (113u)
-#define EDMA3_0_TC2_ERROR_INT                           (114u)
-#define EDMA3_0_TC3_ERROR_INT                           (115u)
-#define EDMA3_0_TC4_ERROR_INT                           (0u)
-#define EDMA3_0_TC5_ERROR_INT                           (0u)
-#define EDMA3_0_TC6_ERROR_INT                           (0u)
-#define EDMA3_0_TC7_ERROR_INT                           (0u)
+#define EDMA3_0_TC0_ERROR_INT                           (112U)
+#define EDMA3_0_TC1_ERROR_INT                           (113U)
+#define EDMA3_0_TC2_ERROR_INT                           (114U)
+#define EDMA3_0_TC3_ERROR_INT                           (115U)
+#define EDMA3_0_TC4_ERROR_INT                           (0U)
+#define EDMA3_0_TC5_ERROR_INT                           (0U)
+#define EDMA3_0_TC6_ERROR_INT                           (0U)
+#define EDMA3_0_TC7_ERROR_INT                           (0U)
 
 /**
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
@@ -119,12 +119,12 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  */
 /* EDMA 0 */
 
-#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
-#define EDMA3_0_HWI_INT_CC_ERR                              (7u)
-#define EDMA3_0_HWI_INT_TC0_ERR                             (10u)
-#define EDMA3_0_HWI_INT_TC1_ERR                             (10u)
-#define EDMA3_0_HWI_INT_TC2_ERR                             (10u)
-#define EDMA3_0_HWI_INT_TC3_ERR                             (10u)
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7U)
+#define EDMA3_0_HWI_INT_CC_ERR                              (7U)
+#define EDMA3_0_HWI_INT_TC0_ERR                             (10U)
+#define EDMA3_0_HWI_INT_TC1_ERR                             (10U)
+#define EDMA3_0_HWI_INT_TC2_ERR                             (10U)
+#define EDMA3_0_HWI_INT_TC3_ERR                             (10U)
 
 
 /**
@@ -142,7 +142,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                       /* 31     0 */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F00u)  /* TBD */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F00U)  /* TBD */
 
 
 /**
@@ -160,16 +160,16 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
 /* DMA channels 32-63 DOES NOT exist in omapl138. */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF003C00u) /* TBD */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF003C00U) /* TBD */
 
 
 /* Variable which will be used internally for referring number of Event Queues*/
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
                                                         EDMA3_0_NUM_EVTQUE,
                                                     };
 
 /* Variable which will be used internally for referring number of TCs.        */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
                                                     EDMA3_0_NUM_TC,
                                                 };
 
@@ -177,10 +177,10 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
  * Variable which will be used internally for referring transfer completion
  * interrupt.
  */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     {
-        EDMA3_0_CC_XFER_COMPLETION_INT, 0, 0u, 0u, 0u, 0u, 0u, 0u,
+        EDMA3_0_CC_XFER_COMPLETION_INT, 0, 0U, 0U, 0U, 0U, 0U, 0U,
     },
 };
 
@@ -188,7 +188,7 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
  * Variable which will be used internally for referring channel controller's
  * error interrupt.
  */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {
                                                     EDMA3_0_CC_ERROR_INT,
                                                };
 
@@ -196,7 +196,7 @@ unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
  * Variable which will be used internally for referring transfer controllers'
  * error interrupts.
  */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][8] =
 {
    {
        EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
@@ -210,15 +210,15 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] = {
                                                     EDMA3_0_HWI_INT_XFER_COMP
                                                   };
 
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] = {
                                                    EDMA3_0_HWI_INT_CC_ERR
                                                };
 
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
                                                      {
                                                         EDMA3_0_HWI_INT_TC0_ERR,
                                                         EDMA3_0_HWI_INT_TC1_ERR,
@@ -253,19 +253,19 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,
          * PaRAM entry n corresponds to channel n.
          */
-        1u,
+        1U,
 
         /** Existence of memory protection feature */
-        0u,
+        0U,
 
         /** Global Register Region of CC Registers */
-        (void *)0x49000000u,
+        (void *)0x49000000U,
         /** Transfer Controller (TC) Registers */
         {
-            (void *)0x49800000u,
-            (void *)0x49900000u,
-            (void *)0x49A00000u,
-            (void *)0x49B00000u,
+            (void *)0x49800000U,
+            (void *)0x49900000U,
+            (void *)0x49A00000U,
+            (void *)0x49B00000U,
             (void *)NULL,
             (void *)NULL,
             (void *)NULL,
@@ -297,14 +297,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)
          */
         {
-            0u,
-            1u,
-            2u,
-            3u,
-            0u,
-            0u,
-            0u,
-            0u
+            0U,
+            1U,
+            2U,
+            3U,
+            0U,
+            0U,
+            0U,
+            0U
         },
         /**
          * \brief To Configure the Threshold level of number of events
@@ -315,14 +315,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).
          */
         {
-            16u,
-            16u,
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U
         },
 
         /**
@@ -332,14 +332,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.
          */
             {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
             },
 
         /**
@@ -347,14 +347,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * if it exists, otherwise of no use.
          */
             {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
+            8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
+            16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,
+            24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,
+            32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U
+            40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,
+            48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,
+            56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U
             },
 
          /**
@@ -363,22 +363,22 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
           * on the mapped channel.
           */
             {
-            0u, 1u, 2u, 3u,
-            4u, 5u, 6u, 7u,
-            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u,
-            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            24u, 25u, 26u, 27u,
-            28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
+            0U, 1U, 2U, 3U,
+            4U, 5U, 6U, 7U,
+            8U, 9U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12U, 13U, 14U, 15U,
+            16U, 17U, 18U, 19U,
+            20U, 21U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24U, 25U, 26U, 27U,
+            28U, 29U, 30U, 31U,
+            32U, 33U, 34U, 35U,
+            36U, 37U, 38U, 39U,
+            40U, 41U, 42U, 43U,
+            44U, 45U, 46U, 47U,
+            48U, 49U, 50U, 51U,
+            52U, 53U, 54U, 55U,
+            56U, 57U, 58U, 59U,
+            60U, 61U, 62U, 63U
             },
 
         /**
@@ -403,36 +403,36 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu},
+            {0xFFFFFFFFU, 0xFFFFFFFFU},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x000000FFu},
+            {0x000000FFU},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu},
+            {0xFFFFFFFFU, 0xFFFFFFFFU},
 
             /* Resources reserved by Region 1 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31       0 */
@@ -442,7 +442,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31       0 */
@@ -454,46 +454,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
+            {0xFFFFFFFFU, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x000000FFu},
+            {0x000000FFU},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
+            {0xFFFFFFFFU, 0x00000000U},
 
             /* Resources reserved by Region 1 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0xFFFFFFFFU, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* resvdDmaChannels */
             /* 31       0 */
-            {0xFF3FF3FFu,
+            {0xFF3FF3FFU,
             /* 63..32 */
-            0x00000000u},
+            0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31       0 */
@@ -505,46 +505,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
+            {0xFFFFFFFFU, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x000000FFu},
+            {0x000000FFU},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
+            {0xFFFFFFFFU, 0x00000000U},
 
             /* Resources reserved by Region 1 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0xFFFFFFFFU, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* resvdDmaChannels */
             /* 31       0 */
-            {0xFF3FF3FFu,
+            {0xFF3FF3FFU,
             /* 63..32 */
-            0x00000000u},
+            0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31       0 */
@@ -557,235 +557,235 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x0000F000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
 
         /* Resources owned/reserved by region 4 */
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x0000F000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
 
         /* Resources owned/reserved by region 5 */
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
 
         /* Resources owned/reserved by region 6 */
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
 
         /* Resources owned/reserved by region 7 */
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
     },
 };
index 4dc5c71eee525dccb45ac4c6b8dbedef30b41048..8b612581d76d9fac2bcee0b90a2c7675874c98c2 100755 (executable)
@@ -60,22 +60,22 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[];
+extern uint32_t hwIntCcErr[];
+extern uint32_t hwIntTcErr[];
 
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
 /* This variable has to be used as an extern */
-unsigned int gpp_num = 0;
+uint32_t gpp_num = 0;
 
 Hwi_Handle hwiCCXferCompInt;
 Hwi_Handle hwiCCErrInt;
@@ -96,45 +96,45 @@ typedef struct  {
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003FU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
 
 
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)
-#define EDMA3_NUM_TCC                     (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95U)
+#define EDMA3_NUM_TCC                     (64U)
 
 /*
  * Forward decleration
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum);
 
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
 
 /**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
     {
     static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
     Hwi_Params hwiParams; 
     Error_Block      eb;
 
@@ -225,10 +225,10 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     }
 
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
        static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
@@ -252,13 +252,13 @@ void unregisterEdma3Interrupts (unsigned int edma3Id)
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
+    uint32_t xbarEvtNum = 0;
+    int32_t          edmaChanNum = 0;
 
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
                (chanNum != NULL) &&
@@ -284,13 +284,13 @@ EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
+    uint32_t scrChanOffset = 0;
+    uint32_t scrRegOffset  = 0;
+    uint32_t xBarEvtNum    = 0;
     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);
 
 
@@ -335,7 +335,7 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
        }
 
 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
-                                   unsigned int edma3Id)
+                                   uint32_t edma3Id)
     {
     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
@@ -351,7 +351,7 @@ EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
     return retVal;
     }
 
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
     {
     printf("memory Protection error");
     }
index 684821be910804c2e5e12d178cbc1981e4dced8d..d182b5e1be11d974d070ba2ad3686c075420089b 100755 (executable)
 #include <ti/sdo/edma3/rm/edma3_rm.h>
 
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         1u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+#define NUM_EDMA3_INSTANCES         1U
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 /* Number of DSPs present in the system */
-#define NUM_DSPS                    1u
-const unsigned int numDsps = NUM_DSPS;
+#define NUM_DSPS                    1U
+const uint32_t numDsps = NUM_DSPS;
 
 /* Determine the processor id by reading DNUM register. */
-unsigned short determineProcId()
+uint16_t determineProcId()
 {
     return 1;
 }
 
-signed char*  getGlobalAddr(signed char* addr)
+int8_t*  getGlobalAddr(int8_t* addr)
 {
      return (addr); /* The address is already a global address */
 }
-unsigned short isGblConfigRequired(unsigned int dspNum)
+uint16_t isGblConfigRequired(uint32_t dspNum)
 {
     (void) dspNum;
 
@@ -69,40 +69,40 @@ unsigned short isGblConfigRequired(unsigned int dspNum)
 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 
 /** Number of PaRAM Sets available                                            */
-#define EDMA3_NUM_PARAMSET                              (512u)
+#define EDMA3_NUM_PARAMSET                              (512U)
 
 /** Number of TCCS available                                                  */
-#define EDMA3_NUM_TCC                                   (64u)
+#define EDMA3_NUM_TCC                                   (64U)
 
 /** Number of DMA Channels available                                          */
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+#define EDMA3_NUM_DMA_CHANNELS                          (64U)
 
 /** Number of QDMA Channels available                                         */
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+#define EDMA3_NUM_QDMA_CHANNELS                         (8U)
 
 /** Number of Event Queues available                                          */
-#define EDMA3_0_NUM_EVTQUE                              (4u)
+#define EDMA3_0_NUM_EVTQUE                              (4U)
 
 /** Number of Transfer Controllers available                                  */
-#define EDMA3_0_NUM_TC                                  (4u)
+#define EDMA3_0_NUM_TC                                  (4U)
 
 /** Number of Regions                                                         */
-#define EDMA3_0_NUM_REGIONS                             (2u)
+#define EDMA3_0_NUM_REGIONS                             (2U)
 
 
 /** Interrupt no. for Transfer Completion                                     */
-#define EDMA3_0_CC_XFER_COMPLETION_INT                  (20u)
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (20U)
 /** Interrupt no. for CC Error                                                */
-#define EDMA3_0_CC_ERROR_INT                            (21u)
+#define EDMA3_0_CC_ERROR_INT                            (21U)
 /** Interrupt no. for TCs Error                                               */
-#define EDMA3_0_TC0_ERROR_INT                           (22u)
-#define EDMA3_0_TC1_ERROR_INT                           (27u)
-#define EDMA3_0_TC2_ERROR_INT                           (28u)
-#define EDMA3_0_TC3_ERROR_INT                           (29u)
-#define EDMA3_0_TC4_ERROR_INT                           (0u)
-#define EDMA3_0_TC5_ERROR_INT                           (0u)
-#define EDMA3_0_TC6_ERROR_INT                           (0u)
-#define EDMA3_0_TC7_ERROR_INT                           (0u)
+#define EDMA3_0_TC0_ERROR_INT                           (22U)
+#define EDMA3_0_TC1_ERROR_INT                           (27U)
+#define EDMA3_0_TC2_ERROR_INT                           (28U)
+#define EDMA3_0_TC3_ERROR_INT                           (29U)
+#define EDMA3_0_TC4_ERROR_INT                           (0U)
+#define EDMA3_0_TC5_ERROR_INT                           (0U)
+#define EDMA3_0_TC6_ERROR_INT                           (0U)
+#define EDMA3_0_TC7_ERROR_INT                           (0U)
 
 /**
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
@@ -120,12 +120,12 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  */
 /* EDMA 0 */
 
-#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
-#define EDMA3_0_HWI_INT_CC_ERR                              (7u)
-#define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
-#define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
-#define EDMA3_0_HWI_INT_TC2_ERR                             (7u)
-#define EDMA3_0_HWI_INT_TC3_ERR                             (7u)
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7U)
+#define EDMA3_0_HWI_INT_CC_ERR                              (7U)
+#define EDMA3_0_HWI_INT_TC0_ERR                             (7U)
+#define EDMA3_0_HWI_INT_TC1_ERR                             (7U)
+#define EDMA3_0_HWI_INT_TC2_ERR                             (7U)
+#define EDMA3_0_HWI_INT_TC3_ERR                             (7U)
 
 
 /**
@@ -143,7 +143,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                       /* 31     0 */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F00u)  /* TBD */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F00U)  /* TBD */
 
 
 /**
@@ -161,16 +161,16 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
 /* DMA channels 32-63 DOES NOT exist in omapl138. */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF033C00u) /* TBD */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF033C00U) /* TBD */
 
 
 /* Variable which will be used internally for referring number of Event Queues*/
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
                                                         EDMA3_0_NUM_EVTQUE,
                                                     };
 
 /* Variable which will be used internally for referring number of TCs.        */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
                                                     EDMA3_0_NUM_TC,
                                                 };
 
@@ -178,10 +178,10 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
  * Variable which will be used internally for referring transfer completion
  * interrupt.
  */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     {
-        0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+        0U, EDMA3_0_CC_XFER_COMPLETION_INT, 0U, 0U, 0U, 0U, 0U, 0U,
     },
 };
 
@@ -189,7 +189,7 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
  * Variable which will be used internally for referring channel controller's
  * error interrupt.
  */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {
                                                     EDMA3_0_CC_ERROR_INT,
                                                };
 
@@ -197,7 +197,7 @@ unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
  * Variable which will be used internally for referring transfer controllers'
  * error interrupts.
  */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][8] =
 {
    {
        EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
@@ -211,15 +211,15 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] = {
                                                     EDMA3_0_HWI_INT_XFER_COMP
                                                   };
 
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] = {
                                                    EDMA3_0_HWI_INT_CC_ERR
                                                };
 
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
                                                      {
                                                         EDMA3_0_HWI_INT_TC0_ERR,
                                                         EDMA3_0_HWI_INT_TC1_ERR,
@@ -254,19 +254,19 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,
          * PaRAM entry n corresponds to channel n.
          */
-        1u,
+        1U,
 
         /** Existence of memory protection feature */
-        0u,
+        0U,
 
         /** Global Register Region of CC Registers */
-        (void *)0x09000000u,
+        (void *)0x09000000U,
         /** Transfer Controller (TC) Registers */
         {
-            (void *)0x09800000u,
-            (void *)0x09900000u,
-            (void *)0x09A00000u,
-            (void *)0x09B00000u,
+            (void *)0x09800000U,
+            (void *)0x09900000U,
+            (void *)0x09A00000U,
+            (void *)0x09B00000U,
             (void *)NULL,
             (void *)NULL,
             (void *)NULL,
@@ -298,14 +298,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)
          */
         {
-            0u,
-            1u,
-            2u,
-            3u,
-            0u,
-            0u,
-            0u,
-            0u
+            0U,
+            1U,
+            2U,
+            3U,
+            0U,
+            0U,
+            0U,
+            0U
         },
         /**
          * \brief To Configure the Threshold level of number of events
@@ -316,14 +316,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).
          */
         {
-            16u,
-            16u,
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U
         },
 
         /**
@@ -333,14 +333,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.
          */
             {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
             },
 
         /**
@@ -348,14 +348,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * if it exists, otherwise of no use.
          */
             {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
+            8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
+            16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,
+            24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,
+            32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U
+            40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,
+            48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,
+            56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U
             },
 
          /**
@@ -364,22 +364,22 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
           * on the mapped channel.
           */
             {
-            0u, 1u, 2u, 3u,
-            4u, 5u, 6u, 7u,
-            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u,
-            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            24u, 25u, 26u, 27u,
-            28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
+            0U, 1U, 2U, 3U,
+            4U, 5U, 6U, 7U,
+            8U, 9U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12U, 13U, 14U, 15U,
+            16U, 17U, 18U, 19U,
+            20U, 21U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24U, 25U, 26U, 27U,
+            28U, 29U, 30U, 31U,
+            32U, 33U, 34U, 35U,
+            36U, 37U, 38U, 39U,
+            40U, 41U, 42U, 43U,
+            44U, 45U, 46U, 47U,
+            48U, 49U, 50U, 51U,
+            52U, 53U, 54U, 55U,
+            56U, 57U, 58U, 59U,
+            60U, 61U, 62U, 63U
             },
 
         /**
@@ -405,36 +405,36 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
+            {0xFFFFFFFFU, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x000000FFu},
+            {0x000000FFU},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
+            {0xFFFFFFFFU, 0x00000000U},
 
             /* Resources reserved by Region 1 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0xFFFFFFFFU, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* resvdDmaChannels */
             /* 31       0 */
@@ -444,7 +444,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31       0 */
@@ -456,36 +456,36 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu},
+            {0xFFFFFFFFU, 0xFFFFFFFFU},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x000000FFu},
+            {0x000000FFU},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu},
+            {0xFFFFFFFFU, 0xFFFFFFFFU},
 
             /* Resources reserved by Region 1 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* resvdDmaChannels */
             /* 31       0 */
@@ -495,7 +495,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31       0 */
@@ -507,282 +507,282 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x0000F000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
 
         /* Resources owned/reserved by region 3 */
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x0000F000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
 
         /* Resources owned/reserved by region 4 */
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x0000F000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
 
         /* Resources owned/reserved by region 5 */
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
 
         /* Resources owned/reserved by region 6 */
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
 
         /* Resources owned/reserved by region 7 */
         {
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
         },
     },
 };
index 7f7a5be0a21e398ebe216dd7dcde94b41f98f008..86a23970c9dfcddf37e16c5b7cdd532aa5d96985 100755 (executable)
@@ -47,7 +47,7 @@
   * (Not all TC error ISRs need to be registered, register only for the
   * available Transfer Controllers).
   */
-void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 {
                                                 &lisrEdma3TC0ErrHandler0,
                                                 &lisrEdma3TC1ErrHandler0,
@@ -59,20 +59,20 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
                                                 &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[];
+extern uint32_t hwIntCcErr[];
+extern uint32_t hwIntTcErr[];
 
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
 
 /* External Instance Specific Configuration Structure */
 extern EDMA3_RM_GblXbarToChanConfigParams 
@@ -89,44 +89,44 @@ typedef struct  {
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
 
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003FU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
 
 
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (64u)
-#define EDMA3_NUM_TCC                     (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (64U)
+#define EDMA3_NUM_TCC                     (64U)
 
 /*
  * Forward decleration
  */
-EDMA3_RM_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_RM_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_RM_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
+EDMA3_RM_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum);
 
 
 /**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
     {
     static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
@@ -173,10 +173,10 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     }
 
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
        static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
@@ -206,13 +206,13 @@ void unregisterEdma3Interrupts (unsigned int edma3Id)
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_RM_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_RM_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig)
        {
     EDMA3_RM_Result edma3Result = EDMA3_RM_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
+    uint32_t xbarEvtNum = 0;
+    int32_t          edmaChanNum = 0;
 
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
                (chanNum != NULL) &&
@@ -238,13 +238,13 @@ EDMA3_RM_Result sampleMapXbarEvtToChan (unsigned int eventNum,
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_RM_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
+EDMA3_RM_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum)
        {
     EDMA3_RM_Result edma3Result = EDMA3_RM_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
+    uint32_t scrChanOffset = 0;
+    uint32_t scrRegOffset  = 0;
+    uint32_t xBarEvtNum    = 0;
     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x08140F00);
 
 
@@ -289,7 +289,7 @@ EDMA3_RM_Result sampleConfigScr (unsigned int eventNum,
        }
 
 EDMA3_RM_Result sampleInitXbarEvt(EDMA3_RM_Handle hEdma, 
-                                   unsigned int edma3Id)
+                                   uint32_t edma3Id)
     {
     EDMA3_DRV_Result retVal = EDMA3_RM_E_INVALID_PARAM;
     const EDMA3_RM_GblXbarToChanConfigParams *sampleXbarToChanConfig =
index 93754b2e160ecae4ab5d2d6c12d77f620a691103..6ac8914b8182ed2182d374a280e5d46490ed3951 100644 (file)
 #include <ti/sdo/edma3/rm/edma3_rm.h>
 
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES                    1u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+#define NUM_EDMA3_INSTANCES                    1U
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 /* Number of DSPs present in the system */
-#define NUM_DSPS                                       1u
-const unsigned int numDsps = NUM_DSPS;
+#define NUM_DSPS                                       1U
+const uint32_t numDsps = NUM_DSPS;
 
 /* Determine the processor id by reading DNUM register. */
-unsigned short determineProcId()
+uint16_t determineProcId()
        {
 #if 0
-       volatile unsigned int *addr;
-       unsigned int core_no;
+       volatile uint32_t *addr;
+       uint32_t core_no;
 
     /* Identify the core number */
-    addr = (unsigned int *)(CGEM_REG_START+0x40000);
+    addr = (uint32_t *)(CGEM_REG_START+0x40000);
     core_no = ((*addr) & 0x000F0000)>>16;
 
        return core_no;
@@ -64,12 +64,12 @@ unsigned short determineProcId()
        return 4;
        }
 
-signed char*  getGlobalAddr(signed char* addr)
+int8_t*  getGlobalAddr(int8_t* addr)
 {
      return (addr); /* The address is already a global address */
 }
 
-unsigned short isGblConfigRequired(unsigned int dspNum)
+uint16_t isGblConfigRequired(uint32_t dspNum)
        {
        (void) dspNum;
 
@@ -80,26 +80,26 @@ unsigned short isGblConfigRequired(unsigned int dspNum)
 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 
 /** Number of PaRAM Sets available */
-#define EDMA3_NUM_PARAMSET                             (512u)
+#define EDMA3_NUM_PARAMSET                             (512U)
 /** Number of TCCS available */
-#define EDMA3_NUM_TCC                                  (64u)
+#define EDMA3_NUM_TCC                                  (64U)
 /** Number of Event Queues available */
-#define EDMA3_NUM_EVTQUE                                (4u)
+#define EDMA3_NUM_EVTQUE                                (4U)
 /** Number of Transfer Controllers available */
-#define EDMA3_NUM_TC                                    (4u)
+#define EDMA3_NUM_TC                                    (4U)
 /** Interrupt no. for Transfer Completion */
 #define EDMA3_CC_XFER_COMPLETION_INT                    (62)
 /** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT                              (46u)
+#define EDMA3_CC_ERROR_INT                              (46U)
 /** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT                             (0u)
-#define EDMA3_TC1_ERROR_INT                             (0u)
-#define EDMA3_TC2_ERROR_INT                             (0u)
-#define EDMA3_TC3_ERROR_INT                             (0u)
-#define EDMA3_TC4_ERROR_INT                             (0u)
-#define EDMA3_TC5_ERROR_INT                             (0u)
-#define EDMA3_TC6_ERROR_INT                             (0u)
-#define EDMA3_TC7_ERROR_INT                             (0u)
+#define EDMA3_TC0_ERROR_INT                             (0U)
+#define EDMA3_TC1_ERROR_INT                             (0U)
+#define EDMA3_TC2_ERROR_INT                             (0U)
+#define EDMA3_TC3_ERROR_INT                             (0U)
+#define EDMA3_TC4_ERROR_INT                             (0U)
+#define EDMA3_TC5_ERROR_INT                             (0U)
+#define EDMA3_TC6_ERROR_INT                             (0U)
+#define EDMA3_TC7_ERROR_INT                             (0U)
 
 /**
 * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
@@ -115,9 +115,9 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
 * to TC error interrupts.
 */
-#define EDMA3_HWI_INT_XFER_COMP                                                        (7u)
-#define EDMA3_HWI_INT_CC_ERR                                                   (11u)
-#define EDMA3_HWI_INT_TC_ERR                                                   (11u)
+#define EDMA3_HWI_INT_XFER_COMP                                                        (7U)
+#define EDMA3_HWI_INT_CC_ERR                                                   (11U)
+#define EDMA3_HWI_INT_TC_ERR                                                   (11U)
 
 
 /**
@@ -135,7 +135,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                                                                          /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0U)
 
 /**
  * \brief Mapping of DMA channels 32-63 to Hardware Events from
@@ -152,19 +152,19 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                                                                          /* 63     32 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFU)
 
 /* Variable which will be used internally for referring number of Event Queues. */
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
 
 /* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
 
 /**
  * Variable which will be used internally for referring transfer completion
  * interrupt.
  */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
                                                        {
                                                        EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
                                                        EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
@@ -175,13 +175,13 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
  * Variable which will be used internally for referring channel controller's
  * error interrupt.
  */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
 
 /**
  * Variable which will be used internally for referring transfer controllers'
  * error interrupts.
  */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
                                 {
                                 EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
                                 EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
@@ -194,9 +194,9 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
-unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
-unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+uint32_t hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+uint32_t hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+uint32_t hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
 
 
 /* Driver Object Initialization Configuration */
@@ -204,19 +204,19 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
        {
            {
            /** Total number of DMA Channels supported by the EDMA3 Controller */
-           64u,
+           64U,
            /** Total number of QDMA Channels supported by the EDMA3 Controller */
-           8u,
+           8U,
            /** Total number of TCCs supported by the EDMA3 Controller */
-           64u,
+           64U,
            /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-           512u,
+           512U,
            /** Total number of Event Queues in the EDMA3 Controller */
-           4u,
+           4U,
            /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-           4u,
+           4U,
            /** Number of Regions on this EDMA3 controller */
-           5u,
+           5U,
 
            /**
             * \brief Channel mapping existence
@@ -224,19 +224,19 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
             * for a channel number to a parameter entry number or, in other words,
             * PaRAM entry n corresponds to channel n.
             */
-           1u,
+           1U,
 
            /** Existence of memory protection feature */
-           1u,
+           1U,
 
            /** Global Register Region of CC Registers */
-           (void *)0x49000000u,
+           (void *)0x49000000U,
            /** Transfer Controller (TC) Registers */
                {
-               (void *)0x49800000u,
-               (void *)0x49900000u,
-               (void *)0x49A00000u,
-               (void *)0x49B00000u,
+               (void *)0x49800000U,
+               (void *)0x49900000U,
+               (void *)0x49A00000U,
+               (void *)0x49B00000U,
                (void *)NULL,
                (void *)NULL,
                (void *)NULL,
@@ -268,14 +268,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
             * device (ARM, DSP, USB, etc)
             */
                {
-               0u,
-               1u,
-               2u,
-               3u,
-               0u,
-               0u,
-               0u,
-               0u
+               0U,
+               1U,
+               2U,
+               3U,
+               0U,
+               0U,
+               0U,
+               0U
                },
            /**
             * \brief To Configure the Threshold level of number of events
@@ -286,14 +286,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
             * in the queue watermark threshold register (QWMTHRA).
             */
                {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
+               16U,
+               16U,
+               16U,
+               16U,
+               0U,
+               0U,
+               0U,
+               0U
                },
 
            /**
@@ -303,14 +303,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
             * DBS values. It is defined in Bytes.
             */
                {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
+               16U,
+               16U,
+               16U,
+               16U,
+               0U,
+               0U,
+               0U,
+               0U
                },
 
            /**
@@ -318,14 +318,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
             * if it exists, otherwise of no use.
             */
             {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
+            8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
+            16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,
+            24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,
+            32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U
+            40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,
+            48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,
+            56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U
             },
 
             /**
@@ -334,22 +334,22 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
              * on the mapped channel.
              */
             {
-            0u, 1u, 2u, 3u,
-            4u, 5u, 6u, 7u,
-            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u,
-            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            24u, 25u, 26u, 27u,
-            28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
+            0U, 1U, 2U, 3U,
+            4U, 5U, 6U, 7U,
+            8U, 9U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12U, 13U, 14U, 15U,
+            16U, 17U, 18U, 19U,
+            20U, 21U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24U, 25U, 26U, 27U,
+            28U, 29U, 30U, 31U,
+            32U, 33U, 34U, 35U,
+            36U, 37U, 38U, 39U,
+            40U, 41U, 42U, 43U,
+            44U, 45U, 46U, 47U,
+            48U, 49U, 50U, 51U,
+            52U, 53U, 54U, 55U,
+            56U, 57U, 58U, 59U,
+            60U, 61U, 62U, 63U
             },
 
 
@@ -359,8 +359,8 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
             * All channels need not be mapped, some can be free also.
             */
                {
-               0x00000000u,
-               0x00000000u
+               0x00000000U,
+               0x00000000U
                },
                },
        };
@@ -374,383 +374,383 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                        /* Resources owned/reserved by region 0 */
                        {
                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* ownQdmaChannels */
                /* 31     0 */
-               {0x00000001u},
+               {0x00000001U},
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
 
                /* Resources reserved by Region 0 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
+        {0x00000000U, 0x00000000U},
 
                /* resvdQdmaChannels */
                /* 31     0 */
-               {0x00000000u},
+               {0x00000000U},
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
+        {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 1 */
                    {
                        /* ownPaRAMSets */
                        /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* ownQdmaChannels */
                /* 31     0 */
-               {0x00000002u},
+               {0x00000002U},
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* Resources reserved by Region 1 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
+        {0x00000000U, 0x00000000U},
 
                /* resvdQdmaChannels */
                /* 31     0 */
-               {0x00000000u},
+               {0x00000000U},
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
+        {0x00000000U, 0x00000000U},
                    },
 
                /* Resources owned/reserved by region 2 */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+                0xFFFFFFFFU, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* ownQdmaChannels */
                /* 31     0 */
-               {0x00000004u},
+               {0x00000004U},
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* Resources reserved by Region 2 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
+        {0x00000000U, 0x00000000U},
 
                /* resvdQdmaChannels */
                /* 31     0 */
-               {0x00000000u},
+               {0x00000000U},
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
+        {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 3 */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                0x00000000U, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* ownQdmaChannels */
                /* 31     0 */
-               {0x00000008u},
+               {0x00000008U},
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* Resources reserved by Region 3 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* resvdDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
+               {0x00000000U, 0x00000000U},
 
                /* resvdQdmaChannels */
                /* 31     0 */
-               {0x00000000u},
+               {0x00000000U},
 
                /* resvdTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
+               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 4 */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+                0x00000000U, 0x00000000U, 0xFFFFFFFFU, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* ownQdmaChannels */
                /* 31     0 */
-               {0x00000008u},
+               {0x00000008U},
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* Resources reserved by Region 4 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* resvdDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
+               {0x00000000U, 0x00000000U},
 
                /* resvdQdmaChannels */
                /* 31     0 */
-               {0x00000000u},
+               {0x00000000U},
 
                /* resvdTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
+               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 5 */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+                0x00000000U, 0x00000000U, 0x00000000U, 0xFFFFFFFFU,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* ownQdmaChannels */
                /* 31     0 */
-               {0x00000008u},
+               {0x00000008U},
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
+               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                /* Resources reserved by Region 5 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
                /* resvdDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
+               {0x00000000U, 0x00000000U},
 
                /* resvdQdmaChannels */
                /* 31     0 */
-               {0x00000000u},
+               {0x00000000U},
 
                /* resvdTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
+               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 6 */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 7 */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
            },
        };
index f6dabd784ff6a7072979e2cb09f819eaf5a43176..0c0efcc7339752408e49e91a2d8646128d468d22 100644 (file)
@@ -50,7 +50,7 @@
   * (Not all TC error ISRs need to be registered, register only for the
   * available Transfer Controllers).
   */
-void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 {
                                                 &lisrEdma3TC0ErrHandler0,
                                                 &lisrEdma3TC1ErrHandler0,
@@ -62,32 +62,32 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
                                                 &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern unsigned int hwIntXferComp;
-extern unsigned int hwIntCcErr;
-extern unsigned int hwIntTcErr;
+extern uint32_t hwIntXferComp;
+extern uint32_t hwIntCcErr;
+extern uint32_t hwIntTcErr;
 
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
 /* This variable has to be used as an extern */
-//unsigned int gpp_num = 4;
+//uint32_t gpp_num = 4;
 
 Hwi_Handle hwiCCXferCompInt;
 Hwi_Handle hwiCCErrInt;
 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
 
 /**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
     {
     static UInt32 cookie = 0;
-    //unsigned int numTc = 0;
+    //uint32_t numTc = 0;
     Hwi_Params hwiParams; 
     Error_Block      eb;
 
@@ -183,10 +183,10 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     }
 
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
        static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
index 5a6f16ec2d59391a52d8544dcbddf9e0db1040c3..32784b93ec0f8f516c69d0929d65926ab2c5f22f 100755 (executable)
 
 #include <ti/sdo/edma3/rm/edma3_rm.h>
 
-#define NUM_SHADOW_REGIONS                      (4u)
+#define NUM_SHADOW_REGIONS                      (4U)
 
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         1u
+#define NUM_EDMA3_INSTANCES         1U
 
 /**
  * \brief Mapping of DMA channels 0-31 to Hardware Events from
@@ -59,7 +59,7 @@
  */
 /* EDMA3 0 */
                                                 /* 31     0 */
-#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0        (0xFF3FF3FFu)
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0        (0xFF3FF3FFU)
 /**
  * EDMA channels 22 and 23, which correspond to GPIO
  * bank interrupts will be used for memory-to-memory data transfers.
  */
 /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
 /* EDMA3 0 */
-#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1        (0x0u)
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1        (0x0U)
 
 /** Number of PaRAM Sets available                                            */
-#define EDMA3_NUM_PARAMSET                              (512u)
+#define EDMA3_NUM_PARAMSET                              (512U)
 
 /** Number of TCCS available                                                  */
-#define EDMA3_NUM_TCC                                   (64u)
+#define EDMA3_NUM_TCC                                   (64U)
 
 /** Number of DMA Channels available                                          */
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+#define EDMA3_NUM_DMA_CHANNELS                          (64U)
 
 /** Number of QDMA Channels available                                         */
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+#define EDMA3_NUM_QDMA_CHANNELS                         (8U)
 
 /** Number of Event Queues available                                          */
-#define EDMA3_0_NUM_EVTQUE                              (4u)
+#define EDMA3_0_NUM_EVTQUE                              (4U)
 
 /** Number of Transfer Controllers available                                  */
-#define EDMA3_0_NUM_TC                                  (4u)
+#define EDMA3_0_NUM_TC                                  (4U)
 
 /** Number of Regions                                                         */
-#define EDMA3_0_NUM_REGIONS                             (2u)
+#define EDMA3_0_NUM_REGIONS                             (2U)
 
 
 /** Interrupt no. for Transfer Completion                                     */
-#define EDMA3_0_CC_XFER_COMPLETION_INT                  (20u)
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (20U)
 /** Interrupt no. for CC Error                                                */
-#define EDMA3_0_CC_ERROR_INT                            (21u)
+#define EDMA3_0_CC_ERROR_INT                            (21U)
 /** Interrupt no. for TCs Error                                               */
-#define EDMA3_0_TC0_ERROR_INT                           (22u)
-#define EDMA3_0_TC1_ERROR_INT                           (27u)
-#define EDMA3_0_TC2_ERROR_INT                           (28u)
-#define EDMA3_0_TC3_ERROR_INT                           (29u)
-#define EDMA3_0_TC4_ERROR_INT                           (0u)
-#define EDMA3_0_TC5_ERROR_INT                           (0u)
-#define EDMA3_0_TC6_ERROR_INT                           (0u)
-#define EDMA3_0_TC7_ERROR_INT                           (0u)
+#define EDMA3_0_TC0_ERROR_INT                           (22U)
+#define EDMA3_0_TC1_ERROR_INT                           (27U)
+#define EDMA3_0_TC2_ERROR_INT                           (28U)
+#define EDMA3_0_TC3_ERROR_INT                           (29U)
+#define EDMA3_0_TC4_ERROR_INT                           (0U)
+#define EDMA3_0_TC5_ERROR_INT                           (0U)
+#define EDMA3_0_TC6_ERROR_INT                           (0U)
+#define EDMA3_0_TC7_ERROR_INT                           (0U)
 
 EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
 {
@@ -144,19 +144,19 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
      * for a channel number to a parameter entry number or, in other words,
      * PaRAM entry n corresponds to channel n.
      */
-    0u,
+    0U,
 
     /** Existence of memory protection feature */
-    0u,
+    0U,
 
     /** Global Register Region of CC Registers */
-    (void *)(0x49000000u),
+    (void *)(0x49000000U),
     /** Transfer Controller (TC) Registers */
         {
-        (void *)(0x49800000u),
-        (void *)(0x49900000u),
-        (void *)(0x49A00000u),
-        (void *)(0x49B00000u),
+        (void *)(0x49800000U),
+        (void *)(0x49900000U),
+        (void *)(0x49A00000U),
+        (void *)(0x49B00000U),
         (void *)NULL,
         (void *)NULL,
         (void *)NULL,
@@ -188,14 +188,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
      * device (ARM, DSP, USB, etc)
      */
         {
-        0u,
-        1u,
-        2u,
-        3u,
-        0u,
-        0u,
-        0u,
-        0u
+        0U,
+        1U,
+        2U,
+        3U,
+        0U,
+        0U,
+        0U,
+        0U
         },
     /**
      * \brief To Configure the Threshold level of number of events
@@ -206,14 +206,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
      * in the queue watermark threshold register (QWMTHRA).
      */
         {
-        16u,
-        16u,
-        16u,
-        16u,
-        0u,
-        0u,
-        0u,
-        0u
+        16U,
+        16U,
+        16U,
+        16U,
+        0U,
+        0U,
+        0U,
+        0U
         },
 
     /**
@@ -223,14 +223,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
      * DBS values. It is defined in Bytes.
      */
         {
-        16u,
-        16u,
-        16u,
-        16u,
-        0u,
-        0u,
-        0u,
-        0u
+        16U,
+        16U,
+        16U,
+        16U,
+        0U,
+        0U,
+        0U,
+        0U
         },
 
     /**
@@ -238,10 +238,10 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
      * if it exists, otherwise of no use.
      */
         {
-        0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+        0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
+        8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
+        16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,
+        24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,
         /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
         EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
@@ -267,14 +267,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
       * on the mapped channel.
       */
         {
-        0u, 1u, 2u, 3u,
-        4u, 5u, 6u, 7u,
-        8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u,
-        20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        24u, 25u, 26u, 27u,
-        28u, 29u, 30u, 31u,
+        0U, 1U, 2U, 3U,
+        4U, 5U, 6U, 7U,
+        8U, 9U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        12U, 13U, 14U, 15U,
+        16U, 17U, 18U, 19U,
+        20U, 21U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        24U, 25U, 26U, 27U,
+        28U, 29U, 30U, 31U,
         /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
         EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
@@ -308,84 +308,84 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SH
             /* Resources owned by Region 0 */
              /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* Resources reserved by Region 0 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
           },
 
           {
             /* Resources owned by Region 1 */
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
+            {0xFFFFFFFFU, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x000000FFu},
+            {0x000000FFU},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
+            {0xFFFFFFFFU, 0x00000000U},
 
             /* Resources reserved by Region 1 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0xFFFFFFFFU, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* resvdDmaChannels */
             /* 31      0  63..32 */
@@ -393,7 +393,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SH
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31      0  63..32 */
@@ -404,96 +404,96 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SH
             /* Resources owned by Region 2 */
              /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* Resources reserved by Region 2 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
           },
 
           {
             /* Resources owned by Region 3 */
              /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* Resources reserved by Region 3 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
             /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+             0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
 
             /* resvdDmaChannels */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
 
             /* resvdQdmaChannels */
             /* 31     0 */
-            {0x00000000u},
+            {0x00000000U},
 
             /* resvdTccs */
             /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
+            {0x00000000U, 0x00000000U},
           },
         },
 };