Misra C Fixes: DRA72x Files
authorSunil MS <x0190988@ti.com>
Wed, 15 Oct 2014 11:36:00 +0000 (17:06 +0530)
committerSunil MS <x0190988@ti.com>
Mon, 20 Oct 2014 14:14:33 +0000 (19:44 +0530)
MISRA.ASM.ENCAPS
MISRA.BITS.NOT_UNSIGNED
MISRA.BUILTIN_NUMERIC
MISRA.CVALUE.IMPL.CAST
MISRA.DECL.ARRAY_SIZE
MISRA.DEFINE.BADEXP
MISRA.EXPR.PARENS
MISRA.FUNC.NOPROT.DEF
MISRA.FUNC.UNNAMED.PARAMS
MISRA.IF.NO_COMPOUND
MISRA.IF.NO_ELSE
MISRA.INIT.BRACES
MISRA.LITERAL.UNSIGNED.SUFFIX
MISRA.VAR.UNIQUE.STATIC

Change-Id: I9fe1c474521b5fde38e941251ae56ed17546d89a
Signed-off-by: Sunil MS <x0190988@ti.com>
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c

index 7e627a8233c93e47531789c18243708182c5f515..fb31454ef69edd912d1d70a1bf9081701374cce8 100644 (file)
   */
 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 {
-                                                (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorInt[];
-extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
-extern uint32_t numEdma3Tc[];
-extern uint32_t ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
-extern uint32_t ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorIntXbarInstNo[];
-extern uint32_t ccErrEdmaXbarIndex[];
-extern uint32_t tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
-extern uint32_t tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t ccXferCompIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccCompEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t ccErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t tcErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern uint32_t hwIntXferComp[];
-extern uint32_t hwIntCcErr[];
-extern uint32_t hwIntTcErr[];
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
 
 extern uint32_t dsp_num;
 /* This variable has to be used as an extern */
@@ -90,8 +90,8 @@ Hwi_Handle hwiCCErrInt;
 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
 
 /* External Instance Specific Configuration Structure */
-extern EDMA3_DRV_GblXbarToChanConfigParams
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+extern EDMA3_DRV_GblXbarToChanConfigParams 
+                                                               sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
 
 typedef struct  {
     volatile Uint32 TPCC_EVTMUX[32];
@@ -121,6 +121,14 @@ EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
                                   uint32_t chanNum);
 
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
+                                   uint32_t edma3Id);
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (uint32_t edma3Id);
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (uint32_t edma3Id);
+
 void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
 
 /**  To Register the ISRs with the underlying OS, if required. */
@@ -133,7 +141,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
      * Skip these interrupt xbar configuration.
      * if it is accessing EVE internal edma instance ie edma3id = 2 and dsp_num = 1.
      */
-    if (edma3Id != 2 && dsp_num != 1)
+    if ((edma3Id != 2U) && (dsp_num != 1U))
     {
         IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
         IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
@@ -156,13 +164,13 @@ void registerEdma3Interrupts (uint32_t edma3Id)
     /* argument for the ISR */
     hwiParams.arg = edma3Id;
        /* set the priority ID     */
-       //hwiParams.priority = hwIntXferComp[edma3Id];
-
+       /* hwiParams.priority = hwIntXferComp[edma3Id]; */
+    
     hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
                                        ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
                                        (const Hwi_Params *) (&hwiParams),
                                        &eb);
-    if (TRUE == Error_check(&eb))
+    if ((bool)TRUE == Error_check(&eb))
     {
         System_printf("HWI Create Failed\n",Error_getCode(&eb));
     }
@@ -172,14 +180,14 @@ void registerEdma3Interrupts (uint32_t edma3Id)
     /* argument for the ISR */
     hwiParams.arg = edma3Id;
        /* set the priority ID     */
-       //hwiParams.priority = hwIntCcErr[edma3Id];
-
+       /* hwiParams.priority = hwIntCcErr[edma3Id]; */
+       
        hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
                 ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
                 (const Hwi_Params *) (&hwiParams),
                 &eb);
 
-    if (TRUE == Error_check(&eb))
+    if ((bool)TRUE == Error_check(&eb))
     {
         System_printf("HWI Create Failed\n",Error_getCode(&eb));
     }
@@ -191,13 +199,13 @@ void registerEdma3Interrupts (uint32_t edma3Id)
         /* argument for the ISR */
         hwiParams.arg = edma3Id;
        /* set the priority ID     */
-        //hwiParams.priority = hwIntTcErr[edma3Id];
-
+        /* hwiParams.priority = hwIntTcErr[edma3Id]; */
+        
         hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
                     (ptrEdma3TcIsrHandler[numTc]),
                     (const Hwi_Params *) (&hwiParams),
                     &eb);
-        if (TRUE == Error_check(&eb))
+        if ((bool)TRUE == Error_check(&eb))
         {
             System_printf("HWI Create Failed\n",Error_getCode(&eb));
         }
@@ -219,11 +227,11 @@ void registerEdma3Interrupts (uint32_t edma3Id)
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
-       static UInt32 cookie = 0;
+       static UInt32 cookiee = 0;
     uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
-    cookie = Hwi_disable();
+    cookiee = Hwi_disable();
 
     Hwi_delete(&hwiCCXferCompInt);
     Hwi_delete(&hwiCCErrInt);
@@ -233,7 +241,7 @@ void unregisterEdma3Interrupts (uint32_t edma3Id)
         numTc++;
        }
     /* Restore interrupts */
-    Hwi_restore(cookie);
+    Hwi_restore(cookiee);
     }
 
 /**
@@ -289,17 +297,17 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
                (chanNum < EDMA3_NUM_TCC))
                {
-               scrRegOffset = chanNum / 2;
-               scrChanOffset = chanNum - (scrRegOffset * 2);
-               xBarEvtNum = eventNum + 1;
-
+               scrRegOffset = chanNum / 2U;
+               scrChanOffset = chanNum - (scrRegOffset * 2U);
+               xBarEvtNum = eventNum + 1U;
+               
                switch(scrChanOffset)
                        {
                        case 0:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
                                break;
-                       case 1:
+                       case 1U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
@@ -335,5 +343,8 @@ EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
 
 void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
     {
+#ifdef EDMA3_DRV_DEBUG
+    /*  Added to fix Misra C error */
     printf("memory Protection error");
+#endif
     }
index 7d6a011e66a4062ca696440fc86ec50ab80444cc..76cc9a133363e72f4024845c84eae7fae8de3f68 100644 (file)
@@ -59,41 +59,73 @@ int32_t myCoreNum;
 #define CORE_ID_C0 0x0
 #define CORE_ID_C1 0x1
 
-uint16_t determineProcId()
+#ifdef BUILD_DRA72X_MPU
+void __inline readProcFeatureReg(void);
+void __inline readProcFeatureReg(void)
+{
+    asm ("    push    {r0-r2} \n\t"
+            "    MRC p15, 0, r0, c0, c0, 5\n\t"
+                "    LDR      r1, =myCoreNum\n\t"
+                "    STR      r0, [r1]\n\t"
+                "    pop    {r0-r2}\n\t");
+}
+#endif
+
+int8_t*  getGlobalAddr(int8_t* addr);
+
+uint16_t determineProcId(void);
+
+uint16_t isGblConfigRequired(uint32_t dspNum);
+
+uint16_t determineProcId(void)
 {
-    uint16_t regionNo = numEdma3Instances;
+    uint16_t regionNo = (uint16_t)numEdma3Instances;
 #ifdef BUILD_DRA72X_DSP
     extern __cregister volatile uint32_t DNUM;
 #endif
 
-    myCoreNum = numDsps;
+    myCoreNum = (int32_t)numDsps;
 
 #ifdef BUILD_DRA72X_MPU
-    asm ("    push    {r0-r2} \n\t"
-            "    MRC p15, 0, r0, c0, c0, 5\n\t"
-                "    LDR      r1, =myCoreNum\n\t"
-                "    STR      r0, [r1]\n\t"
-                "    pop    {r0-r2}\n\t");
-       if((myCoreNum & 0x03) == 1)
-               regionNo = 1;
-       else
-               regionNo = 0;
+    readProcFeatureReg();
+/* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */
+       regionNo = 0U;
+    if(((uint32_t)myCoreNum & 0x03U) == 1U)
+    {
+        regionNo = 1U;
+    }
 #elif defined(BUILD_DRA72X_IPU)
     myCoreNum = (*(uint32_t *)(PID0_ADDRESS));
-    if(Core_getIpuId() == 1){
-        if(myCoreNum == CORE_ID_C0)
-            regionNo = 4;
-        else if (myCoreNum == CORE_ID_C1)
-            regionNo = 5;
+    if(Core_getIpuId() == 1U){
+        if(myCoreNum == (int32_t)CORE_ID_C0)
+        {
+            regionNo = 4U;
+        }
+        else if (myCoreNum == (int32_t)CORE_ID_C1)
+        {
+            regionNo = 5U;
+        }
+        else
+        {
+            /* Nothing to be done here*/
+        }
     }
-    if(Core_getIpuId() == 2){
-        if(myCoreNum == CORE_ID_C0)
-            regionNo = 6;
-        else if (myCoreNum == CORE_ID_C1)
-            regionNo = 7;
+    if(Core_getIpuId() == 2U){
+        if(myCoreNum == (int32_t)CORE_ID_C0)
+        {
+            regionNo = 6U;
+        }
+        else if (myCoreNum == (int32_t)CORE_ID_C1)
+        {
+            regionNo = 7U;
+        }
+        else
+        {
+            /* Nothing to be done here*/
+        }
     }
 #elif defined(BUILD_DRA72X_DSP)
-       regionNo = 2;
+       regionNo = 2U;
 #endif
        return regionNo;
 }
@@ -105,7 +137,7 @@ int8_t*  getGlobalAddr(int8_t* addr)
 uint16_t isGblConfigRequired(uint32_t dspNum)
 {
     (void) dspNum;
-       return 1;
+       return 1U;
 }
 
 /* Semaphore handles */
@@ -171,31 +203,31 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)
 
 #ifdef BUILD_DRA72X_MPU
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A15
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_A15_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A15
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_A15
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_A15)
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_A15)
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_A15_XBAR_INST_NO)
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_A15)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_A15)
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)
 
 #elif defined BUILD_DRA72X_DSP
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_DSP_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_DSP
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_DSP
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_DSP_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_DSP_XBAR_INST_NO
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_DSP)
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_DSP)
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_DSP_XBAR_INST_NO)
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_DSP)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_DSP)
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_DSP_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_DSP_XBAR_INST_NO)
 
 #elif defined BUILD_DRA72X_IPU
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU_C0
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_IPU)
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_IPU_XBAR_INST_NO)
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_IPU)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_IPU)
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_IPU_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_IPU_XBAR_INST_NO)
 
 #else
 #define EDMA3_CC_XFER_COMPLETION_INT                    (0U)
@@ -203,8 +235,8 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define CC_ERROR_INT_XBAR_INST_NO                       (0U)
 #define EDMA3_TC0_ERROR_INT                             (0U)
 #define EDMA3_TC1_ERROR_INT                             (0U)
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)
 #endif
 
 #define EDMA3_TC2_ERROR_INT                             (0U)
@@ -299,6 +331,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 /* Variable which will be used internally for referring number of Event Queues*/
 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
                                                         EDMA3_NUM_EVTQUE,
+                                                        EDMA3_NUM_EVTQUE
                                                     };
 
 /* Variable which will be used internally for referring number of TCs.        */
@@ -489,14 +522,22 @@ uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
         EDMA3_HWI_INT_TC0_ERR,
         EDMA3_HWI_INT_TC1_ERR,
         EDMA3_HWI_INT_TC2_ERR,
-        EDMA3_HWI_INT_TC3_ERR
+        EDMA3_HWI_INT_TC3_ERR,
+        0,
+        0,
+        0,
+        0
     },
     /* EDMA3 INSTANCE# 1 */
     {
         EDMA3_HWI_INT_TC0_ERR,
         EDMA3_HWI_INT_TC1_ERR,
         EDMA3_HWI_INT_TC2_ERR,
-        EDMA3_HWI_INT_TC3_ERR
+        EDMA3_HWI_INT_TC3_ERR,
+        0,
+        0,
+        0,
+        0
     }
 };
 
index 9705fbc07237656e5c2f481f6b506a04f5d8cd85..b5c8a99809b2864b4ee2c4a4b34669cc94905e90 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * sample_tda2xx_int_reg.c
+ * sample_dra72x_int_reg.c
  *
  * Platform specific interrupt registration and un-registration routines.
  *
@@ -60,30 +60,30 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorInt[];
-extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
-extern uint32_t numEdma3Tc[];
-extern uint32_t ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
-extern uint32_t ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorIntXbarInstNo[];
-extern uint32_t ccErrEdmaXbarIndex[];
-extern uint32_t tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
-extern uint32_t tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t ccXferCompIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccCompEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t ccErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorIntXbarInstNo[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t tcErrEdmaXbarIndex[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern uint32_t hwIntXferComp[];
-extern uint32_t hwIntCcErr[];
-extern uint32_t hwIntTcErr[];
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
 
 extern uint32_t dsp_num;
 
 /* External Instance Specific Configuration Structure */
-extern EDMA3_DRV_GblXbarToChanConfigParams
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+extern EDMA3_DRV_GblXbarToChanConfigParams 
+                                                               sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
 
 typedef struct  {
     volatile Uint32 TPCC_EVTMUX[32];
@@ -114,6 +114,14 @@ EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
                                   uint32_t chanNum);
 
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
+                                   uint32_t edma3Id);
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (uint32_t edma3Id);
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (uint32_t edma3Id);
+
 
 /**  To Register the ISRs with the underlying OS, if required. */
 void registerEdma3Interrupts (uint32_t edma3Id)
@@ -136,13 +144,13 @@ void registerEdma3Interrupts (uint32_t edma3Id)
     /* Enable the Xfer Completion Event Interrupt */
     EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
                                                (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
-                               edma3Id, 1);
+                               edma3Id, (Bool)1);
     EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
 
     /* Enable the CC Error Event Interrupt */
     EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
                                                (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
-                                               edma3Id, 1);
+                                               edma3Id, (Bool)1);
     EventCombiner_enableEvent(ccErrorInt[edma3Id]);
 
     /* Enable the TC Error Event Interrupt, according to the number of TCs. */
@@ -150,7 +158,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
            {
         EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
                             (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
-                            edma3Id, 1);
+                            edma3Id, (Bool)1);
         EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
         numTc++;
        }
@@ -180,11 +188,11 @@ void registerEdma3Interrupts (uint32_t edma3Id)
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
-       static UInt32 cookie = 0;
+       static UInt32 cookiee = 0;
     uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
-    cookie = Hwi_disable();
+    cookiee = Hwi_disable();
 
     /* Disable the Xfer Completion Event Interrupt */
        EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
@@ -200,7 +208,7 @@ void unregisterEdma3Interrupts (uint32_t edma3Id)
        }
 
     /* Restore interrupts */
-    Hwi_restore(cookie);
+    Hwi_restore(cookiee);
     }
 
 /**
@@ -256,17 +264,17 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
                (chanNum < EDMA3_NUM_TCC))
                {
-               scrRegOffset = chanNum / 2;
-               scrChanOffset = chanNum - (scrRegOffset * 2);
-               xBarEvtNum = eventNum  + 1;
-
+               scrRegOffset = chanNum / 2U;
+               scrChanOffset = chanNum - (scrRegOffset * 2U);
+               xBarEvtNum = eventNum  + 1U;
+               
                switch(scrChanOffset)
                        {
                        case 0:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
                                break;
-                       case 1:
+                       case 1U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));