Misc changes in EDMA3 Driver
authorAnuj Aggarwal <anuj.aggarwal@ti.com>
Thu, 20 Aug 2009 05:31:27 +0000 (11:01 +0530)
committerAnuj Aggarwal <anuj.aggarwal@ti.com>
Thu, 20 Aug 2009 05:31:27 +0000 (11:01 +0530)
- license header change
- dynamic ranges of logical channels
- internal data structures now 2D to handle multiple EDMA3 hardwares
- edma3MemSet -> edma3MemZero
- EDMA3_DRV_requestChannel cleaned and modified to take new requests
- Link channel API modified so that it doesn't clear the TCC code of link
channels having their own TCC values
- Added New APIs:
EDMA3_DRV_registerTccCb
EDMA3_DRV_unregisterTccCb
EDMA3_DRV_setTcErrorInt
EDMA3_DRV_getChannelStatus
EDMA3_DRV_mapTccLinkCh
- Big Endian change
- Misc changes done to clean-up the code

packages/ti/sdo/edma3/drv/edma3_drv.h
packages/ti/sdo/edma3/drv/src/edma3.h
packages/ti/sdo/edma3/drv/src/edma3_drv_adv.c
packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c
packages/ti/sdo/edma3/drv/src/edma3_drv_init.c

index 780e8e2f5654d44f877681482754e56ac5a9882b..9bfcdddcf2ac17252b919253c512c658698b663a 100644 (file)
@@ -1,91 +1,42 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**|                            ****                                          |**
-**|                            ****                                          |**
-**|                            ******o***                                    |**
-**|                      ********_///_****                                   |**
-**|                      ***** /_//_/ ****                                   |**
-**|                       ** ** (__/ ****                                    |**
-**|                           *********                                      |**
-**|                            ****                                          |**
-**|                            ***                                           |**
-**|                                                                          |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
-**|                        ALL RIGHTS RESERVED                               |**
-**|                                                                          |**
-**| Permission is hereby granted to licensees of Texas Instruments           |**
-**| Incorporated (TI) products to use this computer program for the sole     |**
-**| purpose of implementing a licensee product based on TI products.         |**
-**| No other rights to reproduce, use, or disseminate this computer          |**
-**| program, whether in part or in whole, are granted.                       |**
-**|                                                                          |**
-**| TI makes no representation or warranties with respect to the             |**
-**| performance of this computer program, and specifically disclaims         |**
-**| any responsibility for any damages, special or consequential,            |**
-**| connected with the use of this program.                                  |**
-**|                                                                          |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/** \file   edma3_drv.h
-    \brief  EDMA3 Controller
-
-    This file contains Application Interface for the EDMA3 Driver. EDMA3 Driver
-    uses the EDMA3 Resource Manager internally for resource allocation,
-    interrupt handling and EDMA3 registers programming.
-
-    (C) Copyright 2006, Texas Instruments, Inc
-
-    \version    0.0.1   Purushotam Kumar    - Created
-                0.1.0   Joseph Fernandez    - Made generic
-                                            - Added documentation
-                                            - Moved SoC specific defines
-                                            to SoC specific header.
-                0.2.0     Anuj Aggarwal     - Modified it for EDMA3 package
-                                            - Added multiple instances
-                                            capability
-                0.2.1     Anuj Aggarwal     - Modified it for more run time
-                                            configuration.
-                                            - Made EDMA3 package OS
-                                            independent.
-                0.2.2     Anuj Aggarwal     - Critical section handling code
-                                            modification. Uses semaphore and
-                                            interrupts disabling mechanism
-                                            for resource sharing.
-                0.3.0     Anuj Aggarwal     - Renamed EDMA3_DVR to EDMA3_DRV
-                                            - IPR bit clearing in RM ISR
-                                              issue fixed.
-                                            - Sample application made generic
-                0.3.1     Anuj Aggarwal     - Added DMA/QDMA Channel to TCC
-                                              mapping, to fix QDMA missed
-                                              event issue.
-                0.3.2     Anuj Aggarwal     - Added support for POLL mode
-                                            - Added a new API to modify the
-                                              CC Register.
-                1.0.0     Anuj Aggarwal     - Fixed resource allocation related
-                                              bugs.
-                1.0.0.1     Anuj Aggarwal   - Fixed spurious missed event
-                                              generation related bug.
-                1.0.0.2     Anuj Aggarwal   - Made the EDMA3 package RTSC
-                                              compliant.
-                1.0.0.3     Anuj Aggarwal   - Changed the directory structure
-                                              as per RTSC standard.
-                1.01.00.01  Anuj Aggarwal   - a) Added new APIs to allocate
-                                              logical channels
-                                              b) Created EDMA3 config files
-                                              for different platforms
-                                              c) Misc changes
-                1.02.00.01  Anuj Aggarwal   - a) Added DM6467 support
-                                              b) Fixed some MRs
-                1.03.00.01  Anuj Aggarwal   - a) Added non-RTSC PJT files
-                                              b) IOCTL Interface added.
-                                              c) Fixed some MRs.
-                1.04  Anuj Aggarwal         - a) Header files modified to have
-                                                extern "C" declarations.
-                                              b) Implemented ECNs DPSP00009815
-                                                & DPSP00010035.
-
- */
+/*
+ * edma3_drv.h
+ *
+ * This file contains Application Interface for the EDMA3 Driver. EDMA3 Driver
+ * uses the EDMA3 Resource Manager internally for resource allocation, interrupt
+ * handling and EDMA3 registers programming.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
 
 #ifndef _EDMA3_DRV_H_
 #define _EDMA3_DRV_H_
@@ -615,10 +566,10 @@ typedef struct  {
      * any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA
      * channel (like QDMA Channels).
      */
-    unsigned short      dmaChPaRAMMapExists;
+    unsigned int               dmaChPaRAMMapExists;
 
     /** Existence of memory protection feature */
-    unsigned short      memProtectionExists;
+    unsigned int               memProtectionExists;
 
     /** Base address of EDMA3 CC memory mapped registers. */
     void                *globalRegs;
@@ -843,7 +794,7 @@ typedef struct
      * region associated with this master instance will receive the EDMA3
      * interrupts (if enabled).
      */
-    unsigned short          isMaster;
+    unsigned int                       isMaster;
 
     /**
      * EDMA3 resources related shadow region specific information. Which all
@@ -1066,6 +1017,14 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * PaRAM Sets will be chosen and returned.
  */
 #define EDMA3_DRV_LINK_CHANNEL                      1005u
+
+/**
+ * Used to specify any available PaRAM Set while requesting
+ * one. Used in the API EDMA3_DRV_requestChannel(), for Link channels.
+ * PaRAM Set from the pool of (owned && non_reserved && available_right_now)
+ * PaRAM Sets will be chosen and returned.
+ */
+#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC                                1006u
 /*---------------------------------------------------------------------------*/
 
 
@@ -1404,11 +1363,11 @@ EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
 
 
 /**
- *  \brief  Disables the DMA Channel by clearing the Event Enable Register and 
+ *  \brief  Disables the DMA Channel by clearing the Event Enable Register and
  *     clears Error Register & Secondary Event Register for a specific DMA channel.
  *
  *  This API clears the Event Enable register, Event Miss register and Secondary
- *     Event register for a specific DMA channel. It also clears the CC Error 
+ *     Event register for a specific DMA channel. It also clears the CC Error
  *     register.
  *
  *  \param  hEdma            [IN]     Handle to the EDMA Driver Instance.
@@ -2095,20 +2054,22 @@ EDMA3_DRV_Result EDMA3_DRV_setTransferParams (
 /**
  * \brief   Chain the two specified channels.
  *
- * This API is used to chain two previously allocated logical (DMA/QDMA)
- * channels.
+ * This API is used to chain a DMA channel to a previously allocated DMA/QDMA
+ * channel.
  *
  * Chaining is different from Linking. The EDMA3 link feature reloads the
  * current channel parameter set with the linked parameter set. The EDMA3
  * chaining feature does not modify or update any channel parameter set;
- * it provides a synchronization event to the chained channel.
+ * it provides a synchronization event (or trigger) to the chained DMA channel,
+ * as soon as the transfer (final or intermediate) completes on the main
+ * DMA/QDMA channel.
  *
  * \param   hEdma               [IN]    Handle to the EDMA Driver Instance.
  *
- * \param   lCh1                [IN]    Channel to which particular channel
- *                                      will be chained.
- * \param   lCh2                [IN]    Channel which needs to be chained to
- *                                      the first channel.
+ * \param   lCh1                [IN]    DMA/QDMA channel to which a particular
+ *                                      DMA channel will be chained.
+ * \param   lCh2                [IN]    DMA channel which needs to be chained to
+ *                                      the first DMA/QDMA channel.
  * \param   chainOptions        [IN]    Options such as intermediate interrupts
  *                                      are required or not, intermediate/final
  *                                      chaining is enabled or not etc.
@@ -2247,12 +2208,12 @@ EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
 /**
  * \brief Disable the event driven DMA channel or QDMA channel
  *
- * This API disables the DMA channel (which was previously triggered in event 
+ * This API disables the DMA channel (which was previously triggered in event
  * mode) by clearing the Event Enable Register; it disables the QDMA channel by
  * clearing the QDMA Event Enable Register.
  *
  * This API should NOT be used for DMA channels which are not mapped to any
- * hardware events and are used for memory-to-memory copy based transfers. In 
+ * hardware events and are used for memory-to-memory copy based transfers. In
  * case of that, this API returns error.
  *
  * \param   hEdma       [IN]    Handle to the EDMA Driver Instance
@@ -2488,6 +2449,8 @@ typedef struct  {
  * This is a mapping of the EDMA3 PaRAM set provided to the user
  * for ease of modification of the individual fields
  */
+#ifndef BIG_ENDIAN_MODE
+/* LITTLE_ENDIAN_MODE */
 typedef struct  {
         /** OPT field of PaRAM Set */
         volatile unsigned int opt;
@@ -2560,7 +2523,85 @@ typedef struct  {
         volatile unsigned short cCnt;
 
 } EDMA3_DRV_PaRAMRegs;
+#else
+/* BIG_ENDIAN_MODE */
+typedef struct  {
+        /** OPT field of PaRAM Set */
+        volatile unsigned int opt;
+
+        /**
+         * \brief Starting byte address of Source
+         * For FIFO mode, srcAddr must be a 256-bit aligned address.
+         */
+        volatile unsigned int srcAddr;
+
+        /**
+         * \brief Number of Arrays in each Frame (BCNT)
+         */
+        volatile unsigned short bCnt;
+
+        /**
+         * \brief Number of bytes in each Array (ACNT)
+         */
+        volatile unsigned short aCnt;
+
+        /**
+         * \brief Starting byte address of destination
+         * For FIFO mode, destAddr must be a 256-bit aligned address.
+         * i.e. 5 LSBs should be 0.
+         */
+        volatile unsigned int destAddr;
+
+        /**
+         * \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
+         * If DAM is set to 1 (via channelOptions) then destInterArrIndex should
+         * be an even multiple of 32 bytes
+         */
+        volatile short  destBIdx;
+
+        /**
+         * \brief Index between consec. arrays of a Source Frame (SRCBIDX)
+         * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
+         * be an even multiple of 32 bytes.
+         */
+        volatile short  srcBIdx;
+
+        /**
+         * \brief Reload value of the numArrInFrame (BCNT)
+         * Relevant only for A-sync transfers
+         */
+        volatile unsigned short bCntReload;
+
+        /**
+         * \brief Address for linking (AutoReloading of a PaRAM Set)
+         * This must point to a valid aligned 32-byte PaRAM set
+         * A value of 0xFFFF means no linking
+         * Linking is especially useful for use with ping-pong buffers and
+         * circular buffers
+         */
+        volatile unsigned short linkAddr;
 
+        /**
+         * \brief Index between consecutive frames of a Dest Block (DSTCIDX)
+         */
+        volatile short  destCIdx;
+
+        /**
+         * \brief Index between consecutive frames of a Source Block (SRCCIDX)
+         */
+        volatile short  srcCIdx;
+
+        /**
+         * \brief Reserved
+         */
+        volatile short  reserved;
+
+        /**
+         * \brief Number of Frames in a block (CCNT)
+         */
+        volatile unsigned short cCnt;
+} EDMA3_DRV_PaRAMRegs;
+#endif         /* #ifndef BIG_ENDIAN_MODE */
 
 /**
  * \brief Event queue priorities setup
@@ -3043,6 +3084,178 @@ EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId,
                                                                EDMA3_DRV_Result *errorCode);
 
 
+/**
+ * \brief   Registers a transfer completion handler for a specific DMA/QDMA
+ *                     channel
+ *
+ * This function registers a non-NULL callback function for a specific DMA or QDMA
+ * channel and enables the completion interrupt for the TCC associated with
+ * the underlying channel in the IER/IERH register. If user enables the transfer
+ * completion interrupts (intermediate or final) in the associated PaRAM Set,
+ * the registered callback function will be called by the EDMA3 driver.
+ *
+ * If a call-back function is already registered for the channel, the API fails
+ * with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.
+ *
+ * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param  channelId           [IN]    DMA/QDMA channel for which the callback
+ *                                                                             function needs to be registered.
+ * \param   tccCb               [IN]    The callback function to be registered.
+ * \param   cbData              [IN]    Callback data to be passed while calling
+ *                                      the callback function.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique channelId values. It is non-
+ *          re-entrant for same channelId value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_registerTccCb(EDMA3_DRV_Handle hEdma,
+                    const unsigned int channelId,
+                    EDMA3_RM_TccCallback tccCb,
+                    void *cbData);
+
+/**
+ * \brief   Un-register the previously registered callback function against a
+ *          DMA/QDMA channel.
+ *
+ * This function unregisters the previously registered callback function against
+ * a DMA/QDMA channel by removing any stored callback function. Moreover, it
+ * clears the interrupt enable register (IER/IERH) by writing to the IECR/
+ * IECRH register, for the TCC associated with that particular channel.
+ *
+ * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param  channelId           [IN]    DMA/QDMA channel for which the callback
+ *                                                                             function needs to be un-registered.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code.
+ *
+ * \note    This function is re-entrant for unique channelId. It is
+ *                     non-re-entrant for same channelId.
+ */
+EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb(EDMA3_DRV_Handle hEdma,
+                    const unsigned int channelId);
+
+
+/**\enum    EDMA3_DRV_Tc_Err
+ * \brief   TC Error Enablers
+ *
+ * Use this enum to enable/disable the specific EDMA3 Transfer Controller
+ * Interrupt.
+ */
+typedef enum
+{
+       /**
+        * Interrupt disable for bus error
+        */
+       EDMA3_DRV_TC_ERR_BUSERR_DIS = 0,
+
+       /**
+        * Interrupt enable for bus error
+        */
+       EDMA3_DRV_TC_ERR_BUSERR_EN,
+
+       /**
+        * Interrupt disable for transfer request error
+        */
+       EDMA3_DRV_TC_ERR_TRERR_DIS,
+
+       /**
+        * Interrupt enable for transfer request error
+        */
+       EDMA3_DRV_TC_ERR_TRERR_EN,
+
+       /**
+        * Interrupt disable for MMR address error
+        */
+       EDMA3_DRV_TC_ERR_MMRAERR_DIS,
+
+       /**
+        * Interrupt enable for MMR address error
+        */
+       EDMA3_DRV_TC_ERR_MMRAERR_EN,
+
+       /**
+        * Disable all TC error interrupts
+        */
+       EDMA3_DRV_TC_ERR_DIS,
+
+       /**
+        * Enable all TC error interrupts
+        */
+       EDMA3_DRV_TC_ERR_EN
+} EDMA3_DRV_Tc_Err;
+
+
+/**
+ * \brief   Un-register the previously registered callback function against a
+ *          DMA/QDMA channel.
+ *
+ * This function unregisters the previously registered callback function against
+ * a DMA/QDMA channel by removing any stored callback function. Moreover, it
+ * clears the interrupt enable register (IER/IERH) by writing to the IECR/
+ * IECRH register, for the TCC associated with that particular channel.
+ *
+ * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param  channelId           [IN]    DMA/QDMA channel for which the callback
+ *                                                                             function needs to be un-registered.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code.
+ *
+ * \note    This function is re-entrant for unique channelId. It is
+ *                     non-re-entrant for same channelId.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(unsigned int phyCtrllerInstId,
+                                       unsigned int tcId,
+                                       EDMA3_DRV_Tc_Err tcErr);
+
+
+#define EDMA3_DRV_CHANNEL_CLEAN                                0x0000u
+#define EDMA3_DRV_CHANNEL_EVENT_PENDING                0x0001u
+#define EDMA3_DRV_CHANNEL_XFER_COMPLETE                0x0002u
+#define EDMA3_DRV_CHANNEL_ERR                          0x0004u
+
+/**
+ * \brief   Un-register the previously registered callback function against a
+ *          DMA/QDMA channel.
+ *
+ * This function unregisters the previously registered callback function against
+ * a DMA/QDMA channel by removing any stored callback function. Moreover, it
+ * clears the interrupt enable register (IER/IERH) by writing to the IECR/
+ * IECRH register, for the TCC associated with that particular channel.
+ *
+ * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param  channelId           [IN]    DMA/QDMA channel for which the callback
+ *                                                                             function needs to be un-registered.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code.
+ *
+ * \note    This function is re-entrant for unique channelId. It is
+ *                     non-re-entrant for same channelId.
+ */
+EDMA3_DRV_Result EDMA3_DRV_getChannelStatus(EDMA3_DRV_Handle hEdma,
+                        unsigned int lCh, unsigned int *lchStatus);
+
+
+/**
+ * \brief  Associates a link channel and a TCC
+ *
+ * This API is used to map a TCC to a LINK channel. It should be used with LINK
+ * channels ONLY else it will fail.
+ *
+ * \param   hEdma           [IN]    Handle to the EDMA Driver Instance.
+ * \param   linkCh          [IN]    Link Channel to which a particular TCC
+ *                                  needs to be mapped.
+ * \param   tcc             [IN]    TCC which needs to be mapped
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique linkCh values. It is
+ *          non-re-entrant for same linkCh values.
+ */
+EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh ( EDMA3_DRV_Handle hEdma,
+                                                unsigned int linkCh,
+                                                unsigned int tcc);
+
 
 /* @} Edma3DrvTransferSetupOpt */
 
@@ -3054,3 +3267,4 @@ EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId,
 #endif /* extern "C" */
 
 #endif         /* _EDMA3_DRV_H_ */
+
index 7fae38a3922f8410ed09d2c9581384467a1a2649..7955ceb3a6f4960acbe8adfe632031c7a4ef6f89 100644 (file)
@@ -1,41 +1,40 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**|                            ****                                          |**
-**|                            ****                                          |**
-**|                            ******o***                                    |**
-**|                      ********_///_****                                   |**
-**|                      ***** /_//_/ ****                                   |**
-**|                       ** ** (__/ ****                                    |**
-**|                           *********                                      |**
-**|                            ****                                          |**
-**|                            ***                                           |**
-**|                                                                          |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
-**|                        ALL RIGHTS RESERVED                               |**
-**|                                                                          |**
-**| Permission is hereby granted to licensees of Texas Instruments           |**
-**| Incorporated (TI) products to use this computer program for the sole     |**
-**| purpose of implementing a licensee product based on TI products.         |**
-**| No other rights to reproduce, use, or disseminate this computer          |**
-**| program, whether in part or in whole, are granted.                       |**
-**|                                                                          |**
-**| TI makes no representation or warranties with respect to the             |**
-**| performance of this computer program, and specifically disclaims         |**
-**| any responsibility for any damages, special or consequential,            |**
-**| connected with the use of this program.                                  |**
-**|                                                                          |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/** \file   edma3.h
-    \brief  EDMA3 Driver Internal header file.
-
-    This file contains implementation specific details used by the EDMA3
-    Driver internally.
-
-    (C) Copyright 2006, Texas Instruments, Inc
-
- */
+/*
+ * edma3.h
+ *
+ * EDMA3 Driver Internal header file.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
 
 #ifndef _EDMA3_H_
 #define _EDMA3_H_
@@ -149,11 +148,21 @@ extern "C" {
 
 
 /* Other Mask defines */
+/** DCHMAP-PaRAMEntry bitfield Clear */
+#define EDMA3_DRV_DCH_PARAM_CLR_MASK                (~EDMA3_CCRL_DCHMAP_PAENTRY_MASK)
+/** DCHMAP-PaRAMEntry bitfield Set */
+#define EDMA3_DRV_DCH_PARAM_SET_MASK(paRAMId)       (((EDMA3_CCRL_DCHMAP_PAENTRY_MASK >> EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT)
+
+/** QCHMAP-PaRAMEntry bitfield Clear */
+#define EDMA3_DRV_QCH_PARAM_CLR_MASK                (~EDMA3_CCRL_QCHMAP_PAENTRY_MASK)
+/** QCHMAP-PaRAMEntry bitfield Set */
+#define EDMA3_DRV_QCH_PARAM_SET_MASK(paRAMId)       (((EDMA3_CCRL_QCHMAP_PAENTRY_MASK >> EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT)
 /** QCHMAP-TrigWord bitfield Clear */
 #define EDMA3_DRV_QCH_TRWORD_CLR_MASK               (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
 /** QCHMAP-TrigWord bitfield Set */
-#define EDMA3_DRV_QCH_TRWORD_SET_MASK(paRAMId)      (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
-
+#define EDMA3_DRV_QCH_TRWORD_SET_MASK(trWord)      (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (trWord)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
+/** QCHMAP-PaRAMEntry & TrigWord bitfield Clear */
+#define EDMA3_DRV_QCH_PARAM_TRWORD_CLR_MASK         (EDMA3_DRV_QCH_PARAM_CLR_MASK | EDMA3_DRV_QCH_TRWORD_CLR_MASK)
 
 /** Max value of ACnt */
 #define EDMA3_DRV_ACNT_MAX_VAL              (0xFFFFu)
@@ -184,38 +193,6 @@ extern "C" {
 /** Min value of Queue Priority */
 #define EDMA3_DRV_QPRIORITY_MIN_VAL         (0u)
 
-
-
-
-/**
- * \defgroup Edma3DrvIntBoundVals Boundary Values
- *
- * Boundary Values for Logical Channel Ranges
- *
- * @{
- */
-/** Max of DMA Channels */
-#define EDMA3_DRV_DMA_CH_MAX_VAL        (EDMA3_MAX_DMA_CH - 1u)
-
-/** Min of Link Channels */
-#define EDMA3_DRV_LINK_CH_MIN_VAL       (EDMA3_DRV_DMA_CH_MAX_VAL + 1u)
-
-/** Max of Link Channels */
-#define EDMA3_DRV_LINK_CH_MAX_VAL       (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u)
-
-/** Min of QDMA Channels */
-#define EDMA3_DRV_QDMA_CH_MIN_VAL       (EDMA3_DRV_LINK_CH_MAX_VAL + 1u)
-
-/** Max of QDMA Channels */
-#define EDMA3_DRV_QDMA_CH_MAX_VAL       (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u)
-
-/** Max of Logical Channels */
-#define EDMA3_DRV_LOG_CH_MAX_VAL       (EDMA3_DRV_QDMA_CH_MAX_VAL)
-
-
-/* @} Edma3DrvIntBoundVals */
-
-
 /**
  * \defgroup Edma3DrvIntObjMaint Object Maintenance
  *
@@ -287,7 +264,7 @@ typedef struct
      * Only the master instance shadow region will receive the
      * EDMA3 interrupts, if enabled.
      */
-    unsigned short          isMaster;
+    unsigned int               isMaster;
 
     /**
      * EDMA3 Driver Instance (Shadow Region) specific
@@ -348,7 +325,7 @@ typedef struct {
 typedef enum
 {
     /** Invalid Channel */
-    EDMA3_DRV_CHANNEL_TYPE_NONE,
+    EDMA3_DRV_CHANNEL_TYPE_NONE                = 0,
 
     /** DMA Channel */
     EDMA3_DRV_CHANNEL_TYPE_DMA      = 1,
@@ -357,21 +334,23 @@ typedef enum
     EDMA3_DRV_CHANNEL_TYPE_QDMA     = 2,
 
     /** LINK Channel */
-    EDMA3_DRV_CHANNEL_TYPE_LINK     = 3
+    EDMA3_DRV_CHANNEL_TYPE_LINK     = 3,
 
+    /** LINK Channel with TCC */
+    EDMA3_DRV_CHANNEL_TYPE_LINK_TCC    = 4
 } EDMA3_DRV_ChannelType;
 
 
 /**
  * \brief Event Queue Number for DMA/QDMA Channels.
  *
- * If EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME is defined, then the queue 
- * number registers for DMA/QDMA channels will be programmed during init time 
- * only; the queue number registers will NOT be changed during run-time to 
- * avoid (potential) race conditions. The following arrays will be used to 
+ * If EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME is defined, then the queue
+ * number registers for DMA/QDMA channels will be programmed during init time
+ * only; the queue number registers will NOT be changed during run-time to
+ * avoid (potential) race conditions. The following arrays will be used to
  * program the DMA/QDMA queue number registers.
  *
- * User has to provide the array values depending on the resources' 
+ * User has to provide the array values depending on the resources'
  * availability and the system requirements.
  *
  */
index 0b2da37097c580c7d98358f687b940e03513945a..9f9fa106e82aaba47a2646692c221e82b79013b0 100644 (file)
@@ -1,52 +1,52 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**|                            ****                                          |**
-**|                            ****                                          |**
-**|                            ******o***                                    |**
-**|                      ********_///_****                                   |**
-**|                      ***** /_//_/ ****                                   |**
-**|                       ** ** (__/ ****                                    |**
-**|                           *********                                      |**
-**|                            ****                                          |**
-**|                            ***                                           |**
-**|                                                                          |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
-**|                        ALL RIGHTS RESERVED                               |**
-**|                                                                          |**
-**| Permission is hereby granted to licensees of Texas Instruments           |**
-**| Incorporated (TI) products to use this computer program for the sole     |**
-**| purpose of implementing a licensee product based on TI products.         |**
-**| No other rights to reproduce, use, or disseminate this computer          |**
-**| program, whether in part or in whole, are granted.                       |**
-**|                                                                          |**
-**| TI makes no representation or warranties with respect to the             |**
-**| performance of this computer program, and specifically disclaims         |**
-**| any responsibility for any damages, special or consequential,            |**
-**| connected with the use of this program.                                  |**
-**|                                                                          |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/**
-*      \file           edma3_drv_adv.c
-*
-*   \brief      EDMA3 Driver Advanced Interface Implementation
-*   This file contains advanced-level EDMA3 Driver APIs which are required
-*      to:
-*      a) Link and chain two channels.
-*              b) Set/get the whole PaRAM Set in one shot.
-*              c) Set/get each individual field of the PaRAM Set.
-*      d) Poll mode APIs.
-*              e) IOCTL interface.
-*      These APIs are provided to have complete control on the EDMA3 hardware and
-*      normally advanced users are expected to use them for their specific use-cases.
-*
-*      @author: PSP Team, TII
-*
+/*
+ * edma3_drv_adv.c
+ *
+ * EDMA3 Driver Advanced Interface Implementation. This file contains
+ * advanced-level EDMA3 Driver APIs which are required to:
+ * a) Link and chain two channels.
+ * b) Set/get the whole PaRAM Set in one shot.
+ * c) Set/get each individual field of the PaRAM Set.
+ * d) Poll mode APIs.
+ * e) IOCTL interface.
+ * These APIs are provided to have complete control on the EDMA3 hardware and
+ * normally advanced users are expected to use them for their specific
+ * use-cases.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
 */
 
 
-/* EDMa3 Driver Internal Header Files */
+/* EDMA3 Driver Internal Header Files */
 #include <ti/sdo/edma3/drv/src/edma3.h>
 /* Resource Manager Internal Header Files */
 #include <ti/sdo/edma3/rm/src/edma3resmgr.h>
@@ -95,8 +95,8 @@ extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
  */
 extern EDMA3_RM_Instance *ptrRMIArray;
 
-/** Local MemSet function */
-extern void edma3MemSet(void *dst, unsigned char data, unsigned int len);
+/** Local MemZero function */
+extern void edma3MemZero(void *dst, unsigned int len);
 /** Local MemCpy function to copy PaRAM Set ONLY */
 extern void edma3ParamCpy(void *dst, const void *src);
 
@@ -131,6 +131,19 @@ extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGI
  */
 extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
 
+/** Max of DMA Channels */
+extern unsigned int edma3_dma_ch_max_val[];
+/** Min of Link Channels */
+extern unsigned int edma3_link_ch_min_val[];
+/** Max of Link Channels */
+extern unsigned int edma3_link_ch_max_val[];
+/** Min of QDMA Channels */
+extern unsigned int edma3_qdma_ch_min_val[];
+/** Max of QDMA Channels */
+extern unsigned int edma3_qdma_ch_max_val[];
+/** Max of Logical Channels */
+extern unsigned int edma3_log_ch_max_val[];
+
 
 /**
  * \brief  Link two logical channels.
@@ -179,6 +192,7 @@ EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma,
     unsigned int optVal = 0;
     unsigned int newOptVal = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -190,9 +204,7 @@ EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if (((lCh1 > EDMA3_DRV_LOG_CH_MAX_VAL)
-       || (lCh2 > EDMA3_DRV_LOG_CH_MAX_VAL))
-        || (hEdma == NULL))
+    if (hEdma == NULL)
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -210,49 +222,67 @@ EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma,
             }
         else
             {
-            paRAM1Id = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh1].paRAMId;
-            paRAM2Id = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh2].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+                       }
+               }
 
-            if ((paRAM1Id < 0) || (paRAM1Id >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if ((lCh1 > edma3_log_ch_max_val [edma3Id])
+               || (lCh2 > edma3_log_ch_max_val [edma3Id]))
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
-            if ((paRAM2Id < 0) || (paRAM2Id >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAM1Id = edma3DrvChBoundRes[edma3Id][lCh1].paRAMId;
+        paRAM2Id = edma3DrvChBoundRes[edma3Id][lCh2].paRAMId;
 
-            if (result == EDMA3_DRV_SOK)
-                {
-                /* Get the Link-bcntReload PaRAM set entry */
-                linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAM1Id].OPT) +
-                                    (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
-                linkBcntReld &= 0xFFFF0000u;
-                /* Update the Link field with lch2 PaRAM set */
-                linkBcntReld |= (0xFFFFu & (unsigned int)(&(globalRegs->PARAMENTRY [paRAM2Id].OPT)));
-
-                /* Store it back */
-                *((&globalRegs->PARAMENTRY[paRAM1Id].OPT)
-                            + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;
-
-                /*
-                * Set the TCC field of PaRAM set associated with lch2 to
-                * the same as that of lch1.
-                */
-                /* for channel 1 */
-                optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAM1Id].OPT));
-                oldTccVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal);
-
-                /* for channel 2 */
-                optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAM2Id].OPT));
-                newOptVal = (optVal & EDMA3_DRV_OPT_TCC_CLR_MASK)
-                            |
-                            (EDMA3_DRV_OPT_TCC_SET_MASK(oldTccVal));
-                *(&globalRegs->PARAMENTRY[paRAM2Id].OPT) = newOptVal;
-                }
+        if ((paRAM1Id < 0) || (paRAM1Id >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+
+        if ((paRAM2Id < 0) || (paRAM2Id >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
             }
+               }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Get the Link-bcntReload PaRAM set entry */
+        linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAM1Id].OPT) +
+                            (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
+        linkBcntReld &= 0xFFFF0000u;
+        /* Update the Link field with lch2 PaRAM set */
+        linkBcntReld |= (0xFFFFu & (unsigned int)(&(globalRegs->PARAMENTRY [paRAM2Id].OPT)));
+
+        /* Store it back */
+        *((&globalRegs->PARAMENTRY[paRAM1Id].OPT)
+                    + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;
+
+        /*
+        * Set the TCC field of PaRAM set associated with lch2 to
+        * the same as that of lch1. This should be done ONLY when
+        * lch2 is NOT associated with any other TCC.
+        */
+               if (edma3DrvChBoundRes[edma3Id][lCh2].tcc == EDMA3_MAX_TCC)
+               {
+               /* for channel 1 */
+               optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAM1Id].OPT));
+               oldTccVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal);
+
+               /* for channel 2 */
+               optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAM2Id].OPT));
+               newOptVal = (optVal & EDMA3_DRV_OPT_TCC_CLR_MASK)
+                           |
+                           (EDMA3_DRV_OPT_TCC_SET_MASK(oldTccVal));
+               *(&globalRegs->PARAMENTRY[paRAM2Id].OPT) = newOptVal;
+                       }
         }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
@@ -266,8 +296,6 @@ EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma,
     return result;
     }
 
-
-
 /**
  * \brief  Unlink the channel from the earlier linked logical channel.
  *
@@ -291,6 +319,7 @@ EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int l
     EDMA3_DRV_Instance *drvInst = NULL;
     EDMA3_DRV_Object *drvObject = NULL;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -302,7 +331,7 @@ EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int l
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
+    if (hEdma == NULL)
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -320,29 +349,40 @@ EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int l
             }
         else
             {
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
-
-            if (result == EDMA3_DRV_SOK)
-                {
-                /* Get the Link-bcntReload PaRAM set entry */
-                linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +
-                                                        (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
-
-                /* Remove any linking */
-                linkBcntReld |= 0xFFFFu;
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
-                /* Store it back */
-                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
-                            + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;
-                }
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+               else
+               {
+               /* Get the Link-bcntReload PaRAM set entry */
+               linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+                                                       + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
+
+               /* Remove any linking */
+               linkBcntReld |= 0xFFFFu;
+
+               /* Store it back */
+               *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+                           + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;
+               }
+               }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -355,24 +395,25 @@ EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int l
     return result;
     }
 
-
 /**
  * \brief   Chain the two specified channels.
  *
- * This API is used to chain two previously allocated logical (DMA/QDMA)
- * channels.
+ * This API is used to chain a DMA channel to a previously allocated DMA/QDMA
+ * channel.
  *
  * Chaining is different from Linking. The EDMA3 link feature reloads the
  * current channel parameter set with the linked parameter set. The EDMA3
  * chaining feature does not modify or update any channel parameter set;
- * it provides a synchronization event to the chained channel.
+ * it provides a synchronization event (or trigger) to the chained DMA channel,
+ * as soon as the transfer (final or intermediate) completes on the main
+ * DMA/QDMA channel.
  *
  * \param   hEdma               [IN]    Handle to the EDMA Driver Instance.
  *
- * \param   lCh1                [IN]    Channel to which particular channel
- *                                      will be chained.
- * \param   lCh2                [IN]    Channel which needs to be chained to
- *                                      the first channel.
+ * \param   lCh1                [IN]    DMA/QDMA channel to which a particular
+ *                                      DMA channel will be chained.
+ * \param   lCh2                [IN]    DMA channel which needs to be chained to
+ *                                      the first DMA/QDMA channel.
  * \param   chainOptions        [IN]    Options such as intermediate interrupts
  *                                      are required or not, intermediate/final
  *                                      chaining is enabled or not etc.
@@ -393,6 +434,7 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -404,8 +446,7 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if (((lCh1 > EDMA3_DRV_LOG_CH_MAX_VAL) || (lCh2 > EDMA3_DRV_LOG_CH_MAX_VAL))
-        || (hEdma == NULL))
+    if (hEdma == NULL)
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -425,18 +466,30 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
             {
             result =  EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-    if (result == EDMA3_DRV_SOK)
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if ((lCh1 > edma3_log_ch_max_val [edma3Id])
+                       || (lCh2 > edma3_dma_ch_max_val [edma3Id]))
         {
-        paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh1].paRAMId;
-        globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh1].paRAMId;
         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+               }
 
     if (result == EDMA3_DRV_SOK)
         {
@@ -488,11 +541,10 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
         *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
 
         /* Set the trigger mode of lch2 as the same as of lch1 */
-        edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh2].trigMode =
-                    edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh1].trigMode;
+        edma3DrvChBoundRes[edma3Id][lCh2].trigMode =
+                    edma3DrvChBoundRes[edma3Id][lCh1].trigMode;
         }
 
-
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
@@ -504,8 +556,6 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
     return result;
     }
 
-
-
 /**
  * \brief   Unchain the two channels.
  *
@@ -527,6 +577,7 @@ EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -538,7 +589,7 @@ EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
+    if (hEdma == NULL)
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -553,18 +604,29 @@ EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,
             {
             result =  EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-    if (result == EDMA3_DRV_SOK)
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
         {
-        paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
-        globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+               }
 
     if (result == EDMA3_DRV_SOK)
         {
@@ -617,6 +679,7 @@ EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Instance *drvInst = NULL;
     EDMA3_DRV_Object *drvObject = NULL;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -629,10 +692,8 @@ EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
     if((hEdma == NULL)
-        || (((lCh < EDMA3_DRV_QDMA_CH_MIN_VAL)
-        || (lCh > EDMA3_DRV_QDMA_CH_MAX_VAL))
         || ((trigWord < EDMA3_RM_QDMA_TRIG_OPT)
-        || (trigWord > EDMA3_RM_QDMA_TRIG_CCNT))))
+        || (trigWord > EDMA3_RM_QDMA_TRIG_CCNT)))
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -650,11 +711,26 @@ EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,
             }
         else
             {
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-            globalRegs->QCHMAP[lCh -EDMA3_DRV_QDMA_CH_MIN_VAL] &= EDMA3_DRV_QCH_TRWORD_CLR_MASK;
-            globalRegs->QCHMAP[lCh -EDMA3_DRV_QDMA_CH_MIN_VAL] |= EDMA3_DRV_QCH_TRWORD_SET_MASK(trigWord);
-            }
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if ((lCh < edma3_qdma_ch_min_val[edma3Id])
+        || (lCh > edma3_qdma_ch_max_val[edma3Id]))
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        globalRegs->QCHMAP[lCh - edma3_qdma_ch_min_val[edma3Id]]
+                                       &= EDMA3_DRV_QCH_TRWORD_CLR_MASK;
+        globalRegs->QCHMAP[lCh - edma3_qdma_ch_min_val[edma3Id]]
+                                       |= EDMA3_DRV_QCH_TRWORD_SET_MASK(trigWord);
         }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
@@ -699,6 +775,7 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -710,8 +787,7 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
-        || (newPaRAM == NULL))
+    if ((hEdma == NULL) || (newPaRAM == NULL))
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -726,18 +802,29 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma,
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-    if (result == EDMA3_DRV_SOK)
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
         {
-        globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
-        paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+               }
 
     if (result == EDMA3_DRV_SOK)
         {
@@ -779,6 +866,7 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -790,8 +878,7 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
-        || (currPaRAM == NULL))
+    if ((hEdma == NULL) || (currPaRAM == NULL))
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -806,18 +893,29 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-    if (result == EDMA3_DRV_SOK)
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
         {
-        globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
-        paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+               }
 
     if (result == EDMA3_DRV_SOK)
         {
@@ -869,6 +967,7 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -880,7 +979,7 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if(((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
+    if((hEdma == NULL)
         || ((paRAMEntry < EDMA3_DRV_PARAM_ENTRY_OPT)
         || (paRAMEntry > EDMA3_DRV_PARAM_ENTRY_CCNT)))
         {
@@ -900,19 +999,32 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,
             }
         else
             {
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
-            else
-                {
-                *((&globalRegs->PARAMENTRY[paRAMId].OPT) + (unsigned int)paRAMEntry) = newPaRAMEntryVal;
-                }
-            }
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
         }
+#endif
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+        else
+            {
+            *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
+                                       (unsigned int)paRAMEntry) = newPaRAMEntryVal;
+            }
+               }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -951,6 +1063,7 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -962,10 +1075,13 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if(((lCh > EDMA3_DRV_LOG_CH_MAX_VAL)
-        || ((hEdma == NULL) || (paRAMEntryVal == NULL)))
-        || ((paRAMEntry < EDMA3_DRV_PARAM_ENTRY_OPT)
-        || (paRAMEntry > EDMA3_DRV_PARAM_ENTRY_CCNT)))
+    if((hEdma == NULL) || (paRAMEntryVal == NULL))
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+
+    if((paRAMEntry < EDMA3_DRV_PARAM_ENTRY_OPT)
+        || (paRAMEntry > EDMA3_DRV_PARAM_ENTRY_CCNT))
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -983,20 +1099,32 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,
             }
         else
             {
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
-            else
-                {
-                *paRAMEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned int)paRAMEntry));
-                }
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+               else
+            {
+            *paRAMEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+                                                                                                       + (unsigned int)paRAMEntry));
+            }
+               }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1044,6 +1172,7 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,
     unsigned int paramEntryVal = 0;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1055,23 +1184,6 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    /*
-    * THIS API IS NOT ALLOWED FOR QDMA CHANNELS.
-    * Reason being setting one PaRAM field might trigger the
-    * transfer if the word written happends to be the trigger
-    * word. One should use EDMA3_DRV_setPaRAMEntry ()
-    * API instead to write the whole 32 bit word.
-    */
-    if ((lCh >= EDMA3_DRV_QDMA_CHANNEL_0) && (lCh <= EDMA3_DRV_QDMA_CHANNEL_7))
-        {
-        result =  EDMA3_DRV_E_INVALID_PARAM;
-        }
-
-    if(lCh > EDMA3_DRV_LOG_CH_MAX_VAL)
-        {
-        result = EDMA3_DRV_E_INVALID_PARAM;
-        }
-
     if((hEdma == NULL)
         || ((paRAMField < EDMA3_DRV_PARAM_FIELD_OPT)
         || (paRAMField > EDMA3_DRV_PARAM_FIELD_CCNT)))
@@ -1089,19 +1201,42 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,
             {
             result =  EDMA3_DRV_E_INVALID_PARAM;
             }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
+
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    /*
+    * THIS API IS NOT ALLOWED FOR QDMA CHANNELS.
+    * Reason being setting one PaRAM field might trigger the
+    * transfer if the word written happends to be the trigger
+    * word. One should use EDMA3_DRV_setPaRAMEntry ()
+    * API instead to write the whole 32 bit word.
+    */
+    if ((lCh <= edma3_qdma_ch_min_val[edma3Id])
+                       && (lCh >= edma3_qdma_ch_max_val[edma3Id]))
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
         }
 
-    if (result == EDMA3_DRV_SOK)
+    if (lCh > edma3_log_ch_max_val [edma3Id])
         {
-        paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
-        globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
-
+               }
 
     if (result == EDMA3_DRV_SOK)
         {
@@ -1231,6 +1366,7 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
     unsigned int paramEntryVal = 0;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1242,10 +1378,13 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if(((lCh > EDMA3_DRV_LOG_CH_MAX_VAL)
-       || ((hEdma == NULL) || (currPaRAMFieldVal == NULL)))
-       || ((paRAMField < EDMA3_DRV_PARAM_FIELD_OPT)
-       || (paRAMField > EDMA3_DRV_PARAM_FIELD_CCNT)))
+    if ((hEdma == NULL) || (currPaRAMFieldVal == NULL))
+        {
+        result =  EDMA3_DRV_E_INVALID_PARAM;
+        }
+
+    if((paRAMField < EDMA3_DRV_PARAM_FIELD_OPT)
+       || (paRAMField > EDMA3_DRV_PARAM_FIELD_CCNT))
         {
         result =  EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -1260,18 +1399,29 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
             {
             result =  EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-    if (result == EDMA3_DRV_SOK)
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
         {
-        paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
-        globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
         if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+               }
 
     if (result == EDMA3_DRV_SOK)
         {
@@ -1430,7 +1580,9 @@ EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,
 
             if (result == EDMA3_DRV_SOK)
                 {
-                edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);
+                edma3OsProtectEntry (drvObject->phyCtrllerInstId,
+                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       &intState);
 
                 /* Set TC Priority among system-wide bus-masters and Queue Watermark Level */
                 evtQNum = 0;
@@ -1442,7 +1594,9 @@ EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,
                     evtQNum++;
                     }
 
-                edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
+                edma3OsProtectExit (drvObject->phyCtrllerInstId,
+                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       intState);
                 }
             }
         }
@@ -1458,8 +1612,6 @@ EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,
     return result;
     }
 
-
-
 /**
  * \brief   Associate Channel to Event Queue
  *
@@ -1485,6 +1637,7 @@ EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ(EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Instance *drvInst = NULL;
     EDMA3_DRV_Object *drvObject = NULL;
     unsigned int intState;
+    unsigned int edma3Id;
     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
 
@@ -1509,62 +1662,67 @@ EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ(EDMA3_DRV_Handle hEdma,
         drvInst = (EDMA3_DRV_Instance *)hEdma;
         drvObject = drvInst->pDrvObjectHandle;
 
-        if (drvObject == NULL)
+        if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
             {
-            result = EDMA3_DRV_E_INVALID_PARAM;
+            result =  EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-    if (result == EDMA3_DRV_SOK)
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (channelId > edma3_log_ch_max_val [edma3Id])
         {
-        if (drvObject->gblCfgParams.globalRegs == NULL)
-            {
-            result = EDMA3_DRV_E_INVALID_PARAM;
-            }
+        result = EDMA3_DRV_E_INVALID_PARAM;
         }
 
-    if (result == EDMA3_DRV_SOK)
+    /* Check the event queue */
+    if (eventQ >= drvObject->gblCfgParams.numEvtQueue)
         {
-        globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
-
-               /* If parameter checking is enabled... */
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-        /* Check the event queue */
-        if (eventQ >= drvObject->gblCfgParams.numEvtQueue)
-            {
-            result = EDMA3_DRV_E_INVALID_PARAM;
-            }
-#endif
+        result = EDMA3_DRV_E_INVALID_PARAM;
         }
+#endif
 
     if (result == EDMA3_DRV_SOK)
         {
-        if (channelId <= EDMA3_DRV_DMA_CH_MAX_VAL)
+        if (channelId <= edma3_dma_ch_max_val [edma3Id])
             {
             /* DMA channel */
-            edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);
+            edma3OsProtectEntry (edma3Id,
+                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                               &intState);
 
             globalRegs->DMAQNUM[channelId >> 3u] &=
                                         EDMA3_DRV_DMAQNUM_CLR_MASK(channelId);
             globalRegs->DMAQNUM[channelId >> 3u] |=
                                 EDMA3_DRV_DMAQNUM_SET_MASK(channelId, eventQ);
 
-            edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState);
+            edma3OsProtectExit(edma3Id,
+                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                               intState);
             }
         else
             {
-            if ((channelId >= EDMA3_DRV_QDMA_CH_MIN_VAL)
-                     && (channelId <= EDMA3_DRV_QDMA_CH_MAX_VAL))
+            if ((channelId >= edma3_qdma_ch_min_val[edma3Id])
+                     && (channelId <= edma3_qdma_ch_max_val[edma3Id]))
                 {
                 /* QDMA channel */
-                edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);
+                edma3OsProtectEntry (edma3Id,
+                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                       &intState);
 
                 globalRegs->QDMAQNUM &=
-                            EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-EDMA3_DRV_QDMA_CH_MIN_VAL);
+                       EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-edma3_qdma_ch_min_val[edma3Id]);
                 globalRegs->QDMAQNUM |=
-                            EDMA3_DRV_QDMAQNUM_SET_MASK(channelId-EDMA3_DRV_QDMA_CH_MIN_VAL, eventQ);
+                                       EDMA3_DRV_QDMAQNUM_SET_MASK(channelId-edma3_qdma_ch_min_val[edma3Id], eventQ);
 
-                edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState);
+                edma3OsProtectExit(edma3Id,
+                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       intState);
                 }
             else
                 {
@@ -1585,7 +1743,6 @@ EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ(EDMA3_DRV_Handle hEdma,
     return result;
     }
 
-
 /**
  * \brief   Get the Event Queue mapped to the specified DMA/QDMA channel.
  *
@@ -1607,6 +1764,7 @@ EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Instance *drvInst = NULL;
     EDMA3_DRV_Object *drvObject = NULL;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+    unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1618,8 +1776,7 @@ EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if (((hEdma == NULL) || (mappedEvtQ == NULL))
-        || (channelId > EDMA3_DRV_LOG_CH_MAX_VAL))
+    if ((hEdma == NULL) || (mappedEvtQ == NULL))
         {
         result =  EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -1635,30 +1792,32 @@ EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
+               }
+
+       if (EDMA3_DRV_SOK == result)
+               {
+        globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               edma3Id = drvObject->phyCtrllerInstId;
+
+        if (channelId <= edma3_dma_ch_max_val [edma3Id])
+            {
+            *mappedEvtQ = ((globalRegs->DMAQNUM[channelId >> 3u])
+                            & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(channelId))))
+                              >> ((channelId%8u)*4u);
+            }
         else
             {
-            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
-
-            if (channelId <= EDMA3_DRV_DMA_CH_MAX_VAL)
+            if ((channelId >= edma3_qdma_ch_min_val[edma3Id])
+                 &&(channelId <= edma3_qdma_ch_max_val[edma3Id]))
                 {
-                *mappedEvtQ = ((globalRegs->DMAQNUM[channelId >> 3u])
-                                & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(channelId))))
-                                  >> ((channelId%8u)*4u);
+                *mappedEvtQ = ((globalRegs->QDMAQNUM)
+                                & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId - edma3_qdma_ch_min_val[edma3Id]))))
+                               >> (channelId*4u);
                 }
             else
                 {
-                if ((channelId >= EDMA3_DRV_QDMA_CH_MIN_VAL)
-                     &&(channelId <= EDMA3_DRV_QDMA_CH_MAX_VAL))
-                    {
-                    *mappedEvtQ = ((globalRegs->QDMAQNUM)
-                                    & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId -EDMA3_DRV_QDMA_CH_MIN_VAL))))
-                                   >> (channelId*4u);
-                    }
-                else
-                    {
-                    /* Only valid for DMA/QDMA channel, return error... */
-                    result = EDMA3_DRV_E_INVALID_PARAM;
-                    }
+                /* Only valid for DMA/QDMA channel, return error... */
+                result = EDMA3_DRV_E_INVALID_PARAM;
                 }
             }
         }
@@ -1703,7 +1862,6 @@ EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     volatile unsigned int regPhyAddr = 0x0u;
 
-
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
@@ -1756,7 +1914,6 @@ EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
             }
         }
 
-
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
@@ -1765,13 +1922,9 @@ EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
                 EDMA3_DVT_dNONE));
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
 
-
     return result;
     }
 
-
-
-
 /**
  * \brief   Get the Channel Controller (CC) Register value
  *
@@ -1792,7 +1945,6 @@ EDMA3_DRV_Result EDMA3_DRV_getCCRegister ( EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     volatile unsigned int regPhyAddr = 0x0u;
 
-
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
@@ -1801,7 +1953,6 @@ EDMA3_DRV_Result EDMA3_DRV_getCCRegister ( EDMA3_DRV_Handle hEdma,
                 EDMA3_DVT_dNONE));
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
 
-
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
     if (((hEdma == NULL) || (regValue == NULL))
@@ -1832,7 +1983,6 @@ EDMA3_DRV_Result EDMA3_DRV_getCCRegister ( EDMA3_DRV_Handle hEdma,
             }
         }
 
-
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
@@ -1841,12 +1991,9 @@ EDMA3_DRV_Result EDMA3_DRV_getCCRegister ( EDMA3_DRV_Handle hEdma,
                 EDMA3_DVT_dNONE));
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
 
-
     return result;
     }
 
-
-
 /**
  * \brief   Wait for a transfer completion interrupt to occur and clear it.
  *
@@ -1875,7 +2022,6 @@ EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
     volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
     unsigned int tccBitMask = 0x0u;
 
-
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
@@ -1884,7 +2030,6 @@ EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
                 EDMA3_DVT_dNONE));
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
 
-
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
     if (hEdma == NULL)
@@ -1920,7 +2065,6 @@ EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
                 shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)
                                         (&globalRegs->SHADOW[drvInst->regionId]);
 
-
                 if (shadowRegs != NULL)
                     {
                     if(tccNo < 32u)
@@ -1960,7 +2104,6 @@ EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
             }
         }
 
-
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
@@ -1969,11 +2112,9 @@ EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
                 EDMA3_DVT_dNONE));
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
 
-
     return result;
     }
 
-
 /**
  * \brief   Returns the status of a previously initiated transfer.
  *
@@ -2006,7 +2147,6 @@ EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
     volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
     unsigned int tccBitMask = 0x0u;
 
-
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
@@ -2089,7 +2229,6 @@ EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
             }
         }
 
-
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
                 EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
@@ -2098,12 +2237,9 @@ EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
                 EDMA3_DVT_dNONE));
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
 
-
     return result;
     }
 
-
-
 /**
  * \brief   Get the PaRAM Set Physical Address associated with a logical channel
  *
@@ -2136,7 +2272,7 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
-
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -2149,8 +2285,7 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
-        || (paramPhyAddr == NULL))
+    if ((hEdma == NULL) || (paramPhyAddr == NULL))
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -2164,23 +2299,35 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
 
         if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
             {
-            result = EDMA3_DRV_E_INVALID_PARAM;
+            result =  EDMA3_DRV_E_INVALID_PARAM;
             }
         else
             {
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+               }
+               }
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
-            else
-                {
-                *paramPhyAddr = (unsigned int)&(globalRegs->PARAMENTRY [paRAMId].OPT);
-                }
-            }
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
         }
+#endif
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+               else
+            {
+            *paramPhyAddr = (unsigned int)&(globalRegs->PARAMENTRY [paRAMId].OPT);
+            }
+               }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -2191,11 +2338,8 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
 
     return result;
-
     }
 
-
-
 /**
  *  \brief EDMA3 Driver IOCTL
  *
@@ -2229,7 +2373,6 @@ EDMA3_DRV_Result EDMA3_DRV_Ioctl(
                 EDMA3_DVT_dNONE));
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
 
-
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
     if (hEdma == NULL)
@@ -2260,7 +2403,10 @@ EDMA3_DRV_Result EDMA3_DRV_Ioctl(
             {
             case EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION:
                 {
-                result = EDMA3_RM_Ioctl (drvInst->resMgrInstance, EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION, cmdArg, param);
+                result = EDMA3_RM_Ioctl (drvInst->resMgrInstance,
+                                                                               EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION,
+                                                                               cmdArg,
+                                                                               param);
 
                 break;
                 }
@@ -2273,7 +2419,10 @@ EDMA3_DRV_Result EDMA3_DRV_Ioctl(
                     }
                 else
                     {
-                    result = EDMA3_RM_Ioctl (drvInst->resMgrInstance, EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION, cmdArg, param);
+                    result = EDMA3_RM_Ioctl (drvInst->resMgrInstance,
+                                                                                       EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION,
+                                                                                       cmdArg,
+                                                                                       param);
                     }
 
                 break;
@@ -2285,7 +2434,6 @@ EDMA3_DRV_Result EDMA3_DRV_Ioctl(
             }
         }
 
-
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
         EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
                     EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
@@ -2295,11 +2443,8 @@ EDMA3_DRV_Result EDMA3_DRV_Ioctl(
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
 
         return result;
-
     }
 
-
-
 /**
  * \brief      Return the previously opened EDMA3 Driver Instance handle
  *
@@ -2392,5 +2537,579 @@ EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId,
        return (EDMA3_DRV_Handle)drvInstanceHandle;
        }
 
-/* End of File */
 
+/**
+ * \brief   Registers a transfer completion handler for a specific DMA/QDMA
+ *                     channel
+ *
+ * This function registers a non-NULL callback function for a specific DMA or QDMA
+ * channel and enables the completion interrupt for the TCC associated with
+ * the underlying channel in the IER/IERH register. If user enables the transfer
+ * completion interrupts (intermediate or final) in the associated PaRAM Set,
+ * the registered callback function will be called by the EDMA3 driver.
+ *
+ * If a call-back function is already registered for the channel, the API fails
+ * with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.
+ *
+ * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param  channelId           [IN]    DMA/QDMA channel for which the callback
+ *                                                                             function needs to be registered.
+ * \param   tccCb               [IN]    The callback function to be registered.
+ * \param   cbData              [IN]    Callback data to be passed while calling
+ *                                      the callback function.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique channelId values. It is non-
+ *          re-entrant for same channelId value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_registerTccCb(EDMA3_DRV_Handle hEdma,
+                    const unsigned int channelId,
+                    EDMA3_RM_TccCallback tccCb,
+                    void *cbData)
+       {
+    EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    EDMA3_DRV_Instance *drvInst = NULL;
+    EDMA3_DRV_Object *drvObject = NULL;
+       unsigned int edma3Id;
+    EDMA3_RM_ResDesc channelObj;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+    EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+                EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+                EDMA3_DVT_dCOUNTER,
+                EDMA3_DVT_dNONE,
+                EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if ((hEdma == NULL) || (tccCb == NULL))
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        drvInst = (EDMA3_DRV_Instance *)hEdma;
+        drvObject = drvInst->pDrvObjectHandle;
+
+        if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+               }
+               }
+
+       if (result == EDMA3_DRV_SOK)
+               {
+           if (channelId <= edma3_dma_ch_max_val [edma3Id])
+               {
+               channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+                       channelObj.resId = channelId;
+               }
+               else
+                       {
+                       if ((channelId >= edma3_qdma_ch_min_val[edma3Id])
+                               || (channelId <= edma3_qdma_ch_max_val[edma3Id]))
+                               {
+                       channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+                               channelObj.resId = channelId - edma3_qdma_ch_min_val[edma3Id];
+                               }
+                       else
+                               {
+                               result = EDMA3_DRV_E_INVALID_PARAM;
+                               }
+                       }
+               }
+
+       if (result == EDMA3_DRV_SOK)
+               {
+               /* Call the RM function now */
+               result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
+                                                   (EDMA3_RM_ResDesc *)&channelObj,
+                                                   edma3DrvChBoundRes[edma3Id][channelId].tcc,
+                                                   tccCb,
+                                                   cbData);
+               }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+        EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+                    EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+                    EDMA3_DVT_dCOUNTER,
+                    EDMA3_DVT_dNONE,
+                    EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+    return result;
+       }
+
+
+/**
+ * \brief   Un-register the previously registered callback function against a
+ *          DMA/QDMA channel.
+ *
+ * This function un-registers the previously registered callback function for
+ * the DMA/QDMA channel by removing any stored callback function. Moreover, it
+ * clears the interrupt enable register (IER/IERH) by writing to the IECR/
+ * IECRH register, for the TCC associated with that particular channel.
+ *
+ * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param  channelId           [IN]    DMA/QDMA channel for which the callback
+ *                                                                             function needs to be un-registered.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code.
+ *
+ * \note    This function is re-entrant for unique channelId. It is
+ *                     non-re-entrant for same channelId.
+ */
+EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb(EDMA3_DRV_Handle hEdma,
+                    const unsigned int channelId)
+
+       {
+    EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    EDMA3_DRV_Instance *drvInst = NULL;
+    EDMA3_DRV_Object *drvObject = NULL;
+       unsigned int edma3Id;
+    EDMA3_RM_ResDesc channelObj;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+    EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+                EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+                EDMA3_DVT_dCOUNTER,
+                EDMA3_DVT_dNONE,
+                EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (hEdma == NULL)
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        drvInst = (EDMA3_DRV_Instance *)hEdma;
+        drvObject = drvInst->pDrvObjectHandle;
+
+        if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+               }
+               }
+
+       if (result == EDMA3_DRV_SOK)
+               {
+           if (channelId <= edma3_dma_ch_max_val [edma3Id])
+               {
+               channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+                       channelObj.resId = channelId;
+               }
+               else
+                       {
+                       if ((channelId >= edma3_qdma_ch_min_val[edma3Id])
+                               || (channelId <= edma3_qdma_ch_max_val[edma3Id]))
+                               {
+                       channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+                               channelObj.resId = channelId - edma3_qdma_ch_min_val[edma3Id];
+                               }
+                       else
+                               {
+                               result = EDMA3_DRV_E_INVALID_PARAM;
+                               }
+                       }
+               }
+
+       if (result == EDMA3_DRV_SOK)
+               {
+               /* Call the RM function now */
+               result = EDMA3_RM_unregisterTccCb (drvInst->resMgrInstance,
+                                                   (EDMA3_RM_ResDesc *)&channelObj);
+               }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+        EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+                    EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+                    EDMA3_DVT_dCOUNTER,
+                    EDMA3_DVT_dNONE,
+                    EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+    return result;
+       }
+
+
+EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(unsigned int phyCtrllerInstId,
+                                       unsigned int tcId,
+                                       EDMA3_DRV_Tc_Err tcErr)
+       {
+    EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    EDMA3_DRV_Object *drvObject = NULL;
+    volatile EDMA3_TCRL_Regs *tcRegs = NULL;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+    EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+                EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+                EDMA3_DVT_dCOUNTER,
+                EDMA3_DVT_dNONE,
+                EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+       if (phyCtrllerInstId >= EDMA3_MAX_EDMA3_INSTANCES)
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+
+    if ((tcErr < EDMA3_DRV_TC_ERR_BUSERR_DIS)
+        || (tcErr > EDMA3_DRV_TC_ERR_EN))
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+       /* Check if the parameters are OK. */
+       if (EDMA3_DRV_SOK == result)
+        {
+        drvObject = &drvObj[phyCtrllerInstId];
+
+        if (drvObject == NULL)
+            {
+            result =  EDMA3_DRV_E_INVALID_PARAM;
+            }
+               else
+                       {
+               if (tcId >= drvObject->gblCfgParams.numTcs)
+                       {
+                       result = EDMA3_DRV_E_INVALID_PARAM;
+                       }
+                       }
+               }
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        tcRegs = (volatile EDMA3_TCRL_Regs *)(drvObject->gblCfgParams.tcRegs[tcId]);
+
+           if (NULL == tcRegs)
+               {
+               result = EDMA3_DRV_E_INVALID_PARAM;
+               }
+               }
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        switch (tcErr)
+               {
+               case EDMA3_DRV_TC_ERR_BUSERR_DIS:
+                               tcRegs->ERREN &= ~(1 << EDMA3_TCRL_ERREN_BUSERR_SHIFT);
+                               break;
+
+               case EDMA3_DRV_TC_ERR_BUSERR_EN:
+                               tcRegs->ERREN |= (1 << EDMA3_TCRL_ERREN_BUSERR_SHIFT);
+                               break;
+
+               case EDMA3_DRV_TC_ERR_TRERR_DIS:
+                               tcRegs->ERREN &= ~(1 << EDMA3_TCRL_ERREN_TRERR_SHIFT);
+                               break;
+
+               case EDMA3_DRV_TC_ERR_TRERR_EN:
+                               tcRegs->ERREN |= (1 << EDMA3_TCRL_ERREN_TRERR_SHIFT);
+                               break;
+
+               case EDMA3_DRV_TC_ERR_MMRAERR_DIS:
+                               tcRegs->ERREN &= ~(1 << EDMA3_TCRL_ERREN_MMRAERR_SHIFT);
+                               break;
+
+               case EDMA3_DRV_TC_ERR_MMRAERR_EN:
+                               tcRegs->ERREN |= (1 << EDMA3_TCRL_ERREN_MMRAERR_SHIFT);
+                               break;
+
+               case EDMA3_DRV_TC_ERR_DIS:
+                               tcRegs->ERREN = EDMA3_TCRL_ERREN_RESETVAL;
+                               break;
+
+               case EDMA3_DRV_TC_ERR_EN:
+                               tcRegs->ERREN = (EDMA3_TCRL_ERREN_BUSERR_MASK
+                                                               | EDMA3_TCRL_ERREN_TRERR_MASK
+                                                               | EDMA3_TCRL_ERREN_MMRAERR_MASK);
+                               break;
+
+                       default:
+                               result = EDMA3_DRV_E_INVALID_PARAM;
+                               break;
+               }
+               }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+    EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+                EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+                EDMA3_DVT_dCOUNTER,
+                EDMA3_DVT_dNONE,
+                EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+    return result;
+       }
+
+
+/**
+ * \brief   Un-register the previously registered callback function against a
+ *          DMA/QDMA channel.
+ *
+ * This function unregisters the previously registered callback function against
+ * a DMA/QDMA channel by removing any stored callback function. Moreover, it
+ * clears the interrupt enable register (IER/IERH) by writing to the IECR/
+ * IECRH register, for the TCC associated with that particular channel.
+ *
+ * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param  channelId           [IN]    DMA/QDMA channel for which the callback
+ *                                                                             function needs to be un-registered.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code.
+ *
+ * \note    This function is re-entrant for unique channelId. It is
+ *                     non-re-entrant for same channelId.
+ */
+EDMA3_DRV_Result EDMA3_DRV_getChannelStatus(EDMA3_DRV_Handle hEdma,
+                        unsigned int lCh, unsigned int *lchStatus)
+       {
+       EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    EDMA3_DRV_Instance *drvInst = NULL;
+    EDMA3_DRV_Object *drvObject = NULL;
+    volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+    volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
+       unsigned int edma3Id;
+       unsigned int status = 0x0;
+       unsigned int tcc;
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+    EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+                EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_START,
+                EDMA3_DVT_dCOUNTER,
+                EDMA3_DVT_dNONE,
+                EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if ((hEdma == NULL)
+               || (lchStatus == NULL))
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+       /* Check if the parameters are OK. */
+       if (EDMA3_DRV_SOK == result)
+        {
+        drvInst = (EDMA3_DRV_Instance *)hEdma;
+        drvObject = drvInst->pDrvObjectHandle;
+
+        if ((drvObject == NULL) ||
+                       (drvObject->gblCfgParams.globalRegs == NULL))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+        else
+            {
+            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+            shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)
+                                    (&globalRegs->SHADOW[drvInst->regionId]);
+            edma3Id = drvObject->phyCtrllerInstId;
+               }
+               }
+
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+
+       /* Not valid for Link channels */
+    if ( lCh >= edma3_link_ch_min_val [edma3Id]
+               && lCh <= edma3_link_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        tcc = edma3DrvChBoundRes[edma3Id][lCh].tcc;
+
+        if (tcc >= drvObject->gblCfgParams.numTccs)
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+               }
+
+       if (EDMA3_DRV_SOK == result)
+       {
+       /* DMA Channel, check for event pending and event miss */
+               if (lCh <= edma3_dma_ch_max_val[edma3Id])
+                       {
+                       if (lCh < 32u)
+                               {
+                       if((globalRegs->EMR & (1u << lCh)) != FALSE)
+                           {
+                           status |= EDMA3_DRV_CHANNEL_ERR;
+                           }
+
+                       if((shadowRegs->ER & (1u << lCh)) != FALSE)
+                           {
+                           status |= EDMA3_DRV_CHANNEL_EVENT_PENDING;
+                           }
+                               }
+                       else
+                               {
+                if((globalRegs->EMRH & (1u << (lCh-32u))) != FALSE)
+                    {
+                    status |= EDMA3_DRV_CHANNEL_ERR;
+                    }
+
+                       if((shadowRegs->ERH & (1u << (lCh-32u))) != FALSE)
+                           {
+                           status |= EDMA3_DRV_CHANNEL_EVENT_PENDING;
+                           }
+                               }
+                       }
+
+       /* QDMA Channel, check for event miss */
+               if (lCh >= edma3_qdma_ch_min_val[edma3Id]
+                       && lCh <= edma3_qdma_ch_max_val[edma3Id])
+                       {
+                       unsigned int qdma_ch = lCh - edma3_qdma_ch_min_val[edma3Id];
+
+               if((globalRegs->QEMR & (1u << qdma_ch)) != FALSE)
+                   {
+                   status |= EDMA3_DRV_CHANNEL_ERR;
+                   }
+                       }
+
+               /* Check for xfer completion interrupt */
+               if (tcc < 32u)
+                       {
+               if((shadowRegs->IPR & (1u << tcc)) != FALSE)
+                   {
+                   status |= EDMA3_DRV_CHANNEL_XFER_COMPLETE;
+                   }
+                       }
+               else
+                       {
+               if((shadowRegs->IPRH & (1u << (tcc-32u))) != FALSE)
+                   {
+                   status |= EDMA3_DRV_CHANNEL_XFER_COMPLETE;
+                   }
+                       }
+
+               /* Update the status */
+               *lchStatus = status;
+               }
+
+#ifdef EDMA3_INSTRUMENTATION_ENABLED
+    EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
+                EDMA3_DVT_DESC(EDMA3_DVT_eFUNC_END,
+                EDMA3_DVT_dCOUNTER,
+                EDMA3_DVT_dNONE,
+                EDMA3_DVT_dNONE));
+#endif /* EDMA3_INSTRUMENTATION_ENABLED */
+
+    return result;
+    }
+
+
+/**
+ * \brief  Associates a link channel and a TCC
+ *
+ * This API is used to map a TCC to a LINK channel. It should be used with LINK
+ * channels ONLY else it will fail.
+ *
+ * \param   hEdma           [IN]    Handle to the EDMA Driver Instance.
+ * \param   linkCh          [IN]    Link Channel to which a particular TCC
+ *                                  needs to be mapped.
+ * \param   tcc             [IN]    TCC which needs to be mapped
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique linkCh values. It is
+ *          non-re-entrant for same linkCh values.
+ */
+EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh ( EDMA3_DRV_Handle hEdma,
+                                                unsigned int linkCh,
+                                                unsigned int tcc)
+       {
+    EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    EDMA3_DRV_Instance *drvInst = NULL;
+    EDMA3_DRV_Object *drvObject = NULL;
+    int paRAMId;
+    volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
+
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (hEdma == NULL)
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        drvInst = (EDMA3_DRV_Instance *)hEdma;
+        drvObject = drvInst->pDrvObjectHandle;
+
+        if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+               }
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        edma3Id = drvObject->phyCtrllerInstId;
+        globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+
+        /* Validate the arguments */
+               if ((linkCh < edma3_link_ch_min_val[edma3Id] ||
+                               linkCh > edma3_link_ch_max_val[edma3Id]) ||
+                               (tcc >= drvObject->gblCfgParams.numTccs))
+                       {
+                       result = EDMA3_DRV_E_INVALID_PARAM;
+                       }
+               }
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][linkCh].paRAMId;
+
+        if (paRAMId < 0 || paRAMId >= drvObject->gblCfgParams.numPaRAMSets)
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+               else
+                       {
+            /* Set TCC in ParamSet.OPT field */
+            globalRegs->PARAMENTRY [paRAMId].OPT &= EDMA3_DRV_OPT_TCC_CLR_MASK;
+            globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(tcc);
+
+                       /* Update the tcc */
+                       edma3DrvChBoundRes[edma3Id][linkCh].tcc = tcc;
+                       }
+               }
+
+       return result;
+       }
+
+/* End of File */
index 9acb440eb81f0675a895bc4926fa2a38247e6e9b..3f891c27fae5d829059766f78a7149d2d67056a4 100644 (file)
@@ -1,52 +1,50 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**|                            ****                                          |**
-**|                            ****                                          |**
-**|                            ******o***                                    |**
-**|                      ********_///_****                                   |**
-**|                      ***** /_//_/ ****                                   |**
-**|                       ** ** (__/ ****                                    |**
-**|                           *********                                      |**
-**|                            ****                                          |**
-**|                            ***                                           |**
-**|                                                                          |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
-**|                        ALL RIGHTS RESERVED                               |**
-**|                                                                          |**
-**| Permission is hereby granted to licensees of Texas Instruments           |**
-**| Incorporated (TI) products to use this computer program for the sole     |**
-**| purpose of implementing a licensee product based on TI products.         |**
-**| No other rights to reproduce, use, or disseminate this computer          |**
-**| program, whether in part or in whole, are granted.                       |**
-**|                                                                          |**
-**| TI makes no representation or warranties with respect to the             |**
-**| performance of this computer program, and specifically disclaims         |**
-**| any responsibility for any damages, special or consequential,            |**
-**| connected with the use of this program.                                  |**
-**|                                                                          |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/**
-*      \file           edma3_drv_basic.c
-*
-*   \brief      EDMA3 Driver Basic Interface Implementation
-*   This file contains beginner-level EDMA3 Driver APIs which are required
-*      to:
-*      a) Request/free a DMA, QDMA and Link channel.
-*              b) Program various fields in the PaRAM Set like source/destination
-*                      parameters, transfer parameters etc.
-*      c) Enable/disable a transfer.
-*      These APIs are provided to program a DMA/QDMA channel for simple use-cases
-*      and don't expose all the features of EDMA3 hardware. Users who want to go
-*      beyond this and have complete control on the EDMA3 hardware are advised
-*      to refer edma3_drv_adv.c source file.
-*
-*      @author: PSP Team, TII
-*
+/*
+ * edma3_drv_basic.c
+ *
+ * EDMA3 Driver Basic Interface Implementation. This file contains
+ * beginner-level EDMA3 Driver APIs which are required to:
+ * a) Request/free a DMA, QDMA and Link channel.
+ * b) Program various fields in the PaRAM Set like source/destination
+ * parameters, transfer parameters etc.
+ * c) Enable/disable a transfer.
+ * These APIs are provided to program a DMA/QDMA channel for simple use-cases
+ * and don't expose all the features of EDMA3 hardware. Users who want to go
+ * beyond this and have complete control on the EDMA3 hardware are advised
+ * to refer edma3_drv_adv.c source file.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
 */
 
-
 /* EDMa3 Driver Internal Header Files */
 #include <ti/sdo/edma3/drv/src/edma3.h>
 /* Resource Manager Internal Header Files */
@@ -105,7 +103,7 @@ extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
 extern EDMA3_RM_Instance *ptrRMIArray;
 
 /** Local MemSet function */
-extern void edma3MemSet(void *dst, unsigned char data, unsigned int len);
+extern void edma3MemZero(void *dst, unsigned int len);
 /** Local MemCpy function */
 extern void edma3MemCpy(void *dst, const void *src, unsigned int len);
 
@@ -141,7 +139,18 @@ extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGI
  */
 extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
 
-
+/** Max of DMA Channels */
+extern unsigned int edma3_dma_ch_max_val[];
+/** Min of Link Channels */
+extern unsigned int edma3_link_ch_min_val[];
+/** Max of Link Channels */
+extern unsigned int edma3_link_ch_max_val[];
+/** Min of QDMA Channels */
+extern unsigned int edma3_qdma_ch_min_val[];
+/** Max of QDMA Channels */
+extern unsigned int edma3_qdma_ch_max_val[];
+/** Max of Logical Channels */
+extern unsigned int edma3_log_ch_max_val[];
 
 /* Local functions prototypes */
 /*---------------------------------------------------------------------------*/
@@ -281,15 +290,15 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
     EDMA3_RM_ResDesc resObj;
     EDMA3_RM_ResDesc channelObj;
     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
-    unsigned int linkBcntReld = 0;
     EDMA3_DRV_Instance *drvInst = NULL;
     EDMA3_DRV_Object *drvObject = NULL;
-    EDMA3_RM_ResType savedResType;
     unsigned int mappedTcc = EDMA3_DRV_CH_NO_TCC_MAP;
     int paRAMId = (int)EDMA3_RM_RES_ANY;
     EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
     int mappedPaRAMId;
+       unsigned int edma3Id;
+       unsigned int freeDmaQdmaChannel = FALSE;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -299,6 +308,7 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
                 EDMA3_DVT_dNONE));
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
 
+
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
     if ((pLCh == NULL) || (hEdma == NULL))
@@ -307,7 +317,6 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
         }
 #endif
 
-       /* Check if the parameters are OK. */
        if (EDMA3_DRV_SOK == result)
         {
         drvInst = (EDMA3_DRV_Instance *)hEdma;
@@ -317,363 +326,390 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        else
-            {
-            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
 
-                       /* If parameter checking is enabled... */
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-            if (((*pLCh) != EDMA3_DRV_LINK_CHANNEL) &&
-                ((evtQueue >= drvObject->gblCfgParams.numEvtQueue) || (pTcc == NULL)))
+       if (EDMA3_DRV_SOK == result)
+        {
+        edma3Id = drvObject->phyCtrllerInstId;
+        globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+
+        /* Identify the request type and validate the appropriate arguments.
+                * Starting in the order of PaRAM Set availability,
+                * check for a specific DMA channel request first.
+                */
+               if ((*pLCh) <= edma3_dma_ch_max_val [edma3Id])
+                       {
+                       /* A 'Specific' DMA channel is requested */
+                       chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
+                       /* Fill the resObj structure as well */
+                       resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+                       resObj.resId = *pLCh;
+
+                       /* Check the TCC and Event Queue number */
+            if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
+                               || (pTcc == NULL))
                 {
                 result = EDMA3_DRV_E_INVALID_PARAM;
                 }
-#endif
-
-                       /* Check if the parameters are OK. */
-                       if (EDMA3_DRV_SOK == result)
+                       }
+
+               if ((*pLCh) == EDMA3_DRV_DMA_CHANNEL_ANY)
+                       {
+                       /* 'Any' DMA channel is requested */
+                       chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
+                       resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+                       resObj.resId = EDMA3_RM_RES_ANY;
+
+                       /* Check the TCC and Event Queue number */
+            if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
+                               || (pTcc == NULL))
                 {
-                if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL)
-                    {
-                    /*
-                     * Do nothing.  Do not allocate channel.
-                     * Typically this option is for request
-                     * of a PaRAM Set for linking purpose.
-                     */
-                    result = EDMA3_DRV_SOK;
-                    }
-                else if ((*pLCh) == EDMA3_DRV_DMA_CHANNEL_ANY)
+                result = EDMA3_DRV_E_INVALID_PARAM;
+                }
+                       }
+
+               if (((*pLCh) >= edma3_link_ch_min_val[edma3Id]) &&
+                               ((*pLCh) <= edma3_link_ch_max_val[edma3Id]))
+                       {
+                       /* A 'Specific' Link channel is requested, TCC may or may not be
+                        * required.
+                        */
+                       /* Save the PaRAM Id for future use */
+                       paRAMId = *pLCh;
+
+                       if (pTcc != NULL)
+                               {
+                               if (*pTcc < drvObject->gblCfgParams.numTccs)
+                                       {
+                                       /* Argument passed as *pTcc is a valid TCC number */
+                                       chType = EDMA3_DRV_CHANNEL_TYPE_LINK_TCC;
+                               resObj.type = EDMA3_RM_RES_PARAM_SET;
+                                       }
+                               else
+                                       {
+                                       /* Argument passed as *pTcc is Invalid TCC number */
+                                       result = EDMA3_DRV_E_INVALID_PARAM;
+                                       }
+                               }
+                       else
+                               {
+                               /* pTcc is NULL, only Link Channel required */
+                               chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
+                               resObj.type = EDMA3_RM_RES_PARAM_SET;
+                               }
+                       }
+
+               if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL)
+                       {
+                       /* 'Any' Link channel is requested, TCC is not required */
+                       chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
+                       resObj.type = EDMA3_RM_RES_PARAM_SET;
+                       }
+
+               if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL_WITH_TCC)
+                       {
+                       /* 'Any' Link channel is requested, TCC is required */
+                       if (*pTcc < drvObject->gblCfgParams.numTccs)
+                               {
+                               /* Argument passed as *pTcc is a valid TCC number */
+                               chType = EDMA3_DRV_CHANNEL_TYPE_LINK_TCC;
+                               resObj.type = EDMA3_RM_RES_PARAM_SET;
+                               }
+                       else
+                               {
+                               /* Argument passed as *pTcc is Invalid TCC number */
+                               result = EDMA3_DRV_E_INVALID_PARAM;
+                               }
+                       }
+
+               if (((*pLCh) >= EDMA3_DRV_QDMA_CHANNEL_0) &&
+                               ((*pLCh) <= EDMA3_DRV_QDMA_CHANNEL_7))
+                       {
+                       /* A 'Specific' QDMA channel is requested */
+                       chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
+                       resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+                       resObj.resId = *pLCh - EDMA3_DRV_QDMA_CHANNEL_0;
+
+                       /* Check the TCC and Event Queue number */
+            if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
+                               || (pTcc == NULL))
+                {
+                result = EDMA3_DRV_E_INVALID_PARAM;
+                }
+                       }
+
+               if ((*pLCh) == EDMA3_DRV_QDMA_CHANNEL_ANY)
+                       {
+                       /* 'Any' QDMA channel is requested */
+                       chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
+                       resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+                       resObj.resId = EDMA3_RM_RES_ANY;
+
+                       /* Check the TCC and Event Queue number */
+            if ((evtQueue >= drvObject->gblCfgParams.numEvtQueue)
+                               || (pTcc == NULL))
+                {
+                result = EDMA3_DRV_E_INVALID_PARAM;
+                }
+                       }
+
+               if (EDMA3_DRV_CHANNEL_TYPE_NONE == chType)
+                       {
+                       /* Invalid request */
+                       result = EDMA3_DRV_E_INVALID_PARAM;
+                       }
+               }
+
+       /* Step 1: Allocate the DMA/QDMA channel first, if required */
+       if (EDMA3_DRV_SOK == result)
+        {
+        switch (chType)
+               {
+               case EDMA3_DRV_CHANNEL_TYPE_DMA:
+                               result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
+                                                                                               (EDMA3_RM_ResDesc *)&resObj);
+                if (result == EDMA3_RM_SOK)
                     {
-                    /* First request for any available DMA channel */
-                    resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
-                    resObj.resId = EDMA3_RM_RES_ANY;
-                    result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
+                    *pLCh = resObj.resId;
 
-                    if (result == EDMA3_RM_SOK)
+                    mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];
+                    if (mappedPaRAMId != EDMA3_DRV_CH_NO_PARAM_MAP)
                         {
-                        *pLCh = resObj.resId;
-                        mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];
-                        mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh];
-                        if (mappedPaRAMId != EDMA3_DRV_CH_NO_PARAM_MAP)
+                        paRAMId = mappedPaRAMId;
+                        }
+
+                    if (*pTcc == EDMA3_DRV_TCC_ANY)
+                        {
+                           mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh];
+                        if (mappedTcc == EDMA3_DRV_CH_NO_TCC_MAP)
                             {
-                            /*
-                             * There is a PaRAM Set statically mapped to the returned
-                             * channel number.
-                             * This imposes a constraint on the PaRAM Set which we
-                             * next request for.
-                             * We update the PaRAM Set number with the one statically
-                             * reserved for the afore-returned channel number.
-                             */
-                            paRAMId = mappedPaRAMId;
+                            mappedTcc = EDMA3_RM_RES_ANY;
                             }
-                        chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
-
-                        /* Save the Resource Type for TCC registeration */
-                        channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
                         }
                     else
                         {
-                        result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL;
+                        mappedTcc = *pTcc;
                         }
-                    }
-                else if ((*pLCh) == EDMA3_DRV_QDMA_CHANNEL_ANY)
-                    {
-                    /* First request for any available QDMA channel */
-                    resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
-                    resObj.resId = EDMA3_RM_RES_ANY;
-                    result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
-                                                (EDMA3_RM_ResDesc *)&resObj);
-                    if (result == EDMA3_DRV_SOK)
-                        {
-                        (*pLCh) = resObj.resId + EDMA3_DRV_QDMA_CH_MIN_VAL;
-                        chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
 
-                        /* Save the Resource Type for TCC registeration */
-                        channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
-                        }
-                    else
-                        {
-                        result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;
-                        }
+                    /* Save the Resource Type/ID for TCC registeration */
+                    channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+                                       channelObj.resId = *pLCh;
+
+                                       /* Free DMA channel in case the function fails in future */
+                                       freeDmaQdmaChannel = TRUE;
                     }
-                else if ((*pLCh) <= EDMA3_DRV_DMA_CH_MAX_VAL)
+                else
                     {
-                    /* Request for a specific DMA channel */
-                    resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
-                    resObj.resId = *pLCh;
-                    result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
-                    if (result != EDMA3_RM_SOK)
-                        {
-                        result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL;
-                        }
-                    else
-                        {
-                        mappedPaRAMId = drvObject->gblCfgParams.dmaChannelPaRAMMap[*pLCh];
-                        mappedTcc = drvObject->gblCfgParams.dmaChannelTccMap[*pLCh];
-                        if (mappedPaRAMId != EDMA3_DRV_CH_NO_PARAM_MAP)
-                            {
-                            /*
-                             * There is a PaRAM Set statically mapped to the returned
-                             * channel number.
-                             * This imposes a constraint on the PaRAM Set which we
-                             * next request for.
-                             * We update the PaRAM Set number with the one statically
-                             * reserved for the afore-returned channel number.
-                             */
-                            paRAMId = mappedPaRAMId;
-                            }
-                        chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
-
-                        /* Save the Resource Type for TCC registeration */
-                        channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
-                        }
+                    result = EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL;
                     }
-                else if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL) && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))
+
+                               break;
+
+               case EDMA3_DRV_CHANNEL_TYPE_QDMA:
+                               result = EDMA3_RM_allocResource(drvInst->resMgrInstance,
+                                                                                               (EDMA3_RM_ResDesc *)&resObj);
+                if (result == EDMA3_DRV_SOK)
                     {
-                    /* Request for a specific QDMA channel */
-                    resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
-                    resObj.resId = (((*pLCh)) - EDMA3_DRV_QDMA_CH_MIN_VAL);
-                    result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
-                    if (result != EDMA3_RM_SOK)
+                    (*pLCh) = resObj.resId + edma3_qdma_ch_min_val[edma3Id];
+
+                    if (*pTcc == EDMA3_DRV_TCC_ANY)
                         {
-                        result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;
+                        mappedTcc = EDMA3_RM_RES_ANY;
                         }
                     else
                         {
-                        chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
-
-                        /* Save the Resource Type for TCC registeration */
-                        channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+                        mappedTcc = *pTcc;
                         }
+
+                    /* Save the Resource Type/ID for TCC registeration */
+                    channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+                                       channelObj.resId = resObj.resId;
+
+                                       /* Free DMA channel in case the function fails in future */
+                                       freeDmaQdmaChannel = TRUE;
                     }
                 else
                     {
-                    result = EDMA3_DRV_E_INVALID_PARAM;
+                    result = EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL;
                     }
+                               break;
 
-                if (result == EDMA3_DRV_SOK)
-                    {
-                    /* Request for a PaRAM Set */
-                    savedResType = resObj.type;
-                    resObj.type = EDMA3_RM_RES_PARAM_SET;
-                    resObj.resId = (unsigned int)paRAMId;
-                    result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
-
-                    paRAMId = (int)resObj.resId;
-                    if ((*pLCh) == EDMA3_DRV_LINK_CHANNEL)
+                       default:
+                               break;
+               }
+               }
+
+       /* Step 2: Allocate the PaRAM Set */
+       if (EDMA3_DRV_SOK == result)
+        {
+        resObj.type = EDMA3_RM_RES_PARAM_SET;
+        resObj.resId = (unsigned int)paRAMId;
+        result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
+               }
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = (int)resObj.resId;
+
+        if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
+               {
+               /* Link channel number should be same as the PaRAM Set */
+            *pLCh = resObj.resId;
+                       edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
+            edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
+               }
+
+        if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK_TCC)
+            {
+               /* Link channel number should be same as the PaRAM Set */
+            *pLCh = resObj.resId;
+                       edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
+            edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
+
+                       /* save the tcc now */
+                       edma3DrvChBoundRes[edma3Id][*pLCh].tcc = *pTcc;
+
+            /* Set TCC in ParamSet.OPT field */
+            globalRegs->PARAMENTRY [paRAMId].OPT  &= EDMA3_DRV_OPT_TCC_CLR_MASK;
+            globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
+            }
+               }
+       else
+               {
+               /* PaRAM allocation failed, free the previously allocated DMA/QDMA
+                * channel, if required
+                */
+               if ((chType == EDMA3_DRV_CHANNEL_TYPE_DMA
+                       || chType == EDMA3_DRV_CHANNEL_TYPE_QDMA) &&
+                       (TRUE == freeDmaQdmaChannel))
+                       {
+               EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
+                       }
+               }
+
+       /* Step 3: Allocate TCC only for DMA/QDMA channels */
+       if ((EDMA3_DRV_SOK == result) &&
+               (chType == EDMA3_DRV_CHANNEL_TYPE_DMA || chType == EDMA3_DRV_CHANNEL_TYPE_QDMA))
+        {
+        resObj.type = EDMA3_RM_RES_TCC;
+        resObj.resId = mappedTcc;
+        result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
+
+               if (EDMA3_DRV_SOK == result)
+               {
+               *pTcc = resObj.resId;
+
+                       /* Save TCC and PaRAM set */
+                       edma3DrvChBoundRes[edma3Id][*pLCh].tcc = *pTcc;
+                       edma3DrvChBoundRes[edma3Id][*pLCh].paRAMId = paRAMId;
+
+                       switch (chType)
+                               {
+                               case EDMA3_DRV_CHANNEL_TYPE_DMA:
+                                       {
+                                       /* Step 4: Register the callback function, if required */
+                                       if (NULL != tccCb)
+                                               {
+                           result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
+                                                                           (EDMA3_RM_ResDesc *)&channelObj,
+                                                                           *pTcc, tccCb, cbData);
+                                               }
+                    if (result != EDMA3_DRV_SOK)
                         {
-                        if (result == EDMA3_RM_SOK)
-                            {
-                            unsigned int linkCh = EDMA3_DRV_LINK_CH_MIN_VAL;
-
-                            /*
-                             * Search for the next Link channel handle available,
-                             * starting from EDMA3_DRV_LINK_CH_MIN_VAL.
-                             */
-                            while ((edma3DrvChBoundRes[drvObject->phyCtrllerInstId][linkCh].paRAMId != -1)
-                                    && (linkCh <= EDMA3_DRV_LINK_CH_MAX_VAL))
-                                {
-                                /* Move to the next handle. */
-                                linkCh++;
-                                }
-
-                            /* Verify the returned handle, it should lie in the correct range */
-                            if (linkCh > EDMA3_DRV_LINK_CH_MAX_VAL)
-                                {
-                                result = EDMA3_DRV_E_INVALID_PARAM;
-                                }
-                            else
-                                {
-                                *pLCh = linkCh;
-                                }
-                            }
+                        EDMA3_DRV_freeChannel (hEdma, *pLCh);
+                        result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
                         }
-                    else
-                        {
-                        if (result != EDMA3_DRV_SOK)
-                            {
-                            /*
-                             * Free the already allocated channel
-                             * (only if channel is a Non-Link Channel)
-                             */
-                            resObj.type = savedResType;
-                            resObj.resId = *pLCh;
-                            EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
-                            }
-                        else
-                            {
-                            /* Request for a TCC */
-                            resObj.type = EDMA3_RM_RES_TCC;
-                            if ((*pTcc) == EDMA3_DRV_TCC_ANY)
-                                {
-                                if (mappedTcc == EDMA3_DRV_CH_NO_TCC_MAP)
-                                    {
-                                    resObj.resId = EDMA3_RM_RES_ANY;
-                                    }
-                                else
-                                    {
-                                    resObj.resId = mappedTcc;
-                                    }
-                                }
-                            else
-                                {
-                                resObj.resId = *pTcc;
-                                }
-
-                            result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
-                            if (result == EDMA3_DRV_SOK)
-                                {
-                                *pTcc = resObj.resId;
-                                }
-                            else
-                                {
-                                resObj.type = savedResType;
-                                resObj.resId = *pLCh;
-                                EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
-
-                                resObj.type = EDMA3_RM_RES_PARAM_SET;
-                                resObj.resId = (unsigned int)paRAMId;
-                                EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
-                                result = EDMA3_DRV_E_TCC_UNAVAIL;
-                                }
-
-                            if (result == EDMA3_DRV_SOK)
-                                {
-                                /* If callback function is not null, register it with the RM. */
-                                if (NULL != tccCb)
-                                    {
-                                    /**
-                                     * Fill the resource id, whose associated TCC
-                                     * needs to be registered.
-                                     * For QDMA channels, pass the actual QDMA
-                                     * channel no instead of (*pLCh).
-                                     */
-                                    if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL)
-                                                 && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))
-                                        {
-                                        channelObj.resId = (*pLCh) - EDMA3_DRV_QDMA_CH_MIN_VAL;
-                                        }
-                                    else
-                                        {
-                                        channelObj.resId = (*pLCh);
-                                        }
-
-                                    result = EDMA3_RM_registerTccCb (
-                                            drvInst->resMgrInstance,
-                                            (EDMA3_RM_ResDesc *)&channelObj,
-                                            *pTcc, tccCb, cbData);
-
-                                    if (result != EDMA3_DRV_SOK)
-                                        {
-                                        EDMA3_DRV_freeChannel (hEdma, *pLCh);
-                                        result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
-                                        }
-                                    }
-
-                                if (result == EDMA3_DRV_SOK)
-                                    {
+                                       else
+                                               {
 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
-                                                               unsigned int intState=0;
-                                    edma3OsProtectEntry(EDMA3_OS_PROTECT_INTERRUPT, &intState);
-
-                                    /* Associate Channel to Event Queue */
-                                    if ((*pLCh) < drvObject->gblCfgParams.numDmaChannels)
-                                        {
-                                        globalRegs->DMAQNUM[(*pLCh) >> 3u] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh);
-                                        globalRegs->DMAQNUM[(*pLCh) >> 3u] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh),evtQueue);
-                                        }
-                                    else if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL)
-                                             && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))
-                                            {
-                                            globalRegs->QDMAQNUM &=
-                                                EDMA3_DRV_QDMAQNUM_CLR_MASK((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL);
-                                            globalRegs->QDMAQNUM |=
-                                                EDMA3_DRV_QDMAQNUM_SET_MASK((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL,evtQueue);
-                                            }
-
-                                    edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState);
-#endif                                                                 
-
-                                    /**
-                                     * Map the allocated PaRAM Set to the logical
-                                     * DMa/QDMA channel.
-                                     */
-                                    if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)
-                                        {
-                                        result = EDMA3_RM_mapQdmaChannel (drvInst->resMgrInstance,
-                                                                        ((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL),
-                                                                        paRAMId,
-                                                                        EDMA3_RM_QDMA_TRIG_DEFAULT);
-                                        }
-                                    else
-                                        {
-                                        /**
-                                         * First check whether the mapping feature is supported on the underlying
-                                         * platform. In case it is not supported, dont call this API, because this
-                                         * API returns error in case the feature is not there.
-                                         */
-                                        if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
-                                            {
-                                            result = EDMA3_RM_mapEdmaChannel (drvInst->resMgrInstance,
-                                                                                 *pLCh,
-                                                                                 paRAMId);
-                                            }
-                                        }
-
-                                    if (result != EDMA3_DRV_SOK)
-                                        {
-                                        EDMA3_DRV_freeChannel (hEdma, *pLCh);
-                                        result = EDMA3_DRV_E_CH_PARAM_BIND_FAIL;
-                                        }
-                                    else
-                                        {
-                                        /* Bind the resources PaRAM Set and TCC */
-                                        /* Set TCC of Param Set corresponding to specified paramId */
-                                        globalRegs->PARAMENTRY [paRAMId].OPT  &= EDMA3_DRV_OPT_TCC_CLR_MASK;
-                                        globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
-
-                                        edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].tcc = *pTcc;
-                                        }
-                                    }
-                                }
+                                               unsigned int intState = 0;
+                        edma3OsProtectEntry(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
+                                                                                       &intState);
+                        /* Step 5: Associate DMA Channel to Event Queue */
+                        globalRegs->DMAQNUM[(*pLCh) >> 3u] &= EDMA3_DRV_DMAQNUM_CLR_MASK(*pLCh);
+                        globalRegs->DMAQNUM[(*pLCh) >> 3u] |= EDMA3_DRV_DMAQNUM_SET_MASK((*pLCh), evtQueue);
+
+                        edma3OsProtectExit(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
+                                                                                       intState);
+#endif
+
+                        /* Step 6: Map PaRAM Set to DMA Channel */
+                                               if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
+                               {
+                                           globalRegs->DCHMAP[*pLCh] &= EDMA3_DRV_DCH_PARAM_CLR_MASK;
+                                           globalRegs->DCHMAP[*pLCh] |= EDMA3_DRV_DCH_PARAM_SET_MASK(paRAMId);
                             }
-                        }
 
-                    if (result == EDMA3_DRV_SOK)
+                        /* Step 7: Set TCC in ParamSet.OPT field */
+                        globalRegs->PARAMENTRY [paRAMId].OPT  &= EDMA3_DRV_OPT_TCC_CLR_MASK;
+                        globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
+
+                                               edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_NONE;
+                                               }
+                                       }
+                                       break;
+
+                               case EDMA3_DRV_CHANNEL_TYPE_QDMA:
+                                       {
+                                       unsigned int qdmaChannel = channelObj.resId;
+
+                                       /* Step 4: Register the callback function, if required */
+                                       if (NULL != tccCb)
+                                               {
+                           result = EDMA3_RM_registerTccCb (drvInst->resMgrInstance,
+                                                                           (EDMA3_RM_ResDesc *)&channelObj,
+                                                                           *pTcc, tccCb, cbData);
+                                               }
+                    if (result != EDMA3_DRV_SOK)
                         {
-                        /* Save the PaRAM Id and Trigger mode */
-                        edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].paRAMId = paRAMId;
-                        edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].trigMode =
-                                                                EDMA3_DRV_TRIG_MODE_NONE;
-
-                        /* Make the Link field NULL */
-                        /* Get the Link-bcntReload PaRAM set entry */
-                        linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +
-                                                (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
-
-                        /* Remove any linking */
-                        linkBcntReld |= 0xFFFFu;
-
-                        /* Store it back */
-                        *((&globalRegs->PARAMENTRY[paRAMId].OPT)
-                                    + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;
-
-                        /*
-                        * For QDMA channels, Enable the transfer.
-                        * So that user doesn't have to call EDMA3_DRV_enableTransfer() again.
-                        */
-                        if (((*pLCh) >= EDMA3_DRV_QDMA_CH_MIN_VAL)
-                             && ((*pLCh) <= EDMA3_DRV_QDMA_CH_MAX_VAL))
-                            {
-                            drvInst->shadowRegs->QEESR = (1u<<((*pLCh)-EDMA3_DRV_QDMA_CH_MIN_VAL));
-                            /* save the trigger mode for future use */
-                            edma3DrvChBoundRes[drvObject->phyCtrllerInstId][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;
-                            }
+                        EDMA3_DRV_freeChannel (hEdma, *pLCh);
+                        result = EDMA3_DRV_E_TCC_REGISTER_FAIL;
                         }
-                    }
-                }
-            }
-        }
+                                       else
+                                               {
+#ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
+                                               unsigned int intState = 0;
+                        edma3OsProtectEntry(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
+                                                                                       &intState);
+                        /* Step 5: Associate QDMA Channel to Event Queue */
+                        globalRegs->QDMAQNUM &= EDMA3_DRV_QDMAQNUM_CLR_MASK(qdmaChannel);
+                        globalRegs->QDMAQNUM |= EDMA3_DRV_QDMAQNUM_SET_MASK(qdmaChannel, evtQueue);
+
+                        edma3OsProtectExit(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
+                                                                                       intState);
+#endif
+
+                        /* Step 6: Map PaRAM Set to DMA Channel and set the Default Trigger Word */
+                                       globalRegs->QCHMAP[qdmaChannel] &= EDMA3_DRV_QCH_PARAM_TRWORD_CLR_MASK;
+                                       globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_PARAM_SET_MASK(paRAMId);
+                                       globalRegs->QCHMAP[qdmaChannel] |= EDMA3_DRV_QCH_TRWORD_SET_MASK(EDMA3_RM_QDMA_TRIG_DEFAULT);
+
+                        /* Step 7: Set TCC in ParamSet.OPT field */
+                        globalRegs->PARAMENTRY [paRAMId].OPT  &= EDMA3_DRV_OPT_TCC_CLR_MASK;
+                        globalRegs->PARAMENTRY [paRAMId].OPT |= EDMA3_DRV_OPT_TCC_SET_MASK(*pTcc);
+
+                                               edma3DrvChBoundRes[edma3Id][*pLCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;
+
+                                               /* Step 8: Enable the QDMA Channel */
+                                               drvInst->shadowRegs->QEESR = 1u << qdmaChannel;
+                                               }
+                                       }
+                                       break;
+                               }
+                       }
+               else
+                       {
+                       /* TCC allocation failed, free the PaRAM Set, */
+            resObj.type = EDMA3_RM_RES_PARAM_SET;
+            resObj.resId = (unsigned int)paRAMId;
+            EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
+
+                       /* And free the DMA/QDMA channel */
+                       EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&channelObj);
+
+                       result = EDMA3_DRV_E_TCC_UNAVAIL;
+                       }
+               }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -725,6 +761,7 @@ EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
     int paRAMId;
     unsigned int tcc;
     EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE;
+    unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -736,13 +773,13 @@ EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((channelId > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
+    if (hEdma == NULL)
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
 #endif
 
-    if (result == EDMA3_DRV_SOK)
+    if (EDMA3_DRV_SOK == result)
         {
         drvInst = (EDMA3_DRV_Instance *)hEdma;
         drvObject = drvInst->pDrvObjectHandle;
@@ -751,37 +788,43 @@ EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
+               else
+                       {
+                       edma3Id = drvObject->phyCtrllerInstId;
+                       }
         }
 
-    if (result == EDMA3_DRV_SOK)
+    if (EDMA3_DRV_SOK == result)
         {
         /* Check the channel type */
-        if (channelId <= EDMA3_DRV_DMA_CH_MAX_VAL)
+        if (channelId <= edma3_dma_ch_max_val [edma3Id])
             {
             /* DMA Channel */
             chType = EDMA3_DRV_CHANNEL_TYPE_DMA;
             }
 
-        if ((channelId >= EDMA3_DRV_LINK_CH_MIN_VAL) && (channelId <= EDMA3_DRV_LINK_CH_MAX_VAL))
+        if ((channelId >= edma3_link_ch_min_val[edma3Id])
+                               && (channelId <= edma3_link_ch_max_val[edma3Id]))
             {
             /* LINK Channel */
             chType = EDMA3_DRV_CHANNEL_TYPE_LINK;
             }
 
-        if ((channelId >= EDMA3_DRV_QDMA_CH_MIN_VAL) && (channelId <= EDMA3_DRV_QDMA_CH_MAX_VAL))
+        if ((channelId >= edma3_qdma_ch_min_val[edma3Id])
+                               && (channelId <= edma3_qdma_ch_max_val[edma3Id]))
             {
             /* QDMA Channel */
             chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
             }
 
-        if (chType == 0)
+        if (chType == EDMA3_DRV_CHANNEL_TYPE_NONE)
             {
             result = EDMA3_DRV_E_INVALID_PARAM;
             }
         }
 
 
-    if (result == EDMA3_DRV_SOK)
+    if (EDMA3_DRV_SOK == result)
         {
         if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
             {
@@ -789,21 +832,21 @@ EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
             resObj.type = EDMA3_RM_RES_PARAM_SET;
 
             /* Get the PaRAM id from the book-keeping info. */
-            resObj.resId = (unsigned int)(edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId);
+            resObj.resId = (unsigned int)(edma3DrvChBoundRes[edma3Id][channelId].paRAMId);
 
             result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
                                         (EDMA3_RM_ResDesc *)&resObj);
 
-            if (result == EDMA3_DRV_SOK)
+            if (EDMA3_DRV_SOK == result)
                 {
-                edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId = -1;
+                edma3DrvChBoundRes[edma3Id][channelId].paRAMId = -1;
                 }
             }
         else
             {
             /* DMA/QDMA Channel */
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId;
-            tcc = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].tcc;
+            paRAMId = edma3DrvChBoundRes[edma3Id][channelId].paRAMId;
+            tcc = edma3DrvChBoundRes[edma3Id][channelId].tcc;
 
             /* Check the paRAMId and tcc values first */
             if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
@@ -816,23 +859,23 @@ EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
                 result = EDMA3_DRV_E_INVALID_PARAM;
                 }
 
-            if (result == EDMA3_DRV_SOK)
+            if (EDMA3_DRV_SOK == result)
                 {
                 /* Disable the transfer and remove various mappings. */
                 result = edma3RemoveMapping(hEdma, channelId);
                 }
 
-            if (result == EDMA3_DRV_SOK)
+            if (EDMA3_DRV_SOK == result)
                 {
                 /* Now Free the PARAM set and TCC */
                 resObj.type = EDMA3_RM_RES_PARAM_SET;
                 resObj.resId = (unsigned int)paRAMId;
                 result = EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
 
-                if (result == EDMA3_DRV_SOK)
+                if (EDMA3_DRV_SOK == result)
                     {
                     /* PaRAM Set Freed */
-                    edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].paRAMId = -1;
+                    edma3DrvChBoundRes[edma3Id][channelId].paRAMId = -1;
 
                     /* Free the TCC */
                     resObj.type = EDMA3_RM_RES_TCC;
@@ -841,16 +884,16 @@ EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
                                                 (EDMA3_RM_ResDesc *)&resObj);
                     }
 
-                if (result == EDMA3_DRV_SOK)
+                if (EDMA3_DRV_SOK == result)
                     {
                     /* TCC Freed. */
-                    edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].tcc = 0;
+                    edma3DrvChBoundRes[edma3Id][channelId].tcc = EDMA3_MAX_TCC;
 
                     /* Now free the DMA/QDMA Channel in the end. */
                     if (chType == EDMA3_DRV_CHANNEL_TYPE_QDMA)
                         {
                         resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
-                        resObj.resId = (channelId - EDMA3_DRV_QDMA_CH_MIN_VAL);
+                        resObj.resId = (channelId - edma3_qdma_ch_min_val[edma3Id]);
                         result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
                                                     (EDMA3_RM_ResDesc *)&resObj);
                         }
@@ -880,11 +923,11 @@ EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
 
 
 /**
- *  \brief  Disables the DMA Channel by clearing the Event Enable Register and 
+ *  \brief  Disables the DMA Channel by clearing the Event Enable Register and
  *     clears Error Register & Secondary Event Register for a specific DMA channel.
  *
  *  This API clears the Event Enable register, Event Miss register and Secondary
- *     Event register for a specific DMA channel. It also clears the CC Error 
+ *     Event register for a specific DMA channel. It also clears the CC Error
  *     register.
  *
  *  \param  hEdma            [IN]     Handle to the EDMA Driver Instance.
@@ -904,6 +947,7 @@ EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
     unsigned int count;
     unsigned int value = 0;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -933,9 +977,11 @@ EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
             }
         else
             {
+            edma3Id = drvObject->phyCtrllerInstId;
+
                        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-            if (channelId > EDMA3_DRV_DMA_CH_MAX_VAL)
+            if (channelId > edma3_dma_ch_max_val [edma3Id])
                 {
                 result = EDMA3_DRV_E_INVALID_PARAM;
                 }
@@ -1026,6 +1072,7 @@ EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
     unsigned int oldOptVal = 0;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1037,7 +1084,7 @@ EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
+    if ((hEdma == NULL)
         || ((optField < EDMA3_DRV_OPT_FIELD_SAM)
         || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))
         {
@@ -1057,82 +1104,94 @@ EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
             }
         else
             {
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
-            if (result == EDMA3_DRV_SOK)
-                {
-                oldOptVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+               }
 
-                switch (optField)
-                    {
-                    case EDMA3_DRV_OPT_FIELD_SAM :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_SAM_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_SAM_SET_MASK(newOptFieldVal));
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_DAM :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_DAM_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_DAM_SET_MASK(newOptFieldVal));
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_SYNCDIM :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_SYNCDIM_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_SYNCDIM_SET_MASK(newOptFieldVal));
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_STATIC :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_STATIC_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_STATIC_SET_MASK(newOptFieldVal));
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_FWID :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_FWID_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_FWID_SET_MASK(newOptFieldVal));
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_TCCMODE :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCMODE_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_TCCMODE_SET_MASK(newOptFieldVal));
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_TCC :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCC_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_TCC_SET_MASK(newOptFieldVal));
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_TCINTEN :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCINTEN_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_TCINTEN_SET_MASK(newOptFieldVal));
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_ITCINTEN :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCINTEN_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_ITCINTEN_SET_MASK(newOptFieldVal));
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_TCCHEN :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCHEN_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_TCCHEN_SET_MASK(newOptFieldVal));
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_ITCCHEN :
-                        newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCCHEN_CLR_MASK)
-                                    |
-                                    (EDMA3_DRV_OPT_ITCCHEN_SET_MASK(newOptFieldVal));
-                        break;
-                    default:
-                        break;
-                    }
+    if (EDMA3_DRV_SOK == result)
+        {
+        oldOptVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
 
-                *(&globalRegs->PARAMENTRY[paRAMId].OPT) = newOptVal;
-                }
+        switch (optField)
+            {
+            case EDMA3_DRV_OPT_FIELD_SAM :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_SAM_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_SAM_SET_MASK(newOptFieldVal));
+                break;
+            case EDMA3_DRV_OPT_FIELD_DAM :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_DAM_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_DAM_SET_MASK(newOptFieldVal));
+                break;
+            case EDMA3_DRV_OPT_FIELD_SYNCDIM :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_SYNCDIM_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_SYNCDIM_SET_MASK(newOptFieldVal));
+                break;
+            case EDMA3_DRV_OPT_FIELD_STATIC :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_STATIC_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_STATIC_SET_MASK(newOptFieldVal));
+                break;
+            case EDMA3_DRV_OPT_FIELD_FWID :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_FWID_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_FWID_SET_MASK(newOptFieldVal));
+                break;
+            case EDMA3_DRV_OPT_FIELD_TCCMODE :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCMODE_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_TCCMODE_SET_MASK(newOptFieldVal));
+                break;
+            case EDMA3_DRV_OPT_FIELD_TCC :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCC_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_TCC_SET_MASK(newOptFieldVal));
+                break;
+            case EDMA3_DRV_OPT_FIELD_TCINTEN :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCINTEN_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_TCINTEN_SET_MASK(newOptFieldVal));
+                break;
+            case EDMA3_DRV_OPT_FIELD_ITCINTEN :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCINTEN_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_ITCINTEN_SET_MASK(newOptFieldVal));
+                break;
+            case EDMA3_DRV_OPT_FIELD_TCCHEN :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_TCCHEN_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_TCCHEN_SET_MASK(newOptFieldVal));
+                break;
+            case EDMA3_DRV_OPT_FIELD_ITCCHEN :
+                newOptVal = (oldOptVal & EDMA3_DRV_OPT_ITCCHEN_CLR_MASK)
+                            |
+                            (EDMA3_DRV_OPT_ITCCHEN_SET_MASK(newOptFieldVal));
+                break;
+            default:
+                break;
             }
+
+        *(&globalRegs->PARAMENTRY[paRAMId].OPT) = newOptVal;
         }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
@@ -1177,6 +1236,7 @@ EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
     unsigned int optVal = 0;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1188,8 +1248,7 @@ EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if (((lCh > EDMA3_DRV_LOG_CH_MAX_VAL)
-        || ((hEdma == NULL) || (optFieldVal == NULL)))
+    if (((hEdma == NULL) || (optFieldVal == NULL))
         || ((optField < EDMA3_DRV_OPT_FIELD_SAM)
         || (optField > EDMA3_DRV_OPT_FIELD_ITCCHEN)))
         {
@@ -1209,57 +1268,69 @@ EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
             }
         else
             {
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
-            if (result == EDMA3_DRV_SOK)
-                {
-                optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+               }
 
-                switch (optField)
-                    {
-                    case EDMA3_DRV_OPT_FIELD_SAM :
-                        *optFieldVal = EDMA3_DRV_OPT_SAM_GET_MASK(optVal);
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_DAM :
-                        *optFieldVal = EDMA3_DRV_OPT_DAM_GET_MASK(optVal);
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_SYNCDIM :
-                        *optFieldVal = EDMA3_DRV_OPT_SYNCDIM_GET_MASK(optVal);
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_STATIC :
-                        *optFieldVal = EDMA3_DRV_OPT_STATIC_GET_MASK(optVal);
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_FWID :
-                        *optFieldVal = EDMA3_DRV_OPT_FWID_GET_MASK(optVal);
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_TCCMODE :
-                        *optFieldVal = EDMA3_DRV_OPT_TCCMODE_GET_MASK(optVal);
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_TCC :
-                        *optFieldVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal);
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_TCINTEN :
-                        *optFieldVal = EDMA3_DRV_OPT_TCINTEN_GET_MASK(optVal);
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_ITCINTEN :
-                        *optFieldVal = EDMA3_DRV_OPT_ITCINTEN_GET_MASK(optVal);
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_TCCHEN :
-                        *optFieldVal = EDMA3_DRV_OPT_TCCHEN_GET_MASK(optVal);
-                        break;
-                    case EDMA3_DRV_OPT_FIELD_ITCCHEN :
-                        *optFieldVal = EDMA3_DRV_OPT_ITCCHEN_GET_MASK(optVal);
-                        break;
-                    default:
-                        break;
-                    }
-                }
+    if (EDMA3_DRV_SOK == result)
+        {
+        optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+
+        switch (optField)
+            {
+            case EDMA3_DRV_OPT_FIELD_SAM :
+                *optFieldVal = EDMA3_DRV_OPT_SAM_GET_MASK(optVal);
+                break;
+            case EDMA3_DRV_OPT_FIELD_DAM :
+                *optFieldVal = EDMA3_DRV_OPT_DAM_GET_MASK(optVal);
+                break;
+            case EDMA3_DRV_OPT_FIELD_SYNCDIM :
+                *optFieldVal = EDMA3_DRV_OPT_SYNCDIM_GET_MASK(optVal);
+                break;
+            case EDMA3_DRV_OPT_FIELD_STATIC :
+                *optFieldVal = EDMA3_DRV_OPT_STATIC_GET_MASK(optVal);
+                break;
+            case EDMA3_DRV_OPT_FIELD_FWID :
+                *optFieldVal = EDMA3_DRV_OPT_FWID_GET_MASK(optVal);
+                break;
+            case EDMA3_DRV_OPT_FIELD_TCCMODE :
+                *optFieldVal = EDMA3_DRV_OPT_TCCMODE_GET_MASK(optVal);
+                break;
+            case EDMA3_DRV_OPT_FIELD_TCC :
+                *optFieldVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal);
+                break;
+            case EDMA3_DRV_OPT_FIELD_TCINTEN :
+                *optFieldVal = EDMA3_DRV_OPT_TCINTEN_GET_MASK(optVal);
+                break;
+            case EDMA3_DRV_OPT_FIELD_ITCINTEN :
+                *optFieldVal = EDMA3_DRV_OPT_ITCINTEN_GET_MASK(optVal);
+                break;
+            case EDMA3_DRV_OPT_FIELD_TCCHEN :
+                *optFieldVal = EDMA3_DRV_OPT_TCCHEN_GET_MASK(optVal);
+                break;
+            case EDMA3_DRV_OPT_FIELD_ITCCHEN :
+                *optFieldVal = EDMA3_DRV_OPT_ITCCHEN_GET_MASK(optVal);
+                break;
+            default:
+                break;
             }
         }
 
@@ -1316,6 +1387,7 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
     unsigned int mappedEvtQ = 0;
     unsigned int defaultBurstSize = 0;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1327,9 +1399,9 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
-        || ((addrMode < EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO)))
-        || ((fifoWidth < EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT)))
+    if ((hEdma == NULL)
+        || (((addrMode < EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))
+        || ((fifoWidth < EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))))
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -1355,72 +1427,84 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
             }
         else
             {
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+               }
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        /**
+          * If request is for FIFO mode, check whether the FIFO size
+          * is supported by the Transfer Controller which will be used for
+          * this transfer or not.
+          */
+        if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
+            {
+            if (lCh <= edma3_dma_ch_max_val [edma3Id])
                 {
-                result = EDMA3_DRV_E_INVALID_PARAM;
+                mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u])
+                                & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
+                                  >> ((lCh%8u)*4u);
                 }
-
-            if (result == EDMA3_DRV_SOK)
+            else
                 {
-                /**
-                  * If request is for FIFO mode, check whether the FIFO size
-                  * is supported by the Transfer Controller which will be used for
-                  * this transfer or not.
-                  */
-                if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
+                if ((lCh >= edma3_qdma_ch_min_val[edma3Id])
+                     &&(lCh <= edma3_qdma_ch_max_val[edma3Id]))
                     {
-                    if (lCh <= EDMA3_DRV_DMA_CH_MAX_VAL)
-                        {
-                        mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u])
-                                        & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
-                                          >> ((lCh%8u)*4u);
-                        }
-                    else
-                        {
-                        if ((lCh >= EDMA3_DRV_QDMA_CH_MIN_VAL)
-                             &&(lCh <= EDMA3_DRV_QDMA_CH_MAX_VAL))
-                            {
-                            mappedEvtQ = ((globalRegs->QDMAQNUM)
-                                            & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh -EDMA3_DRV_QDMA_CH_MIN_VAL))))
-                                           >> (lCh*4u);
-                            }
-                        }
-
-                    /**
-                       * mappedEvtQ contains the event queue and hence the TC which will
-                       * process this transfer request. Check whether this TC supports the
-                       * FIFO size or not.
-                       */
-                    defaultBurstSize = 1u << fifoWidth;
-                    if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
-                        {
-                        result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
-                        }
+                    mappedEvtQ = ((globalRegs->QDMAQNUM)
+                                    & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
+                                   >> (lCh*4u);
                     }
+                }
 
-                if (EDMA3_DRV_SOK == result)
-                    {
-                    /* Set Src Address */
-                    *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
-                                (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC) = srcAddr;
+            /**
+               * mappedEvtQ contains the event queue and hence the TC which will
+               * process this transfer request. Check whether this TC supports the
+               * FIFO size or not.
+               */
+            defaultBurstSize = 1u << fifoWidth;
+            if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
+                {
+                result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
+                }
+            }
+       }
 
-                    opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+       if (EDMA3_DRV_SOK == result)
+        {
+        /* Set Src Address */
+        *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
+                    (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC) = srcAddr;
 
-                    /* Set SAM */
-                    opt &= EDMA3_DRV_OPT_SAM_CLR_MASK;
-                    opt |= EDMA3_DRV_OPT_SAM_SET_MASK(addrMode);
-                    /* Set FIFO Width */
-                    opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
-                    opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
+        opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
 
-                    /* Set the OPT */
-                    *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
-                    }
-                }
-            }
+        /* Set SAM */
+        opt &= EDMA3_DRV_OPT_SAM_CLR_MASK;
+        opt |= EDMA3_DRV_OPT_SAM_SET_MASK(addrMode);
+        /* Set FIFO Width */
+        opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
+        opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
+
+        /* Set the OPT */
+        *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
         }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
@@ -1476,6 +1560,7 @@ EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
     unsigned int mappedEvtQ = 0;
     unsigned int defaultBurstSize = 0;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1487,9 +1572,9 @@ EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
-        || ((addrMode < EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO)))
-        || ((fifoWidth < EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT)))
+    if ((hEdma == NULL)
+        || (((addrMode < EDMA3_DRV_ADDR_MODE_INCR) || (addrMode > EDMA3_DRV_ADDR_MODE_FIFO))
+        || ((fifoWidth < EDMA3_DRV_W8BIT) || (fifoWidth > EDMA3_DRV_W256BIT))))
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -1515,72 +1600,84 @@ EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
             }
         else
             {
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+               }
+
+    if (EDMA3_DRV_SOK == result)
+        {
+        /**
+          * If request is for FIFO mode, check whether the FIFO size
+          * is supported by the Transfer Controller which will be used for
+          * this transfer or not.
+          */
+        if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
+            {
+            if (lCh <= edma3_dma_ch_max_val [edma3Id])
                 {
-                result = EDMA3_DRV_E_INVALID_PARAM;
+                mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u])
+                                & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
+                                  >> ((lCh%8u)*4u);
                 }
-
-            if (result == EDMA3_DRV_SOK)
+            else
                 {
-                /**
-                  * If request is for FIFO mode, check whether the FIFO size
-                  * is supported by the Transfer Controller which will be used for
-                  * this transfer or not.
-                  */
-                if (addrMode == EDMA3_DRV_ADDR_MODE_FIFO)
+                if ((lCh >= edma3_qdma_ch_min_val[edma3Id])
+                     &&(lCh <= edma3_qdma_ch_max_val[edma3Id]))
                     {
-                    if (lCh <= EDMA3_DRV_DMA_CH_MAX_VAL)
-                        {
-                        mappedEvtQ = ((globalRegs->DMAQNUM[lCh >> 3u])
-                                        & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(lCh))))
-                                          >> ((lCh%8u)*4u);
-                        }
-                    else
-                        {
-                        if ((lCh >= EDMA3_DRV_QDMA_CH_MIN_VAL)
-                             &&(lCh <= EDMA3_DRV_QDMA_CH_MAX_VAL))
-                            {
-                            mappedEvtQ = ((globalRegs->QDMAQNUM)
-                                            & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh -EDMA3_DRV_QDMA_CH_MIN_VAL))))
-                                           >> (lCh*4u);
-                            }
-                        }
-
-                    /**
-                       * mappedEvtQ contains the event queue and hence the TC which will
-                       * process this transfer request. Check whether this TC supports the
-                       * FIFO size or not.
-                       */
-                    defaultBurstSize = 1u << fifoWidth;
-                    if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
-                        {
-                        result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
-                        }
+                    mappedEvtQ = ((globalRegs->QDMAQNUM)
+                                    & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(lCh - edma3_qdma_ch_min_val[edma3Id]))))
+                                   >> (lCh*4u);
                     }
+                }
 
-                if (EDMA3_DRV_SOK == result)
-                    {
-                    /* Set the Dest address */
-                    *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
-                                (unsigned int)EDMA3_DRV_PARAM_ENTRY_DST) = destAddr;
+            /**
+               * mappedEvtQ contains the event queue and hence the TC which will
+               * process this transfer request. Check whether this TC supports the
+               * FIFO size or not.
+               */
+            defaultBurstSize = 1u << fifoWidth;
+            if (defaultBurstSize > drvObject->gblCfgParams.tcDefaultBurstSize[mappedEvtQ])
+                {
+                result = EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED;
+                }
+            }
+       }
 
-                    opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+    if (EDMA3_DRV_SOK == result)
+        {
+        /* Set the Dest address */
+        *((&globalRegs->PARAMENTRY[paRAMId].OPT) +
+                    (unsigned int)EDMA3_DRV_PARAM_ENTRY_DST) = destAddr;
 
-                    /* Set DAM */
-                    opt &= EDMA3_DRV_OPT_DAM_CLR_MASK;
-                    opt |= EDMA3_DRV_OPT_DAM_SET_MASK(addrMode);
-                    /* Set FIFO Width */
-                    opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
-                    opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
+        opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
 
-                    /* Set the OPT */
-                    *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
-                    }
-                }
-            }
+        /* Set DAM */
+        opt &= EDMA3_DRV_OPT_DAM_CLR_MASK;
+        opt |= EDMA3_DRV_OPT_DAM_SET_MASK(addrMode);
+        /* Set FIFO Width */
+        opt &= EDMA3_DRV_OPT_FWID_CLR_MASK;
+        opt |= EDMA3_DRV_OPT_FWID_SET_MASK(fifoWidth);
+
+        /* Set the OPT */
+        *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
         }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
@@ -1595,7 +1692,6 @@ EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
     }
 
 
-
 /**
  * \brief   DMA source index setup
  *
@@ -1639,6 +1735,7 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1650,7 +1747,7 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
+    if (hEdma == NULL)
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -1676,42 +1773,53 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,
             }
         else
             {
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
-
-            if (result == EDMA3_DRV_SOK)
-                {
-                /* Get SrcDestBidx PaRAM Set entry */
-                srcDstBidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +
-                                                        (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
-
-                srcDstBidx &= 0xFFFF0000u;
-                /* Update it */
-                srcDstBidx |= (unsigned int)(srcBIdx & 0xFFFF);
-
-                /* Store it back */
-                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
-                            + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
-
-                /* Get SrcDestCidx PaRAM Set entry */
-                srcDstCidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +
-                                                        (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
-                srcDstCidx &= 0xFFFF0000u;
-                /* Update it */
-                srcDstCidx |= (unsigned int)(srcCIdx & 0xFFFF);
-
-                /* Store it back */
-                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
-                            + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
-                }
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
             }
-        }
+               else
+               {
+               /* Get SrcDestBidx PaRAM Set entry */
+               srcDstBidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+                                                       + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
+
+               srcDstBidx &= 0xFFFF0000u;
+               /* Update it */
+               srcDstBidx |= (unsigned int)(srcBIdx & 0xFFFF);
+
+               /* Store it back */
+               *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+                           + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
+
+               /* Get SrcDestCidx PaRAM Set entry */
+               srcDstCidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+                                                       + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+
+               srcDstCidx &= 0xFFFF0000u;
+               /* Update it */
+               srcDstCidx |= (unsigned int)(srcCIdx & 0xFFFF);
+
+               /* Store it back */
+               *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+                           + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
+               }
+               }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1768,6 +1876,7 @@ EDMA3_DRV_Result  EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int l
     EDMA3_DRV_Object *drvObject = NULL;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1779,7 +1888,7 @@ EDMA3_DRV_Result  EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int l
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
+    if (hEdma == NULL)
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -1805,40 +1914,51 @@ EDMA3_DRV_Result  EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int l
             }
         else
             {
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
-            if (result == EDMA3_DRV_SOK)
-                {
-                /* Get SrcDestBidx PaRAM Set entry */
-                srcDstBidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +
-                                                        (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+               else
+            {
+            /* Get SrcDestBidx PaRAM Set entry */
+            srcDstBidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+                                                       + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
 
-                srcDstBidx &= 0xFFFFu;
-                /* Update it */
-                srcDstBidx |= (unsigned int)((destBIdx & 0xFFFF) << 16u);
+            srcDstBidx &= 0xFFFFu;
+            /* Update it */
+            srcDstBidx |= (unsigned int)((destBIdx & 0xFFFF) << 16u);
 
-                /* Store it back */
-                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
-                            + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
+            /* Store it back */
+            *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+                        + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
 
-                /* Get SrcDestCidx PaRAM Set entry */
-                srcDstCidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +
-                                                        (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+            /* Get SrcDestCidx PaRAM Set entry */
+            srcDstCidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+                                                       + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
 
-                srcDstCidx &= 0xFFFFu;
-                /* Update it */
-                srcDstCidx |= (unsigned int)((destCIdx & 0xFFFF) << 16u);
+            srcDstCidx &= 0xFFFFu;
+            /* Update it */
+            srcDstCidx |= (unsigned int)((destCIdx & 0xFFFF) << 16u);
 
-                /* Store it back */
-                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
-                            + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
-                }
+            /* Store it back */
+            *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+                        + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
             }
         }
 
@@ -1926,6 +2046,7 @@ EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     int paRAMId = 0;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1937,7 +2058,7 @@ EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
+    if (hEdma == NULL)
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -1964,43 +2085,55 @@ EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,
             }
         else
             {
-            abCnt = aCnt | ((bCnt&0xFFFFu) << 16u);
-            paRAMId = edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].paRAMId;
+            edma3Id = drvObject->phyCtrllerInstId;
             globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
 
-            if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
-                {
-                result = EDMA3_DRV_E_INVALID_PARAM;
-                }
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
 
-            if (result == EDMA3_DRV_SOK)
-                {
-                /* Set aCnt and bCnt */
-                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
-                            + (unsigned int)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = abCnt;
+       if (EDMA3_DRV_SOK == result)
+        {
+        paRAMId = edma3DrvChBoundRes[edma3Id][lCh].paRAMId;
+        if ((paRAMId < 0) || (paRAMId >= drvObject->gblCfgParams.numPaRAMSets))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+               else
+               {
+               abCnt = aCnt | ((bCnt&0xFFFFu) << 16u);
 
-                /* Set cCnt */
-                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
-                            + (unsigned int)EDMA3_DRV_PARAM_ENTRY_CCNT) = cCnt;
+            /* Set aCnt and bCnt */
+            *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+                        + (unsigned int)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = abCnt;
 
+            /* Set cCnt */
+            *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+                        + (unsigned int)EDMA3_DRV_PARAM_ENTRY_CCNT) = cCnt;
 
-                linkBCntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) +
-                                                        (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
 
-                linkBCntReld |= ((bCntReload & 0xFFFFu) << 16u);
+            linkBCntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+                                                       + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
 
-                /* Set bCntReload */
-                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
-                            + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBCntReld;
+            linkBCntReld |= ((bCntReload & 0xFFFFu) << 16u);
 
-                opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+            /* Set bCntReload */
+            *((&globalRegs->PARAMENTRY[paRAMId].OPT)
+                        + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBCntReld;
 
-                /* Set Sync Type */
-                opt &= EDMA3_DRV_OPT_SYNCDIM_CLR_MASK;
-                opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK(syncType);
+            opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
 
-                *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
-                }
+            /* Set Sync Type */
+            opt &= EDMA3_DRV_OPT_SYNCDIM_CLR_MASK;
+            opt |= EDMA3_DRV_OPT_SYNCDIM_SET_MASK(syncType);
+
+            *(&globalRegs->PARAMENTRY[paRAMId].OPT) = opt;
             }
         }
 
@@ -2055,6 +2188,7 @@ EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -2066,14 +2200,38 @@ EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
+    if (hEdma == NULL)
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+       if (EDMA3_DRV_SOK == result)
+        {
+        drvInst = (EDMA3_DRV_Instance *)hEdma;
+        drvObject = drvInst->pDrvObjectHandle;
+
+        if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
+
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
 
     /* Trigger type is Manual */
     if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
-       && (lCh > EDMA3_DRV_DMA_CH_MAX_VAL))
+       && (lCh > edma3_dma_ch_max_val [edma3Id]))
         {
         /* Channel Id lies outside DMA channel range */
         result = EDMA3_DRV_E_INVALID_PARAM;
@@ -2081,96 +2239,81 @@ EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
 
     /* Trigger type is QDMA */
     if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
-       && ((lCh < EDMA3_DRV_QDMA_CH_MIN_VAL)
-       || (lCh > EDMA3_DRV_QDMA_CH_MAX_VAL)))
+       && ((lCh < edma3_qdma_ch_min_val[edma3Id])
+       || (lCh > edma3_qdma_ch_max_val[edma3Id])))
         {
         /* Channel Id lies outside QDMA channel range */
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
+
+       /* Trigger type is Event */
+    if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
+       && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
+         & (1u<<(lCh%32u))) == FALSE))
+       {
+        /* Channel was not mapped to any Hw Event. */
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
 #endif
 
-       /* Check if the parameters are OK. */
        if (EDMA3_DRV_SOK == result)
         {
-        drvInst = (EDMA3_DRV_Instance *)hEdma;
-        drvObject = drvInst->pDrvObjectHandle;
-
-        if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
-            {
-            result = EDMA3_DRV_E_INVALID_PARAM;
-            }
-        else
+        switch (trigMode)
             {
-            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
-
-            switch (trigMode)
+            case EDMA3_DRV_TRIG_MODE_MANUAL :
                 {
-                case EDMA3_DRV_TRIG_MODE_MANUAL :
+                if (lCh < 32u)
                     {
-                    if (lCh < 32u)
-                        {
-                        drvInst->shadowRegs->ESR = (1UL << lCh);
-                        }
-                    else
-                        {
-                        drvInst->shadowRegs->ESRH = (1UL << (lCh-32u));
-                        }
-                    edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].trigMode = EDMA3_DRV_TRIG_MODE_MANUAL;
+                    drvInst->shadowRegs->ESR = (1UL << lCh);
                     }
-                    break;
-
-                case EDMA3_DRV_TRIG_MODE_QDMA :
+                else
                     {
-                    drvInst->shadowRegs->QEESR = (1u<<(lCh - EDMA3_DRV_QDMA_CH_MIN_VAL));
-                    edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].trigMode = EDMA3_DRV_TRIG_MODE_QDMA;
+                    drvInst->shadowRegs->ESRH = (1UL << (lCh-32u));
                     }
-                    break;
-
-                case EDMA3_DRV_TRIG_MODE_EVENT :
-                    {
-                    /* Trigger type is Event */
-/* If parameter checking is enabled... */
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-                    if (((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
-                         & (1u<<(lCh%32u))) == FALSE))
-                       {
-                        /* Channel was not mapped to any Hw Event. */
-                        result = EDMA3_DRV_E_INVALID_PARAM;
-                        }
-#endif
+                edma3DrvChBoundRes[edma3Id][lCh].trigMode =
+                                                                                                       EDMA3_DRV_TRIG_MODE_MANUAL;
+                }
+                break;
 
-                                       if (EDMA3_DRV_SOK == result)
-                                               {
-                           if (lCh < 32u)
-                              {
-                               /*clear SECR to clean any previous NULL request */
-                               drvInst->shadowRegs->SECR = (1UL << lCh);
+            case EDMA3_DRV_TRIG_MODE_QDMA :
+                {
+                drvInst->shadowRegs->QEESR = (1u<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
+                edma3DrvChBoundRes[edma3Id][lCh].trigMode =
+                                                                                                               EDMA3_DRV_TRIG_MODE_QDMA;
+                }
+                break;
 
-                               /*clear EMCR to clean any previous NULL request */
-                               globalRegs->EMCR = (1UL << lCh);
+            case EDMA3_DRV_TRIG_MODE_EVENT :
+                {
+                if (lCh < 32u)
+                   {
+                    /*clear SECR to clean any previous NULL request */
+                    drvInst->shadowRegs->SECR = (1UL << lCh);
 
-                               drvInst->shadowRegs->EESR = (1UL << lCh);
-                               }
-                           else
-                               {
-                               /*clear SECR to clean any previous NULL request */
-                               drvInst->shadowRegs->SECRH = (1UL << (lCh-32u));
+                    /*clear EMCR to clean any previous NULL request */
+                    globalRegs->EMCR = (1UL << lCh);
 
-                               /*clear EMCR to clean any previous NULL request */
-                               globalRegs->EMCRH = (1UL << (lCh-32u));
+                    drvInst->shadowRegs->EESR = (1UL << lCh);
+                    }
+                else
+                    {
+                    /*clear SECR to clean any previous NULL request */
+                    drvInst->shadowRegs->SECRH = (1UL << (lCh-32u));
 
-                               drvInst->shadowRegs->EESRH = (1UL << (lCh-32u));
-                               }
+                    /*clear EMCR to clean any previous NULL request */
+                    globalRegs->EMCRH = (1UL << (lCh-32u));
 
-                           edma3DrvChBoundRes[drvObject->phyCtrllerInstId][lCh].trigMode = EDMA3_DRV_TRIG_MODE_EVENT;
-                       }
+                    drvInst->shadowRegs->EESRH = (1UL << (lCh-32u));
                     }
-                    break;
 
-                default :
-                    result = EDMA3_DRV_E_INVALID_PARAM;
-                    break;
-                }
+                edma3DrvChBoundRes[edma3Id][lCh].trigMode =
+                                                                                                               EDMA3_DRV_TRIG_MODE_EVENT;
+               }
+                break;
+
+            default :
+                result = EDMA3_DRV_E_INVALID_PARAM;
+                break;
             }
         }
 
@@ -2220,6 +2363,7 @@ EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Instance *drvInst = NULL;
     EDMA3_DRV_Object *drvObject = NULL;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -2231,14 +2375,39 @@ EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
+    if (hEdma == NULL)
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+#endif
+
+       /* Check if the parameters are OK. */
+       if (EDMA3_DRV_SOK == result)
+        {
+        drvInst = (EDMA3_DRV_Instance *)hEdma;
+        drvObject = drvInst->pDrvObjectHandle;
+
+        if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
+            {
+            result = EDMA3_DRV_E_INVALID_PARAM;
+            }
+        else
+            {
+            edma3Id = drvObject->phyCtrllerInstId;
+            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
+               }
+               }
+
+       /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+    if (lCh > edma3_log_ch_max_val [edma3Id])
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
 
     /* Trigger type is Manual */
     if ((EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
-       && (lCh > EDMA3_DRV_DMA_CH_MAX_VAL))
+       && (lCh > edma3_dma_ch_max_val [edma3Id]))
         {
         /* Channel Id lies outside DMA channel range */
         result = EDMA3_DRV_E_INVALID_PARAM;
@@ -2246,122 +2415,104 @@ EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
 
     /* Trigger type is QDMA */
     if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
-       && ((lCh < EDMA3_DRV_QDMA_CH_MIN_VAL)
-       || (lCh > EDMA3_DRV_QDMA_CH_MAX_VAL)))
+       && ((lCh < edma3_qdma_ch_min_val[edma3Id])
+       || (lCh > edma3_qdma_ch_max_val[edma3Id])))
         {
         /* Channel Id lies outside QDMA channel range */
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
+
+       /* Trigger type is Event */
+    if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
+       && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
+         & (1u<<(lCh%32u))) == FALSE))
+       {
+        /* Channel was not mapped to any Hw Event. */
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
 #endif
 
-       /* Check if the parameters are OK. */
        if (EDMA3_DRV_SOK == result)
         {
-        drvInst = (EDMA3_DRV_Instance *)hEdma;
-        drvObject = drvInst->pDrvObjectHandle;
-
-        if ((drvObject == NULL) || (drvObject->gblCfgParams.globalRegs == NULL))
-            {
-            result = EDMA3_DRV_E_INVALID_PARAM;
-            }
-        else
+        switch (trigMode)
             {
-            globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
-
-            switch (trigMode)
+            case EDMA3_DRV_TRIG_MODE_MANUAL :
                 {
-                case EDMA3_DRV_TRIG_MODE_MANUAL :
+                if (lCh < 32u)
                     {
-                    if (lCh < 32u)
+                    if((drvInst->shadowRegs->SER & (1u<<lCh))!=FALSE)
                         {
-                        if((drvInst->shadowRegs->SER & (1u<<lCh))!=FALSE)
-                            {
-                            drvInst->shadowRegs->SECR = (1u<<lCh);
-                            }
-                        if((globalRegs->EMR & (1u<<lCh))!=FALSE)
-                            {
-                            globalRegs->EMCR = (1u<<lCh);
-                            }
+                        drvInst->shadowRegs->SECR = (1u<<lCh);
                         }
-                    else
+                    if((globalRegs->EMR & (1u<<lCh))!=FALSE)
                         {
-                        if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE)
-                            {
-                            drvInst->shadowRegs->SECRH = (1u<<(lCh-32u));
-                            }
+                        globalRegs->EMCR = (1u<<lCh);
+                        }
+                    }
+                else
+                    {
+                    if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE)
+                        {
+                        drvInst->shadowRegs->SECRH = (1u<<(lCh-32u));
+                        }
 
-                        if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE)
-                            {
-                            globalRegs->EMCRH = (1u<<(lCh-32u));
-                            }
+                    if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE)
+                        {
+                        globalRegs->EMCRH = (1u<<(lCh-32u));
                         }
                     }
-                    break;
+                }
+                break;
+
+            case EDMA3_DRV_TRIG_MODE_QDMA :
+                {
+                drvInst->shadowRegs->QEECR = (1u<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
+                }
+                break;
 
-                case EDMA3_DRV_TRIG_MODE_QDMA :
+            case EDMA3_DRV_TRIG_MODE_EVENT :
+                {
+                if (lCh < 32u)
                     {
-                    drvInst->shadowRegs->QEECR = (1u<<(lCh - EDMA3_DRV_QDMA_CH_MIN_VAL));
-                    }
-                    break;
+                    drvInst->shadowRegs->EECR = (1u << lCh);
 
-                case EDMA3_DRV_TRIG_MODE_EVENT :
+                    if((drvInst->shadowRegs->ER & (1u<<lCh))!=FALSE)
+                        {
+                        drvInst->shadowRegs->ECR = (1u<<lCh);
+                        }
+                    if((drvInst->shadowRegs->SER & (1u<<lCh))!=FALSE)
+                        {
+                        drvInst->shadowRegs->SECR = (1u<<lCh);
+                        }
+                    if((globalRegs->EMR & (1u<<lCh))!=FALSE)
+                        {
+                        globalRegs->EMCR = (1u<<lCh);
+                        }
+                    }
+                else
                     {
-                    /* Trigger type is Event */
-/* If parameter checking is enabled... */
-#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-                    if (((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
-                         & (1u<<(lCh%32u))) == FALSE))
-                       {
-                        /* Channel was not mapped to any Hw Event. */
-                        result = EDMA3_DRV_E_INVALID_PARAM;
+                    drvInst->shadowRegs->EECRH = (1u << (lCh-32u));
+                    if((drvInst->shadowRegs->ERH & (1u<<(lCh-32u)))!=FALSE)
+                        {
+                        drvInst->shadowRegs->ECRH = (1u<<(lCh-32u));
                         }
-#endif
 
-                                       if (EDMA3_DRV_SOK == result)
-                                               {
-                           if (lCh < 32u)
-                               {
-                               drvInst->shadowRegs->EECR = (1u << lCh);
-
-                               if((drvInst->shadowRegs->ER & (1u<<lCh))!=FALSE)
-                                   {
-                                   drvInst->shadowRegs->ECR = (1u<<lCh);
-                                   }
-                               if((drvInst->shadowRegs->SER & (1u<<lCh))!=FALSE)
-                                   {
-                                   drvInst->shadowRegs->SECR = (1u<<lCh);
-                                   }
-                               if((globalRegs->EMR & (1u<<lCh))!=FALSE)
-                                   {
-                                   globalRegs->EMCR = (1u<<lCh);
-                                   }
-                               }
-                           else
-                               {
-                               drvInst->shadowRegs->EECRH = (1u << (lCh-32u));
-                               if((drvInst->shadowRegs->ERH & (1u<<(lCh-32u)))!=FALSE)
-                                   {
-                                   drvInst->shadowRegs->ECRH = (1u<<(lCh-32u));
-                                   }
-
-                               if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE)
-                                   {
-                                   drvInst->shadowRegs->SECRH = (1u<<(lCh-32u));
-                                   }
-
-                               if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE)
-                                   {
-                                   globalRegs->EMCRH = (1u<<(lCh-32u));
-                                   }
-                               }
+                    if((drvInst->shadowRegs->SERH & (1u<<(lCh-32u)))!=FALSE)
+                        {
+                        drvInst->shadowRegs->SECRH = (1u<<(lCh-32u));
                         }
-                    }
-                    break;
 
-                default :
-                    result = EDMA3_DRV_E_INVALID_PARAM;
-                    break;
+                    if((globalRegs->EMRH & (1u<<(lCh-32u)))!=FALSE)
+                        {
+                        globalRegs->EMCRH = (1u<<(lCh-32u));
+                        }
+                    }
                 }
+                break;
+
+            default :
+                result = EDMA3_DRV_E_INVALID_PARAM;
+                break;
             }
         }
 
@@ -2379,12 +2530,12 @@ EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
 /**
  * \brief Disable the event driven DMA channel or QDMA channel
  *
- * This API disables the DMA channel (which was previously triggered in event 
+ * This API disables the DMA channel (which was previously triggered in event
  * mode) by clearing the Event Enable Register; it disables the QDMA channel by
  * clearing the QDMA Event Enable Register.
  *
  * This API should NOT be used for DMA channels which are not mapped to any
- * hardware events and are used for memory-to-memory copy based transfers. In 
+ * hardware events and are used for memory-to-memory copy based transfers. In
  * case of that, this API returns error.
  *
  * \param   hEdma       [IN]    Handle to the EDMA Driver Instance
@@ -2402,6 +2553,7 @@ EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
     EDMA3_DRV_Instance *drvInst = NULL;
     EDMA3_DRV_Object *drvObject = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -2413,21 +2565,8 @@ EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((lCh > EDMA3_DRV_LOG_CH_MAX_VAL) || (hEdma == NULL))
-        {
-        result = EDMA3_DRV_E_INVALID_PARAM;
-        }
-
-    /* Trigger type is Manual */
-    if (EDMA3_DRV_TRIG_MODE_MANUAL == trigMode)
-        result = EDMA3_DRV_E_INVALID_PARAM;
-               
-    /* Trigger type is QDMA */
-    if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
-       && ((lCh < EDMA3_DRV_QDMA_CH_MIN_VAL)
-       || (lCh > EDMA3_DRV_QDMA_CH_MAX_VAL)))
+    if (hEdma == NULL)
         {
-        /* Channel Id lies outside QDMA channel range */
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
 #endif
@@ -2444,41 +2583,58 @@ EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
             }
         else
             {
-            switch (trigMode)
-                {
-                case EDMA3_DRV_TRIG_MODE_QDMA:
-                    {
-                    drvInst->shadowRegs->QEECR = (1u<<(lCh - EDMA3_DRV_QDMA_CH_MIN_VAL));
-                    }
-                    break;
+            edma3Id = drvObject->phyCtrllerInstId;
+               }
+               }
 
-                case EDMA3_DRV_TRIG_MODE_EVENT:
-                    {
-                    /* Trigger type is Event */
-/* If parameter checking is enabled... */
+       /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-                    if (((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
-                         & (1u<<(lCh%32u))) == FALSE))
-                       {
-                        /* Channel was not mapped to any Hw Event. */
-                        result = EDMA3_DRV_E_INVALID_PARAM;
-                        }
+    if (lCh > edma3_log_ch_max_val [edma3Id])
+        {
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+
+    /* Trigger type is QDMA */
+    if ((EDMA3_DRV_TRIG_MODE_QDMA == trigMode)
+       && ((lCh < edma3_qdma_ch_min_val[edma3Id])
+       || (lCh > edma3_qdma_ch_max_val[edma3Id])))
+        {
+        /* Channel Id lies outside QDMA channel range */
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
+
+       /* Trigger type is Event */
+    if ((EDMA3_DRV_TRIG_MODE_EVENT == trigMode)
+       && ((drvObject->gblCfgParams.dmaChannelHwEvtMap [lCh/32u]
+         & (1u<<(lCh%32u))) == FALSE))
+       {
+        /* Channel was not mapped to any Hw Event. */
+        result = EDMA3_DRV_E_INVALID_PARAM;
+        }
 #endif
 
-                                       if (EDMA3_DRV_SOK == result)
-                                               {
-                           if (lCh < 32u)
-                               drvInst->shadowRegs->EECR = (1u << lCh);
-                           else
-                               drvInst->shadowRegs->EECRH = (1u << (lCh-32u));
-                        }
-                    }
-                    break;
+       if (EDMA3_DRV_SOK == result)
+        {
+        switch (trigMode)
+            {
+            case EDMA3_DRV_TRIG_MODE_QDMA:
+                {
+                drvInst->shadowRegs->QEECR = (1u<<(lCh - edma3_qdma_ch_min_val[edma3Id]));
+                }
+                break;
 
-                default :
-                    result = EDMA3_DRV_E_INVALID_PARAM;
-                    break;
+            case EDMA3_DRV_TRIG_MODE_EVENT:
+                {
+                if (lCh < 32u)
+                    drvInst->shadowRegs->EECR = (1u << lCh);
+                else
+                    drvInst->shadowRegs->EECRH = (1u << (lCh-32u));
                 }
+                break;
+
+            default :
+                result = EDMA3_DRV_E_INVALID_PARAM;
+                break;
             }
         }
 
@@ -2498,14 +2654,15 @@ EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
 static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
                                  unsigned int channelId)
     {
-    unsigned int intState;
+       unsigned int intState=0;
     EDMA3_DRV_Instance *drvInst = NULL;
     EDMA3_DRV_Object *drvObject = NULL;
     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
     EDMA3_RM_ResDesc channelObj;
+       unsigned int edma3Id;
 
-    assert ((hEdma != NULL) && (channelId <= EDMA3_DRV_LOG_CH_MAX_VAL));
+       assert (hEdma != NULL);
 
     drvInst = (EDMA3_DRV_Instance *)hEdma;
     drvObject = drvInst->pDrvObjectHandle;
@@ -2516,86 +2673,90 @@ static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
         }
     else
         {
+        edma3Id = drvObject->phyCtrllerInstId;
         globalRegs = (volatile EDMA3_CCRL_Regs *)
                                 (drvObject->gblCfgParams.globalRegs);
+       }
 
-        /**
-         * Disable any ongoing transfer on the channel, if transfer was
-         * enabled earlier.
-         */
-        if (EDMA3_DRV_TRIG_MODE_NONE !=
-            edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].trigMode)
+       assert (channelId <= edma3_log_ch_max_val [edma3Id]);
+
+
+    /**
+     * Disable any ongoing transfer on the channel, if transfer was
+     * enabled earlier.
+     */
+    if (EDMA3_DRV_TRIG_MODE_NONE !=
+        edma3DrvChBoundRes[edma3Id][channelId].trigMode)
+        {
+        result = EDMA3_DRV_disableTransfer(hEdma, channelId,
+            edma3DrvChBoundRes[edma3Id][channelId].trigMode);
+        }
+
+    if (EDMA3_DRV_SOK == result)
+        {
+        /*
+        * Unregister the TCC Callback function and disable the interrupts.
+        */
+        if (channelId < drvObject->gblCfgParams.numDmaChannels)
             {
-            result = EDMA3_DRV_disableTransfer(hEdma, channelId,
-                edma3DrvChBoundRes[drvObject->phyCtrllerInstId][channelId].trigMode);
+            /* DMA channel */
+            channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
+            channelObj.resId = channelId;
             }
-
-        if (result == EDMA3_DRV_SOK)
+        else
             {
-            /*
-            * Unregister the TCC Callback function and disable the interrupts.
-            */
-            if (channelId < drvObject->gblCfgParams.numDmaChannels)
-                {
-                /* DMA channel */
-                channelObj.type = EDMA3_RM_RES_DMA_CHANNEL;
-                channelObj.resId = channelId;
-                }
-            else
-                {
-                /* QDMA channel */
-                channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
-                channelObj.resId = channelId - EDMA3_DRV_QDMA_CH_MIN_VAL;
-                }
+            /* QDMA channel */
+            channelObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
+            channelObj.resId = channelId - edma3_qdma_ch_min_val[edma3Id];
+            }
 
-            result = EDMA3_RM_unregisterTccCb(drvInst->resMgrInstance,
-                        (EDMA3_RM_ResDesc *)&channelObj);
+        result = EDMA3_RM_unregisterTccCb(drvInst->resMgrInstance,
+                    (EDMA3_RM_ResDesc *)&channelObj);
+       }
 
-            if (result == EDMA3_RM_SOK)
-                {
-                edma3OsProtectEntry(EDMA3_OS_PROTECT_INTERRUPT, &intState);
+    if (result == EDMA3_RM_SOK)
+        {
+        edma3OsProtectEntry(edma3Id, EDMA3_OS_PROTECT_INTERRUPT, &intState);
 
-                if (channelId <= EDMA3_DRV_DMA_CH_MAX_VAL)
-                    {
-                    /* DMA channel */
+        if (channelId <= edma3_dma_ch_max_val [edma3Id])
+            {
+            /* DMA channel */
 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
-                    /* Remove the channel to Event Queue mapping */
-                    globalRegs->DMAQNUM[channelId >> 3u] &=
-                                    EDMA3_DRV_DMAQNUM_CLR_MASK(channelId);
+            /* Remove the channel to Event Queue mapping */
+            globalRegs->DMAQNUM[channelId >> 3u] &=
+                            EDMA3_DRV_DMAQNUM_CLR_MASK(channelId);
 #endif
-
-                    /**
-                     * If DMA channel to PaRAM Set mapping exists,
-                     * remove it too.
-                     */
-                    if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
-                        {
-                        globalRegs->DCHMAP[channelId] &=
-                                                EDMA3_RM_DCH_PARAM_CLR_MASK;
-                        }
-                    }
-                else
-                    {
-                    /* QDMA channel */
+            /**
+             * If DMA channel to PaRAM Set mapping exists,
+             * remove it too.
+             */
+            if (TRUE == drvObject->gblCfgParams.dmaChPaRAMMapExists)
+                {
+                globalRegs->DCHMAP[channelId] &=
+                                        EDMA3_RM_DCH_PARAM_CLR_MASK;
+                }
+            }
+        else
+            {
+            /* QDMA channel */
 #ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
-                    /* Remove the channel to Event Queue mapping */
-                    globalRegs->QDMAQNUM = (globalRegs->QDMAQNUM) &
-                        (EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-EDMA3_DRV_QDMA_CH_MIN_VAL));
+            /* Remove the channel to Event Queue mapping */
+            globalRegs->QDMAQNUM = (globalRegs->QDMAQNUM) &
+                (EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId-edma3_qdma_ch_min_val[edma3Id]));
 #endif
-
-                    /* Remove the channel to PARAM set mapping */
-                    /* Unmap PARAM Set Number for specified channelId */
-                    globalRegs->QCHMAP[channelId-EDMA3_DRV_QDMA_CH_MIN_VAL] &=
-                                                EDMA3_RM_QCH_PARAM_CLR_MASK;
-
-                    /* Reset the Trigger Word */
-                    globalRegs->QCHMAP[channelId-EDMA3_DRV_QDMA_CH_MIN_VAL] &=
-                                                EDMA3_RM_QCH_TRWORD_CLR_MASK;
-                    }
-
-                edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT, intState);
-                }
+            /* Remove the channel to PARAM set mapping */
+            /* Unmap PARAM Set Number for specified channelId */
+            globalRegs->QCHMAP[channelId-edma3_qdma_ch_min_val[edma3Id]] &=
+                                        EDMA3_RM_QCH_PARAM_CLR_MASK;
+
+            /* Reset the Trigger Word */
+            globalRegs->QCHMAP[channelId-edma3_qdma_ch_min_val[edma3Id]] &=
+                                        EDMA3_RM_QCH_TRWORD_CLR_MASK;
             }
+
+        edma3OsProtectExit(edma3Id,
+                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                       intState);
         }
 
     return result;
index 85afd6d6d3d2091753fb8d4b098dd9a8a6978825..25870e3b5c4f9d85299d57df8a6cd182b1d5d0b4 100644 (file)
@@ -1,47 +1,46 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**|                            ****                                          |**
-**|                            ****                                          |**
-**|                            ******o***                                    |**
-**|                      ********_///_****                                   |**
-**|                      ***** /_//_/ ****                                   |**
-**|                       ** ** (__/ ****                                    |**
-**|                           *********                                      |**
-**|                            ****                                          |**
-**|                            ***                                           |**
-**|                                                                          |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
-**|                        ALL RIGHTS RESERVED                               |**
-**|                                                                          |**
-**| Permission is hereby granted to licensees of Texas Instruments           |**
-**| Incorporated (TI) products to use this computer program for the sole     |**
-**| purpose of implementing a licensee product based on TI products.         |**
-**| No other rights to reproduce, use, or disseminate this computer          |**
-**| program, whether in part or in whole, are granted.                       |**
-**|                                                                          |**
-**| TI makes no representation or warranties with respect to the             |**
-**| performance of this computer program, and specifically disclaims         |**
-**| any responsibility for any damages, special or consequential,            |**
-**| connected with the use of this program.                                  |**
-**|                                                                          |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/**
-*      \file           edma3_drv_init.c
-*
-*   \brief      EDMA3 Driver Initialization Interface Implementation
-*   This file contains EDMA3 Driver APIs used to:
-*      a) Create/delete EDMA3 Driver Object
-*      b) Open/close EDMA3 Driver Instance.
-*      These APIs are required to initialize EDMA3 properly.
-*
-*      @author: PSP Team, TII
-*
+/*
+ * edma3_drv_init.c
+ *
+ * EDMA3 Driver Initialization Interface Implementation. This file contains
+ * EDMA3 Driver APIs used to:
+ * a) Create/delete EDMA3 Driver Object
+ * b) Open/close EDMA3 Driver Instance.
+ * These APIs are required to initialize EDMA3 properly.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
 */
 
-
-/* EDMa3 Driver Internal Header Files */
+/* EDMA3 Driver Internal Header Files */
 #include <ti/sdo/edma3/drv/src/edma3.h>
 /* Resource Manager Internal Header Files */
 #include <ti/sdo/edma3/rm/src/edma3resmgr.h>
@@ -93,8 +92,8 @@ extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
  */
 extern EDMA3_RM_Instance *ptrRMIArray;
 
-/** Local MemSet function */
-extern void edma3MemSet(void *dst, unsigned char data, unsigned int len);
+/** Local MemZero function */
+extern void edma3MemZero(void *dst, unsigned int len);
 /** Local MemCpy function */
 extern void edma3MemCpy(void *dst, const void *src, unsigned int len);
 
@@ -134,13 +133,13 @@ EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_
 /**
  * \brief Event Queue Number for DMA/QDMA Channels.
  *
- * If EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME is defined, then the queue 
- * number registers for DMA/QDMA channels will be programmed during init time 
- * only; the queue number registers will NOT be changed during run-time to 
- * avoid (potential) race conditions. The following arrays will be used to 
+ * If EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME is defined, then the queue
+ * number registers for DMA/QDMA channels will be programmed during init time
+ * only; the queue number registers will NOT be changed during run-time to
+ * avoid (potential) race conditions. The following arrays will be used to
  * program the DMA/QDMA queue number registers.
  *
- * User has to provide the array values depending on the resources' 
+ * User has to provide the array values depending on the resources'
  * availability and the system requirements.
  *
  */
@@ -157,7 +156,7 @@ EDMA3_DRV_DmaQdmaQueueNum edma3DmaQdmaQueueNumConfig = {
         0u, 1u, 0u, 1u, 0u, 1u, 0u, 1u,
         0u, 1u, 0u, 1u, 0u, 1u, 0u, 1u,
         },
-        
+
                {
                /* QDMA Channels 0-7 */
         0u, 1u, 0u, 1u, 0u, 1u, 0u, 1u,
@@ -247,7 +246,7 @@ EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
             {
             for (count = 0; count < EDMA3_MAX_EDMA3_INSTANCES; count++)
                 {
-                edma3MemSet((void *)&(drvObj[count]) , 0x00u,
+                edma3MemZero((void *)&(drvObj[count]),
                             sizeof(EDMA3_DRV_Object));
                 }
             drvInitDone = TRUE;
@@ -269,8 +268,7 @@ EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
                                         sizeof (EDMA3_DRV_GblConfigParams));
 
                 /* Reset the RM global info struct first */
-                edma3MemSet((void *)&(rmGblCfgParams) ,
-                                    0x00u,
+                edma3MemZero((void *)&(rmGblCfgParams) ,
                                     sizeof (EDMA3_RM_GblConfigParams));
 
                 /* Fill the RM global info struct with the DRV global info */
@@ -307,7 +305,7 @@ EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
                 /* Make all the Driver instances for this EDMA3 HW NULL */
                 for (count = 0; count < drvObj[phyCtrllerInstId].gblCfgParams.numRegions; count++)
                     {
-                    edma3MemSet((void *)&(drvInstance[phyCtrllerInstId][count]) , 0x00u,
+                    edma3MemZero((void *)&(drvInstance[phyCtrllerInstId][count]),
                                 sizeof(EDMA3_DRV_Instance));
                     }
 
@@ -319,7 +317,7 @@ EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
                     edma3DrvChBoundRes[phyCtrllerInstId][count].trigMode =
                                                 EDMA3_DRV_TRIG_MODE_NONE;
                     }
-               }
+                               }
 
 
 /* Initialize the Queue Number Registers, if required. */
@@ -333,27 +331,27 @@ EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
                                if (NULL != globalRegs)
                                        {
                        /* Initialize DMA Queue Num Registers */
-                       for (count = 0; 
-                                               count < drvObj[phyCtrllerInstId].gblCfgParams.numDmaChannels; 
+                       for (count = 0;
+                                               count < drvObj[phyCtrllerInstId].gblCfgParams.numDmaChannels;
                                                count++)
                            {
                         globalRegs->DMAQNUM[count >> 3u] &= EDMA3_DRV_DMAQNUM_CLR_MASK(count);
-                        globalRegs->DMAQNUM[count >> 3u] |= EDMA3_DRV_DMAQNUM_SET_MASK(count, 
+                        globalRegs->DMAQNUM[count >> 3u] |= EDMA3_DRV_DMAQNUM_SET_MASK(count,
                                                                                edma3DmaQdmaQueueNumConfig.dmaChannelQueueNum[count]);
                            }
 
                        /* Initialize QDMA Queue Num Registers */
-                       for (count = 0; 
-                                               count < drvObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels; 
+                       for (count = 0;
+                                               count < drvObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels;
                                                count++)
                            {
                         globalRegs->QDMAQNUM &= EDMA3_DRV_QDMAQNUM_CLR_MASK(count);
-                        globalRegs->QDMAQNUM |= EDMA3_DRV_QDMAQNUM_SET_MASK(count, 
+                        globalRegs->QDMAQNUM |= EDMA3_DRV_QDMAQNUM_SET_MASK(count,
                                                                                edma3DmaQdmaQueueNumConfig.qdmaChannelQueueNum[count]);
                            }
                                        }
                 }
-#endif                         
+#endif
             }
         }
 
@@ -434,7 +432,7 @@ EDMA3_DRV_Result EDMA3_DRV_delete(unsigned int phyCtrllerInstId,
                     drvObj[phyCtrllerInstId].state = EDMA3_DRV_DELETED;
 
                     /* Also, reset the Driver Object Global Config Info */
-                    edma3MemSet((void *)&(drvObj[phyCtrllerInstId].gblCfgParams) , 0x00u,
+                    edma3MemZero((void *)&(drvObj[phyCtrllerInstId].gblCfgParams),
                             sizeof(EDMA3_DRV_GblConfigParams));
                     }
                 }
@@ -596,14 +594,19 @@ EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId,
             else
                 {
                 drvObject->state = EDMA3_DRV_OPENED;
-                edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);
+                edma3OsProtectEntry (phyCtrllerInstId,
+                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       &intState);
                 drvObject->numOpens++;
-                edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
+                edma3OsProtectExit (phyCtrllerInstId,
+                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       intState);
                 }
             }
         }
 
-    *errorCode = result;
+       if (errorCode)
+               *errorCode = result;
     return (EDMA3_DRV_Handle)drvInstanceHandle;
     }
 
@@ -673,18 +676,22 @@ EDMA3_DRV_Result EDMA3_DRV_close(EDMA3_DRV_Handle hEdma,
                     /* Set the driver instance specific info null */
                     drvInst->resMgrInstance = NULL;
                     drvInst->pDrvObjectHandle = NULL;
-                    edma3MemSet((void *)&(drvInst->drvInstInitConfig), 0x00,
+                    edma3MemZero((void *)&(drvInst->drvInstInitConfig),
                                                 sizeof (EDMA3_DRV_InstanceInitConfig));
                     drvInst->shadowRegs = NULL;
 
-                    edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);
+                    edma3OsProtectEntry (drvObject->phyCtrllerInstId,
+                                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                                               &intState);
                     /* Decrease the Number of Opens */
                     --drvObject->numOpens;
                     if (NULL == drvObject->numOpens)
                         {
                         drvObject->state = EDMA3_DRV_CLOSED;
                         }
-                    edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
+                    edma3OsProtectExit (drvObject->phyCtrllerInstId,
+                                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                                               intState);
                     }
                 }
             }