added event mux base address as macro
authorPrasad Konnur <prasadkonnur@ti.com>
Fri, 19 Apr 2013 07:47:16 +0000 (13:17 +0530)
committerPrasad Konnur <prasadkonnur@ti.com>
Fri, 19 Apr 2013 07:47:16 +0000 (13:17 +0530)
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_int_reg.c

index e27b67b45951bb0b5c5434761222bd0ef73facf8..79348c3aa8547d599ab1d030a7964acf722aa789 100644 (file)
@@ -110,6 +110,8 @@ typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 \r
 #define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)\r
 #define EDMA3_NUM_TCC                     (64u)\r
+\r
+#define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)\r
 /*\r
  * Forward decleration\r
  */\r
index d05277b643febbc4d9f3fc834c0f820116255f71..cc1088be3c7e727ac24ca31a4cdaec824b9b8a2e 100644 (file)
@@ -419,7 +419,6 @@ unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
 #define DSP1_EDMA3_TC0_BASE_ADDR                    ((void *)(0x01D05000))\r
 #define DSP1_EDMA3_TC1_BASE_ADDR                    ((void *)(0x01D06000))\r
 \r
-#define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)\r
 /* Driver Object Initialization Configuration */\r
 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
 {\r
index 14c0e86b7abf798157aca5d9da163abdfd55c613..e8744410fa55f457e25f7c843e38d2e9b502dc9e 100644 (file)
@@ -103,6 +103,8 @@ typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 #define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)
 #define EDMA3_NUM_TCC                     (64u)
 
+#define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
+
 /*
  * Forward decleration
  */