PRSDK-415 Update global cfgparams for AM335x
authorSinthu Raja M <x0257345@ti.com>
Wed, 31 Jan 2018 16:38:16 +0000 (22:08 +0530)
committerPratap Reddy <x0257344@ti.com>
Wed, 21 Feb 2018 20:16:41 +0000 (01:46 +0530)
 Reused reserved PARAM set masking code removed previously.
 Updated Global cfgparams to allocate user request PARAM set.

packages/ti/sdo/edma3/drv/sample/src/platforms/sample_am335x_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_am335x_cfg.c
packages/ti/sdo/edma3/rm/src/edma3resmgr.c

index 8f6683c2ce80c9613937c0de4f478a847e1c9018..c4f85738064c35e46511b096e7e48846c6bdf5d1 100644 (file)
@@ -362,6 +362,18 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
      * \brief Mapping from each DMA channel to a Parameter RAM set,
      * if it exists, otherwise of no use.
      */
+#ifdef EDMA3_RES_USER_REQ
+        {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+        },
+#else
         {
         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
@@ -396,6 +408,7 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP,
         EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_PARAM_MAP
         },
+#endif
 
      /**
       * \brief Mapping from each DMA channel to a TCC. This specific
@@ -490,6 +503,16 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU
           {
             /* Resources owned by Region 1 */
              /* ownPaRAMSets */
+#ifdef EDMA3_RES_USER_REQ
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
+            /* 159  128     191  160     223  192     255  224 */
+            0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+#else
             /* 31     0     63    32     95    64     127   96 */
             {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
             /* 159  128     191  160     223  192     255  224 */
@@ -498,6 +521,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU
              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
             /* 415  384     447  416     479  448     511  480 */
              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+#endif
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
index a002f4281ffec707e34284af5337df0bab903779..11ae7cd0f5f7eb433dc7719df00eb173f0cc922d 100644 (file)
@@ -362,6 +362,18 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
      * \brief Mapping from each DMA channel to a Parameter RAM set,
      * if it exists, otherwise of no use.
      */
+#ifdef EDMA3_RES_USER_REQ
+        {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+        },
+#else
         {
         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
@@ -396,6 +408,7 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
         },
+#endif
 
      /**
       * \brief Mapping from each DMA channel to a TCC. This specific
@@ -489,6 +502,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM
           {
             /* Resources owned by Region 1 */
             /* ownPaRAMSets */
+#ifdef EDMA3_RES_USER_REQ
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
+            /* 159  128     191  160     223  192     255  224 */
+            0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+#else
             /* 31     0     63    32     95    64     127   96 */
             {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
             /* 159  128     191  160     223  192     255  224 */
@@ -497,6 +520,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM
              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
             /* 415  384     447  416     479  448     511  480 */
              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+#endif
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
index b54cddfcfbe293a0b3a964c07b0b44718ab1a01b..78c0cdce2e4f6014d2cf5e7b71a65ce597eacdf8 100755 (executable)
@@ -879,6 +879,18 @@ EDMA3_RM_Handle EDMA3_RM_open (uint32_t phyCtrllerInstId,
                             = rmInstance->initParam.rmInstInitConfig->ownTccs[resMgrIdx];
                         }
 
+                    /*
+                     * Mark the PaRAM Sets corresponding to DMA channels as RESERVED.
+                     * For e.g. on a platform where only 32 DMA channels exist,
+                     * mark the first 32 PaRAM Sets as reserved. These param sets
+                     * will not be returned in case user requests for ANY link
+                     * channel.
+                     */
+                    for (resMgrIdx = 0U; resMgrIdx < rmObj->gblCfgParams.numDmaChannels; ++resMgrIdx)
+                        {
+                        rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets[resMgrIdx/32U] |= ((uint32_t)1U<<(resMgrIdx%32U));
+                        }
+
                     /*
                     * If the EDMA RM instance is MASTER (ie. initParam->isMaster
                     * is TRUE), save the region ID.