Addition of M3 support for Centaurus
authorprasad <prasad.konnur@ti.com>
Fri, 14 Oct 2011 12:09:39 +0000 (17:39 +0530)
committerprasad <prasad.konnur@ti.com>
Fri, 14 Oct 2011 12:09:39 +0000 (17:39 +0530)
Added cfg files, makefiles and examples build using makefile

16 files changed:
examples/edma3_driver/evmTI814x_M3/makefile [new file with mode: 0644]
examples/edma3_driver/evmTI814x_M3/rtsc_config/AmmuCfg.cfg [new file with mode: 0644]
examples/edma3_driver/evmTI814x_M3/rtsc_config/edma3_drv_bios6_ti814x_m3video_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmTI814x_M3/rtsc_config/edma3_drv_bios6_ti814x_m3vpss_st_sample.cfg [new file with mode: 0644]
packages/component.mk
packages/makefile
packages/ti/sdo/edma3/drv/sample/makefile
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/sample/makefile
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3vpss_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3vpss_int_reg.c [new file with mode: 0644]

diff --git a/examples/edma3_driver/evmTI814x_M3/makefile b/examples/edma3_driver/evmTI814x_M3/makefile
new file mode 100644 (file)
index 0000000..ccbc85d
--- /dev/null
@@ -0,0 +1,37 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_arm_ti814x_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files 
+#  need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_m3vpss = edma3_lld_drv edma3_lld_rm
+COMP_LIST_m3video = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_m3vpss = rtsc_config/edma3_drv_bios6_ti816x_m3vpss_st_sample.cfg
+XDC_CFG_FILE_m3video = rtsc_config/edma3_drv_bios6_ti816x_m3video_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
+              qdma_link_test.c
+CFLAGS_LOCAL_COMMON = 
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example: 
+#   SRCS_<core/SoC/platform-name> = 
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk 
+#     and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evmTI814x_M3/rtsc_config/AmmuCfg.cfg b/examples/edma3_driver/evmTI814x_M3/rtsc_config/AmmuCfg.cfg
new file mode 100644 (file)
index 0000000..aea02b5
--- /dev/null
@@ -0,0 +1,224 @@
+/* 
+ * Copyright (c) 2009, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+/*
+ *  ======== DucatiAmmu.cfg ========
+ *
+ *  An example configuration script used by both the server and client
+ *  applications running on either Bios6 or Linux.
+ */
+function init()
+{
+var Program = xdc.useModule('xdc.cfg.Program');
+{
+  var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+
+
+  var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+  Cache.enableCache = true;
+  
+
+  /*********************** Small Pages *************************/
+  /* smallPages[0] & smallPages[1] are auto-programmed by h/w */
+  /* Overwrite smallPage[1] so that 16K is covered. H/w reset value configures
+   * only 4K */
+  AMMU.smallPages[0].pageEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[0].logicalAddress = 0x00000000;
+  AMMU.smallPages[0].translatedAddress = 0x55020000;
+  AMMU.smallPages[0].translationEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[0].size = AMMU.Small_16K;
+  AMMU.smallPages[0].volatileQualifier = AMMU.Volatile_FOLLOW;  
+  AMMU.smallPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+  
+  /* Overwrite smallPage[1] so that 16K is covered. H/w reset value configures
+   * only 4K */
+  AMMU.smallPages[1].pageEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[1].logicalAddress = 0x40000000;
+  AMMU.smallPages[1].translatedAddress = 0x55080000;
+  AMMU.smallPages[1].translationEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[1].size = AMMU.Small_16K;
+  AMMU.smallPages[1].volatileQualifier = AMMU.Volatile_FOLLOW;  
+
+/*
+  AMMU.smallPages[2].pageEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[2].logicalAddress = 0x00004000;
+  AMMU.smallPages[2].translatedAddress = 0x55024000;
+  AMMU.smallPages[2].translationEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[2].size = AMMU.Small_16K;
+  AMMU.smallPages[2].volatileQualifier = AMMU.Volatile_FOLLOW;  
+  AMMU.smallPages[2].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.smallPages[2].L1_posted = AMMU.PostedPolicy_POSTED;
+  
+  AMMU.smallPages[3].pageEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[3].logicalAddress = 0x00008000;
+  AMMU.smallPages[3].translatedAddress = 0x55028000;
+  AMMU.smallPages[3].translationEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[3].size = AMMU.Small_16K;
+  AMMU.smallPages[3].volatileQualifier = AMMU.Volatile_FOLLOW;  
+  AMMU.smallPages[3].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.smallPages[3].L1_posted = AMMU.PostedPolicy_POSTED;
+  
+  AMMU.smallPages[4].pageEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[4].logicalAddress = 0x0000C000;
+  AMMU.smallPages[4].translatedAddress = 0x5502C000;
+  AMMU.smallPages[4].translationEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[4].size = AMMU.Small_16K;
+  AMMU.smallPages[4].volatileQualifier = AMMU.Volatile_FOLLOW;  
+  AMMU.smallPages[4].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.smallPages[4].L1_posted = AMMU.PostedPolicy_POSTED;
+
+  AMMU.smallPages[5].pageEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[5].logicalAddress = 0x00010000;
+  AMMU.smallPages[5].translatedAddress = 0x55030000;
+  AMMU.smallPages[5].translationEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[5].size = AMMU.Small_16K;
+  AMMU.smallPages[5].volatileQualifier = AMMU.Volatile_FOLLOW;  
+  AMMU.smallPages[5].endianism = AMMU.Endianism_BIG;    
+  AMMU.smallPages[5].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.smallPages[5].L1_posted = AMMU.PostedPolicy_POSTED;
+
+  AMMU.smallPages[6].pageEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[6].logicalAddress = 0x00014000;
+  AMMU.smallPages[6].translatedAddress = 0x55034000;
+  AMMU.smallPages[6].translationEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[6].size = AMMU.Small_16K;
+  AMMU.smallPages[6].volatileQualifier = AMMU.Volatile_FOLLOW;  
+  AMMU.smallPages[6].endianism = AMMU.Endianism_BIG;    
+  AMMU.smallPages[6].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.smallPages[6].L1_posted = AMMU.PostedPolicy_POSTED;
+
+  AMMU.smallPages[7].pageEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[7].logicalAddress = 0x00018000;
+  AMMU.smallPages[7].translatedAddress = 0x55038000;
+  AMMU.smallPages[7].translationEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[7].size = AMMU.Small_16K;
+  AMMU.smallPages[7].volatileQualifier = AMMU.Volatile_FOLLOW;  
+  AMMU.smallPages[7].endianism = AMMU.Endianism_BIG;    
+  AMMU.smallPages[7].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.smallPages[7].L1_posted = AMMU.PostedPolicy_POSTED;
+
+  AMMU.smallPages[8].pageEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[8].logicalAddress = 0x0001C000;
+  AMMU.smallPages[8].translatedAddress = 0x5503C000;
+  AMMU.smallPages[8].translationEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[8].size = AMMU.Small_16K;
+  AMMU.smallPages[8].volatileQualifier = AMMU.Volatile_FOLLOW;  
+  AMMU.smallPages[8].endianism = AMMU.Endianism_BIG;    
+  AMMU.smallPages[8].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.smallPages[8].L1_posted = AMMU.PostedPolicy_POSTED;
+  
+  AMMU.smallPages[9].pageEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[9].logicalAddress = 0x00020000;
+  AMMU.smallPages[9].translatedAddress = 0x55040000;
+  AMMU.smallPages[9].translationEnabled = AMMU.Enable_YES;
+  AMMU.smallPages[9].size = AMMU.Small_16K;
+  AMMU.smallPages[9].volatileQualifier = AMMU.Volatile_FOLLOW;  
+  AMMU.smallPages[9].endianism = AMMU.Endianism_BIG;    
+  AMMU.smallPages[9].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.smallPages[9].L1_posted = AMMU.PostedPolicy_POSTED;
+*/
+  
+  /*********************** Medium Pages *************************/
+  /* L2 space is mapped to virtual address 0 */
+  /* config medium page[0] to map 256K VA 0x00000000 to PA 0x55020000 - L2 SRAM */
+  /* Make it L1 cacheable */
+  AMMU.mediumPages[0].pageEnabled = AMMU.Enable_YES;
+  AMMU.mediumPages[0].logicalAddress = 0x00300000;
+  AMMU.mediumPages[0].translatedAddress = 0x40300000;
+  AMMU.mediumPages[0].translationEnabled = AMMU.Enable_YES;
+  AMMU.mediumPages[0].size = AMMU.Medium_256K;
+  AMMU.mediumPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+  AMMU.mediumPages[0].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+  AMMU.mediumPages[0].L1_allocate    = AMMU.AllocatePolicy_ALLOCATE;
+  AMMU.mediumPages[0].L1_posted = AMMU.PostedPolicy_POSTED;
+
+  
+  AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
+  AMMU.mediumPages[1].logicalAddress = 0x00400000;
+  AMMU.mediumPages[1].translatedAddress = 0x40400000;
+  AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
+  AMMU.mediumPages[1].size = AMMU.Medium_256K;
+  AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+  AMMU.mediumPages[1].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+  AMMU.mediumPages[1].L1_allocate    = AMMU.AllocatePolicy_ALLOCATE;
+  AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_POSTED;
+
+
+  /*********************** Large Pages *************************/
+  /* Instruction Code: Large page  (512M); cacheable */
+  AMMU.largePages[0].pageEnabled = AMMU.Enable_YES;
+  AMMU.largePages[0].logicalAddress = 0x60000000;
+  AMMU.largePages[0].translationEnabled = AMMU.Enable_NO;
+  AMMU.largePages[0].size = AMMU.Large_512M;
+  AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_NON_POSTED;
+  AMMU.largePages[0].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.largePages[0].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+
+
+  /* config large page[0] to map 512MB VA 0x40000000 to Config space */
+  AMMU.largePages[1].pageEnabled = AMMU.Enable_YES;
+  AMMU.largePages[1].logicalAddress = 0x40000000;
+  AMMU.largePages[1].translationEnabled = AMMU.Enable_NO;
+  AMMU.largePages[1].size = AMMU.Large_512M;
+  AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
+  AMMU.largePages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.largePages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+
+
+  /* V_M3/D_M3 code and data regions */
+  /* config large page[1] to map 512MB VA 0x80000000 to DDR 0x80000000  - Non cached */
+  AMMU.largePages[2].pageEnabled = AMMU.Enable_YES;
+  AMMU.largePages[2].logicalAddress = 0x80000000;
+  AMMU.largePages[2].translationEnabled = AMMU.Enable_NO;
+  AMMU.largePages[2].size = AMMU.Large_512M;
+  AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+  AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_POSTED;
+  AMMU.largePages[2].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.largePages[2].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+
+  
+  AMMU.largePages[3].pageEnabled = AMMU.Enable_YES;
+  AMMU.largePages[3].logicalAddress = 0xA0000000;
+  AMMU.largePages[3].translationEnabled = AMMU.Enable_NO;
+  AMMU.largePages[3].size = AMMU.Large_512M;
+  AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.largePages[3].L1_posted = AMMU.PostedPolicy_POSTED;
+  AMMU.largePages[3].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+  AMMU.largePages[3].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+
+   var GateDualCore = xdc.useModule ('ti.sysbios.family.arm.ducati.GateDualCore');
+   GateDualCore.initGates = true;
+}
+}
\ No newline at end of file
diff --git a/examples/edma3_driver/evmTI814x_M3/rtsc_config/edma3_drv_bios6_ti814x_m3video_st_sample.cfg b/examples/edma3_driver/evmTI814x_M3/rtsc_config/edma3_drv_bios6_ti814x_m3video_st_sample.cfg
new file mode 100644 (file)
index 0000000..3a76b01
--- /dev/null
@@ -0,0 +1,41 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
+var Startup   = xdc.useModule ("xdc.runtime.Startup");
+var System    = xdc.useModule ("xdc.runtime.System");
+var Log       = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
+var Error = xdc.useModule('xdc.runtime.Error');
+var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+var Program     = xdc.useModule("xdc.cfg.Program");
+
+
+/* ISR/SWI stack        */
+Program.stack           = 0x4000;
+
+/* Heap used when creating semaphore's, TSK's or malloc() ... */
+Program.heap            = 0x15000;
+
+/* enable print of exception handing info */
+HwiM3.enableException = true;
+
+/* DSP/BIOS expects this to set to 1 */
+var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.id = 0;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+/* MMU/Cache related configurations                                           */
+
+var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+var Mmu    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+var AmmuCfg = xdc.loadCapsule("AmmuCfg.cfg");
+AmmuCfg.init();
+
+Program.sectMap[".my_sect_ddr"] = "DDR3_RAM";
+
+/* Enable the cache                                                           */
+Cache1.enableCache = true;
diff --git a/examples/edma3_driver/evmTI814x_M3/rtsc_config/edma3_drv_bios6_ti814x_m3vpss_st_sample.cfg b/examples/edma3_driver/evmTI814x_M3/rtsc_config/edma3_drv_bios6_ti814x_m3vpss_st_sample.cfg
new file mode 100644 (file)
index 0000000..fa2a47d
--- /dev/null
@@ -0,0 +1,41 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
+var Startup   = xdc.useModule ("xdc.runtime.Startup");
+var System    = xdc.useModule ("xdc.runtime.System");
+var Log       = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
+var Error = xdc.useModule('xdc.runtime.Error');
+var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+var Program     = xdc.useModule("xdc.cfg.Program");
+
+
+/* ISR/SWI stack        */
+Program.stack           = 0x4000;
+
+/* Heap used when creating semaphore's, TSK's or malloc() ... */
+Program.heap            = 0x15000;
+
+/* enable print of exception handing info */
+HwiM3.enableException = true;
+
+/* DSP/BIOS expects this to set to 1 */
+var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.id = 1;
+
+/* USE EDMA3 Sample App */
+xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+/* MMU/Cache related configurations                                           */
+
+var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+var Mmu    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+var AmmuCfg = xdc.loadCapsule("AmmuCfg.cfg");
+AmmuCfg.init();
+
+Program.sectMap[".my_sect_ddr"] = "DDR3_M3";
+
+/* Enable the cache                                                           */
+Cache1.enableCache = true;
index 96275fb5f0f780dd35f5b8658ff400ca8b101cad..8bb088fea219763482ec7055f5a00e90eb39412a 100755 (executable)
@@ -174,6 +174,9 @@ edma3_drv_ti814x-evm_674_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_t
 edma3_drv_ti814x-evm_a8_example_EXAMPLES_RELPATH = examples/edma3_driver/evmTI814x_ARM
 edma3_drv_ti814x-evm_a8_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_ti814x-evm_a8_example_EXAMPLES_RELPATH)
 
+edma3_drv_ti814x-evm_m3_example_EXAMPLES_RELPATH = examples/edma3_driver/evmTI814x_M3
+edma3_drv_ti814x-evm_m3_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_ti814x-evm_m3_example_EXAMPLES_RELPATH)
+
 edma3_drv_ti816x-evm_674_example_EXAMPLES_RELPATH = examples/edma3_driver/evmTI816x
 edma3_drv_ti816x-evm_674_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_ti816x-evm_674_example_EXAMPLES_RELPATH)
 
index 97f18ba276b63358c61b181ea058f1ee2c24b0e9..8ef27044707b0005cd92fe6333479d7b8e2c3c47 100755 (executable)
@@ -293,6 +293,93 @@ edma3_lld_ti814x-evm_a8_libs_rmsample_clean:
        $(ECHO) \# Cleaning ti814x-evm:rel:edma3_lld_rm_sample
        $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=ti814x-evm CORE=a8host PROFILE_a8host=release
 
+#=======================================================================================================================================
+#To Build libs For Platform ti814x-evm Target m3
+edma3_lld_ti814x-evm_m3_libs: edma3_lld_ti814x-evm_m3_libs_rm edma3_lld_ti814x-evm_m3_libs_drvsample edma3_lld_ti814x-evm_m3_libs_rmsample
+edma3_lld_ti814x-evm_m3_libs_drv:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making m3:debug:edma3_lld_drv 
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+       $(ECHO) \# Making m3:release:edma3_lld_drv 
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release
+       $(ECHO) \# Making m3:debug:edma3_lld_drv 
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug
+       $(ECHO) \# Making m3:release:edma3_lld_drv 
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
+endif
+edma3_lld_ti814x-evm_m3_libs_rm:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making ti814x-evm:debug:edma3_lld_rm 
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+       $(ECHO) \# Making ti814x-evm:rel:edma3_lld_rm 
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release
+       $(ECHO) \# Making ti814x-evm:debug:edma3_lld_rm 
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug
+       $(ECHO) \# Making ti814x-evm:rel:edma3_lld_rm 
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
+endif
+edma3_lld_ti814x-evm_m3_libs_drvsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making ti814x-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+       $(ECHO) \# Making ti814x-evm:rel:edma3_lld_drv_sample   
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release
+       $(ECHO) \# Making ti814x-evm:rel:edma3_lld_drv_sample 
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
+       $(ECHO) \# Making ti814x-evm:debug:edma3_lld_drv_sample 
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug
+endif
+edma3_lld_ti814x-evm_m3_libs_rmsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making ti814x-evm:debug:edma3_lld_rm_sample 
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug
+       $(ECHO) \# Making ti814x-evm:rel:edma3_lld_rm_sample 
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release 
+       $(ECHO) \# Making ti814x-evm:debug:edma3_lld_rm_sample 
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+       $(ECHO) \# Making ti814x-evm:rel:edma3_lld_rm_sample 
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release
+endif
+
+#To Clean libs For Platform ti814x-evm Target m3
+edma3_lld_ti814x-evm_m3_libs_clean: edma3_lld_ti814x-evm_m3_libs_drv_clean edma3_lld_ti814x-evm_m3_libs_rm_clean edma3_lld_ti814x-evm_m3_libs_drvsample_clean edma3_lld_ti814x-evm_m3_libs_rmsample_clean
+edma3_lld_ti814x-evm_m3_libs_drv_clean:
+       $(ECHO) \# Cleaning m3:debug:edma3_lld_drv 
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+       $(ECHO) \# Cleaning m3:release:edma3_lld_drv 
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release
+       $(ECHO) \# Cleaning m3:debug:edma3_lld_drv 
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug
+       $(ECHO) \# Cleaning m3:release:edma3_lld_drv 
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
+edma3_lld_ti814x-evm_m3_libs_rm_clean:
+       $(ECHO) \# Cleaning ti814x-evm:debug:edma3_lld_rm 
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+       $(ECHO) \# Cleaning ti814x-evm:rel:edma3_lld_rm 
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release
+       $(ECHO) \# Cleaning ti814x-evm:debug:edma3_lld_rm 
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug
+       $(ECHO) \# Cleaning ti814x-evm:rel:edma3_lld_rm 
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
+edma3_lld_ti814x-evm_m3_libs_drvsample_clean:
+       $(ECHO) \# Cleaning ti814x-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+       $(ECHO) \# Cleaning ti814x-evm:rel:edma3_lld_drv_sample         
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release
+       $(ECHO) \# Cleaning ti814x-evm:rel:edma3_lld_drv_sample 
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
+       $(ECHO) \# Cleaning ti814x-evm:debug:edma3_lld_drv_sample 
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug
+edma3_lld_ti814x-evm_m3_libs_rmsample_clean:
+       $(ECHO) \# Cleaning ti814x-evm:debug:edma3_lld_rm_sample 
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug
+       $(ECHO) \# Cleaning ti814x-evm:rel:edma3_lld_rm_sample 
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release   
+       $(ECHO) \# Cleaning ti814x-evm:debug:edma3_lld_rm_sample 
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+       $(ECHO) \# Cleaning ti814x-evm:rel:edma3_lld_rm_sample 
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release
+
 #=======================================================================================================================================
 #To Build libs For Platform c6472-evm Target 64p
 edma3_lld_c6472-evm_64p_libs: edma3_lld_c6472-evm_64p_libs_drv edma3_lld_c6472-evm_64p_libs_rm edma3_lld_c6472-evm_64p_libs_drvsample edma3_lld_c6472-evm_64p_libs_rmsample
@@ -1267,6 +1354,29 @@ ifeq ($(FORMAT),ELF)
        $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=ti816x-evm CORE=m3vpss PROFILE_m3vpss=release
 endif
 
+edma3_drv_ti814x-evm_m3_example:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Configuring XDC packages for $@:m3:debug 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug   
+
+       $(ECHO) \# Configuring XDC packages for $@:m3:release 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
+       $(ECHO) \# Making example $@:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
+
+       $(ECHO) \# Configuring XDC packages for $@:m3:debug 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+
+       $(ECHO) \# Configuring XDC packages for $@:m3:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release     
+       $(ECHO) \# Making example $@:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release
+endif
+
 #=======================================================================================================================================
 #
 # Rule to clean all examples
@@ -1349,6 +1459,18 @@ ifeq ($(FORMAT),ELF)
        $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=ti814x-evm CORE=a8host PROFILE_a8host=release
 endif
 
+edma3_drv_ti814x-evm_m3_example_clean:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Cleaning example $@:debug
+       $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=debug
+       $(ECHO) \# Cleaning example $@:release
+       $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=ti814x-evm CORE=m3vpss PROFILE_m3vpss=release
+       $(ECHO) \# Cleaning example $@:debug
+       $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=debug
+       $(ECHO) \# Cleaning example $@:release
+       $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
+endif
+
 edma3_drv_ti816x-evm_m3_example_clean:
 ifeq ($(FORMAT),ELF)
        $(ECHO) \# Cleaning example $@:debug
index 9844fe42472161496911be38d219195f1a8ded69..84b5ddc5ec5fcd7a2ad9f06f186bf7f3d3a5be96 100755 (executable)
@@ -35,15 +35,19 @@ SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_int_reg.c
 SRCS_ti816x-sim = sample_ti816x_cfg.c sample_ti816x_int_reg.c
 else
 SRCS_omapl138-evm = sample_omapl138_arm_cfg.c sample_omapl138_arm_int_reg.c
+endif
+ifeq ($(CORE),a8host)
 SRCS_ti814x-evm = sample_ti814x_arm_cfg.c sample_ti814x_arm_int_reg.c
 endif
 ifeq ($(CORE),m3video)
 SRCS_ti816x-evm = sample_ti816x_m3video_cfg.c sample_ti816x_m3video_int_reg.c
 SRCS_ti816x-sim = sample_ti816x_m3video_cfg.c sample_ti816x_m3video_int_reg.c
+SRCS_ti814x-evm = sample_ti814x_m3video_cfg.c sample_ti814x_m3video_int_reg.c
 endif
 ifeq ($(CORE),m3vpss)
 SRCS_ti816x-evm = sample_ti816x_m3vpss_cfg.c sample_ti816x_m3vpss_int_reg.c
 SRCS_ti816x-sim = sample_ti816x_m3vpss_cfg.c sample_ti816x_m3vpss_int_reg.c
+SRCS_ti814x-evm = sample_ti814x_m3vpss_cfg.c sample_ti814x_m3vpss_int_reg.c
 endif
 SRCS_c6748-evm = sample_c6748_cfg.c sample_c6748_int_reg.c
 SRCS_da830-evm = sample_da830_cfg.c sample_da830_int_reg.c
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_cfg.c
new file mode 100644 (file)
index 0000000..f9f7d74
--- /dev/null
@@ -0,0 +1,824 @@
+/*
+ * sample_dm740_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES                    1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                                       1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+       {
+#if 0
+       volatile unsigned int *addr;
+       unsigned int core_no;
+
+    /* Identify the core number */
+    addr = (unsigned int *)(CGEM_REG_START+0x40000);
+    core_no = ((*addr) & 0x000F0000)>>16;
+
+       return core_no;
+#endif
+       return 4;
+       }
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+       {
+       (void) dspNum;
+
+       return 0;
+       }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET                             (512u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC                                  (64u)
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE                                (4u)
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC                                    (4u)
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT                    (62)
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT                              (46u)
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT                             (0u)
+#define EDMA3_TC1_ERROR_INT                             (0u)
+#define EDMA3_TC2_ERROR_INT                             (0u)
+#define EDMA3_TC3_ERROR_INT                             (0u)
+#define EDMA3_TC4_ERROR_INT                             (0u)
+#define EDMA3_TC5_ERROR_INT                             (0u)
+#define EDMA3_TC6_ERROR_INT                             (0u)
+#define EDMA3_TC7_ERROR_INT                             (0u)
+
+/**
+* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+* ECM events (SoC specific). These ECM events come
+* under ECM block XXX (handling those specific ECM events). Normally, block
+* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+* is mapped to a specific HWI_INT YYY in the tcf file.
+* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+* to transfer completion interrupt.
+* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+* to CC error interrupts.
+* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+* to TC error interrupts.
+*/
+#define EDMA3_HWI_INT_XFER_COMP                                                        (7u)
+#define EDMA3_HWI_INT_CC_ERR                                                   (11u)
+#define EDMA3_HWI_INT_TC_ERR                                                   (11u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                                                                         /* 31     0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                                                                         /* 63     32 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                                                       {
+                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+                                                       },
+                        };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
+                                {
+                                EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+                                EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+                                EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+                                EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+                                }
+                            };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+
+
+/* Driver Object Initialization Configuration */
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+       {
+           {
+           /** Total number of DMA Channels supported by the EDMA3 Controller */
+           64u,
+           /** Total number of QDMA Channels supported by the EDMA3 Controller */
+           8u,
+           /** Total number of TCCs supported by the EDMA3 Controller */
+           64u,
+           /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+           512u,
+           /** Total number of Event Queues in the EDMA3 Controller */
+           4u,
+           /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+           4u,
+           /** Number of Regions on this EDMA3 controller */
+           6u,
+
+           /**
+            * \brief Channel mapping existence
+            * A value of 0 (No channel mapping) implies that there is fixed association
+            * for a channel number to a parameter entry number or, in other words,
+            * PaRAM entry n corresponds to channel n.
+            */
+           1u,
+
+           /** Existence of memory protection feature */
+           1u,
+
+           /** Global Register Region of CC Registers */
+           (void *)0x49000000u,
+           /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x49800000u,
+               (void *)0x49900000u,
+               (void *)0x49A00000u,
+               (void *)0x49B00000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+           /** Interrupt no. for Transfer Completion */
+           EDMA3_CC_XFER_COMPLETION_INT,
+           /** Interrupt no. for CC Error */
+           EDMA3_CC_ERROR_INT,
+           /** Interrupt no. for TCs Error */
+               {
+               EDMA3_TC0_ERROR_INT,
+               EDMA3_TC1_ERROR_INT,
+               EDMA3_TC2_ERROR_INT,
+               EDMA3_TC3_ERROR_INT,
+               EDMA3_TC4_ERROR_INT,
+               EDMA3_TC5_ERROR_INT,
+               EDMA3_TC6_ERROR_INT,
+               EDMA3_TC7_ERROR_INT
+               },
+
+           /**
+            * \brief EDMA3 TC priority setting
+            *
+            * User can program the priority of the Event Queues
+            * at a system-wide level.  This means that the user can set the
+            * priority of an IO initiated by either of the TCs (Transfer Controllers)
+            * relative to IO initiated by the other bus masters on the
+            * device (ARM, DSP, USB, etc)
+            */
+               {
+               0u,
+               1u,
+               2u,
+               3u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+           /**
+            * \brief To Configure the Threshold level of number of events
+            * that can be queued up in the Event queues. EDMA3CC error register
+            * (CCERR) will indicate whether or not at any instant of time the
+            * number of events queued up in any of the event queues exceeds
+            * or equals the threshold/watermark value that is set
+            * in the queue watermark threshold register (QWMTHRA).
+            */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+           /**
+            * \brief To Configure the Default Burst Size (DBS) of TCs.
+            * An optimally-sized command is defined by the transfer controller
+            * default burst size (DBS). Different TCs can have different
+            * DBS values. It is defined in Bytes.
+            */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+           /**
+            * \brief Mapping from each DMA channel to a Parameter RAM set,
+            * if it exists, otherwise of no use.
+            */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            },
+
+            /**
+             * \brief Mapping from each DMA channel to a TCC. This specific
+             * TCC code will be returned when the transfer is completed
+             * on the mapped channel.
+             */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u,
+            36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u,
+            44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u,
+            52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u,
+            60u, 61u, 62u, 63u
+            },
+
+
+           /**
+            * \brief Mapping of DMA channels to Hardware Events from
+            * various peripherals, which use EDMA for data transfer.
+            * All channels need not be mapped, some can be free also.
+            */
+               {
+               0x00000000u,
+               0x00000000u
+               },
+               },
+       };
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+       {
+               /* EDMA3 INSTANCE# 0 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000001u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+
+               /* Resources reserved by Region 0 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                   {
+                       /* ownPaRAMSets */
+                       /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000002u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 1 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                   },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000004u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 2 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 3 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 4 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 5 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+           },
+       };
+
+/* Driver Instance Cross bar event to channel map Initialization Configuration */
+EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Event to channel map for region 0 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 1 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, 26, 27, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 2 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 3 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 4 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 5 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 6 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 7 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+    }
+};
+
+/* End of File */
+
+
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_int_reg.c
new file mode 100644 (file)
index 0000000..35459d6
--- /dev/null
@@ -0,0 +1,358 @@
+/*
+ * sample_dm740_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+// #include <stdio.h>
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/* External Instance Specific Configuration Structure */
+extern EDMA3_DRV_GblXbarToChanConfigParams 
+                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+
+typedef struct  {
+    volatile Uint32 DSP_INTMUX[21];
+    volatile Uint32 DUCATI_INTMUX[15];
+    volatile Uint32 TPCC_EVTMUX[16];
+    volatile Uint32 TIMER_EVTCAPT;
+    volatile Uint32 GPIO_MUX;
+} CSL_IntmuxRegs;
+
+typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+
+
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)
+#define EDMA3_NUM_TCC                     (64u)
+
+/*
+ * Forward decleration
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum);
+
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp;
+extern unsigned int hwIntCcErr;
+extern unsigned int hwIntTcErr;
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+//unsigned int gpp_num = 4;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+    Hwi_Params hwiParams; 
+    Error_Block      eb;
+
+    /* Initialize the Error Block                                             */
+    Error_init(&eb);
+        
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       //hwiParams.priority = hwIntXferComp;
+       //hwiParams.enableInt = TRUE;
+    
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
+                                       (&lisrEdma3ComplHandler0),
+                                       (const Hwi_Params *) (&hwiParams),
+                                       &eb);
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+       
+       #if 0
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntCcErr;
+       //hwiParams.enableInt = TRUE;
+       
+       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+                (&lisrEdma3CCErrHandler0),
+                (const Hwi_Params *) (&hwiParams),
+                &eb);
+
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        /* Initialize the HWI parameters with user specified values */
+        Hwi_Params_init(&hwiParams);
+        /* argument for the ISR */
+        hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+        hwiParams.priority = hwIntTcErr;
+               //hwiParams.enableInt = TRUE;
+        
+        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+                    (ptrEdma3TcIsrHandler[numTc]),
+                    (const Hwi_Params *) (&hwiParams),
+                    &eb);
+        if (TRUE == Error_check(&eb))
+        {
+            System_printf("HWI Create Failed\n",Error_getCode(&eb));
+        }
+        numTc++;
+       }
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(ccErrorInt[edma3Id]);
+    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
+    numTc = 0;
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+               
+       #endif
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    Hwi_delete(&hwiCCXferCompInt);
+    Hwi_delete(&hwiCCErrInt);
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_delete(&hwiTCErrInt[numTc]);
+        numTc++;
+       }
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**
+ * \brief   sampleMapXbarEvtToChan
+ *
+ * This function reads from the sample configuration structure which specifies 
+ * cross bar events mapped to DMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+    unsigned int xbarEvtNum = 0;
+    int          edmaChanNum = 0;
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum != NULL) &&
+               (edmaGblXbarConfig != NULL))
+               {
+               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
+               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
+               if (edmaChanNum != -1)
+                       {
+                       *chanNum = edmaChanNum;
+                       edma3Result = EDMA3_DRV_SOK;
+                       }
+               }
+       return (edma3Result);
+       }
+       
+
+/**
+ * \brief   sampleConfigScr
+ *
+ * This function configures control config registers for the cross bar events 
+ * mapped to the EDMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
+    unsigned int scrChanOffset = 0;
+    unsigned int scrRegOffset  = 0;
+    unsigned int xBarEvtNum    = 0;
+    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);
+
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum < EDMA3_NUM_TCC))
+               {
+               scrRegOffset = chanNum / 4;
+               scrChanOffset = chanNum - (scrRegOffset * 4);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+               
+               switch(scrChanOffset)
+                       {
+                       case 0:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
+                               break;
+                       case 1:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
+                               break;
+                       case 2:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
+                               break;
+                       case 3:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
+                               break;
+                       default:
+                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+                               break;
+                       }
+               }
+       else
+               {
+               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+               }
+       return edma3Result;
+       }
+
+
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
+                                   unsigned int edma3Id)
+    {
+    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
+    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
+                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
+    if (hEdma != NULL)
+        {
+        retVal = EDMA3_DRV_initXbarEventMap(hEdma, 
+                                                                       sampleXbarToChanConfig, 
+                                                                       &sampleMapXbarEvtToChan, 
+                                                                       &sampleConfigScr);
+        }
+    
+    return retVal;
+    }
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_cfg.c
new file mode 100644 (file)
index 0000000..12576f2
--- /dev/null
@@ -0,0 +1,824 @@
+/*
+ * sample_dm740_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES                    1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                                       1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+       {
+#if 0
+       volatile unsigned int *addr;
+       unsigned int core_no;
+
+    /* Identify the core number */
+    addr = (unsigned int *)(CGEM_REG_START+0x40000);
+    core_no = ((*addr) & 0x000F0000)>>16;
+
+       return core_no;
+#endif
+       return 5;
+       }
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+       {
+       (void) dspNum;
+
+       return 0;
+       }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET                             (512u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC                                  (64u)
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE                                (4u)
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC                                    (4u)
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT                    (63)
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT                              (46u)
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT                             (0u)
+#define EDMA3_TC1_ERROR_INT                             (0u)
+#define EDMA3_TC2_ERROR_INT                             (0u)
+#define EDMA3_TC3_ERROR_INT                             (0u)
+#define EDMA3_TC4_ERROR_INT                             (0u)
+#define EDMA3_TC5_ERROR_INT                             (0u)
+#define EDMA3_TC6_ERROR_INT                             (0u)
+#define EDMA3_TC7_ERROR_INT                             (0u)
+
+/**
+* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+* ECM events (SoC specific). These ECM events come
+* under ECM block XXX (handling those specific ECM events). Normally, block
+* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+* is mapped to a specific HWI_INT YYY in the tcf file.
+* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+* to transfer completion interrupt.
+* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+* to CC error interrupts.
+* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+* to TC error interrupts.
+*/
+#define EDMA3_HWI_INT_XFER_COMP                                                        (7u)
+#define EDMA3_HWI_INT_CC_ERR                                                   (11u)
+#define EDMA3_HWI_INT_TC_ERR                                                   (11u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                                                                         /* 31     0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                                                                         /* 63     32 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                                                       {
+                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+                                                       },
+                        };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
+                                {
+                                EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+                                EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+                                EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+                                EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+                                }
+                            };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+
+
+/* Driver Object Initialization Configuration */
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+       {
+           {
+           /** Total number of DMA Channels supported by the EDMA3 Controller */
+           64u,
+           /** Total number of QDMA Channels supported by the EDMA3 Controller */
+           8u,
+           /** Total number of TCCs supported by the EDMA3 Controller */
+           64u,
+           /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+           512u,
+           /** Total number of Event Queues in the EDMA3 Controller */
+           4u,
+           /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+           4u,
+           /** Number of Regions on this EDMA3 controller */
+           6u,
+
+           /**
+            * \brief Channel mapping existence
+            * A value of 0 (No channel mapping) implies that there is fixed association
+            * for a channel number to a parameter entry number or, in other words,
+            * PaRAM entry n corresponds to channel n.
+            */
+           1u,
+
+           /** Existence of memory protection feature */
+           1u,
+
+           /** Global Register Region of CC Registers */
+           (void *)0x49000000u,
+           /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x49800000u,
+               (void *)0x49900000u,
+               (void *)0x49A00000u,
+               (void *)0x49B00000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+           /** Interrupt no. for Transfer Completion */
+           EDMA3_CC_XFER_COMPLETION_INT,
+           /** Interrupt no. for CC Error */
+           EDMA3_CC_ERROR_INT,
+           /** Interrupt no. for TCs Error */
+               {
+               EDMA3_TC0_ERROR_INT,
+               EDMA3_TC1_ERROR_INT,
+               EDMA3_TC2_ERROR_INT,
+               EDMA3_TC3_ERROR_INT,
+               EDMA3_TC4_ERROR_INT,
+               EDMA3_TC5_ERROR_INT,
+               EDMA3_TC6_ERROR_INT,
+               EDMA3_TC7_ERROR_INT
+               },
+
+           /**
+            * \brief EDMA3 TC priority setting
+            *
+            * User can program the priority of the Event Queues
+            * at a system-wide level.  This means that the user can set the
+            * priority of an IO initiated by either of the TCs (Transfer Controllers)
+            * relative to IO initiated by the other bus masters on the
+            * device (ARM, DSP, USB, etc)
+            */
+               {
+               0u,
+               1u,
+               2u,
+               3u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+           /**
+            * \brief To Configure the Threshold level of number of events
+            * that can be queued up in the Event queues. EDMA3CC error register
+            * (CCERR) will indicate whether or not at any instant of time the
+            * number of events queued up in any of the event queues exceeds
+            * or equals the threshold/watermark value that is set
+            * in the queue watermark threshold register (QWMTHRA).
+            */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+           /**
+            * \brief To Configure the Default Burst Size (DBS) of TCs.
+            * An optimally-sized command is defined by the transfer controller
+            * default burst size (DBS). Different TCs can have different
+            * DBS values. It is defined in Bytes.
+            */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+           /**
+            * \brief Mapping from each DMA channel to a Parameter RAM set,
+            * if it exists, otherwise of no use.
+            */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            },
+
+            /**
+             * \brief Mapping from each DMA channel to a TCC. This specific
+             * TCC code will be returned when the transfer is completed
+             * on the mapped channel.
+             */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u,
+            36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u,
+            44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u,
+            52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u,
+            60u, 61u, 62u, 63u
+            },
+
+
+           /**
+            * \brief Mapping of DMA channels to Hardware Events from
+            * various peripherals, which use EDMA for data transfer.
+            * All channels need not be mapped, some can be free also.
+            */
+               {
+               0x00000000u,
+               0x00000000u
+               },
+               },
+       };
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+       {
+               /* EDMA3 INSTANCE# 0 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000001u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+
+               /* Resources reserved by Region 0 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                   {
+                       /* ownPaRAMSets */
+                       /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000002u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 1 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                   },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000004u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 2 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 3 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 4 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 5 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+           },
+       };
+
+/* Driver Instance Cross bar event to channel map Initialization Configuration */
+EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Event to channel map for region 0 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 1 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, 26, 27, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 2 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 3 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 4 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 5 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 6 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 7 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+    }
+};
+
+/* End of File */
+
+
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_int_reg.c
new file mode 100644 (file)
index 0000000..35459d6
--- /dev/null
@@ -0,0 +1,358 @@
+/*
+ * sample_dm740_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+// #include <stdio.h>
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/* External Instance Specific Configuration Structure */
+extern EDMA3_DRV_GblXbarToChanConfigParams 
+                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+
+typedef struct  {
+    volatile Uint32 DSP_INTMUX[21];
+    volatile Uint32 DUCATI_INTMUX[15];
+    volatile Uint32 TPCC_EVTMUX[16];
+    volatile Uint32 TIMER_EVTCAPT;
+    volatile Uint32 GPIO_MUX;
+} CSL_IntmuxRegs;
+
+typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+
+
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)
+#define EDMA3_NUM_TCC                     (64u)
+
+/*
+ * Forward decleration
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum);
+
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp;
+extern unsigned int hwIntCcErr;
+extern unsigned int hwIntTcErr;
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+//unsigned int gpp_num = 4;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+    Hwi_Params hwiParams; 
+    Error_Block      eb;
+
+    /* Initialize the Error Block                                             */
+    Error_init(&eb);
+        
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       //hwiParams.priority = hwIntXferComp;
+       //hwiParams.enableInt = TRUE;
+    
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
+                                       (&lisrEdma3ComplHandler0),
+                                       (const Hwi_Params *) (&hwiParams),
+                                       &eb);
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+       
+       #if 0
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntCcErr;
+       //hwiParams.enableInt = TRUE;
+       
+       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+                (&lisrEdma3CCErrHandler0),
+                (const Hwi_Params *) (&hwiParams),
+                &eb);
+
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        /* Initialize the HWI parameters with user specified values */
+        Hwi_Params_init(&hwiParams);
+        /* argument for the ISR */
+        hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+        hwiParams.priority = hwIntTcErr;
+               //hwiParams.enableInt = TRUE;
+        
+        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+                    (ptrEdma3TcIsrHandler[numTc]),
+                    (const Hwi_Params *) (&hwiParams),
+                    &eb);
+        if (TRUE == Error_check(&eb))
+        {
+            System_printf("HWI Create Failed\n",Error_getCode(&eb));
+        }
+        numTc++;
+       }
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(ccErrorInt[edma3Id]);
+    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
+    numTc = 0;
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+               
+       #endif
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    Hwi_delete(&hwiCCXferCompInt);
+    Hwi_delete(&hwiCCErrInt);
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_delete(&hwiTCErrInt[numTc]);
+        numTc++;
+       }
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**
+ * \brief   sampleMapXbarEvtToChan
+ *
+ * This function reads from the sample configuration structure which specifies 
+ * cross bar events mapped to DMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+    unsigned int xbarEvtNum = 0;
+    int          edmaChanNum = 0;
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum != NULL) &&
+               (edmaGblXbarConfig != NULL))
+               {
+               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
+               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
+               if (edmaChanNum != -1)
+                       {
+                       *chanNum = edmaChanNum;
+                       edma3Result = EDMA3_DRV_SOK;
+                       }
+               }
+       return (edma3Result);
+       }
+       
+
+/**
+ * \brief   sampleConfigScr
+ *
+ * This function configures control config registers for the cross bar events 
+ * mapped to the EDMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
+    unsigned int scrChanOffset = 0;
+    unsigned int scrRegOffset  = 0;
+    unsigned int xBarEvtNum    = 0;
+    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);
+
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum < EDMA3_NUM_TCC))
+               {
+               scrRegOffset = chanNum / 4;
+               scrChanOffset = chanNum - (scrRegOffset * 4);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+               
+               switch(scrChanOffset)
+                       {
+                       case 0:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
+                               break;
+                       case 1:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
+                               break;
+                       case 2:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
+                               break;
+                       case 3:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
+                               break;
+                       default:
+                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+                               break;
+                       }
+               }
+       else
+               {
+               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+               }
+       return edma3Result;
+       }
+
+
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
+                                   unsigned int edma3Id)
+    {
+    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
+    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
+                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
+    if (hEdma != NULL)
+        {
+        retVal = EDMA3_DRV_initXbarEventMap(hEdma, 
+                                                                       sampleXbarToChanConfig, 
+                                                                       &sampleMapXbarEvtToChan, 
+                                                                       &sampleConfigScr);
+        }
+    
+    return retVal;
+    }
index 762192bd31a8d30937b09d2a70b4ad047e478781..6f0bbddde3a6dd667e9ac4ee59166dd759c99c3d 100755 (executable)
@@ -34,15 +34,19 @@ SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_int_reg.c
 SRCS_ti816x-sim = sample_ti816x_cfg.c sample_ti816x_int_reg.c
 else
 SRCS_omapl138-evm = sample_omapl138_arm_cfg.c sample_omapl138_arm_int_reg.c
+endif
+ifeq ($(CORE),a8host)
 SRCS_ti814x-evm = sample_ti814x_arm_cfg.c sample_ti814x_arm_int_reg.c
 endif
 ifeq ($(CORE),m3video)
 SRCS_ti816x-evm = sample_ti816x_m3video_cfg.c sample_ti816x_m3video_int_reg.c
 SRCS_ti816x-sim = sample_ti816x_m3video_cfg.c sample_ti816x_m3video_int_reg.c
+SRCS_ti814x-evm = sample_ti814x_m3video_cfg.c sample_ti814x_m3video_int_reg.c
 endif
 ifeq ($(CORE),m3vpss)
 SRCS_ti816x-evm = sample_ti816x_m3vpss_cfg.c sample_ti816x_m3vpss_int_reg.c
 SRCS_ti816x-sim = sample_ti816x_m3vpss_cfg.c sample_ti816x_m3vpss_int_reg.c
+SRCS_ti814x-evm = sample_ti814x_m3video_cfg.c sample_ti814x_m3video_int_reg.c
 endif
 SRCS_c6748-evm = sample_c6748_cfg.c sample_c6748_int_reg.c
 SRCS_da830-evm = sample_da830_cfg.c sample_da830_int_reg.c
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_cfg.c
new file mode 100644 (file)
index 0000000..93754b2
--- /dev/null
@@ -0,0 +1,762 @@
+/*
+ * sample_dm740_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES                    1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                                       1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+       {
+#if 0
+       volatile unsigned int *addr;
+       unsigned int core_no;
+
+    /* Identify the core number */
+    addr = (unsigned int *)(CGEM_REG_START+0x40000);
+    core_no = ((*addr) & 0x000F0000)>>16;
+
+       return core_no;
+#endif
+       return 4;
+       }
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+       {
+       (void) dspNum;
+
+       return 0;
+       }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET                             (512u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC                                  (64u)
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE                                (4u)
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC                                    (4u)
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT                    (62)
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT                              (46u)
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT                             (0u)
+#define EDMA3_TC1_ERROR_INT                             (0u)
+#define EDMA3_TC2_ERROR_INT                             (0u)
+#define EDMA3_TC3_ERROR_INT                             (0u)
+#define EDMA3_TC4_ERROR_INT                             (0u)
+#define EDMA3_TC5_ERROR_INT                             (0u)
+#define EDMA3_TC6_ERROR_INT                             (0u)
+#define EDMA3_TC7_ERROR_INT                             (0u)
+
+/**
+* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+* ECM events (SoC specific). These ECM events come
+* under ECM block XXX (handling those specific ECM events). Normally, block
+* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+* is mapped to a specific HWI_INT YYY in the tcf file.
+* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+* to transfer completion interrupt.
+* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+* to CC error interrupts.
+* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+* to TC error interrupts.
+*/
+#define EDMA3_HWI_INT_XFER_COMP                                                        (7u)
+#define EDMA3_HWI_INT_CC_ERR                                                   (11u)
+#define EDMA3_HWI_INT_TC_ERR                                                   (11u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_rm_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_rm_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                                                                         /* 31     0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_rm_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_rm_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                                                                         /* 63     32 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                                                       {
+                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+                                                       },
+                        };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
+                                {
+                                EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+                                EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+                                EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+                                EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+                                }
+                            };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+       {
+           {
+           /** Total number of DMA Channels supported by the EDMA3 Controller */
+           64u,
+           /** Total number of QDMA Channels supported by the EDMA3 Controller */
+           8u,
+           /** Total number of TCCs supported by the EDMA3 Controller */
+           64u,
+           /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+           512u,
+           /** Total number of Event Queues in the EDMA3 Controller */
+           4u,
+           /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+           4u,
+           /** Number of Regions on this EDMA3 controller */
+           5u,
+
+           /**
+            * \brief Channel mapping existence
+            * A value of 0 (No channel mapping) implies that there is fixed association
+            * for a channel number to a parameter entry number or, in other words,
+            * PaRAM entry n corresponds to channel n.
+            */
+           1u,
+
+           /** Existence of memory protection feature */
+           1u,
+
+           /** Global Register Region of CC Registers */
+           (void *)0x49000000u,
+           /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x49800000u,
+               (void *)0x49900000u,
+               (void *)0x49A00000u,
+               (void *)0x49B00000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+           /** Interrupt no. for Transfer Completion */
+           EDMA3_CC_XFER_COMPLETION_INT,
+           /** Interrupt no. for CC Error */
+           EDMA3_CC_ERROR_INT,
+           /** Interrupt no. for TCs Error */
+               {
+               EDMA3_TC0_ERROR_INT,
+               EDMA3_TC1_ERROR_INT,
+               EDMA3_TC2_ERROR_INT,
+               EDMA3_TC3_ERROR_INT,
+               EDMA3_TC4_ERROR_INT,
+               EDMA3_TC5_ERROR_INT,
+               EDMA3_TC6_ERROR_INT,
+               EDMA3_TC7_ERROR_INT
+               },
+
+           /**
+            * \brief EDMA3 TC priority setting
+            *
+            * User can program the priority of the Event Queues
+            * at a system-wide level.  This means that the user can set the
+            * priority of an IO initiated by either of the TCs (Transfer Controllers)
+            * relative to IO initiated by the other bus masters on the
+            * device (ARM, DSP, USB, etc)
+            */
+               {
+               0u,
+               1u,
+               2u,
+               3u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+           /**
+            * \brief To Configure the Threshold level of number of events
+            * that can be queued up in the Event queues. EDMA3CC error register
+            * (CCERR) will indicate whether or not at any instant of time the
+            * number of events queued up in any of the event queues exceeds
+            * or equals the threshold/watermark value that is set
+            * in the queue watermark threshold register (QWMTHRA).
+            */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+           /**
+            * \brief To Configure the Default Burst Size (DBS) of TCs.
+            * An optimally-sized command is defined by the transfer controller
+            * default burst size (DBS). Different TCs can have different
+            * DBS values. It is defined in Bytes.
+            */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+           /**
+            * \brief Mapping from each DMA channel to a Parameter RAM set,
+            * if it exists, otherwise of no use.
+            */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            },
+
+            /**
+             * \brief Mapping from each DMA channel to a TCC. This specific
+             * TCC code will be returned when the transfer is completed
+             * on the mapped channel.
+             */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u,
+            36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u,
+            44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u,
+            52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u,
+            60u, 61u, 62u, 63u
+            },
+
+
+           /**
+            * \brief Mapping of DMA channels to Hardware Events from
+            * various peripherals, which use EDMA for data transfer.
+            * All channels need not be mapped, some can be free also.
+            */
+               {
+               0x00000000u,
+               0x00000000u
+               },
+               },
+       };
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+       {
+               /* EDMA3 INSTANCE# 0 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000001u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+
+               /* Resources reserved by Region 0 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                   {
+                       /* ownPaRAMSets */
+                       /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000002u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 1 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                   },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000004u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 2 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 3 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 4 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 5 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+           },
+       };
+
+
+
+/* End of File */
+
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_int_reg.c
new file mode 100644 (file)
index 0000000..79347dc
--- /dev/null
@@ -0,0 +1,204 @@
+/*
+ * sample_dm740_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+// #include <stdio.h>
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp;
+extern unsigned int hwIntCcErr;
+extern unsigned int hwIntTcErr;
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+//unsigned int gpp_num = 4;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+    Hwi_Params hwiParams; 
+    Error_Block      eb;
+
+    /* Initialize the Error Block                                             */
+    Error_init(&eb);
+        
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntXferComp;
+       //hwiParams.enableInt = TRUE;
+    
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
+                                       (&lisrEdma3ComplHandler0),
+                                       (const Hwi_Params *) (&hwiParams),
+                                       &eb);
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+       #if 0
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntCcErr;
+       //hwiParams.enableInt = TRUE;
+       
+       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+                (&lisrEdma3CCErrHandler0),
+                (const Hwi_Params *) (&hwiParams),
+                &eb);
+
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        /* Initialize the HWI parameters with user specified values */
+        Hwi_Params_init(&hwiParams);
+        /* argument for the ISR */
+        hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+        hwiParams.priority = hwIntTcErr;
+               //hwiParams.enableInt = TRUE;
+        
+        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+                    (ptrEdma3TcIsrHandler[numTc]),
+                    (const Hwi_Params *) (&hwiParams),
+                    &eb);
+        if (TRUE == Error_check(&eb))
+        {
+            System_printf("HWI Create Failed\n",Error_getCode(&eb));
+        }
+        numTc++;
+       }
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(ccErrorInt[edma3Id]);
+#if 0
+    Hwi_enableInterrupt(13);
+#endif
+    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
+    numTc = 0;
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+       #endif
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    Hwi_delete(&hwiCCXferCompInt);
+    Hwi_delete(&hwiCCErrInt);
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_delete(&hwiTCErrInt[numTc]);
+        numTc++;
+       }
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3vpss_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3vpss_cfg.c
new file mode 100644 (file)
index 0000000..a861bbf
--- /dev/null
@@ -0,0 +1,762 @@
+/*
+ * sample_dm740_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES                    1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                                       1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+       {
+#if 0
+       volatile unsigned int *addr;
+       unsigned int core_no;
+
+    /* Identify the core number */
+    addr = (unsigned int *)(CGEM_REG_START+0x40000);
+    core_no = ((*addr) & 0x000F0000)>>16;
+
+       return core_no;
+#endif
+       return 4;
+       }
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+       {
+       (void) dspNum;
+
+       return 0;
+       }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET                             (512u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC                                  (64u)
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE                                (4u)
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC                                    (4u)
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT                    (63)
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT                              (46u)
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT                             (0u)
+#define EDMA3_TC1_ERROR_INT                             (0u)
+#define EDMA3_TC2_ERROR_INT                             (0u)
+#define EDMA3_TC3_ERROR_INT                             (0u)
+#define EDMA3_TC4_ERROR_INT                             (0u)
+#define EDMA3_TC5_ERROR_INT                             (0u)
+#define EDMA3_TC6_ERROR_INT                             (0u)
+#define EDMA3_TC7_ERROR_INT                             (0u)
+
+/**
+* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+* ECM events (SoC specific). These ECM events come
+* under ECM block XXX (handling those specific ECM events). Normally, block
+* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+* is mapped to a specific HWI_INT YYY in the tcf file.
+* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+* to transfer completion interrupt.
+* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+* to CC error interrupts.
+* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+* to TC error interrupts.
+*/
+#define EDMA3_HWI_INT_XFER_COMP                                                        (7u)
+#define EDMA3_HWI_INT_CC_ERR                                                   (11u)
+#define EDMA3_HWI_INT_TC_ERR                                                   (11u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_rm_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_rm_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                                                                         /* 31     0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_rm_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_rm_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                                                                         /* 63     32 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                                                       {
+                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
+                                                       },
+                        };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
+                                {
+                                EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+                                EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+                                EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+                                EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+                                }
+                            };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+       {
+           {
+           /** Total number of DMA Channels supported by the EDMA3 Controller */
+           64u,
+           /** Total number of QDMA Channels supported by the EDMA3 Controller */
+           8u,
+           /** Total number of TCCs supported by the EDMA3 Controller */
+           64u,
+           /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+           512u,
+           /** Total number of Event Queues in the EDMA3 Controller */
+           4u,
+           /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+           4u,
+           /** Number of Regions on this EDMA3 controller */
+           5u,
+
+           /**
+            * \brief Channel mapping existence
+            * A value of 0 (No channel mapping) implies that there is fixed association
+            * for a channel number to a parameter entry number or, in other words,
+            * PaRAM entry n corresponds to channel n.
+            */
+           1u,
+
+           /** Existence of memory protection feature */
+           1u,
+
+           /** Global Register Region of CC Registers */
+           (void *)0x49000000u,
+           /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x49800000u,
+               (void *)0x49900000u,
+               (void *)0x49A00000u,
+               (void *)0x49B00000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+           /** Interrupt no. for Transfer Completion */
+           EDMA3_CC_XFER_COMPLETION_INT,
+           /** Interrupt no. for CC Error */
+           EDMA3_CC_ERROR_INT,
+           /** Interrupt no. for TCs Error */
+               {
+               EDMA3_TC0_ERROR_INT,
+               EDMA3_TC1_ERROR_INT,
+               EDMA3_TC2_ERROR_INT,
+               EDMA3_TC3_ERROR_INT,
+               EDMA3_TC4_ERROR_INT,
+               EDMA3_TC5_ERROR_INT,
+               EDMA3_TC6_ERROR_INT,
+               EDMA3_TC7_ERROR_INT
+               },
+
+           /**
+            * \brief EDMA3 TC priority setting
+            *
+            * User can program the priority of the Event Queues
+            * at a system-wide level.  This means that the user can set the
+            * priority of an IO initiated by either of the TCs (Transfer Controllers)
+            * relative to IO initiated by the other bus masters on the
+            * device (ARM, DSP, USB, etc)
+            */
+               {
+               0u,
+               1u,
+               2u,
+               3u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+           /**
+            * \brief To Configure the Threshold level of number of events
+            * that can be queued up in the Event queues. EDMA3CC error register
+            * (CCERR) will indicate whether or not at any instant of time the
+            * number of events queued up in any of the event queues exceeds
+            * or equals the threshold/watermark value that is set
+            * in the queue watermark threshold register (QWMTHRA).
+            */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+           /**
+            * \brief To Configure the Default Burst Size (DBS) of TCs.
+            * An optimally-sized command is defined by the transfer controller
+            * default burst size (DBS). Different TCs can have different
+            * DBS values. It is defined in Bytes.
+            */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+           /**
+            * \brief Mapping from each DMA channel to a Parameter RAM set,
+            * if it exists, otherwise of no use.
+            */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            },
+
+            /**
+             * \brief Mapping from each DMA channel to a TCC. This specific
+             * TCC code will be returned when the transfer is completed
+             * on the mapped channel.
+             */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u,
+            36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u,
+            44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u,
+            52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u,
+            60u, 61u, 62u, 63u
+            },
+
+
+           /**
+            * \brief Mapping of DMA channels to Hardware Events from
+            * various peripherals, which use EDMA for data transfer.
+            * All channels need not be mapped, some can be free also.
+            */
+               {
+               0x00000000u,
+               0x00000000u
+               },
+               },
+       };
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+       {
+               /* EDMA3 INSTANCE# 0 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000001u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+
+               /* Resources reserved by Region 0 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                   {
+                       /* ownPaRAMSets */
+                       /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000002u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 1 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                   },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000004u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 2 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+        /* 31    0    63     32 */
+        {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 3 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 4 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* ownDmaChannels */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* ownQdmaChannels */
+               /* 31     0 */
+               {0x00000008u},
+
+               /* ownTccs */
+               /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+               /* Resources reserved by Region 5 */
+               /* resvdPaRAMSets */
+               /* 31     0     63    32     95    64     127   96 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+               /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+               /* resvdDmaChannels */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+
+               /* resvdQdmaChannels */
+               /* 31     0 */
+               {0x00000000u},
+
+               /* resvdTccs */
+               /* 31     0     63    32 */
+               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+           },
+       };
+
+
+
+/* End of File */
+
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3vpss_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3vpss_int_reg.c
new file mode 100644 (file)
index 0000000..79347dc
--- /dev/null
@@ -0,0 +1,204 @@
+/*
+ * sample_dm740_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+// #include <stdio.h>
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp;
+extern unsigned int hwIntCcErr;
+extern unsigned int hwIntTcErr;
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+//unsigned int gpp_num = 4;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+    Hwi_Params hwiParams; 
+    Error_Block      eb;
+
+    /* Initialize the Error Block                                             */
+    Error_init(&eb);
+        
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntXferComp;
+       //hwiParams.enableInt = TRUE;
+    
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
+                                       (&lisrEdma3ComplHandler0),
+                                       (const Hwi_Params *) (&hwiParams),
+                                       &eb);
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+       #if 0
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntCcErr;
+       //hwiParams.enableInt = TRUE;
+       
+       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+                (&lisrEdma3CCErrHandler0),
+                (const Hwi_Params *) (&hwiParams),
+                &eb);
+
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        /* Initialize the HWI parameters with user specified values */
+        Hwi_Params_init(&hwiParams);
+        /* argument for the ISR */
+        hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+        hwiParams.priority = hwIntTcErr;
+               //hwiParams.enableInt = TRUE;
+        
+        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+                    (ptrEdma3TcIsrHandler[numTc]),
+                    (const Hwi_Params *) (&hwiParams),
+                    &eb);
+        if (TRUE == Error_check(&eb))
+        {
+            System_printf("HWI Create Failed\n",Error_getCode(&eb));
+        }
+        numTc++;
+       }
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(ccErrorInt[edma3Id]);
+#if 0
+    Hwi_enableInterrupt(13);
+#endif
+    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
+    numTc = 0;
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+       #endif
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    Hwi_delete(&hwiCCXferCompInt);
+    Hwi_delete(&hwiCCErrInt);
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_delete(&hwiTCErrInt[numTc]);
+        numTc++;
+       }
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+