Misra C fixes: TI-814x
authorSunil MS <x0190988@ti.com>
Wed, 15 Oct 2014 08:07:25 +0000 (13:37 +0530)
committerSunil MS <x0190988@ti.com>
Thu, 16 Oct 2014 05:04:16 +0000 (10:34 +0530)
MISRA.CVALUE.IMPL.CAST
MISRA.DECL.ARRAY_SIZE
MISRA.DEFINE.BADEXP
MISRA.FUNC.NOPROT.DEF
MISRA.INIT.BRACES
MISRA.LITERAL.UNSIGNED.SUFFIX
MISRA.TOKEN.CPCOM
MISRA.VAR.UNIQUE.STATIC

Change-Id: Ib867705ee9ca196f7c3acf0bb9130b70827dfefa
Signed-off-by: Sunil MS <x0190988@ti.com>
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_int_reg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_int_reg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_m3video_int_reg.c

index e49a4b622701c0461492f4123852719766a1a698..9807565b695fc03709c07196e22429d17deed09c 100755 (executable)
   */
 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 {
-                                                (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorInt[];
-extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
-extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern uint32_t hwIntXferComp[];
-extern uint32_t hwIntCcErr[];
-extern uint32_t hwIntTcErr[];
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
 
 extern uint32_t dsp_num;
 /* This variable has to be used as an extern */
@@ -83,7 +83,7 @@ Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
 
 /* External Instance Specific Configuration Structure */
 extern EDMA3_DRV_GblXbarToChanConfigParams 
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+                                                               sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
 
 typedef struct  {
     volatile Uint32 DSP_INTMUX[21];
@@ -130,6 +130,15 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
 
 void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
 
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
+                                   uint32_t edma3Id);
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (uint32_t edma3Id);
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (uint32_t edma3Id);
+
 /**  To Register the ISRs with the underlying OS, if required. */
 void registerEdma3Interrupts (uint32_t edma3Id)
     {
@@ -152,13 +161,13 @@ void registerEdma3Interrupts (uint32_t edma3Id)
     /* argument for the ISR */
     hwiParams.arg = edma3Id;
        /* set the priority ID     */
-       //hwiParams.priority = hwIntXferComp[edma3Id];
+       /* hwiParams.priority = hwIntXferComp[edma3Id]; */
     
     hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
                                        ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
                                        (const Hwi_Params *) (&hwiParams),
                                        &eb);
-    if (TRUE == Error_check(&eb))
+    if ((bool)TRUE == Error_check(&eb))
     {
         System_printf("HWI Create Failed\n",Error_getCode(&eb));
     }
@@ -175,7 +184,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
                 (const Hwi_Params *) (&hwiParams),
                 &eb);
 
-    if (TRUE == Error_check(&eb))
+    if ((bool)TRUE == Error_check(&eb))
     {
         System_printf("HWI Create Failed\n",Error_getCode(&eb));
     }
@@ -193,7 +202,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
                     (ptrEdma3TcIsrHandler[numTc]),
                     (const Hwi_Params *) (&hwiParams),
                     &eb);
-        if (TRUE == Error_check(&eb))
+        if ((bool)TRUE == Error_check(&eb))
         {
             System_printf("HWI Create Failed\n",Error_getCode(&eb));
         }
@@ -229,13 +238,13 @@ void registerEdma3Interrupts (uint32_t edma3Id)
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
-       static UInt32 cookie = 0;
+       static UInt32 cookiee = 0;
 #ifdef BUILD_CENTAURUS_A8
     uint32_t numTc = 0;
 #endif /* BUILD_CENTAURUS_A8 */
 
     /* Disabling the global interrupts */
-    cookie = Hwi_disable();
+    cookiee = Hwi_disable();
 
     Hwi_delete(&hwiCCXferCompInt);
 
@@ -249,7 +258,7 @@ void unregisterEdma3Interrupts (uint32_t edma3Id)
 #endif /* BUILD_CENTAURUS_A8 */
 
     /* Restore interrupts */
-    Hwi_restore(cookie);
+    Hwi_restore(cookiee);
     }
 
 /**
@@ -305,9 +314,9 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
                (chanNum < EDMA3_NUM_TCC))
                {
-               scrRegOffset = chanNum / 4;
-               scrChanOffset = chanNum - (scrRegOffset * 4);
-               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+               scrRegOffset = chanNum / 4U;
+               scrChanOffset = chanNum - (scrRegOffset * 4U);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1U;
                
                switch(scrChanOffset)
                        {
@@ -315,17 +324,17 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
                                break;
-                       case 1:
+                       case 1U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
                                break;
-                       case 2:
+                       case 2U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
                                break;
-                       case 3:
+                       case 3U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
@@ -361,5 +370,8 @@ EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
 
 void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
     {
+#ifdef EDMA3_DRV_DEBUG
+    /*  Added to fix Misra C error */
     printf("memory Protection error");
+#endif
     }
index 49a4471012ee7bc667e4b0085346cf12f41511f4..f88f5562812b463777c91c2950bbccb7f273bcc0 100755 (executable)
@@ -48,19 +48,26 @@ const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
 #define NUM_DSPS                    1U
 const uint32_t numDsps = NUM_DSPS;
 
+int8_t*  getGlobalAddr(int8_t* addr);
+
+uint16_t isGblConfigRequired(uint32_t dspNum);
+
+/* Determine the processor id by reading DNUM register. */
+uint16_t determineProcId(void);
+
 /* Determine the processor id by reading DNUM register. */
-uint16_t determineProcId()
+uint16_t determineProcId(void)
 {
 #ifdef BUILD_CENTAURUS_A8
-       return 0;
+       return 0U;
 #elif defined BUILD_CENTAURUS_DSP
-       return 1;
+       return 1U;
 #elif defined BUILD_CENTAURUS_M3VPSS
-       return 5;
+       return 5U;
 #elif defined BUILD_CENTAURUS_M3VIDEO
-       return 4;
+       return 4U;
 #else
-       return 1;
+       return 1U;
 #endif
 }
 
@@ -72,9 +79,9 @@ uint16_t isGblConfigRequired(uint32_t dspNum)
 {
     (void) dspNum;
 #ifdef BUILD_CENTAURUS_DSP
-       return 1;
+       return 1U;
 #else
-       return 0;
+       return 0U;
 #endif
 }
 
@@ -110,13 +117,13 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO            (62U)
 
 #ifdef BUILD_CENTAURUS_A8
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A8
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_A8)
 #elif defined BUILD_CENTAURUS_DSP
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_DSP)
 #elif defined BUILD_CENTAURUS_M3VIDEO
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO)
 #elif defined BUILD_CENTAURUS_M3VPSS
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_M3VPSS
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_M3VPSS)
 #else
 #define EDMA3_CC_XFER_COMPLETION_INT                    {0U}
 #endif
@@ -126,9 +133,9 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_CC_ERROR_INT_DSP                          (21U)
 
 #ifdef BUILD_CENTAURUS_A8
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A8
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_A8)
 #elif defined BUILD_CENTAURUS_DSP
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_DSP)
 #else
 #define EDMA3_CC_ERROR_INT                              (0U)
 #endif
@@ -144,15 +151,15 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_TC3_ERROR_INT_A8                          (115U)
 
 #ifdef BUILD_CENTAURUS_A8
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A8
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_A8
-#define EDMA3_TC2_ERROR_INT                             EDMA3_TC2_ERROR_INT_A8
-#define EDMA3_TC3_ERROR_INT                             EDMA3_TC3_ERROR_INT_A8
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_A8)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_A8)
+#define EDMA3_TC2_ERROR_INT                             (EDMA3_TC2_ERROR_INT_A8)
+#define EDMA3_TC3_ERROR_INT                             (EDMA3_TC3_ERROR_INT_A8)
 #elif defined BUILD_CENTAURUS_DSP
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_DSP
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_DSP
-#define EDMA3_TC2_ERROR_INT                             EDMA3_TC2_ERROR_INT_DSP
-#define EDMA3_TC3_ERROR_INT                             EDMA3_TC3_ERROR_INT_DSP
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_DSP)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_DSP)
+#define EDMA3_TC2_ERROR_INT                             (EDMA3_TC2_ERROR_INT_DSP)
+#define EDMA3_TC3_ERROR_INT                             (EDMA3_TC3_ERROR_INT_DSP)
 #else
 #define EDMA3_TC0_ERROR_INT                             (0U)
 #define EDMA3_TC1_ERROR_INT                             (0U)
@@ -286,7 +293,11 @@ uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
                                                         EDMA3_HWI_INT_TC0_ERR,
                                                         EDMA3_HWI_INT_TC1_ERR,
                                                         EDMA3_HWI_INT_TC2_ERR,
-                                                        EDMA3_HWI_INT_TC3_ERR
+                                                        EDMA3_HWI_INT_TC3_ERR,
+                                                        0,
+                                                        0,
+                                                        0,
+                                                        0
                                                      }
                                                };
 
index 14273a5757bf0fa40e67c448644169a1f9b05be2..7588d3d35868f1126f78e7721e3f8a39a619ee92 100755 (executable)
@@ -59,24 +59,24 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorInt[];
-extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
-extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern uint32_t hwIntXferComp[];
-extern uint32_t hwIntCcErr[];
-extern uint32_t hwIntTcErr[];
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
 
 extern uint32_t dsp_num;
 
 /* External Instance Specific Configuration Structure */
 extern EDMA3_DRV_GblXbarToChanConfigParams 
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+                                                               sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
 
 typedef struct  {
     volatile Uint32 DSP_INTMUX[21];
@@ -121,6 +121,14 @@ EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
 EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
                                   uint32_t chanNum);
 
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
+                                   uint32_t edma3Id);
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (uint32_t edma3Id);
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (uint32_t edma3Id);
 
 /**  To Register the ISRs with the underlying OS, if required. */
 void registerEdma3Interrupts (uint32_t edma3Id)
@@ -134,13 +142,13 @@ void registerEdma3Interrupts (uint32_t edma3Id)
     /* Enable the Xfer Completion Event Interrupt */
     EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
                                                (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
-                               edma3Id, 1);
+                               edma3Id, (Bool)1);
     EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
 
     /* Enable the CC Error Event Interrupt */
     EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
                                                (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
-                                               edma3Id, 1);
+                                               edma3Id, (Bool)1);
     EventCombiner_enableEvent(ccErrorInt[edma3Id]);
 
     /* Enable the TC Error Event Interrupt, according to the number of TCs. */
@@ -148,7 +156,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
            {
         EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
                             (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
-                            edma3Id, 1);
+                            edma3Id, (Bool)1);
         EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
         numTc++;
        }
@@ -175,11 +183,11 @@ void registerEdma3Interrupts (uint32_t edma3Id)
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
-       static UInt32 cookie = 0;
+       static UInt32 cookiee = 0;
     uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
-    cookie = Hwi_disable();
+    cookiee = Hwi_disable();
 
     /* Disable the Xfer Completion Event Interrupt */
        EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
@@ -195,7 +203,7 @@ void unregisterEdma3Interrupts (uint32_t edma3Id)
        }
 
     /* Restore interrupts */
-    Hwi_restore(cookie);
+    Hwi_restore(cookiee);
     }
 
 /**
@@ -251,9 +259,9 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
                (chanNum < EDMA3_NUM_TCC))
                {
-               scrRegOffset = chanNum / 4;
-               scrChanOffset = chanNum - (scrRegOffset * 4);
-               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+               scrRegOffset = chanNum / 4U;
+               scrChanOffset = chanNum - (scrRegOffset * 4U);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1U;
                
                switch(scrChanOffset)
                        {
@@ -261,17 +269,17 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
                                break;
-                       case 1:
+                       case 1U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
                                break;
-                       case 2:
+                       case 2U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
                                break;
-                       case 3:
+                       case 3U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
index 6ac8914b8182ed2182d374a280e5d46490ed3951..822fdd4a66b86ede214389e14c935f97cdacfc30 100644 (file)
@@ -48,8 +48,15 @@ const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
 #define NUM_DSPS                                       1U
 const uint32_t numDsps = NUM_DSPS;
 
+int8_t*  getGlobalAddr(int8_t* addr);
+
+uint16_t isGblConfigRequired(uint32_t dspNum);
+
+/* Determine the processor id by reading DNUM register. */
+uint16_t determineProcId(void);
+
 /* Determine the processor id by reading DNUM register. */
-uint16_t determineProcId()
+uint16_t determineProcId(void)
        {
 #if 0
        volatile uint32_t *addr;
@@ -61,7 +68,7 @@ uint16_t determineProcId()
 
        return core_no;
 #endif
-       return 4;
+       return 4U;
        }
 
 int8_t*  getGlobalAddr(int8_t* addr)
@@ -73,7 +80,7 @@ uint16_t isGblConfigRequired(uint32_t dspNum)
        {
        (void) dspNum;
 
-       return 0;
+       return 0U;
        }
 
 /* Semaphore handles */
index 0c0efcc7339752408e49e91a2d8646128d468d22..e7df212ea5183c31991f7804cbf228697f1e1a8e 100644 (file)
@@ -44,7 +44,7 @@
 
 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
 
-// #include <stdio.h>
+/* #include <stdio.h> */
 /**
   * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
   * (Not all TC error ISRs need to be registered, register only for the
@@ -62,10 +62,10 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorInt[];
-extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
-extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
@@ -77,17 +77,23 @@ extern uint32_t hwIntTcErr;
 
 extern uint32_t dsp_num;
 /* This variable has to be used as an extern */
-//uint32_t gpp_num = 4;
+/* uint32_t gpp_num = 4; */
 
 Hwi_Handle hwiCCXferCompInt;
 Hwi_Handle hwiCCErrInt;
 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
 
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (uint32_t edma3Id);
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (uint32_t edma3Id);
+
 /**  To Register the ISRs with the underlying OS, if required. */
 void registerEdma3Interrupts (uint32_t edma3Id)
     {
     static UInt32 cookie = 0;
-    //uint32_t numTc = 0;
+    /* uint32_t numTc = 0; */
     Hwi_Params hwiParams; 
     Error_Block      eb;
 
@@ -104,13 +110,13 @@ void registerEdma3Interrupts (uint32_t edma3Id)
     hwiParams.arg = edma3Id;
        /* set the priority ID     */
        hwiParams.priority = hwIntXferComp;
-       //hwiParams.enableInt = TRUE;
+       /* hwiParams.enableInt = TRUE; */
     
     hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
                                        (&lisrEdma3ComplHandler0),
                                        (const Hwi_Params *) (&hwiParams),
                                        &eb);
-    if (TRUE == Error_check(&eb))
+    if ((bool)TRUE == Error_check(&eb))
     {
         System_printf("HWI Create Failed\n",Error_getCode(&eb));
     }
@@ -122,14 +128,14 @@ void registerEdma3Interrupts (uint32_t edma3Id)
     hwiParams.arg = edma3Id;
        /* set the priority ID     */
        hwiParams.priority = hwIntCcErr;
-       //hwiParams.enableInt = TRUE;
+       /* hwiParams.enableInt = TRUE; */
        
        hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
                 (&lisrEdma3CCErrHandler0),
                 (const Hwi_Params *) (&hwiParams),
                 &eb);
 
-    if (TRUE == Error_check(&eb))
+    if ((bool)TRUE == Error_check(&eb))
     {
         System_printf("HWI Create Failed\n",Error_getCode(&eb));
     }
@@ -142,7 +148,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
         hwiParams.arg = edma3Id;
        /* set the priority ID     */
         hwiParams.priority = hwIntTcErr;
-               //hwiParams.enableInt = TRUE;
+               /* hwiParams.enableInt = TRUE; */
         
         hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
                     (ptrEdma3TcIsrHandler[numTc]),
@@ -185,11 +191,11 @@ void registerEdma3Interrupts (uint32_t edma3Id)
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
-       static UInt32 cookie = 0;
+       static UInt32 cookiee = 0;
     uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
-    cookie = Hwi_disable();
+    cookiee = Hwi_disable();
 
     Hwi_delete(&hwiCCXferCompInt);
     Hwi_delete(&hwiCCErrInt);
@@ -199,6 +205,6 @@ void unregisterEdma3Interrupts (uint32_t edma3Id)
         numTc++;
        }
     /* Restore interrupts */
-    Hwi_restore(cookie);
+    Hwi_restore(cookiee);
     }