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Misra C Fix:DRA72X Files
authorSunil MS <x0190988@ti.com>
Wed, 15 Oct 2014 11:06:07 +0000 (16:36 +0530)
committerSunil MS <x0190988@ti.com>
Mon, 20 Oct 2014 14:14:16 +0000 (19:44 +0530)
MISRA.BUILTIN_NUMERIC
MISRA.LITERAL.UNSIGNED.SUFFIX

Change-Id: I328788af9a7fb863305e627926713fac522182ca
Signed-off-by: Sunil MS <x0190988@ti.com>
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c patch | blob | history
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c patch | blob | history
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c patch | blob | history
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_arm_int_reg.c patch | blob | history
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c patch | blob | history
packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c patch | blob | history

diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c
index 05c4f2e5efeac70e4afea027dbec622472ca598f..7e627a8233c93e47531789c18243708182c5f515 100644 (file)
--- a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c
+++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c
@@ -62,28 +62,28 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
-extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
-extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorIntXbarInstNo[];
-extern unsigned int ccErrEdmaXbarIndex[];
-extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
-extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
+extern uint32_t ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorIntXbarInstNo[];
+extern uint32_t ccErrEdmaXbarIndex[];
+extern uint32_t tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
+extern uint32_t tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[];
+extern uint32_t hwIntCcErr[];
+extern uint32_t hwIntTcErr[];
 
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
 /* This variable has to be used as an extern */
-unsigned int gpp_num = 0;
+uint32_t gpp_num = 0;
 
 Hwi_Handle hwiCCXferCompInt;
 Hwi_Handle hwiCCErrInt;
@@ -99,35 +99,35 @@ typedef struct  {
 
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
 
 
-#define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127u)
-#define EDMA3_NUM_TCC                     (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127U)
+#define EDMA3_NUM_TCC                     (64U)
 
 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
 /*
  * Forward decleration
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum);
 
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
 
 /**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
     {
     static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 
     /*
      * Skip these interrupt xbar configuration.
@@ -217,10 +217,10 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     }
 
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
        static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
@@ -244,13 +244,13 @@ void unregisterEdma3Interrupts (unsigned int edma3Id)
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
+    uint32_t xbarEvtNum = 0;
+    int32_t          edmaChanNum = 0;
 
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
                (chanNum != NULL) &&
@@ -276,13 +276,13 @@ EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
+    uint32_t scrChanOffset = 0;
+    uint32_t scrRegOffset  = 0;
+    uint32_t xBarEvtNum    = 0;
     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
 
 
@@ -317,7 +317,7 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
        }
 
 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
-                                   unsigned int edma3Id)
+                                   uint32_t edma3Id)
     {
     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
@@ -333,7 +333,7 @@ EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
     return retVal;
     }
 
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
     {
     printf("memory Protection error");
     }
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c
index c9a6d79871f3673396ab79b9fcbeb6abca417b2d..7d6a011e66a4062ca696440fc86ec50ab80444cc 100644 (file)
--- a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c
+++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c
@@ -45,25 +45,25 @@
 #endif
 
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         2u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+#define NUM_EDMA3_INSTANCES         2U
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 /* Number of DSPs present in the system */
-#define NUM_DSPS                    1u
-const unsigned int numDsps = NUM_DSPS;
+#define NUM_DSPS                    1U
+const uint32_t numDsps = NUM_DSPS;
 
 /* Determine the processor id by reading DNUM register. */
 /* Statically allocate the region numbers with cores. */
-int myCoreNum;
-#define PID0_ADDRESS 0xE00FFFE0
+int32_t myCoreNum;
+#define PID0_ADDRESS 0xE00FFFE0U
 #define CORE_ID_C0 0x0
 #define CORE_ID_C1 0x1
 
-unsigned short determineProcId()
+uint16_t determineProcId()
 {
-    unsigned short regionNo = numEdma3Instances;
+    uint16_t regionNo = numEdma3Instances;
 #ifdef BUILD_DRA72X_DSP
-    extern __cregister volatile unsigned int DNUM;
+    extern __cregister volatile uint32_t DNUM;
 #endif
 
     myCoreNum = numDsps;
@@ -79,7 +79,7 @@ unsigned short determineProcId()
        else
                regionNo = 0;
 #elif defined(BUILD_DRA72X_IPU)
-    myCoreNum = (*(unsigned int *)(PID0_ADDRESS));
+    myCoreNum = (*(uint32_t *)(PID0_ADDRESS));
     if(Core_getIpuId() == 1){
         if(myCoreNum == CORE_ID_C0)
             regionNo = 4;
@@ -98,11 +98,11 @@ unsigned short determineProcId()
        return regionNo;
 }
 
-signed char*  getGlobalAddr(signed char* addr)
+int8_t*  getGlobalAddr(int8_t* addr)
 {
      return (addr); /* The address is already a global address */
 }
-unsigned short isGblConfigRequired(unsigned int dspNum)
+uint16_t isGblConfigRequired(uint32_t dspNum)
 {
     (void) dspNum;
        return 1;
@@ -112,63 +112,63 @@ unsigned short isGblConfigRequired(unsigned int dspNum)
 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 
 /** Number of PaRAM Sets available                                            */
-#define EDMA3_NUM_PARAMSET                              (512u)
+#define EDMA3_NUM_PARAMSET                              (512U)
 
 /** Number of TCCS available                                                  */
-#define EDMA3_NUM_TCC                                   (64u)
+#define EDMA3_NUM_TCC                                   (64U)
 
 /** Number of DMA Channels available                                          */
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+#define EDMA3_NUM_DMA_CHANNELS                          (64U)
 
 /** Number of QDMA Channels available                                         */
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+#define EDMA3_NUM_QDMA_CHANNELS                         (8U)
 
 /** Number of Event Queues available                                          */
-#define EDMA3_NUM_EVTQUE                                (4u)
+#define EDMA3_NUM_EVTQUE                                (4U)
 
 /** Number of Transfer Controllers available                                  */
-#define EDMA3_NUM_TC                                    (2u)
+#define EDMA3_NUM_TC                                    (2U)
 
 /** Number of Regions                                                         */
-#define EDMA3_NUM_REGIONS                               (8u)
+#define EDMA3_NUM_REGIONS                               (8U)
 
 /** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)
-#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38u)
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34u)
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33u)
+#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66U)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38U)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34U)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33U)
 
 /** Based on the interrupt number to be mapped define the XBAR instance number */
-#define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)
-#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7u)
-#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12u)
-#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11u)
+#define COMPLETION_INT_A15_XBAR_INST_NO                 (29U)
+#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7U)
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12U)
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11U)
 
 /** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT_A15                          (67u)
-#define EDMA3_CC_ERROR_INT_DSP                          (39u)
-#define EDMA3_CC_ERROR_INT_IPU                          (35u)
+#define EDMA3_CC_ERROR_INT_A15                          (67U)
+#define EDMA3_CC_ERROR_INT_DSP                          (39U)
+#define EDMA3_CC_ERROR_INT_IPU                          (35U)
 
 /** Based on the interrupt number to be mapped define the XBAR instance number */
-#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)
-#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8u)
-#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13u)
+#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30U)
+#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8U)
+#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13U)
 
 /** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT_A15                         (68u)
-#define EDMA3_TC0_ERROR_INT_DSP                         (40u)
-#define EDMA3_TC0_ERROR_INT_IPU                         (36u)
-#define EDMA3_TC1_ERROR_INT_A15                         (69u)
-#define EDMA3_TC1_ERROR_INT_DSP                         (41u)
-#define EDMA3_TC1_ERROR_INT_IPU                         (37u)
+#define EDMA3_TC0_ERROR_INT_A15                         (68U)
+#define EDMA3_TC0_ERROR_INT_DSP                         (40U)
+#define EDMA3_TC0_ERROR_INT_IPU                         (36U)
+#define EDMA3_TC1_ERROR_INT_A15                         (69U)
+#define EDMA3_TC1_ERROR_INT_DSP                         (41U)
+#define EDMA3_TC1_ERROR_INT_IPU                         (37U)
 
 /** Based on the interrupt number to be mapped define the XBAR instance number */
-#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)
-#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9u)
-#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14u)
-#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)
-#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10u)
-#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15u)
+#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31U)
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9U)
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14U)
+#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32U)
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10U)
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)
 
 #ifdef BUILD_DRA72X_MPU
 #define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15
@@ -198,40 +198,40 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO
 
 #else
-#define EDMA3_CC_XFER_COMPLETION_INT                    (0u)
-#define EDMA3_CC_ERROR_INT                              (0u)
-#define CC_ERROR_INT_XBAR_INST_NO                       (0u)
-#define EDMA3_TC0_ERROR_INT                             (0u)
-#define EDMA3_TC1_ERROR_INT                             (0u)
+#define EDMA3_CC_XFER_COMPLETION_INT                    (0U)
+#define EDMA3_CC_ERROR_INT                              (0U)
+#define CC_ERROR_INT_XBAR_INST_NO                       (0U)
+#define EDMA3_TC0_ERROR_INT                             (0U)
+#define EDMA3_TC1_ERROR_INT                             (0U)
 #define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
 #define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
 #endif
 
-#define EDMA3_TC2_ERROR_INT                             (0u)
-#define EDMA3_TC3_ERROR_INT                             (0u)
-#define EDMA3_TC4_ERROR_INT                             (0u)
-#define EDMA3_TC5_ERROR_INT                             (0u)
-#define EDMA3_TC6_ERROR_INT                             (0u)
-#define EDMA3_TC7_ERROR_INT                             (0u)
+#define EDMA3_TC2_ERROR_INT                             (0U)
+#define EDMA3_TC3_ERROR_INT                             (0U)
+#define EDMA3_TC4_ERROR_INT                             (0U)
+#define EDMA3_TC5_ERROR_INT                             (0U)
+#define EDMA3_TC6_ERROR_INT                             (0U)
+#define EDMA3_TC7_ERROR_INT                             (0U)
 
-#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19u)
-#define DSP1_EDMA3_CC_ERROR_INT                         (27u)
-#define DSP1_EDMA3_TC0_ERROR_INT                        (28u)
-#define DSP1_EDMA3_TC1_ERROR_INT                        (29u)
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19U)
+#define DSP1_EDMA3_CC_ERROR_INT                         (27U)
+#define DSP1_EDMA3_TC0_ERROR_INT                        (28U)
+#define DSP1_EDMA3_TC1_ERROR_INT                        (29U)
 
 /** XBAR interrupt source index numbers for EDMA interrupts */
-#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)
-#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)
-#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)
-#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)
-#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)
-#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)
-#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)
-#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)
-
-#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)
-#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)
-#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361U)
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362U)
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363U)
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364U)
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365U)
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366U)
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367U)
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368U)
+
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359U)
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370U)
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371U)
 
 /**
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
@@ -249,12 +249,12 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  */
 /* EDMA 0 */
 
-#define EDMA3_HWI_INT_XFER_COMP                           (7u)
-#define EDMA3_HWI_INT_CC_ERR                              (7u)
-#define EDMA3_HWI_INT_TC0_ERR                             (10u)
-#define EDMA3_HWI_INT_TC1_ERR                             (10u)
-#define EDMA3_HWI_INT_TC2_ERR                             (10u)
-#define EDMA3_HWI_INT_TC3_ERR                             (10u)
+#define EDMA3_HWI_INT_XFER_COMP                           (7U)
+#define EDMA3_HWI_INT_CC_ERR                              (7U)
+#define EDMA3_HWI_INT_TC0_ERR                             (10U)
+#define EDMA3_HWI_INT_TC1_ERR                             (10U)
+#define EDMA3_HWI_INT_TC2_ERR                             (10U)
+#define EDMA3_HWI_INT_TC3_ERR                             (10U)
 
 /**
  * \brief Mapping of DMA channels 0-31 to Hardware Events from
@@ -275,8 +275,8 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                       /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06Eu)  /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFu)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06EU)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFU)  /* TBD */
 
 /**
  * \brief Mapping of DMA channels 32-63 to Hardware Events from
@@ -292,17 +292,17 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  *
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCu) /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000u) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCU) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000U) /* TBD */
 
 
 /* Variable which will be used internally for referring number of Event Queues*/
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
                                                         EDMA3_NUM_EVTQUE,
                                                     };
 
 /* Variable which will be used internally for referring number of TCs.        */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
                                                     EDMA3_NUM_TC,
                                                     EDMA3_NUM_TC
                                                 };
@@ -311,14 +311,14 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
  * Variable which will be used internally for referring transfer completion
  * interrupt.
  */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
     {
         EDMA3_CC_XFER_COMPLETION_INT_A15,
         EDMA3_CC_XFER_COMPLETION_INT_A15,
                EDMA3_CC_XFER_COMPLETION_INT_DSP,
-        0u,
+        0U,
                EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
         EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,
         EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
@@ -326,25 +326,25 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
     },
     /* EDMA3 INSTANCE# 1 */
     {
-        0u,
-        0u,
+        0U,
+        0U,
         DSP1_EDMA3_CC_XFER_COMPLETION_INT,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u
+        0U,
+        0U,
+        0U,
+        0U,
+        0U
     }
 };
 /** These are the Xbar instance numbers corresponding to interrupt numbers */
-unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
     {
         COMPLETION_INT_A15_XBAR_INST_NO,
         COMPLETION_INT_A15_XBAR_INST_NO,
                COMPLETION_INT_DSP_XBAR_INST_NO,
-        0u,
+        0U,
                COMPLETION_INT_IPU_C0_XBAR_INST_NO,
         COMPLETION_INT_IPU_C1_XBAR_INST_NO,
         COMPLETION_INT_IPU_C0_XBAR_INST_NO,
@@ -352,19 +352,19 @@ unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
     },
     /* EDMA3 INSTANCE# 1 */
     {
-        0u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u
+        0U,
+        0U,
+        0U,
+        0U,
+        0U,
+        0U,
+        0U,
+        0U
     }
 };
 
 /** These are the Interrupt Crossbar Index For EDMA Completion for different regions */
-unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
        {
@@ -394,17 +394,17 @@ unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
  * Variable which will be used internally for referring channel controller's
  * error interrupt.
  */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] =
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] =
 {
     EDMA3_CC_ERROR_INT,
     DSP1_EDMA3_CC_ERROR_INT
 };
-unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =
+uint32_t ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =
 {
     CC_ERROR_INT_XBAR_INST_NO,
     CC_ERROR_INT_XBAR_INST_NO
 };
-unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] =
+uint32_t ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] =
 {
        XBAR_EDMA_TPCC_IRQ_ERR,
     XBAR_EDMA_TPCC_IRQ_ERR
@@ -414,7 +414,7 @@ unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] =
  * Variable which will be used internally for referring transfer controllers'
  * error interrupts.
  */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
     {
@@ -431,37 +431,37 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
     }
 };
-unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
     {
        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
-       0u, 0u,
-       0u, 0u,
-       0u, 0u,
+       0U, 0U,
+       0U, 0U,
+       0U, 0U,
     },
     /* EDMA3 INSTANCE# 1 */
     {
        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
-       0u, 0u,
-       0u, 0u,
-       0u, 0u,
+       0U, 0U,
+       0U, 0U,
+       0U, 0U,
     }
 };
 
-unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
     {
        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
-       0u, 0u,
-       0u, 0u, 0u, 0u,
+       0U, 0U,
+       0U, 0U, 0U, 0U,
     },
     /* EDMA3 INSTANCE# 1 */
     {
        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
-       0u, 0u,
-       0u, 0u, 0u, 0u,
+       0U, 0U,
+       0U, 0U, 0U, 0U,
     }
 };
 
@@ -470,19 +470,19 @@ unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] =
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =
 {
     EDMA3_HWI_INT_XFER_COMP,
     EDMA3_HWI_INT_XFER_COMP
 };
 
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] =
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =
 {
     EDMA3_HWI_INT_CC_ERR,
     EDMA3_HWI_INT_CC_ERR
 };
 
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
     {
@@ -548,10 +548,10 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,
          * PaRAM entry n corresponds to channel n.
          */
-        1u,
+        1U,
 
         /** Existence of memory protection feature */
-        0u,
+        0U,
 
         /** Global Register Region of CC Registers */
         EDMA3_CC_BASE_ADDR,
@@ -592,14 +592,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)
          */
         {
-            0u,
-            1u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            0U,
+            1U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
         /**
          * \brief To Configure the Threshold level of number of events
@@ -610,14 +610,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).
          */
         {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
 
         /**
@@ -627,14 +627,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.
          */
             {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
             },
 
         /**
@@ -733,10 +733,10 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,
          * PaRAM entry n corresponds to channel n.
          */
-        1u,
+        1U,
 
         /** Existence of memory protection feature */
-        0u,
+        0U,
 
         /** Global Register Region of CC Registers */
         DSP1_EDMA3_CC_BASE_ADDR,
@@ -777,14 +777,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)
          */
         {
-            0u,
-            1u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            0U,
+            1U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
         /**
          * \brief To Configure the Threshold level of number of events
@@ -795,14 +795,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).
          */
         {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
 
         /**
@@ -812,14 +812,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.
          */
             {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
             },
 
         /**
@@ -916,35 +916,35 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -952,46 +952,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                        /* Resources owned/reserved by region 1 (Associated to MPU core 1) */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                  /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -999,46 +999,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 2 (Associated to DSP1)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1046,93 +1046,93 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1140,46 +1140,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1187,46 +1187,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1234,46 +1234,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1281,11 +1281,11 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
            },
                /* EDMA3 INSTANCE# 1 DSP1 EDMA*/
@@ -1294,129 +1294,129 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                        /* Resources owned/reserved by region 1 (Not Associated to any core supported) */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 2 (Associated to DSP core)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1424,246 +1424,246 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
            }
 };
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c
index abd1c2d13fa935dbbe08556f9c5367c043043142..9705fbc07237656e5c2f481f6b506a04f5d8cd85 100644 (file)
--- a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c
+++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c
@@ -60,26 +60,26 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
-extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
-extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorIntXbarInstNo[];
-extern unsigned int ccErrEdmaXbarIndex[];
-extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
-extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
+extern uint32_t ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorIntXbarInstNo[];
+extern uint32_t ccErrEdmaXbarIndex[];
+extern uint32_t tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
+extern uint32_t tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[];
+extern uint32_t hwIntCcErr[];
+extern uint32_t hwIntTcErr[];
 
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
 
 /* External Instance Specific Configuration Structure */
 extern EDMA3_DRV_GblXbarToChanConfigParams
@@ -91,35 +91,35 @@ typedef struct  {
 
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
 
 
-#define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127u)
-#define EDMA3_NUM_TCC                     (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127U)
+#define EDMA3_NUM_TCC                     (64U)
 
 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
 
 /*
  * Forward decleration
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum);
 
 
 /**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
     {
     static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
     /* Do the xbar configuration only for edma inst 0 */
        /* EDMA inst 1 is for DSP1 EDMA which has direct interrupt mapping */
        if(edma3Id == 0)
@@ -178,10 +178,10 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     }
 
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
        static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
@@ -211,13 +211,13 @@ void unregisterEdma3Interrupts (unsigned int edma3Id)
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
+    uint32_t xbarEvtNum = 0;
+    int32_t          edmaChanNum = 0;
 
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
                (chanNum != NULL) &&
@@ -243,13 +243,13 @@ EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
+    uint32_t scrChanOffset = 0;
+    uint32_t scrRegOffset  = 0;
+    uint32_t xBarEvtNum    = 0;
     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
 
 
@@ -284,7 +284,7 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
        }
 
 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
-                                   unsigned int edma3Id)
+                                   uint32_t edma3Id)
     {
     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_arm_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_arm_int_reg.c
index 2f56be501b126ead2a90a1b12466e97693f39686..88276f5ce2b9705c2be407956249e884c671e807 100644 (file)
--- a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_arm_int_reg.c
+++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_arm_int_reg.c
@@ -60,22 +60,22 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[];
+extern uint32_t hwIntCcErr[];
+extern uint32_t hwIntTcErr[];
 
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
 /* This variable has to be used as an extern */
-unsigned int gpp_num = 0;
+uint32_t gpp_num = 0;
 
 Hwi_Handle hwiCCXferCompInt;
 Hwi_Handle hwiCCErrInt;
@@ -91,35 +91,35 @@ typedef struct  {
 
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
 
 
-#define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127u)
-#define EDMA3_NUM_TCC                     (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127U)
+#define EDMA3_NUM_TCC                     (64U)
 
 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
 /*
  * Forward decleration
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum);
 
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
 
 /**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
     {
     static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
     Hwi_Params hwiParams;
     Error_Block      eb;
 
@@ -210,10 +210,10 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     }
 
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
        static UInt32 cookie = 0;
-    unsigned int numTc = 0;
+    uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
@@ -237,13 +237,13 @@ void unregisterEdma3Interrupts (unsigned int edma3Id)
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+                 uint32_t *chanNum,
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
+    uint32_t xbarEvtNum = 0;
+    int32_t          edmaChanNum = 0;
 
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
                (chanNum != NULL) &&
@@ -269,13 +269,13 @@ EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
  *
  * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+                                  uint32_t chanNum)
        {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
+    uint32_t scrChanOffset = 0;
+    uint32_t scrRegOffset  = 0;
+    uint32_t xBarEvtNum    = 0;
     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
 
 
@@ -310,7 +310,7 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
        }
 
 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
-                                   unsigned int edma3Id)
+                                   uint32_t edma3Id)
     {
     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
@@ -326,7 +326,7 @@ EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
     return retVal;
     }
 
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
     {
     printf("memory Protection error");
     }
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c
index 8f17253e52c8effaaf28b5f42e6df96316e82769..4a3dbdc5a984efa838be222dd508b819476bf105 100644 (file)
--- a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c
+++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c
@@ -44,24 +44,24 @@
 
 #endif
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         2u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+#define NUM_EDMA3_INSTANCES         2U
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 /* Number of DSPs present in the system */
-#define NUM_DSPS                    1u
-const unsigned int numDsps = NUM_DSPS;
+#define NUM_DSPS                    1U
+const uint32_t numDsps = NUM_DSPS;
 
 /* Determine the processor id by reading DNUM register. */
 /* Statically allocate the region numbers with cores. */
-int myCoreNum;
+int32_t myCoreNum;
 #define PID0_ADDRESS 0xE00FFFE0
 #define CORE_ID_C0 0x0
 #define CORE_ID_C1 0x1
-unsigned short determineProcId()
+uint16_t determineProcId()
 {
-unsigned short regionNo = numEdma3Instances;
+uint16_t regionNo = numEdma3Instances;
 #ifdef BUILD_TDA2XX_DSP
-extern __cregister volatile unsigned int DNUM;
+extern __cregister volatile uint32_t DNUM;
 #endif
 myCoreNum = numDsps;
 #ifdef BUILD_TDA2XX_MPU
@@ -76,7 +76,7 @@ myCoreNum = numDsps;
        else
                regionNo = 0;
 #elif defined(BUILD_TDA2XX_IPU)
-myCoreNum = (*(unsigned int *)(PID0_ADDRESS));
+myCoreNum = (*(uint32_t *)(PID0_ADDRESS));
 if(Core_getIpuId() == 1){
        if(myCoreNum == CORE_ID_C0)
                regionNo = 4;
@@ -99,11 +99,11 @@ if(Core_getIpuId() == 2){
        return regionNo;
 }
 
-signed char*  getGlobalAddr(signed char* addr)
+int8_t*  getGlobalAddr(int8_t* addr)
 {
      return (addr); /* The address is already a global address */
 }
-unsigned short isGblConfigRequired(unsigned int dspNum)
+uint16_t isGblConfigRequired(uint32_t dspNum)
 {
     (void) dspNum;
 
@@ -114,63 +114,63 @@ unsigned short isGblConfigRequired(unsigned int dspNum)
 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 
 /** Number of PaRAM Sets available                                            */
-#define EDMA3_NUM_PARAMSET                              (512u)
+#define EDMA3_NUM_PARAMSET                              (512U)
 
 /** Number of TCCS available                                                  */
-#define EDMA3_NUM_TCC                                   (64u)
+#define EDMA3_NUM_TCC                                   (64U)
 
 /** Number of DMA Channels available                                          */
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+#define EDMA3_NUM_DMA_CHANNELS                          (64U)
 
 /** Number of QDMA Channels available                                         */
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+#define EDMA3_NUM_QDMA_CHANNELS                         (8U)
 
 /** Number of Event Queues available                                          */
-#define EDMA3_NUM_EVTQUE                              (4u)
+#define EDMA3_NUM_EVTQUE                              (4U)
 
 /** Number of Transfer Controllers available                                  */
-#define EDMA3_NUM_TC                                  (4u)
+#define EDMA3_NUM_TC                                  (4U)
 
 /** Number of Regions                                                         */
-#define EDMA3_NUM_REGIONS                             (2u)
+#define EDMA3_NUM_REGIONS                             (2U)
 
 /** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)
-#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38u)
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34u)
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33u)
+#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66U)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38U)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34U)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33U)
 
 /** Based on the interrupt number to be mapped define the XBAR instance number */
-#define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)
-#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7u)
-#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12u)
-#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11u)
+#define COMPLETION_INT_A15_XBAR_INST_NO                 (29U)
+#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7U)
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12U)
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11U)
 
 /** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT_A15                          (67u)
-#define EDMA3_CC_ERROR_INT_DSP                          (39u)
-#define EDMA3_CC_ERROR_INT_IPU                          (35u)
+#define EDMA3_CC_ERROR_INT_A15                          (67U)
+#define EDMA3_CC_ERROR_INT_DSP                          (39U)
+#define EDMA3_CC_ERROR_INT_IPU                          (35U)
 
 /** Based on the interrupt number to be mapped define the XBAR instance number */
-#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)
-#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8u)
-#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13u)
+#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30U)
+#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8U)
+#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13U)
 
 /** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT_A15                         (68u)
-#define EDMA3_TC0_ERROR_INT_DSP                         (40u)
-#define EDMA3_TC0_ERROR_INT_IPU                         (36u)
-#define EDMA3_TC1_ERROR_INT_A15                         (69u)
-#define EDMA3_TC1_ERROR_INT_DSP                         (41u)
-#define EDMA3_TC1_ERROR_INT_IPU                         (37u)
+#define EDMA3_TC0_ERROR_INT_A15                         (68U)
+#define EDMA3_TC0_ERROR_INT_DSP                         (40U)
+#define EDMA3_TC0_ERROR_INT_IPU                         (36U)
+#define EDMA3_TC1_ERROR_INT_A15                         (69U)
+#define EDMA3_TC1_ERROR_INT_DSP                         (41U)
+#define EDMA3_TC1_ERROR_INT_IPU                         (37U)
 
 /** Based on the interrupt number to be mapped define the XBAR instance number */
-#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)
-#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9u)
-#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14u)
-#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)
-#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10u)
-#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15u)
+#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31U)
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9U)
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14U)
+#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32U)
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10U)
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)
 
 #ifdef BUILD_DRA72X_MPU
 #define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15
@@ -200,40 +200,40 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO
 
 #else
-#define EDMA3_CC_XFER_COMPLETION_INT                    (0u)
-#define EDMA3_CC_ERROR_INT                              (0u)
-#define CC_ERROR_INT_XBAR_INST_NO                       (0u)
-#define EDMA3_TC0_ERROR_INT                             (0u)
-#define EDMA3_TC1_ERROR_INT                             (0u)
+#define EDMA3_CC_XFER_COMPLETION_INT                    (0U)
+#define EDMA3_CC_ERROR_INT                              (0U)
+#define CC_ERROR_INT_XBAR_INST_NO                       (0U)
+#define EDMA3_TC0_ERROR_INT                             (0U)
+#define EDMA3_TC1_ERROR_INT                             (0U)
 #define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
 #define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
 #endif
 
-#define EDMA3_TC2_ERROR_INT                             (0u)
-#define EDMA3_TC3_ERROR_INT                             (0u)
-#define EDMA3_TC4_ERROR_INT                             (0u)
-#define EDMA3_TC5_ERROR_INT                             (0u)
-#define EDMA3_TC6_ERROR_INT                             (0u)
-#define EDMA3_TC7_ERROR_INT                             (0u)
+#define EDMA3_TC2_ERROR_INT                             (0U)
+#define EDMA3_TC3_ERROR_INT                             (0U)
+#define EDMA3_TC4_ERROR_INT                             (0U)
+#define EDMA3_TC5_ERROR_INT                             (0U)
+#define EDMA3_TC6_ERROR_INT                             (0U)
+#define EDMA3_TC7_ERROR_INT                             (0U)
 
-#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19u)
-#define DSP1_EDMA3_CC_ERROR_INT                         (27u)
-#define DSP1_EDMA3_TC0_ERROR_INT                        (28u)
-#define DSP1_EDMA3_TC1_ERROR_INT                        (29u)
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19U)
+#define DSP1_EDMA3_CC_ERROR_INT                         (27U)
+#define DSP1_EDMA3_TC0_ERROR_INT                        (28U)
+#define DSP1_EDMA3_TC1_ERROR_INT                        (29U)
 
 /** XBAR interrupt source index numbers for EDMA interrupts */
-#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)
-#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)
-#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)
-#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)
-#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)
-#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)
-#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)
-#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)
-
-#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)
-#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)
-#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361U)
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362U)
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363U)
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364U)
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365U)
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366U)
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367U)
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368U)
+
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359U)
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370U)
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371U)
 
 /**
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
@@ -251,12 +251,12 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  */
 /* EDMA 0 */
 
-#define EDMA3_HWI_INT_XFER_COMP                           (7u)
-#define EDMA3_HWI_INT_CC_ERR                              (7u)
-#define EDMA3_HWI_INT_TC0_ERR                             (10u)
-#define EDMA3_HWI_INT_TC1_ERR                             (10u)
-#define EDMA3_HWI_INT_TC2_ERR                             (10u)
-#define EDMA3_HWI_INT_TC3_ERR                             (10u)
+#define EDMA3_HWI_INT_XFER_COMP                           (7U)
+#define EDMA3_HWI_INT_CC_ERR                              (7U)
+#define EDMA3_HWI_INT_TC0_ERR                             (10U)
+#define EDMA3_HWI_INT_TC1_ERR                             (10U)
+#define EDMA3_HWI_INT_TC2_ERR                             (10U)
+#define EDMA3_HWI_INT_TC3_ERR                             (10U)
 
 
 /**
@@ -278,8 +278,8 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                       /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06Eu)  /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFu)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06EU)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFU)  /* TBD */
 
 /**
  * \brief Mapping of DMA channels 32-63 to Hardware Events from
@@ -295,17 +295,17 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  *
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCu) /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000u) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCU) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000U) /* TBD */
 
 
 /* Variable which will be used internally for referring number of Event Queues*/
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
                                                         EDMA3_NUM_EVTQUE,
                                                     };
 
 /* Variable which will be used internally for referring number of TCs.        */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
                                                     EDMA3_NUM_TC,
                                                     EDMA3_NUM_TC
                                                 };
@@ -314,14 +314,14 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
  * Variable which will be used internally for referring transfer completion
  * interrupt.
  */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
     {
         EDMA3_CC_XFER_COMPLETION_INT_A15,
         EDMA3_CC_XFER_COMPLETION_INT_A15,
                EDMA3_CC_XFER_COMPLETION_INT_DSP,
-        0u,
+        0U,
                EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
         EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,
         EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
@@ -329,14 +329,14 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
     },
     /* EDMA3 INSTANCE# 1 */
     {
-        0u,
-        0u,
+        0U,
+        0U,
         DSP1_EDMA3_CC_XFER_COMPLETION_INT,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u
+        0U,
+        0U,
+        0U,
+        0U,
+        0U
     }
 };
 
@@ -344,7 +344,7 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
  * Variable which will be used internally for referring channel controller's
  * error interrupt.
  */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] =
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] =
 {
     EDMA3_CC_ERROR_INT,
     DSP1_EDMA3_CC_ERROR_INT
@@ -354,7 +354,7 @@ unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] =
  * Variable which will be used internally for referring transfer controllers'
  * error interrupts.
  */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
     {
@@ -376,19 +376,19 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] =
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =
 {
     EDMA3_HWI_INT_XFER_COMP,
     EDMA3_HWI_INT_XFER_COMP
 };
 
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] =
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =
 {
     EDMA3_HWI_INT_CC_ERR,
     EDMA3_HWI_INT_CC_ERR
 };
 
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
     {
@@ -454,10 +454,10 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,
          * PaRAM entry n corresponds to channel n.
          */
-        1u,
+        1U,
 
         /** Existence of memory protection feature */
-        0u,
+        0U,
 
         /** Global Register Region of CC Registers */
         EDMA3_CC_BASE_ADDR,
@@ -498,14 +498,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)
          */
         {
-            0u,
-            1u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            0U,
+            1U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
         /**
          * \brief To Configure the Threshold level of number of events
@@ -516,14 +516,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).
          */
         {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
 
         /**
@@ -533,14 +533,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.
          */
             {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
             },
 
         /**
@@ -639,10 +639,10 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,
          * PaRAM entry n corresponds to channel n.
          */
-        1u,
+        1U,
 
         /** Existence of memory protection feature */
-        0u,
+        0U,
 
         /** Global Register Region of CC Registers */
         DSP1_EDMA3_CC_BASE_ADDR,
@@ -683,14 +683,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)
          */
         {
-            0u,
-            1u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            0U,
+            1U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
         /**
          * \brief To Configure the Threshold level of number of events
@@ -701,14 +701,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).
          */
         {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
 
         /**
@@ -718,14 +718,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.
          */
             {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
             },
 
         /**
@@ -822,35 +822,35 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -858,46 +858,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                        /* Resources owned/reserved by region 1 (Associated to MPU core 1) */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                  /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -905,46 +905,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                        /* Resources owned/reserved by region 2 (Associated to any DSP core) */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -952,93 +952,93 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1046,46 +1046,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1093,46 +1093,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1140,46 +1140,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1187,11 +1187,11 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
            },
                /* EDMA3 INSTANCE# 1 DSP1 EDMA*/
@@ -1200,129 +1200,129 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                        /* Resources owned/reserved by region 1 (Not Associated to any core supported) */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 2 (Associated to DSP core)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1330,246 +1330,246 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
            }
 };
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c
index e27db93e13bb1b2a79640dd96d302889fc4fcd7c..7aaf43c01ef81b1d7fcb7af8876cba096d0dc3f6 100644 (file)
--- a/packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c
+++ b/packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c
@@ -42,69 +42,69 @@
 
 #endif
 
-#define NUM_SHADOW_REGIONS                      (8u)
+#define NUM_SHADOW_REGIONS                      (8U)
 
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         2u
+#define NUM_EDMA3_INSTANCES         2U
 
 /** Number of PaRAM Sets available                                            */
-#define EDMA3_NUM_PARAMSET                              (512u)
+#define EDMA3_NUM_PARAMSET                              (512U)
 
 /** Number of TCCS available                                                  */
-#define EDMA3_NUM_TCC                                   (64u)
+#define EDMA3_NUM_TCC                                   (64U)
 
 /** Number of DMA Channels available                                          */
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+#define EDMA3_NUM_DMA_CHANNELS                          (64U)
 
 /** Number of QDMA Channels available                                         */
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+#define EDMA3_NUM_QDMA_CHANNELS                         (8U)
 
 /** Number of Event Queues available                                          */
-#define EDMA3_NUM_EVTQUE                                (4u)
+#define EDMA3_NUM_EVTQUE                                (4U)
 
 /** Number of Transfer Controllers available                                  */
-#define EDMA3_NUM_TC                                    (2u)
+#define EDMA3_NUM_TC                                    (2U)
 
 /** Number of Regions                                                         */
-#define EDMA3_NUM_REGIONS                               (8u)
+#define EDMA3_NUM_REGIONS                               (8U)
 
 /** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)
-#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38u)
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34u)
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33u)
+#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66U)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38U)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34U)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33U)
 
 /** Based on the interrupt number to be mapped define the XBAR instance number */
-#define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)
-#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7u)
-#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12u)
-#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11u)
+#define COMPLETION_INT_A15_XBAR_INST_NO                 (29U)
+#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7U)
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12U)
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11U)
 
 /** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT_A15                          (67u)
-#define EDMA3_CC_ERROR_INT_DSP                          (39u)
-#define EDMA3_CC_ERROR_INT_IPU                          (35u)
+#define EDMA3_CC_ERROR_INT_A15                          (67U)
+#define EDMA3_CC_ERROR_INT_DSP                          (39U)
+#define EDMA3_CC_ERROR_INT_IPU                          (35U)
 
 /** Based on the interrupt number to be mapped define the XBAR instance number */
-#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)
-#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8u)
-#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13u)
+#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30U)
+#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8U)
+#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13U)
 
 /** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT_A15                         (68u)
-#define EDMA3_TC0_ERROR_INT_DSP                         (40u)
-#define EDMA3_TC0_ERROR_INT_IPU                         (36u)
-#define EDMA3_TC1_ERROR_INT_A15                         (69u)
-#define EDMA3_TC1_ERROR_INT_DSP                         (41u)
-#define EDMA3_TC1_ERROR_INT_IPU                         (37u)
+#define EDMA3_TC0_ERROR_INT_A15                         (68U)
+#define EDMA3_TC0_ERROR_INT_DSP                         (40U)
+#define EDMA3_TC0_ERROR_INT_IPU                         (36U)
+#define EDMA3_TC1_ERROR_INT_A15                         (69U)
+#define EDMA3_TC1_ERROR_INT_DSP                         (41U)
+#define EDMA3_TC1_ERROR_INT_IPU                         (37U)
 
 /** Based on the interrupt number to be mapped define the XBAR instance number */
-#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)
-#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9u)
-#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14u)
-#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)
-#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10u)
-#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15u)
+#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31U)
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9U)
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14U)
+#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32U)
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10U)
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)
 
 #ifdef BUILD_DRA72X_MPU
 #define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15
@@ -134,26 +134,26 @@
 #define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO
 
 #else
-#define EDMA3_CC_XFER_COMPLETION_INT                    (0u)
-#define EDMA3_CC_ERROR_INT                              (0u)
-#define CC_ERROR_INT_XBAR_INST_NO                       (0u)
-#define EDMA3_TC0_ERROR_INT                             (0u)
-#define EDMA3_TC1_ERROR_INT                             (0u)
+#define EDMA3_CC_XFER_COMPLETION_INT                    (0U)
+#define EDMA3_CC_ERROR_INT                              (0U)
+#define CC_ERROR_INT_XBAR_INST_NO                       (0U)
+#define EDMA3_TC0_ERROR_INT                             (0U)
+#define EDMA3_TC1_ERROR_INT                             (0U)
 #define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
 #define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
 #endif
 
-#define EDMA3_TC2_ERROR_INT                             (0u)
-#define EDMA3_TC3_ERROR_INT                             (0u)
-#define EDMA3_TC4_ERROR_INT                             (0u)
-#define EDMA3_TC5_ERROR_INT                             (0u)
-#define EDMA3_TC6_ERROR_INT                             (0u)
-#define EDMA3_TC7_ERROR_INT                             (0u)
+#define EDMA3_TC2_ERROR_INT                             (0U)
+#define EDMA3_TC3_ERROR_INT                             (0U)
+#define EDMA3_TC4_ERROR_INT                             (0U)
+#define EDMA3_TC5_ERROR_INT                             (0U)
+#define EDMA3_TC6_ERROR_INT                             (0U)
+#define EDMA3_TC7_ERROR_INT                             (0U)
 
 #define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19u)
 #define DSP1_EDMA3_CC_ERROR_INT                         (27u)
 #define DSP1_EDMA3_TC0_ERROR_INT                        (28u)
-#define DSP1_EDMA3_TC1_ERROR_INT                        (29u)
+#define DSP1_EDMA3_TC1_ERROR_INT                        (29U)
 
 /** XBAR interrupt source index numbers for EDMA interrupts */
 #define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)
@@ -185,12 +185,12 @@
  */
 /* EDMA 0 */
 
-#define EDMA3_HWI_INT_XFER_COMP                           (7u)
-#define EDMA3_HWI_INT_CC_ERR                              (7u)
-#define EDMA3_HWI_INT_TC0_ERR                             (10u)
-#define EDMA3_HWI_INT_TC1_ERR                             (10u)
-#define EDMA3_HWI_INT_TC2_ERR                             (10u)
-#define EDMA3_HWI_INT_TC3_ERR                             (10u)
+#define EDMA3_HWI_INT_XFER_COMP                           (7U)
+#define EDMA3_HWI_INT_CC_ERR                              (7U)
+#define EDMA3_HWI_INT_TC0_ERR                             (10U)
+#define EDMA3_HWI_INT_TC1_ERR                             (10U)
+#define EDMA3_HWI_INT_TC2_ERR                             (10U)
+#define EDMA3_HWI_INT_TC3_ERR                             (10U)
 
 /**
  * \brief Mapping of DMA channels 0-31 to Hardware Events from
@@ -230,7 +230,7 @@
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCu) /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000u) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000U) /* TBD */
 
 
 
@@ -283,10 +283,10 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,
          * PaRAM entry n corresponds to channel n.
          */
-        1u,
+        1U,
 
         /** Existence of memory protection feature */
-        0u,
+        0U,
 
         /** Global Register Region of CC Registers */
         EDMA3_CC_BASE_ADDR,
@@ -327,14 +327,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)
          */
         {
-            0u,
-            1u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            0U,
+            1U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
         /**
          * \brief To Configure the Threshold level of number of events
@@ -345,14 +345,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).
          */
         {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
 
         /**
@@ -362,14 +362,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.
          */
             {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
             },
 
         /**
@@ -468,10 +468,10 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,
          * PaRAM entry n corresponds to channel n.
          */
-        1u,
+        1U,
 
         /** Existence of memory protection feature */
-        0u,
+        0U,
 
         /** Global Register Region of CC Registers */
         DSP1_EDMA3_CC_BASE_ADDR,
@@ -512,14 +512,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)
          */
         {
-            0u,
-            1u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            0U,
+            1U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
         /**
          * \brief To Configure the Threshold level of number of events
@@ -530,14 +530,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).
          */
         {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
         },
 
         /**
@@ -547,14 +547,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.
          */
             {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
+            16U,
+            16U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U,
+            0U
             },
 
         /**
@@ -651,35 +651,35 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_R
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -687,46 +687,46 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_R
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                        /* Resources owned/reserved by region 1 (Associated to MPU core 1) */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                  /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -734,46 +734,46 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_R
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 2 (Associated to DSP1)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -781,93 +781,93 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_R
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -875,46 +875,46 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_R
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -922,46 +922,46 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_R
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -969,46 +969,46 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_R
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1016,11 +1016,11 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_R
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
            },
                /* EDMA3 INSTANCE# 1 DSP1 EDMA*/
@@ -1029,129 +1029,129 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_R
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                        /* Resources owned/reserved by region 1 (Not Associated to any core supported) */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
                        },
 
                /* Resources owned/reserved by region 2 (Associated to DSP core)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x000000FFU},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
@@ -1159,246 +1159,246 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_SHADOW_R
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00U},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00U, 0x00U},
                        },
 
                /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00000000U},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00000000U, 0x00000000U},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},