Misc changes in Resource Manager
authorAnuj Aggarwal <anuj.aggarwal@ti.com>
Thu, 20 Aug 2009 05:09:50 +0000 (10:39 +0530)
committerAnuj Aggarwal <anuj.aggarwal@ti.com>
Thu, 20 Aug 2009 05:09:50 +0000 (10:39 +0530)
- license header change
- dynamic ranges of logical channels according to the number of
resources available in the EDMA3 controller
- 2D internal data structures to handle multiple EDMA3 hardwares
- edma3MemSet -> edma3MemZero
- edma3OsProtectEntry / edma3OsProtectExit signature change to
accomodate EDMA3 controller ID

packages/ti/sdo/edma3/rm/edma3_common.h
packages/ti/sdo/edma3/rm/edma3_rm.h
packages/ti/sdo/edma3/rm/src/edma3_da830_cfg.c [deleted file]
packages/ti/sdo/edma3/rm/src/edma3_log.h
packages/ti/sdo/edma3/rm/src/edma3_rl_cc.h
packages/ti/sdo/edma3/rm/src/edma3_rl_tc.h
packages/ti/sdo/edma3/rm/src/edma3_rm_gbl_data.c
packages/ti/sdo/edma3/rm/src/edma3resmgr.c
packages/ti/sdo/edma3/rm/src/edma3resmgr.h

index 71d3ab3bf605a56c4dcacde0b77c172462b1c1f2..f2cc092e6c3d8770d2811b70df653d5db76002f6 100644 (file)
@@ -1,43 +1,40 @@
-/******************************************************************************
-**+-------------------------------------------------------------------------+**
-**|                            ****                                         |**
-**|                            ****                                         |**
-**|                            ******o***                                   |**
-**|                      ********_///_****                                  |**
-**|                      ***** /_//_/ ****                                  |**
-**|                       ** ** (__/ ****                                   |**
-**|                           *********                                     |**
-**|                            ****                                         |**
-**|                            ***                                          |**
-**|                                                                         |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated          |**
-**|                        ALL RIGHTS RESERVED                              |**
-**|                                                                         |**
-**| Permission is hereby granted to licensees of Texas Instruments          |**
-**| Incorporated (TI) products to use this computer program for the sole    |**
-**| purpose of implementing a licensee product based on TI products.        |**
-**| No other rights to reproduce, use, or disseminate this computer         |**
-**| program, whether in part or in whole, are granted.                      |**
-**|                                                                         |**
-**| TI makes no representation or warranties with respect to the            |**
-**| performance of this computer program, and specifically disclaims        |**
-**| any responsibility for any damages, special or consequential,           |**
-**| connected with the use of this program.                                 |**
-**|                                                                         |**
-**+-------------------------------------------------------------------------+**
-******************************************************************************/
-
-/** \file   edma3_common.h
-    \brief  EDMA3 Common header provides generic defines/typedefs and
-             debugging info.
-
-    This file contains the generic defines and typedefs and the debugging
-    info that are common across interfaces of EDMA Res Mgr and EDMA Driver
-    and visible to the application.
-
-    (C) Copyright 2006, Texas Instruments, Inc
-
- */
+/*
+ * edma3_common.h
+ *
+ * EDMA3 common header providing generic defines/typedefs and debugging info.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
 
 #ifndef _EDMA3_COMMON_H_
 #define _EDMA3_COMMON_H_
@@ -128,7 +125,7 @@ typedef void    *EDMA3_OS_Sem_Handle;
  * Manager.
  */
 /** Maximum EDMA3 Controllers on the SoC */
-#define EDMA3_MAX_EDMA3_INSTANCES               (1u)
+#define EDMA3_MAX_EDMA3_INSTANCES               (3u)
 /** Maximum DMA channels supported by the EDMA3 Controller */
 #define EDMA3_MAX_DMA_CH                        (64u)
 /** Maximum QDMA channels supported by the EDMA3 Controller */
@@ -269,6 +266,7 @@ extern void lisrEdma3TC7ErrHandler0(unsigned int arg);
  *      For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the
  *      Transfer Controller number whose interrupt needs to be disabled.
  *
+ * \param   edma3InstanceId is EDMA3 hardware instance id.
  * \param   level is numeric identifier of the desired degree of protection.
  * \param   intState is memory location where current state of protection is
  *      saved for future use while restoring it via edma3OsProtectExit() (Only
@@ -276,7 +274,9 @@ extern void lisrEdma3TC7ErrHandler0(unsigned int arg);
  *
  * \return  None
  */
-extern void edma3OsProtectEntry (int level, unsigned int *intState);
+extern void edma3OsProtectEntry (unsigned int edma3InstanceId,
+                                                                               int level, 
+                                                                               unsigned int *intState);
 
 
 /** \fn     extern void edma3OsProtectExit (int level, unsigned int intState);
@@ -291,6 +291,7 @@ extern void edma3OsProtectEntry (int level, unsigned int *intState);
  *      For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the
  *      Transfer Controller number whose interrupt needs to be enabled.
  *
+ * \param   edma3InstanceId is EDMA3 hardware instance id.
  * \param   level is numeric identifier of the desired degree of protection.
  * \param   intState is original state of protection at time when the
  *      corresponding edma3OsProtectEntry() was called (Only
@@ -298,7 +299,9 @@ extern void edma3OsProtectEntry (int level, unsigned int *intState);
  *
  * \return  None
  */
-extern void edma3OsProtectExit (int level, unsigned int intState);
+extern void edma3OsProtectExit (unsigned int edma3InstanceId,
+                                                                               int level, 
+                                                                               unsigned int intState);
 
 
 /**
index 32f8ccdd7599365f426a4bfaddd657cdfcbe3a25..6d64903c936c21430069a58c1755ecda13c55011 100644 (file)
@@ -1,41 +1,40 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**|                            ****                                          |**
-**|                            ****                                          |**
-**|                            ******o***                                    |**
-**|                      ********_///_****                                   |**
-**|                      ***** /_//_/ ****                                   |**
-**|                       ** ** (__/ ****                                    |**
-**|                           *********                                      |**
-**|                            ****                                          |**
-**|                            ***                                           |**
-**|                                                                          |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
-**|                        ALL RIGHTS RESERVED                               |**
-**|                                                                          |**
-**| Permission is hereby granted to licensees of Texas Instruments           |**
-**| Incorporated (TI) products to use this computer program for the sole     |**
-**| purpose of implementing a licensee product based on TI products.         |**
-**| No other rights to reproduce, use, or disseminate this computer          |**
-**| program, whether in part or in whole, are granted.                       |**
-**|                                                                          |**
-**| TI makes no representation or warranties with respect to the             |**
-**| performance of this computer program, and specifically disclaims         |**
-**| any responsibility for any damages, special or consequential,            |**
-**| connected with the use of this program.                                  |**
-**|                                                                          |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/** \file   edma3_rm.h
-    \brief  EDMA3 Controller Resource Manager Interface
-
-    This file contains Application Interface for the EDMA3 Controller
-    Resource Manager.
-
-    (C) Copyright 2006, Texas Instruments, Inc
-
- */
+/*
+ * edma3_rm.h
+ *
+ * EDMA3 Controller Resource Manager Interface
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
 
 #ifndef _EDMA3_RM_H_
 #define _EDMA3_RM_H_
@@ -756,10 +755,10 @@ typedef struct  {
      * any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA
      * channel (like QDMA Channels).
      */
-    unsigned short      dmaChPaRAMMapExists;
+    unsigned int               dmaChPaRAMMapExists;
 
     /** Existence of memory protection feature */
-    unsigned short      memProtectionExists;
+    unsigned int               memProtectionExists;
 
     /** Base address of EDMA3 CC memory mapped registers. */
     void                *globalRegs;
@@ -983,7 +982,7 @@ typedef struct {
      * region associated with this master instance will receive the EDMA3
      * interrupts (if enabled).
      */
-    unsigned short                  isMaster;
+    unsigned int                       isMaster;
 
     /**
      * EDMA3 resources related shadow region specific information. Which all
@@ -1005,7 +1004,7 @@ typedef struct {
     /**
      * Whether initialization of Region Specific Registers is required or not?
      */
-    unsigned short                  regionInitEnable;
+    unsigned int                                       regionInitEnable;
 
     /** Instance wide Global Error callback parameters */
     EDMA3_RM_GblErrCallbackParams   gblerrCbParams;
@@ -1892,7 +1891,7 @@ typedef enum
  *
  * Use this enum to get the physical address of the Channel Controller or the
  * Transfer Controller. The address returned could be used by the advanced
- * usres to set/get some specific registers direclty.
+ * users to set/get some specific registers direclty.
  */
 typedef enum
 {
diff --git a/packages/ti/sdo/edma3/rm/src/edma3_da830_cfg.c b/packages/ti/sdo/edma3/rm/src/edma3_da830_cfg.c
deleted file mode 100644 (file)
index 9af7465..0000000
+++ /dev/null
@@ -1,529 +0,0 @@
-/******************************************************************************
-**+-------------------------------------------------------------------------+**
-**|                            ****                                         |**
-**|                            ****                                         |**
-**|                            ******o***                                   |**
-**|                      ********_///_****                                  |**
-**|                      ***** /_//_/ ****                                  |**
-**|                       ** ** (__/ ****                                   |**
-**|                           *********                                     |**
-**|                            ****                                         |**
-**|                            ***                                          |**
-**|                                                                         |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated          |**
-**|                        ALL RIGHTS RESERVED                              |**
-**|                                                                         |**
-**| Permission is hereby granted to licensees of Texas Instruments          |**
-**| Incorporated (TI) products to use this computer program for the sole    |**
-**| purpose of implementing a licensee product based on TI products.        |**
-**| No other rights to reproduce, use, or disseminate this computer         |**
-**| program, whether in part or in whole, are granted.                      |**
-**|                                                                         |**
-**| TI makes no representation or warranties with respect to the            |**
-**| performance of this computer program, and specifically disclaims        |**
-**| any responsibility for any damages, special or consequential,           |**
-**| connected with the use of this program.                                 |**
-**|                                                                         |**
-**+-------------------------------------------------------------------------+**
-******************************************************************************/
-
-/** \file   edma3_da830_cfg.c
- *  \brief  EDMA3 Driver Adaptation Configuration File (Soc Specific) for DA8xx
- *          platform.
- *
- *  This file contains configuration data for adaptation of EDMA3 RM
- *
- *  (C) Copyright 2008, Texas Instruments, Inc
- *
- *  \version    0.1     Anuj Aggarwal     - Created
- */
-
-#include <ti/sdo/edma3/rm/edma3_rm.h>
-
-/** Total number of DMA Channels supported by the EDMA3 Controller */
-#define NUM_DMA_CHANNELS                        (32u)
-/** Total number of QDMA Channels supported by the EDMA3 Controller */
-#define NUM_QDMA_CHANNELS                       (8u)
-/** Total number of TCCs supported by the EDMA3 Controller */
-#define NUM_TCC                                 (32u)
-/** Total number of PaRAM Sets supported by the EDMA3 Controller */
-#define NUM_PARAM_SETS                          (128u)
-/** Total number of Event Queues in the EDMA3 Controller */
-#define NUM_EVENT_QUEUE                         (2u)
-/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-#define NUM_TC                                  (2u)
-/** Number of Regions on this EDMA3 controller */
-#define NUM_REGION                              (4u)
-
-/**
- * \brief Channel mapping existence
- * A value of 0 (No channel mapping) implies that there is fixed association
- * for a channel number to a parameter entry number or, in other words,
- * PaRAM entry n corresponds to channel n.
- */
-#define CHANNEL_MAPPING_EXISTENCE               (0u)
-/** Existence of memory protection feature */
-#define MEM_PROTECTION_EXISTENCE                (0u)
-
-/** Global Register Region of CC Registers */
-#define CC_BASE_ADDRESS                         (0x01C00000u)
-/** Transfer Controller 0 Registers */
-#define TC0_BASE_ADDRESS                        (0x01C08000u)
-/** Transfer Controller 1 Registers */
-#define TC1_BASE_ADDRESS                        (0x01C08400u)
-/** Transfer Controller 2 Registers */
-#define TC2_BASE_ADDRESS                        NULL
-/** Transfer Controller 3 Registers */
-#define TC3_BASE_ADDRESS                        NULL
-/** Transfer Controller 4 Registers */
-#define TC4_BASE_ADDRESS                        NULL
-/** Transfer Controller 5 Registers */
-#define TC5_BASE_ADDRESS                        NULL
-/** Transfer Controller 6 Registers */
-#define TC6_BASE_ADDRESS                        NULL
-/** Transfer Controller 7 Registers */
-#define TC7_BASE_ADDRESS                        NULL
-
-/** Interrupt no. for Transfer Completion */
-#define XFER_COMPLETION_INT                     (8u)
-/** Interrupt no. for CC Error */
-#define CC_ERROR_INT                            (56u)
-/** Interrupt no. for TC 0 Error */
-#define TC0_ERROR_INT                           (57u)
-/** Interrupt no. for TC 1 Error */
-#define TC1_ERROR_INT                           (58u)
-/** Interrupt no. for TC 2 Error */
-#define TC2_ERROR_INT                           (0u)
-/** Interrupt no. for TC 3 Error */
-#define TC3_ERROR_INT                           (0u)
-/** Interrupt no. for TC 4 Error */
-#define TC4_ERROR_INT                           (0u)
-/** Interrupt no. for TC 5 Error */
-#define TC5_ERROR_INT                           (0u)
-/** Interrupt no. for TC 6 Error */
-#define TC6_ERROR_INT                           (0u)
-/** Interrupt no. for TC 7 Error */
-#define TC7_ERROR_INT                           (0u)
-
-/**
- * \brief Mapping of DMA channels 0-31 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                                                               /* 31     0 */
-#define DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xCF3FFFFFu)
-/**
- * EDMA channels 22, 23, 28 & 29 which correspond to GPIO bank interrupts will
- * be used for memory-to-memory data transfers, since there are no free dma
- * channels.
- */
-
-
-/**
- * \brief Mapping of DMA channels 32-63 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-/* DMA channels 32-63 DOES NOT exist in DA830. */
-#define DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x0u)
-
-
-EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
-{
-    {
-    /** Total number of DMA Channels supported by the EDMA3 Controller */
-    NUM_DMA_CHANNELS,
-    /** Total number of QDMA Channels supported by the EDMA3 Controller */
-    NUM_QDMA_CHANNELS,
-    /** Total number of TCCs supported by the EDMA3 Controller */
-    NUM_TCC,
-    /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-    NUM_PARAM_SETS,
-    /** Total number of Event Queues in the EDMA3 Controller */
-    NUM_EVENT_QUEUE,
-    /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-    NUM_TC,
-    /** Number of Regions on this EDMA3 controller */
-    NUM_REGION,
-
-    /**
-     * \brief Channel mapping existence
-     * A value of 0 (No channel mapping) implies that there is fixed association
-     * for a channel number to a parameter entry number or, in other words,
-     * PaRAM entry n corresponds to channel n.
-     */
-    CHANNEL_MAPPING_EXISTENCE,
-
-    /** Existence of memory protection feature */
-    MEM_PROTECTION_EXISTENCE,
-
-    /** Global Register Region of CC Registers */
-    (void *)(CC_BASE_ADDRESS),
-    /** Transfer Controller (TC) Registers */
-        {
-        (void *)(TC0_BASE_ADDRESS),
-        (void *)(TC1_BASE_ADDRESS),
-        (void *)(TC2_BASE_ADDRESS),
-        (void *)(TC3_BASE_ADDRESS),
-        (void *)(TC4_BASE_ADDRESS),
-        (void *)(TC5_BASE_ADDRESS),
-        (void *)(TC6_BASE_ADDRESS),
-        (void *)(TC7_BASE_ADDRESS)
-        },
-    /** Interrupt no. for Transfer Completion */
-    XFER_COMPLETION_INT,
-    /** Interrupt no. for CC Error */
-    CC_ERROR_INT,
-    /** Interrupt no. for TCs Error */
-        {
-        TC0_ERROR_INT,
-        TC1_ERROR_INT,
-        TC2_ERROR_INT,
-        TC3_ERROR_INT,
-        TC4_ERROR_INT,
-        TC5_ERROR_INT,
-        TC6_ERROR_INT,
-        TC7_ERROR_INT
-        },
-
-   /**
-     * \brief EDMA3 TC priority setting
-     *
-     * User can program the priority of the Event Queues
-     * at a system-wide level.  This means that the user can set the
-     * priority of an IO initiated by either of the TCs (Transfer Controllers)
-     * relative to IO initiated by the other bus masters on the
-     * device (ARM, DSP, USB, etc)
-     */
-        {
-        0u,
-        1u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u
-        },
-    /**
-     * \brief To Configure the Threshold level of number of events
-     * that can be queued up in the Event queues. EDMA3CC error register
-     * (CCERR) will indicate whether or not at any instant of time the
-     * number of events queued up in any of the event queues exceeds
-     * or equals the threshold/watermark value that is set
-     * in the queue watermark threshold register (QWMTHRA).
-     */
-        {
-        16u,
-        16u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u
-        },
-
-    /**
-     * \brief To Configure the Default Burst Size (DBS) of TCs.
-     * An optimally-sized command is defined by the transfer controller
-     * default burst size (DBS). Different TCs can have different
-     * DBS values. It is defined in Bytes.
-     */
-        {
-        16u,
-        16u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u
-        },
-
-    /**
-     * \brief Mapping from each DMA channel to a Parameter RAM set,
-     * if it exists, otherwise of no use.
-     */
-        {
-        0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-        /* DMA channels 32-63 DOES NOT exist in DA830. */
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
-        },
-
-     /**
-      * \brief Mapping from each DMA channel to a TCC. This specific
-      * TCC code will be returned when the transfer is completed
-      * on the mapped channel.
-      */
-        {
-        0u, 1u, 2u, 3u,
-        4u, 5u, 6u, 7u,
-        8u, 9u, 10u, 11u,
-        12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u,
-        20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        24u, 25u, 26u, 27u,
-        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31,
-        /* DMA channels 32-63 DOES NOT exist in DA830. */
-        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
-        },
-
-    /**
-     * \brief Mapping of DMA channels to Hardware Events from
-     * various peripherals, which use EDMA for data transfer.
-     * All channels need not be mapped, some can be free also.
-     */
-        {
-        DMA_CHANNEL_TO_EVENT_MAPPING_0,
-        DMA_CHANNEL_TO_EVENT_MAPPING_1
-        }
-    }
-};
-
-
-/* Default RM Instance Initialization Configuration */
-EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_REGION] =
-{
-        {
-          {
-            /* Resources owned by Region 0 */
-             /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* Resources reserved by Region 0 */
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-          },
-
-          {
-            /* Resources owned by Region 1 */
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x000000FFu},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
-
-            /* Resources reserved by Region 1 */
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* resvdDmaChannels */
-            /* 31                                        0  63                                                  32 */
-            {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31                                        0  63                                                  32 */
-            {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
-          },
-
-          {
-            /* Resources owned by Region 2 */
-             /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* Resources reserved by Region 2 */
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-          },
-
-          {
-            /* Resources owned by Region 3 */
-             /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* Resources reserved by Region 3 */
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-          }
-        }
-};
-
-/* End of File */
-
-
-
index b9e7185132d92ac65e98e9acdcdce2cc290d879b..6b33dda557c381bd4a59adda5ce5080f8d05f881 100644 (file)
@@ -1,46 +1,40 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**|                            ****                                          |**
-**|                            ****                                          |**
-**|                            ******o***                                    |**
-**|                      ********_///_****                                   |**
-**|                      ***** /_//_/ ****                                   |**
-**|                       ** ** (__/ ****                                    |**
-**|                           *********                                      |**
-**|                            ****                                          |**
-**|                            ***                                           |**
-**|                                                                          |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
-**|                        ALL RIGHTS RESERVED                               |**
-**|                                                                          |**
-**| Permission is hereby granted to licensees of Texas Instruments           |**
-**| Incorporated (TI) products to use this computer program for the sole     |**
-**| purpose of implementing a licensee product based on TI products.         |**
-**| No other rights to reproduce, use, or disseminate this computer          |**
-**| program, whether in part or in whole, are granted.                       |**
-**|                                                                          |**
-**| TI makes no representation or warranties with respect to the             |**
-**| performance of this computer program, and specifically disclaims         |**
-**| any responsibility for any damages, special or consequential,            |**
-**| connected with the use of this program.                                  |**
-**|                                                                          |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-
-/** \file   edma3_log.h
-    \brief  EDMA3 logging/tracing service
-
-    This file contains interface for EDMA3 error/event/message logging and
-    tracing service.
-
-    (C) Copyright 2006, Texas Instruments, Inc
-
-    \author     EDMA3 Architecture Team
-
-    \version    1.0 Anant Gole  Created
- */
-
+/*
+ * edma3_log.h
+ *
+ * EDMA3 logging/tracing service
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
 
 #ifndef _EDMA3_LOG_H_
 #define _EDMA3_LOG_H_
index 4e443c652459463d1ea6e52ce52980f868999e1c..c1f2010146b7ec3b83afd41415ed28aa37f1d648 100644 (file)
@@ -1,43 +1,40 @@
-/******************************************************************************
-**+-------------------------------------------------------------------------+**
-**|                            ****                                         |**
-**|                            ****                                         |**
-**|                            ******o***                                   |**
-**|                      ********_///_****                                  |**
-**|                      ***** /_//_/ ****                                  |**
-**|                       ** ** (__/ ****                                   |**
-**|                           *********                                     |**
-**|                            ****                                         |**
-**|                            ***                                          |**
-**|                                                                         |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated          |**
-**|                        ALL RIGHTS RESERVED                              |**
-**|                                                                         |**
-**| Permission is hereby granted to licensees of Texas Instruments          |**
-**| Incorporated (TI) products to use this computer program for the sole    |**
-**| purpose of implementing a licensee product based on TI products.        |**
-**| No other rights to reproduce, use, or disseminate this computer         |**
-**| program, whether in part or in whole, are granted.                      |**
-**|                                                                         |**
-**| TI makes no representation or warranties with respect to the            |**
-**| performance of this computer program, and specifically disclaims        |**
-**| any responsibility for any damages, special or consequential,           |**
-**| connected with the use of this program.                                 |**
-**|                                                                         |**
-**+-------------------------------------------------------------------------+**
-******************************************************************************/
-
-/**  \file   edma3_rl_cc.h
-       \brief  EDMA3 Channel Controller Register Desciption.
-
-        This file contains the register layer for the EDMA3 Channel Controller.
-
-    (C) Copyright 2006, Texas Instruments, Inc
-
-    \version
-                1.0     Anuj Aggarwal       - Created
-
- */
+/*
+ * edma3_rl_cc.h
+ *
+ * EDMA3 Channel Controller Register Desciption.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
 
 #ifndef _EDMA3_RL_CC_H_
 #define _EDMA3_RL_CC_H_
index 6a937397ba74fef02109a41fff9d4ca2fcf2eae5..0e6cb91a5d650e5dfdb0296d7e8ea71c45c826d2 100644 (file)
@@ -1,43 +1,40 @@
-/******************************************************************************
-**+-------------------------------------------------------------------------+**
-**|                            ****                                         |**
-**|                            ****                                         |**
-**|                            ******o***                                   |**
-**|                      ********_///_****                                  |**
-**|                      ***** /_//_/ ****                                  |**
-**|                       ** ** (__/ ****                                   |**
-**|                           *********                                     |**
-**|                            ****                                         |**
-**|                            ***                                          |**
-**|                                                                         |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated          |**
-**|                        ALL RIGHTS RESERVED                              |**
-**|                                                                         |**
-**| Permission is hereby granted to licensees of Texas Instruments          |**
-**| Incorporated (TI) products to use this computer program for the sole    |**
-**| purpose of implementing a licensee product based on TI products.        |**
-**| No other rights to reproduce, use, or disseminate this computer         |**
-**| program, whether in part or in whole, are granted.                      |**
-**|                                                                         |**
-**| TI makes no representation or warranties with respect to the            |**
-**| performance of this computer program, and specifically disclaims        |**
-**| any responsibility for any damages, special or consequential,           |**
-**| connected with the use of this program.                                 |**
-**|                                                                         |**
-**+-------------------------------------------------------------------------+**
-******************************************************************************/
-
-/**  \file   edma3_rl_tc.h
-       \brief  EDMA3 Transfer Controller Register Desciption.
-
-        This file contains the register layer for the EDMA3 Transfer Controller.
-
-    (C) Copyright 2006, Texas Instruments, Inc
-
-    \version
-                1.0     Anuj Aggarwal       - Created
-
- */
+/*
+ * edma3_rl_tc.h
+ *
+ * EDMA3 Transfer Controller Register Desciption.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
 
 #ifndef _EDMA3_RL_TC_H_
 #define _EDMA3_RL_TC_H_
index 81829f78df8c1386ac961740dcc29ccb94af0302..91355858052bf6e1a8e630116744c1fd2921d5b6 100644 (file)
@@ -1,42 +1,40 @@
-/******************************************************************************
-**+-------------------------------------------------------------------------+**
-**|                            ****                                         |**
-**|                            ****                                         |**
-**|                            ******o***                                   |**
-**|                      ********_///_****                                  |**
-**|                      ***** /_//_/ ****                                  |**
-**|                       ** ** (__/ ****                                   |**
-**|                           *********                                     |**
-**|                            ****                                         |**
-**|                            ***                                          |**
-**|                                                                         |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated          |**
-**|                        ALL RIGHTS RESERVED                              |**
-**|                                                                         |**
-**| Permission is hereby granted to licensees of Texas Instruments          |**
-**| Incorporated (TI) products to use this computer program for the sole    |**
-**| purpose of implementing a licensee product based on TI products.        |**
-**| No other rights to reproduce, use, or disseminate this computer         |**
-**| program, whether in part or in whole, are granted.                      |**
-**|                                                                         |**
-**| TI makes no representation or warranties with respect to the            |**
-**| performance of this computer program, and specifically disclaims        |**
-**| any responsibility for any damages, special or consequential,           |**
-**| connected with the use of this program.                                 |**
-**|                                                                         |**
-**+-------------------------------------------------------------------------+**
-******************************************************************************/
-
-/** \file       edma3_rm_gbl_data.c
-    \brief      Source file for the Resource Manager, for internal
-                data structures.
-
-    (C) Copyright 2006, Texas Instruments, Inc
-
-    \version
-                0.1.0     Anuj Aggarwal     - Created
-
- */
+/*
+ * edma3_rm_gbl_data.c
+ *
+ * Source file for the Resource Manager, for internal data structures.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
 
 /* Resource Manager Internal Header Files */
 #include <ti/sdo/edma3/rm/src/edma3resmgr.h>
index dee4915192e26174ec4bcfc3b2b60929b8c988a3..94c4ae9686a0f49363072c20d9d7de71066f37a1 100644 (file)
@@ -1,40 +1,40 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**|                            ****                                          |**
-**|                            ****                                          |**
-**|                            ******o***                                    |**
-**|                      ********_///_****                                   |**
-**|                      ***** /_//_/ ****                                   |**
-**|                       ** ** (__/ ****                                    |**
-**|                           *********                                      |**
-**|                            ****                                          |**
-**|                            ***                                           |**
-**|                                                                          |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
-**|                        ALL RIGHTS RESERVED                               |**
-**|                                                                          |**
-**| Permission is hereby granted to licensees of Texas Instruments           |**
-**| Incorporated (TI) products to use this computer program for the sole     |**
-**| purpose of implementing a licensee product based on TI products.         |**
-**| No other rights to reproduce, use, or disseminate this computer          |**
-**| program, whether in part or in whole, are granted.                       |**
-**|                                                                          |**
-**| TI makes no representation or warranties with respect to the             |**
-**| performance of this computer program, and specifically disclaims         |**
-**| any responsibility for any damages, special or consequential,            |**
-**| connected with the use of this program.                                  |**
-**|                                                                          |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/** \file       edma3resmgr.c
-    \brief      EDMA3 Controller Resource Manager Interface Implementation
-
-    This file contains Resource Manager Implementation for the EDMA3 Controller.
-
-    (C) Copyright 2006, Texas Instruments, Inc
-
- */
+/*
+ * edma3resmgr.c
+ *
+ * EDMA3 Controller Resource Manager Interface Implementation
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
 
 /* Resource Manager Internal Header Files */
 #include <ti/sdo/edma3/rm/src/edma3resmgr.h>
@@ -136,7 +136,18 @@ extern EDMA3_RM_InstanceInitConfig *ptrInitCfgArray;
 extern EDMA3_RM_Instance *resMgrInstance;
 extern EDMA3_RM_Instance *ptrRMIArray;
 
-
+/** Max of DMA Channels */
+unsigned int edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Min of Link Channels */
+unsigned int edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Max of Link Channels */
+unsigned int edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Min of QDMA Channels */
+unsigned int edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Max of QDMA Channels */
+unsigned int edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+/** Max of Logical Channels */
+unsigned int edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
 
 /* Globals */
 /*---------------------------------------------------------------------------*/
@@ -158,7 +169,7 @@ EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];
  * scenario, this DMA channel <-> TCC mapping will be used to point to
  * the correct callback function.
  */
-static unsigned int edma3DmaChTccMapping [EDMA3_MAX_DMA_CH];
+static unsigned int edma3DmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_DMA_CH];
 
 
 /**
@@ -170,7 +181,7 @@ static unsigned int edma3DmaChTccMapping [EDMA3_MAX_DMA_CH];
  * scenario, this QDMA channel <-> TCC mapping will be used to point to
  * the correct callback function.
  */
-static unsigned int edma3QdmaChTccMapping [EDMA3_MAX_QDMA_CH];
+static unsigned int edma3QdmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_QDMA_CH];
 
 
 /**
@@ -178,7 +189,7 @@ static unsigned int edma3QdmaChTccMapping [EDMA3_MAX_QDMA_CH];
  * against a particular TCC. Used to call the callback
  * functions linked to the particular channel.
  */
-static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_TCC];
+static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TCC];
 
 
 /** edma3RegionId will be updated ONCE using the parameter regionId passed to
@@ -190,11 +201,13 @@ static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_TCC];
  */
 static EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS;
 
-/** masterExists will be updated when the Master RM Instance modifies the
+/** masterExists[] will be updated when the Master RM Instance modifies the
  * Global EDMA3 configuration registers. It is used to prevent any other
  * Master RM Instance creation.
+ * masterExists[] is per EDMA3 hardware, hence it is created
+ * as an array.
  */
-static unsigned short masterExists = FALSE;
+static unsigned short masterExists [EDMA3_MAX_EDMA3_INSTANCES] = {FALSE,FALSE,FALSE};
 
 /**
  * Number of PaRAM Sets actually present on the SoC. This will be updated
@@ -207,7 +220,12 @@ unsigned int edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS;
  * The list of Interrupt Channels which get allocated while requesting the
  * TCC. It will be used while checking the IPR/IPRH bits in the RM ISR.
  */
-static unsigned int allocatedTCCs[2u] = {0x0u, 0x0u};
+static unsigned int allocatedTCCs[EDMA3_MAX_EDMA3_INSTANCES][2u] =
+                                                                                       {
+                                                                                       {0x0u, 0x0u},
+                                                                                       {0x0u, 0x0u},
+                                                                                       {0x0u, 0x0u},
+                                                                                       };
 
 
 /**
@@ -281,8 +299,8 @@ static void edma3CCErrHandler (const EDMA3_RM_Obj *rmObj);
 static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum);
 
 
-/** Local MemSet function */
-void edma3MemSet(void *dst, unsigned char data, unsigned int len);
+/** Local MemZero function */
+void edma3MemZero(void *dst, unsigned int len);
 /** Local MemCpy function */
 void edma3MemCpy(void *dst, const void *src, unsigned int len);
 /* Local MemCopy function to copy Param Set ONLY */
@@ -398,8 +416,11 @@ EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
         /* Initialize the global variables for the first time */
         if (FALSE == rmInitDone)
             {
-            edma3MemSet((void *)&(resMgrObj[count]) , 0x00u,
-                        sizeof(resMgrObj));
+            edma3MemZero((void *)&(resMgrObj[count]),
+                               sizeof(resMgrObj));
+            edma3MemZero((void *)(&(edma3IntrParams[0u])),
+                sizeof(edma3IntrParams));
+
             rmInitDone = TRUE;
             }
 
@@ -445,9 +466,16 @@ EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
 
 
             /**
-             * Update the actual number of PaRAM sets.
+             * Update the actual number of PaRAM sets and
+             * Initialize Boundary Values for Logical Channel Ranges.
              */
             edma3NumPaRAMSets = resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets;
+                       edma3_dma_ch_max_val[phyCtrllerInstId] = resMgrObj[phyCtrllerInstId].gblCfgParams.numDmaChannels - 1u;
+                       edma3_link_ch_min_val[phyCtrllerInstId] = edma3_dma_ch_max_val[phyCtrllerInstId] + 1u;
+                       edma3_link_ch_max_val[phyCtrllerInstId] = edma3_link_ch_min_val[phyCtrllerInstId] + resMgrObj[phyCtrllerInstId].gblCfgParams.numPaRAMSets - 1u;
+                       edma3_qdma_ch_min_val[phyCtrllerInstId] = edma3_link_ch_max_val[phyCtrllerInstId] + 1u;
+                       edma3_qdma_ch_max_val[phyCtrllerInstId] = edma3_qdma_ch_min_val[phyCtrllerInstId] + resMgrObj[phyCtrllerInstId].gblCfgParams.numQdmaChannels - 1u;
+                       edma3_log_ch_max_val[phyCtrllerInstId] = edma3_qdma_ch_max_val[phyCtrllerInstId];
 
             resMgrObj[phyCtrllerInstId].phyCtrllerInstId = phyCtrllerInstId;
             resMgrObj[phyCtrllerInstId].state = EDMA3_RM_CREATED;
@@ -456,13 +484,11 @@ EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
             /* Make all the RM instances for this EDMA3 HW NULL */
             for (count = 0u; count < EDMA3_MAX_RM_INSTANCES; count++)
                 {
-                edma3MemSet((void *)((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count),
-                            0x00u,
+                edma3MemZero((void *)((EDMA3_RM_Instance *)(ptrRMIArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count),
                             sizeof(EDMA3_RM_Instance));
 
                 /* Also make this data structure NULL */
-                edma3MemSet((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count),
-                            0x00u,
+                edma3MemZero((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + count),
                             sizeof(EDMA3_RM_InstanceInitConfig));
                 }
 
@@ -472,7 +498,7 @@ EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
                     count++
                 )
                 {
-                edma3DmaChTccMapping[count] = EDMA3_MAX_TCC;
+                edma3DmaChTccMapping[phyCtrllerInstId][count] = EDMA3_MAX_TCC;
                 }
 
             /* Initialize the global edma3QdmaChTccMapping array with EDMA3_MAX_TCC */
@@ -481,14 +507,9 @@ EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
                     count++
                 )
                 {
-                edma3QdmaChTccMapping[count] = EDMA3_MAX_TCC;
+                edma3QdmaChTccMapping[phyCtrllerInstId][count] = EDMA3_MAX_TCC;
                 }
 
-            /* Make the global edma3IntrParams array for interrupts NULL */
-            edma3MemSet((void *)(&(edma3IntrParams[0u])), 0x00u,
-                sizeof(edma3IntrParams));
-
-
             /* Reset edma3RmChBoundRes Array*/
             for (count = 0u; count < EDMA3_MAX_LOGICAL_CH; count++)
                 {
@@ -497,7 +518,7 @@ EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
                 }
 
             /* Make the contiguousParamRes array NULL */
-            edma3MemSet((void *)(&(contiguousParamRes[0u])), 0x00u,
+            edma3MemZero((void *)(&(contiguousParamRes[0u])),
                 sizeof(contiguousParamRes));
 
 
@@ -590,12 +611,11 @@ EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId,
                 resMgrObj[phyCtrllerInstId].state = EDMA3_RM_DELETED;
 
                 /* Reset the Allocated TCCs Array also. */
-                allocatedTCCs[0u] = 0x0u;
-                allocatedTCCs[1u] = 0x0u;
+                allocatedTCCs[phyCtrllerInstId][0u] = 0x0u;
+                allocatedTCCs[phyCtrllerInstId][1u] = 0x0u;
 
                 /* Also, reset the RM Object Global Config Info */
-                edma3MemSet((void *)&(resMgrObj[phyCtrllerInstId].gblCfgParams),
-                         0x00u,
+                edma3MemZero((void *)&(resMgrObj[phyCtrllerInstId].gblCfgParams),
                          sizeof(EDMA3_RM_GblConfigParams));
                 }
             }
@@ -654,7 +674,6 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
     unsigned int paramSetDwrds = 0u;
     unsigned int tccDwrds = 0u;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
-    unsigned int mappedPaRAMId;
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_RM_PARAM_CHECK_DISABLE
@@ -687,7 +706,9 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
                 }
             else
                 {
-                edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);
+                edma3OsProtectEntry (phyCtrllerInstId,
+                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       &intState);
 
                 /** Check state of RM Object.
                   * If no RM instance is opened and this is the first one,
@@ -698,7 +719,9 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
                     (rmObj->state != EDMA3_RM_CLOSED)))
                     {
                     result = EDMA3_RM_E_INVALID_STATE;
-                    edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
+                    edma3OsProtectExit (phyCtrllerInstId,
+                                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                                               intState);
                     }
                 else
                     {
@@ -711,7 +734,9 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
                         && (rmObj->state != EDMA3_RM_OPENED))
                         {
                         result = EDMA3_RM_E_INVALID_STATE;
-                        edma3OsProtectExit(EDMA3_OS_PROTECT_INTERRUPT,intState);
+                           edma3OsProtectExit (phyCtrllerInstId,
+                                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                                       intState);
                         }
                     else
                         {
@@ -719,8 +744,9 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
                         if (rmObj->numOpens >= EDMA3_MAX_RM_INSTANCES)
                             {
                             result = EDMA3_RM_E_MAX_RM_INST_OPENED;
-                            edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT,
-                                                 intState);
+                                   edma3OsProtectExit (phyCtrllerInstId,
+                                                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                                                               intState);
                             }
                         }
                     }
@@ -736,11 +762,13 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
         * or not. There should NOT be more than 1 master.
         * Return error code if master already exists
         */
-        if ((TRUE == masterExists) && (TRUE == initParam->isMaster))
+        if ((TRUE == masterExists[phyCtrllerInstId]) && (TRUE == initParam->isMaster))
             {
             /* No two masters should exist, return error */
             result = EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS;
-            edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
+            edma3OsProtectExit (phyCtrllerInstId,
+                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                               intState);
             }
         else
             {
@@ -759,8 +787,7 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
                         rmInstance = temp_ptr_rm_inst;
 
                         /* Also make this data structure NULL, just for safety. */
-                        edma3MemSet((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx),
-                                    0x00u,
+                        edma3MemZero((void *)((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx),
                                     sizeof(EDMA3_RM_InstanceInitConfig));
 
                         break;
@@ -772,7 +799,9 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
             if (NULL == rmInstance)
                 {
                 result = EDMA3_RM_E_MAX_RM_INST_OPENED;
-                edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
+                edma3OsProtectExit (phyCtrllerInstId,
+                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       intState);
                 }
             else
                 {
@@ -819,8 +848,25 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
                                 ((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);
 
                     dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32u;
+                                       if (dmaChDwrds == 0)
+                                               {
+                                               /* In case DMA channels are < 32 */
+                                               dmaChDwrds = 1;
+                                               }
+
                     paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32u;
+                                       if (paramSetDwrds == 0)
+                                               {
+                                               /* In case PaRAM Sets are < 32 */
+                                               paramSetDwrds = 1;
+                                               }
+
                     tccDwrds = rmObj->gblCfgParams.numTccs / 32u;
+                                       if (tccDwrds == 0)
+                                               {
+                                               /* In case TCCs are < 32 */
+                                               tccDwrds = 1;
+                                               }
 
                     for (resMgrIdx = 0u; resMgrIdx < dmaChDwrds; ++resMgrIdx)
                         {
@@ -881,7 +927,7 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
                         {
                         /* Store the region id to use it in the ISRs */
                         edma3RegionId = rmInstance->initParam.regionId;
-                        masterExists = TRUE;
+                        masterExists[phyCtrllerInstId] = TRUE;
                         }
 
                     if (TRUE == initParam->regionInitEnable)
@@ -923,7 +969,9 @@ EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
                     result = EDMA3_RM_E_INVALID_PARAM;
                     }
 
-                edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
+                edma3OsProtectExit (phyCtrllerInstId,
+                                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                                       intState);
                 }
             }
         }
@@ -1013,33 +1061,37 @@ EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr,
 
                 /**
                  * If this is the Master Instance, reset the static variable
-                 * 'masterExists'.
+                 * 'masterExists[]'.
                  */
                 if (TRUE == rmInstance->initParam.isMaster)
                     {
-                    masterExists = FALSE;
+                    masterExists[rmObj->phyCtrllerInstId] = FALSE;
                     edma3RegionId = EDMA3_MAX_REGIONS;
                     }
 
                 /* Reset the Initparam for this RM Instance */
-                edma3MemSet((void *)&(rmInstance->initParam) , 0x00u,
+                edma3MemZero((void *)&(rmInstance->initParam),
                                             sizeof(EDMA3_RM_Param));
 
                 /* Critical section starts */
-                edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);
+                edma3OsProtectEntry (rmObj->phyCtrllerInstId,
+                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                       &intState);
 
                 /* Decrease the Number of Opens */
                 --rmObj->numOpens;
                 if (NULL == rmObj->numOpens)
                     {
-                    edma3MemSet((void *)&(edma3RmChBoundRes[rmObj->phyCtrllerInstId]), 0x00u,
-                                            sizeof(edma3RmChBoundRes));
+                    edma3MemZero((void *)&(edma3RmChBoundRes[rmObj->phyCtrllerInstId]),
+                                            sizeof(edma3RmChBoundRes[rmObj->phyCtrllerInstId]));
 
                     rmObj->state = EDMA3_RM_CLOSED;
                     }
 
                 /* Critical section ends */
-                edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
+                edma3OsProtectExit (rmObj->phyCtrllerInstId,
+                                                       EDMA3_OS_PROTECT_INTERRUPT,
+                                                       intState);
 
                 rmInstance->pResMgrObjHandle = NULL;
                 rmInstance->shadowRegs = NULL;
@@ -1580,8 +1632,7 @@ EDMA3_RM_Result EDMA3_RM_allocResource(EDMA3_RM_Handle hEdmaResMgr,
                                     if ((TRUE == rmInstance->regModificationRequired)
                                         && (TRUE == rmInstance->paramInitRequired))
                                         {
-                                        edma3MemSet((void *)(&gblRegs->PARAMENTRY[avlblIdx]),
-                                                    0x00u,
+                                        edma3MemZero((void *)(&gblRegs->PARAMENTRY[avlblIdx]),
                                                     sizeof(gblRegs->PARAMENTRY[avlblIdx]));
                                         }
 
@@ -1615,8 +1666,7 @@ EDMA3_RM_Result EDMA3_RM_allocResource(EDMA3_RM_Handle hEdmaResMgr,
                                         if ((TRUE == rmInstance->regModificationRequired)
                                             && (TRUE == rmInstance->paramInitRequired))
                                             {
-                                            edma3MemSet((void *)(&gblRegs->PARAMENTRY[resId]),
-                                                        0x00u,
+                                            edma3MemZero((void *)(&gblRegs->PARAMENTRY[resId]),
                                                         sizeof(gblRegs->PARAMENTRY[resId]));
                                             }
 
@@ -1753,7 +1803,9 @@ EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr,
 
             resIdSet = 1u << (resId%32u);
 
-            edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);
+            edma3OsProtectEntry (rmObj->phyCtrllerInstId,
+                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                               &intState);
 
             if (EDMA3_RM_SOK == result)
                 {
@@ -1976,7 +2028,9 @@ EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr,
 
                 }
 
-            edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
+            edma3OsProtectExit (rmObj->phyCtrllerInstId,
+                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                               intState);
             }
         }
 
@@ -2086,7 +2140,7 @@ EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
     int paRAMId = (int)EDMA3_RM_RES_ANY;
     volatile EDMA3_CCRL_Regs *gblRegs = NULL;
     unsigned int qdmaChId = EDMA3_MAX_PARAM_SETS;
-
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -2156,6 +2210,7 @@ EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
 
     if (result == EDMA3_RM_SOK)
         {
+        edma3Id = rmObj->phyCtrllerInstId;
         gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
 
         switch (chObj->type)
@@ -2230,7 +2285,7 @@ EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
                     }
                 else
                     {
-                    if (chObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL)
+                    if (chObj->resId <= edma3_dma_ch_max_val[edma3Id])
                         {
                         /* Request for a specific DMA channel */
                         resObj.type = EDMA3_RM_RES_DMA_CHANNEL;
@@ -2319,7 +2374,7 @@ EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
                         chObj->resId = resObj.resId;
 
                         /* Save the Logical-QDMA channel id for future use. */
-                        qdmaChId = resObj.resId + EDMA3_RM_QDMA_CH_MIN_VAL;
+                        qdmaChId = resObj.resId + edma3_qdma_ch_min_val[edma3Id];
 
                         /**
                          * Check the PaRAM Set user has specified for this QDMA channel.
@@ -2334,7 +2389,7 @@ EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
                     }
                 else
                     {
-                    if (chObj->resId < EDMA3_MAX_QDMA_CH)
+                    if (chObj->resId < rmObj->gblCfgParams.numQdmaChannels)
                         {
                         /* Request for a specific QDMA channel */
                         resObj.type = EDMA3_RM_RES_QDMA_CHANNEL;
@@ -2344,7 +2399,7 @@ EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
                         if (result == EDMA3_RM_SOK)
                             {
                             /* Save the Logical-QDMA channel id for future use. */
-                            qdmaChId = chObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL;
+                            qdmaChId = chObj->resId + edma3_qdma_ch_min_val[edma3Id];
 
                             /**
                              * Check the PaRAM Set user has specified for this QDMA channel.
@@ -2396,7 +2451,7 @@ EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
 
                         if (result == EDMA3_RM_SOK)
                             {
-                            unsigned int linkCh = EDMA3_RM_LINK_CH_MIN_VAL;
+                            unsigned int linkCh = edma3_link_ch_min_val[edma3Id];
 
                             /* Return the actual PaRAM Id. */
                             chObj->resId = resObj.resId;
@@ -2407,14 +2462,14 @@ EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
                             * It will be used for future operations on the Link channel.
                             */
                             while ((edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId != -1)
-                                        && (linkCh <= EDMA3_RM_LINK_CH_MAX_VAL))
+                                        && (linkCh <= edma3_link_ch_max_val[edma3Id]))
                                 {
                                 /* Move to the next place-holder. */
                                 linkCh++;
                                 }
 
                             /* Verify the returned handle, it should lie in the correct range */
-                            if (linkCh > EDMA3_RM_LINK_CH_MAX_VAL)
+                            if (linkCh > edma3_link_ch_max_val[edma3Id])
                                 {
                                 result = EDMA3_RM_E_INVALID_PARAM;
 
@@ -2714,6 +2769,7 @@ EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr,
     unsigned int qdmaChId;
     unsigned int dmaChId;
     EDMA3_RM_InstanceInitConfig *rmConfig = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -2762,6 +2818,7 @@ EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr,
                 }
             else
                 {
+                edma3Id = rmObj->phyCtrllerInstId;
                 globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
                 }
             }
@@ -2887,7 +2944,7 @@ EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr,
                  * So we have to convert it to make the logical
                  * QDMA channel id first.
                  */
-                qdmaChId = chObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL;
+                qdmaChId = chObj->resId + edma3_qdma_ch_min_val[edma3Id];
 
                 /**
                  * Validate QDMA channel id first.
@@ -2989,12 +3046,12 @@ EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr,
                     if (result == EDMA3_RM_SOK)
                         {
                         /* PaRAM Set freed successfully. */
-                        unsigned int linkCh = EDMA3_RM_LINK_CH_MIN_VAL;
+                        unsigned int linkCh = edma3_link_ch_min_val[edma3Id];
 
                         /* Reset the Logical-Link channel */
                         /* Search for the Logical-Link channel first */
-                        for (linkCh = EDMA3_RM_LINK_CH_MIN_VAL;
-                                linkCh < EDMA3_RM_LINK_CH_MAX_VAL;
+                        for (linkCh = edma3_link_ch_min_val[edma3Id];
+                                linkCh < edma3_link_ch_max_val[edma3Id];
                                 linkCh++)
                             {
                             if (edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId == chObj->resId)
@@ -3498,9 +3555,6 @@ EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr,
     return result;
     }
 
-
-
-
 /**
  * \fn      EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle
  *          hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj);
@@ -3710,7 +3764,7 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
     volatile EDMA3_CCRL_Regs *gblRegs = NULL;
     unsigned int i = 0u;
     unsigned int position = 0u;
-
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -3750,7 +3804,8 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
 
     if (EDMA3_RM_SOK == result)
         {
-     gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+        edma3Id = rmObj->phyCtrllerInstId;
+               gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
 
         if (rmInstance->initParam.rmSemHandle == NULL)
             {
@@ -4047,8 +4102,7 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
                                          */
                                         if (TRUE == rmInstance->paramInitRequired)
                                             {
-                                            edma3MemSet((void *)(&gblRegs->PARAMENTRY[resAllocIdx]),
-                                                        0x00u,
+                                            edma3MemZero((void *)(&gblRegs->PARAMENTRY[resAllocIdx]),
                                                         sizeof(gblRegs->PARAMENTRY[resAllocIdx]));
                                             }
 
@@ -4837,6 +4891,7 @@ EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
     int paRAMId = 0u;
     unsigned int qdmaChId = 0u;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -4887,18 +4942,18 @@ EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
             }
         }
 
-
     if (result == EDMA3_RM_SOK)
         {
+        edma3Id = rmObj->phyCtrllerInstId;
         globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
 
         switch (lChObj->type)
             {
             case EDMA3_RM_RES_DMA_CHANNEL:
                 {
-                if (lChObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL)
+                if (lChObj->resId <= edma3_dma_ch_max_val[edma3Id])
                     {
-                    paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][lChObj->resId].paRAMId;
+                    paRAMId = edma3RmChBoundRes[edma3Id][lChObj->resId].paRAMId;
                     }
                 else
                     {
@@ -4911,8 +4966,8 @@ EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
                 {
                 if (lChObj->resId < EDMA3_MAX_QDMA_CH)
                     {
-                    qdmaChId = lChObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL;
-                    paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;
+                    qdmaChId = lChObj->resId + edma3_qdma_ch_min_val[edma3Id];
+                    paRAMId = edma3RmChBoundRes[edma3Id][qdmaChId].paRAMId;
                     }
                 else
                     {
@@ -5000,6 +5055,7 @@ EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
     int paRAMId = 0u;
     unsigned int qdmaChId = 0u;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -5052,13 +5108,14 @@ EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
 
     if (result == EDMA3_RM_SOK)
         {
+        edma3Id = rmObj->phyCtrllerInstId;
         globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
 
         switch (lChObj->type)
             {
             case EDMA3_RM_RES_DMA_CHANNEL:
                 {
-                if (lChObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL)
+                if (lChObj->resId <= edma3_dma_ch_max_val[edma3Id])
                     {
                     paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][lChObj->resId].paRAMId;
                     }
@@ -5073,7 +5130,7 @@ EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
                 {
                 if (lChObj->resId < EDMA3_MAX_QDMA_CH)
                     {
-                    qdmaChId = lChObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL;
+                    qdmaChId = lChObj->resId + edma3_qdma_ch_min_val[edma3Id];
                     paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;
                     }
                 else
@@ -5172,6 +5229,7 @@ EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
     int paRAMId = 0u;
     unsigned int qdmaChId = 0u;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -5224,15 +5282,16 @@ EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
 
     if (result == EDMA3_RM_SOK)
         {
-        globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
+               edma3Id = rmObj->phyCtrllerInstId;
+               globalRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
 
         switch (lChObj->type)
             {
             case EDMA3_RM_RES_DMA_CHANNEL:
                 {
-                if (lChObj->resId <= EDMA3_RM_DMA_CH_MAX_VAL)
+                if (lChObj->resId <= edma3_dma_ch_max_val[edma3Id])
                     {
-                    paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][lChObj->resId].paRAMId;
+                    paRAMId = edma3RmChBoundRes[edma3Id][lChObj->resId].paRAMId;
                     }
                 else
                     {
@@ -5245,8 +5304,8 @@ EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
                 {
                 if (lChObj->resId < EDMA3_MAX_QDMA_CH)
                     {
-                    qdmaChId = lChObj->resId + EDMA3_RM_QDMA_CH_MIN_VAL;
-                    paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;
+                    qdmaChId = lChObj->resId + edma3_qdma_ch_min_val[edma3Id];
+                    paRAMId = edma3RmChBoundRes[edma3Id][qdmaChId].paRAMId;
                     }
                 else
                     {
@@ -5697,8 +5756,8 @@ EDMA3_RM_Result EDMA3_RM_Ioctl(
 
                                /* If parameter checking is enabled... */
 #ifndef EDMA3_RM_PARAM_CHECK_DISABLE
-                if ((regModificationRequired == 0u)
-                    || (regModificationRequired == 1u))
+                if ((regModificationRequired != 0u)
+                    && (regModificationRequired != 1u))
                     {
                     /* All other values are invalid. */
                     result = EDMA3_RM_E_INVALID_PARAM;
@@ -5783,6 +5842,7 @@ static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
     volatile unsigned int pendingIrqs;
     unsigned int indexl;
     unsigned int indexh;
+       unsigned int edma3Id;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -5794,6 +5854,7 @@ static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
 
     assert (NULL != rmObj);
 
+    edma3Id = rmObj->phyCtrllerInstId;
     ptrEdmaccRegs =
             (volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs;
     if (ptrEdmaccRegs != NULL)
@@ -5818,7 +5879,9 @@ static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
          * channels are owned by the EDMA3 RM Instances.
          */
 
-        edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION, NULL);
+        edma3OsProtectEntry (edma3Id,
+                                               EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
+                                               NULL);
 
         /* Loop for EDMA3_RM_COMPL_HANDLER_RETRY_COUNT number of time,
                   breaks when no pending interrupt is found */
@@ -5832,7 +5895,7 @@ static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
              * Choose interrupts coming from our allocated TCCs
              * and MASK remaining ones.
              */
-            pendingIrqs = (pendingIrqs & allocatedTCCs[0u]);
+            pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][0u]);
 
             while (pendingIrqs)
                 {
@@ -5844,14 +5907,14 @@ static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
                      * while requesting the TCC, its TCC specific bit
                      * in the IPR register will NOT be cleared.
                      */
-                    if(edma3IntrParams[indexl].tccCb != NULL)
+                    if(edma3IntrParams[edma3Id][indexl].tccCb != NULL)
                         {
                          /* here write to ICR to clear the corresponding IPR bits*/
                         shadowRegs->ICR = (1u << indexl);
 
-                        edma3IntrParams[indexl].tccCb (indexl,
+                        edma3IntrParams[edma3Id][indexl].tccCb (indexl,
                                     EDMA3_RM_XFER_COMPLETE,
-                                    edma3IntrParams[indexl].cbData);
+                                    edma3IntrParams[edma3Id][indexl].cbData);
                         }
                     }
                 ++indexl;
@@ -5865,7 +5928,7 @@ static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
              * Choose interrupts coming from our allocated TCCs
              * and MASK remaining ones.
              */
-            pendingIrqs = (pendingIrqs & allocatedTCCs[1u]);
+            pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][1u]);
 
             while (pendingIrqs)
                 {
@@ -5877,14 +5940,14 @@ static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
                      * while requesting the TCC, its TCC specific bit
                      * in the IPRH register will NOT be cleared.
                      */
-                    if(edma3IntrParams[32u+indexh].tccCb!=NULL)
+                    if(edma3IntrParams[edma3Id][32u+indexh].tccCb!=NULL)
                         {
                          /* here write to ICR to clear the corresponding IPR bits*/
                         shadowRegs->ICRH = (1u << indexh);
 
-                        edma3IntrParams[32u+indexh].tccCb(32u+indexh,
+                        edma3IntrParams[edma3Id][32u+indexh].tccCb(32u+indexh,
                                     EDMA3_RM_XFER_COMPLETE,
-                                    edma3IntrParams[32u+indexh].cbData);
+                                    edma3IntrParams[edma3Id][32u+indexh].cbData);
                         }
                     }
                 ++indexh;
@@ -5894,15 +5957,17 @@ static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
             Cnt++;
             }
 
-        indexl = (shadowRegs->IPR & allocatedTCCs[0u]);
-        indexh = (shadowRegs->IPRH & allocatedTCCs[1u]);
+        indexl = (shadowRegs->IPR & allocatedTCCs[edma3Id][0u]);
+        indexh = (shadowRegs->IPRH & allocatedTCCs[edma3Id][1u]);
 
         if((indexl !=0 ) || (indexh !=0 ))
             {
             shadowRegs->IEVAL=0x1u;
             }
 
-        edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION, NULL);
+        edma3OsProtectExit (rmObj->phyCtrllerInstId,
+                                                       EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
+                                                       NULL);
         }
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
@@ -5914,11 +5979,11 @@ static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
     }
 
-/* ARGSUSED */
-void lisrEdma3ComplHandler0(unsigned int arg)
+
+void lisrEdma3ComplHandler0(unsigned int edma3InstanceId)
     {
     /* Invoke Completion Handler ISR */
-    edma3ComplHandler(&resMgrObj[0]);
+    edma3ComplHandler(&resMgrObj[edma3InstanceId]);
     }
 
 
@@ -5941,7 +6006,7 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
     unsigned int index;
     unsigned int evtqueNum;
     EDMA3_RM_Instance *rm_instance = NULL;
-    unsigned int hwId;
+    unsigned int edma3Id;
     unsigned int num_rm_instances_opened;
     EDMA3_RM_Instance *rmInstance   = NULL;
     unsigned int ownedDmaError = 0;
@@ -5958,13 +6023,13 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
 
     assert (rmObj != NULL);
 
+    edma3Id = rmObj->phyCtrllerInstId;
     ptrEdmaccRegs = (volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs;
     if (ptrEdmaccRegs != NULL)
         {
         shadowRegs = (volatile EDMA3_CCRL_ShadowRegs *)&ptrEdmaccRegs->SHADOW[edma3RegionId];
-        hwId = rmObj->phyCtrllerInstId;
         rmInstance = ((EDMA3_RM_Instance *)(ptrRMIArray)
-                            + ((rmObj->phyCtrllerInstId)*EDMA3_MAX_RM_INSTANCES)
+                            + (edma3Id*EDMA3_MAX_RM_INSTANCES)
                             + edma3RegionId);
 
         pendingIrqs = 0u;
@@ -5975,7 +6040,9 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
             || ((ptrEdmaccRegs->QEMR != 0)
             || (ptrEdmaccRegs->CCERR != 0)))
             {
-            edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, NULL);
+            edma3OsProtectEntry (edma3Id,
+                                                               EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
+                                                               NULL);
 
             /* Loop for EDMA3_RM_CCERR_HANDLER_RETRY_COUNT number of time,
                           breaks when no pending interrupt is found */
@@ -5997,7 +6064,7 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
                          * channel), fetch the corresponding TCC
                          * value, mapped to this DMA channel.
                          */
-                        mappedTcc = edma3DmaChTccMapping[index];
+                        mappedTcc = edma3DmaChTccMapping[edma3Id][index];
 
                         /**
                          * Ensure that the mapped tcc is valid and the call
@@ -6014,12 +6081,12 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
                             shadowRegs->SECR = (1u<<index);
 
                             /* Call the callback function if registered earlier. */
-                            if((edma3IntrParams[mappedTcc].tccCb) != NULL)
+                            if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
                                 {
-                                edma3IntrParams[mappedTcc].tccCb (
+                                edma3IntrParams[edma3Id][mappedTcc].tccCb (
                                         mappedTcc,
                                         EDMA3_RM_E_CC_DMA_EVT_MISS,
-                                        edma3IntrParams[mappedTcc].cbData
+                                        edma3IntrParams[edma3Id][mappedTcc].cbData
                                         );
                                 }
                             }
@@ -6057,7 +6124,7 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
                          * channel), fetch the corresponding TCC
                          * value, mapped to this DMA channel.
                          */
-                        mappedTcc = edma3DmaChTccMapping[32u+index];
+                        mappedTcc = edma3DmaChTccMapping[edma3Id][32u+index];
 
                         /**
                          * Ensure that the mapped tcc is valid and the call
@@ -6074,12 +6141,12 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
                             shadowRegs->SECRH = (1u<<index);
 
                             /* Call the callback function if registered earlier. */
-                            if((edma3IntrParams[mappedTcc].tccCb) != NULL)
+                            if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
                                 {
-                                edma3IntrParams[mappedTcc].tccCb (
+                                edma3IntrParams[edma3Id][mappedTcc].tccCb (
                                         mappedTcc,
                                         EDMA3_RM_E_CC_DMA_EVT_MISS,
-                                        edma3IntrParams[mappedTcc].cbData
+                                        edma3IntrParams[edma3Id][mappedTcc].cbData
                                         );
                                 }
                             }
@@ -6120,7 +6187,7 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
                          * channel), fetch the corresponding TCC
                          * value, mapped to this QDMA channel.
                          */
-                        mappedTcc = edma3QdmaChTccMapping[index];
+                        mappedTcc = edma3QdmaChTccMapping[edma3Id][index];
 
                         if (mappedTcc < EDMA3_MAX_TCC)
                            {
@@ -6129,12 +6196,12 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
                             /*Clear any QSER*/
                             shadowRegs->QSECR = (1u<<index);
 
-                            if((edma3IntrParams[mappedTcc].tccCb) != NULL)
+                            if((edma3IntrParams[edma3Id][mappedTcc].tccCb) != NULL)
                                 {
-                                edma3IntrParams[mappedTcc].tccCb (
+                                edma3IntrParams[edma3Id][mappedTcc].tccCb (
                                         mappedTcc,
                                         EDMA3_RM_E_CC_QDMA_EVT_MISS,
-                                        edma3IntrParams[mappedTcc].cbData
+                                        edma3IntrParams[edma3Id][mappedTcc].cbData
                                         );
                                 }
                             }
@@ -6175,11 +6242,11 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
                              * Inform all the RM instances working on this region
                              * about the error by calling their global callback functions.
                              */
-                            num_rm_instances_opened = resMgrObj[hwId].numOpens;
+                            num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
                             for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
                                 {
                                 /* Check whether the RM instance opened working on this region */
-                                rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+                                rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
                                 if (NULL != rm_instance)
                                     {
                                     if (rm_instance->initParam.regionId == edma3RegionId)
@@ -6213,11 +6280,11 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
                          * Inform all the RM instances working on this region
                          * about the error by calling their global callback functions.
                          */
-                        num_rm_instances_opened = resMgrObj[hwId].numOpens;
+                        num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
                         for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
                             {
                             /* Check whether the RM instance opened working on this region */
-                            rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+                            rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
                             if (NULL != rm_instance)
                                 {
                                 if (rm_instance->initParam.regionId == edma3RegionId)
@@ -6276,7 +6343,9 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
                 ptrEdmaccRegs->EEVAL=0x1u;
                 }
 
-            edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, NULL);
+            edma3OsProtectExit (rmObj->phyCtrllerInstId,
+                                                               EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
+                                                               NULL);
             }
         }
 
@@ -6289,11 +6358,10 @@ static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
 #endif /* EDMA3_INSTRUMENTATION_ENABLED */
     }
 
-/* ARGSUSED */
-void lisrEdma3CCErrHandler0(unsigned int arg)
+void lisrEdma3CCErrHandler0(unsigned int edma3InstanceId)
     {
     /* Invoke CC Error Handler ISR */
-    edma3CCErrHandler(&resMgrObj[0]);
+    edma3CCErrHandler(&resMgrObj[edma3InstanceId]);
     }
 
 
@@ -6313,7 +6381,7 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
     unsigned int tcMemErrRdWr = 0u;
     unsigned int resMgrInstIdx = 0u;
     EDMA3_RM_Instance *rm_instance = NULL;
-    unsigned int hwId;
+    unsigned int edma3Id;
     unsigned int num_rm_instances_opened;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
@@ -6329,14 +6397,16 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
     if (rmObj->gblCfgParams.tcRegs[tcNum] != NULL)
         {
         tcRegs = (volatile EDMA3_TCRL_Regs *)(rmObj->gblCfgParams.tcRegs[tcNum]);
-        hwId = rmObj->phyCtrllerInstId;
+        edma3Id = rmObj->phyCtrllerInstId;
         }
 
     if (tcRegs != NULL)
         {
         if(tcRegs->ERRSTAT != 0)
             {
-            edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, &tcNum);
+            edma3OsProtectEntry (rmObj->phyCtrllerInstId,
+                                                               EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
+                                                               &tcNum);
 
             if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT))!=NULL)
                 {
@@ -6353,11 +6423,11 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
                      * Inform all the RM instances working on this region
                      * about the error by calling their global callback functions.
                      */
-                    num_rm_instances_opened = resMgrObj[hwId].numOpens;
+                    num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
                     for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
                         {
                         /* Check whether the RM instance opened working on this region */
-                        rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+                        rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
                         if (NULL != rm_instance)
                             {
                             if (rm_instance->initParam.regionId == edma3RegionId)
@@ -6385,11 +6455,11 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
                          * Inform all the RM instances working on this region
                          * about the error by calling their global callback functions.
                          */
-                        num_rm_instances_opened = resMgrObj[hwId].numOpens;
+                        num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
                         for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
                             {
                             /* Check whether the RM instance opened working on this region */
-                            rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+                            rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
                             if (NULL != rm_instance)
                                 {
                                 if (rm_instance->initParam.regionId == edma3RegionId)
@@ -6417,11 +6487,11 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
                 /* Transfer request (TR) error event. */
                 if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_TRERR_SHIFT))!=NULL)
                     {
-                    num_rm_instances_opened = resMgrObj[hwId].numOpens;
+                    num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
                     for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
                         {
                         /* Check whether the RM instance opened working on this region */
-                        rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+                        rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
                         if (NULL != rm_instance)
                             {
                             if (rm_instance->initParam.regionId == edma3RegionId)
@@ -6447,11 +6517,11 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
                     {
                     if((tcRegs->ERRSTAT & (1 << EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT))!=NULL)
                         {
-                        num_rm_instances_opened = resMgrObj[hwId].numOpens;
+                        num_rm_instances_opened = resMgrObj[edma3Id].numOpens;
                         for (resMgrInstIdx = 0u; num_rm_instances_opened; ++resMgrInstIdx)
                             {
                             /* Check whether the RM instance opened working on this region */
-                            rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (hwId*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
+                            rm_instance = ((EDMA3_RM_Instance *)(ptrRMIArray) + (edma3Id*EDMA3_MAX_RM_INSTANCES) + resMgrInstIdx);
                             if (NULL != rm_instance)
                                 {
                                 if (rm_instance->initParam.regionId == edma3RegionId)
@@ -6476,7 +6546,9 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
                     }
                 }
 
-            edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, tcNum);
+            edma3OsProtectExit (rmObj->phyCtrllerInstId,
+                                                               EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
+                                                               tcNum);
             }
         }
 
@@ -6495,11 +6567,10 @@ static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
  *  ======== lisrEdma3TC0ErrHandler0 ========
  *  EDMA3 instance 0 TC0 Error Interrupt Service Routine
  */
-/* ARGSUSED */
-void lisrEdma3TC0ErrHandler0(unsigned int arg)
+void lisrEdma3TC0ErrHandler0(unsigned int edma3InstanceId)
     {
     /* Invoke Error Handler ISR for TC0*/
-    edma3TCErrHandler(&resMgrObj[0u], 0u);
+    edma3TCErrHandler(&resMgrObj[edma3InstanceId], 0u);
     }
 
 
@@ -6507,44 +6578,40 @@ void lisrEdma3TC0ErrHandler0(unsigned int arg)
  *  ======== lisrEdma3TC1ErrHandler0 ========
  *  EDMA3 instance 0 TC1 Error Interrupt Service Routine
  */
-/* ARGSUSED */
-void lisrEdma3TC1ErrHandler0(unsigned int arg)
+void lisrEdma3TC1ErrHandler0(unsigned int edma3InstanceId)
     {
     /* Invoke Error Handler ISR for TC1*/
-    edma3TCErrHandler(&resMgrObj[0u], 1u);
+    edma3TCErrHandler(&resMgrObj[edma3InstanceId], 1u);
     }
 
 /*
  *  ======== lisrEdma3TC2ErrHandler0 ========
  *  EDMA3 instance 0 TC2 Error Interrupt Service Routine
  */
-/* ARGSUSED */
-void lisrEdma3TC2ErrHandler0(unsigned int arg)
+void lisrEdma3TC2ErrHandler0(unsigned int edma3InstanceId)
     {
     /* Invoke Error Handler ISR for TC2*/
-    edma3TCErrHandler(&resMgrObj[0u], 2u);
+    edma3TCErrHandler(&resMgrObj[edma3InstanceId], 2u);
     }
 
 /*
  *  ======== lisrEdma3TC3ErrHandler0 ========
  *  EDMA3 instance 0 TC3 Error Interrupt Service Routine
  */
-/* ARGSUSED */
-void lisrEdma3TC3ErrHandler0(unsigned int arg)
+void lisrEdma3TC3ErrHandler0(unsigned int edma3InstanceId)
     {
     /* Invoke Error Handler ISR for TC3*/
-    edma3TCErrHandler(&resMgrObj[0u], 3u);
+    edma3TCErrHandler(&resMgrObj[edma3InstanceId], 3u);
     }
 
 /*
  *  ======== lisrEdma3TC4ErrHandler0 ========
  *  EDMA3 instance 0 TC4 Error Interrupt Service Routine
  */
-/* ARGSUSED */
-void lisrEdma3TC4ErrHandler0(unsigned int arg)
+void lisrEdma3TC4ErrHandler0(unsigned int edma3InstanceId)
     {
     /* Invoke Error Handler ISR for TC4*/
-    edma3TCErrHandler(&resMgrObj[0u], 4u);
+    edma3TCErrHandler(&resMgrObj[edma3InstanceId], 4u);
     }
 
 
@@ -6552,11 +6619,10 @@ void lisrEdma3TC4ErrHandler0(unsigned int arg)
  *  ======== lisrEdma3TC5ErrHandler0 ========
  *  EDMA3 instance 0 TC5 Error Interrupt Service Routine
  */
-/* ARGSUSED */
-void lisrEdma3TC5ErrHandler0(unsigned int arg)
+void lisrEdma3TC5ErrHandler0(unsigned int edma3InstanceId)
     {
     /* Invoke Error Handler ISR for TC5*/
-    edma3TCErrHandler(&resMgrObj[0u], 5u);
+    edma3TCErrHandler(&resMgrObj[edma3InstanceId], 5u);
     }
 
 /*
@@ -6564,21 +6630,20 @@ void lisrEdma3TC5ErrHandler0(unsigned int arg)
  *  EDMA3 instance 0 TC6 Error Interrupt Service Routine
  */
 /* ARGSUSED */
-void lisrEdma3TC6ErrHandler0(unsigned int arg)
+void lisrEdma3TC6ErrHandler0(unsigned int edma3InstanceId)
     {
     /* Invoke Error Handler ISR for TC6*/
-    edma3TCErrHandler(&resMgrObj[0u], 6u);
+    edma3TCErrHandler(&resMgrObj[edma3InstanceId], 6u);
     }
 
 /*
  *  ======== lisrEdma3TC7ErrHandler0 ========
  *  EDMA3 instance 0 TC7 Error Interrupt Service Routine
  */
-/* ARGSUSED */
-void lisrEdma3TC7ErrHandler0(unsigned int arg)
+void lisrEdma3TC7ErrHandler0(unsigned int edma3InstanceId)
     {
     /* Invoke Error Handler ISR for TC7*/
-    edma3TCErrHandler(&resMgrObj[0u], 7u);
+    edma3TCErrHandler(&resMgrObj[edma3InstanceId], 7u);
     }
 
 
@@ -6691,34 +6756,23 @@ static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance)
             */
 
             /* 1. Dma Channel (and TCC) <-> Region */
-#ifdef EDMA3_RM_DEBUG
-            EDMA3_RM_PRINTF("DRAE=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAE);
-            EDMA3_RM_PRINTF("DRAEH=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAEH);
-#endif
-
-            edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);
+            edma3OsProtectEntry (phyCtrllerInstId,
+                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                               &intState);
             ptrEdmaccRegs->DRA[regionId].DRAE = 0u;
             ptrEdmaccRegs->DRA[regionId].DRAEH = 0u;
-            edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
-
-#ifdef EDMA3_RM_DEBUG
-            EDMA3_RM_PRINTF("DRAE=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAE);
-            EDMA3_RM_PRINTF("DRAEH=%x\r\n",ptrEdmaccRegs->DRA[regionId].DRAEH);
-#endif
+            edma3OsProtectExit (phyCtrllerInstId,
+                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                               intState);
 
             /* 2. Qdma Channel <-> Region */
-#ifdef EDMA3_RM_DEBUG
-            EDMA3_RM_PRINTF("QRAE=%x\r\n",ptrEdmaccRegs->QRAE[regionId]);
-#endif
-
-            edma3OsProtectEntry (EDMA3_OS_PROTECT_INTERRUPT, &intState);
+            edma3OsProtectEntry (phyCtrllerInstId,
+                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                               &intState);
             ptrEdmaccRegs->QRAE[regionId] = 0u;
-            edma3OsProtectExit (EDMA3_OS_PROTECT_INTERRUPT, intState);
-
-#ifdef EDMA3_RM_DEBUG
-            EDMA3_RM_PRINTF("QRAE=%x\r\n",ptrEdmaccRegs->QRAE[regionId]);
-#endif
-
+            edma3OsProtectExit (phyCtrllerInstId,
+                                                               EDMA3_OS_PROTECT_INTERRUPT,
+                                                               intState);
             }
         }
 
@@ -6727,19 +6781,19 @@ static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance)
 
 
 
-/** Local MemSet function */
-void edma3MemSet(void *dst, unsigned char data, unsigned int len)
+/** Local MemZero function */
+void edma3MemZero(void *dst, unsigned int len)
     {
-    unsigned int i=0u;
-    unsigned char *ds=NULL;
+    unsigned int i = 0u;
+    unsigned int *ds = NULL;
 
     assert (dst != NULL);
 
-    ds = (unsigned char *)dst;
+    ds = (unsigned int *)dst;
 
-    for( i=0;i<len;i++)
+    for (i = 0 ; i < len/4 ; i++)
         {
-        *ds=data;
+        *ds = 0x0;
         ds++;
         }
 
@@ -6751,17 +6805,17 @@ void edma3MemSet(void *dst, unsigned char data, unsigned int len)
 void edma3MemCpy(void *dst, const void *src, unsigned int len)
     {
     unsigned int i=0u;
-    const unsigned char *sr;
-    unsigned char *ds;
+    const unsigned int *sr;
+    unsigned int *ds;
 
-    assert ((src != NULL) && (dst != NULL));
+    assert ((src != NULL) && (dst != NULL) && ((len)%4 == 0));
 
-    sr = (const unsigned char *)src;
-    ds = (unsigned char *)dst;
+    sr = (const unsigned int *)src;
+    ds = (unsigned int *)dst;
 
-    for( i=0;i<len;i++)
+    for (i = 0 ; i < len/4 ; i++)
         {
-        *ds=*sr;
+        *ds = *sr;
         ds++;
         sr++;
         }
@@ -7136,6 +7190,7 @@ static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,
     unsigned int avlblIdx = 0u;
     unsigned int firstResId=0u;
     unsigned int lastResId=0u;
+       unsigned int edma3Id;
 
     assert ((rmInstance != NULL) && (firstResIdObj != NULL));
 
@@ -7148,6 +7203,7 @@ static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,
 
     if (EDMA3_RM_SOK == result)
         {
+        edma3Id = rmObj->phyCtrllerInstId;
         gblRegs = (volatile EDMA3_CCRL_Regs *)(rmObj->gblCfgParams.globalRegs);
 
         if (gblRegs == NULL)
@@ -7260,8 +7316,7 @@ static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,
                      */
                     if (TRUE == rmInstance->paramInitRequired)
                         {
-                        edma3MemSet((void *)(&gblRegs->PARAMENTRY[avlblIdx]),
-                                        0x00u,
+                        edma3MemZero((void *)(&gblRegs->PARAMENTRY[avlblIdx]),
                                         sizeof(gblRegs->PARAMENTRY[avlblIdx]));
                         }
                     }
index 32c23c602ff2c7630e12265e295759a9d69326b2..c78576151ec4a719f804ddc77bdc04514b98b481 100644 (file)
@@ -1,40 +1,40 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**|                            ****                                          |**
-**|                            ****                                          |**
-**|                            ******o***                                    |**
-**|                      ********_///_****                                   |**
-**|                      ***** /_//_/ ****                                   |**
-**|                       ** ** (__/ ****                                    |**
-**|                           *********                                      |**
-**|                            ****                                          |**
-**|                            ***                                           |**
-**|                                                                          |**
-**|         Copyright (c) 1998-2006 Texas Instruments Incorporated           |**
-**|                        ALL RIGHTS RESERVED                               |**
-**|                                                                          |**
-**| Permission is hereby granted to licensees of Texas Instruments           |**
-**| Incorporated (TI) products to use this computer program for the sole     |**
-**| purpose of implementing a licensee product based on TI products.         |**
-**| No other rights to reproduce, use, or disseminate this computer          |**
-**| program, whether in part or in whole, are granted.                       |**
-**|                                                                          |**
-**| TI makes no representation or warranties with respect to the             |**
-**| performance of this computer program, and specifically disclaims         |**
-**| any responsibility for any damages, special or consequential,            |**
-**| connected with the use of this program.                                  |**
-**|                                                                          |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/** \file   edma3resmgr.h
-    \brief  EDMA3 Resource Manager Internal header file.
-
-    This file contains implementation specific details used by the RM internally
-
-    (C) Copyright 2006, Texas Instruments, Inc
-
- */
+/*
+ * edma3resmgr.h
+ *
+ * EDMA3 Resource Manager Internal header file.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
 
 #ifndef _EDMA3_RES_MGR_H_
 #define _EDMA3_RES_MGR_H_
@@ -69,7 +69,7 @@ extern unsigned int edma3NumPaRAMSets;
 /** QCHMAP-PaRAMEntry bitfield Clear */
 #define EDMA3_RM_QCH_PARAM_CLR_MASK                (~EDMA3_CCRL_QCHMAP_PAENTRY_MASK)
 /** QCHMAP-PaRAMEntry bitfield Set */
-#define EDMA3_RM_QCH_PARAM_SET_MASK(paRAMId)       (((EDMA3_CCRL_QCHMAP_PAENTRY_MASK >> EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT)
+#define EDMA3_RM_QCH_PARAM_SET_MASK(trWord)       (((EDMA3_CCRL_QCHMAP_PAENTRY_MASK >> EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT) & (trWord)) << EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT)
 /** QCHMAP-TrigWord bitfield Clear */
 #define EDMA3_RM_QCH_TRWORD_CLR_MASK               (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
 /** QCHMAP-TrigWord bitfield Set */
@@ -124,39 +124,6 @@ typedef enum {
 
 
 
-/**
- * \defgroup Edma3RMIntBoundVals Boundary Values
- *
- * Boundary Values for Logical Channel Ranges
- *
- * @{
- */
-/** Max of DMA Channels */
-#define EDMA3_RM_DMA_CH_MAX_VAL        (EDMA3_MAX_DMA_CH - 1u)
-
-/** Min of Link Channels */
-#define EDMA3_RM_LINK_CH_MIN_VAL       (EDMA3_MAX_DMA_CH)
-
-/** Max of Link Channels */
-#define EDMA3_RM_LINK_CH_MAX_VAL       (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS - 1u)
-
-/** Min of QDMA Channels */
-#define EDMA3_RM_QDMA_CH_MIN_VAL       (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
-
-/** Max of QDMA Channels */
-#define EDMA3_RM_QDMA_CH_MAX_VAL       (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS + EDMA3_MAX_QDMA_CH - 1u)
-
-/** Max of Logical Channels */
-#define EDMA3_RM_LOG_CH_MAX_VAL       (EDMA3_RM_QDMA_CH_MAX_VAL)
-
-
-
-/* @} Edma3RMIntBoundVals */
-
-
-
-
-
 /**
  * \brief EDMA3 Hardware Instance Configuration Structure.
  *
@@ -182,7 +149,6 @@ typedef struct
      * while calling EDMA3_RM_create().
      */
     EDMA3_RM_GblConfigParams gblCfgParams;
-
     } EDMA3_RM_Obj;
 
 
@@ -256,13 +222,14 @@ typedef struct
      * the specific user.
      * User can program only the remaining fields in this case.
      *
-     * Value '0' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will NOT be programmed during their allocation.
-     * Value '1' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed during their allocation.
+     * Value '0' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will NOT be 
+     *                 programmed during their allocation.
+     * Value '1' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be 
+     *                 programmed during their allocation.
      *
      * This value can be modified using the IOCTL commands.
      */
     unsigned int          regModificationRequired;
-
     }EDMA3_RM_Instance;
 
 /* @} Edma3ResMgrIntObjMaint */