Revert "Merge branch 'master' into edma3_keystone2"
authorIvan Pang <i-pang@ti.com>
Mon, 9 Jun 2014 06:07:38 +0000 (02:07 -0400)
committerIvan Pang <i-pang@ti.com>
Mon, 9 Jun 2014 06:07:38 +0000 (02:07 -0400)
This reverts commit 2c7315c0baf24da1a3469def93f112411b0d13bf, reversing
changes made to 1906a1fda2117f255e1cd6aabaf83a7236674434.

94 files changed:
docs/EDMA3_Driver_Release_Notes.doc
docs/EDMA3_RM_Release_Notes.doc
eclipse/features/com.ti.sdo.edma3_02.11.11/feature.xml [moved from eclipse/features/com.ti.sdo.edma3_02.11.12/feature.xml with 75% similarity]
eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.11/Copy of toc_cdoc.xml [moved from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/Copy of toc_cdoc.xml with 100% similarity]
eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.11/META-INF/MANIFEST.MF [moved from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/META-INF/MANIFEST.MF with 69% similarity]
eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.11/plugin.xml [moved from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/plugin.xml with 83% similarity]
eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.11/toc_cdoc.xml [moved from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/toc_cdoc.xml with 100% similarity]
eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.11/toc_top.xml [moved from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/toc_top.xml with 93% similarity]
examples/edma3_driver/evmDRA72x_A15/makefile [deleted file]
examples/edma3_driver/evmDRA72x_A15/rtsc_config/edma3_drv_bios6_dra72x_a15_st_sample.cfg [deleted file]
examples/edma3_driver/evmDRA72x_A15/sample_app/linker.cmd [deleted file]
examples/edma3_driver/evmDRA72x_DSP/dsp_timer.c [deleted file]
examples/edma3_driver/evmDRA72x_DSP/makefile [deleted file]
examples/edma3_driver/evmDRA72x_DSP/rtsc_config/app_mem_seg_placement.cfg [deleted file]
examples/edma3_driver/evmDRA72x_DSP/rtsc_config/custom_config.bld [deleted file]
examples/edma3_driver/evmDRA72x_DSP/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg [deleted file]
examples/edma3_driver/evmDRA72x_DSP/rtsc_config/mem_segment_definition.xs [deleted file]
examples/edma3_driver/evmDRA72x_DSP/rtsc_config/platform.xs [deleted file]
examples/edma3_driver/evmDRA72x_DSP/sample_app/linker.cmd [deleted file]
examples/edma3_driver/evmDRA72x_M4/makefile [deleted file]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg [deleted file]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg [deleted file]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/custom_config.bld [deleted file]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg [deleted file]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg [deleted file]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/mem_segment_definition.xs [deleted file]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/platform.xs [deleted file]
examples/edma3_driver/evmDRA72x_M4/sample_app/linker.cmd [deleted file]
examples/edma3_driver/evmTDA3xx_DSP/dsp_timer.c [deleted file]
examples/edma3_driver/evmTDA3xx_DSP/makefile [deleted file]
examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/app_mem_seg_placement.cfg [deleted file]
examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/custom_config.bld [deleted file]
examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/edma3_drv_bios6_tda3xx_st_sample.cfg [deleted file]
examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/mem_segment_definition.xs [deleted file]
examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/platform.xs [deleted file]
examples/edma3_driver/evmTDA3xx_DSP/sample_app/linker.cmd [deleted file]
examples/edma3_driver/evmTDA3xx_EVE/Readme.txt [deleted file]
examples/edma3_driver/evmTDA3xx_EVE/eve_mmu.c [deleted file]
examples/edma3_driver/evmTDA3xx_EVE/makefile [deleted file]
examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/app_mem_seg_placement.cfg [deleted file]
examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/custom_config.bld [deleted file]
examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/edma3_drv_bios6_tda3xx_st_sample.cfg [deleted file]
examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/mem_segment_definition.xs [deleted file]
examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/platform.xs [deleted file]
examples/edma3_driver/evmTDA3xx_EVE/sample_app/linker.cmd [deleted file]
examples/edma3_driver/evmTDA3xx_M4/makefile [deleted file]
examples/edma3_driver/evmTDA3xx_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg [deleted file]
examples/edma3_driver/evmTDA3xx_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg [deleted file]
examples/edma3_driver/evmTDA3xx_M4/rtsc_config/custom_config.bld [deleted file]
examples/edma3_driver/evmTDA3xx_M4/rtsc_config/edma3_drv_bios6_tda3xx_m4_c0_st_sample.cfg [deleted file]
examples/edma3_driver/evmTDA3xx_M4/rtsc_config/edma3_drv_bios6_tda3xx_m4_c1_st_sample.cfg [deleted file]
examples/edma3_driver/evmTDA3xx_M4/rtsc_config/mem_segment_definition.xs [deleted file]
examples/edma3_driver/evmTDA3xx_M4/rtsc_config/platform.xs [deleted file]
examples/edma3_driver/evmTDA3xx_M4/sample_app/linker.cmd [deleted file]
makerules/common.mk
makerules/env.mk
makerules/platform.mk
makerules/rules_a15.mk
package.xdc
packages/component.mk
packages/makefile
packages/ti/sdo/edma3/drv/docs/EDMA3_Driver_Datasheet.doc
packages/ti/sdo/edma3/drv/docs/EDMA3_Driver_User_Guide.doc
packages/ti/sdo/edma3/drv/edma3_drv.h
packages/ti/sdo/edma3/drv/package.xdc
packages/ti/sdo/edma3/drv/package.xs
packages/ti/sdo/edma3/drv/sample/makefile
packages/ti/sdo/edma3/drv/sample/package.xdc
packages/ti/sdo/edma3/drv/sample/package.xs
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_arm_int_reg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_cfg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_int_reg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/sample_arm_cs.c
packages/ti/sdo/edma3/rm/docs/EDMA3_RM_Datasheet.doc
packages/ti/sdo/edma3/rm/docs/EDMA3_RM_User_Guide.doc
packages/ti/sdo/edma3/rm/edma3_common.h
packages/ti/sdo/edma3/rm/edma3_rm.h
packages/ti/sdo/edma3/rm/makefile
packages/ti/sdo/edma3/rm/package.xdc
packages/ti/sdo/edma3/rm/package.xs
packages/ti/sdo/edma3/rm/sample/makefile
packages/ti/sdo/edma3/rm/sample/package.xdc
packages/ti/sdo/edma3/rm/sample/package.xs
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_arm_int_reg.c [deleted file]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c [deleted file]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_arm_int_reg.c [deleted file]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_cfg.c [deleted file]
packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c [deleted file]
packages/ti/sdo/edma3/rm/src/configs/edma3_tda3xx_cfg.c [deleted file]
release_notes_edma3_lld.html
software-manifest.doc

index f465ac677cf1516eb26ac096b2626545110332f6..39d6fab9442350be6b5d4f090a0248c8cbb9802a 100755 (executable)
Binary files a/docs/EDMA3_Driver_Release_Notes.doc and b/docs/EDMA3_Driver_Release_Notes.doc differ
index 04e4a816d54f9da7eaa6c437eae70d79adff0158..20d460bb444031342ed3e9754b49f0aa1b33c763 100755 (executable)
Binary files a/docs/EDMA3_RM_Release_Notes.doc and b/docs/EDMA3_RM_Release_Notes.doc differ
similarity index 75%
rename from eclipse/features/com.ti.sdo.edma3_02.11.12/feature.xml
rename to eclipse/features/com.ti.sdo.edma3_02.11.11/feature.xml
index 33ca3cbd88edd13e1d90499afc0acb253d715f5d..2307672389cde721e61ed938d35b3f29484014f3 100644 (file)
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <feature
-      id="com.ti.sdo.edma3_02.11.12"
+      id="com.ti.sdo.edma3_02.11.11"
       label="EDMA3"
-      version="02.11.12"
+      version="02.11.11"
       provider-name="Texas Instruments">
 
    <description url="http://ti.com">
@@ -18,8 +18,8 @@
    </license>
 
    <plugin
-        id="com.ti.sdo.edma3.rtscRegistry_02.11.12"
-        version="02.11.12"
+        id="com.ti.sdo.edma3.rtscRegistry_02.11.11"
+        version="02.11.11"
         unpack="false" />
 
    <!-- ADD PLUGINS HERE -->
similarity index 69%
rename from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/META-INF/MANIFEST.MF
rename to eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.11/META-INF/MANIFEST.MF
index 8873f0f8780b282fe4914472752731d75a66c44c..16117e890a18ee8ced35b0d10a561d84bf3bf64b 100644 (file)
@@ -1,8 +1,8 @@
 Manifest-Version: 1.0
 Bundle-ManifestVersion: 2
-Bundle-Name: EDMA3 LLD 02.11.12 Help
-Bundle-SymbolicName: com.ti.sdo.edma3.rtscRegistry_02.11.12;singleton:=true
-Bundle-Version: 02.11.12
+Bundle-Name: EDMA3 LLD 02.11.11 Help
+Bundle-SymbolicName: com.ti.sdo.edma3.rtscRegistry_02.11.11;singleton:=true
+Bundle-Version: 02.11.11
 Bundle-Activator: org.eclipse.rtsc.xdctools.ui.CCSActivator
 Bundle-Vendor: Texas Instruments
 Require-Bundle: org.eclipse.ui,
similarity index 83%
rename from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/plugin.xml
rename to eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.11/plugin.xml
index d789b0861f7e2ea2c2c77893c02e3f6c60236df4..199035bef150454998c307fc18e4daed9feba7a9 100644 (file)
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="utf-8"?>
 <?eclipse version="3.2"?>
-<plugin name="EDMA3 LLD 02.11.12"
-        id="com.ti.sdo.edma3.rtscRegistry_02.11.12"
-        version="02.11.12"
+<plugin name="EDMA3 LLD 02.11.11"
+        id="com.ti.sdo.edma3.rtscRegistry_02.11.11"
+        version="02.11.11"
         provider-name="Texas Instruments">
   <extension point="org.eclipse.help.toc">
     <toc file="toc_top.xml"
     <docs location="../../../" />
     <info installLocation="../../../"
           productName="EDMA3 Driver"
-          versionNumber="02.11.12"
+          versionNumber="02.11.11"
           templateRepositoryPath="../../../packages"
           templateModule="ti.sdo.edma3.templates.Edma3Template"></info>
   </extension>
   <extension point="org.eclipse.rtsc.xdctools.managedbuild.core.rtscProductTypes">
     <productType id="com.ti.sdo.edma3"
                  name="EDMA3 Low Level Driver"
-                 folderPrefix="edma3_lld_02_11_11_16"
+                 folderPrefix="edma3_lld_02_11_11_15"
                  rootMacroName="EDMA3_LLD_INSTALL_DIR" />
   </extension>
   <extension point="org.eclipse.rtsc.xdctools.managedbuild.core.rtscProducts">
     <product productTypeId="com.ti.sdo.edma3"
-             version="02.11.12" />
+             version="02.11.11" />
   </extension>
 </plugin>
similarity index 93%
rename from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/toc_top.xml
rename to eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.11/toc_top.xml
index 041b0a225c1a495b7a76fb6a37b5f1a69a974104..c63d3e47db8582409176261f9ea323efe7d4b890 100644 (file)
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8"?>
 <?NLS TYPE="org.eclipse.help.toc"?>
-<toc label="EDMA3 Low Level Driver 02.11.12 Help">
+<toc label="EDMA3 Low Level Driver 02.11.11 Help">
   <topic label="Release Notes"
          href="release_notes_edma3_lld.html" />
   <topic label="EDMA3 Driver User Guide"
diff --git a/examples/edma3_driver/evmDRA72x_A15/makefile b/examples/edma3_driver/evmDRA72x_A15/makefile
deleted file mode 100644 (file)
index fd80a1f..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-# Makefile for edma3 lld app
-
-APP_NAME = edma3_drv_arm_dra72x_sample
-
-SRCDIR = ../src
-INCDIR = ../src
-
-# List all the external components/interfaces, whose interface header files
-#  need to be included for this component
-INCLUDE_EXTERNAL_INTERFACES = bios xdc edma3_lld
-
-# List all the components required by the application
-COMP_LIST_a15host = edma3_lld_drv edma3_lld_rm
-
-# XDC CFG File
-XDC_CFG_FILE_a15host = rtsc_config/edma3_drv_bios6_dra72x_a15_st_sample.cfg
-
-# Common source files and CFLAGS across all platforms and cores
-SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
-              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
-              qdma_link_test.c
-CFLAGS_LOCAL_COMMON = -DBUILD_DRA72X_MPU
-
-# Core/SoC/platform specific source files and CFLAGS
-# Example:
-#   SRCS_<core/SoC/platform-name> =
-#   CFLAGS_LOCAL_<core/SoC/platform-name> =
-
-# Include common make files
-include $(ROOTDIR)/makerules/common.mk
-
-# OBJs and libraries are built by using rule defined in rules_<target>.mk
-#     and need not be explicitly specified here
-
-# Nothing beyond this point
diff --git a/examples/edma3_driver/evmDRA72x_A15/rtsc_config/edma3_drv_bios6_dra72x_a15_st_sample.cfg b/examples/edma3_driver/evmDRA72x_A15/rtsc_config/edma3_drv_bios6_dra72x_a15_st_sample.cfg
deleted file mode 100644 (file)
index 4a79b29..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/*use modules*/
-var Task = xdc.useModule ("ti.sysbios.knl.Task");
-var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
-var Startup   = xdc.useModule ("xdc.runtime.Startup");
-var System    = xdc.useModule ("xdc.runtime.System");
-var Log       = xdc.useModule ("xdc.runtime.Log");
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Program     = xdc.useModule("xdc.cfg.Program");
-var Cache = xdc.useModule('ti.sysbios.hal.Cache');
-var Error = xdc.useModule('xdc.runtime.Error');
-
-//BIOS.libType = BIOS.LibType_Custom;
-/* Heap used when creating semaphore's, TSK's or malloc() ... */
-Program.heap            = 0x1000;
-
-/* ISR/SWI stack        */
-Program.stack           = 0x4000;
-
-Program.sectMap[".cio"] = new Program.SectionSpec();
-Program.sectMap[".cio"].loadSegment = "EXT_RAM";
-
-/* USE EDMA3 Sample App */
-//xdc.loadPackage('ti.sdo.edma3.drv.sample');
-
-/* MMU/Cache related configurations                                           */
-
-var Cache1  = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
-var Mmu    = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
-var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
-var GnuSupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
-
-/* Enable the cache                                                           */
-Cache1.enableCache = false;
-
-/* Enable the MMU (Required for L1 data caching)                              */
-Mmu.enableMMU = true;
-
-var attrs = new Mmu.DescriptorAttrs();
-Mmu.initDescAttrsMeta(attrs);
-attrs.type = Mmu.DescriptorType_BLOCK;
-attrs.noExecute = true;
-attrs.accPerm = 0;       // R/W at PL1
-attrs.attrIndx = 2;       // Use MAIR0 Byte2
-Mmu.setMAIRMeta(2, 0x04);
-Mmu.setSecondLevelDescMeta(0x43200000, 0x43200000, attrs);
-//Mmu.setSecondLevelDescMeta(0x43400000, 0x43400000, attrs);
-
-Task.initStackFlag = false;
-Task.checkStackFlag = false;
-
-Hwi.initStackFlag = false;
-Hwi.checkStackFlag = false;
\ No newline at end of file
diff --git a/examples/edma3_driver/evmDRA72x_A15/sample_app/linker.cmd b/examples/edma3_driver/evmDRA72x_A15/sample_app/linker.cmd
deleted file mode 100644 (file)
index 436a797..0000000
+++ /dev/null
@@ -1,5 +0,0 @@
-SECTIONS
-{
-    .my_sect_iram > EXT_RAM
-    .my_sect_ddr  > EXT_RAM
-}
diff --git a/examples/edma3_driver/evmDRA72x_DSP/dsp_timer.c b/examples/edma3_driver/evmDRA72x_DSP/dsp_timer.c
deleted file mode 100644 (file)
index 5b6bc5a..0000000
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * dsp_timer.c
- *
- * This file contains the test / demo code to demonstrate the EDMA3 driver
- * functionality on DSP/BIOS 6.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sysbios/knl/Clock.h>
-
-/*
- * mainDsp1TimerTick()   Enable Timer Tick.
- * The DSP timer does not run when
- * the host (A15) is halted because of the emulation suspend signal.
- */
-void mainDsp1TimerTick(UArg arg)
-{
-    Clock_tick();
-}
diff --git a/examples/edma3_driver/evmDRA72x_DSP/makefile b/examples/edma3_driver/evmDRA72x_DSP/makefile
deleted file mode 100644 (file)
index 24b4b14..0000000
+++ /dev/null
@@ -1,39 +0,0 @@
-# Makefile for edma3 lld app
-
-APP_NAME = edma3_drv_tda2xx_sample
-
-SRCDIR = ../src
-INCDIR = ../src
-
-# List all the external components/interfaces, whose interface header files
-#  need to be included for this component
-INCLUDE_EXTERNAL_INTERFACES = bios xdc edma3_lld
-
-# List all the components required by the application
-COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
-
-# XDC CFG File
-XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
-
-CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
-
-PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:DSP_1
-
-# Common source files and CFLAGS across all platforms and cores
-SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
-              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
-              qdma_link_test.c dsp_timer.c
-CFLAGS_LOCAL_COMMON = -DBUILD_TDA2XX_DSP
-
-# Core/SoC/platform specific source files and CFLAGS
-# Example:
-#   SRCS_<core/SoC/platform-name> =
-#   CFLAGS_LOCAL_<core/SoC/platform-name> =
-
-# Include common make files
-include $(ROOTDIR)/makerules/common.mk
-
-# OBJs and libraries are built by using rule defined in rules_<target>.mk
-#     and need not be explicitly specified here
-
-# Nothing beyond this point
diff --git a/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/app_mem_seg_placement.cfg b/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/app_mem_seg_placement.cfg
deleted file mode 100644 (file)
index ceda3f0..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *   @file  app_mem_seg_placement.cfg
- *
- *   @brief
- */
-
-function init()
-{
-    var Program = xdc.useModule('xdc.cfg.Program');
-
-        Program.sectMap[".vecs"]                    = "CODE_CORE_DSP1";
-        Program.sectMap[".text"]                    = "CODE_CORE_DSP1";
-        Program.sectMap[".text:_c_int00"]           = new Program.SectionSpec();
-        Program.sectMap[".text:_c_int00"].loadSegment = "CODE_CORE_DSP1";
-               Program.sectMap[".text:_c_int00"].loadAlign = 0x400;
-        Program.sectMap[".far"]                     = "CODE_CORE_DSP1";
-        Program.sectMap[".cinit"]                   = "CODE_CORE_DSP1";
-        Program.sectMap[".args"]                    = "CODE_CORE_DSP1";
-        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".my_sect_iram"]            = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_DSP1";
-}
diff --git a/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/custom_config.bld b/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/custom_config.bld
deleted file mode 100644 (file)
index 75b856a..0000000
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- *  ======== config.bld ========
- *  Sample Build configuration script
- */
-
-/* load the required modules for the configuration */
-
-var platform_xs = xdc.loadCapsule("platform.xs");
-
-/**********************************c66******************************/
-var C66_ELF = xdc.useModule('ti.targets.elf.C66');
-
-C66_ELF.rootDir = java.lang.System.getenv("CGTOOLS_ELF");
-
-C66_ELF.ccOpts.suffix += " -mi10 -mo --symdebug:none -O3";
-
-/* linker options */
-
-C66_ELF.lnkOpts.suffix += " --zero_init=off ";
-C66_ELF.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";
-
-C66_ELF.platforms = ["ti.platforms.evmDRA7XX:DSP_1"];
-
-C66_ELF.platform = C66_ELF.platforms[0];
-/**********************************c66******************************/
-
-/**********************************c66******************************/
-var C66e = xdc.useModule('ti.targets.elf.C66_big_endian');
-
-C66e.rootDir = java.lang.System.getenv("CGTOOLS_ELF");
-
-C66e.ccOpts.suffix += " -mi10 -mo -me --symdebug:none -O3";
-
-/* linker options */
-
-C66e.lnkOpts.suffix += " --zero_init=off ";
-C66e.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";
-
-C66e.platforms = ["ti.platforms.evmDRA7XX:DSP_1"];
-
-C66e.platform = C66e.platforms[0];
-/**********************************c66******************************/
-
-
-/* list interested targets in Build.targets array  */
-Build.targets = [
-                    C66_ELF,
-                    C66e
-                ];
diff --git a/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg b/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
deleted file mode 100644 (file)
index 2381124..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/*use modules*/
-var Task = xdc.useModule ("ti.sysbios.knl.Task");
-var BIOS = xdc.useModule ("ti.sysbios.BIOS");
-var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var Startup = xdc.useModule ("xdc.runtime.Startup");
-var System = xdc.useModule ("xdc.runtime.System");
-var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
-var halCache = xdc.useModule('ti.sysbios.hal.Cache');
-var InitXbar = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
-
-ECM.eventGroupHwiNum[0] = 7;
-ECM.eventGroupHwiNum[1] = 8;
-ECM.eventGroupHwiNum[2] = 9;
-ECM.eventGroupHwiNum[3] = 10;
-
-/* USE EDMA3 Sample App */
-//xdc.loadPackage('ti.sdo.edma3.drv.sample');
-
-halCache.CacheProxy = Cache;
-
-/***********************************************
- *          CLOCK Module Configuraion          *
- ***********************************************/
-var Clock = xdc.useModule("ti.sysbios.knl.Clock");
-Clock.tickMode = Clock.TickMode_PERIODIC;
-Clock.tickSource = Clock.TickSource_USER;
-
-/* allocate timer 5 to DSP1 */
-var TimerSupport = xdc.useModule('ti.sysbios.family.shared.vayu.TimerSupport');
-TimerSupport.availMask = 0x0020;
-
-/***********************************************
-*           Timer Module Configuraion         *
-***********************************************/
-/* Turn off the timer frequency check. The DSP timer does not run when
- * the host is halted because of the emulation suspend signal.
- */
-var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
-
-Timer.intFreq.hi = 0;
-/* system clock runs at 38.4 MHz */
-Timer.intFreq.lo = 38400000;
-
-var timerParams = new Timer.Params();
-timerParams.period = 1000;
-timerParams.twer.ovf_wup_ena = 1;
-timerParams.tiocpCfg.emufree = 1;
-
-Timer.create(5, '&mainDsp1TimerTick', timerParams);
-
-var segPlacement = xdc.loadCapsule("app_mem_seg_placement.cfg");
-segPlacement.init();
diff --git a/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/mem_segment_definition.xs
deleted file mode 100644 (file)
index e617408..0000000
+++ /dev/null
@@ -1,264 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *  ======== mem_segment_definition.xs ========
- */
-
-
-function getMemSegmentDefinitionIPU_1_0()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_IPU1_0",
-    {
-          name: "CODE_CORE_IPU1_0",
-          base: 0x84000000,
-          len:  0x01000000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",
-    {
-          name: "PRIVATE_DATA_CORE_IPU1_0",
-          base: 0x85000000,
-          len:  0x01800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",
-    {
-          name: "HDVPSS_DESCRIPTOR_NON_CACHED",
-          base: 0xA1800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[6] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionIPU_1_1()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_IPU1_1",
-    {
-          name: "CODE_CORE_IPU1_1",
-          base: 0x86800000,
-          len:  0x01000000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",
-    {
-          name: "PRIVATE_DATA_CORE_IPU1_1",
-          base: 0x87800000,
-          len:  0x01800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionDSP_1()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_DSP1",
-    {
-          name: "CODE_CORE_DSP1",
-          base: 0x83100000,
-          len:  0x00700000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_DSP1",
-    {
-          name: "PRIVATE_DATA_CORE_DSP1",
-          base: 0x83800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionHOST()
-{
-    var memory = new Array();
-
-    memory[8] = ["CODE_CORE_HOST",
-    {
-          name: "CODE_CORE_HOST",
-          base: 0x89000000,
-          len:  0x00800000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[9] = ["PRIVATE_DATA_CORE_HOST",
-    {
-          name: "PRIVATE_DATA_CORE_HOST",
-          base: 0x89800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[10] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[11] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[12] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[13] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
diff --git a/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/platform.xs b/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/platform.xs
deleted file mode 100644 (file)
index 4f1b3df..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *  ======== platform.xs ========
- */
-
-var Build = xdc.useModule('xdc.bld.BuildEnvironment');
-
-var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
-
-Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_0"] =
-{
-       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
-       codeMemory:"CODE_CORE_IPU1_0",
-       dataMemory:"PRIVATE_DATA_CORE_IPU1_0",
-       stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_1"] =
-{
-       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
-       codeMemory:"CODE_CORE_IPU1_1",
-       dataMemory:"PRIVATE_DATA_CORE_IPU1_1",
-       stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:DSP_1"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
-    codeMemory:"CODE_CORE_DSP1",
-    dataMemory:"PRIVATE_DATA_CORE_DSP1",
-    stackMemory:"PRIVATE_DATA_CORE_DSP1"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
-    codeMemory:"CODE_CORE_HOST",
-    dataMemory:"PRIVATE_DATA_CORE_HOST",
-    stackMemory:"PRIVATE_DATA_CORE_HOST"
-};
diff --git a/examples/edma3_driver/evmDRA72x_DSP/sample_app/linker.cmd b/examples/edma3_driver/evmDRA72x_DSP/sample_app/linker.cmd
deleted file mode 100644 (file)
index 6ca6627..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-SECTIONS
-{
-//     .my_sect_iram  > EXT_RAM
-//     .my_sect_ddr  > EXT_RAM
-}
-
-
diff --git a/examples/edma3_driver/evmDRA72x_M4/makefile b/examples/edma3_driver/evmDRA72x_M4/makefile
deleted file mode 100644 (file)
index a3cf5d8..0000000
+++ /dev/null
@@ -1,47 +0,0 @@
-# Makefile for edma3 lld app
-ifeq ($(IPUCORE),1)
-APP_NAME = edma3_drv_arm_tda2xx_core1_sample
-else
-APP_NAME = edma3_drv_arm_tda2xx_core0_sample
-endif
-
-SRCDIR = ../src
-INCDIR = ../src
-
-# List all the external components/interfaces, whose interface header files
-#  need to be included for this component
-INCLUDE_EXTERNAL_INTERFACES = bios xdc edma3_lld
-
-# List all the components required by the application
-COMP_LIST_m4 = edma3_lld_drv edma3_lld_rm
-
-# XDC CFG File
-ifeq ($(IPUCORE),1)
-XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg
-CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
-PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:IPU_1_1
-else
-XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg
-CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
-PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:IPU_1_0
-endif
-
-
-# Common source files and CFLAGS across all platforms and cores
-SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
-              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
-              qdma_link_test.c
-CFLAGS_LOCAL_COMMON = -DBUILD_TDA2XX_IPU
-
-# Core/SoC/platform specific source files and CFLAGS
-# Example:
-#   SRCS_<core/SoC/platform-name> =
-#   CFLAGS_LOCAL_<core/SoC/platform-name> =
-
-# Include common make files
-include $(ROOTDIR)/makerules/common.mk
-
-# OBJs and libraries are built by using rule defined in rules_<target>.mk
-#     and need not be explicitly specified here
-
-# Nothing beyond this point
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg
deleted file mode 100644 (file)
index 351c89a..0000000
+++ /dev/null
@@ -1,37 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *   @file  app_mem_seg_placement.cfg
- *
- *   @brief
- */
-
-function init()
-{
-    var Program = xdc.useModule('xdc.cfg.Program');
-
-        Program.sectMap[".text"]                    = "CODE_CORE_IPU1_0";
-        Program.sectMap[".cinit"]                   = "CODE_CORE_IPU1_0";
-        Program.sectMap[".pinit"]                   = "CODE_CORE_IPU1_0";
-        Program.sectMap[".args"]                    = "CODE_CORE_IPU1_0";
-        Program.sectMap[".const"]                   = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".stack"]                   = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_IPU1_0";
-        //BSP memory section placement
-        Program.sectMap[".bss:extMemNonCache:heap"] = "HDVPSS_DESCRIPTOR_NON_CACHED";
-        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".data"]                    = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_IPU1_0";
-               Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_IPU1_0";
-
-}
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg
deleted file mode 100644 (file)
index bdd0275..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *   @file  app_mem_seg_placement.cfg
- *
- *   @brief
- */
-
-function init()
-{
-    var Program = xdc.useModule('xdc.cfg.Program');
-        Program.sectMap[".text"]                    = "CODE_CORE_IPU1_1";
-        Program.sectMap[".cinit"]                   = "CODE_CORE_IPU1_1";
-        Program.sectMap[".pinit"]                   = "CODE_CORE_IPU1_1";
-        Program.sectMap[".args"]                    = "CODE_CORE_IPU1_1";
-        Program.sectMap[".const"]                   = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".stack"]                   = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_IPU1_1";
-        //BSP memory section placement
-        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".data"]                    = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".far:NDK_MMBUFFER"]        = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".far:NDK_MMBUFFER1"]       = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".far:NDK_OBJMEM"]          = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".far:NDK_PACKETMEM"]       = "PRIVATE_DATA_CORE_IPU1_1";
-               Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_IPU1_1";
-}
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/custom_config.bld b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/custom_config.bld
deleted file mode 100644 (file)
index 3c31ec6..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- *  ======== config.bld ========
- *  Sample Build configuration script
- */
-
-var platform_xs = xdc.loadCapsule("platform.xs");
\ No newline at end of file
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg
deleted file mode 100644 (file)
index 3872ad7..0000000
+++ /dev/null
@@ -1,74 +0,0 @@
-/*use modules*/
-var Task = xdc.useModule ("ti.sysbios.knl.Task");
-var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
-var Startup   = xdc.useModule ("xdc.runtime.Startup");
-var System    = xdc.useModule ("xdc.runtime.System");
-var Log       = xdc.useModule ("xdc.runtime.Log");
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
-var Error = xdc.useModule('xdc.runtime.Error');
-var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
-var Program     = xdc.useModule("xdc.cfg.Program");
-var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
-
-/* ISR/SWI stack        */
-Program.stack           = 0x4000;
-
-/* Heap used when creating semaphore's, TSK's or malloc() ... */
-Program.heap            = 0x15000;
-
-/*Program.sectMap[".ducatiBoot"]          = "L2_RAM";
-Program.sectMap[".bootVecs"]            = "L2_RAM";
-Program.sectMap[".ducatiGates"]         = "L2_RAM";
-*/
-
-/* enable print of exception handing info */
-HwiM3.enableException = true;
-
-/* DSP/BIOS expects this to set to 1 */
-var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
-Core.id = 0;
-Core.ipuId = 1;
-/*
-var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
-M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;
-M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress;
-*/
-/* USE EDMA3 Sample App */
-//xdc.loadPackage('ti.sdo.edma3.drv.sample');
-
-/* MMU/Cache related configurations                                           */
-var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');
-var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
-
-/* Enable the cache                                                           */
-Cache1.enableCache = true;
-
-//if (Core.id == 0)
-/*{
-       AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
-       AMMU.mediumPages[1].logicalAddress = 0x60000000;
-       AMMU.mediumPages[1].translatedAddress = 0x43300000;
-       AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
-       AMMU.mediumPages[1].size = AMMU.Medium_256K;
-       AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-       AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
-       AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-       AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-}*/
-
-if (Core.id == 1)
-{
-       var GateDualCore = xdc.useModule('ti.sysbios.family.arm.ducati.GateDualCore');
-       GateDualCore.initGates = true;
-}
-
-Task.initStackFlag = false;
-Task.checkStackFlag = false;
-
-Hwi.initStackFlag = false;
-Hwi.checkStackFlag = false;
-
-var segPlacement = xdc.loadCapsule("app_mem_seg_placement_ipu1_0.cfg");
-segPlacement.init();
\ No newline at end of file
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg
deleted file mode 100644 (file)
index aaa9efe..0000000
+++ /dev/null
@@ -1,73 +0,0 @@
-/*use modules*/
-var Task = xdc.useModule ("ti.sysbios.knl.Task");
-var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
-var Startup   = xdc.useModule ("xdc.runtime.Startup");
-var System    = xdc.useModule ("xdc.runtime.System");
-var Log       = xdc.useModule ("xdc.runtime.Log");
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
-var Error = xdc.useModule('xdc.runtime.Error');
-var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
-var Program     = xdc.useModule("xdc.cfg.Program");
-var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
-
-/* ISR/SWI stack        */
-Program.stack           = 0x4000;
-
-/* Heap used when creating semaphore's, TSK's or malloc() ... */
-Program.heap            = 0x15000;
-
-/*Program.sectMap[".ducatiBoot"]          = "L2_RAM";
-Program.sectMap[".bootVecs"]            = "L2_RAM";
-Program.sectMap[".ducatiGates"]         = "L2_RAM";
-*/
-
-/* enable print of exception handing info */
-HwiM3.enableException = true;
-
-/* DSP/BIOS expects this to set to 1 */
-var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
-Core.id = 1;
-/*
-var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
-M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;
-M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress;
-*/
-/* USE EDMA3 Sample App */
-//xdc.loadPackage('ti.sdo.edma3.drv.sample');
-
-/* MMU/Cache related configurations                                           */
-var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');
-var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
-
-/* Enable the cache                                                           */
-Cache1.enableCache = true;
-
-//if (Core.id == 0)
-/*{
-       AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
-       AMMU.mediumPages[1].logicalAddress = 0x60000000;
-       AMMU.mediumPages[1].translatedAddress = 0x43300000;
-       AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
-       AMMU.mediumPages[1].size = AMMU.Medium_256K;
-       AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-       AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
-       AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
-       AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
-}*/
-
-if (Core.id == 1)
-{
-       var GateDualCore = xdc.useModule('ti.sysbios.family.arm.ducati.GateDualCore');
-       GateDualCore.initGates = true;
-}
-
-Task.initStackFlag = false;
-Task.checkStackFlag = false;
-
-Hwi.initStackFlag = false;
-Hwi.checkStackFlag = false;
-
-var segPlacement = xdc.loadCapsule("app_mem_seg_placement_ipu1_1.cfg");
-segPlacement.init();
\ No newline at end of file
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/mem_segment_definition.xs
deleted file mode 100644 (file)
index e617408..0000000
+++ /dev/null
@@ -1,264 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *  ======== mem_segment_definition.xs ========
- */
-
-
-function getMemSegmentDefinitionIPU_1_0()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_IPU1_0",
-    {
-          name: "CODE_CORE_IPU1_0",
-          base: 0x84000000,
-          len:  0x01000000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",
-    {
-          name: "PRIVATE_DATA_CORE_IPU1_0",
-          base: 0x85000000,
-          len:  0x01800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",
-    {
-          name: "HDVPSS_DESCRIPTOR_NON_CACHED",
-          base: 0xA1800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[6] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionIPU_1_1()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_IPU1_1",
-    {
-          name: "CODE_CORE_IPU1_1",
-          base: 0x86800000,
-          len:  0x01000000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",
-    {
-          name: "PRIVATE_DATA_CORE_IPU1_1",
-          base: 0x87800000,
-          len:  0x01800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionDSP_1()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_DSP1",
-    {
-          name: "CODE_CORE_DSP1",
-          base: 0x83100000,
-          len:  0x00700000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_DSP1",
-    {
-          name: "PRIVATE_DATA_CORE_DSP1",
-          base: 0x83800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionHOST()
-{
-    var memory = new Array();
-
-    memory[8] = ["CODE_CORE_HOST",
-    {
-          name: "CODE_CORE_HOST",
-          base: 0x89000000,
-          len:  0x00800000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[9] = ["PRIVATE_DATA_CORE_HOST",
-    {
-          name: "PRIVATE_DATA_CORE_HOST",
-          base: 0x89800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[10] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[11] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[12] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[13] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/platform.xs b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/platform.xs
deleted file mode 100644 (file)
index 4f1b3df..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *  ======== platform.xs ========
- */
-
-var Build = xdc.useModule('xdc.bld.BuildEnvironment');
-
-var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
-
-Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_0"] =
-{
-       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
-       codeMemory:"CODE_CORE_IPU1_0",
-       dataMemory:"PRIVATE_DATA_CORE_IPU1_0",
-       stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_1"] =
-{
-       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
-       codeMemory:"CODE_CORE_IPU1_1",
-       dataMemory:"PRIVATE_DATA_CORE_IPU1_1",
-       stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:DSP_1"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
-    codeMemory:"CODE_CORE_DSP1",
-    dataMemory:"PRIVATE_DATA_CORE_DSP1",
-    stackMemory:"PRIVATE_DATA_CORE_DSP1"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
-    codeMemory:"CODE_CORE_HOST",
-    dataMemory:"PRIVATE_DATA_CORE_HOST",
-    stackMemory:"PRIVATE_DATA_CORE_HOST"
-};
diff --git a/examples/edma3_driver/evmDRA72x_M4/sample_app/linker.cmd b/examples/edma3_driver/evmDRA72x_M4/sample_app/linker.cmd
deleted file mode 100644 (file)
index 5062f6d..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-SECTIONS
-{
-//    .my_sect_iram > EXT_RAM
-//    .my_sect_ddr  > EXT_RAM
-//    .resetVecs  > L2_RAM
-}
diff --git a/examples/edma3_driver/evmTDA3xx_DSP/dsp_timer.c b/examples/edma3_driver/evmTDA3xx_DSP/dsp_timer.c
deleted file mode 100644 (file)
index 5b6bc5a..0000000
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * dsp_timer.c
- *
- * This file contains the test / demo code to demonstrate the EDMA3 driver
- * functionality on DSP/BIOS 6.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sysbios/knl/Clock.h>
-
-/*
- * mainDsp1TimerTick()   Enable Timer Tick.
- * The DSP timer does not run when
- * the host (A15) is halted because of the emulation suspend signal.
- */
-void mainDsp1TimerTick(UArg arg)
-{
-    Clock_tick();
-}
diff --git a/examples/edma3_driver/evmTDA3xx_DSP/makefile b/examples/edma3_driver/evmTDA3xx_DSP/makefile
deleted file mode 100644 (file)
index b0a52f8..0000000
+++ /dev/null
@@ -1,39 +0,0 @@
-# Makefile for edma3 lld app
-
-APP_NAME = edma3_drv_tda3xx_sample
-
-SRCDIR = ../src
-INCDIR = ../src
-
-# List all the external components/interfaces, whose interface header files
-#  need to be included for this component
-INCLUDE_EXTERNAL_INTERFACES = bios xdc edma3_lld
-
-# List all the components required by the application
-COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
-
-# XDC CFG File
-XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tda3xx_st_sample.cfg
-
-CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
-
-PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:DSP_1
-
-# Common source files and CFLAGS across all platforms and cores
-SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
-              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
-              qdma_link_test.c dsp_timer.c
-CFLAGS_LOCAL_COMMON = -DBUILD_TDA3XX_DSP
-
-# Core/SoC/platform specific source files and CFLAGS
-# Example:
-#   SRCS_<core/SoC/platform-name> =
-#   CFLAGS_LOCAL_<core/SoC/platform-name> =
-
-# Include common make files
-include $(ROOTDIR)/makerules/common.mk
-
-# OBJs and libraries are built by using rule defined in rules_<target>.mk
-#     and need not be explicitly specified here
-
-# Nothing beyond this point
diff --git a/examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/app_mem_seg_placement.cfg b/examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/app_mem_seg_placement.cfg
deleted file mode 100644 (file)
index ceda3f0..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *   @file  app_mem_seg_placement.cfg
- *
- *   @brief
- */
-
-function init()
-{
-    var Program = xdc.useModule('xdc.cfg.Program');
-
-        Program.sectMap[".vecs"]                    = "CODE_CORE_DSP1";
-        Program.sectMap[".text"]                    = "CODE_CORE_DSP1";
-        Program.sectMap[".text:_c_int00"]           = new Program.SectionSpec();
-        Program.sectMap[".text:_c_int00"].loadSegment = "CODE_CORE_DSP1";
-               Program.sectMap[".text:_c_int00"].loadAlign = 0x400;
-        Program.sectMap[".far"]                     = "CODE_CORE_DSP1";
-        Program.sectMap[".cinit"]                   = "CODE_CORE_DSP1";
-        Program.sectMap[".args"]                    = "CODE_CORE_DSP1";
-        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".my_sect_iram"]            = "PRIVATE_DATA_CORE_DSP1";
-        Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_DSP1";
-}
diff --git a/examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/custom_config.bld b/examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/custom_config.bld
deleted file mode 100644 (file)
index 75b856a..0000000
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- *  ======== config.bld ========
- *  Sample Build configuration script
- */
-
-/* load the required modules for the configuration */
-
-var platform_xs = xdc.loadCapsule("platform.xs");
-
-/**********************************c66******************************/
-var C66_ELF = xdc.useModule('ti.targets.elf.C66');
-
-C66_ELF.rootDir = java.lang.System.getenv("CGTOOLS_ELF");
-
-C66_ELF.ccOpts.suffix += " -mi10 -mo --symdebug:none -O3";
-
-/* linker options */
-
-C66_ELF.lnkOpts.suffix += " --zero_init=off ";
-C66_ELF.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";
-
-C66_ELF.platforms = ["ti.platforms.evmDRA7XX:DSP_1"];
-
-C66_ELF.platform = C66_ELF.platforms[0];
-/**********************************c66******************************/
-
-/**********************************c66******************************/
-var C66e = xdc.useModule('ti.targets.elf.C66_big_endian');
-
-C66e.rootDir = java.lang.System.getenv("CGTOOLS_ELF");
-
-C66e.ccOpts.suffix += " -mi10 -mo -me --symdebug:none -O3";
-
-/* linker options */
-
-C66e.lnkOpts.suffix += " --zero_init=off ";
-C66e.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";
-
-C66e.platforms = ["ti.platforms.evmDRA7XX:DSP_1"];
-
-C66e.platform = C66e.platforms[0];
-/**********************************c66******************************/
-
-
-/* list interested targets in Build.targets array  */
-Build.targets = [
-                    C66_ELF,
-                    C66e
-                ];
diff --git a/examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/edma3_drv_bios6_tda3xx_st_sample.cfg b/examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/edma3_drv_bios6_tda3xx_st_sample.cfg
deleted file mode 100644 (file)
index 2381124..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/*use modules*/
-var Task = xdc.useModule ("ti.sysbios.knl.Task");
-var BIOS = xdc.useModule ("ti.sysbios.BIOS");
-var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var Startup = xdc.useModule ("xdc.runtime.Startup");
-var System = xdc.useModule ("xdc.runtime.System");
-var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
-var halCache = xdc.useModule('ti.sysbios.hal.Cache');
-var InitXbar = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
-
-ECM.eventGroupHwiNum[0] = 7;
-ECM.eventGroupHwiNum[1] = 8;
-ECM.eventGroupHwiNum[2] = 9;
-ECM.eventGroupHwiNum[3] = 10;
-
-/* USE EDMA3 Sample App */
-//xdc.loadPackage('ti.sdo.edma3.drv.sample');
-
-halCache.CacheProxy = Cache;
-
-/***********************************************
- *          CLOCK Module Configuraion          *
- ***********************************************/
-var Clock = xdc.useModule("ti.sysbios.knl.Clock");
-Clock.tickMode = Clock.TickMode_PERIODIC;
-Clock.tickSource = Clock.TickSource_USER;
-
-/* allocate timer 5 to DSP1 */
-var TimerSupport = xdc.useModule('ti.sysbios.family.shared.vayu.TimerSupport');
-TimerSupport.availMask = 0x0020;
-
-/***********************************************
-*           Timer Module Configuraion         *
-***********************************************/
-/* Turn off the timer frequency check. The DSP timer does not run when
- * the host is halted because of the emulation suspend signal.
- */
-var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
-
-Timer.intFreq.hi = 0;
-/* system clock runs at 38.4 MHz */
-Timer.intFreq.lo = 38400000;
-
-var timerParams = new Timer.Params();
-timerParams.period = 1000;
-timerParams.twer.ovf_wup_ena = 1;
-timerParams.tiocpCfg.emufree = 1;
-
-Timer.create(5, '&mainDsp1TimerTick', timerParams);
-
-var segPlacement = xdc.loadCapsule("app_mem_seg_placement.cfg");
-segPlacement.init();
diff --git a/examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/mem_segment_definition.xs
deleted file mode 100644 (file)
index e617408..0000000
+++ /dev/null
@@ -1,264 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *  ======== mem_segment_definition.xs ========
- */
-
-
-function getMemSegmentDefinitionIPU_1_0()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_IPU1_0",
-    {
-          name: "CODE_CORE_IPU1_0",
-          base: 0x84000000,
-          len:  0x01000000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",
-    {
-          name: "PRIVATE_DATA_CORE_IPU1_0",
-          base: 0x85000000,
-          len:  0x01800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",
-    {
-          name: "HDVPSS_DESCRIPTOR_NON_CACHED",
-          base: 0xA1800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[6] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionIPU_1_1()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_IPU1_1",
-    {
-          name: "CODE_CORE_IPU1_1",
-          base: 0x86800000,
-          len:  0x01000000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",
-    {
-          name: "PRIVATE_DATA_CORE_IPU1_1",
-          base: 0x87800000,
-          len:  0x01800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionDSP_1()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_DSP1",
-    {
-          name: "CODE_CORE_DSP1",
-          base: 0x83100000,
-          len:  0x00700000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_DSP1",
-    {
-          name: "PRIVATE_DATA_CORE_DSP1",
-          base: 0x83800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionHOST()
-{
-    var memory = new Array();
-
-    memory[8] = ["CODE_CORE_HOST",
-    {
-          name: "CODE_CORE_HOST",
-          base: 0x89000000,
-          len:  0x00800000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[9] = ["PRIVATE_DATA_CORE_HOST",
-    {
-          name: "PRIVATE_DATA_CORE_HOST",
-          base: 0x89800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[10] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[11] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[12] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[13] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
diff --git a/examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/platform.xs b/examples/edma3_driver/evmTDA3xx_DSP/rtsc_config/platform.xs
deleted file mode 100644 (file)
index 4f1b3df..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *  ======== platform.xs ========
- */
-
-var Build = xdc.useModule('xdc.bld.BuildEnvironment');
-
-var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
-
-Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_0"] =
-{
-       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
-       codeMemory:"CODE_CORE_IPU1_0",
-       dataMemory:"PRIVATE_DATA_CORE_IPU1_0",
-       stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_1"] =
-{
-       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
-       codeMemory:"CODE_CORE_IPU1_1",
-       dataMemory:"PRIVATE_DATA_CORE_IPU1_1",
-       stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:DSP_1"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
-    codeMemory:"CODE_CORE_DSP1",
-    dataMemory:"PRIVATE_DATA_CORE_DSP1",
-    stackMemory:"PRIVATE_DATA_CORE_DSP1"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
-    codeMemory:"CODE_CORE_HOST",
-    dataMemory:"PRIVATE_DATA_CORE_HOST",
-    stackMemory:"PRIVATE_DATA_CORE_HOST"
-};
diff --git a/examples/edma3_driver/evmTDA3xx_DSP/sample_app/linker.cmd b/examples/edma3_driver/evmTDA3xx_DSP/sample_app/linker.cmd
deleted file mode 100644 (file)
index 6ca6627..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-SECTIONS
-{
-//     .my_sect_iram  > EXT_RAM
-//     .my_sect_ddr  > EXT_RAM
-}
-
-
diff --git a/examples/edma3_driver/evmTDA3xx_EVE/Readme.txt b/examples/edma3_driver/evmTDA3xx_EVE/Readme.txt
deleted file mode 100644 (file)
index fdf90b0..0000000
+++ /dev/null
@@ -1,10 +0,0 @@
-===================================================================================
-Running standalone example on EVE core, it is required to configure EVE mmu setting.
-For this gels6 is mandatory CCS_CSP_ADAS_S28_ES1.0_NDA_TRM_vA_gels6 which configures
-default EVE mmu setting or Customer has to configure following address mapping.
-
-EVE MMU0 TLB entry 1: 0x00000000 --> 0x40500000  : 4K Page size
-EVE MMU0 TLB entry 2: 0x4A000000 --> 0x4A000000  : 1M Page size
-EVE MMU0 TLB entry 3: 0x81000000 --> 0x81000000  : 16M Page size
-EVE MMU0 TLB entry 4: 0x40000000 --> 0x40000000  : 16M Page size
-===================================================================================
\ No newline at end of file
diff --git a/examples/edma3_driver/evmTDA3xx_EVE/eve_mmu.c b/examples/edma3_driver/evmTDA3xx_EVE/eve_mmu.c
deleted file mode 100644 (file)
index b97d0f1..0000000
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * eve_mmu.c
- *
- * This file contains the test / demo code to demonstrate the EDMA3 driver
- * functionality on DSP/BIOS 6.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-/******************************************************************************
-*                             Macro Declarations                              *
-******************************************************************************/
-#define WR_MEM_32(addr, data)    *(unsigned int*)(addr) =(unsigned int)(data)
-#define RD_MEM_32(addr)          *(unsigned int*)(addr)
-
-#define MMU_BASE 0x40081000 /* EVE's view */
-/* #define MMU_BASE 0x42081000 */   /* MPU's view */
-#define TESLASS_MMU__MMU_CNTL    ( MMU_BASE + 0x44 )
-#define TESLASS_MMU__MMU_CAM     ( MMU_BASE + 0x58 )
-#define TESLASS_MMU__MMU_RAM     ( MMU_BASE + 0x5c )
-#define TESLASS_MMU__MMU_LOCK    ( MMU_BASE + 0x50 )
-#define TESLASS_MMU__MMU_LD_TLB  ( MMU_BASE + 0x54 )
-
-#define PHY_ADDR1   0x4A000000
-#define VIRT_ADDR1  0x4A000000
-
-/*
- * eve1MmuConfig() This function does EVE MMU settings. This function is
- * called from Reset Module which is defined in configuration file.
- */
-void eveMmuConfig(void)
-{
-    /* ------------------------------------------------------------------------------------------------------- */
-    WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000c | (VIRT_ADDR1 & 0xFFFFE000));
-    WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR1  & 0xFFFFE000));
-
-    /* tlbEntry is bits 8:4
-    #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM          BITFIELD(8, 4) */
-    WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 11 << 4 ));
-    WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );
-    /* ------------------------------------------------------------------------------------------------------- */
-
-    /*Enable MMU*/
-    WR_MEM_32(TESLASS_MMU__MMU_CNTL, ((RD_MEM_32(TESLASS_MMU__MMU_CNTL)) & 0xFFFFFFFD) | 0x2);
-}
diff --git a/examples/edma3_driver/evmTDA3xx_EVE/makefile b/examples/edma3_driver/evmTDA3xx_EVE/makefile
deleted file mode 100644 (file)
index e3865e1..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
-# Makefile for edma3 lld app
-
-APP_NAME = edma3_drv_tda3xx_sample
-
-SRCDIR = ../src .
-INCDIR = ../src
-
-# List all the external components/interfaces, whose interface header files
-#  need to be included for this component
-INCLUDE_EXTERNAL_INTERFACES = bios xdc edma3_lld
-
-# List all the components required by the application
-COMP_LIST_eve = edma3_lld_drv edma3_lld_rm
-
-# XDC CFG File
-XDC_CFG_FILE_eve = rtsc_config/edma3_drv_bios6_tda3xx_st_sample.cfg
-
-CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
-
-PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:EVE_1
-
-# Common source files and CFLAGS across all platforms and cores
-SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
-              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
-              qdma_link_test.c eve_mmu.c
-
-CFLAGS_LOCAL_COMMON = -DBUILD_TDA3XX_EVE
-
-# Core/SoC/platform specific source files and CFLAGS
-# Example:
-#   SRCS_<core/SoC/platform-name> =
-#   CFLAGS_LOCAL_<core/SoC/platform-name> =
-
-# Include common make files
-include $(ROOTDIR)/makerules/common.mk
-
-# OBJs and libraries are built by using rule defined in rules_<target>.mk
-#     and need not be explicitly specified here
-
-# Nothing beyond this point
diff --git a/examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/app_mem_seg_placement.cfg b/examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/app_mem_seg_placement.cfg
deleted file mode 100644 (file)
index 1f4693d..0000000
+++ /dev/null
@@ -1,49 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *   @file  app_mem_seg_placement.cfg
- *
- *   @brief
- */
-
-function init()
-{
-    Program.sectMap[".inthandler"]              = "CODE_CORE_EVE";
-    Program.sectMap[".text"]                    = "CODE_CORE_EVE";
-    Program.sectMap[".stack"]                   = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_EVE";
-    //Program.sectMap[".bss"]                     = "DMEM";
-    Program.sectMap[".cinit"]                   = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".init_array"]              = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".const"]                   = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".data"]                    = "PRIVATE_DATA_CORE_EVE";
-    //Program.sectMap[".data"]                    = "DMEM";
-    Program.sectMap[".switch"]                  = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".far"]                     = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".args"]                    = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".cio"]                     = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".fardata"]                 = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_EVE";
-    //Program.sectMap[".rodata"]                  = "DMEM";
-    Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".my_sect_iram"]            = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_EVE";
-    Program.sectMap[".vecs"]                    = "OCMC3"; //"EVE_1_VECS";
-   /* Program.sectMap[".imemha"]                  = "IBUFHA";
-    Program.sectMap[".imemhb"]                  = "IBUFHB";
-    Program.sectMap[".imemla"]                  = "IBUFLA";
-    Program.sectMap[".imemlb"]                  = "IBUFLB";
-    Program.sectMap[".wmem"]                    = "WBUF";
-    Program.sectMap[".vcop_parameter_block"]    = "WBUF";
-    Program.sectMap["Cdata"]                    = "WBUF";
-    Program.sectMap["Udata"]                    = "WBUF";
-    */
-}
diff --git a/examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/custom_config.bld b/examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/custom_config.bld
deleted file mode 100644 (file)
index 3c31ec6..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- *  ======== config.bld ========
- *  Sample Build configuration script
- */
-
-var platform_xs = xdc.loadCapsule("platform.xs");
\ No newline at end of file
diff --git a/examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/edma3_drv_bios6_tda3xx_st_sample.cfg b/examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/edma3_drv_bios6_tda3xx_st_sample.cfg
deleted file mode 100644 (file)
index 8a479e6..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-/*use modules*/
-var Task = xdc.useModule ("ti.sysbios.knl.Task");
-var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
-var Startup   = xdc.useModule ("xdc.runtime.Startup");
-var System    = xdc.useModule ("xdc.runtime.System");
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Cache       = xdc.useModule('ti.sysbios.family.arp32.Cache');
-var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
-var Cache = xdc.useModule('ti.sysbios.family.arp32.Cache');
-var halCache = xdc.useModule('ti.sysbios.hal.Cache');
-var Reset = xdc.useModule('xdc.runtime.Reset');
-
-Reset.fxns[Reset.fxns.length++] = "&eveMmuConfig";
-
-halCache.CacheProxy = Cache;
-
-//Program.heap = 0x5000;
-
-/* USE EDMA3 Sample App */
-//xdc.loadPackage('ti.sdo.edma3.drv.sample');
-
-var segPlacement = xdc.loadCapsule("app_mem_seg_placement.cfg");
-segPlacement.init();
diff --git a/examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/mem_segment_definition.xs
deleted file mode 100644 (file)
index c2fc00e..0000000
+++ /dev/null
@@ -1,311 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *  ======== mem_segment_definition.xs ========
- */
-
-
-function getMemSegmentDefinitionIPU_1_0()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_IPU1_0",
-    {
-          name: "CODE_CORE_IPU1_0",
-          base: 0x84000000,
-          len:  0x01000000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",
-    {
-          name: "PRIVATE_DATA_CORE_IPU1_0",
-          base: 0x85000000,
-          len:  0x01800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",
-    {
-          name: "HDVPSS_DESCRIPTOR_NON_CACHED",
-          base: 0xA1800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[6] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionIPU_1_1()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_IPU1_1",
-    {
-          name: "CODE_CORE_IPU1_1",
-          base: 0x86800000,
-          len:  0x01000000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",
-    {
-          name: "PRIVATE_DATA_CORE_IPU1_1",
-          base: 0x87800000,
-          len:  0x01800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionDSP_1()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_DSP1",
-    {
-          name: "CODE_CORE_DSP1",
-          base: 0x83100000,
-          len:  0x00700000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_DSP1",
-    {
-          name: "PRIVATE_DATA_CORE_DSP1",
-          base: 0x83800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionHOST()
-{
-    var memory = new Array();
-
-    memory[8] = ["CODE_CORE_HOST",
-    {
-          name: "CODE_CORE_HOST",
-          base: 0x89000000,
-          len:  0x00800000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[9] = ["PRIVATE_DATA_CORE_HOST",
-    {
-          name: "PRIVATE_DATA_CORE_HOST",
-          base: 0x89800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[10] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[11] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[12] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[13] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionEVE()
-{
-    var memory = new Array();
-
-    memory[0] = ["EVE_1_VECS",
-    {
-          name: "EVE_1_VECS",
-          base: 0x81000000,
-          len:  0x00000100,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[1] = ["CODE_CORE_EVE",
-    {
-          name: "CODE_CORE_EVE",
-          base: 0x81000100,
-          len:  0x0004FF00,
-          space: "code",
-          page: 1,
-          access: "RWX"
-    }];
-
-    memory[2] = ["PRIVATE_DATA_CORE_EVE",
-    {
-          name: "PRIVATE_DATA_CORE_EVE",
-          base: 0x81050000,
-          len:  0x00400000,
-          space: "data",
-          page: 1,
-          access: "RWX"
-    }];
-
-    memory[3] = ["OCMC3",
-    {
-          name: "OCMC3",
-          base: 0x40500000,
-          len:  0x00001000,
-          space: "data",
-          page: 1,
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
diff --git a/examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/platform.xs b/examples/edma3_driver/evmTDA3xx_EVE/rtsc_config/platform.xs
deleted file mode 100644 (file)
index 869c1a2..0000000
+++ /dev/null
@@ -1,54 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *  ======== platform.xs ========
- */
-
-var Build = xdc.useModule('xdc.bld.BuildEnvironment');
-
-var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
-
-Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_0"] =
-{
-       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
-       codeMemory:"CODE_CORE_IPU1_0",
-       dataMemory:"PRIVATE_DATA_CORE_IPU1_0",
-       stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_1"] =
-{
-       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
-       codeMemory:"CODE_CORE_IPU1_1",
-       dataMemory:"PRIVATE_DATA_CORE_IPU1_1",
-       stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:DSP_1"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
-    codeMemory:"CODE_CORE_DSP1",
-    dataMemory:"PRIVATE_DATA_CORE_DSP1",
-    stackMemory:"PRIVATE_DATA_CORE_DSP1"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
-    codeMemory:"CODE_CORE_HOST",
-    dataMemory:"PRIVATE_DATA_CORE_HOST",
-    stackMemory:"PRIVATE_DATA_CORE_HOST"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:EVE_1"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionEVE(),
-    codeMemory:"CODE_CORE_EVE",
-    dataMemory:"PRIVATE_DATA_CORE_EVE",
-    stackMemory:"PRIVATE_DATA_CORE_EVE"
-};
diff --git a/examples/edma3_driver/evmTDA3xx_EVE/sample_app/linker.cmd b/examples/edma3_driver/evmTDA3xx_EVE/sample_app/linker.cmd
deleted file mode 100644 (file)
index 821d7b7..0000000
+++ /dev/null
@@ -1,5 +0,0 @@
-SECTIONS
-{
-//    .my_sect_iram > EXT_RAM
-//    .my_sect_ddr  > EXT_RAM
-}
diff --git a/examples/edma3_driver/evmTDA3xx_M4/makefile b/examples/edma3_driver/evmTDA3xx_M4/makefile
deleted file mode 100644 (file)
index 361ae01..0000000
+++ /dev/null
@@ -1,47 +0,0 @@
-# Makefile for edma3 lld app
-ifeq ($(IPUCORE),1)
-APP_NAME = edma3_drv_arm_tda3xx_core1_sample
-else
-APP_NAME = edma3_drv_arm_tda3xx_core0_sample
-endif
-
-SRCDIR = ../src
-INCDIR = ../src
-
-# List all the external components/interfaces, whose interface header files
-#  need to be included for this component
-INCLUDE_EXTERNAL_INTERFACES = bios xdc edma3_lld
-
-# List all the components required by the application
-COMP_LIST_m4 = edma3_lld_drv edma3_lld_rm
-
-# XDC CFG File
-ifeq ($(IPUCORE),1)
-XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda3xx_m4_c1_st_sample.cfg
-CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
-PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:IPU_1_1
-else
-XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda3xx_m4_c0_st_sample.cfg
-CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
-PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:IPU_1_0
-endif
-
-
-# Common source files and CFLAGS across all platforms and cores
-SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
-              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
-              qdma_link_test.c
-CFLAGS_LOCAL_COMMON = -DBUILD_TDA3XX_IPU
-
-# Core/SoC/platform specific source files and CFLAGS
-# Example:
-#   SRCS_<core/SoC/platform-name> =
-#   CFLAGS_LOCAL_<core/SoC/platform-name> =
-
-# Include common make files
-include $(ROOTDIR)/makerules/common.mk
-
-# OBJs and libraries are built by using rule defined in rules_<target>.mk
-#     and need not be explicitly specified here
-
-# Nothing beyond this point
diff --git a/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg b/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg
deleted file mode 100644 (file)
index 351c89a..0000000
+++ /dev/null
@@ -1,37 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *   @file  app_mem_seg_placement.cfg
- *
- *   @brief
- */
-
-function init()
-{
-    var Program = xdc.useModule('xdc.cfg.Program');
-
-        Program.sectMap[".text"]                    = "CODE_CORE_IPU1_0";
-        Program.sectMap[".cinit"]                   = "CODE_CORE_IPU1_0";
-        Program.sectMap[".pinit"]                   = "CODE_CORE_IPU1_0";
-        Program.sectMap[".args"]                    = "CODE_CORE_IPU1_0";
-        Program.sectMap[".const"]                   = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".stack"]                   = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_IPU1_0";
-        //BSP memory section placement
-        Program.sectMap[".bss:extMemNonCache:heap"] = "HDVPSS_DESCRIPTOR_NON_CACHED";
-        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".data"]                    = "PRIVATE_DATA_CORE_IPU1_0";
-        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_IPU1_0";
-               Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_IPU1_0";
-
-}
diff --git a/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg b/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg
deleted file mode 100644 (file)
index bdd0275..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *   @file  app_mem_seg_placement.cfg
- *
- *   @brief
- */
-
-function init()
-{
-    var Program = xdc.useModule('xdc.cfg.Program');
-        Program.sectMap[".text"]                    = "CODE_CORE_IPU1_1";
-        Program.sectMap[".cinit"]                   = "CODE_CORE_IPU1_1";
-        Program.sectMap[".pinit"]                   = "CODE_CORE_IPU1_1";
-        Program.sectMap[".args"]                    = "CODE_CORE_IPU1_1";
-        Program.sectMap[".const"]                   = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".stack"]                   = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_IPU1_1";
-        //BSP memory section placement
-        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".data"]                    = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".far:NDK_MMBUFFER"]        = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".far:NDK_MMBUFFER1"]       = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".far:NDK_OBJMEM"]          = "PRIVATE_DATA_CORE_IPU1_1";
-        Program.sectMap[".far:NDK_PACKETMEM"]       = "PRIVATE_DATA_CORE_IPU1_1";
-               Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_IPU1_1";
-}
diff --git a/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/custom_config.bld b/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/custom_config.bld
deleted file mode 100644 (file)
index 3c31ec6..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- *  ======== config.bld ========
- *  Sample Build configuration script
- */
-
-var platform_xs = xdc.loadCapsule("platform.xs");
\ No newline at end of file
diff --git a/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/edma3_drv_bios6_tda3xx_m4_c0_st_sample.cfg b/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/edma3_drv_bios6_tda3xx_m4_c0_st_sample.cfg
deleted file mode 100644 (file)
index 26212f8..0000000
+++ /dev/null
@@ -1,61 +0,0 @@
-/*use modules*/
-var Task = xdc.useModule ("ti.sysbios.knl.Task");
-var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
-var Startup   = xdc.useModule ("xdc.runtime.Startup");
-var System    = xdc.useModule ("xdc.runtime.System");
-var Log       = xdc.useModule ("xdc.runtime.Log");
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
-var Error = xdc.useModule('xdc.runtime.Error');
-var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
-var Program     = xdc.useModule("xdc.cfg.Program");
-var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
-
-/* ISR/SWI stack        */
-Program.stack           = 0x4000;
-
-/* Heap used when creating semaphore's, TSK's or malloc() ... */
-Program.heap            = 0x15000;
-
-/* enable print of exception handing info */
-HwiM3.enableException = true;
-
-/* DSP/BIOS expects this to set to 1 */
-var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
-Core.id = 0;
-Core.ipuId = 1;
-
-/* Enable below 6 lines only for Zebu comment while running on silicon */
-Program.sectMap[".ducatiBoot"]          = "L2_RAM";
-Program.sectMap[".bootVecs"]            = "L2_RAM";
-Program.sectMap[".ducatiGates"]         = "L2_RAM";
-var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
-M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;
-M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress;
-
-
-/* USE EDMA3 Sample App */
-//xdc.loadPackage('ti.sdo.edma3.drv.sample');
-
-/* MMU/Cache related configurations                                           */
-var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');
-var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
-
-/* Enable the cache                                                           */
-Cache1.enableCache = true;
-
-if (Core.id == 1)
-{
-       var GateDualCore = xdc.useModule('ti.sysbios.family.arm.ducati.GateDualCore');
-       GateDualCore.initGates = true;
-}
-
-Task.initStackFlag = false;
-Task.checkStackFlag = false;
-
-Hwi.initStackFlag = false;
-Hwi.checkStackFlag = false;
-
-var segPlacement = xdc.loadCapsule("app_mem_seg_placement_ipu1_0.cfg");
-segPlacement.init();
\ No newline at end of file
diff --git a/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/edma3_drv_bios6_tda3xx_m4_c1_st_sample.cfg b/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/edma3_drv_bios6_tda3xx_m4_c1_st_sample.cfg
deleted file mode 100644 (file)
index 351165e..0000000
+++ /dev/null
@@ -1,59 +0,0 @@
-/*use modules*/
-var Task = xdc.useModule ("ti.sysbios.knl.Task");
-var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
-var Startup   = xdc.useModule ("xdc.runtime.Startup");
-var System    = xdc.useModule ("xdc.runtime.System");
-var Log       = xdc.useModule ("xdc.runtime.Log");
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
-var Error = xdc.useModule('xdc.runtime.Error');
-var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
-var Program     = xdc.useModule("xdc.cfg.Program");
-var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
-
-/* ISR/SWI stack        */
-Program.stack           = 0x4000;
-
-/* Heap used when creating semaphore's, TSK's or malloc() ... */
-Program.heap            = 0x15000;
-
-/* enable print of exception handing info */
-HwiM3.enableException = true;
-
-/* DSP/BIOS expects this to set to 1 */
-var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
-Core.id = 1;
-
-/* Enable below 6 lines only for Zebu comment while running on silicon */
-Program.sectMap[".ducatiBoot"]          = "L2_RAM";
-Program.sectMap[".bootVecs"]            = "L2_RAM";
-Program.sectMap[".ducatiGates"]         = "L2_RAM";
-var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
-M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;
-M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress;
-
-/* USE EDMA3 Sample App */
-//xdc.loadPackage('ti.sdo.edma3.drv.sample');
-
-/* MMU/Cache related configurations                                           */
-var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');
-var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
-
-/* Enable the cache                                                           */
-Cache1.enableCache = true;
-
-if (Core.id == 1)
-{
-       var GateDualCore = xdc.useModule('ti.sysbios.family.arm.ducati.GateDualCore');
-       GateDualCore.initGates = true;
-}
-
-Task.initStackFlag = false;
-Task.checkStackFlag = false;
-
-Hwi.initStackFlag = false;
-Hwi.checkStackFlag = false;
-
-var segPlacement = xdc.loadCapsule("app_mem_seg_placement_ipu1_1.cfg");
-segPlacement.init();
\ No newline at end of file
diff --git a/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/mem_segment_definition.xs
deleted file mode 100644 (file)
index e617408..0000000
+++ /dev/null
@@ -1,264 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *  ======== mem_segment_definition.xs ========
- */
-
-
-function getMemSegmentDefinitionIPU_1_0()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_IPU1_0",
-    {
-          name: "CODE_CORE_IPU1_0",
-          base: 0x84000000,
-          len:  0x01000000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",
-    {
-          name: "PRIVATE_DATA_CORE_IPU1_0",
-          base: 0x85000000,
-          len:  0x01800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",
-    {
-          name: "HDVPSS_DESCRIPTOR_NON_CACHED",
-          base: 0xA1800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[6] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionIPU_1_1()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_IPU1_1",
-    {
-          name: "CODE_CORE_IPU1_1",
-          base: 0x86800000,
-          len:  0x01000000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",
-    {
-          name: "PRIVATE_DATA_CORE_IPU1_1",
-          base: 0x87800000,
-          len:  0x01800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionDSP_1()
-{
-    var memory = new Array();
-
-    memory[0] = ["CODE_CORE_DSP1",
-    {
-          name: "CODE_CORE_DSP1",
-          base: 0x83100000,
-          len:  0x00700000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[1] = ["PRIVATE_DATA_CORE_DSP1",
-    {
-          name: "PRIVATE_DATA_CORE_DSP1",
-          base: 0x83800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[2] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[3] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[4] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[5] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
-
-function getMemSegmentDefinitionHOST()
-{
-    var memory = new Array();
-
-    memory[8] = ["CODE_CORE_HOST",
-    {
-          name: "CODE_CORE_HOST",
-          base: 0x89000000,
-          len:  0x00800000,
-          space: "code",
-          access: "RWX"
-    }];
-
-    memory[9] = ["PRIVATE_DATA_CORE_HOST",
-    {
-          name: "PRIVATE_DATA_CORE_HOST",
-          base: 0x89800000,
-          len:  0x00800000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[10] = ["SHARED_MEM",
-    {
-          name: "SHARED_MEM",
-          base: 0xA2000000,
-          len:  0x01000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[11] = ["SHARED_FRAME_BUFFER",
-    {
-          name: "SHARED_FRAME_BUFFER",
-          base: 0x8A000000,
-          len:  0x04000000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    memory[12] = ["SHARED_CTRL",
-    {
-          name: "SHARED_CTRL",
-          base: 0xA0000000,
-          len:  0x01000000,
-          space: "code/data",
-          access: "RWX"
-    }];
-
-    memory[13] = ["SHARED_LOG_MEM",
-    {
-          name: "SHARED_LOG_MEM",
-          base: 0xA1000000,
-          len:  0x00700000,
-          space: "data",
-          access: "RWX"
-    }];
-
-    return (memory);
-}
diff --git a/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/platform.xs b/examples/edma3_driver/evmTDA3xx_M4/rtsc_config/platform.xs
deleted file mode 100644 (file)
index 4f1b3df..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-/*******************************************************************************
- *                                                                             *
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
- *                        ALL RIGHTS RESERVED                                  *
- *                                                                             *
- ******************************************************************************/
-
-/*
- *  ======== platform.xs ========
- */
-
-var Build = xdc.useModule('xdc.bld.BuildEnvironment');
-
-var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
-
-Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_0"] =
-{
-       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
-       codeMemory:"CODE_CORE_IPU1_0",
-       dataMemory:"PRIVATE_DATA_CORE_IPU1_0",
-       stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_1"] =
-{
-       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
-       codeMemory:"CODE_CORE_IPU1_1",
-       dataMemory:"PRIVATE_DATA_CORE_IPU1_1",
-       stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:DSP_1"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
-    codeMemory:"CODE_CORE_DSP1",
-    dataMemory:"PRIVATE_DATA_CORE_DSP1",
-    stackMemory:"PRIVATE_DATA_CORE_DSP1"
-};
-
-Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
-{
-    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
-    codeMemory:"CODE_CORE_HOST",
-    dataMemory:"PRIVATE_DATA_CORE_HOST",
-    stackMemory:"PRIVATE_DATA_CORE_HOST"
-};
diff --git a/examples/edma3_driver/evmTDA3xx_M4/sample_app/linker.cmd b/examples/edma3_driver/evmTDA3xx_M4/sample_app/linker.cmd
deleted file mode 100644 (file)
index 5062f6d..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-SECTIONS
-{
-//    .my_sect_iram > EXT_RAM
-//    .my_sect_ddr  > EXT_RAM
-//    .resetVecs  > L2_RAM
-}
index 26e266a32a24749b8aac5e9a9ecde4c1fadb9b05..098e29c917942872a7e91797e59b24a211928e74 100755 (executable)
@@ -195,7 +195,7 @@ ifdef MODULE_NAME
 
 # Clean Object and Library (archive) directories
 clean :
-       $(RM) -rf $(OBJDIR)/* $(DEPDIR)/* $(LIBDIR)/*
+       $(RM) -f $(OBJDIR)/* $(DEPDIR)/* $(LIBDIR)/*
 
 # Create dependencies list to ultimately create module archive library file
 ifeq ($(PLATFORM), $(filter $(PLATFORM),tci6636k2h-evm tci6638k2k-evm tci6630k2l-evm c66ak2e-evm))
@@ -214,7 +214,7 @@ else
 # Clean Object, Binary and Configuro generated directories
 clean :
        $(RM) -rf $(CONFIGURO_DIR)
-       $(RM) -rf $(OBJDIR)/* $(DEPDIR)/*
+       $(RM) -f $(OBJDIR)/* $(DEPDIR)/*
 
 # Create dependencies list to ultimately create application executable binary
 $(CORE) : $(OBJDIR) $(BINDIR) $(DEPDIR) $(CONFIGURO_DIR) $(PKG_LIST) $(BINDIR)/$(APP_NAME)_$(CORE)_$(PROFILE_$(CORE)).$(EXEEXT)
index 67a87d75cec7a4d9ceeaef7b9291b379e37e7ed5..6cca5ca5f471148ba1fa4464da3b20ebfd35de5d 100755 (executable)
@@ -12,7 +12,7 @@ INTERNAL_SW_ROOT ?= E:/EDMA/edma3_lld_02_11_07_01
 # Directory where all external (imported) software packages are located; typically 
 #  those that are NOT checked into version controlled repository. In this case,
 #  compiler tool chains, BIOS, XDC, Syslink, IPC, FC, CE, drivers, codecs, etc.
-EXTERNAL_SW_ROOT ?= C:/PROGRA~2/TEXASI~1
+EXTERNAL_SW_ROOT ?= C:/PROGRA~1/TEXASI~1
 
 # Destination root directory.
 #   - specify the directory where you want to place the object, archive/library,
@@ -23,32 +23,23 @@ EXTERNAL_SW_ROOT ?= C:/PROGRA~2/TEXASI~1
 # Utilities directory. This is required only if the build machine is Windows.
 #   - specify the installation directory of utility which supports POSIX commands
 #     (eg: Cygwin installation or MSYS installation).
-UTILS_INSTALL_DIR = $(EXTERNAL_SW_ROOT)/xdctools_3_25_05_94
+UTILS_INSTALL_DIR = $(EXTERNAL_SW_ROOT)/xdctools_3_25_04_88
 
 # Set path separator, etc based on the OS
-# On windows if sh.exe is installed (cygwin installs) make will execute
-# commands on sh or it executes on windows cmd prompt. When executing on sh,
-# unix style command seperator is used.
 ifeq ($(OS),Windows_NT)
   PATH_SEPARATOR = ;
   UTILSPATH = $(UTILS_INSTALL_DIR)/bin/
-  ifeq (cygwin,$(findstring cygwin,$(PATH)))
-  COMMAND_SEPERATOR = ;
-  else
-  COMMAND_SEPERATOR = &
-  endif
 else 
   # else, assume it is linux
   PATH_SEPARATOR = :
-  COMMAND_SEPERATOR = ;
 endif
 
 # BIOS
-bios_PATH = $(EXTERNAL_SW_ROOT)/bios_6_37_01_24
+bios_PATH = $(EXTERNAL_SW_ROOT)/bios_6_37_00_16_eng
 bios_INCLUDE = $(bios_PATH)/packages
 
 # XDC
-xdc_PATH = $(EXTERNAL_SW_ROOT)/xdctools_3_25_05_94
+xdc_PATH = $(EXTERNAL_SW_ROOT)/xdctools_3_25_04_88
 xdc_INCLUDE = $(xdc_PATH)/packages
 
 # EDMA3 LLD
@@ -59,29 +50,29 @@ include $(edma3_lld_PATH)/packages/component.mk
 # Tools paths
 #
 # Cortex-M3
-CODEGEN_PATH_M3 = $(EXTERNAL_SW_ROOT)/TMS470_5.1.1
+CODEGEN_PATH_M3 = $(EXTERNAL_SW_ROOT)/TIARMC~1.2
 # Cortex-M4
-CODEGEN_PATH_M4 = $(EXTERNAL_SW_ROOT)/TMS470_5.1.1
+CODEGEN_PATH_M4 = $(EXTERNAL_SW_ROOT)/TIARMC~1.2
 # Cortex-A8
-CODEGEN_PATH_A8 = $(EXTERNAL_SW_ROOT)/TMS470_5.1.1
+CODEGEN_PATH_A8 = $(EXTERNAL_SW_ROOT)/TIARMC~1.2
 # Cortex-A8 GCC
-CODEGEN_PATH_A8_GCC = $(EXTERNAL_SW_ROOT)/linaro_4.7.2012q4
+CODEGEN_PATH_A8_GCC = C:/PROGRA~1/GNUTOO~1/4F700~1.720
 
 # Cortex-A15
-CODEGEN_PATH_A15 = $(EXTERNAL_SW_ROOT)/linaro_4.7.2012q4
+CODEGEN_PATH_A15 = C:/PROGRA~1/GNUTOO~1/4F700~1.720
 # Cortex-A15_GCC
 CODEGEN_PATH_A15_GCC = $(EXTERNAL_SW_ROOT)/gcc-linaro-arm-linux-gnueabihf-4.7-2013.03-20130313_linux/
 
 # ARM-9
-CODEGEN_PATH_ARM9 = $(EXTERNAL_SW_ROOT)/TMS470_5.1.1
+CODEGEN_PATH_ARM9 = $(EXTERNAL_SW_ROOT)/TIARMC~1.2
 
 # DSP - Since same toolchain does not support COFF and ELF, there are two entries
 #        This would go away when one version supports both formats
-CODEGEN_PATH_DSP = $(EXTERNAL_SW_ROOT)/C6000_7.4.4
-CODEGEN_PATH_DSPELF = $(EXTERNAL_SW_ROOT)/C6000_7.4.4
+CODEGEN_PATH_DSP = $(EXTERNAL_SW_ROOT)/C6000C~2.1
+CODEGEN_PATH_DSPELF = $(EXTERNAL_SW_ROOT)/C6000C~2.1
 
 # ARP32
-CODEGEN_PATH_ARP32 = $(EXTERNAL_SW_ROOT)/ARP32_1.0.2
+CODEGEN_PATH_ARP32 = $(EXTERNAL_SW_ROOT)/ARP32C~1.2
 
 # Commands commonly used within the make files
 
index cde47ea60d82276e369abe6ffd076a47acc34440..3acb963deb40bc4929ffc60fa070540c0afb6dd9 100755 (executable)
 # Derive SOC from PLATFORM
 #
 
-# tda2xx (Vayu) EVM
+# tda2xx (Vayu) Simulator
 ifeq ($(PLATFORM),tda2xx-evm)
  SOC = tda2xx
  PLATFORM_XDC = "ti.platforms.evmDRA7XX"
 endif
 
-# tda3xx (ADAS low)
-ifeq ($(PLATFORM),tda3xx-evm)
- SOC = tda3xx
- PLATFORM_XDC = "ti.platforms.evmDRA7XX"
-endif
-
-#  dra72x (j6Eco)
-ifeq ($(PLATFORM),dra72x-evm)
- SOC = dra72x
- PLATFORM_XDC = "ti.platforms.evmDRA7XX"
-endif
-
 # ti816x (Netra) catalog EVM
 ifeq ($(PLATFORM),ti816x-evm)
  SOC = ti816x
@@ -218,12 +206,6 @@ ifeq ($(CORE),c6xdsp)
  ifeq ($(SOC),tda2xx)
   ISA = 66
  endif
- ifeq ($(SOC),tda3xx)
-  ISA = 66
- endif
- ifeq ($(SOC),dra72x)
-  ISA = 66
- endif
  ifeq ($(SOC),ti814x)
   ISA = 674
  endif
index 3f785ddf0e13dde326904390eaf82f9b4150d137..7e0929f731e4da4b91037023e7d26ce5f66a2b2c 100644 (file)
@@ -155,7 +155,7 @@ else
 endif\r
 \r
 # XDC specific - assemble XDC-Configuro command\r
-CONFIGURO_CMD = $(xdc_PATH)/xs xdc.tools.configuro -o $(CONFIGURO_DIR) -t $(TARGET_XDC) -p "$(PLATFORM_XDC_NAME)" \
+CONFIGURO_CMD = $(xdc_PATH)/xs xdc.tools.configuro --generationOnly -o $(CONFIGURO_DIR) -t $(TARGET_XDC) -p "$(PLATFORM_XDC_NAME)" \\r
                -r $(PROFILE_$(CORE)) -c $(CODEGEN_PATH_A15) -b $(CONFIG_BLD_FILE) $(XDC_CFG_FILE_NAME)\r
 _XDC_GREP_STRING = \"$(XDC_GREP_STRING)\"\r
 EGREP_CMD = $(EGREP) -ivw $(XDC_GREP_STRING) $(XDCLNKCMD_FILE)\r
@@ -195,6 +195,12 @@ $(LNKCMD_FILE) :
 #      ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)\r
 #      $(EGREP_CMD) > $(LNKCMD_FILE)\r
  \r
+ifndef MODULE_NAME\r
+$(CONFIGURO_DIR)/package/cfg/$(CFG_COBJ_XDC) : $(CFG_C_XDC)\r
+       $(ECHO) \# Compiling generated $< to $@ ...\r
+       $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -o $(CONFIGURO_DIR)/package/cfg/$(CFG_COBJ_XDC) $(CFG_C_XDC)\r
+endif\r
+\r
 # Include dependency make files that were generated by $(CC)\r
 -include $(SRCS:%.c=$(DEPDIR)/%.P)\r
 # Nothing beyond this point\r
index 3c0f265a062008846d9dcbbfed49c9b4ca983a4f..fb219f4c9ef674e6cc423a24e0266f85e0572bdc 100755 (executable)
@@ -9,7 +9,7 @@ requires ti.sdo.edma3.drv;
 requires ti.sdo.edma3.drv.sample;
 
 /*!
- *  ======== edma3_lld_02_11_12_16 ========
+ *  ======== edma3_lld_02_11_11_15 ========
  */
-package edma3_lld_02_11_12_16 [02, 02, 12] {
+package edma3_lld_02_11_11_15 [02, 02, 11] {
 }
index 450ca486d8d04c97766d141bddb7bbb0f14dc192..85a71d9c4ad5d5360752328ac471d8059fefa697 100755 (executable)
@@ -65,54 +65,26 @@ edma3_lld_EXAMPLES_LIST = edma3_drv_ti816x-evm_m3_example edma3_drv_c6472-evm_64
 
 
 ifeq ($(PLATFORM),)
-PLATFORM = dra72x-evm tda3xx-evm tda2xx-evm ti816x-evm ti814x-evm c6a811x-evm c6472-evm c6670-evm c6678-evm c6748-evm da830-evm omapl138-evm tci6486-evm tci6608-sim tci6616-sim tci6614-evm tci6614-sim c6657-evm c66ak2e-evm c6657-sim tci6638k2k-evm tci6630k2l-evm tci6638k2k-sim tci6636k2h-evm
+PLATFORM = tda2xx-evm ti816x-evm ti814x-evm c6a811x-evm c6472-evm c6670-evm c6678-evm c6748-evm da830-evm omapl138-evm tci6486-evm tci6608-sim tci6616-sim tci6614-evm tci6614-sim c6657-evm c66ak2e-evm c6657-sim tci6638k2k-evm tci6630k2l-evm tci6638k2k-sim tci6636k2h-evm
 endif
 
 ifeq ($(TARGET),)
 TARGET = 674 m3 a8 64p 66 m4 a15 eve
-#edma3_lld_LIBS_ALL = edma3_lld_rm_generic
+edma3_lld_LIBS_ALL = edma3_lld_rm_generic
 endif
 
-tda2xx-evm_supported_targets = m4 a15 66 eve
-tda2xx-evm_m4_cores = m4
-tda2xx-evm_a15_cores = a15host
-tda2xx-evm_66_cores = c6xdsp
-tda2xx-evm_eve_cores = eve
-tda2xx-evm_m4_format_support = ELF
-tda2xx-evm_a15_format_support = ELF
-tda2xx-evm_66_format_support = ELF
-tda2xx-evm_eve_format_support = ELF
-#tda2xx-evm_profiles = debug release
-tda2xx-evm_m4_addn_params = "IPUCORE=1" "IPUCORE=0"
-
-tda3xx-evm_supported_targets = m4 66 eve
-tda3xx-evm_m4_cores = m4
-tda3xx-evm_66_cores = c6xdsp
-tda3xx-evm_eve_cores = eve
-tda3xx-evm_m4_format_support = ELF
-tda3xx-evm_66_format_support = ELF
-tda3xx-evm_eve_format_support = ELF
-
-dra72x-evm_supported_targets = a15 m4 66
-dra72x-evm_a15_cores = a15host
-dra72x-evm_m4_cores = m4
-dra72x-evm_66_cores = c6xdsp
-dra72x-evm_a15_format_support = ELF
-dra72x-evm_m4_format_support = ELF
-dra72x-evm_66_format_support = ELF
-
 #Prepare library list to build from the PLATFORM and TARGET
 ifeq ($(PLATFORM),generic)
 edma3_lld_LIBS_ALL = edma3_lld_rm_generic
 else
-edma3_lld_LIBS_ALL += edma3_lld_lib_target $(foreach plat, $(PLATFORM),$(foreach targ,$(TARGET),edma3_lld_$(plat)_$(targ)_libs))
+edma3_lld_LIBS_ALL += $(foreach plat, $(PLATFORM),$(foreach targ,$(TARGET),edma3_lld_$(plat)_$(targ)_libs))
 endif
 
 #Prepare Example list from PLATFORM and TARGET
 ifeq ($(ENDIAN),big)
 edma3_lld_EXAMPLES_LIST = $(foreach plat, $(PLATFORM),$(foreach targ,$(TARGET),edma3_drv_$(plat)_$(targ)_be_example))
 else
-edma3_lld_EXAMPLES_LIST = edma3_drv_example_target $(foreach plat, $(PLATFORM),$(foreach targ,$(TARGET),edma3_drv_$(plat)_$(targ)_example))
+edma3_lld_EXAMPLES_LIST = $(foreach plat, $(PLATFORM),$(foreach targ,$(TARGET),edma3_drv_$(plat)_$(targ)_example))
 endif
 
 
@@ -300,18 +272,4 @@ edma3_drv_tci6630k2l-evm_a15_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_d
 edma3_drv_tda2xx-evm_eve_example_EXAMPLES_RELPATH = examples/edma3_driver/evmtda2xx_EVE
 edma3_drv_tda2xx-evm_eve_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda2xx-evm_eve_example_EXAMPLES_RELPATH)
 
-edma3_drv_tda3xx-evm_66_example_EXAMPLES_RELPATH = examples/edma3_driver/evmTDA3xx_DSP
-edma3_drv_tda3xx-evm_66_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda3xx-evm_66_example_EXAMPLES_RELPATH)
-edma3_drv_tda3xx-evm_m4_example_EXAMPLES_RELPATH = examples/edma3_driver/evmTDA3xx_M4
-edma3_drv_tda3xx-evm_m4_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda3xx-evm_m4_example_EXAMPLES_RELPATH)
-edma3_drv_tda3xx-evm_eve_example_EXAMPLES_RELPATH = examples/edma3_driver/evmTDA3xx_EVE
-edma3_drv_tda3xx-evm_eve_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda3xx-evm_eve_example_EXAMPLES_RELPATH)
-
-edma3_drv_dra72x-evm_a15_example_EXAMPLES_RELPATH = examples/edma3_driver/evmDRA72x_a15
-edma3_drv_dra72x-evm_a15_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_dra72x-evm_a15_example_EXAMPLES_RELPATH)
-edma3_drv_dra72x-evm_66_example_EXAMPLES_RELPATH = examples/edma3_driver/evmDRA72x_DSP
-edma3_drv_dra72x-evm_66_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_dra72x-evm_66_example_EXAMPLES_RELPATH)
-edma3_drv_dra72x-evm_m4_example_EXAMPLES_RELPATH = examples/edma3_driver/evmDRA72x_M4
-edma3_drv_dra72x-evm_m4_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_dra72x-evm_m4_example_EXAMPLES_RELPATH)
-
 # Nothing beyond this point
index d187409c28b2afae4d853d6f8e98bcdafaf9c498..bd786e88eb1e7290ab3ab922f4f26e999df91e66 100755 (executable)
@@ -34,7 +34,7 @@ edma3_lld_PKG_LIST_ALL = $(foreach PKG,$(edma3_lld_COMP_LIST_ALL),$($(PKG)_PKG_L
 CLEANALL_TARGETS = $(addsuffix _clean, $(edma3_lld_LIBS_ALL))
 CLEANALL_EXAMPLES = $(addsuffix _clean, $(edma3_lld_EXAMPLES_LIST))
 
-.PHONY : $(edma3_lld_LIBS_ALL) $(edma3_lld_EXAMPLES_LIST) $(CLEANALL_TARGETS) $(CLEANALL_EXAMPLES) edma3_lld_$(PLATFORM)_$(TARGET)_libs edma3_drv_$(PLATFORM)_$(TARGET)_example edma3_lld_lib_target edma3_drv_example_target
+.PHONY : $(edma3_lld_LIBS_ALL) $(edma3_lld_EXAMPLES_LIST) $(CLEANALL_TARGETS) $(CLEANALL_EXAMPLES)
 
 all: libs examples
 
@@ -56,125 +56,227 @@ cleanexamples: $(CLEANALL_EXAMPLES)
 #
 #=======================================================================================================================================
 
+
+#=======================================================================================================================================
+#To Build libs For Platform tda2xx-evm Target 66
+edma3_lld_tda2xx-evm_66_libs: edma3_lld_tda2xx-evm_66_libs_drv edma3_lld_tda2xx-evm_66_libs_rm edma3_lld_tda2xx-evm_66_libs_drvsample edma3_lld_tda2xx-evm_66_libs_rmsample
+edma3_lld_tda2xx-evm_66_libs_drv:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making 66:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Making 66:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+endif
+edma3_lld_tda2xx-evm_66_libs_rm:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+endif
+edma3_lld_tda2xx-evm_66_libs_drvsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+endif
+edma3_lld_tda2xx-evm_66_libs_rmsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+endif
+
+#To Clean libs For Platform tda2xx-evm Target 66
+edma3_lld_tda2xx-evm_66_libs_clean: edma3_lld_tda2xx-evm_66_libs_drv_clean edma3_lld_tda2xx-evm_66_libs_rm_clean edma3_lld_tda2xx-evm_66_libs_drvsample_clean edma3_lld_tda2xx-evm_66_libs_rmsample_clean
+edma3_lld_tda2xx-evm_66_libs_drv_clean:
+       $(ECHO) \# Cleaning 66:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning 66:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+edma3_lld_tda2xx-evm_66_libs_rm_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+edma3_lld_tda2xx-evm_66_libs_drvsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+edma3_lld_tda2xx-evm_66_libs_rmsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+
 #=======================================================================================================================================
-ifeq (,$($(PLATFORM)_$(TARGET)_profiles))
-ifeq (,$($(PLATFORM)_profiles))
-$(PLATFORM)_$(TARGET)_profiles = debug release
-else
-$(PLATFORM)_$(TARGET)_profiles = $($(PLATFORM)_profiles)
-endif
-endif
-
-edma3_lld_lib_target:
-       $(foreach plat, $(PLATFORM),$(foreach targ,$(TARGET),\
-        $(MAKE) -C $(edma3_lld_PATH)/packages edma3_lld_$(plat)_$(targ)_libs PLATFORM=$(plat) TARGET=$(targ) $(COMMAND_SEPERATOR)\
-    ))
-
-edma3_lld_$(PLATFORM)_$(TARGET)_libs:
-ifeq ($(TARGET),$(findstring $(TARGET),$($(PLATFORM)_supported_targets)))
-       $(foreach current_core, $($(PLATFORM)_$(TARGET)_cores),\
-        $(foreach current_format, $($(PLATFORM)_$(TARGET)_format_support),\
-            $(foreach current_profile, $($(PLATFORM)_$(TARGET)_profiles),\
-                echo \# Making $(PLATFORM):$(current_core):$(current_profile):$(current_format):edma3_lld_drv$(COMMAND_SEPERATOR)\
-                $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-                echo \# Making $(PLATFORM):$(current_core):$(current_profile):$(current_format):edma3_lld_drv_sample$(COMMAND_SEPERATOR)\
-                $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-                echo \# Making $(PLATFORM):$(current_core):$(current_profile):$(current_format):edma3_lld_rm$(COMMAND_SEPERATOR)\
-                $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-                echo \# Making $(PLATFORM):$(current_core):$(current_profile):$(current_format):edma3_lld_rm_sample$(COMMAND_SEPERATOR)\
-                $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-            )))
-endif
-
-edma3_lld_lib_target_clean:
-       $(foreach plat, $(PLATFORM),$(foreach targ,$(TARGET),\
-        $(MAKE) -C $(edma3_lld_PATH)/packages edma3_lld_$(plat)_$(targ)_libs_clean PLATFORM=$(plat) TARGET=$(targ) $(COMMAND_SEPERATOR)\
-    ))
-
-ifeq (,$($(PLATFORM)_$(TARGET)_profiles))
-ifeq (,$($(PLATFORM)_profiles))
-$(PLATFORM)_$(TARGET)_profiles = debug release
-else
-$(PLATFORM)_$(TARGET)_profiles = $($(PLATFORM)_profiles)
-endif
-endif
-edma3_lld_$(PLATFORM)_$(TARGET)_libs_clean:
-ifeq ($(TARGET),$(findstring $(TARGET),$($(PLATFORM)_supported_targets)))
-       $(foreach current_core, $($(PLATFORM)_$(TARGET)_cores),\
-        $(foreach current_format, $($(PLATFORM)_$(TARGET)_format_support),\
-            $(foreach current_profile, $($(PLATFORM)_$(TARGET)_profiles),\
-                echo \# Cleaning $(PLATFORM):$(current_core):$(current_profile):$(current_format):edma3_lld_drv$(COMMAND_SEPERATOR)\
-                $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-                echo \# Cleaning $(PLATFORM):$(current_core):$(current_profile):$(current_format):edma3_lld_drv_sample$(COMMAND_SEPERATOR)\
-                $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-                echo \# Cleaning $(PLATFORM):$(current_core):$(current_profile):$(current_format):edma3_lld_rm$(COMMAND_SEPERATOR)\
-                $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-                echo \# Cleaning $(PLATFORM):$(current_core):$(current_profile):$(current_format):edma3_lld_rm_sample$(COMMAND_SEPERATOR)\
-                $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-            )))
-endif
-
-edma3_drv_example_target:
-       $(foreach plat, $(PLATFORM),$(foreach targ,$(TARGET),\
-        $(MAKE) -C $(edma3_lld_PATH)/packages edma3_drv_$(plat)_$(targ)_example PLATFORM=$(plat) TARGET=$(targ)$(COMMAND_SEPERATOR)\
-    ))
-
-#ifeq (,$($(PLATFORM)_$(TARGET)_addn_params))
-#$(PLATFORM)_$(TARGET)_addn_params = "test"
-#endif
-
-ifeq (,$($(PLATFORM)_$(TARGET)_profiles))
-ifeq (,$($(PLATFORM)_profiles))
-$(PLATFORM)_$(TARGET)_profiles = debug release
-else
-$(PLATFORM)_$(TARGET)_profiles = $($(PLATFORM)_profiles)
-endif
-endif
-edma3_drv_$(PLATFORM)_$(TARGET)_example:
-ifeq ($(TARGET),$(findstring $(TARGET),$($(PLATFORM)_supported_targets)))
-ifneq (,$($(PLATFORM)_$(TARGET)_addn_params))
-       $(foreach current_core, $($(PLATFORM)_$(TARGET)_cores),\
-        $(foreach current_format, $($(PLATFORM)_$(TARGET)_format_support),\
-            $(foreach current_profile, $($(PLATFORM)_$(TARGET)_profiles),\
-                $(foreach addn_param, $($(PLATFORM)_$(TARGET)_addn_params),\
-                    echo \# Configuring XDC packages for $@ $(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-                    $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format) $(addn_param)$(COMMAND_SEPERATOR)\
-                    echo \# Making example $@ $(current_profile)$(COMMAND_SEPERATOR)\
-                    $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format) $(addn_param)$(COMMAND_SEPERATOR)\
-                ))))
-else
-       $(foreach current_core, $($(PLATFORM)_$(TARGET)_cores),\
-        $(foreach current_format, $($(PLATFORM)_$(TARGET)_format_support),\
-            $(foreach current_profile, $($(PLATFORM)_$(TARGET)_profiles),\
-                    echo \# Configuring XDC packages for $@ $(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-                    $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-                    echo \# Making example $@ $(current_profile)$(COMMAND_SEPERATOR)\
-                    $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile) FORMAT=$(current_format)$(COMMAND_SEPERATOR)\
-                )))
-endif
-endif
-
-edma3_drv_example_target_clean:
-       $(foreach plat, $(PLATFORM),$(foreach targ,$(TARGET),\
-        $(MAKE) -C $(edma3_lld_PATH)/packages edma3_drv_$(plat)_$(targ)_example_clean PLATFORM=$(plat) TARGET=$(targ) $(COMMAND_SEPERATOR)\
-    ))
-
-ifeq (,$($(PLATFORM)_$(TARGET)_profiles))
-ifeq (,$($(PLATFORM)_profiles))
-$(PLATFORM)_$(TARGET)_profiles = debug release
-else
-$(PLATFORM)_$(TARGET)_profiles = $($(PLATFORM)_profiles)
-endif
-endif
-edma3_drv_$(PLATFORM)_$(TARGET)_example_clean:
-ifeq ($(TARGET),$(findstring $(TARGET),$($(PLATFORM)_supported_targets)))
-       $(foreach current_core, $($(PLATFORM)_$(TARGET)_cores),\
-        $(foreach current_profile, $($(PLATFORM)_$(TARGET)_profiles),\
-            echo \# cleaning example $@:$(current_profile)$(COMMAND_SEPERATOR)\
-            $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=$(PLATFORM) CORE=$(current_core) PROFILE_$(current_core)=$(current_profile)$(COMMAND_SEPERATOR)\
-        ))
+#To Build libs For Platform tda2xx-evm Target m4
+edma3_lld_tda2xx-evm_m4_libs: edma3_lld_tda2xx-evm_m4_libs_drv edma3_lld_tda2xx-evm_m4_libs_rm edma3_lld_tda2xx-evm_m4_libs_drvsample edma3_lld_tda2xx-evm_m4_libs_rmsample
+edma3_lld_tda2xx-evm_m4_libs_drv:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making m4:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Making m4:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+edma3_lld_tda2xx-evm_m4_libs_rm:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+edma3_lld_tda2xx-evm_m4_libs_drvsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+edma3_lld_tda2xx-evm_m4_libs_rmsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+
+#To Clean libs For Platform tda2xx-evm Target m4
+edma3_lld_tda2xx-evm_m4_libs_clean: edma3_lld_tda2xx-evm_m4_libs_drv_clean edma3_lld_tda2xx-evm_m4_libs_rm_clean edma3_lld_tda2xx-evm_m4_libs_drvsample_clean edma3_lld_tda2xx-evm_m4_libs_rmsample_clean
+edma3_lld_tda2xx-evm_m4_libs_drv_clean:
+       $(ECHO) \# Cleaning m4:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Cleaning m4:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+edma3_lld_tda2xx-evm_m4_libs_rm_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+edma3_lld_tda2xx-evm_m4_libs_drvsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+edma3_lld_tda2xx-evm_m4_libs_rmsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+
+#=======================================================================================================================================
+#To Build libs For Platform tda2xx-evm Target a15
+edma3_lld_tda2xx-evm_a15_libs: edma3_lld_tda2xx-evm_a15_libs_drv edma3_lld_tda2xx-evm_a15_libs_rm edma3_lld_tda2xx-evm_a15_libs_drvsample edma3_lld_tda2xx-evm_a15_libs_rmsample
+edma3_lld_tda2xx-evm_a15_libs_drv:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making a15:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Making a15:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+endif
+edma3_lld_tda2xx-evm_a15_libs_rm:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+endif
+edma3_lld_tda2xx-evm_a15_libs_drvsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+endif
+edma3_lld_tda2xx-evm_a15_libs_rmsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
 endif
 
+#To Clean libs For Platform tda2xx-evm Target a15
+edma3_lld_tda2xx-evm_a15_libs_clean: edma3_lld_tda2xx-evm_a15_libs_drv_clean edma3_lld_tda2xx-evm_a15_libs_rm_clean edma3_lld_tda2xx-evm_a15_libs_drvsample_clean edma3_lld_tda2xx-evm_a15_libs_rmsample_clean
+edma3_lld_tda2xx-evm_a15_libs_drv_clean:
+       $(ECHO) \# Cleaning a15:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Cleaning a15:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+edma3_lld_tda2xx-evm_a15_libs_rm_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+edma3_lld_tda2xx-evm_a15_libs_drvsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+edma3_lld_tda2xx-evm_a15_libs_rmsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+
+#=======================================================================================================================================
+#To Build libs For Platform tda2xx-evm Target EVE
+edma3_lld_tda2xx-evm_eve_libs: edma3_lld_tda2xx-evm_eve_libs_drv edma3_lld_tda2xx-evm_eve_libs_rm edma3_lld_tda2xx-evm_eve_libs_drvsample edma3_lld_tda2xx-evm_eve_libs_rmsample
+edma3_lld_tda2xx-evm_eve_libs_drv:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making eve:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+       $(ECHO) \# Making eve:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+edma3_lld_tda2xx-evm_eve_libs_rm:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+edma3_lld_tda2xx-evm_eve_libs_drvsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+edma3_lld_tda2xx-evm_eve_libs_rmsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+
+#To Clean libs For Platform tda2xx-evm Target eve
+edma3_lld_tda2xx-evm_eve_libs_clean: edma3_lld_tda2xx-evm_eve_libs_drv_clean edma3_lld_tda2xx-evm_eve_libs_rm_clean edma3_lld_tda2xx-evm_eve_libs_drvsample_clean edma3_lld_tda2xx-evm_eve_libs_rmsample_clean
+edma3_lld_tda2xx-evm_eve_libs_drv_clean:
+       $(ECHO) \# Cleaning eve:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+       $(ECHO) \# Cleaning eve:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+edma3_lld_tda2xx-evm_eve_libs_rm_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+edma3_lld_tda2xx-evm_eve_libs_drvsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+edma3_lld_tda2xx-evm_eve_libs_rmsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+    
 #=======================================================================================================================================
 #To Build libs For Platform ti816x-evm Target 674
 edma3_lld_ti816x-evm_674_libs: edma3_lld_ti816x-evm_674_libs_drv edma3_lld_ti816x-evm_674_libs_rm edma3_lld_ti816x-evm_674_libs_drvsample edma3_lld_ti816x-evm_674_libs_rmsample
@@ -2940,6 +3042,52 @@ ifeq ($(FORMAT),ELF)
        $(ECHO) \# Making example $@:release
        $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6a811x-evm CORE=m3vpss PROFILE_m3vpss=release
 endif
+edma3_drv_tda2xx-evm_66_example:
+       $(ECHO) \# Configuring XDC packages for $@:m4:debug 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug     
+
+       $(ECHO) \# Configuring XDC packages for $@:m4:release 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+       $(ECHO) \# Making example $@:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+
+edma3_drv_tda2xx-evm_m4_example:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Configuring XDC packages for $@:m4:debug 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug IPUCORE=0
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug     IPUCORE=0
+
+       $(ECHO) \# Configuring XDC packages for $@:m4:release 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release IPUCORE=0
+       $(ECHO) \# Making example $@:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release IPUCORE=0
+
+       $(ECHO) \# Configuring XDC packages for $@:m4:debug 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug IPUCORE=1
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug IPUCORE=1
+
+       $(ECHO) \# Configuring XDC packages for $@:m4:release 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release IPUCORE=1
+       $(ECHO) \# Making example $@:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release IPUCORE=1
+endif
+
+edma3_drv_tda2xx-evm_a15_example:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Configuring XDC packages for $@:a15host:debug 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug   
+
+       $(ECHO) \# Configuring XDC packages for $@:a15host:release 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+       $(ECHO) \# Making example $@:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+endif
 
 edma3_drv_tci6630k2l-evm_a15_example:
 ifeq ($(FORMAT),ELF)
@@ -2992,6 +3140,19 @@ ifeq ($(FORMAT),ELF)
        $(ECHO) \# Making example $@:release
        $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6638k2k-evm CORE=a15host PROFILE_a15host=release TOOLCHAIN_a15=GCC
 endif
+edma3_drv_tda2xx-evm_eve_example:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Configuring XDC packages for $@:eve:debug $($@_EXAMPLES_PATH)
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug   
+
+       $(ECHO) \# Configuring XDC packages for $@:eve:release 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+       $(ECHO) \# Making example $@:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+
 
 #=======================================================================================================================================
 #
@@ -3109,6 +3270,22 @@ ifeq ($(FORMAT),ELF)
        $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
 endif
 
+edma3_drv_tda2xx-evm_m4_example_clean:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Cleaning example $@:debug
+       $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Cleaning example $@:release
+       $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+
+edma3_drv_tda2xx-evm_eve_example_clean:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Cleaning example $@:debug
+       $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+       $(ECHO) \# Cleaning example $@:release
+       $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+
 edma3_drv_ti816x-evm_m3_example_clean:
 ifeq ($(FORMAT),ELF)
        $(ECHO) \# Cleaning example $@:debug
index b829dd16dd2f1e9ab00a5a09830d7dcf05b6a103..0c1680552f7a159f73614206e98e751089587d7b 100755 (executable)
Binary files a/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver_Datasheet.doc and b/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver_Datasheet.doc differ
index 6e85f09cbe3414c6dff31260aeec90d5edd9a3ea..4e8a61b5e8afdca08281b3fea7d300068e1635d9 100755 (executable)
Binary files a/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver_User_Guide.doc and b/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver_User_Guide.doc differ
index bf0dba1a07975593fa2c95d0f6e7273f13db2845..8a58fee47813ee0db0c7ec0e7c3653af441a7f1b 100755 (executable)
@@ -102,13 +102,13 @@ extern "C" {
   * format:
   *  0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD) 
   */
-#define EDMA3_LLD_DRV_VERSION_ID                   (0x020B0C10)
+#define EDMA3_LLD_DRV_VERSION_ID                   (0x020B0B0D)
 
 /**
  * @brief   This is the version string which describes the EDMA3 LLD along with the
  * date and build information.
  */
-#define EDMA3_LLD_DRV_VERSION_STR                  "EDMA3 LLD Revision: 02.11.12.16"
+#define EDMA3_LLD_DRV_VERSION_STR                  "EDMA3 LLD Revision: 02.11.11.15"
 
 
 /** @brief EDMA3 Driver Error Codes Base define */
@@ -682,7 +682,7 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * DMA channel from the pool of (owned && non_reserved && available_right_now)
  * DMA channels will be chosen and returned.
  */
-#define EDMA3_DRV_DMA_CHANNEL_ANY                   1002U
+#define EDMA3_DRV_DMA_CHANNEL_ANY                   1002u
 
 /**
  * Used to specify any available QDMA Channel while requesting
@@ -690,7 +690,7 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * QDMA channel from the pool of (owned && non_reserved && available_right_now)
  * QDMA channels will be chosen and returned.
  */
-#define EDMA3_DRV_QDMA_CHANNEL_ANY                  1003U
+#define EDMA3_DRV_QDMA_CHANNEL_ANY                  1003u
 
 /**
  * Used to specify any available TCC while requesting
@@ -699,7 +699,7 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * TCC from the pool of (owned && non_reserved && available_right_now)
  * TCCs will be chosen and returned.
  */
-#define EDMA3_DRV_TCC_ANY                           1004U
+#define EDMA3_DRV_TCC_ANY                           1004u
 
 /**
  * Used to specify any available PaRAM Set while requesting
@@ -707,7 +707,7 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * PaRAM Set from the pool of (owned && non_reserved && available_right_now)
  * PaRAM Sets will be chosen and returned.
  */
-#define EDMA3_DRV_LINK_CHANNEL                      1005U
+#define EDMA3_DRV_LINK_CHANNEL                      1005u
 
 /**
  * Used to specify any available PaRAM Set while requesting one. Used in the
@@ -717,7 +717,7 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
  * PaRAM Set from the pool of (owned && non_reserved && available_right_now)
  * PaRAM Sets will be chosen and returned.
  */
-#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC                                1006U
+#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC                                1006u
 
 /**
 @}
@@ -895,19 +895,19 @@ typedef enum
 /** QDMA Channel 0 */
 #define EDMA3_DRV_QDMA_CHANNEL_0    (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
 /** QDMA Channel 1 */
-#define EDMA3_DRV_QDMA_CHANNEL_1    (EDMA3_DRV_QDMA_CHANNEL_0+1U)
+#define EDMA3_DRV_QDMA_CHANNEL_1    (EDMA3_DRV_QDMA_CHANNEL_0+1u)
 /** QDMA Channel 2 */
-#define EDMA3_DRV_QDMA_CHANNEL_2    (EDMA3_DRV_QDMA_CHANNEL_0+2U)
+#define EDMA3_DRV_QDMA_CHANNEL_2    (EDMA3_DRV_QDMA_CHANNEL_0+2u)
 /** QDMA Channel 3 */
-#define EDMA3_DRV_QDMA_CHANNEL_3    (EDMA3_DRV_QDMA_CHANNEL_0+3U)
+#define EDMA3_DRV_QDMA_CHANNEL_3    (EDMA3_DRV_QDMA_CHANNEL_0+3u)
 /** QDMA Channel 4 */
-#define EDMA3_DRV_QDMA_CHANNEL_4    (EDMA3_DRV_QDMA_CHANNEL_0+4U)
+#define EDMA3_DRV_QDMA_CHANNEL_4    (EDMA3_DRV_QDMA_CHANNEL_0+4u)
 /** QDMA Channel 5 */
-#define EDMA3_DRV_QDMA_CHANNEL_5    (EDMA3_DRV_QDMA_CHANNEL_0+5U)
+#define EDMA3_DRV_QDMA_CHANNEL_5    (EDMA3_DRV_QDMA_CHANNEL_0+5u)
 /** QDMA Channel 6 */
-#define EDMA3_DRV_QDMA_CHANNEL_6    (EDMA3_DRV_QDMA_CHANNEL_0+6U)
+#define EDMA3_DRV_QDMA_CHANNEL_6    (EDMA3_DRV_QDMA_CHANNEL_0+6u)
 /** QDMA Channel 7 */
-#define EDMA3_DRV_QDMA_CHANNEL_7    (EDMA3_DRV_QDMA_CHANNEL_0+7U)
+#define EDMA3_DRV_QDMA_CHANNEL_7    (EDMA3_DRV_QDMA_CHANNEL_0+7u)
 
 /**
 @}
@@ -2983,13 +2983,13 @@ EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(uint32_t phyCtrllerInstId,
  * are used while returning the channel status from EDMA3_DRV_getChannelStatus().
  */
 /** Channel is clean; no pending event, completion interrupt and event miss interrupt */
-#define EDMA3_DRV_CHANNEL_CLEAN                                0x0000U
+#define EDMA3_DRV_CHANNEL_CLEAN                                0x0000u
 /** Pending event is detected on the DMA channel */
-#define EDMA3_DRV_CHANNEL_EVENT_PENDING                0x0001U
+#define EDMA3_DRV_CHANNEL_EVENT_PENDING                0x0001u
 /** Transfer completion interrupt is detected on the DMA/QDMA channel */
-#define EDMA3_DRV_CHANNEL_XFER_COMPLETE                0x0002U
+#define EDMA3_DRV_CHANNEL_XFER_COMPLETE                0x0002u
 /** Event miss error interrupt is detected on the DMA/QDMA channel */
-#define EDMA3_DRV_CHANNEL_ERR                          0x0004U
+#define EDMA3_DRV_CHANNEL_ERR                          0x0004u
 
 /**
 @}
@@ -3044,7 +3044,7 @@ EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh (EDMA3_DRV_Handle hEdma,
                                                 uint32_t linkCh,
                                                 uint32_t tcc);
 
-#define EDMA3_DRV_MAX_XBAR_EVENTS (63U)
+#define EDMA3_DRV_MAX_XBAR_EVENTS (63u)
 
 /**\struct  EDMA3_DRV_GblXbarToChanConfigParams
  * \brief   Init-time Configuration structure for EDMA3
index 1dfb67f653ca1dcf75e8b2ab3b3f2a04f30299f9..ba94122e179bbb9832c6ebcda44aeeda8d2df764 100755 (executable)
@@ -46,6 +46,6 @@ requires ti.sdo.edma3.rm;
 /*!
  *  ======== ti.sdo.edma3.drv ========
  */
-package ti.sdo.edma3.drv [02, 02, 12] {
+package ti.sdo.edma3.drv [02, 02, 11] {
     module DRV;
 }
index a3534db21cddfee02b9f3a55bde8683098d2e526..0b02f23de763ce3b0437874a3cf60612d20a771c 100755 (executable)
@@ -82,8 +82,6 @@ function getLibs(prog)
                         'TMS320TI816X',
                         'Vayu',
                         'DRA7XX'
-                        'TDA3XX'
-                        'DRA72X'
                     ];
 
     for (var i = 0; i < devices.length; i++)
index f11859ccb59e87f1013e1e190482c20106b14134..8e3bfeee6f55c81e02220e7a63e7cb2af5e96e67 100755 (executable)
@@ -23,7 +23,7 @@ endif
 # Example:
 #   SRCS_<core/SoC/platform-name> =
 #   CFLAGS_LOCAL_<core/SoC/platform-name> =
-ifeq ($(CORE),$(filter $(CORE), c6xdsp c66xdsp))
+ifeq ($(CORE),c6xdsp)
 SRCS_c6472-evm = sample_c6472_cfg.c sample_c6472_int_reg.c
 SRCS_tci6486-evm = sample_tci6486_cfg.c sample_tci6486_int_reg.c
 SRCS_tci6608-sim = sample_tci6608_cfg.c sample_tci6608_int_reg.c
@@ -47,17 +47,11 @@ CFLAGS_LOCAL_ti814x-evm = -DBUILD_CENTAURUS_DSP
 SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_int_reg.c
 CFLAGS_LOCAL_c6a811x-evm = -DBUILD_C6A811X_DSP
 SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_int_reg.c
-SRCS_tda2xx = sample_tda2xx_cfg.c sample_tda2xx_int_reg.c
-CFLAGS_LOCAL_tda2xx = -DBUILD_TDA2XX_DSP
-SRCS_tda3xx = sample_tda3xx_cfg.c sample_tda3xx_int_reg.c
-CFLAGS_LOCAL_tda3xx = -DBUILD_TDA3XX_DSP
-SRCS_dra72x = sample_dra72x_cfg.c sample_dra72x_int_reg.c
-CFLAGS_LOCAL_dra72x = -DBUILD_DRA72X_DSP
+SRCS_tda2xx-evm = sample_tda2xx_cfg.c sample_tda2xx_int_reg.c
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_DSP
 else
 SRCS_omapl138-evm = sample_omapl138_arm_cfg.c sample_omapl138_arm_int_reg.c
-SRCS_tda2xx = sample_tda2xx_cfg.c sample_tda2xx_arm_int_reg.c
-SRCS_tda3xx = sample_tda3xx_cfg.c sample_tda3xx_arm_int_reg.c
-SRCS_dra72x = sample_dra72x_cfg.c sample_dra72x_arm_int_reg.c
+SRCS_tda2xx-evm = sample_tda2xx_cfg.c sample_tda2xx_arm_int_reg.c
 endif
 
 ifeq ($(CORE),a8host)
@@ -87,21 +81,16 @@ SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_arm_int_reg.c
 SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_arm_int_reg.c
 endif
 
-ifeq ($(CORE),$(filter $(CORE), m4 m4vpss))
-CFLAGS_LOCAL_tda2xx = -DBUILD_TDA2XX_IPU
-CFLAGS_LOCAL_tda3xx = -DBUILD_TDA3XX_IPU
-CFLAGS_LOCAL_dra72x = -DBUILD_DRA72X_IPU
+ifeq ($(CORE),m4)
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_IPU
 endif
 
 ifeq ($(CORE),a15host)
-CFLAGS_LOCAL_tda2xx = -DBUILD_TDA2XX_MPU
-CFLAGS_LOCAL_dra72x = -DBUILD_DRA72X_MPU
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_MPU
 endif
 
 ifeq ($(CORE),eve)
-CFLAGS_LOCAL_tda2xx = -DBUILD_TDA2XX_EVE
-CFLAGS_LOCAL_tda3xx = -DBUILD_TDA3XX_EVE
-CFLAGS_LOCAL_dra72x = -DBUILD_DRA72X_EVE
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_EVE
 endif
 
 SRCS_c6748-evm = sample_c6748_cfg.c sample_c6748_int_reg.c
index 1a960f28c06dd7bdcf98be547261e13985a073d5..4c751cff7693e490a04cd848552b0210d270e4f8 100755 (executable)
@@ -53,6 +53,6 @@ requires ti.sdo.edma3.drv;
 /*!
  *  ======== ti.sdo.edma3.drv.sample ========
  */
-package ti.sdo.edma3.drv.sample [02, 02, 12] {
+package ti.sdo.edma3.drv.sample [02, 02, 11] {
     module DrvSample;
 }
index 345ddaa3f191ab85fbe1003ad452bfe0c1931488..58e7ef4a3bd87704b60ce025145abcf9ec4dfdb1 100755 (executable)
@@ -80,8 +80,6 @@ function getLibs(prog)
                         'TMS320TI816X',
                         'Vayu',
                         'DRA7XX'
-                        'TDA3XX'
-                        'DRA72X'
                     ];
 
     /* Directories for each platform */
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c
deleted file mode 100644 (file)
index e2cdaf5..0000000
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * sample_tda2xx_int_reg.c
- *
- * Platform specific interrupt registration and un-registration routines.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sysbios/knl/Semaphore.h>
-#include <ti/sysbios/hal/Hwi.h>
-#include <ti/sysbios/family/shared/vayu/IntXbar.h>
-#include <ti/sysbios/family/arm/a15/Mmu.h>
-#include <xdc/runtime/Error.h>
-#include <xdc/runtime/System.h>
-
-#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
-
-/**
-  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
-  * (Not all TC error ISRs need to be registered, register only for the
-  * available Transfer Controllers).
-  */
-void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
-                                                {
-                                                (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
-                                                };
-
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
-extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
-extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorIntXbarInstNo[];
-extern unsigned int ccErrEdmaXbarIndex[];
-extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
-extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
-
-extern unsigned int dsp_num;
-/* This variable has to be used as an extern */
-unsigned int gpp_num = 0;
-
-Hwi_Handle hwiCCXferCompInt;
-Hwi_Handle hwiCCErrInt;
-Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
-
-/* External Instance Specific Configuration Structure */
-extern EDMA3_DRV_GblXbarToChanConfigParams
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
-
-typedef struct  {
-    volatile Uint32 TPCC_EVTMUX[32];
-} CSL_IntmuxRegs;
-
-typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
-
-
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)
-#define EDMA3_NUM_TCC                     (64u)
-
-#define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
-/*
- * Forward decleration
- */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
-                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
-
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
-
-/**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
-    {
-    static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-
-    /*
-     * Skip these interrupt xbar configuration.
-     * if it is accessing EVE internal edma instance ie edma3id = 2 and dsp_num = 1.
-     */
-    if (edma3Id != 2 && dsp_num != 1)
-    {
-        IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
-        IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
-        IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
-        IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
-    }
-
-    Hwi_Params hwiParams;
-    Error_Block      eb;
-
-    /* Initialize the Error Block                                             */
-    Error_init(&eb);
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    /* Initialize the HWI parameters with user specified values */
-    Hwi_Params_init(&hwiParams);
-
-    /* argument for the ISR */
-    hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-       //hwiParams.priority = hwIntXferComp[edma3Id];
-
-    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
-                                       ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
-                                       (const Hwi_Params *) (&hwiParams),
-                                       &eb);
-    if (TRUE == Error_check(&eb))
-    {
-        System_printf("HWI Create Failed\n",Error_getCode(&eb));
-    }
-
-    /* Initialize the HWI parameters with user specified values */
-    Hwi_Params_init(&hwiParams);
-    /* argument for the ISR */
-    hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-       //hwiParams.priority = hwIntCcErr[edma3Id];
-
-       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
-                ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
-                (const Hwi_Params *) (&hwiParams),
-                &eb);
-
-    if (TRUE == Error_check(&eb))
-    {
-        System_printf("HWI Create Failed\n",Error_getCode(&eb));
-    }
-
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        /* Initialize the HWI parameters with user specified values */
-        Hwi_Params_init(&hwiParams);
-        /* argument for the ISR */
-        hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-        //hwiParams.priority = hwIntTcErr[edma3Id];
-
-        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
-                    (ptrEdma3TcIsrHandler[numTc]),
-                    (const Hwi_Params *) (&hwiParams),
-                    &eb);
-        if (TRUE == Error_check(&eb))
-        {
-            System_printf("HWI Create Failed\n",Error_getCode(&eb));
-        }
-        numTc++;
-       }
-
-    Hwi_enableInterrupt(ccErrorInt[edma3Id]);
-    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
-    numTc = 0;
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
-        numTc++;
-       }
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
-    {
-       static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    Hwi_delete(&hwiCCXferCompInt);
-    Hwi_delete(&hwiCCErrInt);
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        Hwi_delete(&hwiTCErrInt[numTc]);
-        numTc++;
-       }
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**
- * \brief   sampleMapXbarEvtToChan
- *
- * This function reads from the sample configuration structure which specifies
- * cross bar events mapped to DMA channel.
- *
- * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
-                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
-       {
-    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
-
-       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
-               (chanNum != NULL) &&
-               (edmaGblXbarConfig != NULL))
-               {
-               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
-               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
-               if (edmaChanNum != -1)
-                       {
-                       *chanNum = edmaChanNum;
-                       edma3Result = EDMA3_DRV_SOK;
-                       }
-               }
-       return (edma3Result);
-       }
-
-
-/**
- * \brief   sampleConfigScr
- *
- * This function configures control config registers for the cross bar events
- * mapped to the EDMA channel.
- *
- * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
-       {
-    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
-    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
-
-
-       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
-               (chanNum < EDMA3_NUM_TCC))
-               {
-               scrRegOffset = chanNum / 2;
-               scrChanOffset = chanNum - (scrRegOffset * 2);
-               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
-
-               switch(scrChanOffset)
-                       {
-                       case 0:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
-                               break;
-                       case 1:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
-                               break;
-                       default:
-                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-                               break;
-                       }
-               }
-       else
-               {
-               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-               }
-       return edma3Result;
-       }
-
-EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
-                                   unsigned int edma3Id)
-    {
-    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
-    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
-                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
-    if (hEdma != NULL)
-        {
-        retVal = EDMA3_DRV_initXbarEventMap(hEdma,
-                                                                       sampleXbarToChanConfig,
-                                                                       (EDMA3_DRV_mapXbarEvtToChan)&sampleMapXbarEvtToChan,
-                                                                       (EDMA3_DRV_xbarConfigScr)&sampleConfigScr);
-        }
-
-    return retVal;
-    }
-
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
-    {
-    printf("memory Protection error");
-    }
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c
deleted file mode 100644 (file)
index 87229c0..0000000
+++ /dev/null
@@ -1,1768 +0,0 @@
-/*
- * sample_dra72x_cfg.c
- *
- * SoC specific EDMA3 hardware related information like number of transfer
- * controllers, various interrupt ids etc. It is used while interrupts
- * enabling / disabling. It needs to be ported for different SoCs.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sdo/edma3/drv/edma3_drv.h>
-#ifdef BUILD_DRA72X_IPU
-#include <ti/sysbios/family/arm/ducati/Core.h>
-
-#endif
-
-/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         2u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
-
-/* Number of DSPs present in the system */
-#define NUM_DSPS                    1u
-const unsigned int numDsps = NUM_DSPS;
-
-/* Determine the processor id by reading DNUM register. */
-/* Statically allocate the region numbers with cores. */
-int myCoreNum;
-#define PID0_ADDRESS 0xE00FFFE0
-#define CORE_ID_C0 0x0
-#define CORE_ID_C1 0x1
-
-unsigned short determineProcId()
-{
-    unsigned short regionNo = numEdma3Instances;
-#ifdef BUILD_DRA72X_DSP
-    extern __cregister volatile unsigned int DNUM;
-#endif
-
-    myCoreNum = numDsps;
-
-#ifdef BUILD_DRA72X_MPU
-    asm ("    push    {r0-r2} \n\t"
-            "    MRC p15, 0, r0, c0, c0, 5\n\t"
-                "    LDR      r1, =myCoreNum\n\t"
-                "    STR      r0, [r1]\n\t"
-                "    pop    {r0-r2}\n\t");
-       if((myCoreNum & 0x03) == 1)
-               regionNo = 1;
-       else
-               regionNo = 0;
-#elif defined(BUILD_DRA72X_IPU)
-    myCoreNum = (*(unsigned int *)(PID0_ADDRESS));
-    if(Core_getIpuId() == 1){
-        if(myCoreNum == CORE_ID_C0)
-            regionNo = 4;
-        else if (myCoreNum == CORE_ID_C1)
-            regionNo = 5;
-    }
-    if(Core_getIpuId() == 2){
-        if(myCoreNum == CORE_ID_C0)
-            regionNo = 6;
-        else if (myCoreNum == CORE_ID_C1)
-            regionNo = 7;
-    }
-#elif defined(BUILD_DRA72X_DSP)
-       regionNo = 2;
-#endif
-       return regionNo;
-}
-
-signed char*  getGlobalAddr(signed char* addr)
-{
-     return (addr); /* The address is already a global address */
-}
-unsigned short isGblConfigRequired(unsigned int dspNum)
-{
-    (void) dspNum;
-       return 1;
-}
-
-/* Semaphore handles */
-EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
-
-/** Number of PaRAM Sets available                                            */
-#define EDMA3_NUM_PARAMSET                              (512u)
-
-/** Number of TCCS available                                                  */
-#define EDMA3_NUM_TCC                                   (64u)
-
-/** Number of DMA Channels available                                          */
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)
-
-/** Number of QDMA Channels available                                         */
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
-
-/** Number of Event Queues available                                          */
-#define EDMA3_NUM_EVTQUE                                (4u)
-
-/** Number of Transfer Controllers available                                  */
-#define EDMA3_NUM_TC                                    (2u)
-
-/** Number of Regions                                                         */
-#define EDMA3_NUM_REGIONS                               (8u)
-
-/** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)
-#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38u)
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34u)
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33u)
-
-/** Based on the interrupt number to be mapped define the XBAR instance number */
-#define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)
-#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7u)
-#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12u)
-#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11u)
-
-/** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT_A15                          (67u)
-#define EDMA3_CC_ERROR_INT_DSP                          (39u)
-#define EDMA3_CC_ERROR_INT_IPU                          (35u)
-
-/** Based on the interrupt number to be mapped define the XBAR instance number */
-#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)
-#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8u)
-#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13u)
-
-/** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT_A15                         (68u)
-#define EDMA3_TC0_ERROR_INT_DSP                         (40u)
-#define EDMA3_TC0_ERROR_INT_IPU                         (36u)
-#define EDMA3_TC1_ERROR_INT_A15                         (69u)
-#define EDMA3_TC1_ERROR_INT_DSP                         (41u)
-#define EDMA3_TC1_ERROR_INT_IPU                         (37u)
-
-/** Based on the interrupt number to be mapped define the XBAR instance number */
-#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)
-#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9u)
-#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14u)
-#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)
-#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10u)
-#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15u)
-
-#ifdef BUILD_DRA72X_MPU
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A15
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_A15_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A15
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_A15
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
-
-#elif defined BUILD_DRA72X_DSP
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_DSP_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_DSP
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_DSP
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_DSP_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_DSP_XBAR_INST_NO
-
-#elif defined BUILD_DRA72X_IPU
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU_C0
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO
-
-#else
-#define EDMA3_CC_XFER_COMPLETION_INT                    (0u)
-#define EDMA3_CC_ERROR_INT                              (0u)
-#define CC_ERROR_INT_XBAR_INST_NO                       (0u)
-#define EDMA3_TC0_ERROR_INT                             (0u)
-#define EDMA3_TC1_ERROR_INT                             (0u)
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
-#endif
-
-#define EDMA3_TC2_ERROR_INT                             (0u)
-#define EDMA3_TC3_ERROR_INT                             (0u)
-#define EDMA3_TC4_ERROR_INT                             (0u)
-#define EDMA3_TC5_ERROR_INT                             (0u)
-#define EDMA3_TC6_ERROR_INT                             (0u)
-#define EDMA3_TC7_ERROR_INT                             (0u)
-
-#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19u)
-#define DSP1_EDMA3_CC_ERROR_INT                         (27u)
-#define DSP1_EDMA3_TC0_ERROR_INT                        (28u)
-#define DSP1_EDMA3_TC1_ERROR_INT                        (29u)
-
-/** XBAR interrupt source index numbers for EDMA interrupts */
-#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)
-#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)
-#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)
-#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)
-#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)
-#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)
-#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)
-#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)
-
-#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)
-#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)
-#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)
-
-/**
- * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
- * ECM events (SoC specific). These ECM events come
- * under ECM block XXX (handling those specific ECM events). Normally, block
- * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
- * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
- * is mapped to a specific HWI_INT YYY in the tcf file.
- * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
- * to transfer completion interrupt.
- * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
- * to CC error interrupts.
- * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
- * to TC error interrupts.
- */
-/* EDMA 0 */
-
-#define EDMA3_HWI_INT_XFER_COMP                           (7u)
-#define EDMA3_HWI_INT_CC_ERR                              (7u)
-#define EDMA3_HWI_INT_TC0_ERR                             (10u)
-#define EDMA3_HWI_INT_TC1_ERR                             (10u)
-#define EDMA3_HWI_INT_TC2_ERR                             (10u)
-#define EDMA3_HWI_INT_TC3_ERR                             (10u)
-
-/**
- * \brief Mapping of DMA channels 0-31 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped (channel available)
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * For Vayu Since the xbar can be used to map event to any EDMA channel,
- * If the application is assigning events to other channel this variable
- * should be modified
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                      /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA       (0x3FC0C06Eu)  /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFu)  /* TBD */
-
-/**
- * \brief Mapping of DMA channels 32-63 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped (channel available)
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA       (0xF3FFFFFCu) /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000u) /* TBD */
-
-
-/* Variable which will be used internally for referring number of Event Queues*/
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
-                                                        EDMA3_NUM_EVTQUE,
-                                                    };
-
-/* Variable which will be used internally for referring number of TCs.        */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
-                                                    EDMA3_NUM_TC,
-                                                    EDMA3_NUM_TC
-                                                };
-
-/**
- * Variable which will be used internally for referring transfer completion
- * interrupt.
- */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-        EDMA3_CC_XFER_COMPLETION_INT_A15,
-        EDMA3_CC_XFER_COMPLETION_INT_A15,
-               EDMA3_CC_XFER_COMPLETION_INT_DSP,
-        0u,
-               EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
-        EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,
-        EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
-        EDMA3_CC_XFER_COMPLETION_INT_IPU_C1
-    },
-    /* EDMA3 INSTANCE# 1 */
-    {
-        0u,
-        0u,
-        DSP1_EDMA3_CC_XFER_COMPLETION_INT,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u
-    }
-};
-/** These are the Xbar instance numbers corresponding to interrupt numbers */
-unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-        COMPLETION_INT_A15_XBAR_INST_NO,
-        COMPLETION_INT_A15_XBAR_INST_NO,
-               COMPLETION_INT_DSP_XBAR_INST_NO,
-        0u,
-               COMPLETION_INT_IPU_C0_XBAR_INST_NO,
-        COMPLETION_INT_IPU_C1_XBAR_INST_NO,
-        COMPLETION_INT_IPU_C0_XBAR_INST_NO,
-        COMPLETION_INT_IPU_C1_XBAR_INST_NO,
-    },
-    /* EDMA3 INSTANCE# 1 */
-    {
-        0u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u,
-        0u
-    }
-};
-
-/** These are the Interrupt Crossbar Index For EDMA Completion for different regions */
-unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-       {
-               XBAR_EDMA_TPCC_IRQ_REGION0,
-        XBAR_EDMA_TPCC_IRQ_REGION1,
-        XBAR_EDMA_TPCC_IRQ_REGION2,
-        XBAR_EDMA_TPCC_IRQ_REGION3,
-               XBAR_EDMA_TPCC_IRQ_REGION4,
-        XBAR_EDMA_TPCC_IRQ_REGION5,
-        XBAR_EDMA_TPCC_IRQ_REGION6,
-        XBAR_EDMA_TPCC_IRQ_REGION7
-       },
-    /* EDMA3 INSTANCE# 1 */
-    {
-               XBAR_EDMA_TPCC_IRQ_REGION0,
-        XBAR_EDMA_TPCC_IRQ_REGION1,
-        XBAR_EDMA_TPCC_IRQ_REGION2,
-        XBAR_EDMA_TPCC_IRQ_REGION3,
-               XBAR_EDMA_TPCC_IRQ_REGION4,
-        XBAR_EDMA_TPCC_IRQ_REGION5,
-        XBAR_EDMA_TPCC_IRQ_REGION6,
-        XBAR_EDMA_TPCC_IRQ_REGION7
-       }
-};
-
-/**
- * Variable which will be used internally for referring channel controller's
- * error interrupt.
- */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] =
-{
-    EDMA3_CC_ERROR_INT,
-    DSP1_EDMA3_CC_ERROR_INT
-};
-unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =
-{
-    CC_ERROR_INT_XBAR_INST_NO,
-    CC_ERROR_INT_XBAR_INST_NO
-};
-unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] =
-{
-       XBAR_EDMA_TPCC_IRQ_ERR,
-    XBAR_EDMA_TPCC_IRQ_ERR
-};
-
-/**
- * Variable which will be used internally for referring transfer controllers'
- * error interrupts.
- */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-        EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
-        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
-        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
-        EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
-    },
-    /* EDMA3 INSTANCE# 1 */
-    {
-        EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
-        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
-        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
-        DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,
-    }
-};
-unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-       TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
-       0u, 0u,
-       0u, 0u,
-       0u, 0u,
-    },
-    /* EDMA3 INSTANCE# 1 */
-    {
-       TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
-       0u, 0u,
-       0u, 0u,
-       0u, 0u,
-    }
-};
-
-unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-       XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
-       0u, 0u,
-       0u, 0u, 0u, 0u,
-    },
-    /* EDMA3 INSTANCE# 1 */
-    {
-       XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
-       0u, 0u,
-       0u, 0u, 0u, 0u,
-    }
-};
-
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] =
-{
-    EDMA3_HWI_INT_XFER_COMP,
-    EDMA3_HWI_INT_XFER_COMP
-};
-
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] =
-{
-    EDMA3_HWI_INT_CC_ERR,
-    EDMA3_HWI_INT_CC_ERR
-};
-
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-        EDMA3_HWI_INT_TC0_ERR,
-        EDMA3_HWI_INT_TC1_ERR,
-        EDMA3_HWI_INT_TC2_ERR,
-        EDMA3_HWI_INT_TC3_ERR
-    },
-    /* EDMA3 INSTANCE# 1 */
-    {
-        EDMA3_HWI_INT_TC0_ERR,
-        EDMA3_HWI_INT_TC1_ERR,
-        EDMA3_HWI_INT_TC2_ERR,
-        EDMA3_HWI_INT_TC3_ERR
-    }
-};
-
-/**
- * \brief Base address as seen from the different cores may be different
- * And is defined based on the core
- */
-#if ((defined BUILD_DRA72X_MPU) || (defined BUILD_DRA72X_DSP))
-#define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))
-#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))
-#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))
-#elif (defined BUILD_DRA72X_IPU)
-#define EDMA3_CC_BASE_ADDR                          ((void *)(0x63300000))
-#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x63400000))
-#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x63500000))
-#else
-#define EDMA3_CC_BASE_ADDR                          ((void *)(0x0))
-#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x0))
-#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x0))
-#endif
-
-#define DSP1_EDMA3_CC_BASE_ADDR                     ((void *)(0x01D10000))
-#define DSP1_EDMA3_TC0_BASE_ADDR                    ((void *)(0x01D05000))
-#define DSP1_EDMA3_TC1_BASE_ADDR                    ((void *)(0x01D06000))
-
-/* Driver Object Initialization Configuration */
-EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
-{
-    {
-        /* EDMA3 INSTANCE# 0 */
-        /** Total number of DMA Channels supported by the EDMA3 Controller    */
-        EDMA3_NUM_DMA_CHANNELS,
-        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
-        EDMA3_NUM_QDMA_CHANNELS,
-        /** Total number of TCCs supported by the EDMA3 Controller            */
-        EDMA3_NUM_TCC,
-        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
-        EDMA3_NUM_PARAMSET,
-        /** Total number of Event Queues in the EDMA3 Controller              */
-        EDMA3_NUM_EVTQUE,
-        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
-        EDMA3_NUM_TC,
-        /** Number of Regions on this EDMA3 controller                        */
-        EDMA3_NUM_REGIONS,
-
-        /**
-         * \brief Channel mapping existence
-         * A value of 0 (No channel mapping) implies that there is fixed association
-         * for a channel number to a parameter entry number or, in other words,
-         * PaRAM entry n corresponds to channel n.
-         */
-        1u,
-
-        /** Existence of memory protection feature */
-        0u,
-
-        /** Global Register Region of CC Registers */
-        EDMA3_CC_BASE_ADDR,
-        /** Transfer Controller (TC) Registers */
-        {
-               EDMA3_TC0_BASE_ADDR,
-               EDMA3_TC1_BASE_ADDR,
-               (void *)NULL,
-               (void *)NULL,
-            (void *)NULL,
-            (void *)NULL,
-            (void *)NULL,
-            (void *)NULL
-        },
-        /** Interrupt no. for Transfer Completion */
-        EDMA3_CC_XFER_COMPLETION_INT,
-        /** Interrupt no. for CC Error */
-        EDMA3_CC_ERROR_INT,
-        /** Interrupt no. for TCs Error */
-        {
-            EDMA3_TC0_ERROR_INT,
-            EDMA3_TC1_ERROR_INT,
-            EDMA3_TC2_ERROR_INT,
-            EDMA3_TC3_ERROR_INT,
-            EDMA3_TC4_ERROR_INT,
-            EDMA3_TC5_ERROR_INT,
-            EDMA3_TC6_ERROR_INT,
-            EDMA3_TC7_ERROR_INT
-        },
-
-        /**
-         * \brief EDMA3 TC priority setting
-         *
-         * User can program the priority of the Event Queues
-         * at a system-wide level.  This means that the user can set the
-         * priority of an IO initiated by either of the TCs (Transfer Controllers)
-         * relative to IO initiated by the other bus masters on the
-         * device (ARM, DSP, USB, etc)
-         */
-        {
-            0u,
-            1u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
-        },
-        /**
-         * \brief To Configure the Threshold level of number of events
-         * that can be queued up in the Event queues. EDMA3CC error register
-         * (CCERR) will indicate whether or not at any instant of time the
-         * number of events queued up in any of the event queues exceeds
-         * or equals the threshold/watermark value that is set
-         * in the queue watermark threshold register (QWMTHRA).
-         */
-        {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
-        },
-
-        /**
-         * \brief To Configure the Default Burst Size (DBS) of TCs.
-         * An optimally-sized command is defined by the transfer controller
-         * default burst size (DBS). Different TCs can have different
-         * DBS values. It is defined in Bytes.
-         */
-            {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
-            },
-
-        /**
-         * \brief Mapping from each DMA channel to a Parameter RAM set,
-         * if it exists, otherwise of no use.
-         */
-            {
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
-                       },
-
-         /**
-          * \brief Mapping from each DMA channel to a TCC. This specific
-          * TCC code will be returned when the transfer is completed
-          * on the mapped channel.
-          */
-            {
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            },
-
-        /**
-         * \brief Mapping of DMA channels to Hardware Events from
-         * various peripherals, which use EDMA for data transfer.
-         * All channels need not be mapped, some can be free also.
-         */
-            {
-            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA,
-            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA
-            }
-        },
-    {
-        /* EDMA3 INSTANCE# 1 */
-        /** Total number of DMA Channels supported by the EDMA3 Controller    */
-        EDMA3_NUM_DMA_CHANNELS,
-        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
-        EDMA3_NUM_QDMA_CHANNELS,
-        /** Total number of TCCs supported by the EDMA3 Controller            */
-        EDMA3_NUM_TCC,
-        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
-        EDMA3_NUM_PARAMSET,
-        /** Total number of Event Queues in the EDMA3 Controller              */
-        EDMA3_NUM_EVTQUE,
-        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
-        EDMA3_NUM_TC,
-        /** Number of Regions on this EDMA3 controller                        */
-        EDMA3_NUM_REGIONS,
-
-        /**
-         * \brief Channel mapping existence
-         * A value of 0 (No channel mapping) implies that there is fixed association
-         * for a channel number to a parameter entry number or, in other words,
-         * PaRAM entry n corresponds to channel n.
-         */
-        1u,
-
-        /** Existence of memory protection feature */
-        0u,
-
-        /** Global Register Region of CC Registers */
-        DSP1_EDMA3_CC_BASE_ADDR,
-        /** Transfer Controller (TC) Registers */
-        {
-               DSP1_EDMA3_TC0_BASE_ADDR,
-               DSP1_EDMA3_TC1_BASE_ADDR,
-               (void *)NULL,
-               (void *)NULL,
-            (void *)NULL,
-            (void *)NULL,
-            (void *)NULL,
-            (void *)NULL
-        },
-        /** Interrupt no. for Transfer Completion */
-        DSP1_EDMA3_CC_XFER_COMPLETION_INT,
-        /** Interrupt no. for CC Error */
-        DSP1_EDMA3_CC_ERROR_INT,
-        /** Interrupt no. for TCs Error */
-        {
-            DSP1_EDMA3_TC0_ERROR_INT,
-            DSP1_EDMA3_TC1_ERROR_INT,
-            EDMA3_TC2_ERROR_INT,
-            EDMA3_TC3_ERROR_INT,
-            EDMA3_TC4_ERROR_INT,
-            EDMA3_TC5_ERROR_INT,
-            EDMA3_TC6_ERROR_INT,
-            EDMA3_TC7_ERROR_INT
-        },
-
-        /**
-         * \brief EDMA3 TC priority setting
-         *
-         * User can program the priority of the Event Queues
-         * at a system-wide level.  This means that the user can set the
-         * priority of an IO initiated by either of the TCs (Transfer Controllers)
-         * relative to IO initiated by the other bus masters on the
-         * device (ARM, DSP, USB, etc)
-         */
-        {
-            0u,
-            1u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
-        },
-        /**
-         * \brief To Configure the Threshold level of number of events
-         * that can be queued up in the Event queues. EDMA3CC error register
-         * (CCERR) will indicate whether or not at any instant of time the
-         * number of events queued up in any of the event queues exceeds
-         * or equals the threshold/watermark value that is set
-         * in the queue watermark threshold register (QWMTHRA).
-         */
-        {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
-        },
-
-        /**
-         * \brief To Configure the Default Burst Size (DBS) of TCs.
-         * An optimally-sized command is defined by the transfer controller
-         * default burst size (DBS). Different TCs can have different
-         * DBS values. It is defined in Bytes.
-         */
-            {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
-            },
-
-        /**
-         * \brief Mapping from each DMA channel to a Parameter RAM set,
-         * if it exists, otherwise of no use.
-         */
-            {
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
-                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
-            },
-
-         /**
-          * \brief Mapping from each DMA channel to a TCC. This specific
-          * TCC code will be returned when the transfer is completed
-          * on the mapped channel.
-          */
-            {
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            },
-
-        /**
-         * \brief Mapping of DMA channels to Hardware Events from
-         * various peripherals, which use EDMA for data transfer.
-         * All channels need not be mapped, some can be free also.
-         */
-            {
-            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,
-            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA
-            }
-    }
-};
-
-/**
- * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
- * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
- * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
- * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
- *
- * Only Resources owned by a perticular core are allocated by Driver
- * Reserved resources are not allocated if requested for any available resource
- */
-
-/* Driver Instance Initialization Configuration */
-EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-    {
-               /* EDMA3 INSTANCE# 0 */
-               {
-                       /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000FFu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00u, 0x00u},
-                       },
-
-                       /* Resources owned/reserved by region 1 (Associated to MPU core 1) */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                 /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000FFu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00u, 0x00u},
-                       },
-
-               /* Resources owned/reserved by region 2 (Associated to DSP1)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000FFu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00u, 0x00u},
-                       },
-
-               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000FFu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00u, 0x00u},
-                       },
-
-               /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000FFu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00u, 0x00u},
-                       },
-
-               /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000FFu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00u, 0x00u},
-                       },
-
-               /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000FFu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00u, 0x00u},
-                       },
-           },
-               /* EDMA3 INSTANCE# 1 DSP1 EDMA*/
-               {
-               /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-                       /* Resources owned/reserved by region 1 (Not Associated to any core supported) */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 2 (Associated to DSP core)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000FFu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00u, 0x00u},
-                       },
-
-               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-           }
-};
-
-/* Driver Instance Cross bar event to channel map Initialization Configuration */
-EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-        /* Event to channel map for region 0 */
-        {
-            {-1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1}
-        },
-        /* Event to channel map for region 1 */
-        {
-            {-1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1}
-        },
-        /* Event to channel map for region 2 */
-        {
-            {-1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1}
-        },
-        /* Event to channel map for region 3 */
-        {
-            {-1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1}
-        },
-        /* Event to channel map for region 4 */
-        {
-            {-1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1}
-        },
-        /* Event to channel map for region 5 */
-        {
-            {-1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1}
-        },
-        /* Event to channel map for region 6 */
-        {
-            {-1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1}
-        },
-        /* Event to channel map for region 7 */
-        {
-            {-1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1}
-        },
-    }
-};
-
-/* End of File */
-
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c
deleted file mode 100644 (file)
index b15f0f8..0000000
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * sample_tda2xx_int_reg.c
- *
- * Platform specific interrupt registration and un-registration routines.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sysbios/knl/Semaphore.h>
-#include <ti/sysbios/family/c64p/EventCombiner.h>
-#include <ti/sysbios/family/c64p/Hwi.h>
-#include <ti/sysbios/family/shared/vayu/IntXbar.h>
-
-#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
-
-/**
-  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
-  * (Not all TC error ISRs need to be registered, register only for the
-  * available Transfer Controllers).
-  */
-void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
-                                                {
-                                                &lisrEdma3TC0ErrHandler0,
-                                                &lisrEdma3TC1ErrHandler0,
-                                                &lisrEdma3TC2ErrHandler0,
-                                                &lisrEdma3TC3ErrHandler0,
-                                                &lisrEdma3TC4ErrHandler0,
-                                                &lisrEdma3TC5ErrHandler0,
-                                                &lisrEdma3TC6ErrHandler0,
-                                                &lisrEdma3TC7ErrHandler0,
-                                                };
-
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
-extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
-extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorIntXbarInstNo[];
-extern unsigned int ccErrEdmaXbarIndex[];
-extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
-extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
-
-extern unsigned int dsp_num;
-
-/* External Instance Specific Configuration Structure */
-extern EDMA3_DRV_GblXbarToChanConfigParams
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
-
-typedef struct  {
-    volatile Uint32 TPCC_EVTMUX[32];
-} CSL_IntmuxRegs;
-
-typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
-
-
-#define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127u)
-#define EDMA3_NUM_TCC                     (64u)
-
-#define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
-
-/*
- * Forward decleration
- */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
-                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
-
-
-/**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
-    {
-    static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-    /* Do the xbar configuration only for edma inst 0 */
-       /* EDMA inst 1 is for DSP1 EDMA which has direct interrupt mapping */
-       if(edma3Id == 0)
-       {
-           IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
-           IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
-           IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
-           IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
-       }
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    /* Enable the Xfer Completion Event Interrupt */
-    EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
-                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
-                               edma3Id, 1);
-    EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
-
-    /* Enable the CC Error Event Interrupt */
-    EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
-                                               (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
-                                               edma3Id, 1);
-    EventCombiner_enableEvent(ccErrorInt[edma3Id]);
-
-    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
-                            (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
-                            edma3Id, 1);
-        EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
-        numTc++;
-       }
-
-   /**
-    * Enabling the HWI_ID.
-    * EDMA3 interrupts (transfer completion, CC error etc.)
-    * correspond to different ECM events (SoC specific). These ECM events come
-    * under ECM block XXX (handling those specific ECM events). Normally, block
-    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
-    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
-    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
-    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
-    * API C64_enableIER(), in which the YYY bit is SET.
-    */
-       if(edma3Id == 0)
-       {
-    Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
-    Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
-    Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
-       }
-
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
-    {
-       static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    /* Disable the Xfer Completion Event Interrupt */
-       EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
-
-    /* Disable the CC Error Event Interrupt */
-       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
-
-    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
-    while (numTc < numEdma3Tc[edma3Id])
-       {
-        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
-        numTc++;
-       }
-
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**
- * \brief   sampleMapXbarEvtToChan
- *
- * This function reads from the sample configuration structure which specifies
- * cross bar events mapped to DMA channel.
- *
- * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
-                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
-       {
-    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
-
-       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
-               (chanNum != NULL) &&
-               (edmaGblXbarConfig != NULL))
-               {
-               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
-               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
-               if (edmaChanNum != -1)
-                       {
-                       *chanNum = edmaChanNum;
-                       edma3Result = EDMA3_DRV_SOK;
-                       }
-               }
-       return (edma3Result);
-       }
-
-
-/**
- * \brief   sampleConfigScr
- *
- * This function configures control config registers for the cross bar events
- * mapped to the EDMA channel.
- *
- * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
-       {
-    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
-    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
-
-
-       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
-               (chanNum < EDMA3_NUM_TCC))
-               {
-               scrRegOffset = chanNum / 2;
-               scrChanOffset = chanNum - (scrRegOffset * 2);
-               xBarEvtNum = (eventNum  + 1);
-
-               switch(scrChanOffset)
-                       {
-                       case 0:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
-                               break;
-                       case 1:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
-                               break;
-                       default:
-                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-                               break;
-                       }
-               }
-       else
-               {
-               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-               }
-       return edma3Result;
-       }
-
-EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
-                                   unsigned int edma3Id)
-    {
-    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
-    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
-                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
-    if (hEdma != NULL)
-        {
-        retVal = EDMA3_DRV_initXbarEventMap(hEdma,
-                                                                       sampleXbarToChanConfig,
-                                                                       &sampleMapXbarEvtToChan,
-                                                                       &sampleConfigScr);
-        }
-
-    return retVal;
-    }
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_arm_int_reg.c
deleted file mode 100644 (file)
index ffad00d..0000000
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * sample_tda3xx_int_reg.c
- *
- * Platform specific interrupt registration and un-registration routines.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sysbios/knl/Semaphore.h>
-#include <ti/sysbios/hal/Hwi.h>
-#include <ti/sysbios/family/shared/vayu/IntXbar.h>
-#include <ti/sysbios/family/arm/a15/Mmu.h>
-#include <xdc/runtime/Error.h>
-#include <xdc/runtime/System.h>
-
-#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
-
-/**
-  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
-  * (Not all TC error ISRs need to be registered, register only for the
-  * available Transfer Controllers).
-  */
-void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
-                                                {
-                                                (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
-                                                };
-
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
-extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
-extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorIntXbarInstNo[];
-extern unsigned int ccErrEdmaXbarIndex[];
-extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
-extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
-
-extern unsigned int dsp_num;
-/* This variable has to be used as an extern */
-unsigned int gpp_num = 0;
-
-Hwi_Handle hwiCCXferCompInt;
-Hwi_Handle hwiCCErrInt;
-Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
-
-/* External Instance Specific Configuration Structure */
-extern EDMA3_DRV_GblXbarToChanConfigParams
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
-
-typedef struct  {
-    volatile Uint32 TPCC_EVTMUX[32];
-} CSL_IntmuxRegs;
-
-typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
-
-
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)
-#define EDMA3_NUM_TCC                     (64u)
-
-#define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
-/*
- * Forward decleration
- */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
-                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
-
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
-
-/**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
-    {
-    static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-
-    /*
-     * Skip these interrupt xbar configuration.
-     * if it is accessing EVE internal edma instance ie edma3id = 2 and dsp_num = 1.
-     */
-    if (edma3Id != 2 && dsp_num != 1)
-    {
-        IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
-        IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
-        IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
-        IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
-    }
-
-    Hwi_Params hwiParams;
-    Error_Block      eb;
-
-    /* Initialize the Error Block                                             */
-    Error_init(&eb);
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    /* Initialize the HWI parameters with user specified values */
-    Hwi_Params_init(&hwiParams);
-
-    /* argument for the ISR */
-    hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-       //hwiParams.priority = hwIntXferComp[edma3Id];
-
-    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
-                                       ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
-                                       (const Hwi_Params *) (&hwiParams),
-                                       &eb);
-    if (TRUE == Error_check(&eb))
-    {
-        System_printf("HWI Create Failed\n",Error_getCode(&eb));
-    }
-
-    /* Initialize the HWI parameters with user specified values */
-    Hwi_Params_init(&hwiParams);
-    /* argument for the ISR */
-    hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-       //hwiParams.priority = hwIntCcErr[edma3Id];
-
-       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
-                ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
-                (const Hwi_Params *) (&hwiParams),
-                &eb);
-
-    if (TRUE == Error_check(&eb))
-    {
-        System_printf("HWI Create Failed\n",Error_getCode(&eb));
-    }
-
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        /* Initialize the HWI parameters with user specified values */
-        Hwi_Params_init(&hwiParams);
-        /* argument for the ISR */
-        hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-        //hwiParams.priority = hwIntTcErr[edma3Id];
-
-        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
-                    (ptrEdma3TcIsrHandler[numTc]),
-                    (const Hwi_Params *) (&hwiParams),
-                    &eb);
-        if (TRUE == Error_check(&eb))
-        {
-            System_printf("HWI Create Failed\n",Error_getCode(&eb));
-        }
-        numTc++;
-       }
-
-    Hwi_enableInterrupt(ccErrorInt[edma3Id]);
-    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
-    numTc = 0;
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
-        numTc++;
-       }
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
-    {
-       static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    Hwi_delete(&hwiCCXferCompInt);
-    Hwi_delete(&hwiCCErrInt);
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        Hwi_delete(&hwiTCErrInt[numTc]);
-        numTc++;
-       }
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**
- * \brief   sampleMapXbarEvtToChan
- *
- * This function reads from the sample configuration structure which specifies
- * cross bar events mapped to DMA channel.
- *
- * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
-                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
-       {
-    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
-
-       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
-               (chanNum != NULL) &&
-               (edmaGblXbarConfig != NULL))
-               {
-               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
-               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
-               if (edmaChanNum != -1)
-                       {
-                       *chanNum = edmaChanNum;
-                       edma3Result = EDMA3_DRV_SOK;
-               &nb