Misra C fixes:
authorSunil MS <x0190988@ti.com>
Wed, 8 Oct 2014 11:55:47 +0000 (17:25 +0530)
committerSunil MS <x0190988@ti.com>
Tue, 14 Oct 2014 09:20:30 +0000 (14:50 +0530)
MISRA.BUILTIN_NUMERIC
MISRA.LITERAL.UNSIGNED.SUFFIX

Change-Id: Iee234f7e21a5f2762d87fae581cca76347c39df7
Signed-off-by: Sunil MS <x0190988@ti.com>
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_int_reg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda2xx_arm_int_reg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda2xx_cfg.c
packages/ti/sdo/edma3/rm/src/configs/edma3_tda2xx_cfg.c

index ba2e01154f96c93763af31548532e4c2cd495dd9..5db1de7161adc40d8d7671c1d77099a052c0f4dd 100644 (file)
@@ -99,17 +99,17 @@ typedef struct  {
 \r
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;\r
 \r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)\r
 \r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)\r
 \r
 \r
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX (127u)\r
-#define EDMA3_NUM_TCC                     (64u)\r
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX (127U)\r
+#define EDMA3_NUM_TCC                     (64U)\r
 \r
 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)\r
 /*\r
index 31fa4e739fe942a8b03e7178d9e8ed8910cd9e65..7c29be080f49dc3921a5f9422b9abaf3e2cd8820 100644 (file)
@@ -155,67 +155,67 @@ uint16_t isGblConfigRequired(uint32_t dspNum)
 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
 \r
 /** Number of PaRAM Sets available                                            */\r
-#define EDMA3_NUM_PARAMSET                              (512u)\r
+#define EDMA3_NUM_PARAMSET                              (512U)\r
 \r
 /** Number of TCCS available                                                  */\r
-#define EDMA3_NUM_TCC                                   (64u)\r
+#define EDMA3_NUM_TCC                                   (64U)\r
 \r
 /** Number of DMA Channels available                                          */\r
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)\r
+#define EDMA3_NUM_DMA_CHANNELS                          (64U)\r
 \r
 /** Number of QDMA Channels available                                         */\r
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)\r
+#define EDMA3_NUM_QDMA_CHANNELS                         (8U)\r
 \r
 /** Number of Event Queues available                                          */\r
-#define EDMA3_NUM_EVTQUE                                (4u)\r
+#define EDMA3_NUM_EVTQUE                                (4U)\r
 \r
 /** Number of Transfer Controllers available                                  */\r
-#define EDMA3_NUM_TC                                    (2u)\r
+#define EDMA3_NUM_TC                                    (2U)\r
 \r
 /** Number of Regions                                                         */\r
-#define EDMA3_NUM_REGIONS                               (8u)\r
+#define EDMA3_NUM_REGIONS                               (8U)\r
 \r
 /** Interrupt no. for Transfer Completion */\r
-#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_EVE                (8u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_EVE                (8U)\r
 \r
 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
-#define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)\r
-#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7u)\r
-#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12u)\r
-#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11u)\r
+#define COMPLETION_INT_A15_XBAR_INST_NO                 (29U)\r
+#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7U)\r
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12U)\r
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11U)\r
 \r
 /** Interrupt no. for CC Error */\r
-#define EDMA3_CC_ERROR_INT_A15                          (67u)\r
-#define EDMA3_CC_ERROR_INT_DSP                          (39u)\r
-#define EDMA3_CC_ERROR_INT_IPU                          (35u)\r
-#define EDMA3_CC_ERROR_INT_EVE                          (23u)\r
+#define EDMA3_CC_ERROR_INT_A15                          (67U)\r
+#define EDMA3_CC_ERROR_INT_DSP                          (39U)\r
+#define EDMA3_CC_ERROR_INT_IPU                          (35U)\r
+#define EDMA3_CC_ERROR_INT_EVE                          (23U)\r
 \r
 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
-#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)\r
-#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8u)\r
-#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13u)\r
+#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30U)\r
+#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8U)\r
+#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13U)\r
 \r
 /** Interrupt no. for TCs Error */\r
-#define EDMA3_TC0_ERROR_INT_A15                         (68u)\r
-#define EDMA3_TC0_ERROR_INT_DSP                         (40u)\r
-#define EDMA3_TC0_ERROR_INT_IPU                         (36u)\r
-#define EDMA3_TC0_ERROR_INT_EVE                         (24u)\r
-#define EDMA3_TC1_ERROR_INT_A15                         (69u)\r
-#define EDMA3_TC1_ERROR_INT_DSP                         (41u)\r
-#define EDMA3_TC1_ERROR_INT_IPU                         (37u)\r
-#define EDMA3_TC1_ERROR_INT_EVE                         (25u)\r
+#define EDMA3_TC0_ERROR_INT_A15                         (68U)\r
+#define EDMA3_TC0_ERROR_INT_DSP                         (40U)\r
+#define EDMA3_TC0_ERROR_INT_IPU                         (36U)\r
+#define EDMA3_TC0_ERROR_INT_EVE                         (24U)\r
+#define EDMA3_TC1_ERROR_INT_A15                         (69U)\r
+#define EDMA3_TC1_ERROR_INT_DSP                         (41U)\r
+#define EDMA3_TC1_ERROR_INT_IPU                         (37U)\r
+#define EDMA3_TC1_ERROR_INT_EVE                         (25U)\r
 \r
 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
-#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)\r
-#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9u\r
-#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14u)\r
-#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)\r
-#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10u)\r
-#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15u)\r
+#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31U)\r
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9U\r
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14U)\r
+#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32U)\r
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10U)\r
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)\r
 \r
 #ifdef BUILD_TDA2XX_MPU\r
 #define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_A15)\r
@@ -250,46 +250,46 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_EVE)\r
 #define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_EVE)\r
 /* For accessing EVE internal edma, there is no need to configure Xbar */\r
-#define CC_ERROR_INT_XBAR_INST_NO                       (0u)\r
-#define TC0_ERROR_INT_XBAR_INST_NO                      (0u)\r
-#define TC1_ERROR_INT_XBAR_INST_NO                      (0u)\r
+#define CC_ERROR_INT_XBAR_INST_NO                       (0U)\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      (0U)\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      (0U)\r
 \r
 #else\r
-#define EDMA3_CC_XFER_COMPLETION_INT                    (0u)\r
-#define EDMA3_CC_ERROR_INT                              (0u)\r
-#define CC_ERROR_INT_XBAR_INST_NO                       (0u)\r
-#define EDMA3_TC0_ERROR_INT                             (0u)\r
-#define EDMA3_TC1_ERROR_INT                             (0u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    (0U)\r
+#define EDMA3_CC_ERROR_INT                              (0U)\r
+#define CC_ERROR_INT_XBAR_INST_NO                       (0U)\r
+#define EDMA3_TC0_ERROR_INT                             (0U)\r
+#define EDMA3_TC1_ERROR_INT                             (0U)\r
 #define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
 #define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
 #endif\r
 \r
-#define EDMA3_TC2_ERROR_INT                             (0u)\r
-#define EDMA3_TC3_ERROR_INT                             (0u)\r
-#define EDMA3_TC4_ERROR_INT                             (0u)\r
-#define EDMA3_TC5_ERROR_INT                             (0u)\r
-#define EDMA3_TC6_ERROR_INT                             (0u)\r
-#define EDMA3_TC7_ERROR_INT                             (0u)\r
+#define EDMA3_TC2_ERROR_INT                             (0U)\r
+#define EDMA3_TC3_ERROR_INT                             (0U)\r
+#define EDMA3_TC4_ERROR_INT                             (0U)\r
+#define EDMA3_TC5_ERROR_INT                             (0U)\r
+#define EDMA3_TC6_ERROR_INT                             (0U)\r
+#define EDMA3_TC7_ERROR_INT                             (0U)\r
 \r
-#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19u)\r
-#define DSP2_EDMA3_CC_XFER_COMPLETION_INT               (20u)\r
-#define DSP1_EDMA3_CC_ERROR_INT                         (27u)\r
-#define DSP1_EDMA3_TC0_ERROR_INT                        (28u)\r
-#define DSP1_EDMA3_TC1_ERROR_INT                        (29u)\r
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19U)\r
+#define DSP2_EDMA3_CC_XFER_COMPLETION_INT               (20U)\r
+#define DSP1_EDMA3_CC_ERROR_INT                         (27U)\r
+#define DSP1_EDMA3_TC0_ERROR_INT                        (28U)\r
+#define DSP1_EDMA3_TC1_ERROR_INT                        (29U)\r
 \r
 /** XBAR interrupt source index numbers for EDMA interrupts */\r
-#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)\r
-\r
-#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)\r
-#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)\r
-#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368U)\r
+\r
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359U)\r
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370U)\r
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371U)\r
 \r
 /**\r
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
@@ -307,12 +307,12 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  */\r
 /* EDMA 0 */\r
 \r
-#define EDMA3_HWI_INT_XFER_COMP                           (7u)\r
-#define EDMA3_HWI_INT_CC_ERR                              (7u)\r
-#define EDMA3_HWI_INT_TC0_ERR                             (10u)\r
-#define EDMA3_HWI_INT_TC1_ERR                             (10u)\r
-#define EDMA3_HWI_INT_TC2_ERR                             (10u)\r
-#define EDMA3_HWI_INT_TC3_ERR                             (10u)\r
+#define EDMA3_HWI_INT_XFER_COMP                           (7U)\r
+#define EDMA3_HWI_INT_CC_ERR                              (7U)\r
+#define EDMA3_HWI_INT_TC0_ERR                             (10U)\r
+#define EDMA3_HWI_INT_TC1_ERR                             (10U)\r
+#define EDMA3_HWI_INT_TC2_ERR                             (10U)\r
+#define EDMA3_HWI_INT_TC3_ERR                             (10U)\r
 \r
 /**\r
  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
@@ -333,9 +333,9 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
  */\r
                                                       /* 31     0 */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA       (0x3FC0C06Eu)  /* TBD */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFu)  /* TBD */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA        (0x00000000u)  /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA       (0x3FC0C06EU)  /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFU)  /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA        (0x00000000U)  /* TBD */\r
 \r
 /**\r
  * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
@@ -351,9 +351,9 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  *\r
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
  */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA       (0xF3FFFFFCu) /* TBD */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000u) /* TBD */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA        (0x00000000u) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA       (0xF3FFFFFCU) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000U) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA        (0x00000000U) /* TBD */\r
 \r
 \r
 /* Variable which will be used internally for referring number of Event Queues*/\r
@@ -389,26 +389,26 @@ uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
     },\r
     /* EDMA3 INSTANCE# 1 */\r
     {\r
-        0u,\r
-        0u,\r
+        0U,\r
+        0U,\r
         DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
         DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U\r
     },\r
     /* EDMA3 INSTANCE# 2 */\r
     {\r
-        0u,\r
+        0U,\r
         /* Region 1 (Associated to EVE core)*/\r
         EDMA3_CC_XFER_COMPLETION_INT_EVE,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
     }\r
 };\r
 /** These are the Xbar instance numbers corresponding to interrupt numbers */\r
@@ -427,14 +427,14 @@ uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
     },\r
     /* EDMA3 INSTANCE# 1 */\r
     {\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U\r
     },\r
     /* EDMA3 INSTANCE# 2 */\r
     {\r
@@ -443,14 +443,14 @@ uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
       * there is no need to configure Xbar.\r
       * So getting to zero.\r
       */\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U\r
     }\r
 };\r
 \r
@@ -486,14 +486,14 @@ uint32_t ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
       * there is no need to configure Xbar.\r
       * So getting to zero.\r
       */\r
-               0u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-               0u,\r
-        0u,\r
-        0u,\r
-        0u\r
+               0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+               0U,\r
+        0U,\r
+        0U,\r
+        0U\r
        }\r
 };\r
 \r
@@ -553,23 +553,23 @@ uint32_t tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
     /* EDMA3 INSTANCE# 0 */\r
     {\r
        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
-       0u, 0u,\r
-       0u, 0u,\r
-       0u, 0u,\r
+       0U, 0U,\r
+       0U, 0U,\r
+       0U, 0U,\r
     },\r
     /* EDMA3 INSTANCE# 1 */\r
     {\r
        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
-       0u, 0u,\r
-       0u, 0u,\r
-       0u, 0u,\r
+       0U, 0U,\r
+       0U, 0U,\r
+       0U, 0U,\r
     },\r
     /* EDMA3 INSTANCE# 2 */\r
     {\r
        TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
-       0u, 0u,\r
-       0u, 0u,\r
-       0u, 0u,\r
+       0U, 0U,\r
+       0U, 0U,\r
+       0U, 0U,\r
     }\r
 };\r
 \r
@@ -578,20 +578,20 @@ uint32_t tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
     /* EDMA3 INSTANCE# 0 */\r
     {\r
        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
-       0u, 0u,\r
-       0u, 0u, 0u, 0u,\r
+       0U, 0U,\r
+       0U, 0U, 0U, 0U,\r
     },\r
     /* EDMA3 INSTANCE# 1 */\r
     {\r
        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
-       0u, 0u,\r
-       0u, 0u, 0u, 0u,\r
+       0U, 0U,\r
+       0U, 0U, 0U, 0U,\r
     },\r
     /* EDMA3 INSTANCE# 2 */\r
     {\r
        XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
-       0u, 0u,\r
-       0u, 0u, 0u, 0u,\r
+       0U, 0U,\r
+       0U, 0U, 0U, 0U,\r
     }\r
 };\r
 \r
@@ -703,10 +703,10 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,\r
          * PaRAM entry n corresponds to channel n.\r
          */\r
-        1u,\r
+        1U,\r
 \r
         /** Existence of memory protection feature */\r
-        0u,\r
+        0U,\r
 \r
         /** Global Register Region of CC Registers */\r
         EDMA3_CC_BASE_ADDR,\r
@@ -747,14 +747,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)\r
          */\r
         {\r
-            0u,\r
-            1u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            0U,\r
+            1U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
         },\r
         /**\r
          * \brief To Configure the Threshold level of number of events\r
@@ -765,14 +765,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).\r
          */\r
         {\r
-            16u,\r
-            16u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
         },\r
 \r
         /**\r
@@ -782,14 +782,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.\r
          */\r
             {\r
-            16u,\r
-            16u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
             },\r
 \r
         /**\r
@@ -888,10 +888,10 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,\r
          * PaRAM entry n corresponds to channel n.\r
          */\r
-        1u,\r
+        1U,\r
 \r
         /** Existence of memory protection feature */\r
-        0u,\r
+        0U,\r
 \r
         /** Global Register Region of CC Registers */\r
         DSP1_EDMA3_CC_BASE_ADDR,\r
@@ -932,14 +932,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)\r
          */\r
         {\r
-            0u,\r
-            1u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            0U,\r
+            1U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
         },\r
         /**\r
          * \brief To Configure the Threshold level of number of events\r
@@ -950,14 +950,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).\r
          */\r
         {\r
-            16u,\r
-            16u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
         },\r
 \r
         /**\r
@@ -967,14 +967,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.\r
          */\r
             {\r
-            16u,\r
-            16u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
             },\r
 \r
         /**\r
@@ -1073,10 +1073,10 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,\r
          * PaRAM entry n corresponds to channel n.\r
          */\r
-        1u,\r
+        1U,\r
 \r
         /** Existence of memory protection feature */\r
-        0u,\r
+        0U,\r
 \r
         /** Global Register Region of CC Registers */\r
         EDMA3_CC_BASE_ADDR,\r
@@ -1117,14 +1117,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)\r
          */\r
         {\r
-            0u,\r
-            1u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            0U,\r
+            1U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
         },\r
         /**\r
          * \brief To Configure the Threshold level of number of events\r
@@ -1135,14 +1135,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).\r
          */\r
         {\r
-            16u,\r
-            16u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
         },\r
 \r
         /**\r
@@ -1152,14 +1152,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.\r
          */\r
             {\r
-            16u,\r
-            16u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
             },\r
 \r
         /**\r
@@ -1257,35 +1257,35 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -1293,24 +1293,24 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                        /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 /* \r
  * This instance 0 and region 1 is only accessible to MPU core 1.\r
  * So other cores should not be access.\r
@@ -1318,29 +1318,29 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 #ifdef BUILD_TDA2XX_MPU\r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 #else\r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 #endif\r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -1348,46 +1348,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -1395,46 +1395,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -1442,46 +1442,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -1489,46 +1489,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -1536,46 +1536,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -1583,46 +1583,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -1630,11 +1630,11 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
            },\r
                /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
@@ -1643,129 +1643,129 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                        /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -1773,46 +1773,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -1820,199 +1820,199 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
            },\r
                /* EDMA3 INSTANCE# 2 EVE EDMA*/\r
@@ -2021,82 +2021,82 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 1 (Associated to any EVE core)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
@@ -2104,293 +2104,293 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
            },\r
 };\r
index a21cfec2d002423baa510492cfcd843e2d1c1997..37c64a7a8a1dfd6f1e2cec333e327954964235c9 100644 (file)
@@ -91,17 +91,17 @@ typedef struct  {
 
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
 
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
 
 
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX (127u)
-#define EDMA3_NUM_TCC                     (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX (127U)
+#define EDMA3_NUM_TCC                     (64U)
 
 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
 
index 514d26a10bf56d25c3d3f5d2cf605d3e7955e47f..09dffb4adf88a515cb52e804cfeae3b8af1a29a1 100644 (file)
@@ -60,22 +60,22 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 &lisrEdma3TC7ErrHandler0,\r
                                                 };\r
 \r
-extern unsigned int ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
-extern unsigned int ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];\r
-extern unsigned int tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];\r
-extern unsigned int numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];\r
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];\r
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];\r
 \r
 /**\r
  * Variables which will be used internally for referring the hardware interrupt\r
  * for various EDMA3 interrupts.\r
  */\r
-extern unsigned int hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];\r
-extern unsigned int hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];\r
-extern unsigned int hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];\r
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];\r
 \r
-extern unsigned int dsp_num;\r
+extern uint32_t dsp_num;\r
 /* This variable has to be used as an extern */\r
-unsigned int gpp_num = 0;\r
+uint32_t gpp_num = 0;\r
 \r
 Hwi_Handle hwiCCXferCompInt;\r
 Hwi_Handle hwiCCErrInt;\r
@@ -91,47 +91,47 @@ typedef struct  {
 \r
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;\r
 \r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)\r
 \r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)\r
 \r
 \r
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX (127u)\r
-#define EDMA3_NUM_TCC                     (64u)\r
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX (127U)\r
+#define EDMA3_NUM_TCC                     (64U)\r
 \r
 #define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)\r
 \r
 /*\r
  * Forward decleration\r
  */\r
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
-                 unsigned int *chanNum,\r
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,\r
+                 uint32_t *chanNum,\r
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);\r
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
-                                  unsigned int chanNum);\r
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,\r
+                                  uint32_t chanNum);\r
 \r
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId);\r
 \r
 /**  To Register the ISRs with the underlying OS, if required. */\r
-void registerEdma3Interrupts (unsigned int edma3Id);\r
+void registerEdma3Interrupts (uint32_t edma3Id);\r
 \r
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */\r
-void unregisterEdma3Interrupts (unsigned int edma3Id);\r
+void unregisterEdma3Interrupts (uint32_t edma3Id);\r
 \r
 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
-                                   unsigned int edma3Id);\r
+                                   uint32_t edma3Id);\r
                                    \r
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId);\r
 \r
 /**  To Register the ISRs with the underlying OS, if required. */\r
-void registerEdma3Interrupts (unsigned int edma3Id)\r
+void registerEdma3Interrupts (uint32_t edma3Id)\r
     {\r
     static UInt32 cookie = 0;\r
-    unsigned int numTc = 0;\r
+    uint32_t numTc = 0;\r
     Hwi_Params hwiParams; \r
     Error_Block      eb;\r
 \r
@@ -222,10 +222,10 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     }\r
 \r
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */\r
-void unregisterEdma3Interrupts (unsigned int edma3Id)\r
+void unregisterEdma3Interrupts (uint32_t edma3Id)\r
     {\r
        static UInt32 cookiee = 0;\r
-    unsigned int numTc = 0;\r
+    uint32_t numTc = 0;\r
 \r
     /* Disabling the global interrupts */\r
     cookiee = Hwi_disable();\r
@@ -249,13 +249,13 @@ void unregisterEdma3Interrupts (unsigned int edma3Id)
  *\r
  * \return  EDMA3_DRV_SOK if success, else error code\r
  */\r
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
-                 unsigned int *chanNum,\r
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,\r
+                 uint32_t *chanNum,\r
                  const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)\r
        {\r
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
-    unsigned int xbarEvtNum = 0;\r
-    int          edmaChanNum = 0;\r
+    uint32_t xbarEvtNum = 0;\r
+    int32_t          edmaChanNum = 0;\r
 \r
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA2XX) &&\r
                (chanNum != NULL) &&\r
@@ -281,13 +281,13 @@ EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
  *\r
  * \return  EDMA3_DRV_SOK if success, else error code\r
  */\r
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
-                                  unsigned int chanNum)\r
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,\r
+                                  uint32_t chanNum)\r
        {\r
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;\r
-    unsigned int scrChanOffset = 0;\r
-    unsigned int scrRegOffset  = 0;\r
-    unsigned int xBarEvtNum    = 0;\r
+    uint32_t scrChanOffset = 0;\r
+    uint32_t scrRegOffset  = 0;\r
+    uint32_t xBarEvtNum    = 0;\r
     CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);\r
 \r
 \r
@@ -322,7 +322,7 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
        }\r
 \r
 EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
-                                   unsigned int edma3Id)\r
+                                   uint32_t edma3Id)\r
     {\r
     EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;\r
     const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =\r
@@ -338,7 +338,7 @@ EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
     return retVal;\r
     }\r
 \r
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId)\r
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId)\r
     {\r
 #ifdef EDMA3_RM_DEBUG\r
     /*  Added to fix Misra C error */\r
index a5551d3109c9d4efe3a256c4bcc3ad1f075a8ef7..255d1e488d879d3fe9a901d62806db7e3d7c80d9 100644 (file)
 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
 \r
 /* Number of EDMA3 controllers present in the system */\r
-#define NUM_EDMA3_INSTANCES         1u\r
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
+#define NUM_EDMA3_INSTANCES         1U\r
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;\r
 \r
 /* Number of DSPs present in the system */\r
-#define NUM_DSPS                    1u\r
-const unsigned int numDsps = NUM_DSPS;\r
+#define NUM_DSPS                    1U\r
+const uint32_t numDsps = NUM_DSPS;\r
 \r
 /* Determine the processor id by reading DNUM register. */\r
 /* Statically allocate the region numbers with cores. */\r
-int myCoreNum;\r
+int32_t myCoreNum;\r
 #define PID0_ADDRESS 0xE00FFFE0\r
 #define CORE_ID_C0 0x0\r
 #define CORE_ID_C1 0x1\r
@@ -67,57 +67,77 @@ void __inline readProcFeatureReg(void)
 }\r
 #endif\r
 \r
-signed char*  getGlobalAddr(signed char* addr);\r
+int8_t*  getGlobalAddr(int8_t* addr);\r
 \r
-unsigned short isGblConfigRequired(unsigned int dspNum);\r
+uint16_t isGblConfigRequired(uint32_t dspNum);\r
 \r
-unsigned short determineProcId(void);\r
+uint16_t determineProcId(void);\r
 \r
-unsigned short determineProcId(void)\r
+uint16_t determineProcId(void)\r
 {\r
-unsigned short regionNo = (unsigned short)numEdma3Instances;\r
+uint16_t regionNo = (uint16_t)numEdma3Instances;\r
 #ifdef BUILD_TDA2XX_DSP\r
-extern __cregister volatile unsigned int DNUM;\r
+extern __cregister volatile uint32_t DNUM;\r
 #endif\r
-myCoreNum = (int)numDsps;\r
+myCoreNum = (int32_t)numDsps;\r
 #ifdef BUILD_TDA2XX_MPU\r
 \r
     readProcFeatureReg();\r
                regionNo = 0U;\r
 /* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */\r
-       if(((unsigned int)myCoreNum & 0x03U) == 1U)\r
+       if(((uint32_t)myCoreNum & 0x03U) == 1U)\r
     {\r
                regionNo = 1U;\r
     }\r
 #elif defined(BUILD_TDA2XX_IPU)\r
-myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
+myCoreNum = (*(uint32_t *)(PID0_ADDRESS));\r
 if(Core_getIpuId() == 1){\r
        if(myCoreNum == CORE_ID_C0)\r
-               regionNo = 4;\r
+    {\r
+               regionNo = 4U;\r
+    }\r
        else if (myCoreNum == CORE_ID_C1)\r
-               regionNo = 5;\r
+    {\r
+               regionNo = 5U;\r
+    }\r
+    else\r
+    {\r
+        ;/* Nothing to be done */\r
+    }\r
 }\r
 if(Core_getIpuId() == 2){\r
        if(myCoreNum == CORE_ID_C0)\r
-               regionNo = 6;\r
+    {\r
+               regionNo = 6U;\r
+    }\r
        else if (myCoreNum == CORE_ID_C1)\r
-               regionNo = 7;\r
+    {\r
+               regionNo = 7U;\r
+    }\r
+    else\r
+    {\r
+        ;/* Nothing to be done */\r
+    }\r
 }\r
 #elif defined BUILD_TDA2XX_DSP\r
        myCoreNum = DNUM;\r
        if(myCoreNum == 0)\r
+    {\r
                regionNo = 2;\r
+    }\r
        else\r
+    {\r
                regionNo = 3;\r
+    }\r
 #endif\r
        return regionNo;\r
 }\r
 \r
-signed char*  getGlobalAddr(signed char* addr)\r
+int8_t*  getGlobalAddr(int8_t* addr)\r
 {\r
      return (addr); /* The address is already a global address */\r
 }\r
-unsigned short isGblConfigRequired(unsigned int dspNum)\r
+uint16_t isGblConfigRequired(uint32_t dspNum)\r
 {\r
     (void) dspNum;\r
 \r
@@ -128,40 +148,40 @@ unsigned short isGblConfigRequired(unsigned int dspNum)
 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
 \r
 /** Number of PaRAM Sets available                                            */\r
-#define EDMA3_NUM_PARAMSET                              (512u)\r
+#define EDMA3_NUM_PARAMSET                              (512U)\r
 \r
 /** Number of TCCS available                                                  */\r
-#define EDMA3_NUM_TCC                                   (64u)\r
+#define EDMA3_NUM_TCC                                   (64U)\r
 \r
 /** Number of DMA Channels available                                          */\r
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)\r
+#define EDMA3_NUM_DMA_CHANNELS                          (64U)\r
 \r
 /** Number of QDMA Channels available                                         */\r
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)\r
+#define EDMA3_NUM_QDMA_CHANNELS                         (8U)\r
 \r
 /** Number of Event Queues available                                          */\r
-#define EDMA3_0_NUM_EVTQUE                              (4u)\r
+#define EDMA3_0_NUM_EVTQUE                              (4U)\r
 \r
 /** Number of Transfer Controllers available                                  */\r
-#define EDMA3_0_NUM_TC                                  (4u)\r
+#define EDMA3_0_NUM_TC                                  (4U)\r
 \r
 /** Number of Regions                                                         */\r
-#define EDMA3_0_NUM_REGIONS                             (2u)\r
+#define EDMA3_0_NUM_REGIONS                             (2U)\r
 \r
 \r
 /** Interrupt no. for Transfer Completion                                     */\r
-#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34u)\r
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34U)\r
 /** Interrupt no. for CC Error                                                */\r
-#define EDMA3_0_CC_ERROR_INT                            (35u)\r
+#define EDMA3_0_CC_ERROR_INT                            (35U)\r
 /** Interrupt no. for TCs Error                                               */\r
-#define EDMA3_0_TC0_ERROR_INT                           (36u)\r
-#define EDMA3_0_TC1_ERROR_INT                           (37u)\r
-#define EDMA3_0_TC2_ERROR_INT                           (0u)\r
-#define EDMA3_0_TC3_ERROR_INT                           (0u)\r
-#define EDMA3_0_TC4_ERROR_INT                           (0u)\r
-#define EDMA3_0_TC5_ERROR_INT                           (0u)\r
-#define EDMA3_0_TC6_ERROR_INT                           (0u)\r
-#define EDMA3_0_TC7_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC0_ERROR_INT                           (36U)\r
+#define EDMA3_0_TC1_ERROR_INT                           (37U)\r
+#define EDMA3_0_TC2_ERROR_INT                           (0U)\r
+#define EDMA3_0_TC3_ERROR_INT                           (0U)\r
+#define EDMA3_0_TC4_ERROR_INT                           (0U)\r
+#define EDMA3_0_TC5_ERROR_INT                           (0U)\r
+#define EDMA3_0_TC6_ERROR_INT                           (0U)\r
+#define EDMA3_0_TC7_ERROR_INT                           (0U)\r
 \r
 /**\r
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
@@ -179,12 +199,12 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  */\r
 /* EDMA 0 */\r
 \r
-#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)\r
-#define EDMA3_0_HWI_INT_CC_ERR                              (7u)\r
-#define EDMA3_0_HWI_INT_TC0_ERR                             (7u)\r
-#define EDMA3_0_HWI_INT_TC1_ERR                             (7u)\r
-#define EDMA3_0_HWI_INT_TC2_ERR                             (7u)\r
-#define EDMA3_0_HWI_INT_TC3_ERR                             (7u)\r
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7U)\r
+#define EDMA3_0_HWI_INT_CC_ERR                              (7U)\r
+#define EDMA3_0_HWI_INT_TC0_ERR                             (7U)\r
+#define EDMA3_0_HWI_INT_TC1_ERR                             (7U)\r
+#define EDMA3_0_HWI_INT_TC2_ERR                             (7U)\r
+#define EDMA3_0_HWI_INT_TC3_ERR                             (7U)\r
 \r
 \r
 /**\r
@@ -202,7 +222,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
  */\r
                                                       /* 31     0 */\r
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x3FC0C06Eu)  /* TBD */\r
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x3FC0C06EU)  /* TBD */\r
 \r
 \r
 /**\r
@@ -219,16 +239,16 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  *\r
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
  */\r
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xF3FFFFFCu) /* TBD */\r
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xF3FFFFFCU) /* TBD */\r
 \r
 \r
 /* Variable which will be used internally for referring number of Event Queues*/\r
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
                                                         EDMA3_0_NUM_EVTQUE,\r
                                                     };\r
 \r
 /* Variable which will be used internally for referring number of TCs.        */\r
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
                                                     EDMA3_0_NUM_TC,\r
                                                 };\r
 \r
@@ -236,10 +256,10 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
  * Variable which will be used internally for referring transfer completion\r
  * interrupt.\r
  */\r
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
 {\r
     {\r
-        0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,\r
+        0U, EDMA3_0_CC_XFER_COMPLETION_INT, 0U, 0U, 0U, 0U, 0U, 0U,\r
     },\r
 };\r
 \r
@@ -247,7 +267,7 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
  * Variable which will be used internally for referring channel controller's\r
  * error interrupt.\r
  */\r
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
                                                     EDMA3_0_CC_ERROR_INT,\r
                                                };\r
 \r
@@ -255,7 +275,7 @@ unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
  * Variable which will be used internally for referring transfer controllers'\r
  * error interrupts.\r
  */\r
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
 {\r
    {\r
        EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,\r
@@ -269,15 +289,15 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
  * Variables which will be used internally for referring the hardware interrupt\r
  * for various EDMA3 interrupts.\r
  */\r
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
                                                     EDMA3_0_HWI_INT_XFER_COMP\r
                                                   };\r
 \r
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
                                                    EDMA3_0_HWI_INT_CC_ERR\r
                                                };\r
 \r
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
                                                      {\r
                                                         EDMA3_0_HWI_INT_TC0_ERR,\r
                                                         EDMA3_0_HWI_INT_TC1_ERR,\r
@@ -319,10 +339,10 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * for a channel number to a parameter entry number or, in other words,\r
          * PaRAM entry n corresponds to channel n.\r
          */\r
-        1u,\r
+        1U,\r
 \r
         /** Existence of memory protection feature */\r
-        0u,\r
+        0U,\r
 \r
         /** Global Register Region of CC Registers */\r
         EDMA3_CC_BASE_ADDR,\r
@@ -363,14 +383,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * device (ARM, DSP, USB, etc)\r
          */\r
         {\r
-            0u,\r
-            1u,\r
-            2u,\r
-            3u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            0U,\r
+            1U,\r
+            2U,\r
+            3U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
         },\r
         /**\r
          * \brief To Configure the Threshold level of number of events\r
@@ -381,14 +401,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * in the queue watermark threshold register (QWMTHRA).\r
          */\r
         {\r
-            16u,\r
-            16u,\r
-            16u,\r
-            16u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            16U,\r
+            16U,\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
         },\r
 \r
         /**\r
@@ -398,14 +418,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * DBS values. It is defined in Bytes.\r
          */\r
             {\r
-            16u,\r
-            16u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u,\r
-            0u\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
             },\r
 \r
         /**\r
@@ -413,14 +433,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * if it exists, otherwise of no use.\r
          */\r
             {\r
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u\r
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
+            0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,\r
+            8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,\r
+            16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,\r
+            24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,\r
+            32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U\r
+            40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,\r
+            48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,\r
+            56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U\r
             },\r
 \r
          /**\r
@@ -429,22 +449,22 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
           * on the mapped channel.\r
           */\r
             {\r
-            0u, 1u, 2u, 3u,\r
-            4u, 5u, 6u, 7u,\r
-            8u, 9u, 10u, 11u,\r
-            12u, 13u, 14u, 15u,\r
-            16u, 17u, 18u, 19u,\r
-            20u, 21u, 22u, 23u,\r
-            24u, 25u, 26u, 27u,\r
-            28u, 29u, 30u, 31u,\r
-            32u, 33u, 34u, 35u,\r
-            36u, 37u, 38u, 39u,\r
-            40u, 41u, 42u, 43u,\r
-            44u, 45u, 46u, 47u,\r
-            48u, 49u, 50u, 51u,\r
-            52u, 53u, 54u, 55u,\r
-            56u, 57u, 58u, 59u,\r
-            60u, 61u, 62u, 63u\r
+            0U, 1U, 2U, 3U,\r
+            4U, 5U, 6U, 7U,\r
+            8U, 9U, 10U, 11U,\r
+            12U, 13U, 14U, 15U,\r
+            16U, 17U, 18U, 19U,\r
+            20U, 21U, 22U, 23U,\r
+            24U, 25U, 26U, 27U,\r
+            28U, 29U, 30U, 31U,\r
+            32U, 33U, 34U, 35U,\r
+            36U, 37U, 38U, 39U,\r
+            40U, 41U, 42U, 43U,\r
+            44U, 45U, 46U, 47U,\r
+            48U, 49U, 50U, 51U,\r
+            52U, 53U, 54U, 55U,\r
+            56U, 57U, 58U, 59U,\r
+            60U, 61U, 62U, 63U\r
             },\r
 \r
         /**\r
@@ -470,376 +490,376 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                        /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
         },\r
     },\r
 };\r
index 4a4f4753933fdf885dbd2f0ac68fa6cb10a70d4e..71d165891fbfb331f7eb83e9d566ea37dbf400ca 100644 (file)
 \r
 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
 \r
-#define NUM_SHADOW_REGIONS                      (8u)\r
+#define NUM_SHADOW_REGIONS                      (8U)\r
 \r
 /* Number of EDMA3 controllers present in the system */\r
-#define NUM_EDMA3_INSTANCES         1u\r
+#define NUM_EDMA3_INSTANCES         1U\r
 \r
 /** Number of PaRAM Sets available                                            */\r
-#define EDMA3_NUM_PARAMSET                              (512u)\r
+#define EDMA3_NUM_PARAMSET                              (512U)\r
 \r
 /** Number of TCCS available                                                  */\r
-#define EDMA3_NUM_TCC                                   (64u)\r
+#define EDMA3_NUM_TCC                                   (64U)\r
 \r
 /** Number of DMA Channels available                                          */\r
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)\r
+#define EDMA3_NUM_DMA_CHANNELS                          (64U)\r
 \r
 /** Number of QDMA Channels available                                         */\r
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)\r
+#define EDMA3_NUM_QDMA_CHANNELS                         (8U)\r
 \r
 /** Number of Event Queues available                                          */\r
-#define EDMA3_0_NUM_EVTQUE                              (4u)\r
+#define EDMA3_0_NUM_EVTQUE                              (4U)\r
 \r
 /** Number of Transfer Controllers available                                  */\r
-#define EDMA3_0_NUM_TC                                  (4u)\r
+#define EDMA3_0_NUM_TC                                  (4U)\r
 \r
 /** Number of Regions                                                         */\r
-#define EDMA3_0_NUM_REGIONS                             (2u)\r
+#define EDMA3_0_NUM_REGIONS                             (2U)\r
 \r
 /** Interrupt no. for Transfer Completion                                     */\r
-#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34u)\r
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34U)\r
 /** Interrupt no. for CC Error                                                */\r
-#define EDMA3_0_CC_ERROR_INT                            (35u)\r
+#define EDMA3_0_CC_ERROR_INT                            (35U)\r
 /** Interrupt no. for TCs Error                                               */\r
-#define EDMA3_0_TC0_ERROR_INT                           (36u)\r
-#define EDMA3_0_TC1_ERROR_INT                           (37u)\r
-#define EDMA3_0_TC2_ERROR_INT                           (0u)\r
-#define EDMA3_0_TC3_ERROR_INT                           (0u)\r
-#define EDMA3_0_TC4_ERROR_INT                           (0u)\r
-#define EDMA3_0_TC5_ERROR_INT                           (0u)\r
-#define EDMA3_0_TC6_ERROR_INT                           (0u)\r
-#define EDMA3_0_TC7_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC0_ERROR_INT                           (36U)\r
+#define EDMA3_0_TC1_ERROR_INT                           (37U)\r
+#define EDMA3_0_TC2_ERROR_INT                           (0U)\r
+#define EDMA3_0_TC3_ERROR_INT                           (0U)\r
+#define EDMA3_0_TC4_ERROR_INT                           (0U)\r
+#define EDMA3_0_TC5_ERROR_INT                           (0U)\r
+#define EDMA3_0_TC6_ERROR_INT                           (0U)\r
+#define EDMA3_0_TC7_ERROR_INT                           (0U)\r
 \r
 /** XBAR interrupt source index numbers for EDMA interrupts */\r
-#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)\r
-#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)\r
-\r
-#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)\r
-#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)\r
-#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368U)\r
+\r
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359U)\r
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370U)\r
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371U)\r
 \r
 /**\r
  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
  */\r
                                                 /* 31     0 */\r
-#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0        (0x00000000u)\r
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0        (0x00000000U)\r
 \r
 \r
 /**\r
  *\r
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
  */\r
-#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1        (0x00000000u)\r
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1        (0x00000000U)\r
 \r
 \r
 \r
@@ -161,10 +161,10 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
      * for a channel number to a parameter entry number or, in other words,\r
      * PaRAM entry n corresponds to channel n.\r
      */\r
-    0u,\r
+    0U,\r
 \r
     /** Existence of memory protection feature */\r
-    0u,\r
+    0U,\r
 \r
         /** Global Register Region of CC Registers */\r
         EDMA3_CC_BASE_ADDR,\r
@@ -205,14 +205,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
      * device (ARM, DSP, USB, etc)\r
      */\r
         {\r
-        0u,\r
-        1u,\r
-        2u,\r
-        3u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u\r
+        0U,\r
+        1U,\r
+        2U,\r
+        3U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U\r
         },\r
     /**\r
      * \brief To Configure the Threshold level of number of events\r
@@ -223,14 +223,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
      * in the queue watermark threshold register (QWMTHRA).\r
      */\r
         {\r
-        16u,\r
-        16u,\r
-        16u,\r
-        16u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u\r
+        16U,\r
+        16U,\r
+        16U,\r
+        16U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U\r
         },\r
 \r
     /**\r
@@ -240,14 +240,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
      * DBS values. It is defined in Bytes.\r
      */\r
         {\r
-        16u,\r
-        16u,\r
-        16u,\r
-        16u,\r
-        0u,\r
-        0u,\r
-        0u,\r
-        0u\r
+        16U,\r
+        16U,\r
+        16U,\r
+        16U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U\r
         },\r
 \r
     /**\r
@@ -255,14 +255,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
      * if it exists, otherwise of no use.\r
      */\r
         {\r
-        0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
-        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
-        16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
-        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u\r
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
+        0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,\r
+        8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,\r
+        16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,\r
+        24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,\r
+            32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U\r
+            40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,\r
+            48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,\r
+            56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U\r
         },\r
 \r
      /**\r
@@ -271,22 +271,22 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
       * on the mapped channel.\r
       */\r
         {\r
-        0u, 1u, 2u, 3u,\r
-        4u, 5u, 6u, 7u,\r
-        8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
-        12u, 13u, 14u, 15u,\r
-        16u, 17u, 18u, 19u,\r
-        20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
-        24u, 25u, 26u, 27u,\r
-        28u, 29u, 30u, 31u,\r
-            32u, 33u, 34u, 35u,\r
-            36u, 37u, 38u, 39u,\r
-            40u, 41u, 42u, 43u,\r
-            44u, 45u, 46u, 47u,\r
-            48u, 49u, 50u, 51u,\r
-            52u, 53u, 54u, 55u,\r
-            56u, 57u, 58u, 59u,\r
-            60u, 61u, 62u, 63u\r
+        0U, 1U, 2U, 3U,\r
+        4U, 5U, 6U, 7U,\r
+        8U, 9U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        12U, 13U, 14U, 15U,\r
+        16U, 17U, 18U, 19U,\r
+        20U, 21U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        24U, 25U, 26U, 27U,\r
+        28U, 29U, 30U, 31U,\r
+            32U, 33U, 34U, 35U,\r
+            36U, 37U, 38U, 39U,\r
+            40U, 41U, 42U, 43U,\r
+            44U, 45U, 46U, 47U,\r
+            48U, 49U, 50U, 51U,\r
+            52U, 53U, 54U, 55U,\r
+            56U, 57U, 58U, 59U,\r
+            60U, 61U, 62U, 63U\r
         },\r
 \r
     /**\r
@@ -311,376 +311,376 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SH
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                        /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000FFU},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
         },\r
 };\r