SDOCM00102051 determine core id at runtime
authorPrasad Konnur <prasadkonnur@ti.com>
Thu, 20 Jun 2013 04:52:07 +0000 (10:22 +0530)
committerPrasad Konnur <prasadkonnur@ti.com>
Thu, 20 Jun 2013 04:52:07 +0000 (10:22 +0530)
Updated the cfg file for vayu
return region based on the core on whith code is running

Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
19 files changed:
examples/edma3_driver/evmtda2xx/makefile
examples/edma3_driver/evmtda2xx/rtsc_config/app_mem_seg_placement.cfg [new file with mode: 0644]
examples/edma3_driver/evmtda2xx/rtsc_config/custom_config.bld [new file with mode: 0644]
examples/edma3_driver/evmtda2xx/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
examples/edma3_driver/evmtda2xx/rtsc_config/mem_segment_definition.xs [new file with mode: 0644]
examples/edma3_driver/evmtda2xx/rtsc_config/platform.xs [new file with mode: 0644]
examples/edma3_driver/evmtda2xx/sample_app/linker.cmd
examples/edma3_driver/evmtda2xx_M4/makefile
examples/edma3_driver/evmtda2xx_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/rtsc_config/custom_config.bld [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg [moved from examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_st_sample.cfg with 67% similarity]
examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/rtsc_config/mem_segment_definition.xs [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/rtsc_config/platform.xs [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/sample_app/linker.cmd
packages/makefile
packages/ti/sdo/edma3/drv/sample/makefile
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c

index 24f681d133a07cc8a273302d79550eb4950d3d0d..7a22edc10b98167ad957f61313d16aa69c626f67 100644 (file)
@@ -15,6 +15,10 @@ COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
 # XDC CFG File
 XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
 
+CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
+
+PLATFORM_XDC_CUSTOM = ti.platforms.simVayu:DSP_1
+
 # Common source files and CFLAGS across all platforms and cores
 SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
               dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
diff --git a/examples/edma3_driver/evmtda2xx/rtsc_config/app_mem_seg_placement.cfg b/examples/edma3_driver/evmtda2xx/rtsc_config/app_mem_seg_placement.cfg
new file mode 100644 (file)
index 0000000..4c0dad4
--- /dev/null
@@ -0,0 +1,35 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *   @file  app_mem_seg_placement.cfg
+ *
+ *   @brief 
+ */
+
+function init()
+{
+    var Program = xdc.useModule('xdc.cfg.Program');
+  
+        Program.sectMap[".vecs"]                    = "CODE_CORE_DSP1";
+        Program.sectMap[".text"]                    = "CODE_CORE_DSP1";
+        Program.sectMap[".text:_c_int00"]           = new Program.SectionSpec();
+        Program.sectMap[".text:_c_int00"].loadSegment = "CODE_CORE_DSP1";
+               Program.sectMap[".text:_c_int00"].loadAlign = 0x400;
+        Program.sectMap[".far"]                     = "CODE_CORE_DSP1";
+        Program.sectMap[".cinit"]                   = "CODE_CORE_DSP1";
+        Program.sectMap[".args"]                    = "CODE_CORE_DSP1";
+        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".my_sect_iram"]            = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_DSP1";
+}
diff --git a/examples/edma3_driver/evmtda2xx/rtsc_config/custom_config.bld b/examples/edma3_driver/evmtda2xx/rtsc_config/custom_config.bld
new file mode 100644 (file)
index 0000000..ba44d33
--- /dev/null
@@ -0,0 +1,158 @@
+/*
+ *  ======== config.bld ========
+ *  Sample Build configuration script
+ */
+
+/* load the required modules for the configuration */
+var C64P = xdc.useModule('ti.targets.C64P');
+var C64Pe = xdc.useModule('ti.targets.C64P_big_endian');
+var C674 = xdc.useModule('ti.targets.C674');
+var C64P_ELF = xdc.useModule('ti.targets.elf.C64P');
+var C64Pe_ELF = xdc.useModule('ti.targets.elf.C64P_big_endian');
+var C674_ELF = xdc.useModule('ti.targets.elf.C674');
+var C66 = xdc.useModule('ti.targets.elf.C66');
+var C66e = xdc.useModule('ti.targets.elf.C66_big_endian');
+var Arm = xdc.useModule('ti.targets.arm.elf.Arm9');
+var cortexA8 = xdc.useModule('ti.targets.arm.elf.A8F');
+//var C64T_ELF = xdc.useModule('ti.targets.elf.C64T');
+var M3 = xdc.useModule('ti.targets.arm.elf.M3');
+
+/* compiler paths for the CCS4.0                   */
+var cgtools = java.lang.System.getenv("CGTOOLS");
+var cgtools_elf = java.lang.System.getenv("CGTOOLS_ELF");
+var armcgtools = java.lang.System.getenv("TMS470_CGTOOLS");
+
+C64P.rootDir = cgtools;
+C64Pe.rootDir = cgtools;
+C674.rootDir = cgtools;
+C64P_ELF.rootDir = cgtools_elf;
+//C64T_ELF.rootDir = cgtools_elf;
+C64Pe_ELF.rootDir = cgtools_elf;
+C674_ELF.rootDir = cgtools_elf;
+C66.rootDir = cgtools_elf;
+C66e.rootDir = cgtools_elf;
+Arm.rootDir = armcgtools;
+cortexA8.rootDir = armcgtools;
+M3.rootDir = armcgtools;
+
+/**********************************c674******************************/
+
+/* compiler options                                */
+C64P.ccOpts.suffix += " -mi10 -mo ";
+C64Pe.ccOpts.suffix += " -mi10 -mo -me ";
+C674.ccOpts.suffix += " -mi10 -mo ";
+C64P_ELF.ccOpts.suffix += " -mi10 -mo ";
+//C64T_ELF.ccOpts.suffix += " -mi10 -mo ";
+C64Pe_ELF.ccOpts.suffix += " -mi10 -mo -me ";
+C674_ELF.ccOpts.suffix += " -mi10 -mo ";
+C66.ccOpts.suffix += " -mi10 -mo ";
+C66e.ccOpts.suffix += " -mi10 -mo -me ";
+Arm.ccOpts.suffix += " ";
+cortexA8.ccOpts.suffix += "";
+M3.ccOpts.suffix += "";
+
+/* set default platform and list of all interested platforms */
+C64P.platforms = [
+                     "ti.platforms.evm6472",
+                     "ti.platforms.evmTCI6486",
+                 ];
+C64Pe.platforms = [
+                     "ti.platforms.evm6472",
+                     "ti.platforms.evmTCI6486",
+                 ];
+C674.platforms = [
+                     "ti.platforms.evmDA830",
+                     "ti.platforms.evm6748",
+                     "ti.platforms.evmOMAPL138",
+                     "ti.platforms.simDM8168",
+                     "ti.platforms.evmDM8168",
+                     "ti.platforms.evmDM8148",
+                 ];
+C64P_ELF.platforms = [
+                     "ti.platforms.evm6472",
+                     "ti.platforms.evmTCI6486",
+                 ];
+//C64T_ELF.platforms = [
+//                     "ti.platforms.sdp4430",
+//                 ];
+C64Pe_ELF.platforms = [
+                     "ti.platforms.evm6472",
+                     "ti.platforms.evmTCI6486",
+                 ];
+C674_ELF.platforms = [
+                     "ti.platforms.evmDA830",
+                     "ti.platforms.evm6748",
+                     "ti.platforms.evmOMAPL138",
+                     "ti.platforms.simDM8168",
+                     "ti.platforms.evmDM8168",
+                     "ti.platforms.evmDM8148",
+                 ];
+C66.platforms = [
+                     "ti.platforms.simTCI6608",
+                     "ti.platforms.simTCI6616",
+                     "ti.platforms.simTCI6614",
+                     "ti.platforms.simC6657",
+                     "ti.platforms.simKepler",
+                     "ti.platforms.evm6670",
+                     "ti.platforms.evm6678",
+                     "ti.platforms.evmTCI6614",
+                     "ti.platforms.evm6657",
+                     "ti.platforms.evmTCI6638K2K",
+                 ];
+C66e.platforms = [
+                     "ti.platforms.simTCI6608",
+                     "ti.platforms.simTCI6616",
+                     "ti.platforms.simTCI6614",
+                     "ti.platforms.simC6657",
+                     "ti.platforms.simKepler",
+                     "ti.platforms.evm6670",
+                     "ti.platforms.evm6678",
+                     "ti.platforms.evmTCI6614",
+                     "ti.platforms.evm6657",
+                     "ti.platforms.evmTCI6638K2K",
+                 ];
+Arm.platforms = [
+                     "ti.platforms.evmOMAPL138",
+                 ];
+
+cortexA8.platforms = [
+                         "ti.platforms.evmDM8148",
+                     ];
+M3.platforms = [
+                     "ti.platforms.evmTI816X",
+                 ];
+
+/* select the default platform */
+C64P.platform = C64P.platforms[0];
+C64Pe.platform = C64Pe.platforms[0];
+C674.platform = C674.platforms[0];
+C64P_ELF.platform = C64P_ELF.platforms[0];
+//C64T_ELF.platform = C64T_ELF.platforms[0];
+C64Pe_ELF.platform = C64Pe_ELF.platforms[0];
+C674_ELF.platform = C674_ELF.platforms[0];
+C66.platform = C66.platforms[0];
+C66e.platform = C66e.platforms[0];
+Arm.platform = Arm.platforms[0];
+cortexA8.platform = cortexA8.platforms[0];
+M3.platform = M3.platforms[0];
+
+/* list interested targets in Build.targets array  */
+Build.targets = [
+                  //C64T_ELF,
+                    //C64,
+                    C64P,
+                    C64Pe,
+                    //C67P,
+                    C674,
+                    C64P_ELF,
+                    C64Pe_ELF,
+                    C674_ELF,
+                    C66,
+                    C66e,
+                    Arm,
+                    cortexA8,
+                    M3,
+                  //Win32,
+                ];
+
+var platform_xs = xdc.loadCapsule("platform.xs");
\ No newline at end of file
index 228064b83b0525657fc1c9735c3d391c6427df54..42be85cae6952d4be81564e631ced0d1198ec140 100644 (file)
@@ -20,3 +20,6 @@ ECM.eventGroupHwiNum[3] = 10;
 
 Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
 Timer.timerSettings[0].intNum = 14;
+
+var segPlacement = xdc.loadCapsule("app_mem_seg_placement.cfg");
+segPlacement.init();
diff --git a/examples/edma3_driver/evmtda2xx/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmtda2xx/rtsc_config/mem_segment_definition.xs
new file mode 100644 (file)
index 0000000..0297224
--- /dev/null
@@ -0,0 +1,264 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *  ======== mem_segment_definition.xs ========
+ */
+
+
+function getMemSegmentDefinitionIPU_1_0()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_IPU1_0",
+    {
+          name: "CODE_CORE_IPU1_0",
+          base: 0x84000000,
+          len:  0x01000000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",
+    {
+          name: "PRIVATE_DATA_CORE_IPU1_0",
+          base: 0x85000000,
+          len:  0x01800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",
+    {
+          name: "HDVPSS_DESCRIPTOR_NON_CACHED",
+          base: 0xA1800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[6] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+    
+    return (memory);
+}
+
+function getMemSegmentDefinitionIPU_1_1()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_IPU1_1",
+    {
+          name: "CODE_CORE_IPU1_1",
+          base: 0x86800000,
+          len:  0x01000000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",
+    {
+          name: "PRIVATE_DATA_CORE_IPU1_1",
+          base: 0x87800000,
+          len:  0x01800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+    
+    return (memory);
+}
+
+function getMemSegmentDefinitionDSP_1()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_DSP1",
+    {
+          name: "CODE_CORE_DSP1",
+          base: 0x83100000,
+          len:  0x00700000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_DSP1",
+    {
+          name: "PRIVATE_DATA_CORE_DSP1",
+          base: 0x83800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+    
+    return (memory);
+}
+
+function getMemSegmentDefinitionHOST()
+{
+    var memory = new Array();
+
+    memory[8] = ["CODE_CORE_HOST",
+    {
+          name: "CODE_CORE_HOST",
+          base: 0x89000000,
+          len:  0x00800000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[9] = ["PRIVATE_DATA_CORE_HOST",
+    {
+          name: "PRIVATE_DATA_CORE_HOST",
+          base: 0x89800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[10] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[11] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[12] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[13] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    return (memory);
+}
diff --git a/examples/edma3_driver/evmtda2xx/rtsc_config/platform.xs b/examples/edma3_driver/evmtda2xx/rtsc_config/platform.xs
new file mode 100644 (file)
index 0000000..8ca2143
--- /dev/null
@@ -0,0 +1,46 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *  ======== platform.xs ========
+ */
+
+var Build = xdc.useModule('xdc.bld.BuildEnvironment'); 
+
+var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
+
+Build.platformTable["ti.platforms.simVayu:IPU_1_0"] =
+{      
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
+       codeMemory:"CODE_CORE_IPU1_0",
+       dataMemory:"PRIVATE_DATA_CORE_IPU1_0",
+       stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
+};
+
+Build.platformTable["ti.platforms.simVayu:IPU_1_1"] =
+{      
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
+       codeMemory:"CODE_CORE_IPU1_1",
+       dataMemory:"PRIVATE_DATA_CORE_IPU1_1",
+       stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
+};
+
+Build.platformTable["ti.platforms.simVayu:DSP_1"] =
+{
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
+    codeMemory:"CODE_CORE_DSP1",
+    dataMemory:"PRIVATE_DATA_CORE_DSP1",
+    stackMemory:"PRIVATE_DATA_CORE_DSP1"
+};
+
+Build.platformTable["ti.platforms.simVayu:Cortex_A15"] =
+{
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
+    codeMemory:"CODE_CORE_HOST",
+    dataMemory:"PRIVATE_DATA_CORE_HOST",
+    stackMemory:"PRIVATE_DATA_CORE_HOST"
+};
index 1280f81554932c10367ffbc98112f735a419b4fd..6ca6627afcbabe5c1801b2a37791d7c71180ee84 100644 (file)
@@ -1,7 +1,7 @@
 SECTIONS
 {
-       .my_sect_iram  > EXT_RAM
-       .my_sect_ddr  > EXT_RAM
+//     .my_sect_iram  > EXT_RAM
+//     .my_sect_ddr  > EXT_RAM
 }
 
 
index b0fa6dc92ec696c7a4e89e95985d0be8585e4996..1dd4798f1cb1c97b9fbafb051ea3fd23e959231b 100644 (file)
@@ -1,6 +1,9 @@
 # Makefile for edma3 lld app\r
-\r
-APP_NAME = edma3_drv_arm_tda2xx_sample\r
+ifeq ($(IPUCORE),1)\r
+APP_NAME = edma3_drv_arm_tda2xx_core1_sample\r
+else\r
+APP_NAME = edma3_drv_arm_tda2xx_core0_sample\r
+endif\r
 \r
 SRCDIR = ../src\r
 INCDIR = ../src\r
@@ -13,7 +16,16 @@ INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
 COMP_LIST_m4 = edma3_lld_drv edma3_lld_rm\r
 \r
 # XDC CFG File\r
-XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_st_sample.cfg\r
+ifeq ($(IPUCORE),1)\r
+XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg\r
+CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld\r
+PLATFORM_XDC_CUSTOM = ti.platforms.simVayu:IPU_1_1\r
+else\r
+XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg\r
+CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld\r
+PLATFORM_XDC_CUSTOM = ti.platforms.simVayu:IPU_1_0\r
+endif\r
+\r
 \r
 # Common source files and CFLAGS across all platforms and cores\r
 SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \\r
diff --git a/examples/edma3_driver/evmtda2xx_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg b/examples/edma3_driver/evmtda2xx_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg
new file mode 100644 (file)
index 0000000..b0ca59f
--- /dev/null
@@ -0,0 +1,37 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *   @file  app_mem_seg_placement.cfg
+ *
+ *   @brief 
+ */
+
+function init()
+{
+    var Program = xdc.useModule('xdc.cfg.Program');
+   
+        Program.sectMap[".text"]                    = "CODE_CORE_IPU1_0";
+        Program.sectMap[".cinit"]                   = "CODE_CORE_IPU1_0";
+        Program.sectMap[".pinit"]                   = "CODE_CORE_IPU1_0";
+        Program.sectMap[".args"]                    = "CODE_CORE_IPU1_0";
+        Program.sectMap[".const"]                   = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_IPU1_0"; 
+        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".stack"]                   = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_IPU1_0";
+        //BSP memory section placement
+        Program.sectMap[".bss:extMemNonCache:heap"] = "HDVPSS_DESCRIPTOR_NON_CACHED";
+        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".data"]                    = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_IPU1_0";
+               Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_IPU1_0";
+               
+}
diff --git a/examples/edma3_driver/evmtda2xx_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg b/examples/edma3_driver/evmtda2xx_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg
new file mode 100644 (file)
index 0000000..d128506
--- /dev/null
@@ -0,0 +1,38 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *   @file  app_mem_seg_placement.cfg
+ *
+ *   @brief 
+ */
+
+function init()
+{
+    var Program = xdc.useModule('xdc.cfg.Program');
+        Program.sectMap[".text"]                    = "CODE_CORE_IPU1_1";
+        Program.sectMap[".cinit"]                   = "CODE_CORE_IPU1_1";
+        Program.sectMap[".pinit"]                   = "CODE_CORE_IPU1_1";
+        Program.sectMap[".args"]                    = "CODE_CORE_IPU1_1";
+        Program.sectMap[".const"]                   = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_IPU1_1"; 
+        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".stack"]                   = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_IPU1_1";
+        //BSP memory section placement
+        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".data"]                    = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".far:NDK_MMBUFFER"]        = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".far:NDK_MMBUFFER1"]       = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".far:NDK_OBJMEM"]          = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".far:NDK_PACKETMEM"]       = "PRIVATE_DATA_CORE_IPU1_1";
+               Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_IPU1_1";
+}
diff --git a/examples/edma3_driver/evmtda2xx_M4/rtsc_config/custom_config.bld b/examples/edma3_driver/evmtda2xx_M4/rtsc_config/custom_config.bld
new file mode 100644 (file)
index 0000000..3c31ec6
--- /dev/null
@@ -0,0 +1,6 @@
+/*
+ *  ======== config.bld ========
+ *  Sample Build configuration script
+ */
+
+var platform_xs = xdc.loadCapsule("platform.xs");
\ No newline at end of file
similarity index 67%
rename from examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_st_sample.cfg
rename to examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg
index e2229eadabc33b0e22767a46af8928e1066ce4e2..215f348ed281e9e2865b806045ba7c662ee15a3a 100644 (file)
@@ -1,62 +1,74 @@
-/*use modules*/\r
-var Task = xdc.useModule ("ti.sysbios.knl.Task");\r
-var BIOS      = xdc.useModule ("ti.sysbios.BIOS");\r
-var Startup   = xdc.useModule ("xdc.runtime.Startup");\r
-var System    = xdc.useModule ("xdc.runtime.System");\r
-var Log       = xdc.useModule ("xdc.runtime.Log");\r
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');\r
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');\r
-var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');\r
-var Error = xdc.useModule('xdc.runtime.Error');\r
-var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');\r
-var Program     = xdc.useModule("xdc.cfg.Program");\r
-var InitXbar    = xdc.useModule("ti.sysbios.hal.vayu.IntXbar");\r
-\r
-/* ISR/SWI stack        */\r
-Program.stack           = 0x4000;\r
-\r
-/* Heap used when creating semaphore's, TSK's or malloc() ... */\r
-Program.heap            = 0x15000;\r
-\r
-Program.sectMap[".ducatiBoot"]          = "L2_RAM";\r
-Program.sectMap[".bootVecs"]            = "L2_RAM";\r
-Program.sectMap[".ducatiGates"]         = "L2_RAM"; \r
-\r
-\r
-/* enable print of exception handing info */\r
-HwiM3.enableException = true;\r
-\r
-/* DSP/BIOS expects this to set to 1 */\r
-var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');\r
-Core.id = 0;\r
-\r
-var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');\r
-M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;\r
-M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress; \r
-\r
-/* USE EDMA3 Sample App */\r
-//xdc.loadPackage('ti.sdo.edma3.drv.sample');\r
-\r
-/* MMU/Cache related configurations                                           */\r
-var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');\r
-var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');\r
-\r
-/* Enable the cache                                                           */\r
-Cache1.enableCache = true;\r
-\r
-AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;\r
-AMMU.mediumPages[1].logicalAddress = 0x60000000;\r
-AMMU.mediumPages[1].translatedAddress = 0x43300000;\r
-AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;\r
-AMMU.mediumPages[1].size = AMMU.Medium_256K;\r
-AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;\r
-AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;\r
-AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;\r
-AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;\r
-  \r
-\r
-Task.initStackFlag = false;\r
-Task.checkStackFlag = false;\r
-\r
-Hwi.initStackFlag = false;\r
-Hwi.checkStackFlag = false;\r
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
+var Startup   = xdc.useModule ("xdc.runtime.Startup");
+var System    = xdc.useModule ("xdc.runtime.System");
+var Log       = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
+var Error = xdc.useModule('xdc.runtime.Error');
+var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+var Program     = xdc.useModule("xdc.cfg.Program");
+var InitXbar    = xdc.useModule("ti.sysbios.hal.vayu.IntXbar");
+
+/* ISR/SWI stack        */
+Program.stack           = 0x4000;
+
+/* Heap used when creating semaphore's, TSK's or malloc() ... */
+Program.heap            = 0x15000;
+
+/*Program.sectMap[".ducatiBoot"]          = "L2_RAM";
+Program.sectMap[".bootVecs"]            = "L2_RAM";
+Program.sectMap[".ducatiGates"]         = "L2_RAM"; 
+*/
+
+/* enable print of exception handing info */
+HwiM3.enableException = true;
+
+/* DSP/BIOS expects this to set to 1 */
+var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.id = 0;
+Core.ipuId = 1;
+/*
+var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;
+M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress; 
+*/
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+/* MMU/Cache related configurations                                           */
+var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+
+/* Enable the cache                                                           */
+Cache1.enableCache = true;
+
+//if (Core.id == 0)
+/*{
+       AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
+       AMMU.mediumPages[1].logicalAddress = 0x60000000;
+       AMMU.mediumPages[1].translatedAddress = 0x43300000;
+       AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
+       AMMU.mediumPages[1].size = AMMU.Medium_256K;
+       AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+       AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
+       AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+       AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+}*/
+
+if (Core.id == 1)
+{
+       var GateDualCore = xdc.useModule('ti.sysbios.family.arm.ducati.GateDualCore');
+       GateDualCore.initGates = true;
+}
+
+Task.initStackFlag = false;
+Task.checkStackFlag = false;
+
+Hwi.initStackFlag = false;
+Hwi.checkStackFlag = false;
+
+var segPlacement = xdc.loadCapsule("app_mem_seg_placement_ipu1_0.cfg");
+segPlacement.init();
\ No newline at end of file
diff --git a/examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg b/examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg
new file mode 100644 (file)
index 0000000..7781ebc
--- /dev/null
@@ -0,0 +1,73 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
+var Startup   = xdc.useModule ("xdc.runtime.Startup");
+var System    = xdc.useModule ("xdc.runtime.System");
+var Log       = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
+var Error = xdc.useModule('xdc.runtime.Error');
+var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+var Program     = xdc.useModule("xdc.cfg.Program");
+var InitXbar    = xdc.useModule("ti.sysbios.hal.vayu.IntXbar");
+
+/* ISR/SWI stack        */
+Program.stack           = 0x4000;
+
+/* Heap used when creating semaphore's, TSK's or malloc() ... */
+Program.heap            = 0x15000;
+
+/*Program.sectMap[".ducatiBoot"]          = "L2_RAM";
+Program.sectMap[".bootVecs"]            = "L2_RAM";
+Program.sectMap[".ducatiGates"]         = "L2_RAM"; 
+*/
+
+/* enable print of exception handing info */
+HwiM3.enableException = true;
+
+/* DSP/BIOS expects this to set to 1 */
+var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.id = 1;
+/*
+var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;
+M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress; 
+*/
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+/* MMU/Cache related configurations                                           */
+var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+
+/* Enable the cache                                                           */
+Cache1.enableCache = true;
+
+//if (Core.id == 0)
+/*{
+       AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
+       AMMU.mediumPages[1].logicalAddress = 0x60000000;
+       AMMU.mediumPages[1].translatedAddress = 0x43300000;
+       AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
+       AMMU.mediumPages[1].size = AMMU.Medium_256K;
+       AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+       AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
+       AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+       AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+}*/
+
+if (Core.id == 1)
+{
+       var GateDualCore = xdc.useModule('ti.sysbios.family.arm.ducati.GateDualCore');
+       GateDualCore.initGates = true;
+}
+
+Task.initStackFlag = false;
+Task.checkStackFlag = false;
+
+Hwi.initStackFlag = false;
+Hwi.checkStackFlag = false;
+
+var segPlacement = xdc.loadCapsule("app_mem_seg_placement_ipu1_1.cfg");
+segPlacement.init();
\ No newline at end of file
diff --git a/examples/edma3_driver/evmtda2xx_M4/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmtda2xx_M4/rtsc_config/mem_segment_definition.xs
new file mode 100644 (file)
index 0000000..0297224
--- /dev/null
@@ -0,0 +1,264 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *  ======== mem_segment_definition.xs ========
+ */
+
+
+function getMemSegmentDefinitionIPU_1_0()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_IPU1_0",
+    {
+          name: "CODE_CORE_IPU1_0",
+          base: 0x84000000,
+          len:  0x01000000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",
+    {
+          name: "PRIVATE_DATA_CORE_IPU1_0",
+          base: 0x85000000,
+          len:  0x01800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",
+    {
+          name: "HDVPSS_DESCRIPTOR_NON_CACHED",
+          base: 0xA1800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[6] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+    
+    return (memory);
+}
+
+function getMemSegmentDefinitionIPU_1_1()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_IPU1_1",
+    {
+          name: "CODE_CORE_IPU1_1",
+          base: 0x86800000,
+          len:  0x01000000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",
+    {
+          name: "PRIVATE_DATA_CORE_IPU1_1",
+          base: 0x87800000,
+          len:  0x01800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+    
+    return (memory);
+}
+
+function getMemSegmentDefinitionDSP_1()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_DSP1",
+    {
+          name: "CODE_CORE_DSP1",
+          base: 0x83100000,
+          len:  0x00700000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_DSP1",
+    {
+          name: "PRIVATE_DATA_CORE_DSP1",
+          base: 0x83800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+    
+    return (memory);
+}
+
+function getMemSegmentDefinitionHOST()
+{
+    var memory = new Array();
+
+    memory[8] = ["CODE_CORE_HOST",
+    {
+          name: "CODE_CORE_HOST",
+          base: 0x89000000,
+          len:  0x00800000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[9] = ["PRIVATE_DATA_CORE_HOST",
+    {
+          name: "PRIVATE_DATA_CORE_HOST",
+          base: 0x89800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[10] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[11] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[12] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[13] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    return (memory);
+}
diff --git a/examples/edma3_driver/evmtda2xx_M4/rtsc_config/platform.xs b/examples/edma3_driver/evmtda2xx_M4/rtsc_config/platform.xs
new file mode 100644 (file)
index 0000000..c4408f7
--- /dev/null
@@ -0,0 +1,62 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *  ======== platform.xs ========
+ */
+
+var Build = xdc.useModule('xdc.bld.BuildEnvironment'); 
+
+var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
+
+Build.platformTable["ti.platforms.simVayu:IPU_1_0"] =
+{      
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
+       codeMemory:"CODE_CORE_IPU1_0",
+       dataMemory:"PRIVATE_DATA_CORE_IPU1_0",
+       stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
+};
+
+Build.platformTable["ti.platforms.simVayu:IPU_1_1"] =
+{      
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
+       codeMemory:"CODE_CORE_IPU1_1",
+       dataMemory:"PRIVATE_DATA_CORE_IPU1_1",
+       stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
+};
+
+Build.platformTable["ti.platforms.simVayu:DSP_1"] =
+{
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
+    codeMemory:"CODE_CORE_DSP1",
+    dataMemory:"PRIVATE_DATA_CORE_DSP1",
+    stackMemory:"PRIVATE_DATA_CORE_DSP1"
+};
+
+Build.platformTable["ti.platforms.simVayu:EVE_1"] =
+{
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionEVE_1(),
+    codeMemory:"CODE_CORE_EVE1",
+    dataMemory:"PRIVATE_DATA_CORE_EVE1",
+    stackMemory:"PRIVATE_DATA_CORE_EVE1"
+};
+
+Build.platformTable["ti.platforms.simVayu:EVE_2"] =
+{
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionEVE_2(),
+    codeMemory:"CODE_CORE_EVE2",
+    dataMemory:"PRIVATE_DATA_CORE_EVE2",
+    stackMemory:"PRIVATE_DATA_CORE_EVE2"
+};
+
+Build.platformTable["ti.platforms.simVayu:Cortex_A15"] =
+{
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
+    codeMemory:"CODE_CORE_HOST",
+    dataMemory:"PRIVATE_DATA_CORE_HOST",
+    stackMemory:"PRIVATE_DATA_CORE_HOST"
+};
index f93cddfad89d2e318734e429c8844adf9b744d6b..046689c50b5f8d8549698878b3ac38a78aa6b578 100644 (file)
@@ -5,7 +5,7 @@ MEMORY
 \r
 SECTIONS\r
 {\r
-    .my_sect_iram > EXT_RAM\r
-    .my_sect_ddr  > EXT_RAM\r
-    .resetVecs  > L2_RAM       \r
+//    .my_sect_iram > EXT_RAM\r
+//    .my_sect_ddr  > EXT_RAM\r
+//    .resetVecs  > L2_RAM     \r
 }\r
index c764f5485ddd1e9fa6a281c5914d1b9598494ed2..bea2a3c4aaa622a509c2ee67f09c28878956aec2 100755 (executable)
@@ -2543,14 +2543,24 @@ edma3_drv_tda2xx-evm_66_example:
 edma3_drv_tda2xx-evm_m4_example:
 ifeq ($(FORMAT),ELF)
        $(ECHO) \# Configuring XDC packages for $@:m4:debug 
-       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug IPUCORE=0
        $(ECHO) \# Making example $@:debug
-       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug     
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug     IPUCORE=0
 
-       $(ECHO) \# Configuring XDC packages for $@:m4:release 
-       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
-       $(ECHO) \# Making example $@:release
-       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+#      $(ECHO) \# Configuring XDC packages for $@:m4:release 
+#      $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release IPUCORE=0
+#      $(ECHO) \# Making example $@:release
+#      $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release IPUCORE=0
+
+       $(ECHO) \# Configuring XDC packages for $@:m4:debug 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug IPUCORE=1
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug IPUCORE=1
+
+#      $(ECHO) \# Configuring XDC packages for $@:m4:release 
+#      $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release IPUCORE=1
+#      $(ECHO) \# Making example $@:release
+#      $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release IPUCORE=1
 endif
 
 edma3_drv_tda2xx-evm_a15_example:
index 10ade7c936c9806f18093b2bed9ce35a2aa4a5d9..1815c1b056c21e12790fdd0719e0858eddedf1e8 100755 (executable)
@@ -76,7 +76,7 @@ SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_arm_int_reg.c
 SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_arm_int_reg.c
 endif
 ifeq ($(CORE),m4)
-CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_IPU1
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_IPU
 endif
 ifeq ($(CORE),a15host)
 CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_MPU
index c4ddefbeecb319631a6e8b4b016833cb263099c2..e3b10c95edf8131165c996bbb8ba59022ffb1772 100644 (file)
 */\r
 \r
 #include <ti/sdo/edma3/drv/edma3_drv.h>\r
+#ifdef BUILD_TDA2XX_IPU\r
+#include <ti/sysbios/family/arm/ducati/Core.h> \r
+\r
+#endif\r
 \r
 /* Number of EDMA3 controllers present in the system */\r
 #define NUM_EDMA3_INSTANCES         2u\r
@@ -50,18 +54,47 @@ const unsigned int numDsps = NUM_DSPS;
 \r
 /* Determine the processor id by reading DNUM register. */\r
 /* Statically allocate the region numbers with cores. */\r
+int myCoreNum;\r
+#define PID0_ADDRESS 0xE00FFFE0\r
+#define CORE_ID_C0 0x0\r
+#define CORE_ID_C1 0x1\r
+\r
 unsigned short determineProcId()\r
 {\r
 #ifdef BUILD_TDA2XX_MPU\r
-       return 0;\r
+\r
+    asm ("    push    {r0-r2} \n\t"\r
+            "    MRC p15, 0, r0, c0, c0, 5\n\t"\r
+                "    LDR      r1, =myCoreNum\n\t"\r
+                "    STR      r0, [r1]\n\t"\r
+                "    pop    {r0-r2}\n\t");\r
+       if((myCoreNum & 0x03) == 1)\r
+               return 1;\r
+       else\r
+               return 0;\r
+#elif defined(BUILD_TDA2XX_IPU)\r
+myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
+if(Core_getIpuId() == 1){\r
+       if(myCoreNum == CORE_ID_C0)\r
+               return 4;\r
+       else if (myCoreNum == CORE_ID_C1)\r
+               return 5;\r
+}\r
+if(Core_getIpuId() == 2){\r
+       if(myCoreNum == CORE_ID_C0)\r
+               return 6;\r
+       else if (myCoreNum == CORE_ID_C1)\r
+               return 7;\r
+}\r
 #elif defined BUILD_TDA2XX_DSP\r
-       return 1;\r
-#elif defined BUILD_TDA2XX_IPU0\r
-       return 2;\r
-#elif defined BUILD_TDA2XX_IPU1\r
-       return 3;\r
+extern __cregister volatile unsigned int DNUM;\r
+       myCoreNum = DNUM;\r
+       if(myCoreNum == 0)\r
+               return 2;\r
+       else\r
+               return 3;\r
 #else\r
-       return 4;\r
+       return 0;\r
 #endif\r
 }\r
 \r
@@ -102,44 +135,38 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 /** Interrupt no. for Transfer Completion */\r
 #define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)\r
 #define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU0               (34u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU1               (34u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0               (34u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1               (33u)\r
 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
 #define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)\r
 #define COMPLETION_INT_DSP_XBAR_INST_NO                 (7u)\r
-#define COMPLETION_INT_IPU0_XBAR_INST_NO                (12u)\r
-#define COMPLETION_INT_IPU1_XBAR_INST_NO                (12u)\r
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO                (12u)\r
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO                (11u)\r
 \r
 /** Interrupt no. for CC Error */\r
 #define EDMA3_CC_ERROR_INT_A15                          (67u)\r
 #define EDMA3_CC_ERROR_INT_DSP                          (39u)\r
-#define EDMA3_CC_ERROR_INT_IPU0                         (35u)\r
-#define EDMA3_CC_ERROR_INT_IPU1                         (35u)\r
+#define EDMA3_CC_ERROR_INT_IPU                         (35u)\r
+\r
 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
 #define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)\r
 #define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8u)\r
-#define CC_ERROR_INT_IPU0_XBAR_INST_NO                  (13u)\r
-#define CC_ERROR_INT_IPU1_XBAR_INST_NO                  (13u)\r
-\r
+#define CC_ERROR_INT_IPU_XBAR_INST_NO                  (13u)\r
 \r
 /** Interrupt no. for TCs Error */\r
 #define EDMA3_TC0_ERROR_INT_A15                         (68u)\r
 #define EDMA3_TC0_ERROR_INT_DSP                         (40u)\r
-#define EDMA3_TC0_ERROR_INT_IPU0                        (36u)\r
-#define EDMA3_TC0_ERROR_INT_IPU1                        (36u)\r
+#define EDMA3_TC0_ERROR_INT_IPU                        (36u)\r
 #define EDMA3_TC1_ERROR_INT_A15                         (69u)\r
 #define EDMA3_TC1_ERROR_INT_DSP                         (41u)\r
-#define EDMA3_TC1_ERROR_INT_IPU0                        (37u)\r
-#define EDMA3_TC1_ERROR_INT_IPU1                        (37u)\r
+#define EDMA3_TC1_ERROR_INT_IPU                        (37u)\r
 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
 #define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)\r
 #define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9u)\r
-#define TC0_ERROR_INT_IPU0_XBAR_INST_NO                 (14u)\r
-#define TC0_ERROR_INT_IPU1_XBAR_INST_NO                 (14u)\r
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO                 (14u)\r
 #define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)\r
 #define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10u)\r
-#define TC1_ERROR_INT_IPU0_XBAR_INST_NO                 (15u)\r
-#define TC1_ERROR_INT_IPU1_XBAR_INST_NO                 (15u)\r
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO                 (15u)\r
 \r
 #ifdef BUILD_TDA2XX_MPU\r
 #define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15\r
@@ -159,23 +186,14 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_DSP_XBAR_INST_NO\r
 #define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_DSP_XBAR_INST_NO\r
 \r
-#elif defined BUILD_TDA2XX_IPU1\r
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU0\r
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU0\r
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU0_XBAR_INST_NO\r
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU0\r
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU0\r
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU0_XBAR_INST_NO\r
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU0_XBAR_INST_NO\r
-\r
-#elif defined BUILD_TDA2XX_IPU2\r
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU1\r
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU1\r
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU1_XBAR_INST_NO\r
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU1\r
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU1\r
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU1_XBAR_INST_NO\r
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU1_XBAR_INST_NO\r
+#elif defined BUILD_TDA2XX_IPU\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU_C0\r
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU\r
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU_XBAR_INST_NO\r
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU\r
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU_XBAR_INST_NO\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO\r
 \r
 #else\r
 #define EDMA3_CC_XFER_COMPLETION_INT                    {0u}\r
@@ -194,7 +212,8 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_TC6_ERROR_INT                             (0u)\r
 #define EDMA3_TC7_ERROR_INT                             (0u)\r
 \r
-#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (18u)\r
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19u)\r
+#define DSP2_EDMA3_CC_XFER_COMPLETION_INT               (20u)\r
 #define DSP1_EDMA3_CC_ERROR_INT                         {27u}\r
 #define DSP1_EDMA3_TC0_ERROR_INT                        (28u)\r
 #define DSP1_EDMA3_TC1_ERROR_INT                        (29u)\r
@@ -294,12 +313,13 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
 {\r
     {\r
-        EDMA3_CC_XFER_COMPLETION_INT_A15, EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
-               EDMA3_CC_XFER_COMPLETION_INT_IPU0, EDMA3_CC_XFER_COMPLETION_INT_IPU1,\r
-        0u, 0u, 0u, 0u,\r
+        EDMA3_CC_XFER_COMPLETION_INT_A15, EDMA3_CC_XFER_COMPLETION_INT_A15,\r
+               EDMA3_CC_XFER_COMPLETION_INT_DSP, EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
+               EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
+        EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
     },\r
     {\r
-        0u, DSP1_EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u,\r
+        0u, 0u, DSP1_EDMA3_CC_XFER_COMPLETION_INT, DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
         0u, 0u, 0u, 0u,\r
     },\r
 };\r
@@ -307,9 +327,10 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
 {\r
     {\r
-        COMPLETION_INT_A15_XBAR_INST_NO, COMPLETION_INT_DSP_XBAR_INST_NO,\r
-               COMPLETION_INT_IPU0_XBAR_INST_NO, COMPLETION_INT_IPU1_XBAR_INST_NO,\r
-        0u, 0u, 0u, 0u,\r
+        COMPLETION_INT_A15_XBAR_INST_NO, COMPLETION_INT_A15_XBAR_INST_NO,\r
+               COMPLETION_INT_DSP_XBAR_INST_NO, COMPLETION_INT_DSP_XBAR_INST_NO,\r
+               COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
+        COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
     },\r
 };\r
 \r
@@ -350,10 +371,10 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
        EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
    },\r
    {\r
-       DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
+       EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
-       EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
+       DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
    }\r
 };\r
 unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][8] =\r
@@ -411,7 +432,7 @@ unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
-#elif ((defined BUILD_TDA2XX_IPU0) || (defined BUILD_TDA2XX_IPU1))\r
+#elif (defined BUILD_TDA2XX_IPU)\r
 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x63300000))\r
 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x63400000))\r
 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x63500000))\r
@@ -545,15 +566,39 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * if it exists, otherwise of no use.\r
          */\r
             {\r
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, \r
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
-            },\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
+                       },\r
 \r
          /**\r
           * \brief Mapping from each DMA channel to a TCC. This specific\r
@@ -561,22 +606,22 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
           * on the mapped channel.\r
           */\r
             {\r
-            0u, 1u, 2u, 3u,\r
-            4u, 5u, 6u, 7u,\r
-            8u, 9u, 10u, 11u,\r
-            12u, 13u, 14u, 15u,\r
-            16u, 17u, 18u, 19u,\r
-            20u, 21u, 22u, 23u,\r
-            24u, 25u, 26u, 27u,\r
-            28u, 29u, 30u, 31u,\r
-            32u, 33u, 34u, 35u,\r
-            36u, 37u, 38u, 39u,\r
-            40u, 41u, 42u, 43u,\r
-            44u, 45u, 46u, 47u,\r
-            48u, 49u, 50u, 51u,\r
-            52u, 53u, 54u, 55u,\r
-            56u, 57u, 58u, 59u,\r
-            60u, 61u, 62u, 63u\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
             },\r
 \r
         /**\r
@@ -706,14 +751,38 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * if it exists, otherwise of no use.\r
          */\r
             {\r
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, \r
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
             },\r
 \r
          /**\r
@@ -722,22 +791,22 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
           * on the mapped channel.\r
           */\r
             {\r
-            0u, 1u, 2u, 3u,\r
-            4u, 5u, 6u, 7u,\r
-            8u, 9u, 10u, 11u,\r
-            12u, 13u, 14u, 15u,\r
-            16u, 17u, 18u, 19u,\r
-            20u, 21u, 22u, 23u,\r
-            24u, 25u, 26u, 27u,\r
-            28u, 29u, 30u, 31u,\r
-            32u, 33u, 34u, 35u,\r
-            36u, 37u, 38u, 39u,\r
-            40u, 41u, 42u, 43u,\r
-            44u, 45u, 46u, 47u,\r
-            48u, 49u, 50u, 51u,\r
-            52u, 53u, 54u, 55u,\r
-            56u, 57u, 58u, 59u,\r
-            60u, 61u, 62u, 63u\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
             },\r
 \r
         /**\r
@@ -767,7 +836,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
     {\r
                /* EDMA3 INSTANCE# 0 */\r
                {\r
-                       /* Resources owned/reserved by region 0 (Associated to any MPU core)*/\r
+                       /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
@@ -803,7 +872,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -814,7 +883,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                                {0x00u, 0x00u},\r
                        },\r
 \r
-                       /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
+                       /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
@@ -850,7 +919,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -861,11 +930,11 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                                {0x00u, 0x00u},\r
                        },\r
 \r
-               /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
+               /* Resources owned/reserved by region 2 (Associated to any IPU1 core 0)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0xFFFFFFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -875,15 +944,15 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFu, 0x00000000u},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x0000000Fu},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0xFFFFFFFFu, 0x00000000u},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
@@ -897,7 +966,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -908,11 +977,11 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                                {0x00u, 0x00u},\r
                        },\r
 \r
-               /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
+               /* Resources owned/reserved by region 3 (Associated to any IPU1 core 1)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -922,15 +991,15 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0x00000000u, 0xFFFFFFFFu},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x000000F0u},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0x00000000u, 0xFFFFFFFFu},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
@@ -944,7 +1013,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -955,33 +1024,33 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                                {0x00u, 0x00u},\r
                        },\r
 \r
-               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
+               /* Resources owned/reserved by region 4 (Associated to any IPU2 core 0)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x000000FFu},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -991,44 +1060,44 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00u},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00u, 0x00u},\r
                        },\r
 \r
-               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
+               /* Resources owned/reserved by region 5 (Associated to any IPU2 core 1)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x000000FFu},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -1038,44 +1107,44 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00u},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00u, 0x00u},\r
                        },\r
 \r
-               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
+               /* Resources owned/reserved by region 6 (Associated to any DSP core 0)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x000000FFu},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -1085,44 +1154,44 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00u},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00u, 0x00u},\r
                        },\r
 \r
-               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
+               /* Resources owned/reserved by region 7 (Associated to any DSP core 1)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x000000FFu},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -1132,15 +1201,15 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00u},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00u, 0x00u},\r
                        },\r
            },\r
                /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
@@ -1192,33 +1261,33 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                                {0x00000000u, 0x00000000u},\r
                        },\r
 \r
-                       /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
+                       /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0x00000000u, 0x00000000u},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFu},\r
+                               {0x00000000u},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+                               {0x00000000u, 0x00000000u},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -1228,44 +1297,44 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00000000u, 0x00000000u},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00u},\r
+                               {0x00000000u},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00u, 0x00u},\r
+                               {0x00000000u, 0x00000000u},\r
                        },\r
 \r
-               /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
+               /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x000000FFu},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -1275,44 +1344,44 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00u},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00u, 0x00u},\r
                        },\r
 \r
-               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
+               /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x000000FFu},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -1322,15 +1391,15 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00000000u},\r
+                               {0x00u},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00000000u, 0x00000000u},\r
+                               {0x00u, 0x00u},\r
                        },\r
 \r
                /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r