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raw | patch | inline | side by side (parent: afcf7a7)
raw | patch | inline | side by side (parent: afcf7a7)
| author | Murtaza Gaadiwala <murtaza@ti.com> | |
| Tue, 14 Feb 2012 16:23:22 +0000 (11:23 -0500) | ||
| committer | Prasad Konnur <prasad.konnur@ti.com> | |
| Mon, 7 May 2012 08:37:23 +0000 (14:07 +0530) |
Signed-off-by: Murtaza Gaadiwala <murtaza@ti.com>
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6634_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6634_cfg.c
index fb3801a4bbe1ef2c14cb8a83074561b59ac80010..6946a4bc1fbdad27a0eb1834f5a451bed4a266bd 100644 (file)
#include <ti/sdo/edma3/rm/edma3_rm.h>
/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES 3u
+#define NUM_EDMA3_INSTANCES 5u
const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
/* Number of DSPs present in the system */
-#define NUM_DSPS 4u
+#define NUM_DSPS 8u
//const unsigned int numDsps = NUM_DSPS;
#define CGEM_REG_START (0x01800000)
1, /* DSP#1 is Slave, will not do the global init */
1, /* DSP#2 is Slave, will not do the global init */
1, /* DSP#3 is Slave, will not do the global init */
+ 1, /* DSP#4 is Slave, will not do the global init */
+ 1, /* DSP#5 is Slave, will not do the global init */
+ 1, /* DSP#6 is Slave, will not do the global init */
+ 1, /* DSP#7 is Slave, will not do the global init */
};
unsigned short isGblConfigRequired(unsigned int dspNum)
}
/* Semaphore handles */
-EDMA3_OS_Sem_Handle rmSemHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
+EDMA3_OS_Sem_Handle rmSemHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL,NULL,NULL};
/* Variable which will be used internally for referring number of Event Queues. */
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u, 2u, 2u};
/* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u, 2u, 2u};
/**
* Variable which will be used internally for referring transfer completion
24u, 25u, 26u, 27u,
28u, 29u, 30u, 31u,
},
+ {
+ 225u, 226u, 227u, 228u,
+ 229u, 230u, 231u, 232u,
+ },
+ {
+ 212u, 213u, 214u, 215u,
+ 216u, 217u, 218u, 219u,
+ },
};
/**
* Variable which will be used internally for referring channel controller's
* error interrupt.
*/
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u, 220u, 207u};
/**
* Variable which will be used internally for referring transfer controllers'
18u, 19u, 20u, 21u,
0u, 0u, 0u, 0u,
},
+ {
+ 222u, 223u, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 209u, 210u, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
};
/* Driver Object Initialization Configuration */
{
/* EDMA3 INSTANCE# 0 */
/** Total number of DMA Channels supported by the EDMA3 Controller */
- 16u,
+ 64u,
/** Total number of QDMA Channels supported by the EDMA3 Controller */
8u,
/** Total number of TCCs supported by the EDMA3 Controller */
- 16u,
+ 64u,
/** Total number of PaRAM Sets supported by the EDMA3 Controller */
- 128u,
+ 512u,
/** Total number of Event Queues in the EDMA3 Controller */
2u,
/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
* DBS values. It is defined in Bytes.
*/
{
- 128u,
- 128u,
+ 256u,
+ 256u,
0u,
0u,
0u,
* if it exists, otherwise of no use.
*/
{
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
- /* DMA channels 16-63 DOES NOT exist */
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
},
/**
* on the mapped channel.
*/
{
- 0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- /* DMA channels 16-63 DOES NOT exist */
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
},
/**
* All channels need not be mapped, some can be free also.
*/
{
- 0x00003333u,
+ 0xFFFFFFFFu,
0x00000000u
}
},
* DBS values. It is defined in Bytes.
*/
{
- 64u,
- 64u,
- 64u,
- 64u,
+ 128u,
+ 128u,
+ 128u,
+ 128u,
0u,
0u,
0u,
* if it exists, otherwise of no use.
*/
{
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
- 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
- 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
- 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
},
/**
*/
{
0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
- 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
- 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
},
/**
* All channels need not be mapped, some can be free also.
*/
{
- 0x3FFF3FFFu,
- 0x3FFF3FFFu
+ 0xFFFFFFFFu,
+ 0x00000000u
}
},
0u,
},
- /**
- * \brief EDMA3 TC priority setting
- *
- * User can program the priority of the Event Queues
- * at a system-wide level. This means that the user can set the
- * priority of an IO initiated by either of the TCs (Transfer Controllers)
- * relative to IO initiated by the other bus masters on the
- * device (ARM, DSP, USB, etc)
- */
- {
- 0u,
- 1u,
- 2u,
- 3u,
- 0u,
- 0u,
- 0u,
- 0u
- },
- /**
- * \brief To Configure the Threshold level of number of events
- * that can be queued up in the Event queues. EDMA3CC error register
- * (CCERR) will indicate whether or not at any instant of time the
- * number of events queued up in any of the event queues exceeds
- * or equals the threshold/watermark value that is set
- * in the queue watermark threshold register (QWMTHRA).
- */
- {
- 16u,
- 16u,
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u
- },
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 3 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02728000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x027B0000u,
+ (void *)0x027B8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 225u,
+ /** Interrupt no. for CC Error */
+ 220u,
+ /** Interrupt no. for TCs Error */
+ {
+ 222u,
+ 223u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 4 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02708000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x027B8400u,
+ (void *)0x027B8800u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 212u,
+ /** Interrupt no. for CC Error */
+ 207u,
+ /** Interrupt no. for TCs Error */
+ {
+ 209u,
+ 210u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 256u,
+ 256u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0x00000000u
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000000Fu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000000Fu},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000000F0u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000000F0u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000F00u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000F00u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000F000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000F000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000F0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000F0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00F00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00F00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0F000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0F000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xF0000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xF0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000000Fu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000000Fu},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000000F0u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000000F0u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000F00u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000F00u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000F000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000F000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000F0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000F0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00F00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00F00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0F000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0F000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
- /**
- * \brief To Configure the Default Burst Size (DBS) of TCs.
- * An optimally-sized command is defined by the transfer controller
- * default burst size (DBS). Different TCs can have different
- * DBS values. It is defined in Bytes.
- */
- {
- 64u,
- 64u,
- 64u,
- 64u,
- 0u,
- 0u,
- 0u,
- 0u
- },
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
- /**
- * \brief Mapping from each DMA channel to a Parameter RAM set,
- * if it exists, otherwise of no use.
- */
- {
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
- 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
- 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
- 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
- },
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xF0000000u},
- /**
- * \brief Mapping from each DMA channel to a TCC. This specific
- * TCC code will be returned when the transfer is completed
- * on the mapped channel.
- */
- {
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
- 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
- 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
- },
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
- /**
- * \brief Mapping of DMA channels to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- */
- {
- 0x3FFF3FFFu,
- 0x3FFF3FFFu
- }
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xF0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
},
- };
-EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
- {
- /* EDMA3 INSTANCE# 0 */
+ /* EDMA3 INSTANCE# 2 */
{
/* Resources owned/reserved by region 0 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -662,19 +1860,19 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x0000000Fu, 0x00000000u},
+ {0x00000000u, 0x0000000Fu},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000003u},
+ {0x00000001u},
/* ownTccs */
/* 31 0 63 32 */
- {0x0000000Fu, 0x00000000u},
+ {0x00000000u, 0x0000000Fu},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -683,25 +1881,25 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
- /* 31 0 */
- {0x00000003u, 0x00000000u},
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
{0x00000000u},
/* resvdTccs */
- /* 31 0 */
- {0x00000003u, 0x00000000u},
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 1 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -709,29 +1907,29 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x000000F0u, 0x00000000u},
+ {0x00000000u, 0x000000F0u},
/* ownQdmaChannels */
/* 31 0 */
- {0x0000000Cu},
+ {0x00000002u},
/* ownTccs */
/* 31 0 63 32 */
- {0x000000F0u, 0x00000000u},
+ {0x00000000u, 0x000000F0u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000030u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -739,16 +1937,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000030u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 2 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
@@ -756,29 +1954,29 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000F00u, 0x00000000u},
+ {0x00000000u, 0x00000F00u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000030u},
+ {0x00000004u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000F00u, 0x00000000u},
+ {0x00000000u, 0x00000F00u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000300u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -786,46 +1984,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000300u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 3 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x0000F000u, 0x00000000u},
+ {0x00000000u, 0x0000F000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000C0u},
+ {0x00000008u},
/* ownTccs */
/* 31 0 63 32 */
- {0x0000F000u, 0x00000000u},
+ {0x00000000u, 0x0000F000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00003000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -833,46 +2031,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00003000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 4 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x000F0000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000010u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x000F0000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -880,46 +2078,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 5 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x00F00000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000020u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x00F00000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -927,46 +2125,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 6 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x0F000000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000040u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x0F000000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -974,46 +2172,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 7 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0xF0000000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000080u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0xF0000000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1021,39 +2219,39 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
- },
+ },
- /* EDMA3 INSTANCE# 1 */
- {
- /* Resources owned/reserved by region 0 */
+ /* EDMA3 INSTANCE# 3 */
+ {
+ /* Resources owned/reserved by region 0 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x0000FFFFu, 0x00000000u},
+ {0x00000000u, 0x0000000Fu},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000003u},
+ {0x00000001u},
/* ownTccs */
/* 31 0 63 32 */
- {0x0000FFFFu, 0x00000000u},
+ {0x00000000u, 0x0000000Fu},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1063,7 +2261,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00003FFFu, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1071,36 +2269,36 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00003FFFu, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 1 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFF0000u, 0x00000000u},
+ {0x00000000u, 0x000000F0u},
/* ownQdmaChannels */
/* 31 0 */
- {0x0000000Cu},
+ {0x00000002u},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFF0000u, 0x00000000u},
+ {0x00000000u, 0x000000F0u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1110,7 +2308,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x3FFF0000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1118,36 +2316,36 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x3FFF0000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 2 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0000FFFFu},
+ {0x00000000u, 0x00000F00u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000030u},
+ {0x00000004u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0000FFFFu},
+ {0x00000000u, 0x00000F00u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1157,7 +2355,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00003FFFu},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1165,36 +2363,36 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00003FFFu},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 3 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0xFFFF0000u},
+ {0x00000000u, 0x0000F000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000C0u},
+ {0x00000008u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0xFFFF0000u},
+ {0x00000000u, 0x0000F000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1204,7 +2402,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x3FFF0000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1212,7 +2410,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x3FFF0000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 4 */
@@ -1223,35 +2421,35 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x000F0000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000010u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x000F0000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1259,7 +2457,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 5 */
@@ -1270,35 +2468,35 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x00F00000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000020u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x00F00000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1306,7 +2504,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 6 */
@@ -1319,33 +2517,33 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x0F000000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000040u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x0F000000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1353,7 +2551,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 7 */
@@ -1366,33 +2564,33 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0xF0000000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000080u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0xF0000000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1400,39 +2598,39 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
- },
+ },
- /* EDMA3 INSTANCE# 2 */
+ /* EDMA3 INSTANCE# 4 */
{
- /* Resources owned/reserved by region 0 */
+ /* Resources owned/reserved by region 0 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x0000FFFFu, 0x00000000u},
+ {0x00000000u, 0x0000000Fu},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000003u},
+ {0x00000001u},
/* ownTccs */
/* 31 0 63 32 */
- {0x0000FFFFu, 0x00000000u},
+ {0x00000000u, 0x0000000Fu},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1442,7 +2640,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00003FFFu, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1450,36 +2648,36 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00003FFFu, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 1 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFF0000u, 0x00000000u},
+ {0x00000000u, 0x000000F0u},
/* ownQdmaChannels */
/* 31 0 */
- {0x0000000Cu},
+ {0x00000002u},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFF0000u, 0x00000000u},
+ {0x00000000u, 0x000000F0u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1489,7 +2687,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x3FFF0000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1497,36 +2695,36 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x3FFF0000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 2 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x0000FFFFu},
+ {0x00000000u, 0x00000F00u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000030u},
+ {0x00000004u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x0000FFFFu},
+ {0x00000000u, 0x00000F00u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1536,7 +2734,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00003FFFu},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1544,36 +2742,36 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00003FFFu},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 3 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0xFFFF0000u},
+ {0x00000000u, 0x0000F000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000C0u},
+ {0x00000008u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0xFFFF0000u},
+ {0x00000000u, 0x0000F000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1583,7 +2781,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x3FFF0000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1591,46 +2789,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x3FFF0000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 4 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x000F0000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000010u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x000F0000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1638,46 +2836,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 5 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x00F00000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000020u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x00F00000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1685,46 +2883,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 6 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x0F000000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000040u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x0F000000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1732,46 +2930,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
/* Resources owned/reserved by region 7 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0xF0000000u},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000080u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0xF0000000u},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
@@ -1779,9 +2977,9 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0xFFFFFFFFu, 0x00000000u},
},
- },
+ },
};
/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6634_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6634_int_reg.c
index 5380f2c2928f12b93c2695ef1b8325c9228eca67..ce60bcdbf6fffd98df088cf04623e6f6ad0bf451 100644 (file)
/* Host interrupts for transfer completion */
//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
-unsigned int ccXferHostInt[3][4] = {
- {8u, 24u, 40u, 56u},
- {9u, 25u, 41u, 57u},
- {10u, 26u, 42u, 58u},
+unsigned int ccXferHostInt[5][8] = {
+ {38u, 8u, 24u, 225u, 212u, },
+ {39u, 9u, 25u, 226u, 213u, },
+ {40u, 10, 26u, 227u, 214u, },
+ {41u, 11u, 27u, 228u, 215u, },
+ {42u, 12u, 28u, 229u, 216u, },
};
-unsigned int edma3ErrHostInt[3][4] = {
- {11u, 27u, 43u, 59u},
- {12u, 28u, 44u, 60u},
- {13u, 29u, 45u, 61u},
+unsigned int edma3ErrHostInt[5][8] = {
+ {43u, 13u, 29u, 230u, 217u},
+ {44u, 14u, 30u, 231u, 218u},
+ {45u, 15u, 31u, 232u, 219u},
+ {45u, 15u, 31u, 232u, 219u},
+ {45u, 15u, 31u, 232u, 219u},
};
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6634_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6634_cfg.c
index a98ec74874f1fe527ae58646667c0d03059cd911..5658e971038811ef58f871794827f3516c7c12cc 100644 (file)
#include <ti/sdo/edma3/rm/edma3_rm.h>
-#define NUM_EDMA3_INSTANCES 3u
+#define NUM_EDMA3_INSTANCES 5u
/* Driver Object Initialization Configuration */
EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
{
/* EDMA3 INSTANCE# 0 */
/** Total number of DMA Channels supported by the EDMA3 Controller */
- 16u,
+ 64u,
/** Total number of QDMA Channels supported by the EDMA3 Controller */
8u,
/** Total number of TCCs supported by the EDMA3 Controller */
- 16u,
+ 64u,
/** Total number of PaRAM Sets supported by the EDMA3 Controller */
- 128u,
+ 512u,
/** Total number of Event Queues in the EDMA3 Controller */
2u,
/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
* DBS values. It is defined in Bytes.
*/
{
- 128u,
- 128u,
+ 256u,
+ 256u,
0u,
0u,
0u,
* if it exists, otherwise of no use.
*/
{
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- /* DMA channels 16-63 DOES NOT exist */
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
},
/**
* on the mapped channel.
*/
{
- 0u, 1u, 2u, 3u,
- 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u,
- 12u, 13u, 14u, 15u,
- /* DMA channels 16-63 DOES NOT exist */
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
},
/**
* All channels need not be mapped, some can be free also.
*/
{
- 0x0000FFFFu,
+ 0xFFFFFFFFu,
0x00000000u
}
},
* DBS values. It is defined in Bytes.
*/
{
- 64u,
- 64u,
- 64u,
- 64u,
+ 128u,
+ 128u,
+ 128u,
+ 128u,
0u,
0u,
0u,
* if it exists, otherwise of no use.
*/
{
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
- 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
},
/**
*/
{
0xFFFFFFFFu,
- 0x0000FFFFu
+ 0x00000000u
}
},
0u
},
- /**
- * \brief To Configure the Default Burst Size (DBS) of TCs.
- * An optimally-sized command is defined by the transfer controller
- * default burst size (DBS). Different TCs can have different
- * DBS values. It is defined in Bytes.
- */
- {
- 64u,
- 64u,
- 64u,
- 64u,
- 0u,
- 0u,
- 0u,
- 0u
- },
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 3 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02728000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x027B0000u,
+ (void *)0x027B8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 225u,
+ /** Interrupt no. for CC Error */
+ 220u,
+ /** Interrupt no. for TCs Error */
+ {
+ 222u,
+ 223u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 4 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02708000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x027B8400u,
+ (void *)0x027B8800u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 212u,
+ /** Interrupt no. for CC Error */
+ 207u,
+ /** Interrupt no. for TCs Error */
+ {
+ 209u,
+ 210u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 256u,
+ 256u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0x00000000u
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000000Fu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000000Fu},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000000F0u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000000F0u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000F00u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000F00u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000F000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000F000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000F0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000F0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00F00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00F00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0F000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0F000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xF0000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xF0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000000Fu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000000Fu},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000000F0u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000000F0u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000F00u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000F00u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000F000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000F000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000F0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000F0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00F00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00F00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0F000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0F000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xF0000000u},
- /**
- * \brief Mapping from each DMA channel to a Parameter RAM set,
- * if it exists, otherwise of no use.
- */
- {
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
- EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
- },
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
- /**
- * \brief Mapping from each DMA channel to a TCC. This specific
- * TCC code will be returned when the transfer is completed
- * on the mapped channel.
- */
- {
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
- },
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xF0000000u},
- /**
- * \brief Mapping of DMA channels to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- */
- {
- 0xFFFFFFFFu,
- 0xFF0000FFu
- }
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+ },
},
- };
-EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
- {
- /* EDMA3 INSTANCE# 0 */
+ /* EDMA3 INSTANCE# 2 */
{
/* Resources owned/reserved by region 0 */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -610,19 +1730,19 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x0000000Fu},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000001u},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000u, 0x0000000Fu},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -631,25 +1751,25 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
/* resvdDmaChannels */
- /* 31 0 63 32*/
- {0x0000FFFFu, 0x00000000u},
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
/* resvdQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x00000000u},
/* resvdTccs */
- /* 31 0 63 32*/
- {0x0000FFFFu, 0x00000000u},
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
},