Put global variables in .far section
authorPrasad Konnur <prasadkonnur@ti.com>
Thu, 27 Jun 2013 14:43:57 +0000 (20:13 +0530)
committerPrasad Konnur <prasadkonnur@ti.com>
Wed, 17 Jul 2013 08:46:56 +0000 (14:16 +0530)
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
packages/ti/sdo/edma3/drv/src/edma3_drv_init.c
packages/ti/sdo/edma3/rm/makefile
packages/ti/sdo/edma3/rm/sample/makefile
packages/ti/sdo/edma3/rm/src/edma3_rm_gbl_data.c
packages/ti/sdo/edma3/rm/src/edma3resmgr.c

index 206b9362b4dc116e245795674f112813be4be8a4..2f687f4ea85208c68833cbb40c48f333f2bb988d 100755 (executable)
@@ -103,6 +103,9 @@ extern void edma3MemCpy(void *dst, const void *src, uint32_t len);
  * Typically one object will cater to one EDMA3 HW controller
  * and will have all regions' (ARM, DSP etc) specific config information.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(drvObj, ".far");
+#endif
 EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES];
 
 
@@ -115,6 +118,9 @@ EDMA3_DRV_Object drvObj [EDMA3_MAX_EDMA3_INSTANCES];
  * regions. Multiple EDMA3 Driver instances on the same shadow
  * region are NOT allowed.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(drvInstance, ".far");
+#endif
 EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
 
 
@@ -127,6 +133,9 @@ EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
  * responsibility of the driver to free up the channel-associated resources
  * from the Resource Manager layer).
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(edma3DrvChBoundRes, ".far");
+#endif
 EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
 
 
@@ -144,6 +153,9 @@ EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_
  *
  */
 #ifdef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(edma3DmaQdmaQueueNumConfig, ".far");
+#endif
 EDMA3_DRV_DmaQdmaQueueNum edma3DmaQdmaQueueNumConfig = {
         {
                /* DMA Channels 0-63 */
index 57ccdd2886c37605ea8b42824c2d36e6e507f100..b72f12b2bfd18fab8cf881a27361b46d2a9ae9e1 100644 (file)
@@ -28,6 +28,9 @@ endif
 ifeq ($(CORE),m3vpss)
 CFLAGS_LOCAL_c6a811x-evm = -DBUILD_C6A811X_M3VPSS
 endif
+ifeq ($(CORE),a15host)
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_MPU
+endif
 
 # Core/SoC/platform specific source files and CFLAGS
 # Example: 
index 820f82562ad36909466dd76b71ea47bb0b35fcad..754b46335260136538b9a78131f8769393928f54 100755 (executable)
@@ -67,6 +67,9 @@ SRCS_ti816x-sim = sample_ti816x_m3vpss_cfg.c sample_ti816x_m3vpss_int_reg.c
 SRCS_ti814x-evm = sample_ti814x_m3video_cfg.c sample_ti814x_m3video_int_reg.c
 SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_arm_int_reg.c
 endif
+ifeq ($(CORE),a15host)
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_MPU
+endif
 SRCS_c6748-evm = sample_c6748_cfg.c sample_c6748_int_reg.c
 SRCS_da830-evm = sample_da830_cfg.c sample_da830_int_reg.c
 CFLAGS_LOCAL_ti814x-evm = -DCHIP_TI814X
index 5920b187b55083d6f514b309ed7ab4f96a377e7e..5905cb299a7edcfc7bb902d5542786ccb8469335 100755 (executable)
@@ -57,6 +57,9 @@ const uint32_t EDMA3_MAX_RM_INSTANCES = 8u;
  * this info will be taken from the config file "edma3_<PLATFORM_NAME>_cfg.c",
  * for the specified platform.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(userInstInitConfigArray, ".far");
+#endif
 EDMA3_RM_InstanceInitConfig userInstInitConfigArray[EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES];
 
 
@@ -68,8 +71,10 @@ EDMA3_RM_InstanceInitConfig userInstInitConfigArray[EDMA3_MAX_EDMA3_INSTANCES][M
  * There could be a maximum of EDMA3_MAX_RM_INSTANCES instances per
  * EDMA3 HW.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(resMgrInstanceArray, ".far");
+#endif
 EDMA3_RM_Instance resMgrInstanceArray[EDMA3_MAX_EDMA3_INSTANCES][MAX_EDMA3_RM_INSTANCES];
-
 /* These pointers will be used to refer the above mentioned arrays. */
 EDMA3_RM_Instance *resMgrInstance = (EDMA3_RM_Instance *)resMgrInstanceArray;
 EDMA3_RM_InstanceInitConfig *userInitConfig = (EDMA3_RM_InstanceInitConfig *)userInstInitConfigArray;
index 72e81f5b67321f9b2255eeb60759bd255c39e247..7abd99de1c0ba834ecd65cfbc4b4659b87bda260 100755 (executable)
@@ -160,6 +160,9 @@ uint32_t edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
  * Typically one RM object will cater to one EDMA3 HW controller
  * and will have all the global config information.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(resMgrObj, ".far");
+#endif
 EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];
 
 
@@ -172,6 +175,9 @@ EDMA3_RM_Obj resMgrObj[EDMA3_MAX_EDMA3_INSTANCES];
  * scenario, this DMA channel <-> TCC mapping will be used to point to
  * the correct callback function.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(edma3DmaChTccMapping, ".far");
+#endif
 static uint32_t edma3DmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_DMA_CH];
 
 
@@ -184,6 +190,9 @@ static uint32_t edma3DmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_DMA_C
  * scenario, this QDMA channel <-> TCC mapping will be used to point to
  * the correct callback function.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(edma3QdmaChTccMapping, ".far");
+#endif
 static uint32_t edma3QdmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_QDMA_CH];
 
 
@@ -192,6 +201,9 @@ static uint32_t edma3QdmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_QDMA
  * against a particular TCC. Used to call the callback
  * functions linked to the particular channel.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(edma3IntrParams, ".far");
+#endif
 static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TCC];
 
 
@@ -202,6 +214,9 @@ static EDMA3_RM_TccCallbackParams edma3IntrParams [EDMA3_MAX_EDMA3_INSTANCES][ED
  * which shadow region registers to access. All other interrupts coming
  * from other shadow regions will not be handled.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(edma3RegionId, ".far");
+#endif
 static EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS;
 
 /** masterExists[] will be updated when the Master RM Instance modifies the
@@ -210,12 +225,18 @@ static EDMA3_RM_RegionId edma3RegionId = EDMA3_MAX_REGIONS;
  * masterExists[] is per EDMA3 hardware, hence it is created
  * as an array.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(masterExists, ".far");
+#endif
 static uint32_t masterExists [EDMA3_MAX_EDMA3_INSTANCES] = {FALSE,FALSE,FALSE};
 
 /**
  * Number of PaRAM Sets actually present on the SoC. This will be updated
  * while creating the Resource Manager Object.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(edma3NumPaRAMSets, ".far");
+#endif
 uint32_t edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS;
 
 
@@ -223,6 +244,9 @@ uint32_t edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS;
  * The list of Interrupt Channels which get allocated while requesting the
  * TCC. It will be used while checking the IPR/IPRH bits in the RM ISR.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(allocatedTCCs, ".far");
+#endif
 static uint32_t allocatedTCCs[EDMA3_MAX_EDMA3_INSTANCES][2u] =
                                                                                        {
                                                                                        {0x0u, 0x0u},
@@ -236,6 +260,9 @@ static uint32_t allocatedTCCs[EDMA3_MAX_EDMA3_INSTANCES][2u] =
  * and stored in this array. It will be referenced in
  * EDMA3_RM_allocContiguousResource () to look for contiguous resources.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(contiguousDmaRes, ".far");
+#endif
 static uint32_t contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u};
 
 /**
@@ -243,6 +270,9 @@ static uint32_t contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u};
  * and stored in this array. It will be referenced in
  * EDMA3_RM_allocContiguousResource () to look for contiguous resources.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(contiguousQdmaRes, ".far");
+#endif
 static uint32_t contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u};
 
 /**
@@ -250,6 +280,9 @@ static uint32_t contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u};
  * and stored in this array. It will be referenced in
  * EDMA3_RM_allocContiguousResource () to look for contiguous resources.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(contiguousTccRes, ".far");
+#endif
 static uint32_t contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u};
 
 /**
@@ -257,6 +290,9 @@ static uint32_t contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u};
  * and stored in this array. It will be referenced in
  * EDMA3_RM_allocContiguousResource () to look for contiguous resources.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(contiguousParamRes, ".far");
+#endif
 static uint32_t contiguousParamRes[EDMA3_MAX_PARAM_DWRDS];
 
 
@@ -268,6 +304,9 @@ static uint32_t contiguousParamRes[EDMA3_MAX_PARAM_DWRDS];
  * resource manager, when a request is made to free the channel,
  * to free up the channel-associated resources.
  */
+#ifndef BUILD_TDA2XX_MPU
+#pragma DATA_SECTION(edma3RmChBoundRes, ".far");
+#endif
 static EDMA3_RM_ChBoundResources edma3RmChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];