Updated the Doxygen generated help files for the release 02.11.00.01
authorSundaram Raju <sundaram@ti.com>
Fri, 28 Jan 2011 13:34:34 +0000 (19:04 +0530)
committerSundaram Raju <sundaram@ti.com>
Wed, 2 Feb 2011 10:09:40 +0000 (15:39 +0530)
Signed-off-by: Sundaram Raju <sundaram@ti.com>
68 files changed:
packages/ti/sdo/edma3/drv/docs/EDMA3_Driver.chm
packages/ti/sdo/edma3/drv/docs/html/annotated.html
packages/ti/sdo/edma3/drv/docs/html/classes.html
packages/ti/sdo/edma3/drv/docs/html/doxygen.css
packages/ti/sdo/edma3/drv/docs/html/functions.html
packages/ti/sdo/edma3/drv/docs/html/functions_vars.html
packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___a_p_i.html
packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___d_a_t_a_s_t_r_u_c_t.html
packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html
packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html
packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html
packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html
packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l.html
packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html
packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html
packages/ti/sdo/edma3/drv/docs/html/index.hhc
packages/ti/sdo/edma3/drv/docs/html/index.hhk
packages/ti/sdo/edma3/drv/docs/html/index.hhp
packages/ti/sdo/edma3/drv/docs/html/index.html
packages/ti/sdo/edma3/drv/docs/html/modules.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___ch_bound_resources.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___chain_options.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___evt_que_priority.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___gbl_config_params.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html [new file with mode: 0755]
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___init_config.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___instance.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___instance_init_config.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___misc_param.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___object.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html
packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___paramentry_regs.html
packages/ti/sdo/edma3/drv/docs/html/tabs.css
packages/ti/sdo/edma3/rm/docs/EDMA3_Resource_Manager.chm
packages/ti/sdo/edma3/rm/docs/html/annotated.html
packages/ti/sdo/edma3/rm/docs/html/classes.html
packages/ti/sdo/edma3/rm/docs/html/doxygen.css
packages/ti/sdo/edma3/rm/docs/html/functions.html
packages/ti/sdo/edma3/rm/docs/html/functions_vars.html
packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___a_p_i.html
packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___d_a_t_a_s_t_r_u_c_t.html
packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n.html
packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html
packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html
packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html
packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l.html
packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___d_e_f_i_n_e.html
packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html
packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html
packages/ti/sdo/edma3/rm/docs/html/index.hhc
packages/ti/sdo/edma3/rm/docs/html/index.hhk
packages/ti/sdo/edma3/rm/docs/html/index.hhp
packages/ti/sdo/edma3/rm/docs/html/index.html
packages/ti/sdo/edma3/rm/docs/html/modules.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___ch_bound_resources.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___gbl_config_params.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___gbl_err_callback_params.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html [new file with mode: 0755]
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___instance.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___instance_init_config.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___misc_param.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___obj.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___pa_r_a_m_regs.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___param.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___paramentry_regs.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___res_desc.html
packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___tcc_callback_params.html
packages/ti/sdo/edma3/rm/docs/html/tabs.css

index c723c03286b27b55e1965e6c29c2c508a535b4b3..d8eb0f58c0ed32166eff3e2dc8fe19e0b6a0c876 100755 (executable)
Binary files a/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver.chm and b/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver.chm differ
index 982b1db9967a960c3e3af03d7a9494a24e7b6956..740c0cb5492e90c47eea57b7aa0e6253f48d2f0e 100755 (executable)
@@ -1,22 +1,25 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: Data Structures</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li class="current"><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
   <div class="tabs">
     <ul>
-      <li><a href="classes.html"><span>Alphabetical&nbsp;List</span></a></li>
       <li class="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="classes.html"><span>Data&nbsp;Structure&nbsp;Index</span></a></li>
       <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
     </ul>
   </div>
@@ -27,6 +30,7 @@
   <tr><td class="indexkey"><a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html">EDMA3_DRV_ChBoundResources</a></td><td class="indexvalue">EDMA3 Channel-Bound resources </td></tr>
   <tr><td class="indexkey"><a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a></td><td class="indexvalue">Event queue priorities setup </td></tr>
   <tr><td class="indexkey"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a></td><td class="indexvalue">Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information </td></tr>
+  <tr><td class="indexkey"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a></td><td class="indexvalue">Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information </td></tr>
   <tr><td class="indexkey"><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html">EDMA3_DRV_InitConfig</a></td><td class="indexvalue">Used to Initialize the EDMA3 Driver Instance </td></tr>
   <tr><td class="indexkey"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html">EDMA3_DRV_Instance</a></td><td class="indexvalue">EDMA3 Driver Instance Configuration Structure </td></tr>
   <tr><td class="indexkey"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html">EDMA3_DRV_InstanceInitConfig</a></td><td class="indexvalue">Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information </td></tr>
@@ -36,8 +40,8 @@
   <tr><td class="indexkey"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a></td><td class="indexvalue">EDMA3 Parameter RAM Set in User Configurable format </td></tr>
 </table>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:42 2010 for EDMA3 Driver by&nbsp;
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index e648a73b69b48b01284bb18363dd086b3a7256fc..25b06a99f1eeba6b423c806e50607840794b6907 100755 (executable)
@@ -1,34 +1,37 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: Alphabetical List</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li class="current"><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
   <div class="tabs">
     <ul>
-      <li class="current"><a href="classes.html"><span>Alphabetical&nbsp;List</span></a></li>
       <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+      <li class="current"><a href="classes.html"><span>Data&nbsp;Structure&nbsp;Index</span></a></li>
       <li><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
     </ul>
   </div>
 </div>
 <div class="contents">
-<h1>Data Structure Index</h1><p><div class="qindex"><a class="qindex" href="#letter_E">E</a></div><p>
+<h1>Data Structure Index</h1><div class="qindex"><a class="qindex" href="#letter_E">E</a></div>
 <table align="center" width="95%" border="0" cellspacing="0" cellpadding="0">
 <tr><td><a name="letter_E"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&nbsp;&nbsp;E&nbsp;&nbsp;</div></td></tr></table>
-</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html">EDMA3_DRV_Instance</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___object.html">EDMA3_DRV_Object</a>&nbsp;&nbsp;&nbsp;</td></tr><tr><td><a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html">EDMA3_DRV_InstanceInitConfig</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html">EDMA3_DRV_ParamentryRegs</a>&nbsp;&nbsp;&nbsp;</td></tr><tr><td><a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html">EDMA3_DRV_ChBoundResources</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html">EDMA3_DRV_InitConfig</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html">EDMA3_DRV_MiscParam</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a>&nbsp;&nbsp;&nbsp;</td></tr></table><p><div class="qindex"><a class="qindex" href="#letter_E">E</a></div><p>
+</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html">EDMA3_DRV_Instance</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___object.html">EDMA3_DRV_Object</a>&nbsp;&nbsp;&nbsp;</td></tr><tr><td><a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html">EDMA3_DRV_InstanceInitConfig</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html">EDMA3_DRV_ParamentryRegs</a>&nbsp;&nbsp;&nbsp;</td></tr><tr><td><a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html">EDMA3_DRV_ChBoundResources</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html">EDMA3_DRV_InitConfig</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html">EDMA3_DRV_MiscParam</a>&nbsp;&nbsp;&nbsp;</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a>&nbsp;&nbsp;&nbsp;</td></tr><tr><td><a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a>&nbsp;&nbsp;&nbsp;</td></tr></table><div class="qindex"><a class="qindex" href="#letter_E">E</a></div>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:42 2010 for EDMA3 Driver by&nbsp;
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index 74c22a2f84a6046bb3db32c78b746c526b0f7b96..9ca3cafbcf430a3af0780ee6f0a3714686af3943 100755 (executable)
-BODY,H1,H2,H3,H4,H5,H6,P,CENTER,TD,TH,UL,DL,DIV {
-       font-family: Geneva, Arial, Helvetica, sans-serif;
-}
-BODY,TD {
-       font-size: 90%;
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+       font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+       font-size: 12px;
 }
-H1 {
+
+/* @group Heading Levels */
+
+h1 {
        text-align: center;
-       font-size: 160%;
+       font-size: 150%;
 }
-H2 {
+
+h2 {
        font-size: 120%;
 }
-H3 {
+
+h3 {
        font-size: 100%;
 }
-CAPTION { 
-       font-weight: bold 
+
+dt {
+       font-weight: bold;
+}
+
+div.multicol {
+       -moz-column-gap: 1em;
+       -webkit-column-gap: 1em;
+       -moz-column-count: 3;
+       -webkit-column-count: 3;
 }
-DIV.qindex {
-       width: 100%;
+
+p.startli, p.startdd {
+       margin-top: 2px;
+}
+
+p.endli {
+       margin-bottom: 0px;
+}
+
+p.enddd {
+       margin-bottom: 4px;
+}
+
+/* @end */
+
+caption {
+       font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
        background-color: #e8eef2;
        border: 1px solid #84b0c7;
        text-align: center;
        margin: 2px;
        padding: 2px;
-       line-height: 140%;
 }
-DIV.navpath {
+
+div.qindex, div.navpath {
        width: 100%;
-       background-color: #e8eef2;
-       border: 1px solid #84b0c7;
-       text-align: center;
-       margin: 2px;
-       padding: 2px;
        line-height: 140%;
 }
-DIV.navtab {
-       background-color: #e8eef2;
-       border: 1px solid #84b0c7;
-       text-align: center;
-       margin: 2px;
-       margin-right: 15px;
-       padding: 2px;
+
+div.navtab {
+       margin-right: 15px;
 }
-TD.navtab {
-       font-size: 70%;
+
+/* @group Link Styling */
+
+a {
+       color: #153788;
+       font-weight: normal;
+       text-decoration: none;
 }
-A.qindex {
-       text-decoration: none;
-       font-weight: bold;
-       color: #1A419D;
+
+.contents a:visited {
+       color: #1b77c5;
 }
-A.qindex:visited {
-       text-decoration: none;
-       font-weight: bold;
-       color: #1A419D
+
+a:hover {
+       text-decoration: underline;
 }
-A.qindex:hover {
-       text-decoration: none;
-       background-color: #ddddff;
+
+a.qindex {
+       font-weight: bold;
 }
-A.qindexHL {
-       text-decoration: none;
+
+a.qindexHL {
        font-weight: bold;
        background-color: #6666cc;
        color: #ffffff;
        border: 1px double #9295C2;
 }
-A.qindexHL:hover {
-       text-decoration: none;
-       background-color: #6666cc;
-       color: #ffffff;
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
 }
-A.qindexHL:visited { 
-       text-decoration: none; 
-       background-color: #6666cc; 
-       color: #ffffff 
+
+a.el {
+       font-weight: bold;
 }
-A.el { 
-       text-decoration: none; 
-       font-weight: bold 
+
+a.elRef {
 }
-A.elRef { 
-       font-weight: bold 
+
+a.code {
 }
-A.code:link { 
-       text-decoration: none; 
-       font-weight: normal; 
-       color: #0000FF
+
+a.codeRef {
 }
-A.code:visited { 
-       text-decoration: none; 
-       font-weight: normal; 
-       color: #0000FF
+
+/* @end */
+
+dl.el {
+       margin-left: -1cm;
 }
-A.codeRef:link { 
-       font-weight: normal; 
-       color: #0000FF
+
+.fragment {
+       font-family: monospace, fixed;
+       font-size: 105%;
 }
-A.codeRef:visited { 
-       font-weight: normal; 
-       color: #0000FF
+
+pre.fragment {
+       border: 1px solid #CCCCCC;
+       background-color: #f5f5f5;
+       padding: 4px 6px;
+       margin: 4px 8px 4px 2px;
 }
-A:hover { 
-       text-decoration: none;  
-       background-color: #f2f2ff 
+
+div.ah {
+       background-color: black;
+       font-weight: bold;
+       color: #ffffff;
+       margin-bottom: 3px;
+       margin-top: 3px
 }
-DL.el { 
-       margin-left: -1cm 
+
+div.groupHeader {
+       margin-left: 16px;
+       margin-top: 12px;
+       margin-bottom: 6px;
+       font-weight: bold;
 }
-.fragment {
-       font-family: monospace, fixed;
-       font-size: 95%;
+
+div.groupText {
+       margin-left: 16px;
+       font-style: italic;
 }
-PRE.fragment {
-       border: 1px solid #CCCCCC;
-       background-color: #f5f5f5;
-       margin-top: 4px;
-       margin-bottom: 4px;
-       margin-left: 2px;
-       margin-right: 8px;
-       padding-left: 6px;
-       padding-right: 6px;
-       padding-top: 4px;
-       padding-bottom: 4px;
-}
-DIV.ah { 
-       background-color: black; 
-       font-weight: bold; 
-       color: #ffffff; 
-       margin-bottom: 3px; 
-       margin-top: 3px 
-}
-
-DIV.groupHeader {
-       margin-left: 16px;
-       margin-top: 12px;
-       margin-bottom: 6px;
-       font-weight: bold;
-}
-DIV.groupText { 
-       margin-left: 16px; 
-       font-style: italic; 
-       font-size: 90% 
-}
-BODY {
+
+body {
        background: white;
        color: black;
        margin-right: 20px;
        margin-left: 20px;
 }
-TD.indexkey {
+
+td.indexkey {
        background-color: #e8eef2;
        font-weight: bold;
-       padding-right  : 10px;
-       padding-top    : 2px;
-       padding-left   : 10px;
-       padding-bottom : 2px;
-       margin-left    : 0px;
-       margin-right   : 0px;
-       margin-top     : 2px;
-       margin-bottom  : 2px;
        border: 1px solid #CCCCCC;
+       margin: 2px 0px 2px 0;
+       padding: 2px 10px;
 }
-TD.indexvalue {
+
+td.indexvalue {
        background-color: #e8eef2;
-       font-style: italic;
-       padding-right  : 10px;
-       padding-top    : 2px;
-       padding-left   : 10px;
-       padding-bottom : 2px;
-       margin-left    : 0px;
-       margin-right   : 0px;
-       margin-top     : 2px;
-       margin-bottom  : 2px;
        border: 1px solid #CCCCCC;
+       padding: 2px 10px;
+       margin: 2px 0px;
 }
-TR.memlist {
-       background-color: #f0f0f0; 
+
+tr.memlist {
+       background-color: #f0f0f0;
 }
-P.formulaDsp { 
-       text-align: center; 
+
+p.formulaDsp {
+       text-align: center;
 }
-IMG.formulaDsp {
+
+img.formulaDsp {
+       
 }
-IMG.formulaInl { 
-       vertical-align: middle; 
+
+img.formulaInl {
+       vertical-align: middle;
 }
-SPAN.keyword       { color: #008000 }
-SPAN.keywordtype   { color: #604020 }
-SPAN.keywordflow   { color: #e08000 }
-SPAN.comment       { color: #800000 }
-SPAN.preprocessor  { color: #806020 }
-SPAN.stringliteral { color: #002080 }
-SPAN.charliteral   { color: #008080 }
-SPAN.vhdldigit     { color: #ff00ff }
-SPAN.vhdlchar      { color: #000000 }
-SPAN.vhdlkeyword   { color: #700070 }
-SPAN.vhdllogic     { color: #ff0000 }
 
-.mdescLeft {
-       padding: 0px 8px 4px 8px;
-       font-size: 80%;
-       font-style: italic;
-       background-color: #FAFAFA;
-       border-top: 1px none #E0E0E0;
-       border-right: 1px none #E0E0E0;
-       border-bottom: 1px none #E0E0E0;
-       border-left: 1px none #E0E0E0;
-       margin: 0px;
+div.center {
+       text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
 }
-.mdescRight {
-        padding: 0px 8px 4px 8px;
-       font-size: 80%;
-       font-style: italic;
-       background-color: #FAFAFA;
-       border-top: 1px none #E0E0E0;
-       border-right: 1px none #E0E0E0;
-       border-bottom: 1px none #E0E0E0;
-       border-left: 1px none #E0E0E0;
-       margin: 0px;
+
+div.center img {
+       border: 0px;
 }
-.memItemLeft {
-       padding: 1px 0px 0px 8px;
-       margin: 4px;
-       border-top-width: 1px;
-       border-right-width: 1px;
-       border-bottom-width: 1px;
-       border-left-width: 1px;
-       border-top-color: #E0E0E0;
-       border-right-color: #E0E0E0;
-       border-bottom-color: #E0E0E0;
-       border-left-color: #E0E0E0;
-       border-top-style: solid;
-       border-right-style: none;
-       border-bottom-style: none;
-       border-left-style: none;
-       background-color: #FAFAFA;
-       font-size: 80%;
+
+img.footer {
+       border: 0px;
+       vertical-align: middle;
 }
-.memItemRight {
-       padding: 1px 8px 0px 8px;
-       margin: 4px;
-       border-top-width: 1px;
-       border-right-width: 1px;
-       border-bottom-width: 1px;
-       border-left-width: 1px;
-       border-top-color: #E0E0E0;
-       border-right-color: #E0E0E0;
-       border-bottom-color: #E0E0E0;
-       border-left-color: #E0E0E0;
-       border-top-style: solid;
-       border-right-style: none;
-       border-bottom-style: none;
-       border-left-style: none;
-       background-color: #FAFAFA;
-       font-size: 80%;
+
+/* @group Code Colorization */
+
+span.keyword {
+       color: #008000
 }
-.memTemplItemLeft {
-       padding: 1px 0px 0px 8px;
-       margin: 4px;
-       border-top-width: 1px;
-       border-right-width: 1px;
-       border-bottom-width: 1px;
-       border-left-width: 1px;
-       border-top-color: #E0E0E0;
-       border-right-color: #E0E0E0;
-       border-bottom-color: #E0E0E0;
-       border-left-color: #E0E0E0;
-       border-top-style: none;
-       border-right-style: none;
-       border-bottom-style: none;
-       border-left-style: none;
-       background-color: #FAFAFA;
-       font-size: 80%;
+
+span.keywordtype {
+       color: #604020
 }
-.memTemplItemRight {
-       padding: 1px 8px 0px 8px;
-       margin: 4px;
-       border-top-width: 1px;
-       border-right-width: 1px;
-       border-bottom-width: 1px;
-       border-left-width: 1px;
-       border-top-color: #E0E0E0;
-       border-right-color: #E0E0E0;
-       border-bottom-color: #E0E0E0;
-       border-left-color: #E0E0E0;
-       border-top-style: none;
-       border-right-style: none;
-       border-bottom-style: none;
-       border-left-style: none;
-       background-color: #FAFAFA;
-       font-size: 80%;
+
+span.keywordflow {
+       color: #e08000
 }
-.memTemplParams {
-       padding: 1px 0px 0px 8px;
-       margin: 4px;
-       border-top-width: 1px;
-       border-right-width: 1px;
-       border-bottom-width: 1px;
-       border-left-width: 1px;
-       border-top-color: #E0E0E0;
-       border-right-color: #E0E0E0;
-       border-bottom-color: #E0E0E0;
-       border-left-color: #E0E0E0;
-       border-top-style: solid;
-       border-right-style: none;
-       border-bottom-style: none;
-       border-left-style: none;
-       color: #606060;
-       background-color: #FAFAFA;
-       font-size: 80%;
+
+span.comment {
+       color: #800000
+}
+
+span.preprocessor {
+       color: #806020
+}
+
+span.stringliteral {
+       color: #002080
+}
+
+span.charliteral {
+       color: #008080
+}
+
+span.vhdldigit { 
+       color: #ff00ff 
+}
+
+span.vhdlchar { 
+       color: #000000 
+}
+
+span.vhdlkeyword { 
+       color: #700070 
+}
+
+span.vhdllogic { 
+       color: #ff0000 
 }
-.search { 
+
+/* @end */
+
+.search {
        color: #003399;
        font-weight: bold;
 }
-FORM.search {
+
+form.search {
        margin-bottom: 0px;
        margin-top: 0px;
 }
-INPUT.search { 
+
+input.search {
        font-size: 75%;
        color: #000080;
        font-weight: normal;
        background-color: #e8eef2;
 }
-TD.tiny { 
+
+td.tiny {
        font-size: 75%;
 }
-a {
-       color: #1A41A8;
-}
-a:visited {
-       color: #2A3798;
-}
-.dirtab { 
+
+.dirtab {
        padding: 4px;
        border-collapse: collapse;
        border: 1px solid #84b0c7;
 }
-TH.dirtab { 
+
+th.dirtab {
        background: #e8eef2;
        font-weight: bold;
 }
-HR { 
-       height: 1px;
+
+hr {
+       height: 0;
+       border: none;
+       border-top: 1px solid #666;
+}
+
+/* @group Member Descriptions */
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+       background-color: #FAFAFA;
        border: none;
-       border-top: 1px solid black;
+       margin: 4px;
+       padding: 1px 0 0 8px;
 }
 
-/* Style for detailed member documentation */
+.mdescLeft, .mdescRight {
+       padding: 0px 8px 4px 8px;
+       color: #555;
+}
+
+.memItemLeft, .memItemRight, .memTemplParams {
+       border-top: 1px solid #ccc;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memTemplParams {
+       color: #606060;
+        white-space: nowrap;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
 .memtemplate {
        font-size: 80%;
        color: #606060;
        font-weight: normal;
        margin-left: 3px;
-} 
-.memnav { 
+}
+
+.memnav {
        background-color: #e8eef2;
        border: 1px solid #84b0c7;
        text-align: center;
@@ -365,69 +343,156 @@ HR {
        margin-right: 15px;
        padding: 2px;
 }
+
 .memitem {
-       padding: 4px;
-       background-color: #eef3f5;
-       border-width: 1px;
-       border-style: solid;
-       border-color: #dedeee;
-       -moz-border-radius: 8px 8px 8px 8px;
+       padding: 0;
+       margin-bottom: 10px;
 }
+
 .memname {
        white-space: nowrap;
        font-weight: bold;
 }
-.memdoc{
-       padding-left: 10px;
+
+.memproto, .memdoc {
+       border: 1px solid #84b0c7;      
 }
+
 .memproto {
+       padding: 0;
        background-color: #d5e1e8;
-       width: 100%;
-       border-width: 1px;
-       border-style: solid;
-       border-color: #84b0c7;
        font-weight: bold;
-       -moz-border-radius: 8px 8px 8px 8px;
+       -webkit-border-top-left-radius: 8px;
+       -webkit-border-top-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+       -moz-border-radius-topleft: 8px;
+       -moz-border-radius-topright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+
 }
+
+.memdoc {
+       padding: 2px 5px;
+       background-color: #eef3f5;
+       border-top-width: 0;
+       -webkit-border-bottom-left-radius: 8px;
+       -webkit-border-bottom-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+       -moz-border-radius-bottomleft: 8px;
+       -moz-border-radius-bottomright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+}
+
 .paramkey {
        text-align: right;
 }
+
 .paramtype {
        white-space: nowrap;
 }
+
 .paramname {
        color: #602020;
-       font-style: italic;
        white-space: nowrap;
 }
-/* End Styling for detailed member documentation */
+.paramname em {
+       font-style: normal;
+}
+
+/* @end */
+
+/* @group Directory (tree) */
 
 /* for the tree view */
+
 .ftvtree {
        font-family: sans-serif;
-       margin:0.5em;
+       margin: 0.5em;
 }
-.directory { 
-       font-size: 9pt; 
-       font-weight: bold; 
+
+/* these are for tree view when used as main index */
+
+.directory {
+       font-size: 9pt;
+       font-weight: bold;
 }
-.directory h3 { 
-       margin: 0px; 
-       margin-top: 1em; 
-       font-size: 11pt; 
+
+.directory h3 {
+       margin: 0px;
+       margin-top: 1em;
+       font-size: 11pt;
 }
-.directory > h3 { 
-       margin-top: 0; 
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice.  Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+       height: 61px;
+       background-repeat: no-repeat;
+       background-image: url("yourimage.gif");
 }
-.directory p { 
-       margin: 0px; 
-       white-space: nowrap; 
+.directory h3.swap span {
+       display: none;
 }
-.directory div { 
-       display: none; 
-       margin: 0px; 
+*/
+
+.directory > h3 {
+       margin-top: 0;
 }
-.directory img { 
-       vertical-align: -30%; 
+
+.directory p {
+       margin: 0px;
+       white-space: nowrap;
+}
+
+.directory div {
+       display: none;
+       margin: 0px;
+}
+
+.directory img {
+       vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+       font-size: 100%;
+       font-weight: bold;
+}
+
+.directory-alt h3 {
+       margin: 0px;
+       margin-top: 1em;
+       font-size: 11pt;
 }
 
+.directory-alt > h3 {
+       margin-top: 0;
+}
+
+.directory-alt p {
+       margin: 0px;
+       white-space: nowrap;
+}
+
+.directory-alt div {
+       display: none;
+       margin: 0px;
+}
+
+.directory-alt img {
+       vertical-align: -30%;
+}
+
+/* @end */
+
+address {
+       font-style: normal;
+       color: #333;
+}
index dc31392b6780c7f0de8381ddd8f0bbffa13d77e8..adbabb2f4218c92b082ddc45f45f41550d608fdd 100755 (executable)
@@ -1,22 +1,25 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: Data Fields</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li class="current"><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
   <div class="tabs">
     <ul>
-      <li><a href="classes.html"><span>Alphabetical&nbsp;List</span></a></li>
       <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="classes.html"><span>Data&nbsp;Structure&nbsp;Index</span></a></li>
       <li class="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
     </ul>
   </div>
       <li><a href="#index_x"><span>x</span></a></li>
     </ul>
   </div>
-
-<p>
 </div>
 <div class="contents">
 Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
-<p>
-<h3><a class="anchor" name="index_a">- a -</a></h3><ul>
+
+<h3><a class="anchor" id="index_a">- a -</a></h3><ul>
 <li>A_B_CNT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#07ebc5f75c693a5b50383c0804d1d9e7">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a07ebc5f75c693a5b50383c0804d1d9e7">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>aCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a8b1127bdb0fa8d104a2bdab4c629620">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aa8b1127bdb0fa8d104a2bdab4c629620">EDMA3_DRV_PaRAMRegs</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_b">- b -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_b">- b -</a></h3><ul>
 <li>bCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#0311c99486c3c8c3ae20751289256ac0">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0311c99486c3c8c3ae20751289256ac0">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>bCntReload
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#877333b51a48685e71608f3d65856049">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a877333b51a48685e71608f3d65856049">EDMA3_DRV_PaRAMRegs</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_c">- c -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_c">- c -</a></h3><ul>
 <li>ccError
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#5f7297703c68fdb4d6e9b2a5d4750040">EDMA3_DRV_GblConfigParams</a>
-<li>cCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#675509d3b2db629f66cf296ef0498c7d">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a5f7297703c68fdb4d6e9b2a5d4750040">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>CCNT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#b533890c55e9dd3a71be6b02021823b3">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#ab533890c55e9dd3a71be6b02021823b3">EDMA3_DRV_ParamentryRegs</a>
+</li>
+<li>cCnt
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a675509d3b2db629f66cf296ef0498c7d">EDMA3_DRV_PaRAMRegs</a>
+</li>
+<li>configScrMapXbarToEvt
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ab697a86b3efb21d2ddbbafa2519d21b1">EDMA3_DRV_Instance</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_d">- d -</a></h3><ul>
 <li>destAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#6e8b9889c9d5d9c60961dd1e40330b40">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a6e8b9889c9d5d9c60961dd1e40330b40">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>destBIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#20c505ef21d1c7f1f3c4a7309488ed9c">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a20c505ef21d1c7f1f3c4a7309488ed9c">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>destCIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#0a4d37d7b9a0025f7285d3d788635761">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0a4d37d7b9a0025f7285d3d788635761">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>dmaChannelHwEvtMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#c205feb9fd0a3575627dbec2f95d176c">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ac205feb9fd0a3575627dbec2f95d176c">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>dmaChannelPaRAMMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ef6b47382a74f4aabfa050f6213512d4">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aef6b47382a74f4aabfa050f6213512d4">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>dmaChannelTccMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#09dc86e6c4cbda84547c3033532e1b98">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a09dc86e6c4cbda84547c3033532e1b98">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>dmaChPaRAMMapExists
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#38ffcc4df844701e587fddc6625255b8">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a38ffcc4df844701e587fddc6625255b8">EDMA3_DRV_GblConfigParams</a>
+</li>
+<li>dmaMapXbarToChan
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#a81951f5e7e005e5916aed68b4996181c">EDMA3_DRV_GblXbarToChanConfigParams</a>
+</li>
 <li>drvInstInitConfig
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#d499f6a143851371949c908713c9e640">EDMA3_DRV_Instance</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#0311bf1e9522f4b7c3543bd8b76f6a88">EDMA3_DRV_InitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a0311bf1e9522f4b7c3543bd8b76f6a88">EDMA3_DRV_InitConfig</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ad499f6a143851371949c908713c9e640">EDMA3_DRV_Instance</a>
+</li>
 <li>drvSemHandle
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#50b80ecf78fdb0b172719f92cce22d02">EDMA3_DRV_InitConfig</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#50d92b6f9d98acc19589f3585d17023f">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a50d92b6f9d98acc19589f3585d17023f">EDMA3_DRV_Instance</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a50b80ecf78fdb0b172719f92cce22d02">EDMA3_DRV_InitConfig</a>
+</li>
+<li>drvXbarToEvtMapConfig
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a012dd7bf9aa72726cbe3e5553f778124">EDMA3_DRV_Instance</a>
+</li>
 <li>DST
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#eed3278cea3d526c83477a4cc0eaee40">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aeed3278cea3d526c83477a4cc0eaee40">EDMA3_DRV_ParamentryRegs</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_e">- e -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_e">- e -</a></h3><ul>
 <li>evtQPri
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#8970e4cce82366cef852a60cc5dc1a5a">EDMA3_DRV_GblConfigParams</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#858e5c4051b793b974e6d268c328f2cf">EDMA3_DRV_EvtQuePriority</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a8970e4cce82366cef852a60cc5dc1a5a">EDMA3_DRV_GblConfigParams</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#a858e5c4051b793b974e6d268c328f2cf">EDMA3_DRV_EvtQuePriority</a>
+</li>
 <li>evtQueueWaterMarkLvl
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#60f00b339733c6126951a688072b53b3">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a60f00b339733c6126951a688072b53b3">EDMA3_DRV_GblConfigParams</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_g">- g -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_g">- g -</a></h3><ul>
 <li>gblCfgParams
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#42669ba83291891a8e233c49aff390c3">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#a42669ba83291891a8e233c49aff390c3">EDMA3_DRV_Object</a>
+</li>
 <li>gblerrCb
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#416b12b38ea85487ca86df5d83754cc2">EDMA3_DRV_InitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a416b12b38ea85487ca86df5d83754cc2">EDMA3_DRV_InitConfig</a>
+</li>
 <li>gblerrCbParams
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#8db1897e81a58f66102840e992056e16">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a8db1897e81a58f66102840e992056e16">EDMA3_DRV_Instance</a>
+</li>
 <li>gblerrData
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#dac2401cfe0a00f0d517aaf54df6d489">EDMA3_DRV_InitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#adac2401cfe0a00f0d517aaf54df6d489">EDMA3_DRV_InitConfig</a>
+</li>
 <li>globalRegs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#5efff8708e94a49f71b055578549c97a">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a5efff8708e94a49f71b055578549c97a">EDMA3_DRV_GblConfigParams</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_i">- i -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_i">- i -</a></h3><ul>
 <li>isMaster
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a03b188471e9dc09af09a3b9096f7712">EDMA3_DRV_InitConfig</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#5e27d856f44f731c3182c1a854a7acb6">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#aa03b188471e9dc09af09a3b9096f7712">EDMA3_DRV_InitConfig</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a5e27d856f44f731c3182c1a854a7acb6">EDMA3_DRV_Instance</a>
+</li>
 <li>isSlave
-: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#812d8f331ad701c3927e28ce4c86d8c0">EDMA3_DRV_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a812d8f331ad701c3927e28ce4c86d8c0">EDMA3_DRV_MiscParam</a>
+</li>
 <li>itcchEn
-: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#dcd7e3719abfabb3dd1778835002c7c8">EDMA3_DRV_ChainOptions</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#adcd7e3719abfabb3dd1778835002c7c8">EDMA3_DRV_ChainOptions</a>
+</li>
 <li>itcintEn
-: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#4e5e184a2190f0cbd6fb8a70d86e3b43">EDMA3_DRV_ChainOptions</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#a4e5e184a2190f0cbd6fb8a70d86e3b43">EDMA3_DRV_ChainOptions</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_l">- l -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_l">- l -</a></h3><ul>
 <li>LINK_BCNTRLD
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#cda2db23599012f467bf51f22a01af9e">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#acda2db23599012f467bf51f22a01af9e">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>linkAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#9a90c589c5d20e363b8cd9a64732009e">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a9a90c589c5d20e363b8cd9a64732009e">EDMA3_DRV_PaRAMRegs</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_m">- m -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_m">- m -</a></h3><ul>
+<li>mapXbarToChan
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afac1f63dcd293985df3777abab3b2f9a">EDMA3_DRV_Instance</a>
+</li>
 <li>memProtectionExists
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#fd883a70d5f8bb868e65a69aa44d0f8e">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#afd883a70d5f8bb868e65a69aa44d0f8e">EDMA3_DRV_GblConfigParams</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_n">- n -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_n">- n -</a></h3><ul>
 <li>numDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#1d71e6ded1e1b3d3b14b20a11f896ce3">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1d71e6ded1e1b3d3b14b20a11f896ce3">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numEvtQueue
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#d27e2c83868656fa72ee70a64ac3a534">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ad27e2c83868656fa72ee70a64ac3a534">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numOpens
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#a02b8fca5781ab737d267b0b46598b80">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#aa02b8fca5781ab737d267b0b46598b80">EDMA3_DRV_Object</a>
+</li>
 <li>numPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#9bf9fc29152fe9ddb63bc86683149fc9">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9bf9fc29152fe9ddb63bc86683149fc9">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#629d5fc8d59adc8644f5f7a2691b8230">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a629d5fc8d59adc8644f5f7a2691b8230">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numRegions
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#30316db491c3d5f08182dc5bdde92463">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a30316db491c3d5f08182dc5bdde92463">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#14c6249081e4225ea140904758377c53">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a14c6249081e4225ea140904758377c53">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numTcs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#8285aab9b38d6369896777f08cb8febd">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a8285aab9b38d6369896777f08cb8febd">EDMA3_DRV_GblConfigParams</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_o">- o -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_o">- o -</a></h3><ul>
 <li>OPT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#96fe729021c036ee4a39d58a3c6400e8">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a96fe729021c036ee4a39d58a3c6400e8">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>opt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#32d762dd945673da57fc34f633d078a0">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a32d762dd945673da57fc34f633d078a0">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>ownDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a718b355bf902648c421aef695836fa4">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#aa718b355bf902648c421aef695836fa4">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>ownPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#b14f2d879a9d96a3eb41756e134706c8">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ab14f2d879a9d96a3eb41756e134706c8">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>ownQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#38f397851f049cdebe32340cd2c651c0">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a38f397851f049cdebe32340cd2c651c0">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>ownTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#d90d5a8af55128a3157afb45a4f68d56">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad90d5a8af55128a3157afb45a4f68d56">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_p">- p -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_p">- p -</a></h3><ul>
 <li>param
-: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#9359f6ade97d2f3d910097fafd73da0a">EDMA3_DRV_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a9359f6ade97d2f3d910097fafd73da0a">EDMA3_DRV_MiscParam</a>
+</li>
 <li>paRAMId
-: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#7e7e0d656a59da04f54465a45e078a03">EDMA3_DRV_ChBoundResources</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#a7e7e0d656a59da04f54465a45e078a03">EDMA3_DRV_ChBoundResources</a>
+</li>
 <li>pDrvObjectHandle
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#cc5b518c2a22a43289ca39438133a30b">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#acc5b518c2a22a43289ca39438133a30b">EDMA3_DRV_Instance</a>
+</li>
 <li>phyCtrllerInstId
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#e0923a080e0da9d1b23cd9cf655775aa">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#ae0923a080e0da9d1b23cd9cf655775aa">EDMA3_DRV_Object</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_r">- r -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_r">- r -</a></h3><ul>
 <li>regionId
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#203b65f7e1176d9c5a7736411ba97df8">EDMA3_DRV_InitConfig</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#1eb007f153b58999588f5649ecd2143f">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a203b65f7e1176d9c5a7736411ba97df8">EDMA3_DRV_InitConfig</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a1eb007f153b58999588f5649ecd2143f">EDMA3_DRV_Instance</a>
+</li>
 <li>reserved
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#6285ab933f20d29b5d6892b895582e24">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a6285ab933f20d29b5d6892b895582e24">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>resMgrInstance
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#fc40e1cb787bbdae7afee7c6ea14109e">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afc40e1cb787bbdae7afee7c6ea14109e">EDMA3_DRV_Instance</a>
+</li>
 <li>resvdDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#30630e869042596c4ed487a09bea35c3">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a30630e869042596c4ed487a09bea35c3">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>resvdPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#81d8b8d85f09f042658db196e208794b">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a81d8b8d85f09f042658db196e208794b">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>resvdQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#d6707e2582dc13b7ea4d3a854834406e">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad6707e2582dc13b7ea4d3a854834406e">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>resvdTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#175d4b970b6bf34c05700f4105bae5a6">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a175d4b970b6bf34c05700f4105bae5a6">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_s">- s -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_s">- s -</a></h3><ul>
 <li>shadowRegs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#d92603735455f8173b6e65467b78694a">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ad92603735455f8173b6e65467b78694a">EDMA3_DRV_Instance</a>
+</li>
 <li>SRC
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#6db0f14547c0586bffb62194ffffaf75">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a6db0f14547c0586bffb62194ffffaf75">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>SRC_DST_BIDX
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#ba20f4c8db04e562e01c6791cfebf258">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aba20f4c8db04e562e01c6791cfebf258">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>SRC_DST_CIDX
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#65b8a533cf4f336b920341d35b9a10ad">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a65b8a533cf4f336b920341d35b9a10ad">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>srcAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#8ac1ab47f33fd6834ed4b378a33faf13">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a8ac1ab47f33fd6834ed4b378a33faf13">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>srcBIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#47d95d95fa2d572116180de42eae6d33">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a47d95d95fa2d572116180de42eae6d33">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>srcCIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#cceb3dbc415f63ee4974c9f3a11a11c6">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#acceb3dbc415f63ee4974c9f3a11a11c6">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>state
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#dfc26946970b87cc67579ec54c73a221">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#adfc26946970b87cc67579ec54c73a221">EDMA3_DRV_Object</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_t">- t -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_t">- t -</a></h3><ul>
 <li>tcc
-: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#e9afabd97444eada59c7a74a62a5e20d">EDMA3_DRV_ChBoundResources</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ae9afabd97444eada59c7a74a62a5e20d">EDMA3_DRV_ChBoundResources</a>
+</li>
 <li>tcchEn
-: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#ceecc5cf449e9e5ec46f0ed1854af6e7">EDMA3_DRV_ChainOptions</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#aceecc5cf449e9e5ec46f0ed1854af6e7">EDMA3_DRV_ChainOptions</a>
+</li>
 <li>tcDefaultBurstSize
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a217c4ed918c9d5d695ee19ced91ef00">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aa217c4ed918c9d5d695ee19ced91ef00">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>tcError
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#3fdbb69b709ecd01dc903ec47e59f5a8">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a3fdbb69b709ecd01dc903ec47e59f5a8">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>tcintEn
-: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#6d0d65081b0538bed2734adc7c904d61">EDMA3_DRV_ChainOptions</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#a6d0d65081b0538bed2734adc7c904d61">EDMA3_DRV_ChainOptions</a>
+</li>
 <li>tcRegs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#31847b941f3a290ef68992ea3683228f">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a31847b941f3a290ef68992ea3683228f">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>trigMode
-: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#37ce2e0c452db7c087997ed2d4003c8b">EDMA3_DRV_ChBoundResources</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#a37ce2e0c452db7c087997ed2d4003c8b">EDMA3_DRV_ChBoundResources</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_x">- x -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_x">- x -</a></h3><ul>
 <li>xferCompleteInt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#08b4ad4be6b0cd9c6dd046dfe4f68c1e">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a08b4ad4be6b0cd9c6dd046dfe4f68c1e">EDMA3_DRV_GblConfigParams</a>
+</li>
 </ul>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:42 2010 for EDMA3 Driver by&nbsp;
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index e03a887367d4dc258c7887fe01549ad326bf3299..46a7a0e1f49a19d73064f9922c48b4ef3e827634 100755 (executable)
@@ -1,22 +1,25 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: Data Fields - Variables</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li class="current"><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li class="current"><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
   <div class="tabs">
     <ul>
-      <li><a href="classes.html"><span>Alphabetical&nbsp;List</span></a></li>
       <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="classes.html"><span>Data&nbsp;Structure&nbsp;Index</span></a></li>
       <li class="current"><a href="functions.html"><span>Data&nbsp;Fields</span></a></li>
     </ul>
   </div>
       <li><a href="#index_x"><span>x</span></a></li>
     </ul>
   </div>
-
-<p>
 </div>
 <div class="contents">
 &nbsp;
-<p>
-<h3><a class="anchor" name="index_a">- a -</a></h3><ul>
+
+<h3><a class="anchor" id="index_a">- a -</a></h3><ul>
 <li>A_B_CNT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#07ebc5f75c693a5b50383c0804d1d9e7">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a07ebc5f75c693a5b50383c0804d1d9e7">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>aCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a8b1127bdb0fa8d104a2bdab4c629620">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aa8b1127bdb0fa8d104a2bdab4c629620">EDMA3_DRV_PaRAMRegs</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_b">- b -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_b">- b -</a></h3><ul>
 <li>bCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#0311c99486c3c8c3ae20751289256ac0">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0311c99486c3c8c3ae20751289256ac0">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>bCntReload
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#877333b51a48685e71608f3d65856049">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a877333b51a48685e71608f3d65856049">EDMA3_DRV_PaRAMRegs</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_c">- c -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_c">- c -</a></h3><ul>
 <li>ccError
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#5f7297703c68fdb4d6e9b2a5d4750040">EDMA3_DRV_GblConfigParams</a>
-<li>cCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#675509d3b2db629f66cf296ef0498c7d">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a5f7297703c68fdb4d6e9b2a5d4750040">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>CCNT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#b533890c55e9dd3a71be6b02021823b3">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#ab533890c55e9dd3a71be6b02021823b3">EDMA3_DRV_ParamentryRegs</a>
+</li>
+<li>cCnt
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a675509d3b2db629f66cf296ef0498c7d">EDMA3_DRV_PaRAMRegs</a>
+</li>
+<li>configScrMapXbarToEvt
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ab697a86b3efb21d2ddbbafa2519d21b1">EDMA3_DRV_Instance</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_d">- d -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_d">- d -</a></h3><ul>
 <li>destAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#6e8b9889c9d5d9c60961dd1e40330b40">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a6e8b9889c9d5d9c60961dd1e40330b40">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>destBIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#20c505ef21d1c7f1f3c4a7309488ed9c">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a20c505ef21d1c7f1f3c4a7309488ed9c">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>destCIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#0a4d37d7b9a0025f7285d3d788635761">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0a4d37d7b9a0025f7285d3d788635761">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>dmaChannelHwEvtMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#c205feb9fd0a3575627dbec2f95d176c">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ac205feb9fd0a3575627dbec2f95d176c">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>dmaChannelPaRAMMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ef6b47382a74f4aabfa050f6213512d4">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aef6b47382a74f4aabfa050f6213512d4">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>dmaChannelTccMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#09dc86e6c4cbda84547c3033532e1b98">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a09dc86e6c4cbda84547c3033532e1b98">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>dmaChPaRAMMapExists
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#38ffcc4df844701e587fddc6625255b8">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a38ffcc4df844701e587fddc6625255b8">EDMA3_DRV_GblConfigParams</a>
+</li>
+<li>dmaMapXbarToChan
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#a81951f5e7e005e5916aed68b4996181c">EDMA3_DRV_GblXbarToChanConfigParams</a>
+</li>
 <li>drvInstInitConfig
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#d499f6a143851371949c908713c9e640">EDMA3_DRV_Instance</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#0311bf1e9522f4b7c3543bd8b76f6a88">EDMA3_DRV_InitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a0311bf1e9522f4b7c3543bd8b76f6a88">EDMA3_DRV_InitConfig</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ad499f6a143851371949c908713c9e640">EDMA3_DRV_Instance</a>
+</li>
 <li>drvSemHandle
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#50b80ecf78fdb0b172719f92cce22d02">EDMA3_DRV_InitConfig</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#50d92b6f9d98acc19589f3585d17023f">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a50d92b6f9d98acc19589f3585d17023f">EDMA3_DRV_Instance</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a50b80ecf78fdb0b172719f92cce22d02">EDMA3_DRV_InitConfig</a>
+</li>
+<li>drvXbarToEvtMapConfig
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a012dd7bf9aa72726cbe3e5553f778124">EDMA3_DRV_Instance</a>
+</li>
 <li>DST
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#eed3278cea3d526c83477a4cc0eaee40">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aeed3278cea3d526c83477a4cc0eaee40">EDMA3_DRV_ParamentryRegs</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_e">- e -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_e">- e -</a></h3><ul>
 <li>evtQPri
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#8970e4cce82366cef852a60cc5dc1a5a">EDMA3_DRV_GblConfigParams</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#858e5c4051b793b974e6d268c328f2cf">EDMA3_DRV_EvtQuePriority</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a8970e4cce82366cef852a60cc5dc1a5a">EDMA3_DRV_GblConfigParams</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#a858e5c4051b793b974e6d268c328f2cf">EDMA3_DRV_EvtQuePriority</a>
+</li>
 <li>evtQueueWaterMarkLvl
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#60f00b339733c6126951a688072b53b3">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a60f00b339733c6126951a688072b53b3">EDMA3_DRV_GblConfigParams</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_g">- g -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_g">- g -</a></h3><ul>
 <li>gblCfgParams
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#42669ba83291891a8e233c49aff390c3">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#a42669ba83291891a8e233c49aff390c3">EDMA3_DRV_Object</a>
+</li>
 <li>gblerrCb
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#416b12b38ea85487ca86df5d83754cc2">EDMA3_DRV_InitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a416b12b38ea85487ca86df5d83754cc2">EDMA3_DRV_InitConfig</a>
+</li>
 <li>gblerrCbParams
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#8db1897e81a58f66102840e992056e16">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a8db1897e81a58f66102840e992056e16">EDMA3_DRV_Instance</a>
+</li>
 <li>gblerrData
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#dac2401cfe0a00f0d517aaf54df6d489">EDMA3_DRV_InitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#adac2401cfe0a00f0d517aaf54df6d489">EDMA3_DRV_InitConfig</a>
+</li>
 <li>globalRegs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#5efff8708e94a49f71b055578549c97a">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a5efff8708e94a49f71b055578549c97a">EDMA3_DRV_GblConfigParams</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_i">- i -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_i">- i -</a></h3><ul>
 <li>isMaster
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a03b188471e9dc09af09a3b9096f7712">EDMA3_DRV_InitConfig</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#5e27d856f44f731c3182c1a854a7acb6">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#aa03b188471e9dc09af09a3b9096f7712">EDMA3_DRV_InitConfig</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a5e27d856f44f731c3182c1a854a7acb6">EDMA3_DRV_Instance</a>
+</li>
 <li>isSlave
-: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#812d8f331ad701c3927e28ce4c86d8c0">EDMA3_DRV_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a812d8f331ad701c3927e28ce4c86d8c0">EDMA3_DRV_MiscParam</a>
+</li>
 <li>itcchEn
-: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#dcd7e3719abfabb3dd1778835002c7c8">EDMA3_DRV_ChainOptions</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#adcd7e3719abfabb3dd1778835002c7c8">EDMA3_DRV_ChainOptions</a>
+</li>
 <li>itcintEn
-: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#4e5e184a2190f0cbd6fb8a70d86e3b43">EDMA3_DRV_ChainOptions</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#a4e5e184a2190f0cbd6fb8a70d86e3b43">EDMA3_DRV_ChainOptions</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_l">- l -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_l">- l -</a></h3><ul>
 <li>LINK_BCNTRLD
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#cda2db23599012f467bf51f22a01af9e">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#acda2db23599012f467bf51f22a01af9e">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>linkAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#9a90c589c5d20e363b8cd9a64732009e">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a9a90c589c5d20e363b8cd9a64732009e">EDMA3_DRV_PaRAMRegs</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_m">- m -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_m">- m -</a></h3><ul>
+<li>mapXbarToChan
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afac1f63dcd293985df3777abab3b2f9a">EDMA3_DRV_Instance</a>
+</li>
 <li>memProtectionExists
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#fd883a70d5f8bb868e65a69aa44d0f8e">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#afd883a70d5f8bb868e65a69aa44d0f8e">EDMA3_DRV_GblConfigParams</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_n">- n -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_n">- n -</a></h3><ul>
 <li>numDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#1d71e6ded1e1b3d3b14b20a11f896ce3">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1d71e6ded1e1b3d3b14b20a11f896ce3">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numEvtQueue
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#d27e2c83868656fa72ee70a64ac3a534">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ad27e2c83868656fa72ee70a64ac3a534">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numOpens
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#a02b8fca5781ab737d267b0b46598b80">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#aa02b8fca5781ab737d267b0b46598b80">EDMA3_DRV_Object</a>
+</li>
 <li>numPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#9bf9fc29152fe9ddb63bc86683149fc9">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9bf9fc29152fe9ddb63bc86683149fc9">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#629d5fc8d59adc8644f5f7a2691b8230">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a629d5fc8d59adc8644f5f7a2691b8230">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numRegions
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#30316db491c3d5f08182dc5bdde92463">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a30316db491c3d5f08182dc5bdde92463">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#14c6249081e4225ea140904758377c53">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a14c6249081e4225ea140904758377c53">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>numTcs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#8285aab9b38d6369896777f08cb8febd">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a8285aab9b38d6369896777f08cb8febd">EDMA3_DRV_GblConfigParams</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_o">- o -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_o">- o -</a></h3><ul>
 <li>OPT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#96fe729021c036ee4a39d58a3c6400e8">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a96fe729021c036ee4a39d58a3c6400e8">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>opt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#32d762dd945673da57fc34f633d078a0">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a32d762dd945673da57fc34f633d078a0">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>ownDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a718b355bf902648c421aef695836fa4">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#aa718b355bf902648c421aef695836fa4">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>ownPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#b14f2d879a9d96a3eb41756e134706c8">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ab14f2d879a9d96a3eb41756e134706c8">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>ownQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#38f397851f049cdebe32340cd2c651c0">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a38f397851f049cdebe32340cd2c651c0">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>ownTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#d90d5a8af55128a3157afb45a4f68d56">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad90d5a8af55128a3157afb45a4f68d56">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_p">- p -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_p">- p -</a></h3><ul>
 <li>param
-: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#9359f6ade97d2f3d910097fafd73da0a">EDMA3_DRV_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a9359f6ade97d2f3d910097fafd73da0a">EDMA3_DRV_MiscParam</a>
+</li>
 <li>paRAMId
-: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#7e7e0d656a59da04f54465a45e078a03">EDMA3_DRV_ChBoundResources</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#a7e7e0d656a59da04f54465a45e078a03">EDMA3_DRV_ChBoundResources</a>
+</li>
 <li>pDrvObjectHandle
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#cc5b518c2a22a43289ca39438133a30b">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#acc5b518c2a22a43289ca39438133a30b">EDMA3_DRV_Instance</a>
+</li>
 <li>phyCtrllerInstId
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#e0923a080e0da9d1b23cd9cf655775aa">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#ae0923a080e0da9d1b23cd9cf655775aa">EDMA3_DRV_Object</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_r">- r -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_r">- r -</a></h3><ul>
 <li>regionId
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#203b65f7e1176d9c5a7736411ba97df8">EDMA3_DRV_InitConfig</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#1eb007f153b58999588f5649ecd2143f">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a203b65f7e1176d9c5a7736411ba97df8">EDMA3_DRV_InitConfig</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a1eb007f153b58999588f5649ecd2143f">EDMA3_DRV_Instance</a>
+</li>
 <li>reserved
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#6285ab933f20d29b5d6892b895582e24">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a6285ab933f20d29b5d6892b895582e24">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>resMgrInstance
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#fc40e1cb787bbdae7afee7c6ea14109e">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afc40e1cb787bbdae7afee7c6ea14109e">EDMA3_DRV_Instance</a>
+</li>
 <li>resvdDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#30630e869042596c4ed487a09bea35c3">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a30630e869042596c4ed487a09bea35c3">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>resvdPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#81d8b8d85f09f042658db196e208794b">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a81d8b8d85f09f042658db196e208794b">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>resvdQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#d6707e2582dc13b7ea4d3a854834406e">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad6707e2582dc13b7ea4d3a854834406e">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 <li>resvdTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#175d4b970b6bf34c05700f4105bae5a6">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a175d4b970b6bf34c05700f4105bae5a6">EDMA3_DRV_InstanceInitConfig</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_s">- s -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_s">- s -</a></h3><ul>
 <li>shadowRegs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#d92603735455f8173b6e65467b78694a">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ad92603735455f8173b6e65467b78694a">EDMA3_DRV_Instance</a>
+</li>
 <li>SRC
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#6db0f14547c0586bffb62194ffffaf75">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a6db0f14547c0586bffb62194ffffaf75">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>SRC_DST_BIDX
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#ba20f4c8db04e562e01c6791cfebf258">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aba20f4c8db04e562e01c6791cfebf258">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>SRC_DST_CIDX
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#65b8a533cf4f336b920341d35b9a10ad">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a65b8a533cf4f336b920341d35b9a10ad">EDMA3_DRV_ParamentryRegs</a>
+</li>
 <li>srcAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#8ac1ab47f33fd6834ed4b378a33faf13">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a8ac1ab47f33fd6834ed4b378a33faf13">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>srcBIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#47d95d95fa2d572116180de42eae6d33">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a47d95d95fa2d572116180de42eae6d33">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>srcCIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#cceb3dbc415f63ee4974c9f3a11a11c6">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#acceb3dbc415f63ee4974c9f3a11a11c6">EDMA3_DRV_PaRAMRegs</a>
+</li>
 <li>state
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#dfc26946970b87cc67579ec54c73a221">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#adfc26946970b87cc67579ec54c73a221">EDMA3_DRV_Object</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_t">- t -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_t">- t -</a></h3><ul>
 <li>tcc
-: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#e9afabd97444eada59c7a74a62a5e20d">EDMA3_DRV_ChBoundResources</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ae9afabd97444eada59c7a74a62a5e20d">EDMA3_DRV_ChBoundResources</a>
+</li>
 <li>tcchEn
-: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#ceecc5cf449e9e5ec46f0ed1854af6e7">EDMA3_DRV_ChainOptions</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#aceecc5cf449e9e5ec46f0ed1854af6e7">EDMA3_DRV_ChainOptions</a>
+</li>
 <li>tcDefaultBurstSize
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a217c4ed918c9d5d695ee19ced91ef00">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aa217c4ed918c9d5d695ee19ced91ef00">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>tcError
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#3fdbb69b709ecd01dc903ec47e59f5a8">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a3fdbb69b709ecd01dc903ec47e59f5a8">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>tcintEn
-: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#6d0d65081b0538bed2734adc7c904d61">EDMA3_DRV_ChainOptions</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#a6d0d65081b0538bed2734adc7c904d61">EDMA3_DRV_ChainOptions</a>
+</li>
 <li>tcRegs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#31847b941f3a290ef68992ea3683228f">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a31847b941f3a290ef68992ea3683228f">EDMA3_DRV_GblConfigParams</a>
+</li>
 <li>trigMode
-: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#37ce2e0c452db7c087997ed2d4003c8b">EDMA3_DRV_ChBoundResources</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#a37ce2e0c452db7c087997ed2d4003c8b">EDMA3_DRV_ChBoundResources</a>
+</li>
 </ul>
-<h3><a class="anchor" name="index_x">- x -</a></h3><ul>
+
+
+<h3><a class="anchor" id="index_x">- x -</a></h3><ul>
 <li>xferCompleteInt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#08b4ad4be6b0cd9c6dd046dfe4f68c1e">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a08b4ad4be6b0cd9c6dd046dfe4f68c1e">EDMA3_DRV_GblConfigParams</a>
+</li>
 </ul>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:42 2010 for EDMA3 Driver by&nbsp;
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index 7872126b715a1548b36af3d3535731de3305ce22..b720044cdafdf62740ab738197a3b9174637e46a 100755 (executable)
@@ -1,38 +1,38 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: EDMA3 Driver</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
 </div>
 <div class="contents">
 <h1>EDMA3 Driver</h1><table border="0" cellpadding="0" cellspacing="0">
-<tr><td></td></tr>
-<tr><td colspan="2"><br><h2>Modules</h2></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l.html">EDMA3 Driver Symbols</a></td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___d_a_t_a_s_t_r_u_c_t.html">EDMA3 Driver Data Structures</a></td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html">EDMA3 Driver APIs</a></td></tr>
-
+<tr><td colspan="2"><h2>Modules</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l.html">EDMA3 Driver Symbols</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___d_a_t_a_s_t_r_u_c_t.html">EDMA3 Driver Data Structures</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html">EDMA3 Driver APIs</a></td></tr>
 </table>
-<hr><a name="_details"></a><h2>Detailed Description</h2>
-<h2><a class="anchor" name="Introduction">
+<hr/><a name="_details"></a><h2>Detailed Description</h2>
+<h2><a class="anchor" id="Introduction">
 Introduction</a></h2>
-<h3><a class="anchor" name="xxx">
+<h3><a class="anchor" id="xxx">
 Overview</a></h3>
-EDMA3 Driver is a functional library providing APIs for programming, scheduling and synchronizing with EDMA transfers and many more. </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:41 2010 for EDMA3 Driver by&nbsp;
+<p>EDMA3 Driver is a functional library providing APIs for programming, scheduling and synchronizing with EDMA transfers and many more. </p>
+</div>
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index 3b9a281b9b66ec647c32c6a80f1affff97b18c3d..b7b2f656adaf668777fe5c13124dcb130037c788 100755 (executable)
@@ -1,54 +1,48 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: EDMA3 Driver Data Structures</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
 </div>
 <div class="contents">
-<h1>EDMA3 Driver Data Structures<br>
+<h1>EDMA3 Driver Data Structures<br/>
 <small>
 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___a_p_i.html">EDMA3 Driver</a>]</small>
 </h1><table border="0" cellpadding="0" cellspacing="0">
-<tr><td></td></tr>
-<tr><td colspan="2"><br><h2>Data Structures</h2></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a></td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.  <a href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#_details">More...</a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html">EDMA3_DRV_InstanceInitConfig</a></td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information.  <a href="struct_e_d_m_a3___d_r_v___instance_init_config.html#_details">More...</a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html">EDMA3_DRV_InitConfig</a></td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Used to Initialize the EDMA3 Driver Instance.  <a href="struct_e_d_m_a3___d_r_v___init_config.html#_details">More...</a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html">EDMA3_DRV_MiscParam</a></td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Used to specify the miscellaneous options during EDMA3 Driver Initialization.  <a href="struct_e_d_m_a3___d_r_v___misc_param.html#_details">More...</a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a></td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Structure to be used to configure interrupt generation and chaining options.  <a href="struct_e_d_m_a3___d_r_v___chain_options.html#_details">More...</a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html">EDMA3_DRV_ParamentryRegs</a></td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 PaRAM Set.  <a href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#_details">More...</a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a></td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 Parameter RAM Set in User Configurable format.  <a href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#_details">More...</a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a></td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Event queue priorities setup.  <a href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#_details">More...</a><br></td></tr>
+<tr><td colspan="2"><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a></td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.  <a href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#_details">More...</a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html">EDMA3_DRV_InstanceInitConfig</a></td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information.  <a href="struct_e_d_m_a3___d_r_v___instance_init_config.html#_details">More...</a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html">EDMA3_DRV_InitConfig</a></td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Used to Initialize the EDMA3 Driver Instance.  <a href="struct_e_d_m_a3___d_r_v___init_config.html#_details">More...</a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html">EDMA3_DRV_MiscParam</a></td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Used to specify the miscellaneous options during EDMA3 Driver Initialization.  <a href="struct_e_d_m_a3___d_r_v___misc_param.html#_details">More...</a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a></td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Structure to be used to configure interrupt generation and chaining options.  <a href="struct_e_d_m_a3___d_r_v___chain_options.html#_details">More...</a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html">EDMA3_DRV_ParamentryRegs</a></td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 PaRAM Set.  <a href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#_details">More...</a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a></td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 Parameter RAM Set in User Configurable format.  <a href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#_details">More...</a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a></td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Event queue priorities setup.  <a href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#_details">More...</a><br/></td></tr>
 </table>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:41 2010 for EDMA3 Driver by&nbsp;
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index adceeadf42093fb1bde5006f7f6a510a8cc9dc4c..b628cf6e4386130002e9651828635b28a5eba8a4 100755 (executable)
@@ -1,36 +1,35 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: EDMA3 Driver APIs</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
 </div>
 <div class="contents">
-<h1>EDMA3 Driver APIs<br>
+<h1>EDMA3 Driver APIs<br/>
 <small>
 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___a_p_i.html">EDMA3 Driver</a>]</small>
 </h1><table border="0" cellpadding="0" cellspacing="0">
-<tr><td></td></tr>
-<tr><td colspan="2"><br><h2>Modules</h2></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html">EDMA3 Driver Initialization APIs</a></td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html">EDMA3 Driver Basic APIs</a></td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html">EDMA3 Driver Advanced APIs</a></td></tr>
-
+<tr><td colspan="2"><h2>Modules</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html">EDMA3 Driver Initialization APIs</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html">EDMA3 Driver Basic APIs</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html">EDMA3 Driver Advanced APIs</a></td></tr>
 </table>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:41 2010 for EDMA3 Driver by&nbsp;
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index c0530c07ddb2fcbb3dc4b46f880888b5946beffa..27db22109ade8a14d4ce52601c73524367fa1c7d 100755 (executable)
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: EDMA3 Driver Advanced APIs</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
 </div>
 <div class="contents">
-<h1>EDMA3 Driver Advanced APIs<br>
+<h1>EDMA3 Driver Advanced APIs<br/>
 <small>
 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html">EDMA3 Driver APIs</a>]</small>
 </h1><table border="0" cellpadding="0" cellspacing="0">
-<tr><td></td></tr>
-<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga8561ee446bd1b9d0c5c4b106c9f40a9">EDMA3_DRV_linkChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Link two logical channels.  <a href="#ga8561ee446bd1b9d0c5c4b106c9f40a9"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gca6ef38f26d8e043352fa8963b7f090a">EDMA3_DRV_unlinkChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Unlink the channel from the earlier linked logical channel.  <a href="#gca6ef38f26d8e043352fa8963b7f090a"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gb8e524124e4aaa158fcaf494798def5e">EDMA3_DRV_chainChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a> *chainOptions)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Chain the two specified channels.  <a href="#gb8e524124e4aaa158fcaf494798def5e"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gd6424fda12e9b6cccae47ccb22207bcf">EDMA3_DRV_unchainChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Unchain the two channels.  <a href="#gd6424fda12e9b6cccae47ccb22207bcf"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g669ea0f2097604af17b9213a28985191">EDMA3_DRV_setQdmaTrigWord</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Assign a Trigger Word to the specified QDMA channel.  <a href="#g669ea0f2097604af17b9213a28985191"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g77841fc83e3876a3014963404cfc08ba">EDMA3_DRV_setPaRAM</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, const <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> *newPaRAM)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).  <a href="#g77841fc83e3876a3014963404cfc08ba"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g437d851ec0eb6c05bb118886ee5c17f2">EDMA3_DRV_getPaRAM</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> *currPaRAM)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).  <a href="#g437d851ec0eb6c05bb118886ee5c17f2"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g83bcb5bc4e319fd6e78466ab5df5c0ac">EDMA3_DRV_setPaRAMEntry</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> paRAMEntry, unsigned int newPaRAMEntryVal)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set a particular PaRAM set entry of the specified PaRAM set.  <a href="#g83bcb5bc4e319fd6e78466ab5df5c0ac"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g443b63758caa5383ef0f9f66b29fb5e8">EDMA3_DRV_getPaRAMEntry</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> paRAMEntry, unsigned int *paRAMEntryVal)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get a particular PaRAM set entry of the specified PaRAM set.  <a href="#g443b63758caa5383ef0f9f66b29fb5e8"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g41151895e480b66bf320ec662506f078">EDMA3_DRV_setPaRAMField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> paRAMField, unsigned int newPaRAMFieldVal)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set a particular PaRAM set field of the specified PaRAM set.  <a href="#g41151895e480b66bf320ec662506f078"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g1254ca24861fd4b580010f118f093b51">EDMA3_DRV_getPaRAMField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> paRAMField, unsigned int *currPaRAMFieldVal)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get a particular PaRAM set field of the specified PaRAM set.  <a href="#g1254ca24861fd4b580010f118f093b51"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g6a6c40cddb7bb7bc74635e104757e225">EDMA3_DRV_setEvtQPriority</a> (EDMA3_DRV_Handle hEdma, const <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a> *evtQPriObj)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Sets EDMA TC priority.  <a href="#g6a6c40cddb7bb7bc74635e104757e225"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g4419ae8ba6468ec35090e2717a28f958">EDMA3_DRV_mapChToEvtQ</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Associate Channel to Event Queue.  <a href="#g4419ae8ba6468ec35090e2717a28f958"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gb2058b44b471c44d001035e1a38fd06d">EDMA3_DRV_getMapChToEvtQ</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the Event Queue mapped to the specified DMA/QDMA channel.  <a href="#gb2058b44b471c44d001035e1a38fd06d"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g2574c3da30322981b763e54dd1ea7fb2">EDMA3_DRV_setCCRegister</a> (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set the Channel Controller (CC) Register value.  <a href="#g2574c3da30322981b763e54dd1ea7fb2"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g297f964f8fa3df44683e1bdedd56d928">EDMA3_DRV_getCCRegister</a> (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the Channel Controller (CC) Register value.  <a href="#g297f964f8fa3df44683e1bdedd56d928"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga73fe4d0c29760be55306a8fc1f35161">EDMA3_DRV_waitAndClearTcc</a> (EDMA3_DRV_Handle hEdma, unsigned int tccNo)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Wait for a transfer completion interrupt to occur and clear it.  <a href="#ga73fe4d0c29760be55306a8fc1f35161"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g3c098a85435e55a8eff2561cbcd79a77">EDMA3_DRV_checkAndClearTcc</a> (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns the status of a previously initiated transfer.  <a href="#g3c098a85435e55a8eff2561cbcd79a77"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gfeb7b2a17615b14bdac9b11af69e5142">EDMA3_DRV_getPaRAMPhyAddr</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the PaRAM Set Physical Address associated with a logical channel.  <a href="#gfeb7b2a17615b14bdac9b11af69e5142"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g379162d6a5076160d4ed2e01ca8dcac6">EDMA3_DRV_Ioctl</a> (EDMA3_DRV_Handle hEdma, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g8577940463f7ca5a8977b2fb65fae19a">EDMA3_DRV_IoctlCmd</a> cmd, void *cmdArg, void *param)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 Driver IOCTL.  <a href="#g379162d6a5076160d4ed2e01ca8dcac6"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Handle&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g866c17eaf78a3e0ddc83a397b91fe850">EDMA3_DRV_getInstHandle</a> (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Return the previously opened EDMA3 Driver Instance handle.  <a href="#g866c17eaf78a3e0ddc83a397b91fe850"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g43031c6c66af92677c388c156b50480b">EDMA3_DRV_registerTccCb</a> (EDMA3_DRV_Handle hEdma, const unsigned int channelId, EDMA3_RM_TccCallback tccCb, void *cbData)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Registers a transfer completion handler for a specific DMA/QDMA channel.  <a href="#g43031c6c66af92677c388c156b50480b"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga4ab2ce058e4e40a812b8a20970d4088">EDMA3_DRV_unregisterTccCb</a> (EDMA3_DRV_Handle hEdma, const unsigned int channelId)</td></tr>
+<tr><td colspan="2"><h2>Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a></td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.  <a href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#_details">More...</a><br/></td></tr>
+<tr><td colspan="2"><h2>Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_DRV_Result(*&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a> )(unsigned int eventNum, unsigned int *chanNum, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Associates cross bar mapped event to channel.  <a href="#gae7867a62f61919df85b323ce981163e4"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_DRV_Result(*&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a> )(unsigned int eventNum, unsigned int chanNum)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Writes to the cross bar mapped event to channel to system configuration register.  <a href="#ga02168cc5612b65b34812ce52df7154a3"></a><br/></td></tr>
+<tr><td colspan="2"><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa8561ee446bd1b9d0c5c4b106c9f40a9">EDMA3_DRV_linkChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Link two logical channels.  <a href="#gaa8561ee446bd1b9d0c5c4b106c9f40a9"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaca6ef38f26d8e043352fa8963b7f090a">EDMA3_DRV_unlinkChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Unlink the channel from the earlier linked logical channel.  <a href="#gaca6ef38f26d8e043352fa8963b7f090a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gab8e524124e4aaa158fcaf494798def5e">EDMA3_DRV_chainChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a> *chainOptions)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Chain the two specified channels.  <a href="#gab8e524124e4aaa158fcaf494798def5e"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gad6424fda12e9b6cccae47ccb22207bcf">EDMA3_DRV_unchainChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Unchain the two channels.  <a href="#gad6424fda12e9b6cccae47ccb22207bcf"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga669ea0f2097604af17b9213a28985191">EDMA3_DRV_setQdmaTrigWord</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Assign a Trigger Word to the specified QDMA channel.  <a href="#ga669ea0f2097604af17b9213a28985191"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga77841fc83e3876a3014963404cfc08ba">EDMA3_DRV_setPaRAM</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, const <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> *newPaRAM)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).  <a href="#ga77841fc83e3876a3014963404cfc08ba"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga437d851ec0eb6c05bb118886ee5c17f2">EDMA3_DRV_getPaRAM</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> *currPaRAM)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).  <a href="#ga437d851ec0eb6c05bb118886ee5c17f2"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga83bcb5bc4e319fd6e78466ab5df5c0ac">EDMA3_DRV_setPaRAMEntry</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> paRAMEntry, unsigned int newPaRAMEntryVal)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set a particular PaRAM set entry of the specified PaRAM set.  <a href="#ga83bcb5bc4e319fd6e78466ab5df5c0ac"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga443b63758caa5383ef0f9f66b29fb5e8">EDMA3_DRV_getPaRAMEntry</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> paRAMEntry, unsigned int *paRAMEntryVal)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get a particular PaRAM set entry of the specified PaRAM set.  <a href="#ga443b63758caa5383ef0f9f66b29fb5e8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga41151895e480b66bf320ec662506f078">EDMA3_DRV_setPaRAMField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> paRAMField, unsigned int newPaRAMFieldVal)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set a particular PaRAM set field of the specified PaRAM set.  <a href="#ga41151895e480b66bf320ec662506f078"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1254ca24861fd4b580010f118f093b51">EDMA3_DRV_getPaRAMField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> paRAMField, unsigned int *currPaRAMFieldVal)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get a particular PaRAM set field of the specified PaRAM set.  <a href="#ga1254ca24861fd4b580010f118f093b51"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga6a6c40cddb7bb7bc74635e104757e225">EDMA3_DRV_setEvtQPriority</a> (EDMA3_DRV_Handle hEdma, const <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a> *evtQPriObj)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Sets EDMA TC priority.  <a href="#ga6a6c40cddb7bb7bc74635e104757e225"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga4419ae8ba6468ec35090e2717a28f958">EDMA3_DRV_mapChToEvtQ</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Associate Channel to Event Queue.  <a href="#ga4419ae8ba6468ec35090e2717a28f958"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gab2058b44b471c44d001035e1a38fd06d">EDMA3_DRV_getMapChToEvtQ</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the Event Queue mapped to the specified DMA/QDMA channel.  <a href="#gab2058b44b471c44d001035e1a38fd06d"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga2574c3da30322981b763e54dd1ea7fb2">EDMA3_DRV_setCCRegister</a> (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set the Channel Controller (CC) Register value.  <a href="#ga2574c3da30322981b763e54dd1ea7fb2"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga297f964f8fa3df44683e1bdedd56d928">EDMA3_DRV_getCCRegister</a> (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the Channel Controller (CC) Register value.  <a href="#ga297f964f8fa3df44683e1bdedd56d928"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa73fe4d0c29760be55306a8fc1f35161">EDMA3_DRV_waitAndClearTcc</a> (EDMA3_DRV_Handle hEdma, unsigned int tccNo)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Wait for a transfer completion interrupt to occur and clear it.  <a href="#gaa73fe4d0c29760be55306a8fc1f35161"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga3c098a85435e55a8eff2561cbcd79a77">EDMA3_DRV_checkAndClearTcc</a> (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Returns the status of a previously initiated transfer.  <a href="#ga3c098a85435e55a8eff2561cbcd79a77"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gafeb7b2a17615b14bdac9b11af69e5142">EDMA3_DRV_getPaRAMPhyAddr</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the PaRAM Set Physical Address associated with a logical channel.  <a href="#gafeb7b2a17615b14bdac9b11af69e5142"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga379162d6a5076160d4ed2e01ca8dcac6">EDMA3_DRV_Ioctl</a> (EDMA3_DRV_Handle hEdma, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8577940463f7ca5a8977b2fb65fae19a">EDMA3_DRV_IoctlCmd</a> cmd, void *cmdArg, void *param)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 Driver IOCTL.  <a href="#ga379162d6a5076160d4ed2e01ca8dcac6"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Handle&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga866c17eaf78a3e0ddc83a397b91fe850">EDMA3_DRV_getInstHandle</a> (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Return the previously opened EDMA3 Driver Instance handle.  <a href="#ga866c17eaf78a3e0ddc83a397b91fe850"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga43031c6c66af92677c388c156b50480b">EDMA3_DRV_registerTccCb</a> (EDMA3_DRV_Handle hEdma, const unsigned int channelId, EDMA3_RM_TccCallback tccCb, void *cbData)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Registers a transfer completion handler for a specific DMA/QDMA channel.  <a href="#ga43031c6c66af92677c388c156b50480b"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa4ab2ce058e4e40a812b8a20970d4088">EDMA3_DRV_unregisterTccCb</a> (EDMA3_DRV_Handle hEdma, const unsigned int channelId)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Un-register the previously registered callback function against a DMA/QDMA channel.  <a href="#gaa4ab2ce058e4e40a812b8a20970d4088"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga276f4ecd7f1e59f09ad065b633643ae4">EDMA3_DRV_setTcErrorInt</a> (unsigned int phyCtrllerInstId, unsigned int tcId, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga2b3b55b1d7c987a7873d8b0b085173b2">EDMA3_DRV_Tc_Err</a> tcErr)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enable/disable specific EDMA3 Transfer Controller Interrupts.  <a href="#ga276f4ecd7f1e59f09ad065b633643ae4"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga85bad51ec992ce36ed7f28842b7d8219">EDMA3_DRV_getChannelStatus</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *lchStatus)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the current status of the DMA/QDMA channel.  <a href="#ga85bad51ec992ce36ed7f28842b7d8219"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaba9535a00375255494df382382b834de">EDMA3_DRV_mapTccLinkCh</a> (EDMA3_DRV_Handle hEdma, unsigned int linkCh, unsigned int tcc)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Associates a link channel and a TCC.  <a href="#gaba9535a00375255494df382382b834de"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1ff9d2ede0fb29c7194f15ba58ad8e0f">EDMA3_DRV_initXbarEventMap</a> (EDMA3_DRV_Handle hEdma, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a> mapXbarEvtFunc, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a> configXbarScr)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Initialize the cross bar mapped event to channel function.  <a href="#ga1ff9d2ede0fb29c7194f15ba58ad8e0f"></a><br/></td></tr>
+</table>
+<hr/><h2>Typedef Documentation</h2>
+<a class="anchor" id="gae7867a62f61919df85b323ce981163e4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapXbarEvtToChan" ref="gae7867a62f61919df85b323ce981163e4" args=")(unsigned int eventNum, unsigned int *chanNum, const EDMA3_DRV_GblXbarToChanConfigParams *edmaGblXbarConfig)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef EDMA3_DRV_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a>)(unsigned int eventNum, unsigned int *chanNum, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
 
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Un-register the previously registered callback function against a DMA/QDMA channel.  <a href="#ga4ab2ce058e4e40a812b8a20970d4088"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g276f4ecd7f1e59f09ad065b633643ae4">EDMA3_DRV_setTcErrorInt</a> (unsigned int phyCtrllerInstId, unsigned int tcId, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g2b3b55b1d7c987a7873d8b0b085173b2">EDMA3_DRV_Tc_Err</a> tcErr)</td></tr>
+<p>Associates cross bar mapped event to channel. </p>
+<p>This function have to be defined in the configuration file. This function will be called only if the channel requested for is beyond the maximum number of channels. This function should read from the global cross bar mapped configuration data structure and return the mapped channel number to this event.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>eventNum</em>&nbsp;</td><td>[IN] Event number </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>chanNum</em>&nbsp;</td><td>[IN/OUT]Return the channel number to which the request event is mapped to. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>edmaGblXbarConfig</em>&nbsp;</td><td>[IN] This is the configuration data structure for mapping the events to the channel</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique event values. It is non-re-entrant for same event values. </dd></dl>
 
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Enable/disable specific EDMA3 Transfer Controller Interrupts.  <a href="#g276f4ecd7f1e59f09ad065b633643ae4"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g85bad51ec992ce36ed7f28842b7d8219">EDMA3_DRV_getChannelStatus</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *lchStatus)</td></tr>
+</div>
+</div>
+<a class="anchor" id="ga02168cc5612b65b34812ce52df7154a3"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_xbarConfigScr" ref="ga02168cc5612b65b34812ce52df7154a3" args=")(unsigned int eventNum, unsigned int chanNum)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">typedef EDMA3_DRV_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a>)(unsigned int eventNum, unsigned int chanNum)</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
 
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get the current status of the DMA/QDMA channel.  <a href="#g85bad51ec992ce36ed7f28842b7d8219"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gba9535a00375255494df382382b834de">EDMA3_DRV_mapTccLinkCh</a> (EDMA3_DRV_Handle hEdma, unsigned int linkCh, unsigned int tcc)</td></tr>
+<p>Writes to the cross bar mapped event to channel to system configuration register. </p>
+<p>This function have to be defined in the configuration file. This function will be called only if the event number requested for is beyond the maximum number of channels and if any channel is allocated to this event. This function should read the cross bar mapped event number and write the allocated channel number in Control Config Event Mux registers.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>eventNum</em>&nbsp;</td><td>[IN] Event number </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>chanNum</em>&nbsp;</td><td>[IN/OUT]Return the channel number to which the request event is mapped to.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique event values. It is non-re-entrant for same event values. </dd></dl>
 
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Associates a link channel and a TCC.  <a href="#gba9535a00375255494df382382b834de"></a><br></td></tr>
-</table>
-<hr><h2>Function Documentation</h2>
-<a class="anchor" name="ga8561ee446bd1b9d0c5c4b106c9f40a9"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_linkChannel" ref="ga8561ee446bd1b9d0c5c4b106c9f40a9" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)" -->
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="gaa8561ee446bd1b9d0c5c4b106c9f40a9"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_linkChannel" ref="gaa8561ee446bd1b9d0c5c4b106c9f40a9" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_linkChannel           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_linkChannel </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Link two logical channels. 
-<p>
-This API is used to link two previously allocated logical (DMA/QDMA/Link) channels.<p>
-It sets the Link field of the PaRAM set associated with first logical channel (lCh1) to point it to the PaRAM set associated with second logical channel (lCh2).<p>
-It also sets the TCC field of PaRAM set of second logical channel to the same as that of the first logical channel, only if the TCC field doesnot contain a valid TCC code. In case the second logical channel has its own TCC, the TCC field remains unchanged.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Link two logical channels. </p>
+<p>This API is used to link two previously allocated logical (DMA/QDMA/Link) channels.</p>
+<p>It sets the Link field of the PaRAM set associated with first logical channel (lCh1) to point it to the PaRAM set associated with second logical channel (lCh2).</p>
+<p>It also sets the TCC field of PaRAM set of second logical channel to the same as that of the first logical channel, only if the TCC field doesnot contain a valid TCC code. In case the second logical channel has its own TCC, the TCC field remains unchanged.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh1</em>&nbsp;</td><td>[IN] Logical Channel to which particular channel will be linked. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh2</em>&nbsp;</td><td>[IN] Logical Channel which needs to be linked to the first channel. After the transfer based on the PaRAM set of lCh1 is over, the PaRAM set of lCh2 will be copied to the PaRAM set of lCh1 and transfer will resume. For DMA channels, another sync event is required to initiate the transfer on the Link channel.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh1 &amp; lCh2 values. It is non-re-entrant for same lCh1 &amp; lCh2 values. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh1 &amp; lCh2 values. It is non-re-entrant for same lCh1 &amp; lCh2 values. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="gca6ef38f26d8e043352fa8963b7f090a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unlinkChannel" ref="gca6ef38f26d8e043352fa8963b7f090a" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh)" -->
+</div>
+<a class="anchor" id="gaca6ef38f26d8e043352fa8963b7f090a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unlinkChannel" ref="gaca6ef38f26d8e043352fa8963b7f090a" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_unlinkChannel           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_unlinkChannel </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -169,33 +206,32 @@ It also sets the TCC field of PaRAM set of second logical channel to the same as
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Unlink the channel from the earlier linked logical channel. 
-<p>
-This function breaks the link between the specified channel and the earlier linked logical channel by clearing the Link Address field.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Unlink the channel from the earlier linked logical channel. </p>
+<p>This function breaks the link between the specified channel and the earlier linked logical channel by clearing the Link Address field.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Channel for which linking has to be removed</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="gb8e524124e4aaa158fcaf494798def5e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_chainChannel" ref="gb8e524124e4aaa158fcaf494798def5e" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const EDMA3_DRV_ChainOptions *chainOptions)" -->
+</div>
+<a class="anchor" id="gab8e524124e4aaa158fcaf494798def5e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_chainChannel" ref="gab8e524124e4aaa158fcaf494798def5e" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const EDMA3_DRV_ChainOptions *chainOptions)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_chainChannel           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_chainChannel </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -221,36 +257,35 @@ This function breaks the link between the specified channel and the earlier link
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Chain the two specified channels. 
-<p>
-This API is used to chain a DMA channel to a previously allocated DMA/QDMA channel.<p>
-Chaining is different from Linking. The EDMA3 link feature reloads the current channel parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any channel parameter set; it provides a synchronization event (or trigger) to the chained DMA channel, as soon as the transfer (final or intermediate) completes on the main DMA/QDMA channel.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Chain the two specified channels. </p>
+<p>This API is used to chain a DMA channel to a previously allocated DMA/QDMA channel.</p>
+<p>Chaining is different from Linking. The EDMA3 link feature reloads the current channel parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any channel parameter set; it provides a synchronization event (or trigger) to the chained DMA channel, as soon as the transfer (final or intermediate) completes on the main DMA/QDMA channel.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance.</td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh1</em>&nbsp;</td><td>[IN] DMA/QDMA channel to which a particular DMA channel will be chained. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh2</em>&nbsp;</td><td>[IN] DMA channel which needs to be chained to the first DMA/QDMA channel. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>chainOptions</em>&nbsp;</td><td>[IN] Options such as intermediate interrupts are required or not, intermediate/final chaining is enabled or not etc.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh1 &amp; lCh2 values. It is non-re-entrant for same lCh1 &amp; lCh2 values. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh1 &amp; lCh2 values. It is non-re-entrant for same lCh1 &amp; lCh2 values. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="gd6424fda12e9b6cccae47ccb22207bcf"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unchainChannel" ref="gd6424fda12e9b6cccae47ccb22207bcf" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh)" -->
+</div>
+<a class="anchor" id="gad6424fda12e9b6cccae47ccb22207bcf"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unchainChannel" ref="gad6424fda12e9b6cccae47ccb22207bcf" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_unchainChannel           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_unchainChannel </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -264,32 +299,31 @@ Chaining is different from Linking. The EDMA3 link feature reloads the current c
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Unchain the two channels. 
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Unchain the two channels. </p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Channel whose chaining with the other channel has to be removed.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g669ea0f2097604af17b9213a28985191"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setQdmaTrigWord" ref="g669ea0f2097604af17b9213a28985191" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)" -->
+</div>
+<a class="anchor" id="ga669ea0f2097604af17b9213a28985191"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setQdmaTrigWord" ref="ga669ea0f2097604af17b9213a28985191" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -309,34 +343,33 @@ Unchain the two channels.
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Assign a Trigger Word to the specified QDMA channel. 
-<p>
-This API sets the Trigger word for the specific QDMA channel in the QCHMAP Register. Default QDMA trigger word is CCNT.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Assign a Trigger Word to the specified QDMA channel. </p>
+<p>This API sets the Trigger word for the specific QDMA channel in the QCHMAP Register. Default QDMA trigger word is CCNT.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Instance object </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] QDMA Channel which needs to be assigned the Trigger Word </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>trigWord</em>&nbsp;</td><td>[IN] The Trigger Word for the QDMA channel. Trigger Word is the word in the PaRAM Register Set which, when written to by CPU, will start the QDMA transfer automatically.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g77841fc83e3876a3014963404cfc08ba"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAM" ref="g77841fc83e3876a3014963404cfc08ba" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)" -->
+</div>
+<a class="anchor" id="ga77841fc83e3876a3014963404cfc08ba"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAM" ref="ga77841fc83e3876a3014963404cfc08ba" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setPaRAM           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setPaRAM </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -356,35 +389,34 @@ This API sets the Trigger word for the specific QDMA channel in the QCHMAP Regis
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). 
-<p>
-This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last.<p>
-Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). </p>
+<p>This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last.</p>
+<p>Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Instance object </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel for which new PaRAM set is specified </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>newPaRAM</em>&nbsp;</td><td>[IN] Parameter RAM set to be copied onto existing PaRAM</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g437d851ec0eb6c05bb118886ee5c17f2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAM" ref="g437d851ec0eb6c05bb118886ee5c17f2" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)" -->
+</div>
+<a class="anchor" id="ga437d851ec0eb6c05bb118886ee5c17f2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAM" ref="ga437d851ec0eb6c05bb118886ee5c17f2" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAM           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAM </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -404,33 +436,32 @@ Caution: It should be used carefully when programming the QDMA channels whose tr
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). 
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). </p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Instance object </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel whose PaRAM set is requested </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>currPaRAM</em>&nbsp;</td><td>[IN/OUT] User gets the existing PaRAM here</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g83bcb5bc4e319fd6e78466ab5df5c0ac"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAMEntry" ref="g83bcb5bc4e319fd6e78466ab5df5c0ac" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int newPaRAMEntryVal)" -->
+</div>
+<a class="anchor" id="ga83bcb5bc4e319fd6e78466ab5df5c0ac"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAMEntry" ref="ga83bcb5bc4e319fd6e78466ab5df5c0ac" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int newPaRAMEntryVal)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -444,7 +475,7 @@ Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a>&nbsp;</td>
           <td class="paramname"> <em>paRAMEntry</em>, </td>
         </tr>
         <tr>
@@ -456,34 +487,34 @@ Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Set a particular PaRAM set entry of the specified PaRAM set. 
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Set a particular PaRAM set entry of the specified PaRAM set. </p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel bound to the Parameter RAM set whose specified field needs to be set </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>paRAMEntry</em>&nbsp;</td><td>[IN] Specify the PaRAM set entry which needs to be set </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>newPaRAMEntryVal</em>&nbsp;</td><td>[IN] The new field setting</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This API should be used while setting the PaRAM set entry for QDMA channels. If EDMA3_DRV_setPaRAMField () used, it will trigger the QDMA channel before complete PaRAM set entry is written. For DMA channels, no such constraint is there.</dd></dl>
-This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. 
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This API should be used while setting the PaRAM set entry for QDMA channels. If EDMA3_DRV_setPaRAMField () used, it will trigger the QDMA channel before complete PaRAM set entry is written. For DMA channels, no such constraint is there.</dd></dl>
+<p>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </p>
+
 </div>
-</div><p>
-<a class="anchor" name="g443b63758caa5383ef0f9f66b29fb5e8"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMEntry" ref="g443b63758caa5383ef0f9f66b29fb5e8" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int *paRAMEntryVal)" -->
+</div>
+<a class="anchor" id="ga443b63758caa5383ef0f9f66b29fb5e8"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMEntry" ref="ga443b63758caa5383ef0f9f66b29fb5e8" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int *paRAMEntryVal)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -497,7 +528,7 @@ This function is re-entrant for unique lCh values. It is non- re-entrant for sam
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a>&nbsp;</td>
           <td class="paramname"> <em>paRAMEntry</em>, </td>
         </tr>
         <tr>
@@ -509,34 +540,33 @@ This function is re-entrant for unique lCh values. It is non- re-entrant for sam
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Get a particular PaRAM set entry of the specified PaRAM set. 
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Get a particular PaRAM set entry of the specified PaRAM set. </p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel bound to the Parameter RAM set whose specified field value is needed </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>paRAMEntry</em>&nbsp;</td><td>[IN] Specify the PaRAM set entry which needs to be obtained </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>paRAMEntryVal</em>&nbsp;</td><td>[IN/OUT] The value of the field is returned here</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g41151895e480b66bf320ec662506f078"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAMField" ref="g41151895e480b66bf320ec662506f078" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int newPaRAMFieldVal)" -->
+</div>
+<a class="anchor" id="ga41151895e480b66bf320ec662506f078"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAMField" ref="ga41151895e480b66bf320ec662506f078" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int newPaRAMFieldVal)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setPaRAMField           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setPaRAMField </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -550,7 +580,7 @@ Get a particular PaRAM set entry of the specified PaRAM set.
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a>&nbsp;</td>
           <td class="paramname"> <em>paRAMField</em>, </td>
         </tr>
         <tr>
@@ -562,34 +592,34 @@ Get a particular PaRAM set entry of the specified PaRAM set.
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Set a particular PaRAM set field of the specified PaRAM set. 
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Set a particular PaRAM set field of the specified PaRAM set. </p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel bound to the PaRAM set whose specified field needs to be set </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>paRAMField</em>&nbsp;</td><td>[IN] Specify the PaRAM set field which needs to be set </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>newPaRAMFieldVal</em>&nbsp;</td><td>[IN] The new field setting</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This API CANNOT be used while setting the PaRAM set field for QDMA channels. It can trigger the QDMA channel before complete PaRAM set ENTRY (4-bytes field) is written (for eg, as soon one sets the ACNT field for QDMA channel, transfer is started, before one modifies the BCNT field). For DMA channels, no such constraint is there.</dd></dl>
-This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. 
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This API CANNOT be used while setting the PaRAM set field for QDMA channels. It can trigger the QDMA channel before complete PaRAM set ENTRY (4-bytes field) is written (for eg, as soon one sets the ACNT field for QDMA channel, transfer is started, before one modifies the BCNT field). For DMA channels, no such constraint is there.</dd></dl>
+<p>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </p>
+
+</div>
 </div>
-</div><p>
-<a class="anchor" name="g1254ca24861fd4b580010f118f093b51"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMField" ref="g1254ca24861fd4b580010f118f093b51" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int *currPaRAMFieldVal)" -->
+<a class="anchor" id="ga1254ca24861fd4b580010f118f093b51"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMField" ref="ga1254ca24861fd4b580010f118f093b51" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int *currPaRAMFieldVal)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAMField           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAMField </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -603,7 +633,7 @@ This function is re-entrant for unique lCh values. It is non- re-entrant for sam
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a>&nbsp;</td>
           <td class="paramname"> <em>paRAMField</em>, </td>
         </tr>
         <tr>
@@ -615,34 +645,33 @@ This function is re-entrant for unique lCh values. It is non- re-entrant for sam
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Get a particular PaRAM set field of the specified PaRAM set. 
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Get a particular PaRAM set field of the specified PaRAM set. </p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel bound to the PaRAM set whose specified field value is needed </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>paRAMField</em>&nbsp;</td><td>[IN] Specify the PaRAM set field which needs to be obtained </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>currPaRAMFieldVal</em>&nbsp;</td><td>[IN/OUT] The value of the field is returned here</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g6a6c40cddb7bb7bc74635e104757e225"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setEvtQPriority" ref="g6a6c40cddb7bb7bc74635e104757e225" args="(EDMA3_DRV_Handle hEdma, const EDMA3_DRV_EvtQuePriority *evtQPriObj)" -->
+</div>
+<a class="anchor" id="ga6a6c40cddb7bb7bc74635e104757e225"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setEvtQPriority" ref="ga6a6c40cddb7bb7bc74635e104757e225" args="(EDMA3_DRV_Handle hEdma, const EDMA3_DRV_EvtQuePriority *evtQPriObj)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -656,33 +685,32 @@ Get a particular PaRAM set field of the specified PaRAM set.
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Sets EDMA TC priority. 
-<p>
-User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Sets EDMA TC priority. </p>
+<p>User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>evtQPriObj</em>&nbsp;</td><td>[IN] Priority of the Event Queues</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g4419ae8ba6468ec35090e2717a28f958"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapChToEvtQ" ref="g4419ae8ba6468ec35090e2717a28f958" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)" -->
+</div>
+<a class="anchor" id="ga4419ae8ba6468ec35090e2717a28f958"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapChToEvtQ" ref="ga4419ae8ba6468ec35090e2717a28f958" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -702,33 +730,33 @@ User can program the priority of the Event Queues at a system-wide level. This m
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Associate Channel to Event Queue. 
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Associate Channel to Event Queue. </p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>channelId</em>&nbsp;</td><td>[IN] Logical Channel to which the Event Queue is to be mapped </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>eventQ</em>&nbsp;</td><td>[IN] The Event Queue which is to be mapped to the DMA channel</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>There should not be any data transfer going on while setting the mapping. Results could be unpredictable.</dd></dl>
-This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant. 
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>There should not be any data transfer going on while setting the mapping. Results could be unpredictable.</dd></dl>
+<p>This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant. </p>
+
+</div>
 </div>
-</div><p>
-<a class="anchor" name="gb2058b44b471c44d001035e1a38fd06d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getMapChToEvtQ" ref="gb2058b44b471c44d001035e1a38fd06d" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)" -->
+<a class="anchor" id="gab2058b44b471c44d001035e1a38fd06d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getMapChToEvtQ" ref="gab2058b44b471c44d001035e1a38fd06d" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -748,33 +776,32 @@ This function disables the global interrupts while modifying the global CC Regis
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Get the Event Queue mapped to the specified DMA/QDMA channel. 
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Get the Event Queue mapped to the specified DMA/QDMA channel. </p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>channelId</em>&nbsp;</td><td>[IN] Logical Channel whose associated Event Queue is needed </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>mappedEvtQ</em>&nbsp;</td><td>[IN/OUT] The Event Queue which is mapped to the DMA/QDMA channel</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g2574c3da30322981b763e54dd1ea7fb2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setCCRegister" ref="g2574c3da30322981b763e54dd1ea7fb2" args="(EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)" -->
+</div>
+<a class="anchor" id="ga2574c3da30322981b763e54dd1ea7fb2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setCCRegister" ref="ga2574c3da30322981b763e54dd1ea7fb2" args="(EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setCCRegister           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setCCRegister </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -794,33 +821,32 @@ Get the Event Queue mapped to the specified DMA/QDMA channel.
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Set the Channel Controller (CC) Register value. 
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Set the Channel Controller (CC) Register value. </p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>regOffset</em>&nbsp;</td><td>[IN] CC Register offset whose value needs to be set </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>newRegValue</em>&nbsp;</td><td>[IN] New CC Register Value</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is non re-entrant for users using the same EDMA handle i.e. working on the same shadow region. Before modifying a register, it tries to acquire a semaphore (Driver instance specific), to protect simultaneous modification of the same register by two different users. After the successful change, it releases the semaphore. For users working on different shadow regions, thus different EDMA handles, this function is re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is non re-entrant for users using the same EDMA handle i.e. working on the same shadow region. Before modifying a register, it tries to acquire a semaphore (Driver instance specific), to protect simultaneous modification of the same register by two different users. After the successful change, it releases the semaphore. For users working on different shadow regions, thus different EDMA handles, this function is re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g297f964f8fa3df44683e1bdedd56d928"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getCCRegister" ref="g297f964f8fa3df44683e1bdedd56d928" args="(EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)" -->
+</div>
+<a class="anchor" id="ga297f964f8fa3df44683e1bdedd56d928"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getCCRegister" ref="ga297f964f8fa3df44683e1bdedd56d928" args="(EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getCCRegister           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getCCRegister </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -840,33 +866,32 @@ Set the Channel Controller (CC) Register value.
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Get the Channel Controller (CC) Register value. 
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Get the Channel Controller (CC) Register value. </p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>regOffset</em>&nbsp;</td><td>[IN] CC Register offset whose value is needed </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>regValue</em>&nbsp;</td><td>[IN/OUT] CC Register Value</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="ga73fe4d0c29760be55306a8fc1f35161"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_waitAndClearTcc" ref="ga73fe4d0c29760be55306a8fc1f35161" args="(EDMA3_DRV_Handle hEdma, unsigned int tccNo)" -->
+</div>
+<a class="anchor" id="gaa73fe4d0c29760be55306a8fc1f35161"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_waitAndClearTcc" ref="gaa73fe4d0c29760be55306a8fc1f35161" args="(EDMA3_DRV_Handle hEdma, unsigned int tccNo)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -880,34 +905,33 @@ Get the Channel Controller (CC) Register value.
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Wait for a transfer completion interrupt to occur and clear it. 
-<p>
-This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also.<p>
-This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Wait for a transfer completion interrupt to occur and clear it. </p>
+<p>This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also.</p>
+<p>This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>tccNo</em>&nbsp;</td><td>[IN] TCC, specific to which the function waits on a IPR/IPRH bit.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for different tccNo. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for different tccNo. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g3c098a85435e55a8eff2561cbcd79a77"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_checkAndClearTcc" ref="g3c098a85435e55a8eff2561cbcd79a77" args="(EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)" -->
+</div>
+<a class="anchor" id="ga3c098a85435e55a8eff2561cbcd79a77"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_checkAndClearTcc" ref="ga3c098a85435e55a8eff2561cbcd79a77" args="(EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -927,34 +951,33 @@ This function waits for the specific bit indefinitely in a tight loop, with out
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Returns the status of a previously initiated transfer. 
-<p>
-This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Returns the status of a previously initiated transfer. </p>
+<p>This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>tccNo</em>&nbsp;</td><td>[IN] TCC, specific to which the function checks the status of the IPR/IPRH bit. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>tccStatus</em>&nbsp;</td><td>[IN/OUT] Status of the transfer is returned here. Returns "TRUE" if the transfer has completed (IPR/IPRH bit SET), "FALSE" if the transfer has not completed successfully (IPR/IPRH bit NOT SET).</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for different tccNo. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for different tccNo. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="gfeb7b2a17615b14bdac9b11af69e5142"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMPhyAddr" ref="gfeb7b2a17615b14bdac9b11af69e5142" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)" -->
+</div>
+<a class="anchor" id="gafeb7b2a17615b14bdac9b11af69e5142"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMPhyAddr" ref="gafeb7b2a17615b14bdac9b11af69e5142" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -974,35 +997,34 @@ This is a non-blocking function that returns the status of a previously initiate
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Get the PaRAM Set Physical Address associated with a logical channel. 
-<p>
-This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs.<p>
-Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Get the PaRAM Set Physical Address associated with a logical channel. </p>
+<p>This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs.</p>
+<p>Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel for which the PaRAM set physical address is required </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>paramPhyAddr</em>&nbsp;</td><td>[IN/OUT] PaRAM Set physical address is returned here.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g379162d6a5076160d4ed2e01ca8dcac6"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_Ioctl" ref="g379162d6a5076160d4ed2e01ca8dcac6" args="(EDMA3_DRV_Handle hEdma, EDMA3_DRV_IoctlCmd cmd, void *cmdArg, void *param)" -->
+</div>
+<a class="anchor" id="ga379162d6a5076160d4ed2e01ca8dcac6"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_Ioctl" ref="ga379162d6a5076160d4ed2e01ca8dcac6" args="(EDMA3_DRV_Handle hEdma, EDMA3_DRV_IoctlCmd cmd, void *cmdArg, void *param)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_Ioctl           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_Ioctl </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -1010,7 +1032,7 @@ Least significant 16 bits of this address could be used to program the LINK fiel
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g8577940463f7ca5a8977b2fb65fae19a">EDMA3_DRV_IoctlCmd</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8577940463f7ca5a8977b2fb65fae19a">EDMA3_DRV_IoctlCmd</a>&nbsp;</td>
           <td class="paramname"> <em>cmd</em>, </td>
         </tr>
         <tr>
@@ -1028,35 +1050,34 @@ Least significant 16 bits of this address could be used to program the LINK fiel
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-EDMA3 Driver IOCTL. 
-<p>
-This function provides IOCTL functionality for EDMA3 Driver.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>EDMA3 Driver IOCTL. </p>
+<p>This function provides IOCTL functionality for EDMA3 Driver.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>cmd</em>&nbsp;</td><td>[IN] IOCTL command to be performed </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>cmdArg</em>&nbsp;</td><td>[IN/OUT] IOCTL command argument (if any) </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>param</em>&nbsp;</td><td>[IN/OUT] Device/Cmd specific argument</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different EDMA3 Driver Instances (handles). </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different EDMA3 Driver Instances (handles). </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g866c17eaf78a3e0ddc83a397b91fe850"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getInstHandle" ref="g866c17eaf78a3e0ddc83a397b91fe850" args="(unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)" -->
+</div>
+<a class="anchor" id="ga866c17eaf78a3e0ddc83a397b91fe850"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getInstHandle" ref="ga866c17eaf78a3e0ddc83a397b91fe850" args="(unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Handle EDMA3_DRV_getInstHandle           </td>
+          <td class="memname">EDMA3_DRV_Handle EDMA3_DRV_getInstHandle </td>
           <td>(</td>
           <td class="paramtype">unsigned int&nbsp;</td>
           <td class="paramname"> <em>phyCtrllerInstId</em>, </td>
@@ -1076,35 +1097,35 @@ This function provides IOCTL functionality for EDMA3 Driver.<p>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Return the previously opened EDMA3 Driver Instance handle. 
-<p>
-This API is used to return the previously opened EDMA3 Driver's Instance Handle (region specific), which could be used to call other EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances, for a single shadow region, this API is provided. This API is meant for users who DO NOT want to / could not open a new Driver Instance and hence re-use the existing Driver Instance to allocate EDMA3 resources and use various other EDMA3 Driver APIs.<p>
-In case the Driver Instance is not yet opened, NULL is returned as the function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned in the errorCode.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Return the previously opened EDMA3 Driver Instance handle. </p>
+<p>This API is used to return the previously opened EDMA3 Driver's Instance Handle (region specific), which could be used to call other EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances, for a single shadow region, this API is provided. This API is meant for users who DO NOT want to / could not open a new Driver Instance and hence re-use the existing Driver Instance to allocate EDMA3 resources and use various other EDMA3 Driver APIs.</p>
+<p>In case the Driver Instance is not yet opened, NULL is returned as the function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned in the errorCode.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>phyCtrllerInstId</em>&nbsp;</td><td>[IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>regionId</em>&nbsp;</td><td>[IN] Shadow Region id for which the previously opened driver's instance handle is required. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>errorCode</em>&nbsp;</td><td>[OUT] Error code while returning Driver Instance Handle.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_Handle : If successful, this API will return the driver's instance handle.</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>1) This API returns the previously opened EDMA3 Driver's Instance handle. The instance, if exists, could have been opened by some other user (most probably) or may be by the same user calling this API. If it was opened by some other user, then that user can very well close this instance anytime, without even knowing that the same instance handle is being used by other users as well. In that case, the handle becomes INVALID and user has to open a valid driver instance for his/her use.</dd></dl>
-2) This function is re-entrant. 
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_Handle : If successful, this API will return the driver's instance handle.</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>1) This API returns the previously opened EDMA3 Driver's Instance handle. The instance, if exists, could have been opened by some other user (most probably) or may be by the same user calling this API. If it was opened by some other user, then that user can very well close this instance anytime, without even knowing that the same instance handle is being used by other users as well. In that case, the handle becomes INVALID and user has to open a valid driver instance for his/her use.</dd></dl>
+<p>2) This function is re-entrant. </p>
+
+</div>
 </div>
-</div><p>
-<a class="anchor" name="g43031c6c66af92677c388c156b50480b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_registerTccCb" ref="g43031c6c66af92677c388c156b50480b" args="(EDMA3_DRV_Handle hEdma, const unsigned int channelId, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
+<a class="anchor" id="ga43031c6c66af92677c388c156b50480b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_registerTccCb" ref="ga43031c6c66af92677c388c156b50480b" args="(EDMA3_DRV_Handle hEdma, const unsigned int channelId, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_registerTccCb           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_registerTccCb </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -1130,36 +1151,35 @@ In case the Driver Instance is not yet opened, NULL is returned as the function
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Registers a transfer completion handler for a specific DMA/QDMA channel. 
-<p>
-This function registers a non-NULL callback function for a specific DMA or QDMA channel and enables the completion interrupt for the TCC associated with the underlying channel in the IER/IERH register. It also sets the DRAE/DRAEH register for the TCC associated with the specified DMA/QDMA channel. If user enables the transfer completion interrupts (intermediate or final) in the OPT field of the associated PaRAM Set, the registered callback function will be called by the EDMA3 Resource Manager.<p>
-If a call-back function is already registered for the channel, the API fails with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Registers a transfer completion handler for a specific DMA/QDMA channel. </p>
+<p>This function registers a non-NULL callback function for a specific DMA or QDMA channel and enables the completion interrupt for the TCC associated with the underlying channel in the IER/IERH register. It also sets the DRAE/DRAEH register for the TCC associated with the specified DMA/QDMA channel. If user enables the transfer completion interrupts (intermediate or final) in the OPT field of the associated PaRAM Set, the registered callback function will be called by the EDMA3 Resource Manager.</p>
+<p>If a call-back function is already registered for the channel, the API fails with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>channelId</em>&nbsp;</td><td>[IN] DMA/QDMA channel for which the callback function needs to be registered. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>tccCb</em>&nbsp;</td><td>[IN] The callback function to be registered. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>cbData</em>&nbsp;</td><td>[IN] Callback data to be passed while calling the callback function.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="ga4ab2ce058e4e40a812b8a20970d4088"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unregisterTccCb" ref="ga4ab2ce058e4e40a812b8a20970d4088" args="(EDMA3_DRV_Handle hEdma, const unsigned int channelId)" -->
+</div>
+<a class="anchor" id="gaa4ab2ce058e4e40a812b8a20970d4088"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unregisterTccCb" ref="gaa4ab2ce058e4e40a812b8a20970d4088" args="(EDMA3_DRV_Handle hEdma, const unsigned int channelId)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -1173,33 +1193,32 @@ If a call-back function is already registered for the channel, the API fails wit
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Un-register the previously registered callback function against a DMA/QDMA channel. 
-<p>
-This function un-registers the previously registered callback function for the DMA/QDMA channel by removing any stored callback function. Moreover, it clears the: Interrupt Enable Register (IER/IERH) by writing to the IECR/IECRH register, for the TCC associated with that particular channel, DRA/DRAEH register for the TCC associated with the specified DMA/QDMA channel<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Un-register the previously registered callback function against a DMA/QDMA channel. </p>
+<p>This function un-registers the previously registered callback function for the DMA/QDMA channel by removing any stored callback function. Moreover, it clears the: Interrupt Enable Register (IER/IERH) by writing to the IECR/IECRH register, for the TCC associated with that particular channel, DRA/DRAEH register for the TCC associated with the specified DMA/QDMA channel</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>channelId</em>&nbsp;</td><td>[IN] DMA/QDMA channel for which the callback function needs to be un-registered.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique channelId. It is non-re-entrant for same channelId. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique channelId. It is non-re-entrant for same channelId. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g276f4ecd7f1e59f09ad065b633643ae4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setTcErrorInt" ref="g276f4ecd7f1e59f09ad065b633643ae4" args="(unsigned int phyCtrllerInstId, unsigned int tcId, EDMA3_DRV_Tc_Err tcErr)" -->
+</div>
+<a class="anchor" id="ga276f4ecd7f1e59f09ad065b633643ae4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setTcErrorInt" ref="ga276f4ecd7f1e59f09ad065b633643ae4" args="(unsigned int phyCtrllerInstId, unsigned int tcId, EDMA3_DRV_Tc_Err tcErr)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt </td>
           <td>(</td>
           <td class="paramtype">unsigned int&nbsp;</td>
           <td class="paramname"> <em>phyCtrllerInstId</em>, </td>
@@ -1213,40 +1232,39 @@ This function un-registers the previously registered callback function for the D
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g2b3b55b1d7c987a7873d8b0b085173b2">EDMA3_DRV_Tc_Err</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga2b3b55b1d7c987a7873d8b0b085173b2">EDMA3_DRV_Tc_Err</a>&nbsp;</td>
           <td class="paramname"> <em>tcErr</em></td><td>&nbsp;</td>
         </tr>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Enable/disable specific EDMA3 Transfer Controller Interrupts. 
-<p>
-This function allows one to enable/disable specific EDMA3 Transfer Controller Interrupts. Since these interrupts don't get enabled by default, this API can be used to achieve the same.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Enable/disable specific EDMA3 Transfer Controller Interrupts. </p>
+<p>This function allows one to enable/disable specific EDMA3 Transfer Controller Interrupts. Since these interrupts don't get enabled by default, this API can be used to achieve the same.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>phyCtrllerInstId</em>&nbsp;</td><td>[IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>tcId</em>&nbsp;</td><td>[IN] Transfer Controller Id. It starts from 0 for each EDMA3 hardware and can go upto (TCs available on EDMA3 Hardware - 1). </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>tcErr</em>&nbsp;</td><td>[IN] TC Error Interrupts which need to be enabled/disabled.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique combination of EDMA3 hw and TC. It is non-re-entrant for same combination. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique combination of EDMA3 hw and TC. It is non-re-entrant for same combination. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g85bad51ec992ce36ed7f28842b7d8219"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getChannelStatus" ref="g85bad51ec992ce36ed7f28842b7d8219" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *lchStatus)" -->
+</div>
+<a class="anchor" id="ga85bad51ec992ce36ed7f28842b7d8219"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getChannelStatus" ref="ga85bad51ec992ce36ed7f28842b7d8219" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *lchStatus)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getChannelStatus           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getChannelStatus </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -1266,34 +1284,33 @@ This function allows one to enable/disable specific EDMA3 Transfer Controller In
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Get the current status of the DMA/QDMA channel. 
-<p>
-This function returns the current status of the specific DMA/QDMA channel. For a DMA channel, it checks whether an event is pending in ER, transfer completion interrupt is pending in IPR and event miss error interrupt is pending in EMR or not. For a QDMA channel, it checks whether a transfer completion interrupt is pending in IPR and event miss error interrupt is pending in QEMR or not.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Get the current status of the DMA/QDMA channel. </p>
+<p>This function returns the current status of the specific DMA/QDMA channel. For a DMA channel, it checks whether an event is pending in ER, transfer completion interrupt is pending in IPR and event miss error interrupt is pending in EMR or not. For a QDMA channel, it checks whether a transfer completion interrupt is pending in IPR and event miss error interrupt is pending in QEMR or not.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] DMA/QDMA channel for which the current status is required. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lchStatus</em>&nbsp;</td><td>[IN/OUT]Status of the channel. Defines mentioned above are used (and may be combined) to return the actual status.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="gba9535a00375255494df382382b834de"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapTccLinkCh" ref="gba9535a00375255494df382382b834de" args="(EDMA3_DRV_Handle hEdma, unsigned int linkCh, unsigned int tcc)" -->
+</div>
+<a class="anchor" id="gaba9535a00375255494df382382b834de"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapTccLinkCh" ref="gaba9535a00375255494df382382b834de" args="(EDMA3_DRV_Handle hEdma, unsigned int linkCh, unsigned int tcc)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -1313,31 +1330,82 @@ This function returns the current status of the specific DMA/QDMA channel. For a
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Associates a link channel and a TCC. 
-<p>
-This API is used to map a TCC to a LINK channel. It should be used with LINK channels ONLY else it will fail. It will copy the TCC code in the OPT field of the param set associated with the link channel.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Associates a link channel and a TCC. </p>
+<p>This API is used to map a TCC to a LINK channel. It should be used with LINK channels ONLY else it will fail. It will copy the TCC code in the OPT field of the param set associated with the link channel.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>linkCh</em>&nbsp;</td><td>[IN] Link Channel to which a particular TCC needs to be mapped. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>tcc</em>&nbsp;</td><td>[IN] TCC which needs to be mapped.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique linkCh values. It is non-re-entrant for same linkCh values. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique linkCh values. It is non-re-entrant for same linkCh values. </dd></dl>
 
 </div>
-</div><p>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:42 2010 for EDMA3 Driver by&nbsp;
+<a class="anchor" id="ga1ff9d2ede0fb29c7194f15ba58ad8e0f"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_initXbarEventMap" ref="ga1ff9d2ede0fb29c7194f15ba58ad8e0f" args="(EDMA3_DRV_Handle hEdma, const EDMA3_DRV_GblXbarToChanConfigParams *edmaGblXbarConfig, EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc, EDMA3_DRV_xbarConfigScr configXbarScr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap </td>
+          <td>(</td>
+          <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
+          <td class="paramname"> <em>hEdma</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *&nbsp;</td>
+          <td class="paramname"> <em>edmaGblXbarConfig</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a>&nbsp;</td>
+          <td class="paramname"> <em>mapXbarEvtFunc</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a>&nbsp;</td>
+          <td class="paramname"> <em>configXbarScr</em></td><td>&nbsp;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+<p>Initialize the cross bar mapped event to channel function. </p>
+<p>This API provides interface to associate the cross bar mapped event to edma channel in the driver. This function will called by the application during initilization. User could pass the application specific configuration structure during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_&lt;SOC_NAME&gt;_cfg.c, in case it is available. </p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table border="0" cellspacing="2" cellpadding="0">
+    <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>edmaGblXbarConfig</em>&nbsp;</td><td>[IN] This is the configuration data structure for mapping the events to the channel </td></tr>
+    <tr><td valign="top"></td><td valign="top"><em>mapXbarEvtFunc</em>&nbsp;</td><td>[IN] This is the user defined function for mapping the cross bar event to channel.</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant. </dd></dl>
+
+</div>
+</div>
+</div>
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
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 </html>
index e7e8ff6b320b719f3d591a011388ef34587f9958..4530c0e2c4cd76e82ab9cd7794a63f00b9f46d74 100755 (executable)
@@ -1,73 +1,62 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: EDMA3 Driver Basic APIs</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
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+<body>
+<!-- Generated by Doxygen 1.6.1 -->
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       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
 </div>
 <div class="contents">
-<h1>EDMA3 Driver Basic APIs<br>
+<h1>EDMA3 Driver Basic APIs<br/>
 <small>
 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html">EDMA3 Driver APIs</a>]</small>
 </h1><table border="0" cellpadding="0" cellspacing="0">
-<tr><td></td></tr>
-<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g301122cb5f7cca50ae824611bd816f8e">EDMA3_DRV_requestChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Request a DMA/QDMA/Link channel.  <a href="#g301122cb5f7cca50ae824611bd816f8e"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g0589ed9b15b42ecefc4a6ccd8e1758fc">EDMA3_DRV_freeChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings.  <a href="#g0589ed9b15b42ecefc4a6ccd8e1758fc"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g35daa16c899b38d5af19d7d2d22777a5">EDMA3_DRV_clearErrorBits</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disables the DMA Channel by clearing the Event Enable Register and clears Error Register &amp; Secondary Event Register for a specific DMA channel.  <a href="#g35daa16c899b38d5af19d7d2d22777a5"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g095f1fea5377f30e65e6135414ad6e77">EDMA3_DRV_setOptField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> optField, unsigned int newOptFieldVal)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.  <a href="#g095f1fea5377f30e65e6135414ad6e77"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gd6bc4ec80662493860491f6374af7695">EDMA3_DRV_getOptField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> optField, unsigned int *optFieldVal)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.  <a href="#gd6bc4ec80662493860491f6374af7695"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g95f7e74ccb30f273b42b0cc08664ba55">EDMA3_DRV_setSrcParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> addrMode, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> fifoWidth)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA source parameters setup.  <a href="#g95f7e74ccb30f273b42b0cc08664ba55"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gb4be03dc87dc50975c5ea870944dcee4">EDMA3_DRV_setDestParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> addrMode, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> fifoWidth)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA Destination parameters setup.  <a href="#gb4be03dc87dc50975c5ea870944dcee4"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g212d4abb6f644084b3a29b856c0ef0ac">EDMA3_DRV_setSrcIndex</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA source index setup.  <a href="#g212d4abb6f644084b3a29b856c0ef0ac"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g4e7ec3c58f498bdbac7a507e0cba6221">EDMA3_DRV_setDestIndex</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA destination index setup.  <a href="#g4e7ec3c58f498bdbac7a507e0cba6221"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g8e54f2e2e016bc557ed3374eb46d62ee">EDMA3_DRV_setTransferParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g1cc0705e142298a424a312034bd3b2c2">EDMA3_DRV_SyncType</a> syncType)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA transfer parameters setup.  <a href="#g8e54f2e2e016bc557ed3374eb46d62ee"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g5c80afa7645f1e492951c0419c21dbe6">EDMA3_DRV_enableTransfer</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Start EDMA transfer on the specified channel.  <a href="#g5c80afa7645f1e492951c0419c21dbe6"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gdb56f2a6d896c03a77f14c8fdf57a397">EDMA3_DRV_disableTransfer</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disable DMA transfer on the specified channel.  <a href="#gdb56f2a6d896c03a77f14c8fdf57a397"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g11070a2e9fb80e16fe96e8ad210e0b59">EDMA3_DRV_disableLogicalChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disable the event driven DMA channel or QDMA channel.  <a href="#g11070a2e9fb80e16fe96e8ad210e0b59"></a><br></td></tr>
+<tr><td colspan="2"><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e">EDMA3_DRV_requestChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Request a DMA/QDMA/Link channel.  <a href="#ga301122cb5f7cca50ae824611bd816f8e"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga0589ed9b15b42ecefc4a6ccd8e1758fc">EDMA3_DRV_freeChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings.  <a href="#ga0589ed9b15b42ecefc4a6ccd8e1758fc"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga35daa16c899b38d5af19d7d2d22777a5">EDMA3_DRV_clearErrorBits</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disables the DMA Channel by clearing the Event Enable Register and clears Error Register &amp; Secondary Event Register for a specific DMA channel.  <a href="#ga35daa16c899b38d5af19d7d2d22777a5"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga095f1fea5377f30e65e6135414ad6e77">EDMA3_DRV_setOptField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> optField, unsigned int newOptFieldVal)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.  <a href="#ga095f1fea5377f30e65e6135414ad6e77"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gad6bc4ec80662493860491f6374af7695">EDMA3_DRV_getOptField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> optField, unsigned int *optFieldVal)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.  <a href="#gad6bc4ec80662493860491f6374af7695"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga95f7e74ccb30f273b42b0cc08664ba55">EDMA3_DRV_setSrcParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> addrMode, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> fifoWidth)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA source parameters setup.  <a href="#ga95f7e74ccb30f273b42b0cc08664ba55"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gab4be03dc87dc50975c5ea870944dcee4">EDMA3_DRV_setDestParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> addrMode, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> fifoWidth)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA Destination parameters setup.  <a href="#gab4be03dc87dc50975c5ea870944dcee4"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga212d4abb6f644084b3a29b856c0ef0ac">EDMA3_DRV_setSrcIndex</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA source index setup.  <a href="#ga212d4abb6f644084b3a29b856c0ef0ac"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga4e7ec3c58f498bdbac7a507e0cba6221">EDMA3_DRV_setDestIndex</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA destination index setup.  <a href="#ga4e7ec3c58f498bdbac7a507e0cba6221"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga8e54f2e2e016bc557ed3374eb46d62ee">EDMA3_DRV_setTransferParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga1cc0705e142298a424a312034bd3b2c2">EDMA3_DRV_SyncType</a> syncType)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">DMA transfer parameters setup.  <a href="#ga8e54f2e2e016bc557ed3374eb46d62ee"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga5c80afa7645f1e492951c0419c21dbe6">EDMA3_DRV_enableTransfer</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Start EDMA transfer on the specified channel.  <a href="#ga5c80afa7645f1e492951c0419c21dbe6"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gadb56f2a6d896c03a77f14c8fdf57a397">EDMA3_DRV_disableTransfer</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disable DMA transfer on the specified channel.  <a href="#gadb56f2a6d896c03a77f14c8fdf57a397"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga11070a2e9fb80e16fe96e8ad210e0b59">EDMA3_DRV_disableLogicalChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Disable the event driven DMA channel or QDMA channel.  <a href="#ga11070a2e9fb80e16fe96e8ad210e0b59"></a><br/></td></tr>
 </table>
-<hr><h2>Function Documentation</h2>
-<a class="anchor" name="g301122cb5f7cca50ae824611bd816f8e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_requestChannel" ref="g301122cb5f7cca50ae824611bd816f8e" args="(EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="ga301122cb5f7cca50ae824611bd816f8e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_requestChannel" ref="ga301122cb5f7cca50ae824611bd816f8e" args="(EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_requestChannel           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_requestChannel </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Request a DMA/QDMA/Link channel. 
-<p>
-Each channel (DMA/QDMA/Link) must be requested before initiating a DMA transfer on that channel.<p>
-This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. User can also specify a specific TCC which needs to be allocated with the DMA/QDMA channel or else can request any available TCC.<p>
-For Link channels, ONLY a PaRAM Set is allocated and the allocated PaRAM Set number is returned as the logical channel no. A TCC code can also be specified while making the request. This TCC code will be copied to the LINK field of the allocated PaRAM Set and will be associated with the Link channel.<p>
-User can request a specific logical channel - DMA, QDMA and Link, by passing the channel id in 'pLCh'. Note that the channel id is the same as the actual resource id in case of DMA channels and Link channels. For DMA channels, channel id lies between 0 and (max dma channels - 1). For Link channels, channel id lies between (max dma channels) and (max param sets - 1). To allocate specific QDMA channels, user SHOULD use the defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.<p>
-User can also request ANY available logical channel by specifying the below mentioned values in '*pLCh': a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed. d) EDMA3_DRV_LINK_CHANNEL_WITH_TCC: For Link channels. User should use this value to request link channels with TCC code.<p>
-This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC).<p>
-This API also registers a specific callback function, in case the same is provided, against the allocated TCC. To do this, this API calls EDMA3_RM_registerTccCb(), which is a part of the Resource Manager. Please note that the interrupts are enabled for the specific TCC only if callback function is provided. In the absence of this, the API assumes that the requested logical channel is going to be used in Poll mode environment.<p>
-For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets the event queue for the channel allocated. The event queue needs to be specified by the user.<p>
-For DMA channel, it also sets the DCHMAP register, if required.<p>
-For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Request a DMA/QDMA/Link channel. </p>
+<p>Each channel (DMA/QDMA/Link) must be requested before initiating a DMA transfer on that channel.</p>
+<p>This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. User can also specify a specific TCC which needs to be allocated with the DMA/QDMA channel or else can request any available TCC.</p>
+<p>For Link channels, ONLY a PaRAM Set is allocated and the allocated PaRAM Set number is returned as the logical channel no. A TCC code can also be specified while making the request. This TCC code will be copied to the LINK field of the allocated PaRAM Set and will be associated with the Link channel.</p>
+<p>User can request a specific logical channel - DMA, QDMA and Link, by passing the channel id in 'pLCh'. Note that the channel id is the same as the actual resource id in case of DMA channels and Link channels. For DMA channels, channel id lies between 0 and (max dma channels - 1). For Link channels, channel id lies between (max dma channels) and (max param sets - 1). To allocate specific QDMA channels, user SHOULD use the defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.</p>
+<p>User can also request ANY available logical channel by specifying the below mentioned values in '*pLCh': a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed. d) EDMA3_DRV_LINK_CHANNEL_WITH_TCC: For Link channels. User should use this value to request link channels with TCC code.</p>
+<p>This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC).</p>
+<p>This API also registers a specific callback function, in case the same is provided, against the allocated TCC. To do this, this API calls EDMA3_RM_registerTccCb(), which is a part of the Resource Manager. Please note that the interrupts are enabled for the specific TCC only if callback function is provided. In the absence of this, the API assumes that the requested logical channel is going to be used in Poll mode environment.</p>
+<p>For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets the event queue for the channel allocated. The event queue needs to be specified by the user.</p>
+<p>For DMA channel, it also sets the DCHMAP register, if required.</p>
+<p>For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the previously opened Driver Instance. </td></tr>
-    <tr><td valign="top"></td><td valign="top"><em>pLCh</em>&nbsp;</td><td>[IN/OUT] Requested logical channel id. Examples:<ul>
-<li>EDMA3_DRV_HW_CHANNEL_EVENT_0</li><li>To request a DMA Master Channel mapped to EDMA Event 0.</li></ul>
+    <tr><td valign="top"></td><td valign="top"><em>pLCh</em>&nbsp;</td><td>[IN/OUT] Requested logical channel id. Examples:</p>
+<ul>
+<li>EDMA3_DRV_HW_CHANNEL_EVENT_0</li>
+<li>To request a DMA Master Channel mapped to EDMA Event 0.</li>
+</ul>
 </td></tr>
   </table>
+  </dd>
 </dl>
 <ul>
-<li>EDMA3_DRV_DMA_CHANNEL_ANY</li><li>For requesting any DMA Master channel with no event mapping.</li></ul>
-<p>
+<li>EDMA3_DRV_DMA_CHANNEL_ANY</li>
+<li>For requesting any DMA Master channel with no event mapping.</li>
+</ul>
 <ul>
-<li>EDMA3_DRV_QDMA_CHANNEL_ANY</li><li>For requesting any QDMA Master channel</li></ul>
-<p>
+<li>EDMA3_DRV_QDMA_CHANNEL_ANY</li>
+<li>For requesting any QDMA Master channel</li>
+</ul>
 <ul>
-<li>EDMA3_DRV_QDMA_CHANNEL_0</li><li>For requesting the QDMA Channel 0.</li></ul>
-<p>
+<li>EDMA3_DRV_QDMA_CHANNEL_0</li>
+<li>For requesting the QDMA Channel 0.</li>
+</ul>
 <ul>
-<li>EDMA3_DRV_LINK_CHANNEL</li><li>For requesting a DMA Slave Channel,</li><li>to be linked to some other Master</li><li>channel.</li></ul>
-<p>
+<li>EDMA3_DRV_LINK_CHANNEL</li>
+<li>For requesting a DMA Slave Channel,</li>
+<li>to be linked to some other Master</li>
+<li>channel.</li>
+</ul>
 <ul>
-<li>EDMA3_DRV_LINK_CHANNEL_WITH_TCC</li><li>For requesting a DMA Slave Channel,</li><li>to be linked to some other Master</li><li>channel, with a TCC associated with it.</li></ul>
-<p>
-In case user passes a specific channel Id, pLCh value is left unchanged. In case user requests ANY available resource, the allocated channel id is returned in pLCh.<p>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>To request a PaRAM Set for the purpose of linking to another channel, call the function with</dd></dl>
-*pLCh = EDMA3_DRV_LINK_CHANNEL or EDMA3_DRV_LINK_CHANNEL_WITH_TCC<p>
-This function will update *pLCh with the allocated Link channel handle.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<li>EDMA3_DRV_LINK_CHANNEL_WITH_TCC</li>
+<li>For requesting a DMA Slave Channel,</li>
+<li>to be linked to some other Master</li>
+<li>channel, with a TCC associated with it.</li>
+</ul>
+<p>In case user passes a specific channel Id, pLCh value is left unchanged. In case user requests ANY available resource, the allocated channel id is returned in pLCh.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>To request a PaRAM Set for the purpose of linking to another channel, call the function with</dd></dl>
+<p>*pLCh = EDMA3_DRV_LINK_CHANNEL or EDMA3_DRV_LINK_CHANNEL_WITH_TCC</p>
+<p>This function will update *pLCh with the allocated Link channel handle.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
-    <tr><td valign="top"></td><td valign="top"><em>pTcc</em>&nbsp;</td><td>[IN/OUT] The channel number on which the completion/error interrupt is generated. Not used if user requested for a Link channel. Examples:<ul>
-<li>EDMA3_DRV_HW_CHANNEL_EVENT_0</li><li>To request TCC associated with</li><li>DMA Master Channel mapped to EDMA</li><li>event 0.</li></ul>
+    <tr><td valign="top"></td><td valign="top"><em>pTcc</em>&nbsp;</td><td>[IN/OUT] The channel number on which the completion/error interrupt is generated. Not used if user requested for a Link channel. Examples:</p>
+<ul>
+<li>EDMA3_DRV_HW_CHANNEL_EVENT_0</li>
+<li>To request TCC associated with</li>
+<li>DMA Master Channel mapped to EDMA</li>
+<li>event 0.</li>
+</ul>
 </td></tr>
   </table>
+  </dd>
 </dl>
 <ul>
-<li>EDMA3_DRV_TCC_ANY</li><li>For requesting any TCC with no</li><li>channel mapping. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC, the allocated one is returned in pTcc</li></ul>
-<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<li>EDMA3_DRV_TCC_ANY</li>
+<li>For requesting any TCC with no</li>
+<li>channel mapping. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC, the allocated one is returned in pTcc</li>
+</ul>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>evtQueue</em>&nbsp;</td><td>[IN] Event Queue Number to which the channel will be mapped (valid only for the Master Channel (DMA/QDMA) request)</td></tr>
     <tr><td valign="top"></td><td valign="top"><em>tccCb</em>&nbsp;</td><td>[IN] TCC callback - caters to channel- specific events like "Event Miss Error" or "Transfer Complete"</td></tr>
     <tr><td valign="top"></td><td valign="top"><em>cbData</em>&nbsp;</td><td>[IN] Data which will be passed directly to the tccCb callback function</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function internally uses EDMA3 Resource Manager, which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It also disables the global interrupts while modifying the global CC registers. It is re-entrant, but SHOULD NOT be called from the user callback function (ISR context). </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function internally uses EDMA3 Resource Manager, which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It also disables the global interrupts while modifying the global CC registers. It is re-entrant, but SHOULD NOT be called from the user callback function (ISR context). </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g0589ed9b15b42ecefc4a6ccd8e1758fc"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_freeChannel" ref="g0589ed9b15b42ecefc4a6ccd8e1758fc" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId)" -->
+</div>
+<a class="anchor" id="ga0589ed9b15b42ecefc4a6ccd8e1758fc"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_freeChannel" ref="ga0589ed9b15b42ecefc4a6ccd8e1758fc" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_freeChannel           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_freeChannel </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -192,35 +201,34 @@ This function will update *pLCh with the allocated Link channel handle.<p>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. 
-<p>
-This API internally uses EDMA3_RM_freeResource () to free the desired resources.<p>
-For Link channels, this API only frees the associated PaRAM Set.<p>
-For DMA/QDMA channels, it does the following operations: a) Disable any ongoing transfer on the channel, b) Unregister the TCC Callback function and disable the interrupts, c) Remove the channel to Event Queue mapping, d) For DMA channels, clear the DCHMAP register, if available e) For QDMA channels, clear the QCHMAP register, f) Frees the DMA/QDMA channel in the end.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. </p>
+<p>This API internally uses EDMA3_RM_freeResource () to free the desired resources.</p>
+<p>For Link channels, this API only frees the associated PaRAM Set.</p>
+<p>For DMA/QDMA channels, it does the following operations: a) Disable any ongoing transfer on the channel, b) Unregister the TCC Callback function and disable the interrupts, c) Remove the channel to Event Queue mapping, d) For DMA channels, clear the DCHMAP register, if available e) For QDMA channels, clear the QCHMAP register, f) Frees the DMA/QDMA channel in the end.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>channelId</em>&nbsp;</td><td>[IN] Logical Channel number to be freed.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function disables the global interrupts while modifying the global CC registers and while modifying global data structures, to prevent simultaneous access to the global pool of resources. It internally calls EDMA3_RM_freeResource () for resource de-allocation. It is re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function disables the global interrupts while modifying the global CC registers and while modifying global data structures, to prevent simultaneous access to the global pool of resources. It internally calls EDMA3_RM_freeResource () for resource de-allocation. It is re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g35daa16c899b38d5af19d7d2d22777a5"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_clearErrorBits" ref="g35daa16c899b38d5af19d7d2d22777a5" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId)" -->
+</div>
+<a class="anchor" id="ga35daa16c899b38d5af19d7d2d22777a5"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_clearErrorBits" ref="ga35daa16c899b38d5af19d7d2d22777a5" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_clearErrorBits           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_clearErrorBits </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -234,33 +242,32 @@ For DMA/QDMA channels, it does the following operations: a) Disable any ongoing
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Disables the DMA Channel by clearing the Event Enable Register and clears Error Register &amp; Secondary Event Register for a specific DMA channel. 
-<p>
-This API clears the Event Enable register, Event Miss register and Secondary Event register for a specific DMA channel. It also clears the CC Error register.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Disables the DMA Channel by clearing the Event Enable Register and clears Error Register &amp; Secondary Event Register for a specific DMA channel. </p>
+<p>This API clears the Event Enable register, Event Miss register and Secondary Event register for a specific DMA channel. It also clears the CC Error register.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>channelId</em>&nbsp;</td><td>[IN] DMA Channel needs to be cleaned.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g095f1fea5377f30e65e6135414ad6e77"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setOptField" ref="g095f1fea5377f30e65e6135414ad6e77" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int newOptFieldVal)" -->
+</div>
+<a class="anchor" id="ga095f1fea5377f30e65e6135414ad6e77"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setOptField" ref="ga095f1fea5377f30e65e6135414ad6e77" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int newOptFieldVal)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setOptField           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setOptField </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -274,7 +281,7 @@ This API clears the Event Enable register, Event Miss register and Secondary Eve
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a>&nbsp;</td>
           <td class="paramname"> <em>optField</em>, </td>
         </tr>
         <tr>
@@ -286,35 +293,34 @@ This API clears the Event Enable register, Event Miss register and Secondary Eve
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. 
-<p>
-This API can be used to set various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. </p>
+<p>This API can be used to set various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel, bound to which PaRAM set OPT field needs to be set. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>optField</em>&nbsp;</td><td>[IN] The particular field of OPT Word that needs setting </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>newOptFieldVal</em>&nbsp;</td><td>[IN] The new OPT field value</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="gd6bc4ec80662493860491f6374af7695"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getOptField" ref="gd6bc4ec80662493860491f6374af7695" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int *optFieldVal)" -->
+</div>
+<a class="anchor" id="gad6bc4ec80662493860491f6374af7695"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getOptField" ref="gad6bc4ec80662493860491f6374af7695" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int *optFieldVal)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getOptField           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_getOptField </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -328,7 +334,7 @@ This API can be used to set various optional parameters for an EDMA3 transfer. L
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a>&nbsp;</td>
           <td class="paramname"> <em>optField</em>, </td>
         </tr>
         <tr>
@@ -340,35 +346,34 @@ This API can be used to set various optional parameters for an EDMA3 transfer. L
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. 
-<p>
-This API can be used to read various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. </p>
+<p>This API can be used to read various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel, bound to which PaRAM set OPT field is required. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>optField</em>&nbsp;</td><td>[IN] The particular field of OPT Word that is needed </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>optFieldVal</em>&nbsp;</td><td>[IN/OUT] Value of the OPT field</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g95f7e74ccb30f273b42b0cc08664ba55"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setSrcParams" ref="g95f7e74ccb30f273b42b0cc08664ba55" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)" -->
+</div>
+<a class="anchor" id="ga95f7e74ccb30f273b42b0cc08664ba55"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setSrcParams" ref="ga95f7e74ccb30f273b42b0cc08664ba55" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setSrcParams           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setSrcParams </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -388,51 +393,57 @@ This API can be used to read various optional parameters for an EDMA3 transfer.
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a>&nbsp;</td>
           <td class="paramname"> <em>addrMode</em>, </td>
         </tr>
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a>&nbsp;</td>
           <td class="paramname"> <em>fifoWidth</em></td><td>&nbsp;</td>
         </tr>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-DMA source parameters setup. 
-<p>
-It is used to program the source address, source side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.<p>
-In FIFO Addressing mode, memory location must be 32 bytes aligned.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>DMA source parameters setup. </p>
+<p>It is used to program the source address, source side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.</p>
+<p>In FIFO Addressing mode, memory location must be 32 bytes aligned.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel for which the source parameters are to be configured </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>srcAddr</em>&nbsp;</td><td>[IN] Source address </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>addrMode</em>&nbsp;</td><td>[IN] Address mode [FIFO or Increment] </td></tr>
-    <tr><td valign="top"></td><td valign="top"><em>fifoWidth</em>&nbsp;</td><td>[IN] Width of FIFO (Valid only if addrMode is FIFO)<ol type=1>
-<li>0 - 8 bit</li><li>1 - 16 bit</li><li>2 - 32 bit</li><li>3 - 64 bit</li><li>4 - 128 bit</li><li>5 - 256 bit</li></ol>
+    <tr><td valign="top"></td><td valign="top"><em>fifoWidth</em>&nbsp;</td><td>[IN] Width of FIFO (Valid only if addrMode is FIFO)</p>
+<ol type="1">
+<li>0 - 8 bit</li>
+<li>1 - 16 bit</li>
+<li>2 - 32 bit</li>
+<li>3 - 64 bit</li>
+<li>4 - 128 bit</li>
+<li>5 - 256 bit</li>
+</ol>
 </td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="gb4be03dc87dc50975c5ea870944dcee4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setDestParams" ref="gb4be03dc87dc50975c5ea870944dcee4" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)" -->
+</div>
+<a class="anchor" id="gab4be03dc87dc50975c5ea870944dcee4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setDestParams" ref="gab4be03dc87dc50975c5ea870944dcee4" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setDestParams           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setDestParams </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -452,51 +463,57 @@ In FIFO Addressing mode, memory location must be 32 bytes aligned.<p>
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a>&nbsp;</td>
           <td class="paramname"> <em>addrMode</em>, </td>
         </tr>
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a>&nbsp;</td>
           <td class="paramname"> <em>fifoWidth</em></td><td>&nbsp;</td>
         </tr>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-DMA Destination parameters setup. 
-<p>
-It is used to program the destination address, destination side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.<p>
-In FIFO Addressing mode, memory location must be 32 bytes aligned.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>DMA Destination parameters setup. </p>
+<p>It is used to program the destination address, destination side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.</p>
+<p>In FIFO Addressing mode, memory location must be 32 bytes aligned.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel for which the destination parameters are to be configured </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>destAddr</em>&nbsp;</td><td>[IN] Destination address </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>addrMode</em>&nbsp;</td><td>[IN] Address mode [FIFO or Increment] </td></tr>
-    <tr><td valign="top"></td><td valign="top"><em>fifoWidth</em>&nbsp;</td><td>[IN] Width of FIFO (Valid only if addrMode is FIFO)<ol type=1>
-<li>0 - 8 bit</li><li>1 - 16 bit</li><li>2 - 32 bit</li><li>3 - 64 bit</li><li>4 - 128 bit</li><li>5 - 256 bit</li></ol>
+    <tr><td valign="top"></td><td valign="top"><em>fifoWidth</em>&nbsp;</td><td>[IN] Width of FIFO (Valid only if addrMode is FIFO)</p>
+<ol type="1">
+<li>0 - 8 bit</li>
+<li>1 - 16 bit</li>
+<li>2 - 32 bit</li>
+<li>3 - 64 bit</li>
+<li>4 - 128 bit</li>
+<li>5 - 256 bit</li>
+</ol>
 </td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g212d4abb6f644084b3a29b856c0ef0ac"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setSrcIndex" ref="g212d4abb6f644084b3a29b856c0ef0ac" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)" -->
+</div>
+<a class="anchor" id="ga212d4abb6f644084b3a29b856c0ef0ac"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setSrcIndex" ref="ga212d4abb6f644084b3a29b856c0ef0ac" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setSrcIndex           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setSrcIndex </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -522,37 +539,36 @@ In FIFO Addressing mode, memory location must be 32 bytes aligned.<p>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-DMA source index setup. 
-<p>
-It is used to program the source B index and source C index.<p>
-SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each array in the 2nd dimension. Valid values for SRCBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-synchronized and AB-synchronized transfers.<p>
-SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the 3rd dimension. Valid values for SRCCIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in an AB-synchronized transfer is the first array in the frame.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>DMA source index setup. </p>
+<p>It is used to program the source B index and source C index.</p>
+<p>SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each array in the 2nd dimension. Valid values for SRCBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-synchronized and AB-synchronized transfers.</p>
+<p>SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the 3rd dimension. Valid values for SRCCIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in an AB-synchronized transfer is the first array in the frame.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel for which source indices are to be configured </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>srcBIdx</em>&nbsp;</td><td>[IN] Source B index </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>srcCIdx</em>&nbsp;</td><td>[IN] Source C index</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g4e7ec3c58f498bdbac7a507e0cba6221"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setDestIndex" ref="g4e7ec3c58f498bdbac7a507e0cba6221" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)" -->
+</div>
+<a class="anchor" id="ga4e7ec3c58f498bdbac7a507e0cba6221"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setDestIndex" ref="ga4e7ec3c58f498bdbac7a507e0cba6221" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setDestIndex           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setDestIndex </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -578,37 +594,36 @@ SRCCIDX is a 16-bit signed value (2s complement) used for source address modific
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-DMA destination index setup. 
-<p>
-It is used to program the destination B index and destination C index.<p>
-DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between each array in the 2nd dimension. Valid values for DSTBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-synchronized and AB-synchronized transfers.<p>
-DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the 3rd dimension. Valid values are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in a AB-synchronized transfer is the first array in the frame<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>DMA destination index setup. </p>
+<p>It is used to program the destination B index and destination C index.</p>
+<p>DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between each array in the 2nd dimension. Valid values for DSTBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-synchronized and AB-synchronized transfers.</p>
+<p>DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the 3rd dimension. Valid values are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in a AB-synchronized transfer is the first array in the frame</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel for which dest indices are to be configured </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>destBIdx</em>&nbsp;</td><td>[IN] Destination B index </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>destCIdx</em>&nbsp;</td><td>[IN] Destination C index</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g8e54f2e2e016bc557ed3374eb46d62ee"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setTransferParams" ref="g8e54f2e2e016bc557ed3374eb46d62ee" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, EDMA3_DRV_SyncType syncType)" -->
+</div>
+<a class="anchor" id="ga8e54f2e2e016bc557ed3374eb46d62ee"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setTransferParams" ref="ga8e54f2e2e016bc557ed3374eb46d62ee" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, EDMA3_DRV_SyncType syncType)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setTransferParams           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_setTransferParams </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -646,27 +661,25 @@ DSTCIDX is a 16-bit signed value (2s complement) used for destination address mo
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g1cc0705e142298a424a312034bd3b2c2">EDMA3_DRV_SyncType</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga1cc0705e142298a424a312034bd3b2c2">EDMA3_DRV_SyncType</a>&nbsp;</td>
           <td class="paramname"> <em>syncType</em></td><td>&nbsp;</td>
         </tr>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-DMA transfer parameters setup. 
-<p>
-It is used to specify the various counts (ACNT, BCNT and CCNT), B count reload and the synchronization type<p>
-ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to EDMA3 Transfer Controller. An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.<p>
-BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT are between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays). A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.<p>
-CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. A CCNT value of 0 is considered either a null or dummy transfer.<p>
-BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>DMA transfer parameters setup. </p>
+<p>It is used to specify the various counts (ACNT, BCNT and CCNT), B count reload and the synchronization type</p>
+<p>ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to EDMA3 Transfer Controller. An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.</p>
+<p>BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT are between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays). A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.</p>
+<p>CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. A CCNT value of 0 is considered either a null or dummy transfer.</p>
+<p>BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Logical Channel for which transfer parameters are to be configured </td></tr>
@@ -676,18 +689,19 @@ BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last a
     <tr><td valign="top"></td><td valign="top"><em>bCntReload</em>&nbsp;</td><td>[IN] Reload value for bCnt. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>syncType</em>&nbsp;</td><td>[IN] Transfer synchronization dimension 0: A-synchronized. Each event triggers the transfer of a single array of ACNT bytes. 1: AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g5c80afa7645f1e492951c0419c21dbe6"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_enableTransfer" ref="g5c80afa7645f1e492951c0419c21dbe6" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
+</div>
+<a class="anchor" id="ga5c80afa7645f1e492951c0419c21dbe6"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_enableTransfer" ref="ga5c80afa7645f1e492951c0419c21dbe6" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_enableTransfer           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_enableTransfer </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -701,43 +715,42 @@ BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last a
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a>&nbsp;</td>
           <td class="paramname"> <em>trigMode</em></td><td>&nbsp;</td>
         </tr>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Start EDMA transfer on the specified channel. 
-<p>
-There are multiple ways to trigger an EDMA3 transfer. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.<p>
-In event triggered, a peripheral or an externally generated event triggers the transfer. This API clears the Secondary Event Register and Event Miss Register and then enables the DMA channel by writing to the EESR.<p>
-In manual triggered mode, CPU manually triggers a transfer by writing a 1 in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to start the transfer.<p>
-In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). This API enables the QDMA channel by writing to the QEESR register.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Start EDMA transfer on the specified channel. </p>
+<p>There are multiple ways to trigger an EDMA3 transfer. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.</p>
+<p>In event triggered, a peripheral or an externally generated event triggers the transfer. This API clears the Secondary Event Register and Event Miss Register and then enables the DMA channel by writing to the EESR.</p>
+<p>In manual triggered mode, CPU manually triggers a transfer by writing a 1 in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to start the transfer.</p>
+<p>In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). This API enables the QDMA channel by writing to the QEESR register.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Channel on which transfer has to be started </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>trigMode</em>&nbsp;</td><td>[IN] Mode of triggering start of transfer (Manual, QDMA or Event)</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="gdb56f2a6d896c03a77f14c8fdf57a397"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_disableTransfer" ref="gdb56f2a6d896c03a77f14c8fdf57a397" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
+</div>
+<a class="anchor" id="gadb56f2a6d896c03a77f14c8fdf57a397"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_disableTransfer" ref="gadb56f2a6d896c03a77f14c8fdf57a397" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_disableTransfer           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_disableTransfer </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -751,43 +764,42 @@ In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other EDMA3
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a>&nbsp;</td>
           <td class="paramname"> <em>trigMode</em></td><td>&nbsp;</td>
         </tr>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Disable DMA transfer on the specified channel. 
-<p>
-There are multiple ways by which an EDMA3 transfer could be triggered. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.<p>
-To disable a channel which was previously triggered in manual mode, this API clears the Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.<p>
-To disable a channel which was previously triggered in QDMA mode, this API clears the QDMA Event Enable Register, for the specific QDMA channel.<p>
-To disable a channel which was previously triggered in event mode, this API clears the Event Enable Register. It also clears Event Register, Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Disable DMA transfer on the specified channel. </p>
+<p>There are multiple ways by which an EDMA3 transfer could be triggered. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.</p>
+<p>To disable a channel which was previously triggered in manual mode, this API clears the Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.</p>
+<p>To disable a channel which was previously triggered in QDMA mode, this API clears the QDMA Event Enable Register, for the specific QDMA channel.</p>
+<p>To disable a channel which was previously triggered in event mode, this API clears the Event Enable Register. It also clears Event Register, Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] Channel on which transfer has to be stopped </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>trigMode</em>&nbsp;</td><td>[IN] Mode of triggering start of transfer</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g11070a2e9fb80e16fe96e8ad210e0b59"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_disableLogicalChannel" ref="g11070a2e9fb80e16fe96e8ad210e0b59" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
+</div>
+<a class="anchor" id="ga11070a2e9fb80e16fe96e8ad210e0b59"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_disableLogicalChannel" ref="ga11070a2e9fb80e16fe96e8ad210e0b59" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -801,38 +813,37 @@ To disable a channel which was previously triggered in event mode, this API clea
         <tr>
           <td class="paramkey"></td>
           <td></td>
-          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a>&nbsp;</td>
+          <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a>&nbsp;</td>
           <td class="paramname"> <em>trigMode</em></td><td>&nbsp;</td>
         </tr>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Disable the event driven DMA channel or QDMA channel. 
-<p>
-This API disables the DMA channel (which was previously triggered in event mode) by clearing the Event Enable Register; it disables the QDMA channel by clearing the QDMA Event Enable Register.<p>
-This API should NOT be used for DMA channels which are not mapped to any hardware events and are used for memory-to-memory copy based transfers. In case of that, this API returns error.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Disable the event driven DMA channel or QDMA channel. </p>
+<p>This API disables the DMA channel (which was previously triggered in event mode) by clearing the Event Enable Register; it disables the QDMA channel by clearing the QDMA Event Enable Register.</p>
+<p>This API should NOT be used for DMA channels which are not mapped to any hardware events and are used for memory-to-memory copy based transfers. In case of that, this API returns error.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the EDMA Driver Instance </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>lCh</em>&nbsp;</td><td>[IN] DMA/QDMA Channel which needs to be disabled </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>trigMode</em>&nbsp;</td><td>[IN] Mode of triggering start of transfer</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error Code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value. </dd></dl>
 
 </div>
-</div><p>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:42 2010 for EDMA3 Driver by&nbsp;
+</div>
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index 41897fa3b107af259f1b45d9b6fbe3895f149424..1b9b73105ca7ee749766b408bb15b399883303ac 100755 (executable)
@@ -1,46 +1,44 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: EDMA3 Driver Initialization APIs</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
 </div>
 <div class="contents">
-<h1>EDMA3 Driver Initialization APIs<br>
+<h1>EDMA3 Driver Initialization APIs<br/>
 <small>
 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html">EDMA3 Driver APIs</a>]</small>
 </h1><table border="0" cellpadding="0" cellspacing="0">
-<tr><td></td></tr>
-<tr><td colspan="2"><br><h2>Functions</h2></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#gfc4627bdc96b1720a9d69c694688b20c">EDMA3_DRV_create</a> (unsigned int phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a> *gblCfgParams, const void *miscParam)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Create EDMA3 Driver Object.  <a href="#gfc4627bdc96b1720a9d69c694688b20c"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#g1eccca6dee0e5a05fa845c51df24e97d">EDMA3_DRV_delete</a> (unsigned int phyCtrllerInstId, const void *param)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Delete EDMA3 Driver Object.  <a href="#g1eccca6dee0e5a05fa845c51df24e97d"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Handle&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#gfd80c545b7e21f770743c5cb87fd6351">EDMA3_DRV_open</a> (unsigned int phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html">EDMA3_DRV_InitConfig</a> *initCfg, EDMA3_DRV_Result *errorCode)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Open EDMA3 Driver Instance.  <a href="#gfd80c545b7e21f770743c5cb87fd6351"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#g2e0ec2776dcf873bd49e7af3b9c85f0d">EDMA3_DRV_close</a> (EDMA3_DRV_Handle hEdma, const void *param)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Close the EDMA3 Driver Instance.  <a href="#g2e0ec2776dcf873bd49e7af3b9c85f0d"></a><br></td></tr>
+<tr><td colspan="2"><h2>Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#gafc4627bdc96b1720a9d69c694688b20c">EDMA3_DRV_create</a> (unsigned int phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a> *gblCfgParams, const void *miscParam)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Create EDMA3 Driver Object.  <a href="#gafc4627bdc96b1720a9d69c694688b20c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#ga1eccca6dee0e5a05fa845c51df24e97d">EDMA3_DRV_delete</a> (unsigned int phyCtrllerInstId, const void *param)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Delete EDMA3 Driver Object.  <a href="#ga1eccca6dee0e5a05fa845c51df24e97d"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Handle&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#gafd80c545b7e21f770743c5cb87fd6351">EDMA3_DRV_open</a> (unsigned int phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html">EDMA3_DRV_InitConfig</a> *initCfg, EDMA3_DRV_Result *errorCode)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Open EDMA3 Driver Instance.  <a href="#gafd80c545b7e21f770743c5cb87fd6351"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#ga2e0ec2776dcf873bd49e7af3b9c85f0d">EDMA3_DRV_close</a> (EDMA3_DRV_Handle hEdma, const void *param)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Close the EDMA3 Driver Instance.  <a href="#ga2e0ec2776dcf873bd49e7af3b9c85f0d"></a><br/></td></tr>
 </table>
-<hr><h2>Function Documentation</h2>
-<a class="anchor" name="gfc4627bdc96b1720a9d69c694688b20c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_create" ref="gfc4627bdc96b1720a9d69c694688b20c" args="(unsigned int phyCtrllerInstId, const EDMA3_DRV_GblConfigParams *gblCfgParams, const void *miscParam)" -->
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="gafc4627bdc96b1720a9d69c694688b20c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_create" ref="gafc4627bdc96b1720a9d69c694688b20c" args="(unsigned int phyCtrllerInstId, const EDMA3_DRV_GblConfigParams *gblCfgParams, const void *miscParam)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_create           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_create </td>
           <td>(</td>
           <td class="paramtype">unsigned int&nbsp;</td>
           <td class="paramname"> <em>phyCtrllerInstId</em>, </td>
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Create EDMA3 Driver Object. 
-<p>
-This API is used to create the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance.<p>
-Init-time Configuration structure for EDMA3 hardware is provided to pass the SoC specific information. This configuration information could be provided by the user at init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_&lt;SOC_NAME&gt;_cfg.c, in case it is available.<p>
-This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' argument is NULL. User can avoid these registers' programming (in some specific use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration structure and passing this structure as the third argument (miscParam).<p>
-After successful completion of this API, Driver Object's state changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELETED.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Create EDMA3 Driver Object. </p>
+<p>This API is used to create the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance.</p>
+<p>Init-time Configuration structure for EDMA3 hardware is provided to pass the SoC specific information. This configuration information could be provided by the user at init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_&lt;SOC_NAME&gt;_cfg.c, in case it is available.</p>
+<p>This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' argument is NULL. User can avoid these registers' programming (in some specific use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration structure and passing this structure as the third argument (miscParam).</p>
+<p>After successful completion of this API, Driver Object's state changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELETED.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>phyCtrllerInstId</em>&nbsp;</td><td>[IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>gblCfgParams</em>&nbsp;</td><td>[IN] SoC specific configuration structure for the EDMA3 Hardware. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>miscParam</em>&nbsp;</td><td>[IN] Misc configuration options provided in the structure 'EDMA3_DRV_MiscParam'. For default options, user can pass NULL in this argument.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g1eccca6dee0e5a05fa845c51df24e97d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_delete" ref="g1eccca6dee0e5a05fa845c51df24e97d" args="(unsigned int phyCtrllerInstId, const void *param)" -->
+</div>
+<a class="anchor" id="ga1eccca6dee0e5a05fa845c51df24e97d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_delete" ref="ga1eccca6dee0e5a05fa845c51df24e97d" args="(unsigned int phyCtrllerInstId, const void *param)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_delete           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_delete </td>
           <td>(</td>
           <td class="paramtype">unsigned int&nbsp;</td>
           <td class="paramname"> <em>phyCtrllerInstId</em>, </td>
@@ -103,34 +100,33 @@ After successful completion of this API, Driver Object's state changes to EDMA3_
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Delete EDMA3 Driver Object. 
-<p>
-Use this API to delete the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance. It should be called ONLY after closing all the EDMA3 Driver Instances.<p>
-This API is used to delete the EDMA3 Driver Object. It should be called once for each EDMA3 hardware instance, ONLY after closing all the previously opened EDMA3 Driver Instances.<p>
-After successful completion of this API, Driver Object's state changes to EDMA3_DRV_DELETED.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Delete EDMA3 Driver Object. </p>
+<p>Use this API to delete the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance. It should be called ONLY after closing all the EDMA3 Driver Instances.</p>
+<p>This API is used to delete the EDMA3 Driver Object. It should be called once for each EDMA3 hardware instance, ONLY after closing all the previously opened EDMA3 Driver Instances.</p>
+<p>After successful completion of this API, Driver Object's state changes to EDMA3_DRV_DELETED.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>phyCtrllerInstId</em>&nbsp;</td><td>[IN] EDMA3 Phy Controller Instance Id (Hardware instance id, starting from 0). </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>param</em>&nbsp;</td><td>[IN] For possible future use.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="gfd80c545b7e21f770743c5cb87fd6351"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_open" ref="gfd80c545b7e21f770743c5cb87fd6351" args="(unsigned int phyCtrllerInstId, const EDMA3_DRV_InitConfig *initCfg, EDMA3_DRV_Result *errorCode)" -->
+</div>
+<a class="anchor" id="gafd80c545b7e21f770743c5cb87fd6351"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_open" ref="gafd80c545b7e21f770743c5cb87fd6351" args="(unsigned int phyCtrllerInstId, const EDMA3_DRV_InitConfig *initCfg, EDMA3_DRV_Result *errorCode)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Handle EDMA3_DRV_open           </td>
+          <td class="memname">EDMA3_DRV_Handle EDMA3_DRV_open </td>
           <td>(</td>
           <td class="paramtype">unsigned int&nbsp;</td>
           <td class="paramname"> <em>phyCtrllerInstId</em>, </td>
@@ -150,37 +146,36 @@ After successful completion of this API, Driver Object's state changes to EDMA3_
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Open EDMA3 Driver Instance. 
-<p>
-This API is used to open an EDMA3 Driver Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware instance. Multiple instances on the same shadow region are NOT allowed.<p>
-Also, only ONE Master Driver Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled.<p>
-User could pass the instance specific configuration structure (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_&lt;SOC_NAME&gt;_cfg.c, in case it is available.<p>
-By default, this EDMA3 Driver instance will clear the PaRAM Sets while allocating them. To change the default behavior, user should use the IOCTL interface appropriately.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Open EDMA3 Driver Instance. </p>
+<p>This API is used to open an EDMA3 Driver Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware instance. Multiple instances on the same shadow region are NOT allowed.</p>
+<p>Also, only ONE Master Driver Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled.</p>
+<p>User could pass the instance specific configuration structure (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_&lt;SOC_NAME&gt;_cfg.c, in case it is available.</p>
+<p>By default, this EDMA3 Driver instance will clear the PaRAM Sets while allocating them. To change the default behavior, user should use the IOCTL interface appropriately.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>phyCtrllerInstId</em>&nbsp;</td><td>[IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>initCfg</em>&nbsp;</td><td>[IN] Used to Initialize the EDMA3 Driver Instance (Master or Slave). </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>errorCode</em>&nbsp;</td><td>[OUT] Error code while opening DRV instance.</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_Handle : If successfully opened, the API will return the associated driver's instance handle.</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_Handle : If successfully opened, the API will return the associated driver's instance handle.</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant. </dd></dl>
 
 </div>
-</div><p>
-<a class="anchor" name="g2e0ec2776dcf873bd49e7af3b9c85f0d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_close" ref="g2e0ec2776dcf873bd49e7af3b9c85f0d" args="(EDMA3_DRV_Handle hEdma, const void *param)" -->
+</div>
+<a class="anchor" id="ga2e0ec2776dcf873bd49e7af3b9c85f0d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_close" ref="ga2e0ec2776dcf873bd49e7af3b9c85f0d" args="(EDMA3_DRV_Handle hEdma, const void *param)" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_close           </td>
+          <td class="memname">EDMA3_DRV_Result EDMA3_DRV_close </td>
           <td>(</td>
           <td class="paramtype">EDMA3_DRV_Handle&nbsp;</td>
           <td class="paramname"> <em>hEdma</em>, </td>
@@ -194,30 +189,29 @@ By default, this EDMA3 Driver instance will clear the PaRAM Sets while allocatin
         <tr>
           <td></td>
           <td>)</td>
-          <td></td><td></td><td width="100%"></td>
+          <td></td><td></td><td></td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Close the EDMA3 Driver Instance. 
-<p>
-This API is used to close a previously opened EDMA3 Driver Instance.<p>
-<dl compact><dt><b>Parameters:</b></dt><dd>
+<p>Close the EDMA3 Driver Instance. </p>
+<p>This API is used to close a previously opened EDMA3 Driver Instance.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
   <table border="0" cellspacing="2" cellpadding="0">
     <tr><td valign="top"></td><td valign="top"><em>hEdma</em>&nbsp;</td><td>[IN] Handle to the previously opened EDMA3 Driver Instance. </td></tr>
     <tr><td valign="top"></td><td valign="top"><em>param</em>&nbsp;</td><td>[IN] For possible future use</td></tr>
   </table>
+  </dd>
 </dl>
-<dl class="return" compact><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
-<dl class="note" compact><dt><b>Note:</b></dt><dd>This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>EDMA3_DRV_SOK or EDMA3_DRV Error code</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant. </dd></dl>
 
 </div>
-</div><p>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:42 2010 for EDMA3 Driver by&nbsp;
+</div>
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index dfd74fed2ca6e1f7c04f6a1c845ae07c51d155b9..6d67c0074483693aabe907c23ef8c80deb54ada9 100755 (executable)
@@ -1,34 +1,34 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: EDMA3 Driver Symbols</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
 </div>
 <div class="contents">
-<h1>EDMA3 Driver Symbols<br>
+<h1>EDMA3 Driver Symbols<br/>
 <small>
 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___a_p_i.html">EDMA3 Driver</a>]</small>
 </h1><table border="0" cellpadding="0" cellspacing="0">
-<tr><td></td></tr>
-<tr><td colspan="2"><br><h2>Modules</h2></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html">EDMA3 Driver Defines</a></td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html">EDMA3 Driver Enums</a></td></tr>
-
+<tr><td colspan="2"><h2>Modules</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html">EDMA3 Driver Defines</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html">EDMA3 Driver Enums</a></td></tr>
 </table>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:41 2010 for EDMA3 Driver by&nbsp;
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index f113a649d398eb1b4e870b2190ad73d0b97e7fac..ebf948ceb9d99b3614d8915474b0ab722f81d43f 100755 (executable)
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: EDMA3 Driver Defines</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
 </div>
 <div class="contents">
-<h1>EDMA3 Driver Defines<br>
+<h1>EDMA3 Driver Defines<br/>
 <small>
 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l.html">EDMA3 Driver Symbols</a>]</small>
 </h1><table border="0" cellpadding="0" cellspacing="0">
-<tr><td></td></tr>
-<tr><td colspan="2"><br><h2>Defines</h2></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top"><a class="anchor" name="g1c61cf487147fe68e224d1c123a8b9a0"></a><!-- doxytag: member="EDMA3_LLD_DRV_SYMBOL_DEFINE::EDMA3_DRV_E_BASE" ref="g1c61cf487147fe68e224d1c123a8b9a0" args="" -->
-#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g1c61cf487147fe68e224d1c123a8b9a0">EDMA3_DRV_E_BASE</a>&nbsp;&nbsp;&nbsp;(-128)</td></tr>
-
-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 Driver Error Codes Base define. <br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g2108add0c34a15aae6431e3770ab42dd">EDMA3_DRV_E_OBJ_NOT_DELETED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g571264a50142765bf93790095a628262">EDMA3_DRV_E_OBJ_NOT_CLOSED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-1)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gaa89161057219a701a298204ac3cd827">EDMA3_DRV_E_OBJ_NOT_OPENED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-2)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g7e5b89ad3e356f24adf2ce48a550d96c">EDMA3_DRV_E_RM_CLOSE_FAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-3)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g962a29d0b4af2e62ecf27bab146ad1c5">EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-4)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g2d8b8e068288390cb892d66f8634e4e9">EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-5)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g6dca1e3db587cd849bec8d25cc7949c3">EDMA3_DRV_E_PARAM_SET_UNAVAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-6)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga2d5c5345b0d44d9d3f066168f25cc0a">EDMA3_DRV_E_TCC_UNAVAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-7)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g3a23afbe20784bfbb37df06110d6df47">EDMA3_DRV_E_TCC_REGISTER_FAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-8)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g64926c19c48a9ff8467aa202c466708d">EDMA3_DRV_E_CH_PARAM_BIND_FAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-9)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g6b09cbce9ece5d6b43a0921a8e1cb475">EDMA3_DRV_E_ADDRESS_NOT_ALIGNED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-10)</td></tr>
-
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g6a52829f2849eae65a02e52fbefc65f4">EDMA3_DRV_E_INVALID_PARAM</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-11)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gd8e918ccf5e108e48762ce6d07abc3bd">EDMA3_DRV_E_INVALID_STATE</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-12)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g0592531d6026c0f66b68b8df995ce42a">EDMA3_DRV_E_INST_ALREADY_EXISTS</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-13)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g5efab7f94c820d6b7f15d9e974629fde">EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-14)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g71414464e3ad2e83a022c11d61b5160d">EDMA3_DRV_E_SEMAPHORE</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-15)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g8bb0d23bee588175080a0e5ee8bb037c">EDMA3_DRV_E_INST_NOT_OPENED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-16)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g492616b5ce939ae81e6dcabd4cf5a405">EDMA3_DRV_CH_NO_PARAM_MAP</a>&nbsp;&nbsp;&nbsp;EDMA3_RM_CH_NO_PARAM_MAP</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g404a225fe0e3f78170bac637568b89fe">EDMA3_DRV_CH_NO_TCC_MAP</a>&nbsp;&nbsp;&nbsp;EDMA3_RM_CH_NO_TCC_MAP</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g3f215945183f3d9fc88453c259fa4b7e">EDMA3_DRV_DMA_CHANNEL_ANY</a>&nbsp;&nbsp;&nbsp;1002u</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g48cab1397b2fff89e09b9b1e21b499bd">EDMA3_DRV_QDMA_CHANNEL_ANY</a>&nbsp;&nbsp;&nbsp;1003u</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g72dbba10987168632d1994a98e3b497b">EDMA3_DRV_TCC_ANY</a>&nbsp;&nbsp;&nbsp;1004u</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gc0d22d1bdbb6ee2bd6aa269429486375">EDMA3_DRV_LINK_CHANNEL</a>&nbsp;&nbsp;&nbsp;1005u</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gf8efda8c9a32c28976c682d6480c976f">EDMA3_DRV_LINK_CHANNEL_WITH_TCC</a>&nbsp;&nbsp;&nbsp;1006u</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ged8a176b1257cdc385c940a1a9a84107">EDMA3_DRV_QDMA_CHANNEL_0</a>&nbsp;&nbsp;&nbsp;(EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)</td></tr>
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-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">QDMA Channel defines.  <a href="#ged8a176b1257cdc385c940a1a9a84107"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g926b824823dfc5263108ee41eb6110d0">EDMA3_DRV_QDMA_CHANNEL_1</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+1u)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g41b662ac932dfcddef137609a2bd3ad4">EDMA3_DRV_QDMA_CHANNEL_2</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+2u)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ge97e0af735749d8ab8985dbd738eb578">EDMA3_DRV_QDMA_CHANNEL_3</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+3u)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g1c11bab1b40c683b59c4801962cc6046">EDMA3_DRV_QDMA_CHANNEL_4</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+4u)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g7d6c63e3a6da083430afd94578f4bd84">EDMA3_DRV_QDMA_CHANNEL_5</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+5u)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gc52b4731852ac8dac2f824fe0bdd153c">EDMA3_DRV_QDMA_CHANNEL_6</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+6u)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gfc951e66232fc729344802c3abf6218b">EDMA3_DRV_QDMA_CHANNEL_7</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+7u)</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g2ca0c95ae69ae4cc71cc8137287a8fd1">EDMA3_DRV_CHANNEL_CLEAN</a>&nbsp;&nbsp;&nbsp;0x0000u</td></tr>
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-<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g85bad51ec992ce36ed7f28842b7d8219" title="Get the current status of the DMA/QDMA channel.">EDMA3_DRV_getChannelStatus()</a>.  <a href="#g2ca0c95ae69ae4cc71cc8137287a8fd1"></a><br></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g4b4982df7c3844ea394c9bb743fdf558">EDMA3_DRV_CHANNEL_EVENT_PENDING</a>&nbsp;&nbsp;&nbsp;0x0001u</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#g80c785afc213172fda74b14c59946480">EDMA3_DRV_CHANNEL_XFER_COMPLETE</a>&nbsp;&nbsp;&nbsp;0x0002u</td></tr>
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-<tr><td class="memItemLeft" nowrap align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gb4cc61240f1e9a3f69c602c0ede9553b">EDMA3_DRV_CHANNEL_ERR</a>&nbsp;&nbsp;&nbsp;0x0004u</td></tr>
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+<tr><td colspan="2"><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1c61cf487147fe68e224d1c123a8b9a0"></a><!-- doxytag: member="EDMA3_LLD_DRV_SYMBOL_DEFINE::EDMA3_DRV_E_BASE" ref="ga1c61cf487147fe68e224d1c123a8b9a0" args="" -->
+#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga1c61cf487147fe68e224d1c123a8b9a0">EDMA3_DRV_E_BASE</a>&nbsp;&nbsp;&nbsp;(-128)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">EDMA3 Driver Error Codes Base define. <br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga2108add0c34a15aae6431e3770ab42dd">EDMA3_DRV_E_OBJ_NOT_DELETED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga571264a50142765bf93790095a628262">EDMA3_DRV_E_OBJ_NOT_CLOSED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-1)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gaaa89161057219a701a298204ac3cd827">EDMA3_DRV_E_OBJ_NOT_OPENED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-2)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga7e5b89ad3e356f24adf2ce48a550d96c">EDMA3_DRV_E_RM_CLOSE_FAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-3)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga962a29d0b4af2e62ecf27bab146ad1c5">EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-4)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga2d8b8e068288390cb892d66f8634e4e9">EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-5)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga6dca1e3db587cd849bec8d25cc7949c3">EDMA3_DRV_E_PARAM_SET_UNAVAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-6)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gaa2d5c5345b0d44d9d3f066168f25cc0a">EDMA3_DRV_E_TCC_UNAVAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-7)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga3a23afbe20784bfbb37df06110d6df47">EDMA3_DRV_E_TCC_REGISTER_FAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-8)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga64926c19c48a9ff8467aa202c466708d">EDMA3_DRV_E_CH_PARAM_BIND_FAIL</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-9)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga6b09cbce9ece5d6b43a0921a8e1cb475">EDMA3_DRV_E_ADDRESS_NOT_ALIGNED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-10)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga6a52829f2849eae65a02e52fbefc65f4">EDMA3_DRV_E_INVALID_PARAM</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-11)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gad8e918ccf5e108e48762ce6d07abc3bd">EDMA3_DRV_E_INVALID_STATE</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-12)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga0592531d6026c0f66b68b8df995ce42a">EDMA3_DRV_E_INST_ALREADY_EXISTS</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-13)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga5efab7f94c820d6b7f15d9e974629fde">EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-14)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga71414464e3ad2e83a022c11d61b5160d">EDMA3_DRV_E_SEMAPHORE</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-15)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga8bb0d23bee588175080a0e5ee8bb037c">EDMA3_DRV_E_INST_NOT_OPENED</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-16)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga492616b5ce939ae81e6dcabd4cf5a405">EDMA3_DRV_CH_NO_PARAM_MAP</a>&nbsp;&nbsp;&nbsp;EDMA3_RM_CH_NO_PARAM_MAP</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga404a225fe0e3f78170bac637568b89fe">EDMA3_DRV_CH_NO_TCC_MAP</a>&nbsp;&nbsp;&nbsp;EDMA3_RM_CH_NO_TCC_MAP</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga3f215945183f3d9fc88453c259fa4b7e">EDMA3_DRV_DMA_CHANNEL_ANY</a>&nbsp;&nbsp;&nbsp;1002u</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga48cab1397b2fff89e09b9b1e21b499bd">EDMA3_DRV_QDMA_CHANNEL_ANY</a>&nbsp;&nbsp;&nbsp;1003u</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga72dbba10987168632d1994a98e3b497b">EDMA3_DRV_TCC_ANY</a>&nbsp;&nbsp;&nbsp;1004u</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gac0d22d1bdbb6ee2bd6aa269429486375">EDMA3_DRV_LINK_CHANNEL</a>&nbsp;&nbsp;&nbsp;1005u</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gaf8efda8c9a32c28976c682d6480c976f">EDMA3_DRV_LINK_CHANNEL_WITH_TCC</a>&nbsp;&nbsp;&nbsp;1006u</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gaed8a176b1257cdc385c940a1a9a84107">EDMA3_DRV_QDMA_CHANNEL_0</a>&nbsp;&nbsp;&nbsp;(EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">QDMA Channel defines.  <a href="#gaed8a176b1257cdc385c940a1a9a84107"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga926b824823dfc5263108ee41eb6110d0">EDMA3_DRV_QDMA_CHANNEL_1</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+1u)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga41b662ac932dfcddef137609a2bd3ad4">EDMA3_DRV_QDMA_CHANNEL_2</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+2u)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gae97e0af735749d8ab8985dbd738eb578">EDMA3_DRV_QDMA_CHANNEL_3</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+3u)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga1c11bab1b40c683b59c4801962cc6046">EDMA3_DRV_QDMA_CHANNEL_4</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+4u)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga7d6c63e3a6da083430afd94578f4bd84">EDMA3_DRV_QDMA_CHANNEL_5</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+5u)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gac52b4731852ac8dac2f824fe0bdd153c">EDMA3_DRV_QDMA_CHANNEL_6</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+6u)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gafc951e66232fc729344802c3abf6218b">EDMA3_DRV_QDMA_CHANNEL_7</a>&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+7u)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga2ca0c95ae69ae4cc71cc8137287a8fd1">EDMA3_DRV_CHANNEL_CLEAN</a>&nbsp;&nbsp;&nbsp;0x0000u</td></tr>
+<tr><td class="mdescLeft">&nbsp;</td><td class="mdescRight">Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga85bad51ec992ce36ed7f28842b7d8219" title="Get the current status of the DMA/QDMA channel.">EDMA3_DRV_getChannelStatus()</a>.  <a href="#ga2ca0c95ae69ae4cc71cc8137287a8fd1"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga4b4982df7c3844ea394c9bb743fdf558">EDMA3_DRV_CHANNEL_EVENT_PENDING</a>&nbsp;&nbsp;&nbsp;0x0001u</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga80c785afc213172fda74b14c59946480">EDMA3_DRV_CHANNEL_XFER_COMPLETE</a>&nbsp;&nbsp;&nbsp;0x0002u</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gab4cc61240f1e9a3f69c602c0ede9553b">EDMA3_DRV_CHANNEL_ERR</a>&nbsp;&nbsp;&nbsp;0x0004u</td></tr>
 </table>
-<hr><h2>Define Documentation</h2>
-<a class="anchor" name="g2108add0c34a15aae6431e3770ab42dd"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_OBJ_NOT_DELETED" ref="g2108add0c34a15aae6431e3770ab42dd" args="" -->
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="ga2108add0c34a15aae6431e3770ab42dd"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_OBJ_NOT_DELETED" ref="ga2108add0c34a15aae6431e3770ab42dd" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_OBJ_NOT_DELETED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE)          </td>
+          <td class="memname">#define EDMA3_DRV_E_OBJ_NOT_DELETED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>EDMA3 Driver Object Not Deleted yet. So it cannot be created. </p>
 
-<p>
-EDMA3 Driver Object Not Deleted yet. So it cannot be created. 
 </div>
-</div><p>
-<a class="anchor" name="g571264a50142765bf93790095a628262"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_OBJ_NOT_CLOSED" ref="g571264a50142765bf93790095a628262" args="" -->
+</div>
+<a class="anchor" id="ga571264a50142765bf93790095a628262"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_OBJ_NOT_CLOSED" ref="ga571264a50142765bf93790095a628262" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_OBJ_NOT_CLOSED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-1)          </td>
+          <td class="memname">#define EDMA3_DRV_E_OBJ_NOT_CLOSED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-1)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>EDMA3 Driver Object Not Closed yet. So it cannot be deleted. </p>
 
-<p>
-EDMA3 Driver Object Not Closed yet. So it cannot be deleted. 
 </div>
-</div><p>
-<a class="anchor" name="gaa89161057219a701a298204ac3cd827"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_OBJ_NOT_OPENED" ref="gaa89161057219a701a298204ac3cd827" args="" -->
+</div>
+<a class="anchor" id="gaaa89161057219a701a298204ac3cd827"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_OBJ_NOT_OPENED" ref="gaaa89161057219a701a298204ac3cd827" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_OBJ_NOT_OPENED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-2)          </td>
+          <td class="memname">#define EDMA3_DRV_E_OBJ_NOT_OPENED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-2)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>EDMA3 Driver Object Not Opened yet So it cannot be closed. </p>
 
-<p>
-EDMA3 Driver Object Not Opened yet So it cannot be closed. 
 </div>
-</div><p>
-<a class="anchor" name="g7e5b89ad3e356f24adf2ce48a550d96c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_RM_CLOSE_FAIL" ref="g7e5b89ad3e356f24adf2ce48a550d96c" args="" -->
+</div>
+<a class="anchor" id="ga7e5b89ad3e356f24adf2ce48a550d96c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_RM_CLOSE_FAIL" ref="ga7e5b89ad3e356f24adf2ce48a550d96c" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_RM_CLOSE_FAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-3)          </td>
+          <td class="memname">#define EDMA3_DRV_E_RM_CLOSE_FAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-3)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>While closing EDMA3 Driver, Resource Manager Close Failed. </p>
 
-<p>
-While closing EDMA3 Driver, Resource Manager Close Failed. 
 </div>
-</div><p>
-<a class="anchor" name="g962a29d0b4af2e62ecf27bab146ad1c5"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL" ref="g962a29d0b4af2e62ecf27bab146ad1c5" args="" -->
+</div>
+<a class="anchor" id="ga962a29d0b4af2e62ecf27bab146ad1c5"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL" ref="ga962a29d0b4af2e62ecf27bab146ad1c5" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-4)          </td>
+          <td class="memname">#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-4)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>The requested DMA Channel not available </p>
 
-<p>
-The requested DMA Channel not available 
 </div>
-</div><p>
-<a class="anchor" name="g2d8b8e068288390cb892d66f8634e4e9"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL" ref="g2d8b8e068288390cb892d66f8634e4e9" args="" -->
+</div>
+<a class="anchor" id="ga2d8b8e068288390cb892d66f8634e4e9"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL" ref="ga2d8b8e068288390cb892d66f8634e4e9" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-5)          </td>
+          <td class="memname">#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-5)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>The requested QDMA Channel not available </p>
 
-<p>
-The requested QDMA Channel not available 
 </div>
-</div><p>
-<a class="anchor" name="g6dca1e3db587cd849bec8d25cc7949c3"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_PARAM_SET_UNAVAIL" ref="g6dca1e3db587cd849bec8d25cc7949c3" args="" -->
+</div>
+<a class="anchor" id="ga6dca1e3db587cd849bec8d25cc7949c3"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_PARAM_SET_UNAVAIL" ref="ga6dca1e3db587cd849bec8d25cc7949c3" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_PARAM_SET_UNAVAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-6)          </td>
+          <td class="memname">#define EDMA3_DRV_E_PARAM_SET_UNAVAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-6)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>The requested PaRAM Set not available </p>
 
-<p>
-The requested PaRAM Set not available 
 </div>
-</div><p>
-<a class="anchor" name="ga2d5c5345b0d44d9d3f066168f25cc0a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_TCC_UNAVAIL" ref="ga2d5c5345b0d44d9d3f066168f25cc0a" args="" -->
+</div>
+<a class="anchor" id="gaa2d5c5345b0d44d9d3f066168f25cc0a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_TCC_UNAVAIL" ref="gaa2d5c5345b0d44d9d3f066168f25cc0a" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_TCC_UNAVAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-7)          </td>
+          <td class="memname">#define EDMA3_DRV_E_TCC_UNAVAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-7)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>The requested TCC not available </p>
 
-<p>
-The requested TCC not available 
 </div>
-</div><p>
-<a class="anchor" name="g3a23afbe20784bfbb37df06110d6df47"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_TCC_REGISTER_FAIL" ref="g3a23afbe20784bfbb37df06110d6df47" args="" -->
+</div>
+<a class="anchor" id="ga3a23afbe20784bfbb37df06110d6df47"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_TCC_REGISTER_FAIL" ref="ga3a23afbe20784bfbb37df06110d6df47" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_TCC_REGISTER_FAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-8)          </td>
+          <td class="memname">#define EDMA3_DRV_E_TCC_REGISTER_FAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-8)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>The registration of TCC failed </p>
 
-<p>
-The registration of TCC failed 
 </div>
-</div><p>
-<a class="anchor" name="g64926c19c48a9ff8467aa202c466708d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_CH_PARAM_BIND_FAIL" ref="g64926c19c48a9ff8467aa202c466708d" args="" -->
+</div>
+<a class="anchor" id="ga64926c19c48a9ff8467aa202c466708d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_CH_PARAM_BIND_FAIL" ref="ga64926c19c48a9ff8467aa202c466708d" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-9)          </td>
+          <td class="memname">#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-9)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>The binding of Channel and PaRAM Set failed </p>
 
-<p>
-The binding of Channel and PaRAM Set failed 
 </div>
-</div><p>
-<a class="anchor" name="g6b09cbce9ece5d6b43a0921a8e1cb475"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_ADDRESS_NOT_ALIGNED" ref="g6b09cbce9ece5d6b43a0921a8e1cb475" args="" -->
+</div>
+<a class="anchor" id="ga6b09cbce9ece5d6b43a0921a8e1cb475"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_ADDRESS_NOT_ALIGNED" ref="ga6b09cbce9ece5d6b43a0921a8e1cb475" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-10)          </td>
+          <td class="memname">#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-10)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>The address of the memory location passed as argument is not properly aligned. It should be 32 bytes aligned. </p>
 
-<p>
-The address of the memory location passed as argument is not properly aligned. It should be 32 bytes aligned. 
 </div>
-</div><p>
-<a class="anchor" name="g6a52829f2849eae65a02e52fbefc65f4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INVALID_PARAM" ref="g6a52829f2849eae65a02e52fbefc65f4" args="" -->
+</div>
+<a class="anchor" id="ga6a52829f2849eae65a02e52fbefc65f4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INVALID_PARAM" ref="ga6a52829f2849eae65a02e52fbefc65f4" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_INVALID_PARAM&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-11)          </td>
+          <td class="memname">#define EDMA3_DRV_E_INVALID_PARAM&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-11)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Invalid Parameter passed to API </p>
 
-<p>
-Invalid Parameter passed to API 
 </div>
-</div><p>
-<a class="anchor" name="gd8e918ccf5e108e48762ce6d07abc3bd"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INVALID_STATE" ref="gd8e918ccf5e108e48762ce6d07abc3bd" args="" -->
+</div>
+<a class="anchor" id="gad8e918ccf5e108e48762ce6d07abc3bd"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INVALID_STATE" ref="gad8e918ccf5e108e48762ce6d07abc3bd" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_INVALID_STATE&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-12)          </td>
+          <td class="memname">#define EDMA3_DRV_E_INVALID_STATE&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-12)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Invalid State of EDMA3 HW Obj </p>
 
-<p>
-Invalid State of EDMA3 HW Obj 
 </div>
-</div><p>
-<a class="anchor" name="g0592531d6026c0f66b68b8df995ce42a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INST_ALREADY_EXISTS" ref="g0592531d6026c0f66b68b8df995ce42a" args="" -->
+</div>
+<a class="anchor" id="ga0592531d6026c0f66b68b8df995ce42a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INST_ALREADY_EXISTS" ref="ga0592531d6026c0f66b68b8df995ce42a" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_INST_ALREADY_EXISTS&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-13)          </td>
+          <td class="memname">#define EDMA3_DRV_E_INST_ALREADY_EXISTS&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-13)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>EDMA3 Driver instance already exists for the specified region </p>
 
-<p>
-EDMA3 Driver instance already exists for the specified region 
 </div>
-</div><p>
-<a class="anchor" name="g5efab7f94c820d6b7f15d9e974629fde"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED" ref="g5efab7f94c820d6b7f15d9e974629fde" args="" -->
+</div>
+<a class="anchor" id="ga5efab7f94c820d6b7f15d9e974629fde"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED" ref="ga5efab7f94c820d6b7f15d9e974629fde" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-14)          </td>
+          <td class="memname">#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-14)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>FIFO width not supported by the requested TC </p>
 
-<p>
-FIFO width not supported by the requested TC 
 </div>
-</div><p>
-<a class="anchor" name="g71414464e3ad2e83a022c11d61b5160d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_SEMAPHORE" ref="g71414464e3ad2e83a022c11d61b5160d" args="" -->
+</div>
+<a class="anchor" id="ga71414464e3ad2e83a022c11d61b5160d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_SEMAPHORE" ref="ga71414464e3ad2e83a022c11d61b5160d" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_SEMAPHORE&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-15)          </td>
+          <td class="memname">#define EDMA3_DRV_E_SEMAPHORE&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-15)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Semaphore related error </p>
 
-<p>
-Semaphore related error 
 </div>
-</div><p>
-<a class="anchor" name="g8bb0d23bee588175080a0e5ee8bb037c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INST_NOT_OPENED" ref="g8bb0d23bee588175080a0e5ee8bb037c" args="" -->
+</div>
+<a class="anchor" id="ga8bb0d23bee588175080a0e5ee8bb037c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_E_INST_NOT_OPENED" ref="ga8bb0d23bee588175080a0e5ee8bb037c" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_E_INST_NOT_OPENED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-16)          </td>
+          <td class="memname">#define EDMA3_DRV_E_INST_NOT_OPENED&nbsp;&nbsp;&nbsp;(EDMA3_DRV_E_BASE-16)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>EDMA3 Driver Instance does not exist, it is not opened yet </p>
 
-<p>
-EDMA3 Driver Instance does not exist, it is not opened yet 
 </div>
-</div><p>
-<a class="anchor" name="g492616b5ce939ae81e6dcabd4cf5a405"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CH_NO_PARAM_MAP" ref="g492616b5ce939ae81e6dcabd4cf5a405" args="" -->
+</div>
+<a class="anchor" id="ga492616b5ce939ae81e6dcabd4cf5a405"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CH_NO_PARAM_MAP" ref="ga492616b5ce939ae81e6dcabd4cf5a405" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_CH_NO_PARAM_MAP&nbsp;&nbsp;&nbsp;EDMA3_RM_CH_NO_PARAM_MAP          </td>
+          <td class="memname">#define EDMA3_DRV_CH_NO_PARAM_MAP&nbsp;&nbsp;&nbsp;EDMA3_RM_CH_NO_PARAM_MAP</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.</p>
+<p>This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets. </p>
 
-<p>
-This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.<p>
-This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets. 
 </div>
-</div><p>
-<a class="anchor" name="g404a225fe0e3f78170bac637568b89fe"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CH_NO_TCC_MAP" ref="g404a225fe0e3f78170bac637568b89fe" args="" -->
+</div>
+<a class="anchor" id="ga404a225fe0e3f78170bac637568b89fe"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CH_NO_TCC_MAP" ref="ga404a225fe0e3f78170bac637568b89fe" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_CH_NO_TCC_MAP&nbsp;&nbsp;&nbsp;EDMA3_RM_CH_NO_TCC_MAP          </td>
+          <td class="memname">#define EDMA3_DRV_CH_NO_TCC_MAP&nbsp;&nbsp;&nbsp;EDMA3_RM_CH_NO_TCC_MAP</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for that DMA/QDMA channel. It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.</p>
+<p>This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs. </p>
 
-<p>
-This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for that DMA/QDMA channel. It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.<p>
-This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs. 
 </div>
-</div><p>
-<a class="anchor" name="g3f215945183f3d9fc88453c259fa4b7e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_DMA_CHANNEL_ANY" ref="g3f215945183f3d9fc88453c259fa4b7e" args="" -->
+</div>
+<a class="anchor" id="ga3f215945183f3d9fc88453c259fa4b7e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_DMA_CHANNEL_ANY" ref="ga3f215945183f3d9fc88453c259fa4b7e" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_DMA_CHANNEL_ANY&nbsp;&nbsp;&nbsp;1002u          </td>
+          <td class="memname">#define EDMA3_DRV_DMA_CHANNEL_ANY&nbsp;&nbsp;&nbsp;1002u</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Used to specify any available DMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. DMA channel from the pool of (owned &amp;&amp; non_reserved &amp;&amp; available_right_now) DMA channels will be chosen and returned. </p>
 
-<p>
-Used to specify any available DMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. DMA channel from the pool of (owned &amp;&amp; non_reserved &amp;&amp; available_right_now) DMA channels will be chosen and returned. 
 </div>
-</div><p>
-<a class="anchor" name="g48cab1397b2fff89e09b9b1e21b499bd"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_ANY" ref="g48cab1397b2fff89e09b9b1e21b499bd" args="" -->
+</div>
+<a class="anchor" id="ga48cab1397b2fff89e09b9b1e21b499bd"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_ANY" ref="ga48cab1397b2fff89e09b9b1e21b499bd" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_ANY&nbsp;&nbsp;&nbsp;1003u          </td>
+          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_ANY&nbsp;&nbsp;&nbsp;1003u</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Used to specify any available QDMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. QDMA channel from the pool of (owned &amp;&amp; non_reserved &amp;&amp; available_right_now) QDMA channels will be chosen and returned. </p>
 
-<p>
-Used to specify any available QDMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. QDMA channel from the pool of (owned &amp;&amp; non_reserved &amp;&amp; available_right_now) QDMA channels will be chosen and returned. 
 </div>
-</div><p>
-<a class="anchor" name="g72dbba10987168632d1994a98e3b497b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_TCC_ANY" ref="g72dbba10987168632d1994a98e3b497b" args="" -->
+</div>
+<a class="anchor" id="ga72dbba10987168632d1994a98e3b497b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_TCC_ANY" ref="ga72dbba10987168632d1994a98e3b497b" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_TCC_ANY&nbsp;&nbsp;&nbsp;1004u          </td>
+          <td class="memname">#define EDMA3_DRV_TCC_ANY&nbsp;&nbsp;&nbsp;1004u</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Used to specify any available TCC while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for both DMA and QDMA channels. TCC from the pool of (owned &amp;&amp; non_reserved &amp;&amp; available_right_now) TCCs will be chosen and returned. </p>
 
-<p>
-Used to specify any available TCC while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for both DMA and QDMA channels. TCC from the pool of (owned &amp;&amp; non_reserved &amp;&amp; available_right_now) TCCs will be chosen and returned. 
 </div>
-</div><p>
-<a class="anchor" name="gc0d22d1bdbb6ee2bd6aa269429486375"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_LINK_CHANNEL" ref="gc0d22d1bdbb6ee2bd6aa269429486375" args="" -->
+</div>
+<a class="anchor" id="gac0d22d1bdbb6ee2bd6aa269429486375"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_LINK_CHANNEL" ref="gac0d22d1bdbb6ee2bd6aa269429486375" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_LINK_CHANNEL&nbsp;&nbsp;&nbsp;1005u          </td>
+          <td class="memname">#define EDMA3_DRV_LINK_CHANNEL&nbsp;&nbsp;&nbsp;1005u</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for Link channels. PaRAM Set from the pool of (owned &amp;&amp; non_reserved &amp;&amp; available_right_now) PaRAM Sets will be chosen and returned. </p>
 
-<p>
-Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for Link channels. PaRAM Set from the pool of (owned &amp;&amp; non_reserved &amp;&amp; available_right_now) PaRAM Sets will be chosen and returned. 
 </div>
-</div><p>
-<a class="anchor" name="gf8efda8c9a32c28976c682d6480c976f"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_LINK_CHANNEL_WITH_TCC" ref="gf8efda8c9a32c28976c682d6480c976f" args="" -->
+</div>
+<a class="anchor" id="gaf8efda8c9a32c28976c682d6480c976f"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_LINK_CHANNEL_WITH_TCC" ref="gaf8efda8c9a32c28976c682d6480c976f" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC&nbsp;&nbsp;&nbsp;1006u          </td>
+          <td class="memname">#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC&nbsp;&nbsp;&nbsp;1006u</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for Link channels. TCC code should also be specified and it will be used to populate the LINK field of the PaRAM Set. Without TCC code, the call will fail. PaRAM Set from the pool of (owned &amp;&amp; non_reserved &amp;&amp; available_right_now) PaRAM Sets will be chosen and returned. </p>
 
-<p>
-Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for Link channels. TCC code should also be specified and it will be used to populate the LINK field of the PaRAM Set. Without TCC code, the call will fail. PaRAM Set from the pool of (owned &amp;&amp; non_reserved &amp;&amp; available_right_now) PaRAM Sets will be chosen and returned. 
 </div>
-</div><p>
-<a class="anchor" name="ged8a176b1257cdc385c940a1a9a84107"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_0" ref="ged8a176b1257cdc385c940a1a9a84107" args="" -->
+</div>
+<a class="anchor" id="gaed8a176b1257cdc385c940a1a9a84107"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_0" ref="gaed8a176b1257cdc385c940a1a9a84107" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_0&nbsp;&nbsp;&nbsp;(EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)          </td>
+          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_0&nbsp;&nbsp;&nbsp;(EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-QDMA Channel defines. 
-<p>
-They should be used while requesting a specific QDMA channel in API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a> as the argument (*pLch). Please note that these defines should ONLY be used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#g301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a> and not in any other API to perform further operations. They are only provided to allow user allocate specific QDMA channels. QDMA Channel 0 
+<p>QDMA Channel defines. </p>
+<p>They should be used while requesting a specific QDMA channel in API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a> as the argument (*pLch). Please note that these defines should ONLY be used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a> and not in any other API to perform further operations. They are only provided to allow user allocate specific QDMA channels. QDMA Channel 0 </p>
+
 </div>
-</div><p>
-<a class="anchor" name="g926b824823dfc5263108ee41eb6110d0"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_1" ref="g926b824823dfc5263108ee41eb6110d0" args="" -->
+</div>
+<a class="anchor" id="ga926b824823dfc5263108ee41eb6110d0"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_1" ref="ga926b824823dfc5263108ee41eb6110d0" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_1&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+1u)          </td>
+          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_1&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+1u)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>QDMA Channel 1 </p>
 
-<p>
-QDMA Channel 1 
 </div>
-</div><p>
-<a class="anchor" name="g41b662ac932dfcddef137609a2bd3ad4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_2" ref="g41b662ac932dfcddef137609a2bd3ad4" args="" -->
+</div>
+<a class="anchor" id="ga41b662ac932dfcddef137609a2bd3ad4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_2" ref="ga41b662ac932dfcddef137609a2bd3ad4" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_2&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+2u)          </td>
+          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_2&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+2u)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>QDMA Channel 2 </p>
 
-<p>
-QDMA Channel 2 
 </div>
-</div><p>
-<a class="anchor" name="ge97e0af735749d8ab8985dbd738eb578"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_3" ref="ge97e0af735749d8ab8985dbd738eb578" args="" -->
+</div>
+<a class="anchor" id="gae97e0af735749d8ab8985dbd738eb578"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_3" ref="gae97e0af735749d8ab8985dbd738eb578" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_3&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+3u)          </td>
+          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_3&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+3u)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>QDMA Channel 3 </p>
 
-<p>
-QDMA Channel 3 
 </div>
-</div><p>
-<a class="anchor" name="g1c11bab1b40c683b59c4801962cc6046"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_4" ref="g1c11bab1b40c683b59c4801962cc6046" args="" -->
+</div>
+<a class="anchor" id="ga1c11bab1b40c683b59c4801962cc6046"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_4" ref="ga1c11bab1b40c683b59c4801962cc6046" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_4&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+4u)          </td>
+          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_4&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+4u)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>QDMA Channel 4 </p>
 
-<p>
-QDMA Channel 4 
 </div>
-</div><p>
-<a class="anchor" name="g7d6c63e3a6da083430afd94578f4bd84"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_5" ref="g7d6c63e3a6da083430afd94578f4bd84" args="" -->
+</div>
+<a class="anchor" id="ga7d6c63e3a6da083430afd94578f4bd84"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_5" ref="ga7d6c63e3a6da083430afd94578f4bd84" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_5&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+5u)          </td>
+          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_5&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+5u)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>QDMA Channel 5 </p>
 
-<p>
-QDMA Channel 5 
 </div>
-</div><p>
-<a class="anchor" name="gc52b4731852ac8dac2f824fe0bdd153c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_6" ref="gc52b4731852ac8dac2f824fe0bdd153c" args="" -->
+</div>
+<a class="anchor" id="gac52b4731852ac8dac2f824fe0bdd153c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_6" ref="gac52b4731852ac8dac2f824fe0bdd153c" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_6&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+6u)          </td>
+          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_6&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+6u)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>QDMA Channel 6 </p>
 
-<p>
-QDMA Channel 6 
 </div>
-</div><p>
-<a class="anchor" name="gfc951e66232fc729344802c3abf6218b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_7" ref="gfc951e66232fc729344802c3abf6218b" args="" -->
+</div>
+<a class="anchor" id="gafc951e66232fc729344802c3abf6218b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_QDMA_CHANNEL_7" ref="gafc951e66232fc729344802c3abf6218b" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_7&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+7u)          </td>
+          <td class="memname">#define EDMA3_DRV_QDMA_CHANNEL_7&nbsp;&nbsp;&nbsp;(EDMA3_DRV_QDMA_CHANNEL_0+7u)</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>QDMA Channel 7 </p>
 
-<p>
-QDMA Channel 7 
 </div>
-</div><p>
-<a class="anchor" name="g2ca0c95ae69ae4cc71cc8137287a8fd1"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_CLEAN" ref="g2ca0c95ae69ae4cc71cc8137287a8fd1" args="" -->
+</div>
+<a class="anchor" id="ga2ca0c95ae69ae4cc71cc8137287a8fd1"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_CLEAN" ref="ga2ca0c95ae69ae4cc71cc8137287a8fd1" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_CHANNEL_CLEAN&nbsp;&nbsp;&nbsp;0x0000u          </td>
+          <td class="memname">#define EDMA3_DRV_CHANNEL_CLEAN&nbsp;&nbsp;&nbsp;0x0000u</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
 
-<p>
-Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#g85bad51ec992ce36ed7f28842b7d8219" title="Get the current status of the DMA/QDMA channel.">EDMA3_DRV_getChannelStatus()</a>. 
-<p>
-Channel is clean; no pending event, completion interrupt and event miss interrupt 
+<p>Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga85bad51ec992ce36ed7f28842b7d8219" title="Get the current status of the DMA/QDMA channel.">EDMA3_DRV_getChannelStatus()</a>. </p>
+<p>Channel is clean; no pending event, completion interrupt and event miss interrupt </p>
+
 </div>
-</div><p>
-<a class="anchor" name="g4b4982df7c3844ea394c9bb743fdf558"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_EVENT_PENDING" ref="g4b4982df7c3844ea394c9bb743fdf558" args="" -->
+</div>
+<a class="anchor" id="ga4b4982df7c3844ea394c9bb743fdf558"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_EVENT_PENDING" ref="ga4b4982df7c3844ea394c9bb743fdf558" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_CHANNEL_EVENT_PENDING&nbsp;&nbsp;&nbsp;0x0001u          </td>
+          <td class="memname">#define EDMA3_DRV_CHANNEL_EVENT_PENDING&nbsp;&nbsp;&nbsp;0x0001u</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Pending event is detected on the DMA channel </p>
 
-<p>
-Pending event is detected on the DMA channel 
 </div>
-</div><p>
-<a class="anchor" name="g80c785afc213172fda74b14c59946480"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_XFER_COMPLETE" ref="g80c785afc213172fda74b14c59946480" args="" -->
+</div>
+<a class="anchor" id="ga80c785afc213172fda74b14c59946480"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_XFER_COMPLETE" ref="ga80c785afc213172fda74b14c59946480" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_CHANNEL_XFER_COMPLETE&nbsp;&nbsp;&nbsp;0x0002u          </td>
+          <td class="memname">#define EDMA3_DRV_CHANNEL_XFER_COMPLETE&nbsp;&nbsp;&nbsp;0x0002u</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Transfer completion interrupt is detected on the DMA/QDMA channel </p>
 
-<p>
-Transfer completion interrupt is detected on the DMA/QDMA channel 
 </div>
-</div><p>
-<a class="anchor" name="gb4cc61240f1e9a3f69c602c0ede9553b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_ERR" ref="gb4cc61240f1e9a3f69c602c0ede9553b" args="" -->
+</div>
+<a class="anchor" id="gab4cc61240f1e9a3f69c602c0ede9553b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_CHANNEL_ERR" ref="gab4cc61240f1e9a3f69c602c0ede9553b" args="" -->
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname">#define EDMA3_DRV_CHANNEL_ERR&nbsp;&nbsp;&nbsp;0x0004u          </td>
+          <td class="memname">#define EDMA3_DRV_CHANNEL_ERR&nbsp;&nbsp;&nbsp;0x0004u</td>
         </tr>
       </table>
 </div>
 <div class="memdoc">
+<p>Event miss error interrupt is detected on the DMA/QDMA channel </p>
 
-<p>
-Event miss error interrupt is detected on the DMA/QDMA channel 
 </div>
-</div><p>
 </div>
-<hr size="1"><address style="text-align: right;"><small>Generated on Wed Apr 7 12:01:41 2010 for EDMA3 Driver by&nbsp;
+</div>
+<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by&nbsp;
 <a href="http://www.doxygen.org/index.html">
-<img src="doxygen.png" alt="doxygen" align="middle" border="0"></a> 1.5.5 </small></address>
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
 </body>
 </html>
index 3b9adaaa1532bb29bb3381b90d753a48198def40..07d7659ff4790c3d9d7181f93fa6e1e95efea478 100755 (executable)
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html><head><meta http-equiv="Content-Type" content="text/html;charset=UTF-8">
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <title>EDMA3 Driver: EDMA3 Driver Enums</title>
-<link href="doxygen.css" rel="stylesheet" type="text/css">
-<link href="tabs.css" rel="stylesheet" type="text/css">
-</head><body>
-<!-- Generated by Doxygen 1.5.5 -->
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head>
+<body>
+<!-- Generated by Doxygen 1.6.1 -->
 <div class="navigation" id="top">
   <div class="tabs">
     <ul>
       <li><a href="index.html"><span>Main&nbsp;Page</span></a></li>
       <li><a href="modules.html"><span>Modules</span></a></li>
-      <li><a href="classes.html"><span>Data&nbsp;Structures</span></a></li>
+      <li><a href="annotated.html"><span>Data&nbsp;Structures</span></a></li>
     </ul>
   </div>
 </div>
 <div class="contents">
-<h1>EDMA3 Driver Enums<br>
+<h1>EDMA3 Driver Enums<br/>
 <small>
 [<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l.html">EDMA3 Driver Symbols</a>]</small>
 </h1><table border="0" cellpadding="0" cellspacing="0">
-<tr><td></td></tr>
-<tr><td colspan="2"><br><h2>Enumerations</h2></td></tr>
-<tr><td class="memItemLeft" nowrap align="right" valign="top">enum &nbsp;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#g8e20d4ba59240144067e70bb8beb7879">EDMA3_DRV_HW_CHANNEL_EVENT</a> { <br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb787937748ea68c4fbf181415d15e4548a9d5">EDMA3_DRV_HW_CHANNEL_EVENT_0</a> =  0, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb787934192b4602da79a32906e449e86ddea9">EDMA3_DRV_HW_CHANNEL_EVENT_1</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879c36395e3506bd6fc8daf06ea945c4f1b">EDMA3_DRV_HW_CHANNEL_EVENT_2</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879d26ddd5a62ff5a8c079eff713ed24a6c">EDMA3_DRV_HW_CHANNEL_EVENT_3</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879b8d954a5708596eb302bbe617e16883e">EDMA3_DRV_HW_CHANNEL_EVENT_4</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78792ca5cca9c6e9c39d36c71feb28729a4c">EDMA3_DRV_HW_CHANNEL_EVENT_5</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879fed5d83771dff787abfa671c489c5bc1">EDMA3_DRV_HW_CHANNEL_EVENT_6</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879ad3f865ffab348c3bcfd75339801fc33">EDMA3_DRV_HW_CHANNEL_EVENT_7</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78793725a5901d7680739b36b5ffd3e5128b">EDMA3_DRV_HW_CHANNEL_EVENT_8</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879842a774c34014c24c7ad9e4a8aa2aa72">EDMA3_DRV_HW_CHANNEL_EVENT_9</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78792d99e6b419712a65dcd7a920b36a866e">EDMA3_DRV_HW_CHANNEL_EVENT_10</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879b956cf256d1818a5909f0399d85612f4">EDMA3_DRV_HW_CHANNEL_EVENT_11</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb787905b4c74778694509a7759e4cd124bc23">EDMA3_DRV_HW_CHANNEL_EVENT_12</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78797d86b7fe7d7c3f0077a2c8a445f16943">EDMA3_DRV_HW_CHANNEL_EVENT_13</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb787944782731229ca9470e1f46ed93bf6954">EDMA3_DRV_HW_CHANNEL_EVENT_14</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78796a773568b775bff069188481b2b1dc75">EDMA3_DRV_HW_CHANNEL_EVENT_15</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879a7c914b81cad4f66cd91ec5e89240a9d">EDMA3_DRV_HW_CHANNEL_EVENT_16</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78796dedf754dfe2a6eb21a9c4b2a8342099">EDMA3_DRV_HW_CHANNEL_EVENT_17</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78797c0d3ec834f566bf8b3ce427038baf60">EDMA3_DRV_HW_CHANNEL_EVENT_18</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb787971d5ec033e254c3a355a8c876304296f">EDMA3_DRV_HW_CHANNEL_EVENT_19</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879c9fd5d6ea19828bba5af7052223d532d">EDMA3_DRV_HW_CHANNEL_EVENT_20</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78794945278d24520fa8fe0dbf543582bdb4">EDMA3_DRV_HW_CHANNEL_EVENT_21</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78795222e130853fdbb6ce243bd8f8e516a6">EDMA3_DRV_HW_CHANNEL_EVENT_22</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78793ace2470d524a24e37a8e87fe5f4546e">EDMA3_DRV_HW_CHANNEL_EVENT_23</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879b8dbc9b117c7c16203ffe9268ac8943e">EDMA3_DRV_HW_CHANNEL_EVENT_24</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb787996ff3814c0936e06525dae25737b8e8c">EDMA3_DRV_HW_CHANNEL_EVENT_25</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879524cc629d15967c9e21547a1053af654">EDMA3_DRV_HW_CHANNEL_EVENT_26</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb78799138ddea8bb08222af544e7a1d884ebf">EDMA3_DRV_HW_CHANNEL_EVENT_27</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb7879e916849b035d8101e163ffb18a45f3b1">EDMA3_DRV_HW_CHANNEL_EVENT_28</a>, 
-<br>
-&nbsp;&nbsp;<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gg8e20d4ba59240144067e70bb8beb787997c9fd86fb3de0ff7963cdeb6ae0adb8">EDMA3_DRV_HW_CHANNEL_EVENT_29</a>, 
-<br>
-&nbsp;&nbsp;<a