summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: abff05d)
raw | patch | inline | side by side (parent: abff05d)
author | Sunil MS <x0190988@ti.com> | |
Wed, 10 Sep 2014 06:19:41 +0000 (11:49 +0530) | ||
committer | Sunil MS <x0190988@ti.com> | |
Thu, 9 Oct 2014 14:11:29 +0000 (19:41 +0530) |
MISRA.CVALUE.IMPL.CAST
MISRA.FUNC.PARAMS.IDENT
MISRA.ITER.ONETERM
MISRA.PPARAM.NEEDS.CONST
Signed-off-by: Sunil MS <x0190988@ti.com>
Change-Id: I0321488df8843c59c62b7e23cf27157d8a713d53
Signed-off-by: Sunil MS <x0190988@ti.com>
MISRA.FUNC.PARAMS.IDENT
MISRA.ITER.ONETERM
MISRA.PPARAM.NEEDS.CONST
Signed-off-by: Sunil MS <x0190988@ti.com>
Change-Id: I0321488df8843c59c62b7e23cf27157d8a713d53
Signed-off-by: Sunil MS <x0190988@ti.com>
packages/ti/sdo/edma3/rm/edma3_common.h | patch | blob | history | |
packages/ti/sdo/edma3/rm/edma3_rm.h | patch | blob | history | |
packages/ti/sdo/edma3/rm/src/edma3resmgr.c | patch | blob | history |
index e7087060deb38c71ed12dcb1e0427eda4e6be0a2..07f8c74a47163b14211aee7b5565e5529d90e69a 100755 (executable)
* available Transfer Controllers).
*/
/** EDMA3 Completion Handler ISR Routine */
* available Transfer Controllers).
*/
/** EDMA3 Completion Handler ISR Routine */
-extern void lisrEdma3ComplHandler0 (uint32_t arg);
+extern void lisrEdma3ComplHandler0 (uint32_t edma3InstanceId);
/** EDMA3 CC Error Interrupt Handler ISR Routine */
/** EDMA3 CC Error Interrupt Handler ISR Routine */
-extern void lisrEdma3CCErrHandler0 (uint32_t arg);
+extern void lisrEdma3CCErrHandler0 (uint32_t edma3InstanceId);
/** EDMA3 TC0 Error Interrupt Handler ISR Routine */
/** EDMA3 TC0 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC0ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC1 Error Interrupt Handler ISR Routine */
/** EDMA3 TC1 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC1ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC2 Error Interrupt Handler ISR Routine */
/** EDMA3 TC2 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC2ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC3 Error Interrupt Handler ISR Routine */
/** EDMA3 TC3 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC3ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC4 Error Interrupt Handler ISR Routine */
/** EDMA3 TC4 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC4ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC5 Error Interrupt Handler ISR Routine */
/** EDMA3 TC5 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC5ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC6 Error Interrupt Handler ISR Routine */
/** EDMA3 TC6 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC6ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId);
/** EDMA3 TC7 Error Interrupt Handler ISR Routine */
/** EDMA3 TC7 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC7ErrHandler0(uint32_t arg);
+extern void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId);
/**
* Defines for the level of OS protection needed when calling
/**
* Defines for the level of OS protection needed when calling
index 4731d8dca1e11e37906e0d0362d4cd28ac86e176..02fd6dc014f0dc98bc5162b4d6a0e92668ec61dc 100755 (executable)
* re-entrant for same lChObj value.
*/
EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
* re-entrant for same lChObj value.
*/
EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
const EDMA3_RM_PaRAMRegs *newPaRAM);
/**
const EDMA3_RM_PaRAMRegs *newPaRAM);
/**
* \note This function is re-entrant.
*/
EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
* \note This function is re-entrant.
*/
EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
EDMA3_RM_PaRAMRegs *currPaRAM);
/**
EDMA3_RM_PaRAMRegs *currPaRAM);
/**
* \note This function is re-entrant.
*/
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
* \note This function is re-entrant.
*/
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
uint32_t *paramPhyAddr);
/**
uint32_t *paramPhyAddr);
/**
diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.c b/packages/ti/sdo/edma3/rm/src/edma3resmgr.c
index 27da1a7829d58e168a85c70ed8083e365bb78da2..e3f67e1f528235eaea0c15d61b5d949ab67669e3 100755 (executable)
@@ -333,21 +333,21 @@ static EDMA3_RM_ChBoundResources edma3RmChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][E
/* Local functions prototypes */
/*---------------------------------------------------------------------------*/
/** EDMA3 Instance 0 Completion Handler Interrupt Service Routine */
/* Local functions prototypes */
/*---------------------------------------------------------------------------*/
/** EDMA3 Instance 0 Completion Handler Interrupt Service Routine */
-void lisrEdma3ComplHandler0(uint32_t arg);
+void lisrEdma3ComplHandler0(uint32_t edma3InstanceId);
/** EDMA3 Instance 0 CC Error Interrupt Service Routine */
/** EDMA3 Instance 0 CC Error Interrupt Service Routine */
-void lisrEdma3CCErrHandler0(uint32_t arg);
+void lisrEdma3CCErrHandler0(uint32_t edma3InstanceId);
/**
* EDMA3 Instance 0 TC[0-7] Error Interrupt Service Routines
* for a maximum of 8 TCs (Transfer Controllers).
*/
/**
* EDMA3 Instance 0 TC[0-7] Error Interrupt Service Routines
* for a maximum of 8 TCs (Transfer Controllers).
*/
-void lisrEdma3TC0ErrHandler0(uint32_t arg);
-void lisrEdma3TC1ErrHandler0(uint32_t arg);
-void lisrEdma3TC2ErrHandler0(uint32_t arg);
-void lisrEdma3TC3ErrHandler0(uint32_t arg);
-void lisrEdma3TC4ErrHandler0(uint32_t arg);
-void lisrEdma3TC5ErrHandler0(uint32_t arg);
-void lisrEdma3TC6ErrHandler0(uint32_t arg);
-void lisrEdma3TC7ErrHandler0(uint32_t arg);
+void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId);
+void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId);
/** Interrupt Handler for the Transfer Completion interrupt */
/** Interrupt Handler for the Transfer Completion interrupt */
else
{
edma3OsProtectEntry (phyCtrllerInstId,
else
{
edma3OsProtectEntry (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
&intState);
/** Check state of RM Object.
&intState);
/** Check state of RM Object.
{
result = EDMA3_RM_E_INVALID_STATE;
edma3OsProtectExit (phyCtrllerInstId,
{
result = EDMA3_RM_E_INVALID_STATE;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
intState);
}
else
{
result = EDMA3_RM_E_INVALID_STATE;
edma3OsProtectExit (phyCtrllerInstId,
{
result = EDMA3_RM_E_INVALID_STATE;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
intState);
}
else
{
result = EDMA3_RM_E_MAX_RM_INST_OPENED;
edma3OsProtectExit (phyCtrllerInstId,
{
result = EDMA3_RM_E_MAX_RM_INST_OPENED;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
}
intState);
}
}
/* No two masters should exist, return error */
result = EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS;
edma3OsProtectExit (phyCtrllerInstId,
/* No two masters should exist, return error */
result = EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
intState);
}
else
{
result = EDMA3_RM_E_MAX_RM_INST_OPENED;
edma3OsProtectExit (phyCtrllerInstId,
{
result = EDMA3_RM_E_MAX_RM_INST_OPENED;
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
else
intState);
}
else
rmInstance->initParam.rmInstInitConfig =
((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);
rmInstance->initParam.rmInstInitConfig =
((EDMA3_RM_InstanceInitConfig *)(ptrInitCfgArray) + (phyCtrllerInstId*EDMA3_MAX_RM_INSTANCES) + resMgrIdx);
- dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32U;
+ dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / (uint32_t)32U;
if (dmaChDwrds == 0)
{
/* In case DMA channels are < 32 */
if (dmaChDwrds == 0)
{
/* In case DMA channels are < 32 */
- dmaChDwrds = 1;
+ dmaChDwrds = 1U;
}
}
- paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32U;
+ paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / (uint32_t)32U;
if (paramSetDwrds == 0)
{
/* In case PaRAM Sets are < 32 */
if (paramSetDwrds == 0)
{
/* In case PaRAM Sets are < 32 */
- paramSetDwrds = 1;
+ paramSetDwrds = 1U;
}
}
- tccDwrds = rmObj->gblCfgParams.numTccs / 32U;
+ tccDwrds = rmObj->gblCfgParams.numTccs / (uint32_t)32U;
if (tccDwrds == 0)
{
/* In case TCCs are < 32 */
if (tccDwrds == 0)
{
/* In case TCCs are < 32 */
- tccDwrds = 1;
+ tccDwrds = 1U;
}
for (resMgrIdx = 0U; resMgrIdx < dmaChDwrds; ++resMgrIdx)
}
for (resMgrIdx = 0U; resMgrIdx < dmaChDwrds; ++resMgrIdx)
}
edma3OsProtectExit (phyCtrllerInstId,
}
edma3OsProtectExit (phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
}
}
intState);
}
}
}
else
{
}
else
{
- dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / 32U;
- paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / 32U;
- tccDwrds = rmObj->gblCfgParams.numTccs / 32U;
+ dmaChDwrds = rmObj->gblCfgParams.numDmaChannels / (uint32_t)32U;
+ paramSetDwrds = rmObj->gblCfgParams.numPaRAMSets / (uint32_t)32U;
+ tccDwrds = rmObj->gblCfgParams.numTccs / (uint32_t)32U;
/* Set the instance config as NULL*/
for (resMgrIdx = 0U; resMgrIdx < dmaChDwrds; ++resMgrIdx)
/* Set the instance config as NULL*/
for (resMgrIdx = 0U; resMgrIdx < dmaChDwrds; ++resMgrIdx)
/* Critical section starts */
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
/* Critical section starts */
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
&intState);
/* Decrease the Number of Opens */
&intState);
/* Decrease the Number of Opens */
/* Critical section ends */
edma3OsProtectExit (rmObj->phyCtrllerInstId,
/* Critical section ends */
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
rmInstance->pResMgrObjHandle = NULL;
intState);
rmInstance->pResMgrObjHandle = NULL;
{
rmInstance->shadowRegs->IECR = (1UL << mappedTcc);
}
{
rmInstance->shadowRegs->IECR = (1UL << mappedTcc);
}
- else if(mappedTcc < 64)
+ else if(mappedTcc < 64U)
{
rmInstance->shadowRegs->IECRH = (1UL << (mappedTcc-32U));
}
{
rmInstance->shadowRegs->IECRH = (1UL << (mappedTcc-32U));
}
uint32_t i = 0U;
uint32_t position = 0U;
uint32_t edma3Id;
uint32_t i = 0U;
uint32_t position = 0U;
uint32_t edma3Id;
+ uint32_t errFlag=0U;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
}
}
else
@@ -3632,7 +3633,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
}
}
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
}
}
else
@@ -3681,7 +3686,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
}
}
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
}
}
else
@@ -3741,7 +3750,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
}
}
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
{
/* Specified resource is owned but is already booked */
result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- break;
+ errFlag = 1U;
}
}
else
}
}
else
@@ -3793,7 +3806,11 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
* of the Resource Manager
*/
result = EDMA3_RM_E_RES_NOT_OWNED;
- break;
+ errFlag = 1U;
+ }
+ if(errFlag == 1U)
+ {
+ break;
}
}
}
}
{
/* Semaphore taken successfully, modify the registers. */
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
{
/* Semaphore taken successfully, modify the registers. */
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
&intState);
/* Global interrupts disabled, modify the registers. */
regPhyAddr = (uint32_t)(rmObj->gblCfgParams.globalRegs) + regOffset;
*(uint32_t *)regPhyAddr = newRegValue;
edma3OsProtectExit (rmObj->phyCtrllerInstId,
&intState);
/* Global interrupts disabled, modify the registers. */
regPhyAddr = (uint32_t)(rmObj->gblCfgParams.globalRegs) + regOffset;
*(uint32_t *)regPhyAddr = newRegValue;
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT,
intState);
/* Return the semaphore back */
intState);
/* Return the semaphore back */
tccBitMask = (1U << tccNo);
/* Check the status of the IPR[tccNo] bit. */
tccBitMask = (1U << tccNo);
/* Check the status of the IPR[tccNo] bit. */
- while (FALSE == (shadowRegs->IPR & tccBitMask))
+ while ((uint32_t)FALSE == (shadowRegs->IPR & tccBitMask))
{
/* Transfer not yet completed, bit not SET */
}
{
/* Transfer not yet completed, bit not SET */
}
tccBitMask = (1U << (tccNo - 32U));
/* Check the status of the IPRH[tccNo-32] bit. */
tccBitMask = (1U << (tccNo - 32U));
/* Check the status of the IPRH[tccNo-32] bit. */
- while (FALSE == (shadowRegs->IPRH & tccBitMask))
+ while ((uint32_t)FALSE == (shadowRegs->IPRH & tccBitMask))
{
/* Transfer not yet completed, bit not SET */
}
{
/* Transfer not yet completed, bit not SET */
}
}
EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
}
EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
const EDMA3_RM_PaRAMRegs *newPaRAM)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
const EDMA3_RM_PaRAMRegs *newPaRAM)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int32_t paRAMId = 0U;
+ int32_t paRAMId = 0;
uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
uint32_t edma3Id;
uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
uint32_t edma3Id;
}
EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
}
EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
EDMA3_RM_PaRAMRegs *currPaRAM)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_PaRAMRegs *currPaRAM)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int32_t paRAMId = 0U;
+ int32_t paRAMId = 0;
uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
uint32_t edma3Id;
uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
uint32_t edma3Id;
if (result == EDMA3_RM_SOK)
{
/* Check the param id first. */
if (result == EDMA3_RM_SOK)
{
/* Check the param id first. */
- if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets))
+ if ((paRAMId != -1) && ((uint32_t)paRAMId < edma3NumPaRAMSets))
{
/* Get the PaRAM Set now. */
edma3ParamCpy ((void *)currPaRAM ,
{
/* Get the PaRAM Set now. */
edma3ParamCpy ((void *)currPaRAM ,
}
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
}
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
- EDMA3_RM_ResDesc *lChObj,
+ const EDMA3_RM_ResDesc *lChObj,
uint32_t *paramPhyAddr)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
uint32_t *paramPhyAddr)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int32_t paRAMId = 0U;
+ int32_t paRAMId = 0;
uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
uint32_t edma3Id;
uint32_t qdmaChId = 0U;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
uint32_t edma3Id;
if (result == EDMA3_RM_SOK)
{
/* Check the param id first. */
if (result == EDMA3_RM_SOK)
{
/* Check the param id first. */
- if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets))
+ if ((paRAMId != -1) && (paRAMId < (int32_t)edma3NumPaRAMSets))
{
/* Get the PaRAM Set Address now. */
*paramPhyAddr = (uint32_t)(&(globalRegs->PARAMENTRY [paRAMId].OPT));
{
/* Get the PaRAM Set Address now. */
*paramPhyAddr = (uint32_t)(&(globalRegs->PARAMENTRY [paRAMId].OPT));
indexl = 1U;
indexh = 1U;
indexl = 1U;
indexh = 1U;
- if (numTCCs > 32)
+ if (numTCCs > 32U)
{
isIPR = shadowRegs->IPR | shadowRegs->IPRH;
}
{
isIPR = shadowRegs->IPR | shadowRegs->IPRH;
}
*/
edma3OsProtectEntry (edma3Id,
*/
edma3OsProtectEntry (edma3Id,
- EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
NULL);
/* Loop for EDMA3_RM_COMPL_HANDLER_RETRY_COUNT number of time,
NULL);
/* Loop for EDMA3_RM_COMPL_HANDLER_RETRY_COUNT number of time,
pendingIrqs >>= 1U;
}
pendingIrqs >>= 1U;
}
- if(numTCCs > 32)
+ if(numTCCs > 32U)
{
indexh = 0U;
pendingIrqs = shadowRegs->IPRH;
{
indexh = 0U;
pendingIrqs = shadowRegs->IPRH;
}
indexl = (shadowRegs->IPR & allocatedTCCs[edma3Id][0U]);
}
indexl = (shadowRegs->IPR & allocatedTCCs[edma3Id][0U]);
- if (numTCCs > 32)
+ if (numTCCs > 32U)
{
indexh = (shadowRegs->IPRH & allocatedTCCs[edma3Id][1U]);
}
{
indexh = (shadowRegs->IPRH & allocatedTCCs[edma3Id][1U]);
}
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION,
0);
}
0);
}
pendingIrqs = ((ptrEdmaccRegs->EMR != 0 )
|| (ptrEdmaccRegs->QEMR != 0)
|| (ptrEdmaccRegs->CCERR != 0));
pendingIrqs = ((ptrEdmaccRegs->EMR != 0 )
|| (ptrEdmaccRegs->QEMR != 0)
|| (ptrEdmaccRegs->CCERR != 0));
- if (numTCCs > 32)
+ if (numTCCs > 32U)
{
pendingIrqs = pendingIrqs || (ptrEdmaccRegs->EMRH != 0 );
}
{
pendingIrqs = pendingIrqs || (ptrEdmaccRegs->EMRH != 0 );
}
if(pendingIrqs)
{
edma3OsProtectEntry (edma3Id,
if(pendingIrqs)
{
edma3OsProtectEntry (edma3Id,
- EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
NULL);
/* Loop for EDMA3_RM_CCERR_HANDLER_RETRY_COUNT number of time,
NULL);
/* Loop for EDMA3_RM_CCERR_HANDLER_RETRY_COUNT number of time,
pendingIrqs >>= 1U;
}
pendingIrqs >>= 1U;
}
- if(numTCCs > 32)
+ if(numTCCs > 32U)
{
index = 0U;
pendingIrqs = ptrEdmaccRegs->EMRH;
{
index = 0U;
pendingIrqs = ptrEdmaccRegs->EMRH;
/* Check all the error bits. */
ownedDmaError = ptrEdmaccRegs->EMR;
/* Check all the error bits. */
ownedDmaError = ptrEdmaccRegs->EMR;
- if (numTCCs > 32)
+ if (numTCCs > 32U)
{
ownedDmaHError = ptrEdmaccRegs->EMRH;
}
{
ownedDmaHError = ptrEdmaccRegs->EMRH;
}
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR,
0);
}
}
0);
}
}
if(tcRegs->ERRSTAT != 0)
{
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
if(tcRegs->ERRSTAT != 0)
{
edma3OsProtectEntry (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
&tcNum);
if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT))!= 0)
&tcNum);
if((tcRegs->ERRSTAT & ((uint32_t)1 << EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT))!= 0)
* address. Error information can be read from the error
* details register (ERRDET).
*/
* address. Error information can be read from the error
* details register (ERRDET).
*/
- tcMemErrRdWr = tcRegs->ERRDET & (EDMA3_TCRL_ERRDET_STAT_MASK);
+ tcMemErrRdWr = tcRegs->ERRDET & ((uint32_t)EDMA3_TCRL_ERRDET_STAT_MASK);
if ((tcMemErrRdWr > 0U) && (tcMemErrRdWr < 8U))
{
/**
if ((tcMemErrRdWr > 0U) && (tcMemErrRdWr < 8U))
{
/**
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
}
edma3OsProtectExit (rmObj->phyCtrllerInstId,
- EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
+ (int32_t)EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR,
tcNum);
}
}
tcNum);
}
}
void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC0*/
void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC0*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 0U);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)0U);
}
}
void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC1*/
void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC1*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 1U);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)1U);
}
/*
}
/*
void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC2*/
void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC2*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 2U);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)2U);
}
/*
}
/*
void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC3*/
void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC3*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 3U);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)3U);
}
/*
}
/*
void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC4*/
void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC4*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 4U);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)4U);
}
}
void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC5*/
void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC5*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 5U);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)5U);
}
/*
}
/*
void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC6*/
void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC6*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 6U);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)6U);
}
/*
}
/*
void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC7*/
void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC7*/
- edma3TCErrHandler(&resMgrObj[edma3InstanceId], 7U);
+ edma3TCErrHandler(&resMgrObj[edma3InstanceId], (uint32_t)7U);
}
}
@@ -6105,7 +6122,7 @@ static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId, uint32_t numDmaCha
if (ptrEdmaccRegs != NULL)
{
ptrEdmaccRegs->EMCR = EDMA3_RM_SET_ALL_BITS;
if (ptrEdmaccRegs != NULL)
{
ptrEdmaccRegs->EMCR = EDMA3_RM_SET_ALL_BITS;
- if ( numDmaChannels > 32)
+ if ( numDmaChannels > 32U)
{
/* Clear the EMCRH only if available channels are more than 32 */
ptrEdmaccRegs->EMCRH = EDMA3_RM_SET_ALL_BITS;
{
/* Clear the EMCRH only if available channels are more than 32 */
ptrEdmaccRegs->EMCRH = EDMA3_RM_SET_ALL_BITS;
ds = (uint32_t *)dst;
ds = (uint32_t *)dst;
- for (i = 0 ; i < (len/4) ; i++)
+ for (i = 0U ; i < (len/4U) ; i++)
{
*ds = 0x0;
ds++;
{
*ds = 0x0;
ds++;
sr = (const uint32_t *)src;
ds = (uint32_t *)dst;
sr = (const uint32_t *)src;
ds = (uint32_t *)dst;
- for (i = 0 ; i < (len/4) ; i++)
+ for (i = 0U ; i < (len/4U) ; i++)
{
*ds = *sr;
ds++;
{
*ds = *sr;
ds++;
sr = (const volatile uint32_t *)src;
ds = (volatile uint32_t *)dst;
sr = (const volatile uint32_t *)src;
ds = (volatile uint32_t *)dst;
- for (i = 0; i < 8; i++)
+ for (i = 0U; i < 8U; i++)
{
*ds = *sr;
ds++;
{
*ds = *sr;
ds++;
{
switch (bit)
{
{
switch (bit)
{
- case 1:
+ case 1U:
{
/* Find '1' in first word. */
{
/* Find '1' in first word. */
- position = findBitInWord (resPtr[start_index], start, 1U);
+ position = findBitInWord (resPtr[start_index], start, (uint16_t)1U);
if (position != -1)
{
if (position != -1)
{
else
{
/* '1' NOT found, look into other words. */
else
{
/* '1' NOT found, look into other words. */
- for (i = (int32_t)((int32_t)start_index + 1U); i <= (int32_t)((int32_t)end_index - 1U); i++)
+ for (i = ((int32_t)start_index + (int32_t)1U); i <= ((int32_t)end_index - (int32_t)1U); i++)
{
{
- position = findBitInWord (resPtr[i], 0U, 1U);
+ position = findBitInWord (resPtr[i], (uint32_t)0U, (uint16_t)1U);
if (position != -1)
{
/* '1' Found... */
if (position != -1)
{
/* '1' Found... */
if (ret == -1)
{
/* Still not found, look in the last word. */
if (ret == -1)
{
/* Still not found, look in the last word. */
- position = findBitInWord(resPtr[end_index], 0U, 1U);
+ position = findBitInWord(resPtr[end_index], (uint32_t)0U, (uint16_t)1U);
if (position != -1)
{
/* Finally got it. */
if (position != -1)
{
/* Finally got it. */
- ret = (position + (end_index*32U));
+ ret = (position + ((int32_t)end_index*(int32_t)32U));
}
else
{
}
else
{
}
break;
}
break;
- case 0:
+ case 0U:
{
/* Find '0' in first word. */
{
/* Find '0' in first word. */
- position = findBitInWord(resPtr[start_index], start, 0U);
+ position = findBitInWord(resPtr[start_index], start, (uint16_t)0U);
if (position != -1)
{
ret = position;
if (position != -1)
{
ret = position;
else
{
/* '0' NOT found, look into other words. */
else
{
/* '0' NOT found, look into other words. */
- for (i = (start_index + 1U); i <= (end_index - 1U); i++)
+ for (i = ((int32_t)start_index + (int32_t)1U); i <= ((int32_t)end_index - (int32_t)1U); i++)
{
{
- position = findBitInWord(resPtr[i], 0U, 0U);
+ position = findBitInWord(resPtr[i], (uint32_t)0U, (uint16_t)0U);
if (position != -1)
{
/* '0' found... */
if (position != -1)
{
/* '0' found... */
/* First check whether we have found '0' or not. */
if (ret == -1)
{
/* First check whether we have found '0' or not. */
if (ret == -1)
{
- position = findBitInWord(resPtr[end_index], 0U, 0U);
+ position = findBitInWord(resPtr[end_index], (uint32_t)0U, (uint16_t)0U);
if (position != -1)
{
/* Finally got it. */
if (position != -1)
{
/* Finally got it. */
- ret = (position + (end_index*32U));
+ ret = (position + ((int32_t)end_index*(int32_t)32U));
}
else
{
}
else
{
- return ((ret >= start) ? ret : -1);
-}
+ return ((ret >= (int32_t)start) ? ret : -1);
+ }
while((found == 0) && (start<=end) && (((end-start)+1U) >= numResources))
{
/* Find first '1' starting from 'start' till 'end'. */
while((found == 0) && (start<=end) && (((end-start)+1U) >= numResources))
{
/* Find first '1' starting from 'start' till 'end'. */
- first_one = findBit (resType, start, end, 1U);
+ first_one = findBit (resType, start, end, (uint16_t)1U);
if (first_one != -1)
{
/* Got first 1, search for first '0' now. */
if (first_one != -1)
{
/* Got first 1, search for first '0' now. */
- next_zero = findBit (resType, first_one+1, end, 0U);
+ next_zero = findBit (resType, (uint32_t)first_one+(uint32_t)1, end, (uint16_t)0U);
if (next_zero == -1)
{
/* Unable to find next zero, all 1' are there */
if (next_zero == -1)
{
/* Unable to find next zero, all 1' are there */
- next_zero = end + 1U;
+ next_zero = (int32_t)end + (int32_t)1U;
}
/* check no of resources available */
}
/* check no of resources available */
- num_available = next_zero - first_one;
+ num_available = (uint32_t)next_zero - (uint32_t)first_one;
if (num_available >= numResources)
{
/* hurrah..., we have found enough resources. */
if (num_available >= numResources)
{
/* hurrah..., we have found enough resources. */
else
{
/* Not enough resources, try again */
else
{
/* Not enough resources, try again */
- start = next_zero + 1;
+ start = (uint32_t)next_zero + (uint32_t)1;
}
}
else
}
}
else
}
}
-EDMA3_RM_Result EDMA3_RM_initXbarEventMap (EDMA3_RM_Handle hEdmaResMgr,
+EDMA3_RM_Result EDMA3_RM_initXbarEventMap (EDMA3_RM_Handle hEdma,
const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig,
EDMA3_RM_mapXbarEvtToChan mapXbarEvtFunc,
EDMA3_RM_xbarConfigScr configXbarScr)
const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig,
EDMA3_RM_mapXbarEvtToChan mapXbarEvtFunc,
EDMA3_RM_xbarConfigScr configXbarScr)
/* If parameter checking is enabled... */
#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
/* If parameter checking is enabled... */
#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
- if (hEdmaResMgr == NULL)
+ if (hEdma == NULL)
{
result = EDMA3_RM_E_INVALID_PARAM;
}
{
result = EDMA3_RM_E_INVALID_PARAM;
}
/* Check if the parameters are OK. */
if (EDMA3_DRV_SOK == result)
{
/* Check if the parameters are OK. */
if (EDMA3_DRV_SOK == result)
{
- rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+ rmInstance = (EDMA3_RM_Instance *)hEdma;
if (mapXbarEvtFunc != NULL)
{
if (mapXbarEvtFunc != NULL)
{