Fix for multi-core execution of examples.
authorRaghu Nambiath <rnambiath@ti.com>
Mon, 14 Feb 2011 12:04:00 +0000 (17:34 +0530)
committerSundaram Raju <sundaram@ti.com>
Mon, 14 Feb 2011 12:37:48 +0000 (18:07 +0530)
- Address would need to be global for EDMA transfer
- Testing version querry API added in the EDMA DRV module
- Adding of code to test default RM configuration

Signed-off-by: Sundaram Raju <sundaram@ti.com>
32 files changed:
examples/edma3_driver/evm6472/sample_app/linker.cmd
examples/edma3_driver/evm6472BE/sample_app/linker.cmd
examples/edma3_driver/evmTCI6486/sample_app/linker.cmd
examples/edma3_driver/evmTCI6486BE/sample_app/linker.cmd
examples/edma3_driver/src/dma_chain_test.c
examples/edma3_driver/src/dma_link_test.c
examples/edma3_driver/src/dma_ping_pong_test.c
examples/edma3_driver/src/dma_poll_test.c
examples/edma3_driver/src/dma_test.c
examples/edma3_driver/src/main.c
examples/edma3_driver/src/qdma_link_test.c
examples/edma3_driver/src/qdma_test.c
examples/edma3_driver/src/sample.h
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6472_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6748_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_da830_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl138_arm_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl138_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6486_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_cfg.c
packages/ti/sdo/edma3/drv/sample/src/sample_init.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6472_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6748_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_da830_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl138_arm_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl138_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6486_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti816x_cfg.c

index c29425e0b65a22e6042c6f249212897ad18023cc..794917c3cc81ea45cd57e289c7e3084f7e12b0f7 100644 (file)
@@ -1,15 +1,5 @@
-MEMORY
-{
-       GEM0_L2MEM: o=0x10850000, l=40000h
-       GEM1_L2MEM: o=0x11850000, l=40000h
-       GEM2_L2MEM: o=0x12850000, l=40000h
-       GEM3_L2MEM: o=0x13850000, l=40000h
-       GEM4_L2MEM: o=0x14850000, l=40000h
-       GEM5_L2MEM: o=0x15850000, l=40000h
-}
-
 SECTIONS
 {
-       .my_sect_iram  > GEM0_L2MEM
-       .my_sect_ddr  > GEM0_L2MEM
+       .my_sect_iram  > LL2RAM
+       .my_sect_ddr  > LL2RAM
 }
index c29425e0b65a22e6042c6f249212897ad18023cc..794917c3cc81ea45cd57e289c7e3084f7e12b0f7 100644 (file)
@@ -1,15 +1,5 @@
-MEMORY
-{
-       GEM0_L2MEM: o=0x10850000, l=40000h
-       GEM1_L2MEM: o=0x11850000, l=40000h
-       GEM2_L2MEM: o=0x12850000, l=40000h
-       GEM3_L2MEM: o=0x13850000, l=40000h
-       GEM4_L2MEM: o=0x14850000, l=40000h
-       GEM5_L2MEM: o=0x15850000, l=40000h
-}
-
 SECTIONS
 {
-       .my_sect_iram  > GEM0_L2MEM
-       .my_sect_ddr  > GEM0_L2MEM
+       .my_sect_iram  > LL2RAM
+       .my_sect_ddr  > LL2RAM
 }
index c29425e0b65a22e6042c6f249212897ad18023cc..794917c3cc81ea45cd57e289c7e3084f7e12b0f7 100644 (file)
@@ -1,15 +1,5 @@
-MEMORY
-{
-       GEM0_L2MEM: o=0x10850000, l=40000h
-       GEM1_L2MEM: o=0x11850000, l=40000h
-       GEM2_L2MEM: o=0x12850000, l=40000h
-       GEM3_L2MEM: o=0x13850000, l=40000h
-       GEM4_L2MEM: o=0x14850000, l=40000h
-       GEM5_L2MEM: o=0x15850000, l=40000h
-}
-
 SECTIONS
 {
-       .my_sect_iram  > GEM0_L2MEM
-       .my_sect_ddr  > GEM0_L2MEM
+       .my_sect_iram  > LL2RAM
+       .my_sect_ddr  > LL2RAM
 }
index c29425e0b65a22e6042c6f249212897ad18023cc..794917c3cc81ea45cd57e289c7e3084f7e12b0f7 100644 (file)
@@ -1,15 +1,5 @@
-MEMORY
-{
-       GEM0_L2MEM: o=0x10850000, l=40000h
-       GEM1_L2MEM: o=0x11850000, l=40000h
-       GEM2_L2MEM: o=0x12850000, l=40000h
-       GEM3_L2MEM: o=0x13850000, l=40000h
-       GEM4_L2MEM: o=0x14850000, l=40000h
-       GEM5_L2MEM: o=0x15850000, l=40000h
-}
-
 SECTIONS
 {
-       .my_sect_iram  > GEM0_L2MEM
-       .my_sect_ddr  > GEM0_L2MEM
+       .my_sect_iram  > LL2RAM
+       .my_sect_ddr  > LL2RAM
 }
index bab34a906ca5db2759bc978d5e9af197574534f9..17635345652d656a7883b493cefa9cf3a9a7f25c 100755 (executable)
-/*\r
- * dma_chain_test.c\r
- *\r
- * Test case demonstrating the usgae of DMA channels for transferring data \r
- * between two memory locations. The two DMA channels are chained to each other.\r
- *\r
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ \r
- * \r
- * \r
- *  Redistribution and use in source and binary forms, with or without \r
- *  modification, are permitted provided that the following conditions \r
- *  are met:\r
- *\r
- *    Redistributions of source code must retain the above copyright \r
- *    notice, this list of conditions and the following disclaimer.\r
- *\r
- *    Redistributions in binary form must reproduce the above copyright\r
- *    notice, this list of conditions and the following disclaimer in the \r
- *    documentation and/or other materials provided with the   \r
- *    distribution.\r
- *\r
- *    Neither the name of Texas Instruments Incorporated nor the names of\r
- *    its contributors may be used to endorse or promote products derived\r
- *    from this software without specific prior written permission.\r
- *\r
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
-*/\r
-\r
-#include "sample.h"\r
-\r
-extern signed char   _srcBuff1[MAX_BUFFER_SIZE];\r
-extern signed char   _srcBuff2[MAX_BUFFER_SIZE];\r
-extern signed char   _dstBuff1[MAX_BUFFER_SIZE];\r
-extern signed char   _dstBuff2[MAX_BUFFER_SIZE];\r
-\r
-extern signed char *srcBuff1;\r
-extern signed char *srcBuff2;\r
-extern signed char *dstBuff1;\r
-extern signed char *dstBuff2;\r
-\r
-\r
-/**\r
- *  \brief   EDMA3 mem-to-mem data copy test case, using two DMA channels,\r
- *              chained to each other.\r
- *\r
- *  \param  acnt        [IN]      Number of bytes in an array\r
- *  \param  bcnt        [IN]      Number of arrays in a frame\r
- *  \param  ccnt        [IN]      Number of frames in a block\r
- *  \param  syncType    [IN]      Synchronization type (A/AB Sync)\r
- *\r
- *  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result edma3_test_with_chaining(\r
-                                                       EDMA3_DRV_Handle hEdma,\r
-                                unsigned int acnt,\r
-                                unsigned int bcnt,\r
-                                unsigned int ccnt,\r
-                                EDMA3_DRV_SyncType syncType)\r
-    {\r
-    EDMA3_DRV_ChainOptions chain = {EDMA3_DRV_TCCHEN_DIS,\r
-                                    EDMA3_DRV_ITCCHEN_DIS,\r
-                                    EDMA3_DRV_TCINTEN_DIS,\r
-                                    EDMA3_DRV_ITCINTEN_DIS};\r
-    EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
-    unsigned int BRCnt = 0;\r
-    int srcbidx = 0, desbidx = 0;\r
-    int srccidx = 0, descidx = 0;\r
-    unsigned int ch1Id = 0;\r
-    unsigned int ch2Id = 0;\r
-    unsigned int tcc1 = 0;\r
-    unsigned int tcc2 = 0;\r
-    int i;\r
-    unsigned int numenabled = 0;\r
-    unsigned int count;\r
-    unsigned int Istestpassed1 = 0u;\r
-    unsigned int Istestpassed2 = 0u;\r
-\r
-\r
-    srcBuff1 = (signed char*) _srcBuff1;\r
-    dstBuff1 = (signed char*) _dstBuff1;\r
-    srcBuff2 = (signed char*) _srcBuff2;\r
-    dstBuff2 = (signed char*) _dstBuff2;\r
-\r
-\r
-    /* Initalize source and destination buffers */\r
-    for (count = 0u; count < (acnt*bcnt*ccnt); count++)\r
-        {\r
-        srcBuff1[count] = (int)count+4;\r
-        srcBuff2[count] = (int)count+4;\r
-        /**\r
-         * No need to initialize the destination buffer as it is being invalidated.\r
-        dstBuff1[count] = initval;\r
-        dstBuff2[count] = initval;\r
-        */\r
-        }\r
-\r
-\r
-#ifdef EDMA3_ENABLE_DCACHE\r
-    /*\r
-    * Note: These functions are required if the buffer is in DDR.\r
-    * For other cases, where buffer is NOT in DDR, user\r
-    * may or may not require the below functions.\r
-    */\r
-    /* Flush the Source Buffers */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));\r
-        }\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt));\r
-        }\r
-\r
-    /* Invalidate the Destination Buffers */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));\r
-        }\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt));\r
-        }\r
-#endif  /* EDMA3_ENABLE_DCACHE */\r
-\r
-\r
-    /* Set B count reload as B count. */\r
-    BRCnt = bcnt;\r
-\r
-    /* Setting up the SRC/DES Index */\r
-    srcbidx = (int)acnt;\r
-    desbidx = (int)acnt;\r
-\r
-    if (syncType == EDMA3_DRV_SYNC_A)\r
-        {\r
-        /* A Sync Transfer Mode */\r
-        srccidx = (int)acnt;\r
-        descidx = (int)acnt;\r
-        }\r
-    else\r
-        {\r
-        /* AB Sync Transfer Mode */\r
-        srccidx = ((int)acnt * (int)bcnt);\r
-        descidx = ((int)acnt * (int)bcnt);\r
-        }\r
-\r
-\r
-    /* Transfer complete chaining enable. */\r
-    chain.tcchEn = EDMA3_DRV_TCCHEN_EN;\r
-    /* Intermediate transfer complete chaining enable. */\r
-    chain.itcchEn = EDMA3_DRV_ITCCHEN_EN;\r
-    /* Transfer complete interrupt is enabled. */\r
-    chain.tcintEn = EDMA3_DRV_TCINTEN_EN;\r
-    /* Intermediate transfer complete interrupt is disabled. */\r
-    chain.itcintEn = EDMA3_DRV_ITCINTEN_DIS;\r
-\r
-\r
-    /* Setup for Channel 1*/\r
-    tcc1 = EDMA3_DRV_TCC_ANY;\r
-    ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1,\r
-                                            (EDMA3_RM_EventQueue)0,\r
-                                            &callback1, NULL);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcParams (hEdma, ch1Id,\r
-                                        (unsigned int)(srcBuff1),\r
-                                        EDMA3_DRV_ADDR_MODE_INCR,\r
-                                        EDMA3_DRV_W8BIT);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setDestParams (hEdma, ch1Id,\r
-                                            (unsigned int)(dstBuff1),\r
-                                            EDMA3_DRV_ADDR_MODE_INCR,\r
-                                            EDMA3_DRV_W8BIT);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        if (syncType == EDMA3_DRV_SYNC_A)\r
-            {\r
-            result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,\r
-                                                    ccnt,BRCnt,\r
-                                                    EDMA3_DRV_SYNC_A);\r
-            }\r
-        else\r
-            {\r
-            /* AB Sync Transfer Mode */\r
-            result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,\r
-                                                    ccnt, BRCnt,\r
-                                                    EDMA3_DRV_SYNC_AB);\r
-            }\r
-        }\r
-\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Setup for Channel 2 */\r
-        tcc2 = EDMA3_DRV_TCC_ANY;\r
-        ch2Id = EDMA3_DRV_DMA_CHANNEL_ANY;\r
-\r
-        result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2,\r
-                                            (EDMA3_RM_EventQueue)0,\r
-                                            &callback2, NULL);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2),\r
-                                        EDMA3_DRV_ADDR_MODE_INCR,\r
-                                        EDMA3_DRV_W8BIT);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setDestParams (hEdma, ch2Id,\r
-                                            (unsigned int)(dstBuff2),\r
-                                            EDMA3_DRV_ADDR_MODE_INCR,\r
-                                            EDMA3_DRV_W8BIT);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result =  EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        if (syncType == EDMA3_DRV_SYNC_A)\r
-            {\r
-            result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,\r
-                                                    ccnt, BRCnt,\r
-                                                    EDMA3_DRV_SYNC_A);\r
-            }\r
-        else\r
-            {\r
-            /* AB Sync Transfer Mode */\r
-            result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,\r
-                                                    ccnt, BRCnt,\r
-                                                    EDMA3_DRV_SYNC_AB);\r
-            }\r
-        }\r
-\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /**\r
-         * Enable the Transfer Completion Interrupt on the Chained Channel\r
-         * (Ch 2).\r
-         */\r
-        result = EDMA3_DRV_setOptField (hEdma, ch2Id,\r
-                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /**\r
-         * Enable the Intermediate Transfer Completion Interrupt on the\r
-         * Chained Channel (Ch 2).\r
-         */\r
-        result = EDMA3_DRV_setOptField (hEdma, ch2Id,\r
-                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);\r
-        }\r
-\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Now chain the two channels together. */\r
-        result = EDMA3_DRV_chainChannel(hEdma, ch1Id, ch2Id,\r
-                                    (EDMA3_DRV_ChainOptions *)&chain);\r
-        }\r
-\r
-\r
-    /*Need to activate next param*/\r
-    if (syncType == EDMA3_DRV_SYNC_A)\r
-        {\r
-        numenabled = bcnt * ccnt;\r
-        }\r
-    else\r
-        {\r
-        /* AB Sync Transfer Mode */\r
-        numenabled = ccnt;\r
-        }\r
-\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        for (i = 0; i < numenabled; i++)\r
-            {\r
-            irqRaised2 = 0;\r
-\r
-            /*\r
-             * Now enable the transfer for Master channel as many times\r
-             * as calculated above.\r
-             */\r
-            result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,\r
-                                                EDMA3_DRV_TRIG_MODE_MANUAL);\r
-            if (result != EDMA3_DRV_SOK)\r
-                {\r
-    #ifdef EDMA3_DRV_DEBUG\r
-                EDMA3_DRV_PRINTF ("error from edma3_test_with_chaining\n\r\n");\r
-    #endif  /* EDMA3_DRV_DEBUG */\r
-                break;\r
-                }\r
-\r
-\r
-            /**\r
-             * Transfer on the master channel (ch1Id) will finish after some\r
-             * time.\r
-             * Now, because of the enabling of intermediate chaining on channel\r
-             * 1, after the transfer gets over, a sync event will be sent\r
-             * to channel 2, which will trigger the transfer on it.\r
-             * Also, Final and Intermediate Transfer Complete\r
-             * Interrupts are enabled on channel 2, so we should wait for the\r
-             * completion ISR on channel 2 first, before proceeding\r
-             * ahead.\r
-             */\r
-            while (irqRaised2 == 0)\r
-                {\r
-                /* Wait for the Completion ISR on channel 2. */\r
-                printf ("waiting for interrupt...\n"); \r
-                }\r
-\r
-            /* Check the status of the completed transfer */\r
-            if (irqRaised2 < 0)\r
-                {\r
-                /* Some error occured, break from the FOR loop. */\r
-#ifdef EDMA3_DRV_DEBUG\r
-                EDMA3_DRV_PRINTF ("\r\nedma3_test_with_chaining: Event Miss Occured!!!\r\n");\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-\r
-                /* Clear the error bits first */\r
-                result = EDMA3_DRV_clearErrorBits (hEdma, ch1Id);\r
-\r
-                break;\r
-                }\r
-            }\r
-        }\r
-\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Match the Source and Destination Buffers. */\r
-        if (result == EDMA3_DRV_SOK)\r
-            {\r
-            for (i = 0; i < (acnt*bcnt*ccnt); i++)\r
-                {\r
-                if (srcBuff1[i] != dstBuff1[i])\r
-                    {\r
-                    Istestpassed1 = 0;\r
-\r
-        #ifdef EDMA3_DRV_DEBUG\r
-                    EDMA3_DRV_PRINTF("edma3_test_with_chaining: Data write-read " \\r
-                                    "matching FAILED at i = %d " \\r
-                                    "(srcBuff1 -> dstBuff1)\r\n", i);\r
-        #endif  /* EDMA3_DRV_DEBUG */\r
-                    break;\r
-                    }\r
-                }\r
-            if (i == (acnt*bcnt*ccnt))\r
-                {\r
-                Istestpassed1 = 1u;\r
-                }\r
-\r
-\r
-            for (i = 0; i < (acnt*bcnt*ccnt); i++)\r
-                {\r
-                if (srcBuff2[i] != dstBuff2[i])\r
-                    {\r
-                    Istestpassed2 = 0;\r
-\r
-        #ifdef EDMA3_DRV_DEBUG\r
-                    EDMA3_DRV_PRINTF("edma3_test_with_chaining: Data write-read " \\r
-                                    "matching FAILED at i = %d " \\r
-                                    "(srcBuff2 -> dstBuff2)\r\n", i);\r
-        #endif  /* EDMA3_DRV_DEBUG */\r
-                    break;\r
-                    }\r
-                }\r
-            if (i == (acnt*bcnt*ccnt))\r
-                {\r
-                Istestpassed2 = 1u;\r
-                }\r
-            }\r
-\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Free the previously allocated channels. */\r
-        result = EDMA3_DRV_freeChannel (hEdma, ch1Id);\r
-        if (result != EDMA3_DRV_SOK)\r
-            {\r
-#ifdef EDMA3_DRV_DEBUG\r
-            EDMA3_DRV_PRINTF("edma3_test_with_chaining: EDMA3_DRV_freeChannel() for ch 1 FAILED, error code: %d\r\n", result);\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-            }\r
-        else\r
-            {\r
-            result = EDMA3_DRV_freeChannel (hEdma, ch2Id);\r
-            if (result != EDMA3_DRV_SOK)\r
-                {\r
-#ifdef EDMA3_DRV_DEBUG\r
-                EDMA3_DRV_PRINTF("edma3_test_with_chaining: EDMA3_DRV_freeChannel() for ch 2 FAILED, error code: %d\r\n", result);\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-                }\r
-            }\r
-        }\r
-    }\r
-\r
-\r
-    if((Istestpassed1 == 1u) && (Istestpassed2 == 1u))\r
-        {\r
-#ifdef EDMA3_DRV_DEBUG\r
-        EDMA3_DRV_PRINTF("edma3_test_with_chaining PASSED\r\n");\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-        }\r
-    else\r
-        {\r
-#ifdef EDMA3_DRV_DEBUG\r
-        EDMA3_DRV_PRINTF("edma3_test_with_chaining FAILED\r\n");\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-        result = ((EDMA3_DRV_SOK == result) ?\r
-                                EDMA3_DATA_MISMATCH_ERROR : result);\r
-        }\r
-\r
-\r
-    return result;\r
-    }\r
-\r
+/*
+ * dma_chain_test.c
+ *
+ * Test case demonstrating the usgae of DMA channels for transferring data 
+ * between two memory locations. The two DMA channels are chained to each other.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 
+ * 
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include "sample.h"
+
+extern signed char   _srcBuff1[MAX_BUFFER_SIZE];
+extern signed char   _srcBuff2[MAX_BUFFER_SIZE];
+extern signed char   _dstBuff1[MAX_BUFFER_SIZE];
+extern signed char   _dstBuff2[MAX_BUFFER_SIZE];
+
+extern signed char *srcBuff1;
+extern signed char *srcBuff2;
+extern signed char *dstBuff1;
+extern signed char *dstBuff2;
+
+
+/**
+ *  \brief   EDMA3 mem-to-mem data copy test case, using two DMA channels,
+ *              chained to each other.
+ *
+ *  \param  acnt        [IN]      Number of bytes in an array
+ *  \param  bcnt        [IN]      Number of arrays in a frame
+ *  \param  ccnt        [IN]      Number of frames in a block
+ *  \param  syncType    [IN]      Synchronization type (A/AB Sync)
+ *
+ *  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+EDMA3_DRV_Result edma3_test_with_chaining(
+                                                       EDMA3_DRV_Handle hEdma,
+                                unsigned int acnt,
+                                unsigned int bcnt,
+                                unsigned int ccnt,
+                                EDMA3_DRV_SyncType syncType)
+    {
+    EDMA3_DRV_ChainOptions chain = {EDMA3_DRV_TCCHEN_DIS,
+                                    EDMA3_DRV_ITCCHEN_DIS,
+                                    EDMA3_DRV_TCINTEN_DIS,
+                                    EDMA3_DRV_ITCINTEN_DIS};
+    EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    unsigned int BRCnt = 0;
+    int srcbidx = 0, desbidx = 0;
+    int srccidx = 0, descidx = 0;
+    unsigned int ch1Id = 0;
+    unsigned int ch2Id = 0;
+    unsigned int tcc1 = 0;
+    unsigned int tcc2 = 0;
+    int i;
+    unsigned int numenabled = 0;
+    unsigned int count;
+    unsigned int Istestpassed1 = 0u;
+    unsigned int Istestpassed2 = 0u;
+
+
+    srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
+    dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
+    srcBuff2 = (signed char*) GLOBAL_ADDR(_srcBuff2);
+    dstBuff2 = (signed char*) GLOBAL_ADDR(_dstBuff2);
+
+
+    /* Initalize source and destination buffers */
+    for (count = 0u; count < (acnt*bcnt*ccnt); count++)
+        {
+        srcBuff1[count] = (int)count+4;
+        srcBuff2[count] = (int)count+4;
+        /**
+         * No need to initialize the destination buffer as it is being invalidated.
+        dstBuff1[count] = initval;
+        dstBuff2[count] = initval;
+        */
+        }
+
+
+#ifdef EDMA3_ENABLE_DCACHE
+    /*
+    * Note: These functions are required if the buffer is in DDR.
+    * For other cases, where buffer is NOT in DDR, user
+    * may or may not require the below functions.
+    */
+    /* Flush the Source Buffers */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));
+        }
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt));
+        }
+
+    /* Invalidate the Destination Buffers */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));
+        }
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt));
+        }
+#endif  /* EDMA3_ENABLE_DCACHE */
+
+
+    /* Set B count reload as B count. */
+    BRCnt = bcnt;
+
+    /* Setting up the SRC/DES Index */
+    srcbidx = (int)acnt;
+    desbidx = (int)acnt;
+
+    if (syncType == EDMA3_DRV_SYNC_A)
+        {
+        /* A Sync Transfer Mode */
+        srccidx = (int)acnt;
+        descidx = (int)acnt;
+        }
+    else
+        {
+        /* AB Sync Transfer Mode */
+        srccidx = ((int)acnt * (int)bcnt);
+        descidx = ((int)acnt * (int)bcnt);
+        }
+
+
+    /* Transfer complete chaining enable. */
+    chain.tcchEn = EDMA3_DRV_TCCHEN_EN;
+    /* Intermediate transfer complete chaining enable. */
+    chain.itcchEn = EDMA3_DRV_ITCCHEN_EN;
+    /* Transfer complete interrupt is enabled. */
+    chain.tcintEn = EDMA3_DRV_TCINTEN_EN;
+    /* Intermediate transfer complete interrupt is disabled. */
+    chain.itcintEn = EDMA3_DRV_ITCINTEN_DIS;
+
+
+    /* Setup for Channel 1*/
+    tcc1 = EDMA3_DRV_TCC_ANY;
+    ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1,
+                                            (EDMA3_RM_EventQueue)0,
+                                            &callback1, NULL);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcParams (hEdma, ch1Id,
+                                        (unsigned int)(srcBuff1),
+                                        EDMA3_DRV_ADDR_MODE_INCR,
+                                        EDMA3_DRV_W8BIT);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setDestParams (hEdma, ch1Id,
+                                            (unsigned int)(dstBuff1),
+                                            EDMA3_DRV_ADDR_MODE_INCR,
+                                            EDMA3_DRV_W8BIT);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        if (syncType == EDMA3_DRV_SYNC_A)
+            {
+            result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
+                                                    ccnt,BRCnt,
+                                                    EDMA3_DRV_SYNC_A);
+            }
+        else
+            {
+            /* AB Sync Transfer Mode */
+            result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
+                                                    ccnt, BRCnt,
+                                                    EDMA3_DRV_SYNC_AB);
+            }
+        }
+
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Setup for Channel 2 */
+        tcc2 = EDMA3_DRV_TCC_ANY;
+        ch2Id = EDMA3_DRV_DMA_CHANNEL_ANY;
+
+        result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2,
+                                            (EDMA3_RM_EventQueue)0,
+                                            &callback2, NULL);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2),
+                                        EDMA3_DRV_ADDR_MODE_INCR,
+                                        EDMA3_DRV_W8BIT);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setDestParams (hEdma, ch2Id,
+                                            (unsigned int)(dstBuff2),
+                                            EDMA3_DRV_ADDR_MODE_INCR,
+                                            EDMA3_DRV_W8BIT);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result =  EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        if (syncType == EDMA3_DRV_SYNC_A)
+            {
+            result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
+                                                    ccnt, BRCnt,
+                                                    EDMA3_DRV_SYNC_A);
+            }
+        else
+            {
+            /* AB Sync Transfer Mode */
+            result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
+                                                    ccnt, BRCnt,
+                                                    EDMA3_DRV_SYNC_AB);
+            }
+        }
+
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /**
+         * Enable the Transfer Completion Interrupt on the Chained Channel
+         * (Ch 2).
+         */
+        result = EDMA3_DRV_setOptField (hEdma, ch2Id,
+                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /**
+         * Enable the Intermediate Transfer Completion Interrupt on the
+         * Chained Channel (Ch 2).
+         */
+        result = EDMA3_DRV_setOptField (hEdma, ch2Id,
+                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+        }
+
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Now chain the two channels together. */
+        result = EDMA3_DRV_chainChannel(hEdma, ch1Id, ch2Id,
+                                    (EDMA3_DRV_ChainOptions *)&chain);
+        }
+
+
+    /*Need to activate next param*/
+    if (syncType == EDMA3_DRV_SYNC_A)
+        {
+        numenabled = bcnt * ccnt;
+        }
+    else
+        {
+        /* AB Sync Transfer Mode */
+        numenabled = ccnt;
+        }
+
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        for (i = 0; i < numenabled; i++)
+            {
+            irqRaised2 = 0;
+
+            /*
+             * Now enable the transfer for Master channel as many times
+             * as calculated above.
+             */
+            result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
+                                                EDMA3_DRV_TRIG_MODE_MANUAL);
+            if (result != EDMA3_DRV_SOK)
+                {
+    #ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("error from edma3_test_with_chaining\n\r\n");
+    #endif  /* EDMA3_DRV_DEBUG */
+                break;
+                }
+
+
+            /**
+             * Transfer on the master channel (ch1Id) will finish after some
+             * time.
+             * Now, because of the enabling of intermediate chaining on channel
+             * 1, after the transfer gets over, a sync event will be sent
+             * to channel 2, which will trigger the transfer on it.
+             * Also, Final and Intermediate Transfer Complete
+             * Interrupts are enabled on channel 2, so we should wait for the
+             * completion ISR on channel 2 first, before proceeding
+             * ahead.
+             */
+            while (irqRaised2 == 0)
+                {
+                /* Wait for the Completion ISR on channel 2. */
+                printf ("waiting for interrupt...\n"); 
+                }
+
+            /* Check the status of the completed transfer */
+            if (irqRaised2 < 0)
+                {
+                /* Some error occured, break from the FOR loop. */
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("\r\nedma3_test_with_chaining: Event Miss Occured!!!\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+
+                /* Clear the error bits first */
+                result = EDMA3_DRV_clearErrorBits (hEdma, ch1Id);
+
+                break;
+                }
+            }
+        }
+
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Match the Source and Destination Buffers. */
+        if (result == EDMA3_DRV_SOK)
+            {
+            for (i = 0; i < (acnt*bcnt*ccnt); i++)
+                {
+                if (srcBuff1[i] != dstBuff1[i])
+                    {
+                    Istestpassed1 = 0;
+
+        #ifdef EDMA3_DRV_DEBUG
+                    EDMA3_DRV_PRINTF("edma3_test_with_chaining: Data write-read " \
+                                    "matching FAILED at i = %d " \
+                                    "(srcBuff1 -> dstBuff1)\r\n", i);
+        #endif  /* EDMA3_DRV_DEBUG */
+                    break;
+                    }
+                }
+            if (i == (acnt*bcnt*ccnt))
+                {
+                Istestpassed1 = 1u;
+                }
+
+
+            for (i = 0; i < (acnt*bcnt*ccnt); i++)
+                {
+                if (srcBuff2[i] != dstBuff2[i])
+                    {
+                    Istestpassed2 = 0;
+
+        #ifdef EDMA3_DRV_DEBUG
+                    EDMA3_DRV_PRINTF("edma3_test_with_chaining: Data write-read " \
+                                    "matching FAILED at i = %d " \
+                                    "(srcBuff2 -> dstBuff2)\r\n", i);
+        #endif  /* EDMA3_DRV_DEBUG */
+                    break;
+                    }
+                }
+            if (i == (acnt*bcnt*ccnt))
+                {
+                Istestpassed2 = 1u;
+                }
+            }
+
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Free the previously allocated channels. */
+        result = EDMA3_DRV_freeChannel (hEdma, ch1Id);
+        if (result != EDMA3_DRV_SOK)
+            {
+#ifdef EDMA3_DRV_DEBUG
+            EDMA3_DRV_PRINTF("edma3_test_with_chaining: EDMA3_DRV_freeChannel() for ch 1 FAILED, error code: %d\r\n", result);
+#endif  /* EDMA3_DRV_DEBUG */
+            }
+        else
+            {
+            result = EDMA3_DRV_freeChannel (hEdma, ch2Id);
+            if (result != EDMA3_DRV_SOK)
+                {
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF("edma3_test_with_chaining: EDMA3_DRV_freeChannel() for ch 2 FAILED, error code: %d\r\n", result);
+#endif  /* EDMA3_DRV_DEBUG */
+                }
+            }
+        }
+    }
+
+
+    if((Istestpassed1 == 1u) && (Istestpassed2 == 1u))
+        {
+#ifdef EDMA3_DRV_DEBUG
+        EDMA3_DRV_PRINTF("edma3_test_with_chaining PASSED\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+        }
+    else
+        {
+#ifdef EDMA3_DRV_DEBUG
+        EDMA3_DRV_PRINTF("edma3_test_with_chaining FAILED\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+        result = ((EDMA3_DRV_SOK == result) ?
+                                EDMA3_DATA_MISMATCH_ERROR : result);
+        }
+
+
+    return result;
+    }
+
index e1ee4c2e5b749b8e6405b8d97ecfc326c2779536..1fadeadd804ad6c9e94a25c4e3f9a9ba77e482ab 100755 (executable)
-/*\r
- * dma_link_test.c\r
- *\r
- * EDMA3 mem-to-mem data copy test case, using two DMA channels, linked to each\r
- * other.\r
- *\r
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
- *\r
- *\r
- *  Redistribution and use in source and binary forms, with or without\r
- *  modification, are permitted provided that the following conditions\r
- *  are met:\r
- *\r
- *    Redistributions of source code must retain the above copyright\r
- *    notice, this list of conditions and the following disclaimer.\r
- *\r
- *    Redistributions in binary form must reproduce the above copyright\r
- *    notice, this list of conditions and the following disclaimer in the\r
- *    documentation and/or other materials provided with the\r
- *    distribution.\r
- *\r
- *    Neither the name of Texas Instruments Incorporated nor the names of\r
- *    its contributors may be used to endorse or promote products derived\r
- *    from this software without specific prior written permission.\r
- *\r
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
-*/\r
-\r
-#include "sample.h"\r
-\r
-extern signed char   _srcBuff1[MAX_BUFFER_SIZE];\r
-extern signed char   _srcBuff2[MAX_BUFFER_SIZE];\r
-extern signed char   _dstBuff1[MAX_BUFFER_SIZE];\r
-extern signed char   _dstBuff2[MAX_BUFFER_SIZE];\r
-\r
-extern signed char *srcBuff1;\r
-extern signed char *srcBuff2;\r
-extern signed char *dstBuff1;\r
-extern signed char *dstBuff2;\r
-\r
-\r
-/**\r
- *  \brief   EDMA3 mem-to-mem data copy test case, using two DMA\r
- *              channels, linked to each other.\r
- *\r
- *  \param  acnt        [IN]      Number of bytes in an array\r
- *  \param  bcnt        [IN]      Number of arrays in a frame\r
- *  \param  ccnt        [IN]      Number of frames in a block\r
- *  \param  syncType    [IN]      Synchronization type (A/AB Sync)\r
- *\r
- *  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result edma3_test_with_link(\r
-                                               EDMA3_DRV_Handle hEdma,\r
-                           unsigned int acnt,\r
-                           unsigned int bcnt,\r
-                           unsigned int ccnt,\r
-                           EDMA3_DRV_SyncType syncType)\r
-    {\r
-    EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
-    EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};\r
-    unsigned int ch1Id = 0;\r
-    unsigned int ch2Id = 0;\r
-    unsigned int tcc1 = 0;\r
-    unsigned int tcc2 = 0;\r
-    int i;\r
-    unsigned int count;\r
-    unsigned int Istestpassed1 = 0u;\r
-    unsigned int Istestpassed2 = 0u;\r
-    unsigned int numenabled = 0;\r
-    unsigned int BRCnt = 0;\r
-    int srcbidx = 0, desbidx = 0;\r
-    int srccidx = 0, descidx = 0;\r
-\r
-\r
-    srcBuff1 = (signed char*) _srcBuff1;\r
-    dstBuff1 = (signed char*) _dstBuff1;\r
-    srcBuff2 = (signed char*) _srcBuff2;\r
-    dstBuff2 = (signed char*) _dstBuff2;\r
-\r
-\r
-    /* Initalize source and destination buffers */\r
-    for (count = 0u; count < (acnt*bcnt*ccnt); count++)\r
-        {\r
-        srcBuff1[count] = (int)count+1;\r
-        srcBuff2[count] = (int)count+1;\r
-        /**\r
-         * No need to initialize the destination buffer as it is being invalidated.\r
-        dstBuff1[count] = initval;\r
-        dstBuff2[count] = initval;\r
-        */\r
-        }\r
-\r
-\r
-#ifdef EDMA3_ENABLE_DCACHE\r
-    /*\r
-    * Note: These functions are required if the buffer is in DDR.\r
-    * For other cases, where buffer is NOT in DDR, user\r
-    * may or may not require the below functions.\r
-    */\r
-    /* Flush the Source Buffers */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));\r
-        }\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt));\r
-        }\r
-\r
-    /* Invalidate the Destination Buffers */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));\r
-        }\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt));\r
-        }\r
-#endif  /* EDMA3_ENABLE_DCACHE */\r
-\r
-\r
-    irqRaised1 = 0;\r
-    irqRaised2 = 0;\r
-\r
-    /* Set B count reload as B count. */\r
-    BRCnt = bcnt;\r
-\r
-    /* Setting up the SRC/DES Index */\r
-    srcbidx = (int)acnt;\r
-    desbidx = (int)acnt;\r
-    if (syncType == EDMA3_DRV_SYNC_A)\r
-        {\r
-        /* A Sync Transfer Mode */\r
-        srccidx = (int)acnt;\r
-        descidx = (int)acnt;\r
-        }\r
-    else\r
-        {\r
-        /* AB Sync Transfer Mode */\r
-        srccidx = ((int)acnt * (int)bcnt);\r
-        descidx = ((int)acnt * (int)bcnt);\r
-        }\r
-\r
-\r
-    /* Setup for Channel 1*/\r
-    tcc1 = EDMA3_DRV_TCC_ANY;\r
-    ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;\r
-\r
-    /* Request any DMA channel and any TCC */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1,\r
-                                            (EDMA3_RM_EventQueue)0,\r
-                                            &callback1, NULL);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Fill the PaRAM Set with transfer specific information */\r
-        paramSet.srcAddr    = (unsigned int)(srcBuff1);\r
-        paramSet.destAddr   = (unsigned int)(dstBuff1);\r
-\r
-        /**\r
-         * Be Careful !!!\r
-         * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767\r
-         * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767\r
-         */\r
-        paramSet.srcBIdx    = srcbidx;\r
-        paramSet.destBIdx   = desbidx;\r
-        paramSet.srcCIdx    = srccidx;\r
-        paramSet.destCIdx   = descidx;\r
-\r
-        /**\r
-         * Be Careful !!!\r
-         * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.\r
-         * ACNT/BCNT/CCNT must be greater than or equal to 1.\r
-         * Maximum number of bytes in an array (ACNT) is 65535 bytes\r
-         * Maximum number of arrays in a frame (BCNT) is 65535\r
-         * Maximum number of frames in a block (CCNT) is 65535\r
-         */\r
-        paramSet.aCnt       = acnt;\r
-        paramSet.bCnt       = bcnt;\r
-        paramSet.cCnt       = ccnt;\r
-\r
-        /* For AB-synchronized transfers, BCNTRLD is not used. */\r
-        paramSet.bCntReload = BRCnt;\r
-\r
-        paramSet.linkAddr   = 0xFFFFu;\r
-\r
-        /* Src & Dest are in INCR modes */\r
-        paramSet.opt &= 0xFFFFFFFCu;\r
-        /* Program the TCC */\r
-        paramSet.opt |= ((tcc1 << OPT_TCC_SHIFT) & OPT_TCC_MASK);\r
-\r
-        /* Enable Intermediate & Final transfer completion interrupt */\r
-        paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);\r
-        paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);\r
-\r
-        if (syncType == EDMA3_DRV_SYNC_A)\r
-            {\r
-            paramSet.opt &= 0xFFFFFFFBu;\r
-            }\r
-        else\r
-            {\r
-            /* AB Sync Transfer Mode */\r
-            paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);\r
-            }\r
-\r
-        /* Now, write the PaRAM Set. */\r
-        result = EDMA3_DRV_setPaRAM (hEdma, ch1Id, &paramSet);\r
-        }\r
-\r
-\r
-    /*\r
-     * There is another way to program the PaRAM Set using specific APIs\r
-     * for different PaRAM set entries. It gives user more control and easier\r
-     * to use interface. User can use any of the methods.\r
-     * Below is the alternative way to program the PaRAM Set.\r
-     */\r
-\r
-    /*\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (unsigned int)(srcBuff1),\r
-                                        EDMA3_DRV_ADDR_MODE_INCR,\r
-                                        EDMA3_DRV_W8BIT);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setDestParams (hEdma, ch1Id,\r
-                                            (unsigned int)(dstBuff1),\r
-                                            EDMA3_DRV_ADDR_MODE_INCR,\r
-                                            EDMA3_DRV_W8BIT);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result =  EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        if (syncType == EDMA3_DRV_SYNC_A)\r
-            {\r
-            result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,\r
-                                                ccnt, BRCnt,\r
-                                                EDMA3_DRV_SYNC_A);\r
-            }\r
-        else\r
-            {\r
-            result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,\r
-                                                ccnt, BRCnt,\r
-                                                EDMA3_DRV_SYNC_AB);\r
-            }\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setOptField (hEdma, ch1Id,\r
-                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setOptField (hEdma, ch1Id,\r
-                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);\r
-        }\r
-\r
-    */\r
-\r
-\r
-    /* Request any LINK channel and any TCC */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Setup for Channel 2 */\r
-        ch2Id   = EDMA3_DRV_LINK_CHANNEL;\r
-        tcc2    = EDMA3_DRV_TCC_ANY;\r
-\r
-        result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2,\r
-                                            (EDMA3_RM_EventQueue)0,\r
-                                            &callback1, NULL);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /*\r
-         * Fill the PaRAM Set for the LINK channel\r
-         * with transfer specific information.\r
-         */\r
-        paramSet.srcAddr    = (unsigned int)(srcBuff2);\r
-        paramSet.destAddr   = (unsigned int)(dstBuff2);\r
-\r
-        /**\r
-         * Be Careful !!!\r
-         * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767\r
-         * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767\r
-         */\r
-        paramSet.srcBIdx    = srcbidx;\r
-        paramSet.destBIdx   = desbidx;\r
-        paramSet.srcCIdx    = srccidx;\r
-        paramSet.destCIdx   = descidx;\r
-\r
-        /**\r
-         * Be Careful !!!\r
-         * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.\r
-         * ACNT/BCNT/CCNT must be greater than or equal to 1.\r
-         * Maximum number of bytes in an array (ACNT) is 65535 bytes\r
-         * Maximum number of arrays in a frame (BCNT) is 65535\r
-         * Maximum number of frames in a block (CCNT) is 65535\r
-         */\r
-        paramSet.aCnt       = acnt;\r
-        paramSet.bCnt       = bcnt;\r
-        paramSet.cCnt       = ccnt;\r
-\r
-        /* For AB-synchronized transfers, BCNTRLD is not used. */\r
-        paramSet.bCntReload = BRCnt;\r
-\r
-        paramSet.linkAddr   = 0xFFFFu;\r
-\r
-        /* Reset opt field first */\r
-        paramSet.opt = 0x0u;\r
-        /* Src & Dest are in INCR modes */\r
-        paramSet.opt &= 0xFFFFFFFCu;\r
-\r
-        /* Enable Intermediate & Final transfer completion interrupt */\r
-        paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);\r
-        paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);\r
-\r
-        if (syncType == EDMA3_DRV_SYNC_A)\r
-            {\r
-            paramSet.opt &= 0xFFFFFFFBu;\r
-            }\r
-        else\r
-            {\r
-            /* AB Sync Transfer Mode */\r
-            paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);\r
-            }\r
-\r
-        /* Now, write the PaRAM Set. */\r
-        result = EDMA3_DRV_setPaRAM(hEdma, ch2Id, &paramSet);\r
-        }\r
-\r
-\r
-    /*\r
-     * There is another way to program the PaRAM Set using specific APIs\r
-     * for different PaRAM set entries. It gives user more control and easier\r
-     * to use interface. User can use any of the methods.\r
-     * Below is the alternative way to program the PaRAM Set.\r
-     */\r
-\r
-    /*\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2),\r
-                                        EDMA3_DRV_ADDR_MODE_INCR,\r
-                                        EDMA3_DRV_W8BIT);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setDestParams (hEdma, ch2Id,\r
-                                        (unsigned int)(dstBuff2),\r
-                                        EDMA3_DRV_ADDR_MODE_INCR,\r
-                                        EDMA3_DRV_W8BIT);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result =  EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        if (syncType == EDMA3_DRV_SYNC_A)\r
-            {\r
-            result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,\r
-                                                    ccnt,\r
-                                                    BRCnt,EDMA3_DRV_SYNC_A);\r
-            }\r
-        else\r
-            {\r
-            result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,\r
-                                                    ccnt,\r
-                                                    BRCnt,EDMA3_DRV_SYNC_AB);\r
-            }\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setOptField (hEdma, ch2Id,\r
-                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setOptField (hEdma, ch2Id,\r
-                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);\r
-        }\r
-\r
-    */\r
-\r
-\r
-    /* Link both the channels. */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);\r
-        }\r
-\r
-\r
-    /*\r
-     * Since the transfer is going to happen in Manual mode of EDMA3\r
-     * operation, we have to 'Enable the Transfer' multiple times.\r
-     * Number of times depends upon the Mode (A/AB Sync)\r
-     * and the different counts.\r
-     */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /*Need to activate next param*/\r
-        if (syncType == EDMA3_DRV_SYNC_A)\r
-            {\r
-            numenabled = bcnt * ccnt;\r
-            }\r
-        else\r
-            {\r
-            /* AB Sync Transfer Mode */\r
-            numenabled = ccnt;\r
-            }\r
-\r
-        for (i = 0; i < numenabled; i++)\r
-            {\r
-            irqRaised1 = 0;\r
-\r
-            /*\r
-             * Now enable the transfer for Master channel as many times\r
-             * as calculated above.\r
-             */\r
-            result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,\r
-                                                EDMA3_DRV_TRIG_MODE_MANUAL);\r
-            if (result != EDMA3_DRV_SOK)\r
-                {\r
-#ifdef EDMA3_DRV_DEBUG\r
-                EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n");\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-                break;\r
-                }\r
-\r
-            while (irqRaised1 == 0)\r
-                {\r
-                /* Wait for the Completion ISR on Master Channel. */\r
-                printf ("waiting for interrupt...\n"); \r
-                }\r
-\r
-            /* Check the status of the completed transfer */\r
-            if (irqRaised1 < 0)\r
-                {\r
-                /* Some error occured, break from the FOR loop. */\r
-#ifdef EDMA3_DRV_DEBUG\r
-                EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n");\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-\r
-                /* Clear the error bits first */\r
-                result = EDMA3_DRV_clearErrorBits (hEdma, ch1Id);\r
-\r
-                break;\r
-                }\r
-            }\r
-        }\r
-\r
-\r
-    /**\r
-     * Now the transfer on Master channel is finished.\r
-     * Trigger next (LINK) param.\r
-     */\r
-    if (EDMA3_DRV_SOK == result)\r
-        {\r
-        for (i = 0; i < numenabled; i++)\r
-            {\r
-            irqRaised1 = 0;\r
-\r
-            /*\r
-             * Enable the transfer for LINK channel as many times\r
-             * as calculated above.\r
-             */\r
-            result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,\r
-                                                EDMA3_DRV_TRIG_MODE_MANUAL);\r
-            if (result != EDMA3_DRV_SOK)\r
-                {\r
-#ifdef EDMA3_DRV_DEBUG\r
-                EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n");\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-                break;\r
-                }\r
-\r
-            while (irqRaised1 == 0)\r
-                {\r
-                /* Wait for the Completion ISR on the Link Channel. */\r
-                printf ("waiting for interrupt...\n"); \r
-                }\r
-\r
-            /* Check the status of the completed transfer */\r
-            if (irqRaised1 < 0)\r
-                {\r
-                /* Some error occured, break from the FOR loop. */\r
-#ifdef EDMA3_DRV_DEBUG\r
-                EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n");\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-\r
-                /* Clear the error bits first */\r
-                result = EDMA3_DRV_clearErrorBits (hEdma, ch2Id);\r
-\r
-                break;\r
-                }\r
-            }\r
-        }\r
-\r
-\r
-\r
-    /* Match the Source and Destination Buffers. */\r
-    if (EDMA3_DRV_SOK == result)\r
-        {\r
-        for (i = 0; i < (acnt*bcnt*ccnt); i++)\r
-            {\r
-            if (srcBuff1[i] != dstBuff1[i])\r
-                {\r
-                Istestpassed1 = 0u;\r
-#ifdef EDMA3_DRV_DEBUG\r
-                EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \\r
-                                "matching FAILED at i = %d " \\r
-                                "(srcBuff1 -> dstBuff1)\r\n", i);\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-                break;\r
-                }\r
-            }\r
-        if (i == (acnt*bcnt*ccnt))\r
-            {\r
-            Istestpassed1 = 1u;\r
-            }\r
-\r
-\r
-        for (i = 0; i < (acnt*bcnt*ccnt); i++)\r
-            {\r
-            if (srcBuff2[i] != dstBuff2[i])\r
-                {\r
-                Istestpassed2 = 0;\r
-#ifdef EDMA3_DRV_DEBUG\r
-                EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \\r
-                            "matching FAILED at i = %d " \\r
-                            "(srcBuff2 -> dstBuff2)\r\n", i);\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-                break;\r
-                }\r
-            }\r
-        if (i == (acnt*bcnt*ccnt))\r
-            {\r
-            Istestpassed2 = 1u;\r
-            }\r
-\r
-\r
-        /* Free the previously allocated channels. */\r
-        result = EDMA3_DRV_freeChannel (hEdma, ch1Id);\r
-        if (result != EDMA3_DRV_SOK)\r
-            {\r
-#ifdef EDMA3_DRV_DEBUG\r
-            EDMA3_DRV_PRINTF("edma3_test_with_link: EDMA3_DRV_freeChannel() " \\r
-                                "for ch1 FAILED, error code: %d\r\n", result);\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-            }\r
-        else\r
-            {\r
-            result = EDMA3_DRV_freeChannel (hEdma, ch2Id);\r
-            if (result != EDMA3_DRV_SOK)\r
-                {\r
-#ifdef EDMA3_DRV_DEBUG\r
-                EDMA3_DRV_PRINTF("edma3_test_with_link: " \\r
-                                "EDMA3_DRV_freeChannel() for ch 2 FAILED, " \\r
-                                "error code: %d\r\n", result);\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-                }\r
-            }\r
-        }\r
-\r
-\r
-    if((Istestpassed1 == 1u) && (Istestpassed2 == 1u))\r
-        {\r
-#ifdef EDMA3_DRV_DEBUG\r
-        EDMA3_DRV_PRINTF("edma3_test_with_link PASSED\r\n");\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-        }\r
-    else\r
-        {\r
-#ifdef EDMA3_DRV_DEBUG\r
-        EDMA3_DRV_PRINTF("edma3_test_with_link FAILED\r\n");\r
-#endif  /* EDMA3_DRV_DEBUG */\r
-        result = ((EDMA3_DRV_SOK == result) ?\r
-                                EDMA3_DATA_MISMATCH_ERROR : result);\r
-        }\r
-\r
-\r
-    return result;\r
-}\r
-\r
-\r
+/*
+ * dma_link_test.c
+ *
+ * EDMA3 mem-to-mem data copy test case, using two DMA channels, linked to each
+ * other.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include "sample.h"
+
+extern signed char   _srcBuff1[MAX_BUFFER_SIZE];
+extern signed char   _srcBuff2[MAX_BUFFER_SIZE];
+extern signed char   _dstBuff1[MAX_BUFFER_SIZE];
+extern signed char   _dstBuff2[MAX_BUFFER_SIZE];
+
+extern signed char *srcBuff1;
+extern signed char *srcBuff2;
+extern signed char *dstBuff1;
+extern signed char *dstBuff2;
+
+
+/**
+ *  \brief   EDMA3 mem-to-mem data copy test case, using two DMA
+ *              channels, linked to each other.
+ *
+ *  \param  acnt        [IN]      Number of bytes in an array
+ *  \param  bcnt        [IN]      Number of arrays in a frame
+ *  \param  ccnt        [IN]      Number of frames in a block
+ *  \param  syncType    [IN]      Synchronization type (A/AB Sync)
+ *
+ *  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+EDMA3_DRV_Result edma3_test_with_link(
+                                               EDMA3_DRV_Handle hEdma,
+                           unsigned int acnt,
+                           unsigned int bcnt,
+                           unsigned int ccnt,
+                           EDMA3_DRV_SyncType syncType)
+    {
+    EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};
+    unsigned int ch1Id = 0;
+    unsigned int ch2Id = 0;
+    unsigned int tcc1 = 0;
+    unsigned int tcc2 = 0;
+    int i;
+    unsigned int count;
+    unsigned int Istestpassed1 = 0u;
+    unsigned int Istestpassed2 = 0u;
+    unsigned int numenabled = 0;
+    unsigned int BRCnt = 0;
+    int srcbidx = 0, desbidx = 0;
+    int srccidx = 0, descidx = 0;
+
+
+    srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
+    dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
+    srcBuff2 = (signed char*) GLOBAL_ADDR(_srcBuff2);
+    dstBuff2 = (signed char*) GLOBAL_ADDR(_dstBuff2);
+
+
+    /* Initalize source and destination buffers */
+    for (count = 0u; count < (acnt*bcnt*ccnt); count++)
+        {
+        srcBuff1[count] = (int)count+1;
+        srcBuff2[count] = (int)count+1;
+        /**
+         * No need to initialize the destination buffer as it is being invalidated.
+        dstBuff1[count] = initval;
+        dstBuff2[count] = initval;
+        */
+        }
+
+
+#ifdef EDMA3_ENABLE_DCACHE
+    /*
+    * Note: These functions are required if the buffer is in DDR.
+    * For other cases, where buffer is NOT in DDR, user
+    * may or may not require the below functions.
+    */
+    /* Flush the Source Buffers */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));
+        }
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt));
+        }
+
+    /* Invalidate the Destination Buffers */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));
+        }
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt));
+        }
+#endif  /* EDMA3_ENABLE_DCACHE */
+
+
+    irqRaised1 = 0;
+    irqRaised2 = 0;
+
+    /* Set B count reload as B count. */
+    BRCnt = bcnt;
+
+    /* Setting up the SRC/DES Index */
+    srcbidx = (int)acnt;
+    desbidx = (int)acnt;
+    if (syncType == EDMA3_DRV_SYNC_A)
+        {
+        /* A Sync Transfer Mode */
+        srccidx = (int)acnt;
+        descidx = (int)acnt;
+        }
+    else
+        {
+        /* AB Sync Transfer Mode */
+        srccidx = ((int)acnt * (int)bcnt);
+        descidx = ((int)acnt * (int)bcnt);
+        }
+
+
+    /* Setup for Channel 1*/
+    tcc1 = EDMA3_DRV_TCC_ANY;
+    ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;
+
+    /* Request any DMA channel and any TCC */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1,
+                                            (EDMA3_RM_EventQueue)0,
+                                            &callback1, NULL);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Fill the PaRAM Set with transfer specific information */
+        paramSet.srcAddr    = (unsigned int)(srcBuff1);
+        paramSet.destAddr   = (unsigned int)(dstBuff1);
+
+        /**
+         * Be Careful !!!
+         * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767
+         * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767
+         */
+        paramSet.srcBIdx    = srcbidx;
+        paramSet.destBIdx   = desbidx;
+        paramSet.srcCIdx    = srccidx;
+        paramSet.destCIdx   = descidx;
+
+        /**
+         * Be Careful !!!
+         * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
+         * ACNT/BCNT/CCNT must be greater than or equal to 1.
+         * Maximum number of bytes in an array (ACNT) is 65535 bytes
+         * Maximum number of arrays in a frame (BCNT) is 65535
+         * Maximum number of frames in a block (CCNT) is 65535
+         */
+        paramSet.aCnt       = acnt;
+        paramSet.bCnt       = bcnt;
+        paramSet.cCnt       = ccnt;
+
+        /* For AB-synchronized transfers, BCNTRLD is not used. */
+        paramSet.bCntReload = BRCnt;
+
+        paramSet.linkAddr   = 0xFFFFu;
+
+        /* Src & Dest are in INCR modes */
+        paramSet.opt &= 0xFFFFFFFCu;
+        /* Program the TCC */
+        paramSet.opt |= ((tcc1 << OPT_TCC_SHIFT) & OPT_TCC_MASK);
+
+        /* Enable Intermediate & Final transfer completion interrupt */
+        paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);
+        paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
+
+        if (syncType == EDMA3_DRV_SYNC_A)
+            {
+            paramSet.opt &= 0xFFFFFFFBu;
+            }
+        else
+            {
+            /* AB Sync Transfer Mode */
+            paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
+            }
+
+        /* Now, write the PaRAM Set. */
+        result = EDMA3_DRV_setPaRAM (hEdma, ch1Id, &paramSet);
+        }
+
+
+    /*
+     * There is another way to program the PaRAM Set using specific APIs
+     * for different PaRAM set entries. It gives user more control and easier
+     * to use interface. User can use any of the methods.
+     * Below is the alternative way to program the PaRAM Set.
+     */
+
+    /*
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (unsigned int)(srcBuff1),
+                                        EDMA3_DRV_ADDR_MODE_INCR,
+                                        EDMA3_DRV_W8BIT);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setDestParams (hEdma, ch1Id,
+                                            (unsigned int)(dstBuff1),
+                                            EDMA3_DRV_ADDR_MODE_INCR,
+                                            EDMA3_DRV_W8BIT);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result =  EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        if (syncType == EDMA3_DRV_SYNC_A)
+            {
+            result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
+                                                ccnt, BRCnt,
+                                                EDMA3_DRV_SYNC_A);
+            }
+        else
+            {
+            result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
+                                                ccnt, BRCnt,
+                                                EDMA3_DRV_SYNC_AB);
+            }
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setOptField (hEdma, ch1Id,
+                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setOptField (hEdma, ch1Id,
+                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+        }
+
+    */
+
+
+    /* Request any LINK channel and any TCC */
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Setup for Channel 2 */
+        ch2Id   = EDMA3_DRV_LINK_CHANNEL;
+        tcc2    = EDMA3_DRV_TCC_ANY;
+
+        result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2,
+                                            (EDMA3_RM_EventQueue)0,
+                                            &callback1, NULL);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /*
+         * Fill the PaRAM Set for the LINK channel
+         * with transfer specific information.
+         */
+        paramSet.srcAddr    = (unsigned int)(srcBuff2);
+        paramSet.destAddr   = (unsigned int)(dstBuff2);
+
+        /**
+         * Be Careful !!!
+         * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767
+         * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767
+         */
+        paramSet.srcBIdx    = srcbidx;
+        paramSet.destBIdx   = desbidx;
+        paramSet.srcCIdx    = srccidx;
+        paramSet.destCIdx   = descidx;
+
+        /**
+         * Be Careful !!!
+         * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
+         * ACNT/BCNT/CCNT must be greater than or equal to 1.
+         * Maximum number of bytes in an array (ACNT) is 65535 bytes
+         * Maximum number of arrays in a frame (BCNT) is 65535
+         * Maximum number of frames in a block (CCNT) is 65535
+         */
+        paramSet.aCnt       = acnt;
+        paramSet.bCnt       = bcnt;
+        paramSet.cCnt       = ccnt;
+
+        /* For AB-synchronized transfers, BCNTRLD is not used. */
+        paramSet.bCntReload = BRCnt;
+
+        paramSet.linkAddr   = 0xFFFFu;
+
+        /* Reset opt field first */
+        paramSet.opt = 0x0u;
+        /* Src & Dest are in INCR modes */
+        paramSet.opt &= 0xFFFFFFFCu;
+
+        /* Enable Intermediate & Final transfer completion interrupt */
+        paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);
+        paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
+
+        if (syncType == EDMA3_DRV_SYNC_A)
+            {
+            paramSet.opt &= 0xFFFFFFFBu;
+            }
+        else
+            {
+            /* AB Sync Transfer Mode */
+            paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
+            }
+
+        /* Now, write the PaRAM Set. */
+        result = EDMA3_DRV_setPaRAM(hEdma, ch2Id, &paramSet);
+        }
+
+
+    /*
+     * There is another way to program the PaRAM Set using specific APIs
+     * for different PaRAM set entries. It gives user more control and easier
+     * to use interface. User can use any of the methods.
+     * Below is the alternative way to program the PaRAM Set.
+     */
+
+    /*
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2),
+                                        EDMA3_DRV_ADDR_MODE_INCR,
+                                        EDMA3_DRV_W8BIT);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setDestParams (hEdma, ch2Id,
+                                        (unsigned int)(dstBuff2),
+                                        EDMA3_DRV_ADDR_MODE_INCR,
+                                        EDMA3_DRV_W8BIT);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result =  EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        if (syncType == EDMA3_DRV_SYNC_A)
+            {
+            result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
+                                                    ccnt,
+                                                    BRCnt,EDMA3_DRV_SYNC_A);
+            }
+        else
+            {
+            result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
+                                                    ccnt,
+                                                    BRCnt,EDMA3_DRV_SYNC_AB);
+            }
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setOptField (hEdma, ch2Id,
+                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setOptField (hEdma, ch2Id,
+                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+        }
+
+    */
+
+
+    /* Link both the channels. */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);
+        }
+
+
+    /*
+     * Since the transfer is going to happen in Manual mode of EDMA3
+     * operation, we have to 'Enable the Transfer' multiple times.
+     * Number of times depends upon the Mode (A/AB Sync)
+     * and the different counts.
+     */
+    if (result == EDMA3_DRV_SOK)
+        {
+        /*Need to activate next param*/
+        if (syncType == EDMA3_DRV_SYNC_A)
+            {
+            numenabled = bcnt * ccnt;
+            }
+        else
+            {
+            /* AB Sync Transfer Mode */
+            numenabled = ccnt;
+            }
+
+        for (i = 0; i < numenabled; i++)
+            {
+            irqRaised1 = 0;
+
+            /*
+             * Now enable the transfer for Master channel as many times
+             * as calculated above.
+             */
+            result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
+                                                EDMA3_DRV_TRIG_MODE_MANUAL);
+            if (result != EDMA3_DRV_SOK)
+                {
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+                break;
+                }
+
+            while (irqRaised1 == 0)
+                {
+                /* Wait for the Completion ISR on Master Channel. */
+                printf ("waiting for interrupt...\n"); 
+                }
+
+            /* Check the status of the completed transfer */
+            if (irqRaised1 < 0)
+                {
+                /* Some error occured, break from the FOR loop. */
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+
+                /* Clear the error bits first */
+                result = EDMA3_DRV_clearErrorBits (hEdma, ch1Id);
+
+                break;
+                }
+            }
+        }
+
+
+    /**
+     * Now the transfer on Master channel is finished.
+     * Trigger next (LINK) param.
+     */
+    if (EDMA3_DRV_SOK == result)
+        {
+        for (i = 0; i < numenabled; i++)
+            {
+            irqRaised1 = 0;
+
+            /*
+             * Enable the transfer for LINK channel as many times
+             * as calculated above.
+             */
+            result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
+                                                EDMA3_DRV_TRIG_MODE_MANUAL);
+            if (result != EDMA3_DRV_SOK)
+                {
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+                break;
+                }
+
+            while (irqRaised1 == 0)
+                {
+                /* Wait for the Completion ISR on the Link Channel. */
+                printf ("waiting for interrupt...\n"); 
+                }
+
+            /* Check the status of the completed transfer */
+            if (irqRaised1 < 0)
+                {
+                /* Some error occured, break from the FOR loop. */
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+
+                /* Clear the error bits first */
+                result = EDMA3_DRV_clearErrorBits (hEdma, ch2Id);
+
+                break;
+                }
+            }
+        }
+
+
+
+    /* Match the Source and Destination Buffers. */
+    if (EDMA3_DRV_SOK == result)
+        {
+        for (i = 0; i < (acnt*bcnt*ccnt); i++)
+            {
+            if (srcBuff1[i] != dstBuff1[i])
+                {
+                Istestpassed1 = 0u;
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \
+                                "matching FAILED at i = %d " \
+                                "(srcBuff1 -> dstBuff1)\r\n", i);
+#endif  /* EDMA3_DRV_DEBUG */
+                break;
+                }
+            }
+        if (i == (acnt*bcnt*ccnt))
+            {
+            Istestpassed1 = 1u;
+            }
+
+
+        for (i = 0; i < (acnt*bcnt*ccnt); i++)
+            {
+            if (srcBuff2[i] != dstBuff2[i])
+                {
+                Istestpassed2 = 0;
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \
+                            "matching FAILED at i = %d " \
+                            "(srcBuff2 -> dstBuff2)\r\n", i);
+#endif  /* EDMA3_DRV_DEBUG */
+                break;
+                }
+            }
+        if (i == (acnt*bcnt*ccnt))
+            {
+            Istestpassed2 = 1u;
+            }
+
+
+        /* Free the previously allocated channels. */
+        result = EDMA3_DRV_freeChannel (hEdma, ch1Id);
+        if (result != EDMA3_DRV_SOK)
+            {
+#ifdef EDMA3_DRV_DEBUG
+            EDMA3_DRV_PRINTF("edma3_test_with_link: EDMA3_DRV_freeChannel() " \
+                                "for ch1 FAILED, error code: %d\r\n", result);
+#endif  /* EDMA3_DRV_DEBUG */
+            }
+        else
+            {
+            result = EDMA3_DRV_freeChannel (hEdma, ch2Id);
+            if (result != EDMA3_DRV_SOK)
+                {
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF("edma3_test_with_link: " \
+                                "EDMA3_DRV_freeChannel() for ch 2 FAILED, " \
+                                "error code: %d\r\n", result);
+#endif  /* EDMA3_DRV_DEBUG */
+                }
+            }
+        }
+
+
+    if((Istestpassed1 == 1u) && (Istestpassed2 == 1u))
+        {
+#ifdef EDMA3_DRV_DEBUG
+        EDMA3_DRV_PRINTF("edma3_test_with_link PASSED\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+        }
+    else
+        {
+#ifdef EDMA3_DRV_DEBUG
+        EDMA3_DRV_PRINTF("edma3_test_with_link FAILED\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
+        result = ((EDMA3_DRV_SOK == result) ?
+                                EDMA3_DATA_MISMATCH_ERROR : result);
+        }
+
+
+    return result;
+}
+
+
index 7904913cc66a297cb5e3db07a9486fc9767d3b20..cf4deb8f8b8122c79fbe98d76d99be9b447b7589 100755 (executable)
@@ -258,12 +258,12 @@ EDMA3_DRV_Result edma3_test_ping_pong_mode(EDMA3_DRV_Handle hEdma)
     /* Number of triggers for EDMA3. */
     unsigned int numenabled = PING_PONG_NUM_TRIGGERS;
 
-    pingpongSrcBuf = (signed char*)_pingpongSrcBuf;
-    pingpongDestBuf = (signed char*)_pingpongDestBuf;
+    pingpongSrcBuf = (signed char*)GLOBAL_ADDR(_pingpongSrcBuf);
+    pingpongDestBuf = (signed char*)GLOBAL_ADDR(_pingpongDestBuf);
     pingpongSrcBufCopy = pingpongSrcBuf;
     pingpongDestBufCopy = pingpongDestBuf;
-    dstL1DBuff1 = (signed char*)_dstL1DBuff1;
-    dstL1DBuff2 = (signed char*)_dstL1DBuff2;
+    dstL1DBuff1 = (signed char*)GLOBAL_ADDR(_dstL1DBuff1);
+    dstL1DBuff2 = (signed char*)GLOBAL_ADDR(_dstL1DBuff2);
 
 
     /* Initalize source buffer for PING_PONG_DDR_BUFFER_SIZE bytes of data */
@@ -454,6 +454,7 @@ EDMA3_DRV_Result edma3_test_ping_pong_mode(EDMA3_DRV_Handle hEdma)
 
     if (result == EDMA3_DRV_SOK)
         {
+        irqRaised1 = 0;
         /* Param address successfully fetched. */
         param_handle = (EDMA3_DRV_ParamentryRegs *)phyaddress;
 
@@ -608,10 +609,28 @@ EDMA3_DRV_Result edma3_test_ping_pong_mode(EDMA3_DRV_Handle hEdma)
 #endif  /* EDMA3_DRV_DEBUG */
                 break;
                 }
-            }
-        }
 
+            /* Wait for the Completion ISR. */
+            while (irqRaised1 == 0u)
+                {
+                /* Wait for the Completion ISR. */
+                printf ("waiting for interrupt...\n");
+                }
+
+            /* Check the status of the completed transfer */
+            if (irqRaised1 < 0)
+                {
+                /* Some error occured, break from the FOR loop. */
+#ifdef EDMA3_DRV_DEBUG
+                EDMA3_DRV_PRINTF ("\r\nedma3_test: Event Miss Occured!!!\r\n");
+#endif  /* EDMA3_DRV_DEBUG */
 
+                /* Clear the error bits first */
+                result = EDMA3_DRV_clearErrorBits (hEdma, chId);
+                break;
+                }
+            }
+        }
 
     if (EDMA3_DRV_SOK == result)
         {
index d5af04410457374029689965cad07581e4150a28..9705f454d23ff9eafdaeab53286b2d9ea65ff150 100644 (file)
@@ -80,9 +80,8 @@ EDMA3_DRV_Result edma3_test_poll_mode(
     int srccidx = 0, descidx = 0;
 
 
-    srcBuff1 = (signed char*)_srcBuff1;
-    dstBuff1 = (signed char*)_dstBuff1;
-
+    srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
+    dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
 
     /* Initalize source and destination buffers */
     for (count = 0u; count < (acnt*bcnt*ccnt); count++)
index 840813366f816eed44c25aa1480b5301f4e15c8b..38b4f96c95f38e06b027847b6da9e74f4b5313e5 100755 (executable)
@@ -76,8 +76,8 @@ EDMA3_DRV_Result edma3_test(
     int srccidx = 0, descidx = 0;
 
 
-    srcBuff1 = (signed char*)_srcBuff1;
-    dstBuff1 = (signed char*)_dstBuff1;
+    srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
+    dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
 
 
     /* Initalize source and destination buffers */
index f3bf29561df7e79ed305ca4bbe22b013656abe54..e3db65674305919a5a9c901f3a8177d8004d4543 100644 (file)
 
 #include <xdc/std.h>
 #include <stdio.h>
+#include <string.h>
 #include <ti/sysbios/knl/Task.h>
 #include <ti/sysbios/BIOS.h>
 
 #include "sample.h"
 extern const unsigned int numEdma3Instances;
 
+/**
+ * DSP instance number on which the executable is running. Its value is
+ * determined by reading the processor specific register DNUM.
+ */
+unsigned int dsp_num_tmp;
+/* To find out the DSP# */
+extern unsigned short determineProcId();
+extern EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[][EDMA3_MAX_REGIONS];
+extern EDMA3_RM_InstanceInitConfig defInstInitConfig [][EDMA3_MAX_REGIONS];
+/* External Global Configuration Structure */
+extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[];
+
 EDMA3_DRV_Result edma3MemToMemCpytest (EDMA3_DRV_Handle hEdma);
 
+
 /*
  * Local References
  */
@@ -76,6 +90,8 @@ static void printWelcomeBanner(void)
     printf("*                            ***                              *\n\r");
     printf("*                                                             *\n\r");
     printf("*                     TI EDMA3 LOW LEVEL DRIVER               *\n\r");
+    printf("*                     Version: 0x%x                      *\n\r",EDMA3_DRV_getVersion());
+    printf("*    %s     *\n\r",EDMA3_DRV_getVersionStr());
     printf("*                                                             *\n\r");
     printf("*                                                             *\n\r");
     printf("*       For issues on TI EDMA3 LLD, contact TII PSP Team      *\n\r");
@@ -86,25 +102,112 @@ static void printWelcomeBanner(void)
     printf("\r\n\r\n");
     }
 
+/**
+ *  \brief   This function determines if testing on a EDMA3 instance will be bypassed.
+ *           When there are no EDMA channels allocated for the core from the given EDMA3 
+ *           instance, testing shall be bypassed.
+ *
+ *  \return  TRUE if bypass; FALSE if testing will done.
+ */
+unsigned int bypassCore(unsigned int edmaInstNum)
+{
+       unsigned int i, bypassFlag = 1;
+
+#ifndef EDMA3_DRV_USE_DEF_RM_CFG
+    EDMA3_DRV_InstanceInitConfig *instanceConfig = NULL;
+#else
+    EDMA3_RM_InstanceInitConfig  *rmInstInitCfg = NULL;
+#endif
+
+    /* DSP instance number */
+    dsp_num_tmp = determineProcId();
+
+#ifndef EDMA3_DRV_USE_DEF_RM_CFG
+       /* configuration structure for the Driver */
+       instanceConfig = &sampleInstInitConfig[edmaInstNum][dsp_num_tmp];
+       for (i = 0; i < EDMA3_MAX_DMA_CHAN_DWRDS; i++)
+       {
+           if(instanceConfig->ownDmaChannels[i])
+                       bypassFlag = 0;
+       }
+#else
+    /* configuration structure for the Driver */
+       rmInstInitCfg = &defInstInitConfig[edmaInstNum][dsp_num_tmp];
+       for (i = 0; i < EDMA3_MAX_DMA_CHAN_DWRDS; i++)
+       {
+           if(rmInstInitCfg->ownDmaChannels[i])
+                       bypassFlag = 0;
+       }
+#endif
+
+       return (bypassFlag);
+}
+
 
 void echo()
     {
     EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;
-       unsigned int i;
+       unsigned int i, bypass;
        unsigned int count=0;
-       EDMA3_DRV_Handle hEdma;
+       EDMA3_DRV_Handle hEdma[MAX_NUM_EDMA_INSTANCES];
+
+    memset(hEdma,0,sizeof(hEdma));
 
     /* Print the Welcome Message */
     printWelcomeBanner();
 
+    if(numEdma3Instances > MAX_NUM_EDMA_INSTANCES)
+    {
+        printf("Error numEdma3Instances:%d > MAX_NUM_EDMA_INSTANCES: %d\n", numEdma3Instances, MAX_NUM_EDMA_INSTANCES);
+        return;
+    }
+   
+    for (i = 0; i < numEdma3Instances; i++)
+    {
+        bypass = bypassCore(i);                
+        if(sampleEdma3GblCfgParams[i].numRegions > 1)
+        {
+            /* For multi core test init and de-init only once per test 
+             * for a core. 
+             */
+            if(bypass)
+                   {
+                       printf("Bypassing init for Core %d on EDMA3 instance %d\n", dsp_num_tmp, i);
+                continue;
+                   }
+
+            hEdma[i] = edma3init(i, &edmaResult);
+               if (hEdma[i])
+               {
+                   printf("edma3init() Passed\n");
+               }
+               else
+               {
+                   printf("edma3init() Failed, error code: %d\n", edmaResult);
+               }
+        }
+    }
+     
+
        for (count=0; count<10; count++)
                {
                printf ("\nCount = %d\n",count);
 
                for (i = 0; i < numEdma3Instances; i++)
+           {       
+
+            bypass = bypassCore(i);
+                       if(bypass)
+                       {
+                       printf("Bypass Core %d on EDMA3 instance %d\n", dsp_num_tmp, i);
+                       }
+                       else
                        {
-                   hEdma = edma3init(i, &edmaResult);
-                   if (hEdma)
+                if(sampleEdma3GblCfgParams[i].numRegions == 1)
+                {
+                    /* Single Region Config Do Init and Deinit test for each iteration */
+                    hEdma[i] = edma3init(i, &edmaResult);
+                       if (hEdma[i])
                        {
                        printf("edma3init() Passed\n");
                        }
@@ -112,44 +215,80 @@ void echo()
                        {
                        printf("edma3init() Failed, error code: %d\n", edmaResult);
                        }
+                }
+
+
+                       if (edmaResult == EDMA3_DRV_SOK)
+                           {
+                                   printf("\nStart -> EDMA3 Test memory to memory copy on Instance %d\n",i);
+
+                               edmaResult = edma3MemToMemCpytest(hEdma[i]);
+
+                           if (EDMA3_DRV_SOK != edmaResult)
+                              {
+                               /* Report EDMA Error */
+                               printf("edma3MemToMemCpytest() FAILED!!!!!!!!!!!!!!!!\n");
+                               return;
+                              }
+                           else
+                              {
+                               printf("edma3MemToMemCpytest() Passed\n");
+                              }
+
+                           printf("\nEnd -> EDMA3 Test memory to memory copy\n\n");
+                        }
+
+                if(sampleEdma3GblCfgParams[i].numRegions == 1)
+                {
+                    /* Single Region Config Do deinit */
+                    /* De-init EDMA3 */
+                       if (hEdma[i])
+                       {
+                               edmaResult = edma3deinit(i, hEdma[i]);
+                               if (edmaResult != EDMA3_DRV_SOK)
+                                       {
+                                       printf("edma3deinit() Failed, error code: %d\n", edmaResult);
+                                       }
+                               else
+                                       {
+                                       printf("edma3deinit() Passed\n");
+                                       }
+                    }
+                }
+            }          
+                               
+               }
+       }
 
-                   if (edmaResult == EDMA3_DRV_SOK)
-                       {
-                               printf("\nStart -> EDMA3 Test memory to memory copy on Instance %d\n",i);
-
-                           edmaResult = edma3MemToMemCpytest(hEdma);
-
-                       if (EDMA3_DRV_SOK != edmaResult)
-                          {
-                           /* Report EDMA Error */
-                           printf("edma3MemToMemCpytest() Failed\n");
-                          }
-                       else
-                          {
-                           printf("edma3MemToMemCpytest() Passed\n");
-                          }
-
-                       printf("\nEnd -> EDMA3 Test memory to memory copy\n\n");
-                       }
+    /* Start the Heart Beat Print */
+    tskHeartBit();
 
-                       /* De-init EDMA3 */
-                       if (hEdma)
-                               {
-                               edmaResult = edma3deinit(i, hEdma);
-                           if (edmaResult != EDMA3_DRV_SOK)
+    for (i = 0; i < numEdma3Instances; i++)
+    {  
+        if(sampleEdma3GblCfgParams[i].numRegions > 1)
+        {
+            if(bypass)
+                   {
+                       printf("Bypassing de-init for Core %d on EDMA3 instance %d\n", dsp_num_tmp, i);
+                continue;
+                   }
+    
+            /* Multi core Do deinit */
+            /* De-init EDMA3 */
+               if (hEdma[i])
+               {
+                       edmaResult = edma3deinit(i, hEdma[i]);
+                       if (edmaResult != EDMA3_DRV_SOK)
                                {
                                printf("edma3deinit() Failed, error code: %d\n", edmaResult);
                                }
-                           else
+                       else
                                {
                                printf("edma3deinit() Passed\n");
                                }
-                               }
-                       }
-               }
-
-    /* Start the Heart Beat Print */
-    tskHeartBit();
+            }
+        }
+    }
 
     return;
     }
index 15eec31549c2f5f35359322563cc69c2456ef4e8..8ede5f2c7350d9001fb2dc78e1267c2b0e0f27f1 100755 (executable)
-/*\r
- * qdma_link_test.c\r
- *\r
- * Test case demonstrating the usgae of QDMA channel for transferring data\r
- * between two memory locations. QDMA channel is linked to a LINK channel.\r
- *\r
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
- *\r
- *\r
- *  Redistribution and use in source and binary forms, with or without\r
- *  modification, are permitted provided that the following conditions\r
- *  are met:\r
- *\r
- *    Redistributions of source code must retain the above copyright\r
- *    notice, this list of conditions and the following disclaimer.\r
- *\r
- *    Redistributions in binary form must reproduce the above copyright\r
- *    notice, this list of conditions and the following disclaimer in the\r
- *    documentation and/or other materials provided with the\r
- *    distribution.\r
- *\r
- *    Neither the name of Texas Instruments Incorporated nor the names of\r
- *    its contributors may be used to endorse or promote products derived\r
- *    from this software without specific prior written permission.\r
- *\r
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
-*/\r
-\r
-#include "sample.h"\r
-\r
-extern signed char   _srcBuff1[MAX_BUFFER_SIZE];\r
-extern signed char   _srcBuff2[MAX_BUFFER_SIZE];\r
-extern signed char   _dstBuff1[MAX_BUFFER_SIZE];\r
-extern signed char   _dstBuff2[MAX_BUFFER_SIZE];\r
-\r
-extern signed char *srcBuff1;\r
-extern signed char *srcBuff2;\r
-extern signed char *dstBuff1;\r
-extern signed char *dstBuff2;\r
-\r
-/**\r
- *  \brief   EDMA3 mem-to-mem data copy test case, using a QDMA channel,\r
- *              linked to another LINK channel.\r
- *\r
- *  \param  acnt        [IN]      Number of bytes in an array\r
- *  \param  bcnt        [IN]      Number of arrays in a frame\r
- *  \param  ccnt        [IN]      Number of frames in a block\r
- *  \param  syncType    [IN]      Synchronization type (A/AB Sync)\r
- *\r
- *  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result qdma_test_with_link(\r
-                                       EDMA3_DRV_Handle hEdma,\r
-                    unsigned int acnt,\r
-                    unsigned int bcnt,\r
-                    unsigned int ccnt,\r
-                    EDMA3_DRV_SyncType syncType)\r
-    {\r
-    EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
-    unsigned int i;\r
-    unsigned int count;\r
-    unsigned int Istestpassed1 = 0u;\r
-    unsigned int Istestpassed2 = 0u;\r
-    unsigned int qCh1Id=0;\r
-    unsigned int qTcc1 = 0;\r
-    unsigned int qCh2Id=0;\r
-    unsigned int qTcc2 = 0;\r
-    unsigned int BRCnt = 0;\r
-    int srcbidx = 0, desbidx = 0;\r
-    int srccidx = 0, descidx = 0;\r
-    unsigned int numenabled = 0;\r
-    static signed char* tmpSrcBuff1 = NULL;\r
-    static signed char* tmpDstBuff1 = NULL;\r
-    static signed char* tmpSrcBuff2 = NULL;\r
-    static signed char* tmpDstBuff2 = NULL;\r
-    unsigned int abCNT = 0;\r
-    unsigned int bcntReloadLinkField = 0x0u;\r
-\r
-\r
-    srcBuff1 = (signed char*) _srcBuff1;\r
-    dstBuff1 = (signed char*) _dstBuff1;\r
-    srcBuff2 = (signed char*) _srcBuff2;\r
-    dstBuff2 = (signed char*) _dstBuff2;\r
-\r
-\r
-    /* Store the original pointers for future usage. */\r
-    tmpSrcBuff1 = srcBuff1;\r
-    tmpDstBuff1 = dstBuff1;\r
-    tmpSrcBuff2 = srcBuff2;\r
-    tmpDstBuff2 = dstBuff2;\r
-\r
-\r
-    /* Initalize source and destination buffers */\r
-    for (count= 0u; count < (acnt*bcnt*ccnt); count++)\r
-        {\r
-        srcBuff1[count] = (int)count+3;\r
-        srcBuff2[count] = (int)count+3;\r
-        /**\r
-         * No need to initialize the destination buffer as it is being invalidated.\r
-        dstBuff1[count] = initval;\r
-        dstBuff2[count] = initval;\r
-        */\r
-        }\r
-\r
-\r
-#ifdef EDMA3_ENABLE_DCACHE\r
-    /*\r
-    * Note: These functions are required if the buffer is in DDR.\r
-    * For other cases, where buffer is NOT in DDR, user\r
-    * may or may not require the below functions.\r
-    */\r
-    /* Flush the Source Buffers */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));\r
-        }\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt));\r
-        }\r
-\r
-    /* Invalidate the Destination Buffers */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));\r
-        }\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt));\r
-        }\r
-#endif  /* EDMA3_ENABLE_DCACHE */\r
-\r
-\r
-    /* Set B count reload as B count. */\r
-    BRCnt = bcnt;\r
-\r
-    /* Setting up the SRC/DES Index */\r
-    srcbidx = (int)acnt;\r
-    desbidx = (int)acnt;\r
-\r
-    if (syncType == EDMA3_DRV_SYNC_A)\r
-        {\r
-        /* A Sync Transfer Mode */\r
-        srccidx = (int)acnt;\r
-        descidx = (int)acnt;\r
-        }\r
-    else\r
-        {\r
-        /* AB Sync Transfer Mode */\r
-        srccidx = ((int)acnt * (int)bcnt);\r
-        descidx = ((int)acnt * (int)bcnt);\r
-        }\r
-\r
-\r
-    /* Setup for any QDMA Channel */\r
-    qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;\r
-    qTcc1 = EDMA3_DRV_TCC_ANY;\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,\r
-                                        (EDMA3_RM_EventQueue)0,\r
-                                        &callback1, NULL);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Setup for Channel 2 (Link Channel) */\r
-        qCh2Id = EDMA3_DRV_LINK_CHANNEL;\r
-        qTcc2 = EDMA3_DRV_TCC_ANY;\r
-\r
-        result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2,\r
-                                            (EDMA3_RM_EventQueue)0,\r
-                                            &callback1, NULL);\r
-        }\r
-\r
-    /* Configure the Link Channel first */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id,\r
-                                        (unsigned int)(srcBuff2),\r
-                                        EDMA3_DRV_ADDR_MODE_INCR,\r
-                                        EDMA3_DRV_W8BIT);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setDestParams (hEdma, qCh2Id,\r
-                                            (unsigned int)(dstBuff2),\r
-                                            EDMA3_DRV_ADDR_MODE_INCR,\r
-                                            EDMA3_DRV_W8BIT);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        if (syncType == EDMA3_DRV_SYNC_A)\r
-            {\r
-            result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt,\r
-                                                    ccnt, BRCnt,\r
-                                                    EDMA3_DRV_SYNC_A);\r
-            }\r
-        else\r
-            {\r
-            /* AB Sync Transfer Mode */\r
-            result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt,\r
-                                                    ccnt, BRCnt,\r
-                                                    EDMA3_DRV_SYNC_AB);\r
-            }\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Enable the Transfer Completion Interrupt on Link Channel */\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh2Id,\r
-                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /**\r
-         * Enable the Intermediate Transfer Completion Interrupt on Link\r
-         * Channel.\r
-         */\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh2Id,\r
-                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Link both the channels. */\r
-        result = EDMA3_DRV_linkChannel (hEdma, qCh1Id, qCh2Id);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /**\r
-         * Now configure the QDMA channel. Here lies the trick. Since QDMA\r
-         * channel is linked to another DMA channel, as soon as transfer on\r
-         * QDMA channel is finished, static field being NOT SET, the associated\r
-         * PaRAM Set will be reloaded with the Linked PaRAM Set. Now, as the\r
-         * reload occurs, the QDMA channel will be triggered due to the write\r
-         * on a specific Trigger Word. We want the trigger to happen immediately\r
-         * after the write, so the trigger word should be chosen in such a way\r
-         * that it should trigger after the COMPLETE PaRAM Set will get copied\r
-         * onto the QDMA Channel PaRAM Set. In that case, only ONE option is\r
-         * there to choose the CCNT as the trigger word. All other trigger\r
-         * words will cause the trigger happen in-between the PaRAM Set is\r
-         * loading. So Set the trigger word as CCNT.\r
-         */\r
-        result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,\r
-                                            EDMA3_RM_QDMA_TRIG_CCNT);\r
-        }\r
-\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);\r
-        }\r
-\r
-    abCNT = acnt | ((bcnt & 0xFFFFu) << 16u);\r
-\r
-    /* Write ACNT and BCNT */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id,\r
-                                            EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT,\r
-                                            abCNT);\r
-        }\r
-\r
-    /* Set the SYNC Mode (A/AB Sync) */\r
-    if (syncType == EDMA3_DRV_SYNC_A)\r
-        {\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
-                                        EDMA3_DRV_OPT_FIELD_SYNCDIM, 0u);\r
-        }\r
-    else\r
-        {\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
-                                        EDMA3_DRV_OPT_FIELD_SYNCDIM, 1u);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Enable Transfer Completion Interrupt */\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
-                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Enable Intermediate Transfer Completion Interrupt */\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
-                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Set Source Transfer Mode as Increment Mode. */\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM,\r
-                                        EDMA3_DRV_ADDR_MODE_INCR);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Set Destination Transfer Mode as Increment Mode. */\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM,\r
-                                        EDMA3_DRV_ADDR_MODE_INCR);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Get Link Address. */\r
-        result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id,\r
-                                        EDMA3_DRV_PARAM_FIELD_LINKADDR,\r
-                                        &bcntReloadLinkField);\r
-        }\r
-\r
-    bcntReloadLinkField = (bcntReloadLinkField | (BRCnt << 16));\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Set B Count Reload & Link Address. */\r
-        result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id,\r
-                                        EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD,\r
-                                        bcntReloadLinkField);\r
-        }\r
-\r
-\r
-    /*Need to activate next param*/\r
-    if (syncType == EDMA3_DRV_SYNC_A)\r
-        {\r
-        numenabled = bcnt * ccnt;\r
-        }\r
-    else\r
-        {\r
-        /* AB Sync Transfer Mode */\r
-        numenabled = ccnt;\r
-        }\r
-\r
-\r
-    if (numenabled == 1u)\r
-        {\r
-        /**\r
-         * If only one Sync event is required, make the PaRAM Set associated\r
-         * with the LINK channel as Static.\r
-         */\r
-        if (result == EDMA3_DRV_SOK)\r
-            {\r
-            result = EDMA3_DRV_setOptField (hEdma, qCh2Id,\r
-                                            EDMA3_DRV_OPT_FIELD_STATIC, 1u);\r
-            }\r
-\r
-            /**\r
-             * Be Careful!!!\r
-             * PaRAM Set associated with the Master Channel should NOT be\r
-             * set as Static, otherwise the reload will not occur.\r
-             */\r
-        }\r
-\r
-\r
-\r
-    /*\r
-     * Since the transfer is going to happen in QDMA mode of EDMA3\r
-     * operation, we have to "Trigger" the transfer multiple times.\r
-     * Number of times depends upon the Mode (A/AB Sync)\r
-     * and the different counts.\r
-     */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        for (i = 0u; i < numenabled; i++)\r
-            {\r
-            irqRaised1 = 0u;\r
-\r
-            /* Write to the Source Address */\r
-            result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,\r
-                                            (unsigned int)(srcBuff1),\r
-                                            EDMA3_DRV_ADDR_MODE_INCR,\r
-                                            EDMA3_DRV_W8BIT);\r
-            if (result != EDMA3_DRV_SOK)\r
-                {\r
-                printf ("error from qdma_test_with_link\r\n\r\n");\r
-                return result;\r
-                }\r
-\r
-\r
-            /* Write to the Destination Address */\r
-            result = EDMA3_DRV_setDestParams(hEdma, qCh1Id,\r
-                                                (unsigned int)(dstBuff1),\r
-                                                EDMA3_DRV_ADDR_MODE_INCR,\r
-                                                EDMA3_DRV_W8BIT);\r
-            if (result != EDMA3_DRV_SOK)\r
-                {\r
-                printf ("error from qdma_test_with_link\r\n\r\n");\r
-                return result;\r
-                }\r
-\r
-\r
-            /* Now write to the Trigger Word i.e. CCNT. */\r
-            result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_CCNT, ccnt);\r
-            if (result != EDMA3_DRV_SOK)\r
-                {\r
-                printf ("error from qdma_test_with_link\r\n\r\n");\r
-                return result;\r
-                }\r
-\r
-\r
-            /* After this, transfer will start. */\r
-            while (irqRaised1 == 0)\r
-                {\r
-                /* Wait for the Completion ISR for the Master QDMA Channel. */\r
-                printf ("waiting for interrupt...\n"); \r
-                }\r
-\r
-\r
-            /* Check the status of the completed transfer */\r
-            if (irqRaised1 < 0)\r
-                {\r
-                /* Some error occured, break from the FOR loop. */\r
-                printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n");\r
-\r
-                /* Clear the error bits first */\r
-                result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);\r
-\r
-                break;\r
-                }\r
-\r
-\r
-            /**\r
-             * Now, update the source and destination addresses for next\r
-             * "Trigger".\r
-             */\r
-            srcBuff1 += srccidx;\r
-            dstBuff1 += descidx;\r
-\r
-\r
-            /**\r
-             * Read the current C Count from the PaRAM Set and write it back.\r
-             * In this way, we would write the correct CCNT every time and\r
-             * trigger the transfer also. Since CC will decrement the CCNT\r
-             * after every (ACNT * BCNT) bytes of data transfer, we can use\r
-             * that decremented value to trigger the next transfer.\r
-             * Another option is to take count of CCNT manually (in your code)\r
-             * and write that value.\r
-             * First option seems less error prone.\r
-             */\r
-            result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id, EDMA3_DRV_PARAM_FIELD_CCNT, &ccnt);\r
-            if (result != EDMA3_DRV_SOK)\r
-                {\r
-                printf ("error from qdma_test_with_link\r\n\r\n");\r
-                return result;\r
-                }\r
-            }\r
-        }\r
-\r
-\r
-    /**\r
-     * Transfer on the QDMA channel has finished and Link\r
-     * PaRAM Set is loaded on the QDMA channel PaRAM Set.\r
-     * Now for the transfers on the LINK channel,\r
-     * if only one "TRIGGER" is required,\r
-     * that has already been provided by the PaRAM Set\r
-     * upload.\r
-     * For other triggers, we will take care.\r
-     */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /**\r
-         * One trigger has been provided already, so first wait for\r
-         * that transfer to complete.\r
-         */\r
-        while (irqRaised1 == 0)\r
-            {\r
-            /* Wait for the Completion ISR for the Master QDMA Channel. */\r
-            printf ("waiting for interrupt...\n");     \r
-            }\r
-\r
-        /* Check the status of the completed transfer */\r
-        if (irqRaised1 < 0)\r
-            {\r
-            /* Some error occured, clear the error bits. */\r
-            printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n");\r
-\r
-            /* Clear the error bits first */\r
-            result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);\r
-            }\r
-\r
-\r
-        if (numenabled == 1u)\r
-            {\r
-            /**\r
-             * Only 1 trigger was required which has been provided\r
-             * already. No need to do anything.\r
-             */\r
-            }\r
-        else\r
-            {\r
-            /**\r
-             * One trigger has been provided already, so take that into account.\r
-             */\r
-            numenabled -= 1u;\r
-\r
-            for (i = 0u; i < numenabled; i++)\r
-                {\r
-                irqRaised1 = 0u;\r
-\r
-                if (i == (numenabled - 1u))\r
-                    {\r
-                    /**\r
-                     * Before providing the last trigger,\r
-                     * make the PaRAM Set static.\r
-                     */\r
-                    result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
-                                            EDMA3_DRV_OPT_FIELD_STATIC, 1u);\r
-                    }\r
-\r
-                /**\r
-                 * Now, update the source and destination addresses for next\r
-                 * "Trigger".\r
-                 */\r
-                srcBuff2 += srccidx;\r
-                dstBuff2 += descidx;\r
-\r
-\r
-                /**\r
-                 * Read the current C Count from the PaRAM Set and write it back.\r
-                 * In this way, we would write the correct CCNT every time and\r
-                 * trigger the transfer also.\r
-                 */\r
-                result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id, EDMA3_DRV_PARAM_FIELD_CCNT, &ccnt);\r
-                if (result != EDMA3_DRV_SOK)\r
-                    {\r
-                    printf ("error from qdma_test_with_link\r\n\r\n");\r
-                    return result;\r
-                    }\r
-\r
-\r
-                /* Write to the Source Address */\r
-                result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,\r
-                                                (unsigned int)(srcBuff2),\r
-                                                EDMA3_DRV_ADDR_MODE_INCR,\r
-                                                EDMA3_DRV_W8BIT);\r
-                if (result != EDMA3_DRV_SOK)\r
-                    {\r
-                    printf ("error from qdma_test_with_link\r\n\r\n");\r
-                    return result;\r
-                    }\r
-\r
-\r
-                /* Write to the Destination Address */\r
-                result = EDMA3_DRV_setDestParams(hEdma, qCh1Id,\r
-                                                    (unsigned int)(dstBuff2),\r
-                                                    EDMA3_DRV_ADDR_MODE_INCR,\r
-                                                    EDMA3_DRV_W8BIT);\r
-                if (result != EDMA3_DRV_SOK)\r
-                    {\r
-                    printf ("error from qdma_test_with_link\r\n\r\n");\r
-                    return result;\r
-                    }\r
-\r
-\r
-                /* Now write to the Trigger Word i.e. CCNT. */\r
-                result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_CCNT, ccnt);\r
-                if (result != EDMA3_DRV_SOK)\r
-                    {\r
-                    printf ("error from qdma_test_with_link\r\n\r\n");\r
-                    return result;\r
-                    }\r
-\r
-\r
-                /* After this, transfer will start. */\r
-                while (irqRaised1 == 0)\r
-                    {\r
-                    /* Wait for the Completion ISR for the Link Channel. */\r
-                       printf ("waiting for interrupt...\n");  \r
-                    }\r
-\r
-\r
-                /* Check the status of the completed transfer */\r
-                if (irqRaised1 < 0)\r
-                    {\r
-                    /* Some error occured, break from the FOR loop. */\r
-                    printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n");\r
-\r
-                    /* Clear the error bits first */\r
-                    result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);\r
-\r
-                    break;\r
-                    }\r
-                }\r
-            }\r
-        }\r
-\r
-\r
-    /* Restore the src and dest buffers */\r
-    srcBuff1 = tmpSrcBuff1;\r
-    dstBuff1 = tmpDstBuff1;\r
-    srcBuff2 = tmpSrcBuff2;\r
-    dstBuff2 = tmpDstBuff2;\r
-\r
-\r
-    /* Match the Source and Destination Buffers. */\r
-    if (EDMA3_DRV_SOK == result)\r
-        {\r
-        for (i = 0; i < (acnt*bcnt*ccnt); i++)\r
-            {\r
-            if (srcBuff1[i] != dstBuff1[i])\r
-                {\r
-                Istestpassed1 = 0;\r
-                printf("qdma_test_with_link: Data write-read " \\r
-                                "matching FAILED at i = %d " \\r
-                                "(srcBuff1 -> dstBuff1)\r\r\n", i);\r
-                break;\r
-                }\r
-            }\r
-        if (i == (acnt*bcnt*ccnt))\r
-            {\r
-            Istestpassed1 = 1u;\r
-            }\r
-\r
-\r
-        for (i = 0; i < (acnt*bcnt*ccnt); i++)\r
-            {\r
-            if (srcBuff2[i] != dstBuff2[i])\r
-                {\r
-                Istestpassed2 = 0;\r
-                printf("qdma_test_with_link: Data write-read " \\r
-                                "matching FAILED at i = %d " \\r
-                                "(srcBuff2 -> dstBuff2)\r\n", i);\r
-                break;\r
-                }\r
-            }\r
-        if (i == (acnt*bcnt*ccnt))\r
-            {\r
-            Istestpassed2 = 1u;\r
-            }\r
-        }\r
-\r
-\r
-    if (EDMA3_DRV_SOK == result)\r
-        {\r
-        /* Free the previously allocated channels. */\r
-        result = EDMA3_DRV_freeChannel (hEdma, qCh1Id);\r
-        if (result != EDMA3_DRV_SOK)\r
-            {\r
-            printf("qdma_test_with_link: EDMA3_DRV_freeChannel() for qCh1Id FAILED, error code: %d\r\n", result);\r
-            }\r
-        else\r
-            {\r
-            result = EDMA3_DRV_freeChannel (hEdma, qCh2Id);\r
-            if (result != EDMA3_DRV_SOK)\r
-                {\r
-                printf("qdma_test_with_link: EDMA3_DRV_freeChannel() for qCh2Id FAILED, error code: %d\r\n", result);\r
-                }\r
-            }\r
-        }\r
-\r
-\r
-    if((Istestpassed1 == 1u) && (Istestpassed2 == 1u))\r
-        {\r
-        printf("qdma_test_with_link PASSED\r\n");\r
-        }\r
-    else\r
-        {\r
-        printf("qdma_test_with_link FAILED\r\n");\r
-        result = ((EDMA3_DRV_SOK == result) ?\r
-                                EDMA3_DATA_MISMATCH_ERROR : result);\r
-        }\r
-\r
-\r
-    return result;\r
-    }\r
-\r
+/*
+ * qdma_link_test.c
+ *
+ * Test case demonstrating the usgae of QDMA channel for transferring data
+ * between two memory locations. QDMA channel is linked to a LINK channel.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include "sample.h"
+
+extern signed char   _srcBuff1[MAX_BUFFER_SIZE];
+extern signed char   _srcBuff2[MAX_BUFFER_SIZE];
+extern signed char   _dstBuff1[MAX_BUFFER_SIZE];
+extern signed char   _dstBuff2[MAX_BUFFER_SIZE];
+
+extern signed char *srcBuff1;
+extern signed char *srcBuff2;
+extern signed char *dstBuff1;
+extern signed char *dstBuff2;
+
+/**
+ *  \brief   EDMA3 mem-to-mem data copy test case, using a QDMA channel,
+ *              linked to another LINK channel.
+ *
+ *  \param  acnt        [IN]      Number of bytes in an array
+ *  \param  bcnt        [IN]      Number of arrays in a frame
+ *  \param  ccnt        [IN]      Number of frames in a block
+ *  \param  syncType    [IN]      Synchronization type (A/AB Sync)
+ *
+ *  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+EDMA3_DRV_Result qdma_test_with_link(
+                                       EDMA3_DRV_Handle hEdma,
+                    unsigned int acnt,
+                    unsigned int bcnt,
+                    unsigned int ccnt,
+                    EDMA3_DRV_SyncType syncType)
+    {
+    EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    unsigned int i;
+    unsigned int count;
+    unsigned int Istestpassed1 = 0u;
+    unsigned int Istestpassed2 = 0u;
+    unsigned int qCh1Id=0;
+    unsigned int qTcc1 = 0;
+    unsigned int qCh2Id=0;
+    unsigned int qTcc2 = 0;
+    unsigned int BRCnt = 0;
+    int srcbidx = 0, desbidx = 0;
+    int srccidx = 0, descidx = 0;
+    unsigned int numenabled = 0;
+    static signed char* tmpSrcBuff1 = NULL;
+    static signed char* tmpDstBuff1 = NULL;
+    static signed char* tmpSrcBuff2 = NULL;
+    static signed char* tmpDstBuff2 = NULL;
+    unsigned int abCNT = 0;
+    unsigned int bcntReloadLinkField = 0x0u;
+
+
+    srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
+    dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
+    srcBuff2 = (signed char*) GLOBAL_ADDR(_srcBuff2);
+    dstBuff2 = (signed char*) GLOBAL_ADDR(_dstBuff2);
+
+
+    /* Store the original pointers for future usage. */
+    tmpSrcBuff1 = srcBuff1;
+    tmpDstBuff1 = dstBuff1;
+    tmpSrcBuff2 = srcBuff2;
+    tmpDstBuff2 = dstBuff2;
+
+
+    /* Initalize source and destination buffers */
+    for (count= 0u; count < (acnt*bcnt*ccnt); count++)
+        {
+        srcBuff1[count] = (int)count+3;
+        srcBuff2[count] = (int)count+3;
+        /**
+         * No need to initialize the destination buffer as it is being invalidated.
+        dstBuff1[count] = initval;
+        dstBuff2[count] = initval;
+        */
+        }
+
+
+#ifdef EDMA3_ENABLE_DCACHE
+    /*
+    * Note: These functions are required if the buffer is in DDR.
+    * For other cases, where buffer is NOT in DDR, user
+    * may or may not require the below functions.
+    */
+    /* Flush the Source Buffers */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));
+        }
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheFlush((unsigned int)srcBuff2, (acnt*bcnt*ccnt));
+        }
+
+    /* Invalidate the Destination Buffers */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));
+        }
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheInvalidate((unsigned int)dstBuff2, (acnt*bcnt*ccnt));
+        }
+#endif  /* EDMA3_ENABLE_DCACHE */
+
+
+    /* Set B count reload as B count. */
+    BRCnt = bcnt;
+
+    /* Setting up the SRC/DES Index */
+    srcbidx = (int)acnt;
+    desbidx = (int)acnt;
+
+    if (syncType == EDMA3_DRV_SYNC_A)
+        {
+        /* A Sync Transfer Mode */
+        srccidx = (int)acnt;
+        descidx = (int)acnt;
+        }
+    else
+        {
+        /* AB Sync Transfer Mode */
+        srccidx = ((int)acnt * (int)bcnt);
+        descidx = ((int)acnt * (int)bcnt);
+        }
+
+
+    /* Setup for any QDMA Channel */
+    qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
+    qTcc1 = EDMA3_DRV_TCC_ANY;
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
+                                        (EDMA3_RM_EventQueue)0,
+                                        &callback1, NULL);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Setup for Channel 2 (Link Channel) */
+        qCh2Id = EDMA3_DRV_LINK_CHANNEL;
+        qTcc2 = EDMA3_DRV_TCC_ANY;
+
+        result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2,
+                                            (EDMA3_RM_EventQueue)0,
+                                            &callback1, NULL);
+        }
+
+    /* Configure the Link Channel first */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id,
+                                        (unsigned int)(srcBuff2),
+                                        EDMA3_DRV_ADDR_MODE_INCR,
+                                        EDMA3_DRV_W8BIT);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setDestParams (hEdma, qCh2Id,
+                                            (unsigned int)(dstBuff2),
+                                            EDMA3_DRV_ADDR_MODE_INCR,
+                                            EDMA3_DRV_W8BIT);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        if (syncType == EDMA3_DRV_SYNC_A)
+            {
+            result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt,
+                                                    ccnt, BRCnt,
+                                                    EDMA3_DRV_SYNC_A);
+            }
+        else
+            {
+            /* AB Sync Transfer Mode */
+            result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt,
+                                                    ccnt, BRCnt,
+                                                    EDMA3_DRV_SYNC_AB);
+            }
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Enable the Transfer Completion Interrupt on Link Channel */
+        result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
+                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /**
+         * Enable the Intermediate Transfer Completion Interrupt on Link
+         * Channel.
+         */
+        result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
+                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Link both the channels. */
+        result = EDMA3_DRV_linkChannel (hEdma, qCh1Id, qCh2Id);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /**
+         * Now configure the QDMA channel. Here lies the trick. Since QDMA
+         * channel is linked to another DMA channel, as soon as transfer on
+         * QDMA channel is finished, static field being NOT SET, the associated
+         * PaRAM Set will be reloaded with the Linked PaRAM Set. Now, as the
+         * reload occurs, the QDMA channel will be triggered due to the write
+         * on a specific Trigger Word. We want the trigger to happen immediately
+         * after the write, so the trigger word should be chosen in such a way
+         * that it should trigger after the COMPLETE PaRAM Set will get copied
+         * onto the QDMA Channel PaRAM Set. In that case, only ONE option is
+         * there to choose the CCNT as the trigger word. All other trigger
+         * words will cause the trigger happen in-between the PaRAM Set is
+         * loading. So Set the trigger word as CCNT.
+         */
+        result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
+                                            EDMA3_RM_QDMA_TRIG_CCNT);
+        }
+
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
+        }
+
+    abCNT = acnt | ((bcnt & 0xFFFFu) << 16u);
+
+    /* Write ACNT and BCNT */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id,
+                                            EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT,
+                                            abCNT);
+        }
+
+    /* Set the SYNC Mode (A/AB Sync) */
+    if (syncType == EDMA3_DRV_SYNC_A)
+        {
+        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+                                        EDMA3_DRV_OPT_FIELD_SYNCDIM, 0u);
+        }
+    else
+        {
+        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+                                        EDMA3_DRV_OPT_FIELD_SYNCDIM, 1u);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Enable Transfer Completion Interrupt */
+        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Enable Intermediate Transfer Completion Interrupt */
+        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Set Source Transfer Mode as Increment Mode. */
+        result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM,
+                                        EDMA3_DRV_ADDR_MODE_INCR);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Set Destination Transfer Mode as Increment Mode. */
+        result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM,
+                                        EDMA3_DRV_ADDR_MODE_INCR);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Get Link Address. */
+        result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id,
+                                        EDMA3_DRV_PARAM_FIELD_LINKADDR,
+                                        &bcntReloadLinkField);
+        }
+
+    bcntReloadLinkField = (bcntReloadLinkField | (BRCnt << 16));
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Set B Count Reload & Link Address. */
+        result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id,
+                                        EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD,
+                                        bcntReloadLinkField);
+        }
+
+
+    /*Need to activate next param*/
+    if (syncType == EDMA3_DRV_SYNC_A)
+        {
+        numenabled = bcnt * ccnt;
+        }
+    else
+        {
+        /* AB Sync Transfer Mode */
+        numenabled = ccnt;
+        }
+
+
+    if (numenabled == 1u)
+        {
+        /**
+         * If only one Sync event is required, make the PaRAM Set associated
+         * with the LINK channel as Static.
+         */
+        if (result == EDMA3_DRV_SOK)
+            {
+            result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
+                                            EDMA3_DRV_OPT_FIELD_STATIC, 1u);
+            }
+
+            /**
+             * Be Careful!!!
+             * PaRAM Set associated with the Master Channel should NOT be
+             * set as Static, otherwise the reload will not occur.
+             */
+        }
+
+
+
+    /*
+     * Since the transfer is going to happen in QDMA mode of EDMA3
+     * operation, we have to "Trigger" the transfer multiple times.
+     * Number of times depends upon the Mode (A/AB Sync)
+     * and the different counts.
+     */
+    if (result == EDMA3_DRV_SOK)
+        {
+        for (i = 0u; i < numenabled; i++)
+            {
+            irqRaised1 = 0u;
+
+            /* Write to the Source Address */
+            result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
+                                            (unsigned int)(srcBuff1),
+                                            EDMA3_DRV_ADDR_MODE_INCR,
+                                            EDMA3_DRV_W8BIT);
+            if (result != EDMA3_DRV_SOK)
+                {
+                printf ("error from qdma_test_with_link\r\n\r\n");
+                return result;
+                }
+
+
+            /* Write to the Destination Address */
+            result = EDMA3_DRV_setDestParams(hEdma, qCh1Id,
+                                                (unsigned int)(dstBuff1),
+                                                EDMA3_DRV_ADDR_MODE_INCR,
+                                                EDMA3_DRV_W8BIT);
+            if (result != EDMA3_DRV_SOK)
+                {
+                printf ("error from qdma_test_with_link\r\n\r\n");
+                return result;
+                }
+
+
+            /* Now write to the Trigger Word i.e. CCNT. */
+            result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_CCNT, ccnt);
+            if (result != EDMA3_DRV_SOK)
+                {
+                printf ("error from qdma_test_with_link\r\n\r\n");
+                return result;
+                }
+
+
+            /* After this, transfer will start. */
+            while (irqRaised1 == 0)
+                {
+                /* Wait for the Completion ISR for the Master QDMA Channel. */
+                printf ("waiting for interrupt...\n"); 
+                }
+
+
+            /* Check the status of the completed transfer */
+            if (irqRaised1 < 0)
+                {
+                /* Some error occured, break from the FOR loop. */
+                printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n");
+
+                /* Clear the error bits first */
+                result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);
+
+                break;
+                }
+
+
+            /**
+             * Now, update the source and destination addresses for next
+             * "Trigger".
+             */
+            srcBuff1 += srccidx;
+            dstBuff1 += descidx;
+
+
+            /**
+             * Read the current C Count from the PaRAM Set and write it back.
+             * In this way, we would write the correct CCNT every time and
+             * trigger the transfer also. Since CC will decrement the CCNT
+             * after every (ACNT * BCNT) bytes of data transfer, we can use
+             * that decremented value to trigger the next transfer.
+             * Another option is to take count of CCNT manually (in your code)
+             * and write that value.
+             * First option seems less error prone.
+             */
+            result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id, EDMA3_DRV_PARAM_FIELD_CCNT, &ccnt);
+            if (result != EDMA3_DRV_SOK)
+                {
+                printf ("error from qdma_test_with_link\r\n\r\n");
+                return result;
+                }
+            }
+        }
+
+
+    /**
+     * Transfer on the QDMA channel has finished and Link
+     * PaRAM Set is loaded on the QDMA channel PaRAM Set.
+     * Now for the transfers on the LINK channel,
+     * if only one "TRIGGER" is required,
+     * that has already been provided by the PaRAM Set
+     * upload.
+     * For other triggers, we will take care.
+     */
+    if (result == EDMA3_DRV_SOK)
+        {
+        /**
+         * One trigger has been provided already, so first wait for
+         * that transfer to complete.
+         */
+        while (irqRaised1 == 0)
+            {
+            /* Wait for the Completion ISR for the Master QDMA Channel. */
+            printf ("waiting for interrupt...\n");     
+            }
+
+        /* Check the status of the completed transfer */
+        if (irqRaised1 < 0)
+            {
+            /* Some error occured, clear the error bits. */
+            printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n");
+
+            /* Clear the error bits first */
+            result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);
+            }
+
+
+        if (numenabled == 1u)
+            {
+            /**
+             * Only 1 trigger was required which has been provided
+             * already. No need to do anything.
+             */
+            }
+        else
+            {
+            /**
+             * One trigger has been provided already, so take that into account.
+             */
+            numenabled -= 1u;
+
+            for (i = 0u; i < numenabled; i++)
+                {
+                irqRaised1 = 0u;
+
+                if (i == (numenabled - 1u))
+                    {
+                    /**
+                     * Before providing the last trigger,
+                     * make the PaRAM Set static.
+                     */
+                    result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+                                            EDMA3_DRV_OPT_FIELD_STATIC, 1u);
+                    }
+
+                /**
+                 * Now, update the source and destination addresses for next
+                 * "Trigger".
+                 */
+                srcBuff2 += srccidx;
+                dstBuff2 += descidx;
+
+
+                /**
+                 * Read the current C Count from the PaRAM Set and write it back.
+                 * In this way, we would write the correct CCNT every time and
+                 * trigger the transfer also.
+                 */
+                result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id, EDMA3_DRV_PARAM_FIELD_CCNT, &ccnt);
+                if (result != EDMA3_DRV_SOK)
+                    {
+                    printf ("error from qdma_test_with_link\r\n\r\n");
+                    return result;
+                    }
+
+
+                /* Write to the Source Address */
+                result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
+                                                (unsigned int)(srcBuff2),
+                                                EDMA3_DRV_ADDR_MODE_INCR,
+                                                EDMA3_DRV_W8BIT);
+                if (result != EDMA3_DRV_SOK)
+                    {
+                    printf ("error from qdma_test_with_link\r\n\r\n");
+                    return result;
+                    }
+
+
+                /* Write to the Destination Address */
+                result = EDMA3_DRV_setDestParams(hEdma, qCh1Id,
+                                                    (unsigned int)(dstBuff2),
+                                                    EDMA3_DRV_ADDR_MODE_INCR,
+                                                    EDMA3_DRV_W8BIT);
+                if (result != EDMA3_DRV_SOK)
+                    {
+                    printf ("error from qdma_test_with_link\r\n\r\n");
+                    return result;
+                    }
+
+
+                /* Now write to the Trigger Word i.e. CCNT. */
+                result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_CCNT, ccnt);
+                if (result != EDMA3_DRV_SOK)
+                    {
+                    printf ("error from qdma_test_with_link\r\n\r\n");
+                    return result;
+                    }
+
+
+                /* After this, transfer will start. */
+                while (irqRaised1 == 0)
+                    {
+                    /* Wait for the Completion ISR for the Link Channel. */
+                       printf ("waiting for interrupt...\n");  
+                    }
+
+
+                /* Check the status of the completed transfer */
+                if (irqRaised1 < 0)
+                    {
+                    /* Some error occured, break from the FOR loop. */
+                    printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n");
+
+                    /* Clear the error bits first */
+                    result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);
+
+                    break;
+                    }
+                }
+            }
+        }
+
+
+    /* Restore the src and dest buffers */
+    srcBuff1 = tmpSrcBuff1;
+    dstBuff1 = tmpDstBuff1;
+    srcBuff2 = tmpSrcBuff2;
+    dstBuff2 = tmpDstBuff2;
+
+
+    /* Match the Source and Destination Buffers. */
+    if (EDMA3_DRV_SOK == result)
+        {
+        for (i = 0; i < (acnt*bcnt*ccnt); i++)
+            {
+            if (srcBuff1[i] != dstBuff1[i])
+                {
+                Istestpassed1 = 0;
+                printf("qdma_test_with_link: Data write-read " \
+                                "matching FAILED at i = %d " \
+                                "(srcBuff1 -> dstBuff1)\r\r\n", i);
+                break;
+                }
+            }
+        if (i == (acnt*bcnt*ccnt))
+            {
+            Istestpassed1 = 1u;
+            }
+
+
+        for (i = 0; i < (acnt*bcnt*ccnt); i++)
+            {
+            if (srcBuff2[i] != dstBuff2[i])
+                {
+                Istestpassed2 = 0;
+                printf("qdma_test_with_link: Data write-read " \
+                                "matching FAILED at i = %d " \
+                                "(srcBuff2 -> dstBuff2)\r\n", i);
+                break;
+                }
+            }
+        if (i == (acnt*bcnt*ccnt))
+            {
+            Istestpassed2 = 1u;
+            }
+        }
+
+
+    if (EDMA3_DRV_SOK == result)
+        {
+        /* Free the previously allocated channels. */
+        result = EDMA3_DRV_freeChannel (hEdma, qCh1Id);
+        if (result != EDMA3_DRV_SOK)
+            {
+            printf("qdma_test_with_link: EDMA3_DRV_freeChannel() for qCh1Id FAILED, error code: %d\r\n", result);
+            }
+        else
+            {
+            result = EDMA3_DRV_freeChannel (hEdma, qCh2Id);
+            if (result != EDMA3_DRV_SOK)
+                {
+                printf("qdma_test_with_link: EDMA3_DRV_freeChannel() for qCh2Id FAILED, error code: %d\r\n", result);
+                }
+            }
+        }
+
+
+    if((Istestpassed1 == 1u) && (Istestpassed2 == 1u))
+        {
+        printf("qdma_test_with_link PASSED\r\n");
+        }
+    else
+        {
+        printf("qdma_test_with_link FAILED\r\n");
+        result = ((EDMA3_DRV_SOK == result) ?
+                                EDMA3_DATA_MISMATCH_ERROR : result);
+        }
+
+
+    return result;
+    }
+
index 877cc58b69f4c325fdc28096b1c22ecbe211da96..2295890a4768fee5a57c5f82d5fa102caf45361f 100755 (executable)
-/*\r
- * qdma_test.c\r
- *\r
- * EDMA3 mem-to-mem data copy test case, using a QDMA channel.\r
- *\r
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ \r
- * \r
- * \r
- *  Redistribution and use in source and binary forms, with or without \r
- *  modification, are permitted provided that the following conditions \r
- *  are met:\r
- *\r
- *    Redistributions of source code must retain the above copyright \r
- *    notice, this list of conditions and the following disclaimer.\r
- *\r
- *    Redistributions in binary form must reproduce the above copyright\r
- *    notice, this list of conditions and the following disclaimer in the \r
- *    documentation and/or other materials provided with the   \r
- *    distribution.\r
- *\r
- *    Neither the name of Texas Instruments Incorporated nor the names of\r
- *    its contributors may be used to endorse or promote products derived\r
- *    from this software without specific prior written permission.\r
- *\r
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
-*/\r
-\r
-#include "sample.h"\r
-\r
-extern signed char   _srcBuff1[MAX_BUFFER_SIZE];\r
-extern signed char   _dstBuff1[MAX_BUFFER_SIZE];\r
-\r
-extern signed char *srcBuff1;\r
-extern signed char *dstBuff1;\r
-\r
-\r
-/**\r
- *  \brief   EDMA3 mem-to-mem data copy test case, using a QDMA channel.\r
- *\r
- *\r
- *  \param  acnt        [IN]      Number of bytes in an array\r
- *  \param  bcnt        [IN]      Number of arrays in a frame\r
- *  \param  ccnt        [IN]      Number of frames in a block\r
- *  \param  syncType    [IN]      Synchronization type (A/AB Sync)\r
- *\r
- *  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result qdma_test(\r
-                                       EDMA3_DRV_Handle hEdma,\r
-                    unsigned int acnt,\r
-                    unsigned int bcnt,\r
-                    unsigned int ccnt,\r
-                    EDMA3_DRV_SyncType syncType)\r
-    {\r
-    EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
-    unsigned int i;\r
-    unsigned int count;\r
-    unsigned int Istestpassed = 0u;\r
-    unsigned int numenabled = 0;\r
-    unsigned int qCh1Id=0;\r
-    unsigned int qTcc1 = 0;\r
-    unsigned int BRCnt = 0;\r
-    int srcbidx = 0, desbidx = 0;\r
-    int srccidx = 0, descidx = 0;\r
-    static signed char* tmpSrcBuff1 = NULL;\r
-    static signed char* tmpDstBuff1 = NULL;\r
-\r
-    srcBuff1 = (signed char*) _srcBuff1;\r
-    dstBuff1 = (signed char*) _dstBuff1;\r
-\r
-    tmpSrcBuff1 = srcBuff1;\r
-    tmpDstBuff1 = dstBuff1;\r
-\r
-    /* Initalize source and destination buffers */\r
-    for (count = 0u; count < (acnt*bcnt*ccnt); count++)\r
-        {\r
-        srcBuff1[count] = (int)count+2;\r
-        /**\r
-         * No need to initialize the destination buffer as it is being invalidated.\r
-        dstBuff1[count] = initval;\r
-        */\r
-        }\r
-\r
-#ifdef EDMA3_ENABLE_DCACHE\r
-    /*\r
-    * Note: These functions are required if the buffer is in DDR.\r
-    * For other cases, where buffer is NOT in DDR, user\r
-    * may or may not require the below functions.\r
-    */\r
-    /* Flush the Source Buffer */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));\r
-        }\r
-\r
-    /* Invalidate the Destination Buffer */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));\r
-        }\r
-#endif  /* EDMA3_ENABLE_DCACHE */\r
-\r
-\r
-    irqRaised1 = 0;\r
-\r
-    /* Set B count reload as B count. */\r
-    BRCnt = bcnt;\r
-    /* Setting up the SRC/DES Index */\r
-    srcbidx = (int)acnt;\r
-    desbidx = (int)acnt;\r
-\r
-    if (syncType == EDMA3_DRV_SYNC_A)\r
-        {\r
-        srccidx = (int)acnt;\r
-        descidx = (int)acnt;\r
-        }\r
-    else\r
-        {\r
-        /* AB Sync Transfer Mode */\r
-        srccidx = ((int)acnt * (int)bcnt);\r
-        descidx = ((int)acnt * (int)bcnt);\r
-        }\r
-\r
-\r
-    /* Setup for any QDMA Channel */\r
-    qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;\r
-    qTcc1 = EDMA3_DRV_TCC_ANY;\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,\r
-                                        (EDMA3_RM_EventQueue)0, &callback1,\r
-                                        NULL);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Set QDMA Trigger Word as Destination Address */\r
-        result =  EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,\r
-                                            EDMA3_RM_QDMA_TRIG_DST);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        result =  EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        if (syncType == EDMA3_DRV_SYNC_A)\r
-            {\r
-            result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,\r
-                                                ccnt, BRCnt, EDMA3_DRV_SYNC_A);\r
-            }\r
-        else\r
-            {\r
-            /* AB Sync Transfer Mode */\r
-            result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,\r
-                                                ccnt, BRCnt, EDMA3_DRV_SYNC_AB);\r
-            }\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Enable Transfer Completion Interrupt */\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
-                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Enable Intermediate Transfer Completion Interrupt */\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
-                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Set Source Transfer Mode as Increment Mode. */\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM,\r
-                                        EDMA3_DRV_ADDR_MODE_INCR);\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Set Destination Transfer Mode as Increment Mode. */\r
-        result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM,\r
-                                        EDMA3_DRV_ADDR_MODE_INCR);\r
-        }\r
-\r
-\r
-    /*\r
-     * Since the transfer is going to happen in QDMA mode of EDMA3\r
-     * operation, we have to "Trigger" the transfer multiple times.\r
-     * Number of times depends upon the Mode (A/AB Sync)\r
-     * and the different counts.\r
-     */\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /*Need to activate next param*/\r
-        if (syncType == EDMA3_DRV_SYNC_A)\r
-            {\r
-            numenabled = bcnt * ccnt;\r
-            }\r
-        else\r
-            {\r
-            /* AB Sync Transfer Mode */\r
-            numenabled = ccnt;\r
-            }\r
-\r
-        for (i = 0u; i < numenabled; i++)\r
-            {\r
-            irqRaised1 = 0u;\r
-\r
-            if (i == (numenabled-1u))\r
-                {\r
-                /**\r
-                 * Since OPT.STATIC field should be SET for isolated QDMA\r
-                 * transfers or for the final transfer in a linked list of QDMA\r
-                 * transfers, do the needful for the last request.\r
-                 */\r
-                result = EDMA3_DRV_setOptField (hEdma, qCh1Id,\r
-                                        EDMA3_DRV_OPT_FIELD_STATIC, 1u);\r
-                }\r
-\r
-            /* Write to the Source Address */\r
-            result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,\r
-                                            (unsigned int)(srcBuff1),\r
-                                            EDMA3_DRV_ADDR_MODE_INCR,\r
-                                            EDMA3_DRV_W8BIT);\r
-            /*\r
-             * Now trigger the QDMA channel by writing to the Trigger\r
-             * Word which is set as Destination Address.\r
-             */\r
-            if (result == EDMA3_DRV_SOK)\r
-                {\r
-                result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,\r
-                                                    EDMA3_DRV_PARAM_ENTRY_DST,\r
-                                                    (unsigned int)(dstBuff1));\r
-                if (result != EDMA3_DRV_SOK)\r
-                    {\r
-                    printf ("error from qdma_test\n\r\n");\r
-                    break;\r
-                    }\r
-                }\r
-\r
-            /* Wait for the Completion ISR. */\r
-            while (irqRaised1 == 0)\r
-                {\r
-                /* Wait for the Completion ISR. */\r
-                printf ("waiting for interrupt...\n"); \r
-                }\r
-\r
-            /* Check the status of the completed transfer */\r
-            if (irqRaised1 < 0)\r
-                {\r
-                /* Some error occured, break from the FOR loop. */\r
-                printf ("\r\nqdma_test: Event Miss Occured!!!\r\n");\r
-\r
-                /* Clear the error bits first */\r
-                result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);\r
-\r
-                break;\r
-                }\r
-\r
-            /**\r
-             * Now, update the source and destination addresses for next\r
-             * "Trigger".\r
-             */\r
-            srcBuff1 += srccidx;\r
-            dstBuff1 += descidx;\r
-            }\r
-        }\r
-\r
-    if (result == EDMA3_DRV_SOK)\r
-        {\r
-        /* Restore the src and dest buffers */\r
-        srcBuff1 = tmpSrcBuff1;\r
-        dstBuff1 = tmpDstBuff1;\r
-\r
-        /* Match the Source and Destination Buffers. */\r
-        for (i = 0u; i < (acnt*bcnt*ccnt); i++)\r
-            {\r
-            if (srcBuff1[i] != dstBuff1[i])\r
-                {\r
-                Istestpassed = 0u;\r
-                printf("qdma_test: Data write-read matching FAILED" \\r
-                                " at i = %d\r\n", i);\r
-                break;\r
-                }\r
-            }\r
-        if (i == (acnt*bcnt*ccnt))\r
-            {\r
-            Istestpassed = 1u;\r
-            }\r
-\r
-        /* Free the previously allocated channel. */\r
-        result = EDMA3_DRV_freeChannel (hEdma, qCh1Id);\r
-        if (result != EDMA3_DRV_SOK)\r
-            {\r
-            printf("qdma_test: EDMA3_DRV_freeChannel() FAILED, error code: %d\r\n", result);\r
-            }\r
-        }\r
-\r
-    if(Istestpassed == 1u)\r
-        {\r
-        printf("qdma_test PASSED\r\n");\r
-        }\r
-    else\r
-        {\r
-        printf("qdma_test FAILED\r\n");\r
-        result = ((EDMA3_DRV_SOK == result) ?\r
-                                EDMA3_DATA_MISMATCH_ERROR : result);\r
-        }\r
-\r
-    return result;\r
-    }\r
-\r
-\r
+/*
+ * qdma_test.c
+ *
+ * EDMA3 mem-to-mem data copy test case, using a QDMA channel.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 
+ * 
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include "sample.h"
+
+extern signed char   _srcBuff1[MAX_BUFFER_SIZE];
+extern signed char   _dstBuff1[MAX_BUFFER_SIZE];
+
+extern signed char *srcBuff1;
+extern signed char *dstBuff1;
+
+
+/**
+ *  \brief   EDMA3 mem-to-mem data copy test case, using a QDMA channel.
+ *
+ *
+ *  \param  acnt        [IN]      Number of bytes in an array
+ *  \param  bcnt        [IN]      Number of arrays in a frame
+ *  \param  ccnt        [IN]      Number of frames in a block
+ *  \param  syncType    [IN]      Synchronization type (A/AB Sync)
+ *
+ *  \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+EDMA3_DRV_Result qdma_test(
+                                       EDMA3_DRV_Handle hEdma,
+                    unsigned int acnt,
+                    unsigned int bcnt,
+                    unsigned int ccnt,
+                    EDMA3_DRV_SyncType syncType)
+    {
+    EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+    unsigned int i;
+    unsigned int count;
+    unsigned int Istestpassed = 0u;
+    unsigned int numenabled = 0;
+    unsigned int qCh1Id=0;
+    unsigned int qTcc1 = 0;
+    unsigned int BRCnt = 0;
+    int srcbidx = 0, desbidx = 0;
+    int srccidx = 0, descidx = 0;
+    static signed char* tmpSrcBuff1 = NULL;
+    static signed char* tmpDstBuff1 = NULL;
+
+    srcBuff1 = (signed char*) GLOBAL_ADDR(_srcBuff1);
+    dstBuff1 = (signed char*) GLOBAL_ADDR(_dstBuff1);
+
+    tmpSrcBuff1 = srcBuff1;
+    tmpDstBuff1 = dstBuff1;
+
+    /* Initalize source and destination buffers */
+    for (count = 0u; count < (acnt*bcnt*ccnt); count++)
+        {
+        srcBuff1[count] = (int)count+2;
+        /**
+         * No need to initialize the destination buffer as it is being invalidated.
+        dstBuff1[count] = initval;
+        */
+        }
+
+#ifdef EDMA3_ENABLE_DCACHE
+    /*
+    * Note: These functions are required if the buffer is in DDR.
+    * For other cases, where buffer is NOT in DDR, user
+    * may or may not require the below functions.
+    */
+    /* Flush the Source Buffer */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheFlush((unsigned int)srcBuff1, (acnt*bcnt*ccnt));
+        }
+
+    /* Invalidate the Destination Buffer */
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = Edma3_CacheInvalidate((unsigned int)dstBuff1, (acnt*bcnt*ccnt));
+        }
+#endif  /* EDMA3_ENABLE_DCACHE */
+
+
+    irqRaised1 = 0;
+
+    /* Set B count reload as B count. */
+    BRCnt = bcnt;
+    /* Setting up the SRC/DES Index */
+    srcbidx = (int)acnt;
+    desbidx = (int)acnt;
+
+    if (syncType == EDMA3_DRV_SYNC_A)
+        {
+        srccidx = (int)acnt;
+        descidx = (int)acnt;
+        }
+    else
+        {
+        /* AB Sync Transfer Mode */
+        srccidx = ((int)acnt * (int)bcnt);
+        descidx = ((int)acnt * (int)bcnt);
+        }
+
+
+    /* Setup for any QDMA Channel */
+    qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
+    qTcc1 = EDMA3_DRV_TCC_ANY;
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
+                                        (EDMA3_RM_EventQueue)0, &callback1,
+                                        NULL);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Set QDMA Trigger Word as Destination Address */
+        result =  EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
+                                            EDMA3_RM_QDMA_TRIG_DST);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        result =  EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        if (syncType == EDMA3_DRV_SYNC_A)
+            {
+            result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
+                                                ccnt, BRCnt, EDMA3_DRV_SYNC_A);
+            }
+        else
+            {
+            /* AB Sync Transfer Mode */
+            result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
+                                                ccnt, BRCnt, EDMA3_DRV_SYNC_AB);
+            }
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Enable Transfer Completion Interrupt */
+        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+                                        EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Enable Intermediate Transfer Completion Interrupt */
+        result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+                                        EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Set Source Transfer Mode as Increment Mode. */
+        result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM,
+                                        EDMA3_DRV_ADDR_MODE_INCR);
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Set Destination Transfer Mode as Increment Mode. */
+        result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM,
+                                        EDMA3_DRV_ADDR_MODE_INCR);
+        }
+
+
+    /*
+     * Since the transfer is going to happen in QDMA mode of EDMA3
+     * operation, we have to "Trigger" the transfer multiple times.
+     * Number of times depends upon the Mode (A/AB Sync)
+     * and the different counts.
+     */
+    if (result == EDMA3_DRV_SOK)
+        {
+        /*Need to activate next param*/
+        if (syncType == EDMA3_DRV_SYNC_A)
+            {
+            numenabled = bcnt * ccnt;
+            }
+        else
+            {
+            /* AB Sync Transfer Mode */
+            numenabled = ccnt;
+            }
+
+        for (i = 0u; i < numenabled; i++)
+            {
+            irqRaised1 = 0u;
+
+            if (i == (numenabled-1u))
+                {
+                /**
+                 * Since OPT.STATIC field should be SET for isolated QDMA
+                 * transfers or for the final transfer in a linked list of QDMA
+                 * transfers, do the needful for the last request.
+                 */
+                result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
+                                        EDMA3_DRV_OPT_FIELD_STATIC, 1u);
+                }
+
+            /* Write to the Source Address */
+            result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
+                                            (unsigned int)(srcBuff1),
+                                            EDMA3_DRV_ADDR_MODE_INCR,
+                                            EDMA3_DRV_W8BIT);
+            /*
+             * Now trigger the QDMA channel by writing to the Trigger
+             * Word which is set as Destination Address.
+             */
+            if (result == EDMA3_DRV_SOK)
+                {
+                result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,
+                                                    EDMA3_DRV_PARAM_ENTRY_DST,
+                                                    (unsigned int)(dstBuff1));
+                if (result != EDMA3_DRV_SOK)
+                    {
+                    printf ("error from qdma_test\n\r\n");
+                    break;
+                    }
+                }
+
+            /* Wait for the Completion ISR. */
+            while (irqRaised1 == 0)
+                {
+                /* Wait for the Completion ISR. */
+                printf ("waiting for interrupt...\n"); 
+                }
+
+            /* Check the status of the completed transfer */
+            if (irqRaised1 < 0)
+                {
+                /* Some error occured, break from the FOR loop. */
+                printf ("\r\nqdma_test: Event Miss Occured!!!\r\n");
+
+                /* Clear the error bits first */
+                result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);
+
+                break;
+                }
+
+            /**
+             * Now, update the source and destination addresses for next
+             * "Trigger".
+             */
+            srcBuff1 += srccidx;
+            dstBuff1 += descidx;
+            }
+        }
+
+    if (result == EDMA3_DRV_SOK)
+        {
+        /* Restore the src and dest buffers */
+        srcBuff1 = tmpSrcBuff1;
+        dstBuff1 = tmpDstBuff1;
+
+        /* Match the Source and Destination Buffers. */
+        for (i = 0u; i < (acnt*bcnt*ccnt); i++)
+            {
+            if (srcBuff1[i] != dstBuff1[i])
+                {
+                Istestpassed = 0u;
+                printf("qdma_test: Data write-read matching FAILED" \
+                                " at i = %d\r\n", i);
+                break;
+                }
+            }
+        if (i == (acnt*bcnt*ccnt))
+            {
+            Istestpassed = 1u;
+            }
+
+        /* Free the previously allocated channel. */
+        result = EDMA3_DRV_freeChannel (hEdma, qCh1Id);
+        if (result != EDMA3_DRV_SOK)
+            {
+            printf("qdma_test: EDMA3_DRV_freeChannel() FAILED, error code: %d\r\n", result);
+            }
+        }
+
+    if(Istestpassed == 1u)
+        {
+        printf("qdma_test PASSED\r\n");
+        }
+    else
+        {
+        printf("qdma_test FAILED\r\n");
+        result = ((EDMA3_DRV_SOK == result) ?
+                                EDMA3_DATA_MISMATCH_ERROR : result);
+        }
+
+    return result;
+    }
+
+
index cc41e59f96464316957fa66d3e3677f17a199a34..da771676bc279c0ffd15f511c67aa42ea9c8e444 100644 (file)
@@ -85,11 +85,23 @@ extern void callback1 (unsigned int tcc, EDMA3_RM_TccStatus status,
 extern void callback2 (unsigned int tcc, EDMA3_RM_TccStatus status,
                         void *appData);
 
+extern signed char*  getGlobalAddr(signed char* addr);
 /* Flag variable to check transfer completion on channel 1 */
 extern volatile short irqRaised1;
 /* Flag variable to check transfer completion on channel 2 */
 extern volatile short irqRaised2;
 
+#define MAX_NUM_EDMA_INSTANCES  3
+
+/* Define to verify the default RM config.
+ * Additional configuration required. Update the 
+ * gblCfgReqdArray[] to reflect the master/slave config.
+ * In the case of multiple instances default configuration
+ * may require more than one cores other than core 0 to be master. 
+ * #define EDMA3_DRV_USE_DEF_RM_CFG 
+ */
+
+#define GLOBAL_ADDR(addr) (getGlobalAddr(addr))
 
 /**
  *  \brief   EDMA3 mem-to-mem data copy test case, using a DMA channel.
index f917efaccecfe7caf997be777c2f20b7aec3a693..ba781264c246f6f9d219626537d918a7521df425 100644 (file)
@@ -49,6 +49,7 @@ const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 extern cregister volatile unsigned int DNUM;
 
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
 /* Determine the processor id by reading DNUM register. */
 unsigned short determineProcId()
        {
@@ -56,6 +57,17 @@ unsigned short determineProcId()
        return (unsigned short)DNUM;
        }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+    if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+    {
+        return (addr); /* The address is already a global address */
+    }
+
+    return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+
+
 /** Whether global configuration required for EDMA3 or not.
  * This configuration should be done only once for the EDMA3 hardware by
  * any one of the masters (i.e. DSPs).
@@ -342,14 +354,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                  * on the mapped channel.
                  */
                {
-        0u, 1u, 2u, 3u,
-        4u, 5u, 6u, 7u,
-        8u, 9u, 10u, 11u,
-        12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u,
-        20u, 21u, 22u, 23u,
-        24u, 25u, 26u, 27u,
-        28u, 29u, 30u, 31u,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
@@ -366,7 +378,7 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                 * All channels need not be mapped, some can be free also.
                 */
                {
-               0xFFFFFFFFu,
+               0x00000000u,
                0x00000000u
                }
                }
@@ -379,7 +391,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                /* Resources owned by Region 0 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x0000FFFFu, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -389,7 +401,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0000003Fu},
+               {0x0000FFFFu, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -397,12 +409,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0000003Fu},
+               {0x0000FFFFu, 0x00000000u},
 
                /* Resources reserved by Region 0 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -412,7 +424,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -420,14 +432,14 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 1 */
                /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0xFFFF0000u, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -437,7 +449,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000FC0u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -445,12 +457,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000FC0u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* Resources reserved by Region 1 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -460,7 +472,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -468,16 +480,16 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 2 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -485,7 +497,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0003F000u},
+               {0x00000000u, 0x000000FFu},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -493,12 +505,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0003F000u},
+               {0x00000000u, 0x000000FFu},
 
                /* Resources reserved by Region 2 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -508,7 +520,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -516,7 +528,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
@@ -525,7 +537,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFFFCu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -533,7 +545,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00FC0000u},
+               {0x00000000u, 0x0000FF00u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -541,12 +553,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00FC0000u},
+               {0x00000000u, 0x0000FF00u},
 
                /* Resources reserved by Region 3 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -573,7 +585,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFFF000u, 0x003FFFFFu, 0x00000000u,
+                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -581,7 +593,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0F000000u},
+               {0x00000000u, 0x00FF0000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -589,12 +601,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0F000000u},
+               {0x00000000u, 0x00FF0000u},
 
                /* Resources reserved by Region 4 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -621,7 +633,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0xFFC00000u, 0xFFFFFFFFu,
+                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -629,7 +641,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0xF0000000u},
+               {0x00000000u, 0xFF000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -637,12 +649,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0xF0000000u},
+               {0x00000000u, 0xFF000000u},
 
                /* Resources reserved by Region 5 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
index 1f21dd6c3f79836559b6de8d6a06f26fb7b2a5de..feb51782379fcaec00aaa758ce1dd0265bf5375b 100755 (executable)
@@ -54,6 +54,10 @@ unsigned short determineProcId()
     return 1;
 }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
 unsigned short isGblConfigRequired(unsigned int dspNum)
 {
     (void) dspNum;
index deb0ad60d2c20ca3e796b640c9a6398b0c28d21b..ee011c268f2f124eb541d3360fa925edafc1ab1e 100755 (executable)
@@ -64,6 +64,10 @@ unsigned short determineProcId()
        return 1;
        }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
 unsigned short isGblConfigRequired(unsigned int dspNum)
        {
        (void) dspNum;
index 61353c8aefab8bef34b8d07fecf3da94e5d4d94b..6df2586e590315e7fc89e4e8b0bc0784c113cf50 100644 (file)
@@ -54,6 +54,11 @@ unsigned short determineProcId()
     return 0;
 }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+
 unsigned short isGblConfigRequired(unsigned int dspNum)
 {
     (void) dspNum;
index fbda7ccfb7d77c723683195b6b17bb67b8a2a234..5e670ca80b40e511d23aa47e48e6ff17d7931de9 100755 (executable)
@@ -54,6 +54,10 @@ unsigned short determineProcId()
     return 1;
 }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
 unsigned short isGblConfigRequired(unsigned int dspNum)
 {
     (void) dspNum;
index 38504c7a60a640c136680dc639fb44be87a8a5f2..dccd412431057a2dad9a905735cdefa064c813cb 100644 (file)
@@ -49,6 +49,7 @@ const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 extern cregister volatile unsigned int DNUM;
 
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
 /* Determine the processor id by reading DNUM register. */
 unsigned short determineProcId()
        {
@@ -56,6 +57,17 @@ unsigned short determineProcId()
        return (unsigned short)DNUM;
        }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+    if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+    {
+        return (addr); /* The address is already a global address */
+    }
+
+    return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+
+
 /** Whether global configuration required for EDMA3 or not.
  * This configuration should be done only once for the EDMA3 hardware by
  * any one of the masters (i.e. DSPs).
@@ -342,14 +354,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                  * on the mapped channel.
                  */
                {
-        0u, 1u, 2u, 3u,
-        4u, 5u, 6u, 7u,
-        8u, 9u, 10u, 11u,
-        12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u,
-        20u, 21u, 22u, 23u,
-        24u, 25u, 26u, 27u,
-        28u, 29u, 30u, 31u,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
@@ -366,7 +378,7 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                 * All channels need not be mapped, some can be free also.
                 */
                {
-               0xFFFFFFFFu,
+               0x00000000u,
                0x00000000u
                }
                }
@@ -379,7 +391,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                /* Resources owned by Region 0 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x0000FFFFu, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -389,7 +401,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0000003Fu},
+               {0x0000FFFFu, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -397,12 +409,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0000003Fu},
+               {0x0000FFFFu, 0x00000000u},
 
                /* Resources reserved by Region 0 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -412,7 +424,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -420,14 +432,14 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 1 */
                /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0xFFFF0000u, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -437,7 +449,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000FC0u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -445,12 +457,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000FC0u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* Resources reserved by Region 1 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -460,7 +472,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -468,16 +480,16 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 2 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -485,7 +497,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0003F000u},
+               {0x00000000u, 0x000000FFu},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -493,12 +505,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0003F000u},
+               {0x00000000u, 0x000000FFu},
 
                /* Resources reserved by Region 2 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -508,7 +520,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -516,7 +528,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
@@ -525,7 +537,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFFFCu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -533,7 +545,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00FC0000u},
+               {0x00000000u, 0x0000FF00u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -541,12 +553,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00FC0000u},
+               {0x00000000u, 0x0000FF00u},
 
                /* Resources reserved by Region 3 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -573,7 +585,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFFF000u, 0x003FFFFFu, 0x00000000u,
+                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -581,7 +593,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0F000000u},
+               {0x00000000u, 0x00FF0000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -589,12 +601,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0F000000u},
+               {0x00000000u, 0x00FF0000u},
 
                /* Resources reserved by Region 4 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -621,7 +633,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0xFFC00000u, 0xFFFFFFFFu,
+                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -629,7 +641,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0xF0000000u},
+               {0x00000000u, 0xFF000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -637,12 +649,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0xF0000000u},
+               {0x00000000u, 0xFF000000u},
 
                /* Resources reserved by Region 5 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
index 2f879d36e67928ef1a65c736637ae0b7528342db..9692cc27b78c8dbbab2b4de9dfe32e580df0b51e 100755 (executable)
@@ -54,6 +54,10 @@ unsigned short determineProcId()
     return 0;
 }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
 unsigned short isGblConfigRequired(unsigned int dspNum)
 {
     (void) dspNum;
index c066492bd7ff4a03ac70dc3e5f89963fc42f89e3..d731b4af43c094583ee75ddc7cb697ae4a9ac984 100755 (executable)
@@ -54,6 +54,10 @@ unsigned short determineProcId()
     return 1;
 }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
 unsigned short isGblConfigRequired(unsigned int dspNum)
 {
     (void) dspNum;
index 73c224a2fc443a94064d96ba1c68c880a845698b..f5e15ee9dac26b554071e5de442c046ec7902b8c 100644 (file)
@@ -64,6 +64,11 @@ unsigned short determineProcId()
        return 1;
        }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+
 unsigned short isGblConfigRequired(unsigned int dspNum)
        {
        (void) dspNum;
index 656ac77d961243d25c2a0e7f74ccd79d3ceda37b..d5329e04db1f9a8e83e928bfb4a5bfaa644a25f4 100755 (executable)
@@ -98,7 +98,6 @@ EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode)
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
     Semaphore_Params semParams;
     EDMA3_DRV_GblConfigParams *globalConfig = NULL;
-    EDMA3_DRV_InstanceInitConfig *instanceConfig = NULL;
        EDMA3_DRV_InitConfig initCfg;
        EDMA3_RM_MiscParam miscParam;
        EDMA3_DRV_Handle hEdma = NULL;
@@ -133,8 +132,14 @@ EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode)
                /* Save the semaphore handle for future use */
                semHandle[edma3Id] = initCfg.drvSemHandle;
 
+        /* Driver instance specific config NULL */
+               initCfg.drvInstInitConfig = NULL;
+
+#ifndef EDMA3_DRV_USE_DEF_RM_CFG
+        /* Hook for running examples with default RM config */
                /* configuration structure for the Driver */
-               instanceConfig = &sampleInstInitConfig[edma3Id][dsp_num];
+               initCfg.drvInstInitConfig = &sampleInstInitConfig[edma3Id][dsp_num];
+#endif
 
                initCfg.isMaster = TRUE;
                /* Choose shadow region according to the DSP# */
@@ -142,7 +147,6 @@ EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode)
                /*Saving the regionId for using it in the sample_cs.c file */
                region_id = (EDMA3_RM_RegionId)dsp_num;
                /* Driver instance specific config NULL */
-               initCfg.drvInstInitConfig = instanceConfig;
 
                initCfg.gblerrCb = NULL;
                initCfg.gblerrData = NULL;
index 301c3a561cc2127d100f6707503db8c67a9fc5fc..2814350b6799667152429ffa31c320aa2720db8d 100644 (file)
@@ -49,6 +49,7 @@ const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 extern cregister volatile unsigned int DNUM;
 
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
 /* Determine the processor id by reading DNUM register. */
 unsigned short determineProcId()
        {
@@ -56,6 +57,17 @@ unsigned short determineProcId()
        return (unsigned short)DNUM;
        }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+    if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+    {
+        return (addr); /* The address is already a global address */
+    }
+
+    return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+
+
 /** Whether global configuration required for EDMA3 or not.
  * This configuration should be done only once for the EDMA3 hardware by
  * any one of the masters (i.e. DSPs).
@@ -342,14 +354,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                  * on the mapped channel.
                  */
                {
-        0u, 1u, 2u, 3u,
-        4u, 5u, 6u, 7u,
-        8u, 9u, 10u, 11u,
-        12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u,
-        20u, 21u, 22u, 23u,
-        24u, 25u, 26u, 27u,
-        28u, 29u, 30u, 31u,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
@@ -366,7 +378,7 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                 * All channels need not be mapped, some can be free also.
                 */
                {
-               0xFFFFFFFFu,
+               0x00000000u,
                0x00000000u
                }
                }
@@ -379,7 +391,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                /* Resources owned by Region 0 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x0000FFFFu, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -389,7 +401,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0000003Fu},
+               {0x0000FFFFu, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -397,12 +409,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0000003Fu},
+               {0x0000FFFFu, 0x00000000u},
 
                /* Resources reserved by Region 0 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -412,7 +424,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -420,14 +432,14 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 1 */
                /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0xFFFF0000u, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -437,7 +449,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000FC0u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -445,12 +457,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000FC0u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* Resources reserved by Region 1 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -460,7 +472,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -468,16 +480,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 2 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -485,7 +497,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0003F000u},
+               {0x00000000u, 0x000000FFu},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -493,12 +505,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0003F000u},
+               {0x00000000u, 0x000000FFu},
 
                /* Resources reserved by Region 2 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -508,7 +520,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -516,7 +528,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
@@ -525,7 +537,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFFFCu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -533,7 +545,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00FC0000u},
+               {0x00000000u, 0x0000FF00u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -541,12 +553,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00FC0000u},
+               {0x00000000u, 0x0000FF00u},
 
                /* Resources reserved by Region 3 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -573,7 +585,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFFF000u, 0x003FFFFFu, 0x00000000u,
+                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -581,7 +593,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0F000000u},
+               {0x00000000u, 0x00FF0000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -589,12 +601,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0F000000u},
+               {0x00000000u, 0x00FF0000u},
 
                /* Resources reserved by Region 4 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -621,7 +633,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0xFFC00000u, 0xFFFFFFFFu,
+                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -629,7 +641,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0xF0000000u},
+               {0x00000000u, 0xFF000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -637,12 +649,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0xF0000000u},
+               {0x00000000u, 0xFF000000u},
 
                /* Resources reserved by Region 5 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
index db23c1127740e5194364681d6dce6b28e105dff8..192ed9028755089d0fbfa05ca50fb88735b8bccf 100755 (executable)
@@ -54,6 +54,10 @@ unsigned short determineProcId()
     return 1;
 }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
 unsigned short isGblConfigRequired(unsigned int dspNum)
 {
     (void) dspNum;
index b15369cfb480cf17c9e46d2251125624423ed76d..afffa407cd9ad937cd96c2d8df3e03103415839e 100755 (executable)
@@ -64,6 +64,10 @@ unsigned short determineProcId()
        return 1;
        }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
 unsigned short isGblConfigRequired(unsigned int dspNum)
        {
        (void) dspNum;
index 1113c33c1e8e72b88e1d4feb22fc319db1113da4..b56bb80103010f7730a3a99b2bfd022b277504fd 100644 (file)
@@ -54,6 +54,11 @@ unsigned short determineProcId()
     return 0;
 }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+
 unsigned short isGblConfigRequired(unsigned int dspNum)
 {
     (void) dspNum;
index 96f553be96707e42aadc5f4cea62ff4909507f07..f7f47b56e605f88365cf897801d73a03a85d2ea7 100755 (executable)
@@ -54,6 +54,10 @@ unsigned short determineProcId()
     return 1;
 }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
 unsigned short isGblConfigRequired(unsigned int dspNum)
 {
     (void) dspNum;
index b3b56fb40531033ec64e836bbecad94794185e2b..20721e35429b24fca6c0e7f03152e244b6615d63 100644 (file)
@@ -49,6 +49,7 @@ const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 extern cregister volatile unsigned int DNUM;
 
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
 /* Determine the processor id by reading DNUM register. */
 unsigned short determineProcId()
        {
@@ -56,6 +57,17 @@ unsigned short determineProcId()
        return (unsigned short)DNUM;
        }
 
+signed char*  getGlobalAddr(signed char* addr)
+{
+    if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+    {
+        return (addr); /* The address is already a global address */
+    }
+
+    return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+
+
 /** Whether global configuration required for EDMA3 or not.
  * This configuration should be done only once for the EDMA3 hardware by
  * any one of the masters (i.e. DSPs).
@@ -342,14 +354,14 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                  * on the mapped channel.
                  */
                {
-        0u, 1u, 2u, 3u,
-        4u, 5u, 6u, 7u,
-        8u, 9u, 10u, 11u,
-        12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u,
-        20u, 21u, 22u, 23u,
-        24u, 25u, 26u, 27u,
-        28u, 29u, 30u, 31u,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
@@ -366,7 +378,7 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                 * All channels need not be mapped, some can be free also.
                 */
                {
-               0xFFFFFFFFu,
+               0x00000000u,
                0x00000000u
                }
                }
@@ -379,7 +391,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                /* Resources owned by Region 0 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x0000FFFFu, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -389,7 +401,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0000003Fu},
+               {0x0000FFFFu, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -397,12 +409,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0000003Fu},
+               {0x0000FFFFu, 0x00000000u},
 
                /* Resources reserved by Region 0 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -412,7 +424,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -420,14 +432,14 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 1 */
                /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0xFFFF0000u, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -437,7 +449,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000FC0u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -445,12 +457,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00000FC0u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* Resources reserved by Region 1 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -460,7 +472,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -468,16 +480,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 2 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -485,7 +497,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0003F000u},
+               {0x00000000u, 0x000000FFu},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -493,12 +505,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0003F000u},
+               {0x00000000u, 0x000000FFu},
 
                /* Resources reserved by Region 2 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -508,7 +520,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -516,7 +528,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0xFFFFFFFFu, 0x00000000u},
+        {0x00000000u, 0x00000000u},
          },
 
          {
@@ -525,7 +537,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFFFCu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -533,7 +545,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00FC0000u},
+               {0x00000000u, 0x0000FF00u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -541,12 +553,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x00FC0000u},
+               {0x00000000u, 0x0000FF00u},
 
                /* Resources reserved by Region 3 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -573,7 +585,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFFF000u, 0x003FFFFFu, 0x00000000u,
+                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -581,7 +593,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0F000000u},
+               {0x00000000u, 0x00FF0000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -589,12 +601,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00000000u, 0x0F000000u},
+               {0x00000000u, 0x00FF0000u},
 
                /* Resources reserved by Region 4 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -621,7 +633,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0xFFC00000u, 0xFFFFFFFFu,
+                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -629,7 +641,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00000000u, 0xF0000000u},
+               {0x00000000u, 0xFF000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */