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raw | patch | inline | side by side (parent: 4e1e374)
| author | Sunil MS <x0190988@ti.com> | |
| Thu, 9 Oct 2014 11:53:03 +0000 (17:23 +0530) | ||
| committer | Sunil MS <x0190988@ti.com> | |
| Tue, 14 Oct 2014 09:21:31 +0000 (14:51 +0530) |
MISRA.BUILTIN_NUMERIC
MISRA.LITERAL.UNSIGNED.SUFFIX
Change-Id: I37dc619035afba0e0443b4e6c0ed21dcc53e55ce
Signed-off-by: Sunil MS <x0190988@ti.com>
MISRA.LITERAL.UNSIGNED.SUFFIX
Change-Id: I37dc619035afba0e0443b4e6c0ed21dcc53e55ce
Signed-off-by: Sunil MS <x0190988@ti.com>
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_arm_int_reg.c
index 18b1f5f8b285442364f59f76a33e0c04daba1fc3..d5aad08b2a90e49aaca1b8dab7f8f45708643da0 100644 (file)
(void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
};
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
-extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
-extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorIntXbarInstNo[];
-extern unsigned int ccErrEdmaXbarIndex[];
-extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
-extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
+extern uint32_t ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorIntXbarInstNo[];
+extern uint32_t ccErrEdmaXbarIndex[];
+extern uint32_t tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
+extern uint32_t tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
/**
* Variables which will be used internally for referring the hardware interrupt
* for various EDMA3 interrupts.
*/
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[];
+extern uint32_t hwIntCcErr[];
+extern uint32_t hwIntTcErr[];
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
/* This variable has to be used as an extern */
-unsigned int gpp_num = 0;
+uint32_t gpp_num = 0;
Hwi_Handle hwiCCXferCompInt;
Hwi_Handle hwiCCErrInt;
typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX (127u)
-#define EDMA3_NUM_TCC (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX (127U)
+#define EDMA3_NUM_TCC (64U)
#define EDMA3_EVENT_MUX_REG_BASE_ADDR (0x4a002c78)
/*
* Forward decleration
*/
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
- unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+ uint32_t *chanNum,
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
- unsigned int chanNum);
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+ uint32_t chanNum);
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
/** To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
{
static UInt32 cookie = 0;
- unsigned int numTc = 0;
+ uint32_t numTc = 0;
/*
* Skip these interrupt xbar configuration.
}
/** To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
{
static UInt32 cookie = 0;
- unsigned int numTc = 0;
+ uint32_t numTc = 0;
/* Disabling the global interrupts */
cookie = Hwi_disable();
*
* \return EDMA3_DRV_SOK if success, else error code
*/
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
- unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+ uint32_t *chanNum,
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
{
EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
- unsigned int xbarEvtNum = 0;
- int edmaChanNum = 0;
+ uint32_t xbarEvtNum = 0;
+ int32_t edmaChanNum = 0;
if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX) &&
(chanNum != NULL) &&
*
* \return EDMA3_DRV_SOK if success, else error code
*/
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
- unsigned int chanNum)
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+ uint32_t chanNum)
{
EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
- unsigned int scrChanOffset = 0;
- unsigned int scrRegOffset = 0;
- unsigned int xBarEvtNum = 0;
+ uint32_t scrChanOffset = 0;
+ uint32_t scrRegOffset = 0;
+ uint32_t xBarEvtNum = 0;
CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
}
EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
- unsigned int edma3Id)
+ uint32_t edma3Id)
{
EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
return retVal;
}
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
{
printf("memory Protection error");
}
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_cfg.c
index 25fcb46c99d55cc9dc4b45f2639c4733d5664f5f..160a8f76fbb73eb0ab1eff6e847caa37873d0b89 100644 (file)
#endif
/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES 3u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+#define NUM_EDMA3_INSTANCES 3U
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
/* Number of DSPs present in the system */
-#define NUM_DSPS 1u
-const unsigned int numDsps = NUM_DSPS;
+#define NUM_DSPS 1U
+const uint32_t numDsps = NUM_DSPS;
/* Determine the processor id by reading DNUM register. */
/* Statically allocate the region numbers with cores. */
-int myCoreNum;
-#define PID0_ADDRESS 0xE00FFFE0
+int32_t myCoreNum;
+#define PID0_ADDRESS 0xE00FFFE0U
#define CORE_ID_C0 0x0
#define CORE_ID_C1 0x1
-unsigned short determineProcId()
+uint16_t determineProcId()
{
- unsigned short regionNo = numEdma3Instances;
+ uint16_t regionNo = numEdma3Instances;
#ifdef BUILD_TDA3XX_DSP
- extern __cregister volatile unsigned int DNUM;
+ extern __cregister volatile uint32_t DNUM;
#endif
myCoreNum = numDsps;
#ifdef BUILD_TDA3XX_IPU
- myCoreNum = (*(unsigned int *)(PID0_ADDRESS));
+ myCoreNum = (*(uint32_t *)(PID0_ADDRESS));
if(myCoreNum == CORE_ID_C0)
regionNo = 4;
else if (myCoreNum == CORE_ID_C1)
return regionNo;
}
-signed char* getGlobalAddr(signed char* addr)
+int8_t* getGlobalAddr(int8_t* addr)
{
return (addr); /* The address is already a global address */
}
-unsigned short isGblConfigRequired(unsigned int dspNum)
+uint16_t isGblConfigRequired(uint32_t dspNum)
{
(void) dspNum;
return 1;
EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
/** Number of PaRAM Sets available */
-#define EDMA3_NUM_PARAMSET (512u)
+#define EDMA3_NUM_PARAMSET (512U)
/** Number of TCCS available */
-#define EDMA3_NUM_TCC (64u)
+#define EDMA3_NUM_TCC (64U)
/** Number of DMA Channels available */
-#define EDMA3_NUM_DMA_CHANNELS (64u)
+#define EDMA3_NUM_DMA_CHANNELS (64U)
/** Number of QDMA Channels available */
-#define EDMA3_NUM_QDMA_CHANNELS (8u)
+#define EDMA3_NUM_QDMA_CHANNELS (8U)
/** Number of Event Queues available */
-#define EDMA3_NUM_EVTQUE (4u)
+#define EDMA3_NUM_EVTQUE (4U)
/** Number of Transfer Controllers available */
-#define EDMA3_NUM_TC (2u)
+#define EDMA3_NUM_TC (2U)
/** Number of Regions */
-#define EDMA3_NUM_REGIONS (8u)
+#define EDMA3_NUM_REGIONS (8U)
/** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT_DSP (38u)
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34u)
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33u)
-#define EDMA3_CC_XFER_COMPLETION_INT_EVE (8u)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP (38U)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34U)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33U)
+#define EDMA3_CC_XFER_COMPLETION_INT_EVE (8U)
/** Based on the interrupt number to be mapped define the XBAR instance number */
-#define COMPLETION_INT_DSP_XBAR_INST_NO (7u)
-#define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12u)
-#define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11u)
+#define COMPLETION_INT_DSP_XBAR_INST_NO (7U)
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12U)
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11U)
/** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT_DSP (39u)
-#define EDMA3_CC_ERROR_INT_IPU (35u)
-#define EDMA3_CC_ERROR_INT_EVE (23u)
+#define EDMA3_CC_ERROR_INT_DSP (39U)
+#define EDMA3_CC_ERROR_INT_IPU (35U)
+#define EDMA3_CC_ERROR_INT_EVE (23U)
/** Based on the interrupt number to be mapped define the XBAR instance number */
-#define CC_ERROR_INT_DSP_XBAR_INST_NO (8u)
-#define CC_ERROR_INT_IPU_XBAR_INST_NO (13u)
+#define CC_ERROR_INT_DSP_XBAR_INST_NO (8U)
+#define CC_ERROR_INT_IPU_XBAR_INST_NO (13U)
/** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT_DSP (40u)
-#define EDMA3_TC0_ERROR_INT_IPU (36u)
-#define EDMA3_TC0_ERROR_INT_EVE (24u)
-#define EDMA3_TC1_ERROR_INT_DSP (41u)
-#define EDMA3_TC1_ERROR_INT_IPU (37u)
-#define EDMA3_TC1_ERROR_INT_EVE (25u)
+#define EDMA3_TC0_ERROR_INT_DSP (40U)
+#define EDMA3_TC0_ERROR_INT_IPU (36U)
+#define EDMA3_TC0_ERROR_INT_EVE (24U)
+#define EDMA3_TC1_ERROR_INT_DSP (41U)
+#define EDMA3_TC1_ERROR_INT_IPU (37U)
+#define EDMA3_TC1_ERROR_INT_EVE (25U)
/** Based on the interrupt number to be mapped define the XBAR instance number */
-#define TC0_ERROR_INT_DSP_XBAR_INST_NO (9u)
-#define TC0_ERROR_INT_IPU_XBAR_INST_NO (14u)
-#define TC1_ERROR_INT_DSP_XBAR_INST_NO (10u)
-#define TC1_ERROR_INT_IPU_XBAR_INST_NO (15u)
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO (9U)
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO (14U)
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO (10U)
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO (15U)
#ifdef BUILD_TDA3XX_DSP
#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP
#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_EVE
#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_EVE
/* For accessing EVE internal edma, there is no need to configure Xbar */
-#define CC_ERROR_INT_XBAR_INST_NO 0u
-#define TC0_ERROR_INT_XBAR_INST_NO 0u
-#define TC1_ERROR_INT_XBAR_INST_NO 0u
+#define CC_ERROR_INT_XBAR_INST_NO 0U
+#define TC0_ERROR_INT_XBAR_INST_NO 0U
+#define TC1_ERROR_INT_XBAR_INST_NO 0U
#else
-#define EDMA3_CC_XFER_COMPLETION_INT (0u)
-#define EDMA3_CC_ERROR_INT (0u)
-#define CC_ERROR_INT_XBAR_INST_NO (0u)
-#define EDMA3_TC0_ERROR_INT (0u)
-#define EDMA3_TC1_ERROR_INT (0u)
+#define EDMA3_CC_XFER_COMPLETION_INT (0U)
+#define EDMA3_CC_ERROR_INT (0U)
+#define CC_ERROR_INT_XBAR_INST_NO (0U)
+#define EDMA3_TC0_ERROR_INT (0U)
+#define EDMA3_TC1_ERROR_INT (0U)
#define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_A15_XBAR_INST_NO
#define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_A15_XBAR_INST_NO
#endif
-#define EDMA3_TC2_ERROR_INT (0u)
-#define EDMA3_TC3_ERROR_INT (0u)
-#define EDMA3_TC4_ERROR_INT (0u)
-#define EDMA3_TC5_ERROR_INT (0u)
-#define EDMA3_TC6_ERROR_INT (0u)
-#define EDMA3_TC7_ERROR_INT (0u)
+#define EDMA3_TC2_ERROR_INT (0U)
+#define EDMA3_TC3_ERROR_INT (0U)
+#define EDMA3_TC4_ERROR_INT (0U)
+#define EDMA3_TC5_ERROR_INT (0U)
+#define EDMA3_TC6_ERROR_INT (0U)
+#define EDMA3_TC7_ERROR_INT (0U)
-#define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19u)
-#define DSP2_EDMA3_CC_XFER_COMPLETION_INT (20u)
-#define DSP1_EDMA3_CC_ERROR_INT (27u)
-#define DSP1_EDMA3_TC0_ERROR_INT (28u)
-#define DSP1_EDMA3_TC1_ERROR_INT (29u)
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT (19U)
+#define DSP2_EDMA3_CC_XFER_COMPLETION_INT (20U)
+#define DSP1_EDMA3_CC_ERROR_INT (27U)
+#define DSP1_EDMA3_TC0_ERROR_INT (28U)
+#define DSP1_EDMA3_TC1_ERROR_INT (29U)
/** XBAR interrupt source index numbers for EDMA interrupts */
-#define XBAR_EDMA_TPCC_IRQ_REGION0 (361u)
-#define XBAR_EDMA_TPCC_IRQ_REGION1 (362u)
-#define XBAR_EDMA_TPCC_IRQ_REGION2 (363u)
-#define XBAR_EDMA_TPCC_IRQ_REGION3 (364u)
-#define XBAR_EDMA_TPCC_IRQ_REGION4 (365u)
-#define XBAR_EDMA_TPCC_IRQ_REGION5 (366u)
-#define XBAR_EDMA_TPCC_IRQ_REGION6 (367u)
-#define XBAR_EDMA_TPCC_IRQ_REGION7 (368u)
-
-#define XBAR_EDMA_TPCC_IRQ_ERR (359u)
-#define XBAR_EDMA_TC0_IRQ_ERR (370u)
-#define XBAR_EDMA_TC1_IRQ_ERR (371u)
+#define XBAR_EDMA_TPCC_IRQ_REGION0 (361U)
+#define XBAR_EDMA_TPCC_IRQ_REGION1 (362U)
+#define XBAR_EDMA_TPCC_IRQ_REGION2 (363U)
+#define XBAR_EDMA_TPCC_IRQ_REGION3 (364U)
+#define XBAR_EDMA_TPCC_IRQ_REGION4 (365U)
+#define XBAR_EDMA_TPCC_IRQ_REGION5 (366U)
+#define XBAR_EDMA_TPCC_IRQ_REGION6 (367U)
+#define XBAR_EDMA_TPCC_IRQ_REGION7 (368U)
+
+#define XBAR_EDMA_TPCC_IRQ_ERR (359U)
+#define XBAR_EDMA_TC0_IRQ_ERR (370U)
+#define XBAR_EDMA_TC1_IRQ_ERR (371U)
/**
* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
*/
/* EDMA 0 */
-#define EDMA3_HWI_INT_XFER_COMP (7u)
-#define EDMA3_HWI_INT_CC_ERR (7u)
-#define EDMA3_HWI_INT_TC0_ERR (10u)
-#define EDMA3_HWI_INT_TC1_ERR (10u)
-#define EDMA3_HWI_INT_TC2_ERR (10u)
-#define EDMA3_HWI_INT_TC3_ERR (10u)
+#define EDMA3_HWI_INT_XFER_COMP (7U)
+#define EDMA3_HWI_INT_CC_ERR (7U)
+#define EDMA3_HWI_INT_TC0_ERR (10U)
+#define EDMA3_HWI_INT_TC1_ERR (10U)
+#define EDMA3_HWI_INT_TC2_ERR (10U)
+#define EDMA3_HWI_INT_TC3_ERR (10U)
/**
* \brief Mapping of DMA channels 0-31 to Hardware Events from
* To allocate more DMA channels or TCCs, one has to modify the event mapping.
*/
/* 31 0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA (0x3CC0DB6Eu) /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x00000003u) /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA (0x00000000u) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA (0x3CC0DB6EU) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x00000003U) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA (0x00000000U) /* TBD */
/**
* \brief Mapping of DMA channels 32-63 to Hardware Events from
*
* To allocate more DMA channels or TCCs, one has to modify the event mapping.
*/
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA (0x303F3FFCu) /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000u) /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA (0x00000000u) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA (0x303F3FFCU) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000U) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA (0x00000000U) /* TBD */
/* Variable which will be used internally for referring number of Event Queues*/
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
EDMA3_NUM_EVTQUE,
};
/* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] = {
EDMA3_NUM_TC,
EDMA3_NUM_TC,
EDMA3_NUM_TC
* Variable which will be used internally for referring transfer completion
* interrupt.
*/
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
/* EDMA3 INSTANCE# 0 */
{
},
/* EDMA3 INSTANCE# 1 */
{
- 0u,
- 0u,
+ 0U,
+ 0U,
DSP1_EDMA3_CC_XFER_COMPLETION_INT,
DSP2_EDMA3_CC_XFER_COMPLETION_INT,
- 0u,
- 0u,
- 0u,
- 0u
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/* EDMA3 INSTANCE# 2 */
{
- 0u,
+ 0U,
/* Region 1 (Associated to EVE core)*/
EDMA3_CC_XFER_COMPLETION_INT_EVE,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
}
};
/** These are the Xbar instance numbers corresponding to interrupt numbers */
-unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
/* EDMA3 INSTANCE# 0 */
{
- 0u,
- 0u,
+ 0U,
+ 0U,
COMPLETION_INT_DSP_XBAR_INST_NO,
COMPLETION_INT_DSP_XBAR_INST_NO,
COMPLETION_INT_IPU_C0_XBAR_INST_NO,
COMPLETION_INT_IPU_C1_XBAR_INST_NO,
- 0u,
- 0u,
+ 0U,
+ 0U,
},
/* EDMA3 INSTANCE# 1 */
{
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/* EDMA3 INSTANCE# 2 */
{
@@ -369,19 +369,19 @@ unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
* there is no need to configure Xbar.
* So getting to zero.
*/
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
}
};
/** These are the Interrupt Crossbar Index For EDMA Completion for different regions */
-unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
/* EDMA3 INSTANCE# 0 */
{
* there is no need to configure Xbar.
* So getting to zero.
*/
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
}
};
* Variable which will be used internally for referring channel controller's
* error interrupt.
*/
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] =
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] =
{
EDMA3_CC_ERROR_INT,
DSP1_EDMA3_CC_ERROR_INT,
EDMA3_CC_ERROR_INT
};
-unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =
+uint32_t ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =
{
CC_ERROR_INT_XBAR_INST_NO,
CC_ERROR_INT_XBAR_INST_NO,
CC_ERROR_INT_XBAR_INST_NO
};
-unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] =
+uint32_t ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] =
{
XBAR_EDMA_TPCC_IRQ_ERR,
XBAR_EDMA_TPCC_IRQ_ERR,
* Variable which will be used internally for referring transfer controllers'
* error interrupts.
*/
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
/* EDMA3 INSTANCE# 0 */
{
EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
}
};
-unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
/* EDMA3 INSTANCE# 0 */
{
TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
- 0u, 0u,
- 0u, 0u,
- 0u, 0u,
+ 0U, 0U,
+ 0U, 0U,
+ 0U, 0U,
},
/* EDMA3 INSTANCE# 1 */
{
TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
- 0u, 0u,
- 0u, 0u,
- 0u, 0u,
+ 0U, 0U,
+ 0U, 0U,
+ 0U, 0U,
},
/* EDMA3 INSTANCE# 2 */
{
TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
- 0u, 0u,
- 0u, 0u,
- 0u, 0u,
+ 0U, 0U,
+ 0U, 0U,
+ 0U, 0U,
}
};
-unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
/* EDMA3 INSTANCE# 0 */
{
XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
- 0u, 0u,
- 0u, 0u, 0u, 0u,
+ 0U, 0U,
+ 0U, 0U, 0U, 0U,
},
/* EDMA3 INSTANCE# 1 */
{
XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
- 0u, 0u,
- 0u, 0u, 0u, 0u,
+ 0U, 0U,
+ 0U, 0U, 0U, 0U,
},
/* EDMA3 INSTANCE# 2 */
{
XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
- 0u, 0u,
- 0u, 0u, 0u, 0u,
+ 0U, 0U,
+ 0U, 0U, 0U, 0U,
}
};
* Variables which will be used internally for referring the hardware interrupt
* for various EDMA3 interrupts.
*/
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] =
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =
{
EDMA3_HWI_INT_XFER_COMP,
EDMA3_HWI_INT_XFER_COMP,
EDMA3_CC_XFER_COMPLETION_INT
};
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] =
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =
{
EDMA3_HWI_INT_CC_ERR,
EDMA3_HWI_INT_CC_ERR,
EDMA3_CC_ERROR_INT
};
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
/* EDMA3 INSTANCE# 0 */
{
* for a channel number to a parameter entry number or, in other words,
* PaRAM entry n corresponds to channel n.
*/
- 1u,
+ 1U,
/** Existence of memory protection feature */
- 0u,
+ 0U,
/** Global Register Region of CC Registers */
EDMA3_CC_BASE_ADDR,
* device (ARM, DSP, USB, etc)
*/
{
- 0u,
- 1u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 0U,
+ 1U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* \brief To Configure the Threshold level of number of events
* in the queue watermark threshold register (QWMTHRA).
*/
{
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 16U,
+ 16U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* DBS values. It is defined in Bytes.
*/
{
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 16U,
+ 16U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* for a channel number to a parameter entry number or, in other words,
* PaRAM entry n corresponds to channel n.
*/
- 1u,
+ 1U,
/** Existence of memory protection feature */
- 0u,
+ 0U,
/** Global Register Region of CC Registers */
DSP1_EDMA3_CC_BASE_ADDR,
* device (ARM, DSP, USB, etc)
*/
{
- 0u,
- 1u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 0U,
+ 1U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* \brief To Configure the Threshold level of number of events
* in the queue watermark threshold register (QWMTHRA).
*/
{
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 16U,
+ 16U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* DBS values. It is defined in Bytes.
*/
{
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 16U,
+ 16U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* for a channel number to a parameter entry number or, in other words,
* PaRAM entry n corresponds to channel n.
*/
- 1u,
+ 1U,
/** Existence of memory protection feature */
- 0u,
+ 0U,
/** Global Register Region of CC Registers */
EDMA3_CC_BASE_ADDR,
* device (ARM, DSP, USB, etc)
*/
{
- 0u,
- 1u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 0U,
+ 1U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* \brief To Configure the Threshold level of number of events
* in the queue watermark threshold register (QWMTHRA).
*/
{
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 16U,
+ 16U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* DBS values. It is defined in Bytes.
*/
{
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 16U,
+ 16U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
@@ -1171,129 +1171,129 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 1 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 2 (Associated to any DSP1)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
@@ -1301,46 +1301,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 3 (Associated to any DSP2)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
@@ -1348,46 +1348,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 4 (Associated to any IPU core 0)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
@@ -1395,46 +1395,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 5 (Associated to any IPU core 1)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
@@ -1442,105 +1442,105 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
},
/* EDMA3 INSTANCE# 1 DSP1 EDMA*/
@@ -1549,129 +1549,129 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 1 (Not Associated to any core supported) */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
@@ -1679,46 +1679,46 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
@@ -1726,199 +1726,199 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
},
/* EDMA3 INSTANCE# 2 EVE EDMA*/
@@ -1927,82 +1927,82 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 1 (Associated to any EVE core)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
@@ -2010,293 +2010,293 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 2 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
},
};
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda3xx_int_reg.c
index d627ab727467f2265dba636fba222f4b11d8c4ce..06bcaf91fc4231dc0f7f4aa7871fb32113c485fe 100644 (file)
&lisrEdma3TC7ErrHandler0,
};
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
-extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
-extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorIntXbarInstNo[];
-extern unsigned int ccErrEdmaXbarIndex[];
-extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
-extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
+extern uint32_t ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorIntXbarInstNo[];
+extern uint32_t ccErrEdmaXbarIndex[];
+extern uint32_t tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
+extern uint32_t tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
/**
* Variables which will be used internally for referring the hardware interrupt
* for various EDMA3 interrupts.
*/
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[];
+extern uint32_t hwIntCcErr[];
+extern uint32_t hwIntTcErr[];
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
/* External Instance Specific Configuration Structure */
extern EDMA3_DRV_GblXbarToChanConfigParams
typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX (127u)
-#define EDMA3_NUM_TCC (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX (127U)
+#define EDMA3_NUM_TCC (64U)
#define EDMA3_EVENT_MUX_REG_BASE_ADDR (0x4a002c78)
/*
* Forward decleration
*/
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
- unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+ uint32_t *chanNum,
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
- unsigned int chanNum);
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+ uint32_t chanNum);
/** To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
{
static UInt32 cookie = 0;
- unsigned int numTc = 0;
+ uint32_t numTc = 0;
/* Do the xbar configuration only for edma inst 0 */
/* EDMA inst 1 is for DSP1 EDMA which has direct interrupt mapping */
if(edma3Id == 0)
}
/** To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
{
static UInt32 cookie = 0;
- unsigned int numTc = 0;
+ uint32_t numTc = 0;
/* Disabling the global interrupts */
cookie = Hwi_disable();
*
* \return EDMA3_DRV_SOK if success, else error code
*/
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
- unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+ uint32_t *chanNum,
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
{
EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
- unsigned int xbarEvtNum = 0;
- int edmaChanNum = 0;
+ uint32_t xbarEvtNum = 0;
+ int32_t edmaChanNum = 0;
if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX) &&
(chanNum != NULL) &&
*
* \return EDMA3_DRV_SOK if success, else error code
*/
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
- unsigned int chanNum)
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+ uint32_t chanNum)
{
EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
- unsigned int scrChanOffset = 0;
- unsigned int scrRegOffset = 0;
- unsigned int xBarEvtNum = 0;
+ uint32_t scrChanOffset = 0;
+ uint32_t scrRegOffset = 0;
+ uint32_t xBarEvtNum = 0;
CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
}
EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
- unsigned int edma3Id)
+ uint32_t edma3Id)
{
EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_arm_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_arm_int_reg.c
index dd12525a622fc6fd46132355b7b60fa2b581de91..62a3dc3aebc344dc9ce81e47066f4a94833d41cc 100644 (file)
(void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
};
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
+extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[];
+extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[];
/**
* Variables which will be used internally for referring the hardware interrupt
* for various EDMA3 interrupts.
*/
-extern unsigned int hwIntXferComp[];
-extern unsigned int hwIntCcErr[];
-extern unsigned int hwIntTcErr[];
+extern uint32_t hwIntXferComp[];
+extern uint32_t hwIntCcErr[];
+extern uint32_t hwIntTcErr[];
-extern unsigned int dsp_num;
+extern uint32_t dsp_num;
/* This variable has to be used as an extern */
-unsigned int gpp_num = 0;
+uint32_t gpp_num = 0;
Hwi_Handle hwiCCXferCompInt;
Hwi_Handle hwiCCErrInt;
typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly;
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX (127u)
-#define EDMA3_NUM_TCC (64u)
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX (127U)
+#define EDMA3_NUM_TCC (64U)
#define EDMA3_EVENT_MUX_REG_BASE_ADDR (0x4a002c78)
/*
* Forward decleration
*/
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
- unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+ uint32_t *chanNum,
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
- unsigned int chanNum);
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+ uint32_t chanNum);
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
/** To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
+void registerEdma3Interrupts (uint32_t edma3Id)
{
static UInt32 cookie = 0;
- unsigned int numTc = 0;
+ uint32_t numTc = 0;
Hwi_Params hwiParams;
Error_Block eb;
}
/** To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
+void unregisterEdma3Interrupts (uint32_t edma3Id)
{
static UInt32 cookie = 0;
- unsigned int numTc = 0;
+ uint32_t numTc = 0;
/* Disabling the global interrupts */
cookie = Hwi_disable();
*
* \return EDMA3_DRV_SOK if success, else error code
*/
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
- unsigned int *chanNum,
+EDMA3_DRV_Result sampleMapXbarEvtToChan (uint32_t eventNum,
+ uint32_t *chanNum,
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
{
EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
- unsigned int xbarEvtNum = 0;
- int edmaChanNum = 0;
+ uint32_t xbarEvtNum = 0;
+ int32_t edmaChanNum = 0;
if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX) &&
(chanNum != NULL) &&
*
* \return EDMA3_DRV_SOK if success, else error code
*/
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
- unsigned int chanNum)
+EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
+ uint32_t chanNum)
{
EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
- unsigned int scrChanOffset = 0;
- unsigned int scrRegOffset = 0;
- unsigned int xBarEvtNum = 0;
+ uint32_t scrChanOffset = 0;
+ uint32_t scrRegOffset = 0;
+ uint32_t xBarEvtNum = 0;
CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
}
EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
- unsigned int edma3Id)
+ uint32_t edma3Id)
{
EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
return retVal;
}
-void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
{
printf("memory Protection error");
}
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_cfg.c
index d919b14e5b69c087d4e6ff4715f96fd41fa2868d..2b5129d0a1af78af15734532119da598bdc0ca24 100644 (file)
#include <ti/sdo/edma3/rm/edma3_rm.h>
/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES 1u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+#define NUM_EDMA3_INSTANCES 1U
+const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
/* Number of DSPs present in the system */
-#define NUM_DSPS 1u
-const unsigned int numDsps = NUM_DSPS;
+#define NUM_DSPS 1U
+const uint32_t numDsps = NUM_DSPS;
/* Determine the processor id by reading DNUM register. */
/* Statically allocate the region numbers with cores. */
-int myCoreNum;
-#define PID0_ADDRESS 0xE00FFFE0
+int32_t myCoreNum;
+#define PID0_ADDRESS 0xE00FFFE0U
#define CORE_ID_C0 0x0
#define CORE_ID_C1 0x1
-unsigned short determineProcId()
+uint16_t determineProcId()
{
-unsigned short regionNo = numEdma3Instances;
+uint16_t regionNo = numEdma3Instances;
#ifdef BUILD_TDA2XX_DSP
-extern __cregister volatile unsigned int DNUM;
+extern __cregister volatile uint32_t DNUM;
#endif
myCoreNum = numDsps;
#ifdef BUILD_TDA2XX_MPU
else
regionNo = 0;
#elif defined(BUILD_TDA2XX_IPU)
-myCoreNum = (*(unsigned int *)(PID0_ADDRESS));
+myCoreNum = (*(uint32_t *)(PID0_ADDRESS));
if(Core_getIpuId() == 1){
if(myCoreNum == CORE_ID_C0)
regionNo = 4;
return regionNo;
}
-signed char* getGlobalAddr(signed char* addr)
+int8_t* getGlobalAddr(int8_t* addr)
{
return (addr); /* The address is already a global address */
}
-unsigned short isGblConfigRequired(unsigned int dspNum)
+uint16_t isGblConfigRequired(uint32_t dspNum)
{
(void) dspNum;
EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
/** Number of PaRAM Sets available */
-#define EDMA3_NUM_PARAMSET (512u)
+#define EDMA3_NUM_PARAMSET (512U)
/** Number of TCCS available */
-#define EDMA3_NUM_TCC (64u)
+#define EDMA3_NUM_TCC (64U)
/** Number of DMA Channels available */
-#define EDMA3_NUM_DMA_CHANNELS (64u)
+#define EDMA3_NUM_DMA_CHANNELS (64U)
/** Number of QDMA Channels available */
-#define EDMA3_NUM_QDMA_CHANNELS (8u)
+#define EDMA3_NUM_QDMA_CHANNELS (8U)
/** Number of Event Queues available */
-#define EDMA3_0_NUM_EVTQUE (4u)
+#define EDMA3_0_NUM_EVTQUE (4U)
/** Number of Transfer Controllers available */
-#define EDMA3_0_NUM_TC (4u)
+#define EDMA3_0_NUM_TC (4U)
/** Number of Regions */
-#define EDMA3_0_NUM_REGIONS (2u)
+#define EDMA3_0_NUM_REGIONS (2U)
/** Interrupt no. for Transfer Completion */
-#define EDMA3_0_CC_XFER_COMPLETION_INT (34u)
+#define EDMA3_0_CC_XFER_COMPLETION_INT (34U)
/** Interrupt no. for CC Error */
-#define EDMA3_0_CC_ERROR_INT (35u)
+#define EDMA3_0_CC_ERROR_INT (35U)
/** Interrupt no. for TCs Error */
-#define EDMA3_0_TC0_ERROR_INT (36u)
-#define EDMA3_0_TC1_ERROR_INT (37u)
-#define EDMA3_0_TC2_ERROR_INT (0u)
-#define EDMA3_0_TC3_ERROR_INT (0u)
-#define EDMA3_0_TC4_ERROR_INT (0u)
-#define EDMA3_0_TC5_ERROR_INT (0u)
-#define EDMA3_0_TC6_ERROR_INT (0u)
-#define EDMA3_0_TC7_ERROR_INT (0u)
+#define EDMA3_0_TC0_ERROR_INT (36U)
+#define EDMA3_0_TC1_ERROR_INT (37U)
+#define EDMA3_0_TC2_ERROR_INT (0U)
+#define EDMA3_0_TC3_ERROR_INT (0U)
+#define EDMA3_0_TC4_ERROR_INT (0U)
+#define EDMA3_0_TC5_ERROR_INT (0U)
+#define EDMA3_0_TC6_ERROR_INT (0U)
+#define EDMA3_0_TC7_ERROR_INT (0U)
/**
* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
*/
/* EDMA 0 */
-#define EDMA3_0_HWI_INT_XFER_COMP (7u)
-#define EDMA3_0_HWI_INT_CC_ERR (7u)
-#define EDMA3_0_HWI_INT_TC0_ERR (7u)
-#define EDMA3_0_HWI_INT_TC1_ERR (7u)
-#define EDMA3_0_HWI_INT_TC2_ERR (7u)
-#define EDMA3_0_HWI_INT_TC3_ERR (7u)
+#define EDMA3_0_HWI_INT_XFER_COMP (7U)
+#define EDMA3_0_HWI_INT_CC_ERR (7U)
+#define EDMA3_0_HWI_INT_TC0_ERR (7U)
+#define EDMA3_0_HWI_INT_TC1_ERR (7U)
+#define EDMA3_0_HWI_INT_TC2_ERR (7U)
+#define EDMA3_0_HWI_INT_TC3_ERR (7U)
/**
* To allocate more DMA channels or TCCs, one has to modify the event mapping.
*/
/* 31 0 */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x3FC0C06Eu) /* TBD */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x3FC0C06EU) /* TBD */
/**
*
* To allocate more DMA channels or TCCs, one has to modify the event mapping.
*/
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xF3FFFFFCu) /* TBD */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xF3FFFFFCU) /* TBD */
/* Variable which will be used internally for referring number of Event Queues*/
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
+uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {
EDMA3_0_NUM_EVTQUE,
};
/* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {
+uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] = {
EDMA3_0_NUM_TC,
};
* Variable which will be used internally for referring transfer completion
* interrupt.
*/
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
{
- 0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+ 0U, EDMA3_0_CC_XFER_COMPLETION_INT, 0U, 0U, 0U, 0U, 0U, 0U,
},
};
* Variable which will be used internally for referring channel controller's
* error interrupt.
*/
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {
EDMA3_0_CC_ERROR_INT,
};
* Variable which will be used internally for referring transfer controllers'
* error interrupts.
*/
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][8] =
{
{
EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
* Variables which will be used internally for referring the hardware interrupt
* for various EDMA3 interrupts.
*/
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] = {
EDMA3_0_HWI_INT_XFER_COMP
};
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] = {
EDMA3_0_HWI_INT_CC_ERR
};
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
{
EDMA3_0_HWI_INT_TC0_ERR,
EDMA3_0_HWI_INT_TC1_ERR,
* for a channel number to a parameter entry number or, in other words,
* PaRAM entry n corresponds to channel n.
*/
- 1u,
+ 1U,
/** Existence of memory protection feature */
- 0u,
+ 0U,
/** Global Register Region of CC Registers */
EDMA3_CC_BASE_ADDR,
* device (ARM, DSP, USB, etc)
*/
{
- 0u,
- 1u,
- 2u,
- 3u,
- 0u,
- 0u,
- 0u,
- 0u
+ 0U,
+ 1U,
+ 2U,
+ 3U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* \brief To Configure the Threshold level of number of events
* in the queue watermark threshold register (QWMTHRA).
*/
{
- 16u,
- 16u,
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u
+ 16U,
+ 16U,
+ 16U,
+ 16U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* DBS values. It is defined in Bytes.
*/
{
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
+ 16U,
+ 16U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* if it exists, otherwise of no use.
*/
{
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
- 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
- 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
- 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ 0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
+ 8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
+ 16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,
+ 24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,
+ 32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U,
+ 40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,
+ 48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,
+ 56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U
},
/**
* on the mapped channel.
*/
{
- 0u, 1u, 2u, 3u,
- 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u,
- 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u,
- 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u,
- 28u, 29u, 30u, 31u,
- 32u, 33u, 34u, 35u,
- 36u, 37u, 38u, 39u,
- 40u, 41u, 42u, 43u,
- 44u, 45u, 46u, 47u,
- 48u, 49u, 50u, 51u,
- 52u, 53u, 54u, 55u,
- 56u, 57u, 58u, 59u,
- 60u, 61u, 62u, 63u
+ 0U, 1U, 2U, 3U,
+ 4U, 5U, 6U, 7U,
+ 8U, 9U, 10U, 11U,
+ 12U, 13U, 14U, 15U,
+ 16U, 17U, 18U, 19U,
+ 20U, 21U, 22U, 23U,
+ 24U, 25U, 26U, 27U,
+ 28U, 29U, 30U, 31U,
+ 32U, 33U, 34U, 35U,
+ 36U, 37U, 38U, 39U,
+ 40U, 41U, 42U, 43U,
+ 44U, 45U, 46U, 47U,
+ 48U, 49U, 50U, 51U,
+ 52U, 53U, 54U, 55U,
+ 56U, 57U, 58U, 59U,
+ 60U, 61U, 62U, 63U
},
/**
@@ -449,376 +449,376 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 1 (Associated to any DSP core) */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
},
};
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_tda3xx_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_tda3xx_cfg.c
index 568ce0de4302467152d9e4ac0dac77d13f5b4478..c277a6b94c681724c82e5c50ca264f6f5bb73cef 100644 (file)
#include <ti/sdo/edma3/rm/edma3_rm.h>
-#define NUM_SHADOW_REGIONS (8u)
+#define NUM_SHADOW_REGIONS (8U)
/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES 1u
+#define NUM_EDMA3_INSTANCES 1U
/** Number of PaRAM Sets available */
-#define EDMA3_NUM_PARAMSET (512u)
+#define EDMA3_NUM_PARAMSET (512U)
/** Number of TCCS available */
-#define EDMA3_NUM_TCC (64u)
+#define EDMA3_NUM_TCC (64U)
/** Number of DMA Channels available */
-#define EDMA3_NUM_DMA_CHANNELS (64u)
+#define EDMA3_NUM_DMA_CHANNELS (64U)
/** Number of QDMA Channels available */
-#define EDMA3_NUM_QDMA_CHANNELS (8u)
+#define EDMA3_NUM_QDMA_CHANNELS (8U)
/** Number of Event Queues available */
-#define EDMA3_0_NUM_EVTQUE (4u)
+#define EDMA3_0_NUM_EVTQUE (4U)
/** Number of Transfer Controllers available */
-#define EDMA3_0_NUM_TC (4u)
+#define EDMA3_0_NUM_TC (4U)
/** Number of Regions */
-#define EDMA3_0_NUM_REGIONS (2u)
+#define EDMA3_0_NUM_REGIONS (2U)
/** Interrupt no. for Transfer Completion */
-#define EDMA3_0_CC_XFER_COMPLETION_INT (34u)
+#define EDMA3_0_CC_XFER_COMPLETION_INT (34U)
/** Interrupt no. for CC Error */
-#define EDMA3_0_CC_ERROR_INT (35u)
+#define EDMA3_0_CC_ERROR_INT (35U)
/** Interrupt no. for TCs Error */
-#define EDMA3_0_TC0_ERROR_INT (36u)
-#define EDMA3_0_TC1_ERROR_INT (37u)
-#define EDMA3_0_TC2_ERROR_INT (0u)
-#define EDMA3_0_TC3_ERROR_INT (0u)
-#define EDMA3_0_TC4_ERROR_INT (0u)
-#define EDMA3_0_TC5_ERROR_INT (0u)
-#define EDMA3_0_TC6_ERROR_INT (0u)
-#define EDMA3_0_TC7_ERROR_INT (0u)
+#define EDMA3_0_TC0_ERROR_INT (36U)
+#define EDMA3_0_TC1_ERROR_INT (37U)
+#define EDMA3_0_TC2_ERROR_INT (0U)
+#define EDMA3_0_TC3_ERROR_INT (0U)
+#define EDMA3_0_TC4_ERROR_INT (0U)
+#define EDMA3_0_TC5_ERROR_INT (0U)
+#define EDMA3_0_TC6_ERROR_INT (0U)
+#define EDMA3_0_TC7_ERROR_INT (0U)
/** XBAR interrupt source index numbers for EDMA interrupts */
-#define XBAR_EDMA_TPCC_IRQ_REGION0 (361u)
-#define XBAR_EDMA_TPCC_IRQ_REGION1 (362u)
-#define XBAR_EDMA_TPCC_IRQ_REGION2 (363u)
-#define XBAR_EDMA_TPCC_IRQ_REGION3 (364u)
-#define XBAR_EDMA_TPCC_IRQ_REGION4 (365u)
-#define XBAR_EDMA_TPCC_IRQ_REGION5 (366u)
-#define XBAR_EDMA_TPCC_IRQ_REGION6 (367u)
-#define XBAR_EDMA_TPCC_IRQ_REGION7 (368u)
-
-#define XBAR_EDMA_TPCC_IRQ_ERR (359u)
-#define XBAR_EDMA_TC0_IRQ_ERR (370u)
-#define XBAR_EDMA_TC1_IRQ_ERR (371u)
+#define XBAR_EDMA_TPCC_IRQ_REGION0 (361U)
+#define XBAR_EDMA_TPCC_IRQ_REGION1 (362U)
+#define XBAR_EDMA_TPCC_IRQ_REGION2 (363U)
+#define XBAR_EDMA_TPCC_IRQ_REGION3 (364U)
+#define XBAR_EDMA_TPCC_IRQ_REGION4 (365U)
+#define XBAR_EDMA_TPCC_IRQ_REGION5 (366U)
+#define XBAR_EDMA_TPCC_IRQ_REGION6 (367U)
+#define XBAR_EDMA_TPCC_IRQ_REGION7 (368U)
+
+#define XBAR_EDMA_TPCC_IRQ_ERR (359U)
+#define XBAR_EDMA_TC0_IRQ_ERR (370U)
+#define XBAR_EDMA_TC1_IRQ_ERR (371U)
/**
* \brief Mapping of DMA channels 0-31 to Hardware Events from
* To allocate more DMA channels or TCCs, one has to modify the event mapping.
*/
/* 31 0 */
-#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0 (0x00000000u)
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0 (0x00000000U)
/**
*
* To allocate more DMA channels or TCCs, one has to modify the event mapping.
*/
-#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1 (0x00000000u)
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1 (0x00000000U)
* for a channel number to a parameter entry number or, in other words,
* PaRAM entry n corresponds to channel n.
*/
- 0u,
+ 0U,
/** Existence of memory protection feature */
- 0u,
+ 0U,
/** Global Register Region of CC Registers */
EDMA3_CC_BASE_ADDR,
* device (ARM, DSP, USB, etc)
*/
{
- 0u,
- 1u,
- 2u,
- 3u,
- 0u,
- 0u,
- 0u,
- 0u
+ 0U,
+ 1U,
+ 2U,
+ 3U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* \brief To Configure the Threshold level of number of events
* in the queue watermark threshold register (QWMTHRA).
*/
{
- 16u,
- 16u,
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u
+ 16U,
+ 16U,
+ 16U,
+ 16U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* DBS values. It is defined in Bytes.
*/
{
- 16u,
- 16u,
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u
+ 16U,
+ 16U,
+ 16U,
+ 16U,
+ 0U,
+ 0U,
+ 0U,
+ 0U
},
/**
* if it exists, otherwise of no use.
*/
{
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
- 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
- 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
- 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ 0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,
+ 8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,
+ 16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,
+ 24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,
+ 32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U,
+ 40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,
+ 48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,
+ 56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U
},
/**
* on the mapped channel.
*/
{
- 0u, 1u, 2u, 3u,
- 4u, 5u, 6u, 7u,
- 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u,
- 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 24u, 25u, 26u, 27u,
- 28u, 29u, 30u, 31u,
- 32u, 33u, 34u, 35u,
- 36u, 37u, 38u, 39u,
- 40u, 41u, 42u, 43u,
- 44u, 45u, 46u, 47u,
- 48u, 49u, 50u, 51u,
- 52u, 53u, 54u, 55u,
- 56u, 57u, 58u, 59u,
- 60u, 61u, 62u, 63u
+ 0U, 1U, 2U, 3U,
+ 4U, 5U, 6U, 7U,
+ 8U, 9U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 12U, 13U, 14U, 15U,
+ 16U, 17U, 18U, 19U,
+ 20U, 21U, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 24U, 25U, 26U, 27U,
+ 28U, 29U, 30U, 31U,
+ 32U, 33U, 34U, 35U,
+ 36U, 37U, 38U, 39U,
+ 40U, 41U, 42U, 43U,
+ 44U, 45U, 46U, 47U,
+ 48U, 49U, 50U, 51U,
+ 52U, 53U, 54U, 55U,
+ 56U, 57U, 58U, 59U,
+ 60U, 61U, 62U, 63U
},
/**
@@ -311,376 +311,376 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SH
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 1 (Associated to any DSP core) */
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 159 128 191 160 223 192 255 224 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 287 256 319 288 351 320 383 352 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
/* 415 384 447 416 479 448 511 480 */
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+ 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* ownQdmaChannels */
/* 31 0 */
- {0x000000FFu},
+ {0x000000FFU},
/* ownTccs */
/* 31 0 63 32 */
- {0xFFFFFFFFu, 0xFFFFFFFFu},
+ {0xFFFFFFFFU, 0xFFFFFFFFU},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00u},
+ {0x00U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00u, 0x00u},
+ {0x00U, 0x00U},
},
/* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
/* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* ownDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* ownQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* ownTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,
/* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+ 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},
/* resvdDmaChannels */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
/* resvdQdmaChannels */
/* 31 0 */
- {0x00000000u},
+ {0x00000000U},
/* resvdTccs */
/* 31 0 63 32 */
- {0x00000000u, 0x00000000u},
+ {0x00000000U, 0x00000000U},
},
},
};