Misra C Fixes: DRA72x Files
authorSunil MS <x0190988@ti.com>
Wed, 15 Oct 2014 12:09:30 +0000 (17:39 +0530)
committerSunil MS <x0190988@ti.com>
Mon, 20 Oct 2014 14:14:47 +0000 (19:44 +0530)
MISRA.ASM.ENCAPS
MISRA.BITS.NOT_UNSIGNED
MISRA.BUILTIN_NUMERIC
MISRA.CVALUE.IMPL.CAST
MISRA.DECL.ARRAY_SIZE
MISRA.DEFINE.BADEXP
MISRA.EXPR.PARENS
MISRA.FUNC.NOPROT.DEF
MISRA.FUNC.UNNAMED.PARAMS
MISRA.IF.NO_COMPOUND
MISRA.IF.NO_ELSE
MISRA.INIT.BRACES
MISRA.LITERAL.UNSIGNED.SUFFIX
MISRA.VAR.UNIQUE.STATIC

Change-Id: Idf2f31dd1c42d8e1a4c7ab068a53a917e64c0619
Signed-off-by: Sunil MS <x0190988@ti.com>
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_arm_int_reg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c
packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c

index 88276f5ce2b9705c2be407956249e884c671e807..0f6b426d80a38f503ee759c9f16e134de1cc7a46 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * sample_tda2xx_int_reg.c
+ * sample_dra72x_int_reg.c
  *
  * Platform specific interrupt registration and un-registration routines.
  *
   */
 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 {
-                                                (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorInt[];
-extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
-extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern uint32_t hwIntXferComp[];
-extern uint32_t hwIntCcErr[];
-extern uint32_t hwIntTcErr[];
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
 
 extern uint32_t dsp_num;
 /* This variable has to be used as an extern */
@@ -82,8 +82,8 @@ Hwi_Handle hwiCCErrInt;
 Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
 
 /* External Instance Specific Configuration Structure */
-extern EDMA3_DRV_GblXbarToChanConfigParams
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+extern EDMA3_DRV_GblXbarToChanConfigParams 
+                                                               sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
 
 typedef struct  {
     volatile Uint32 TPCC_EVTMUX[32];
@@ -115,6 +115,17 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
 
 void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
 
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (uint32_t edma3Id);
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (uint32_t edma3Id);
+
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
+                                   uint32_t edma3Id);
+                                   
+void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
+
 /**  To Register the ISRs with the underlying OS, if required. */
 void registerEdma3Interrupts (uint32_t edma3Id)
     {
@@ -141,7 +152,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
                                        ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
                                        (const Hwi_Params *) (&hwiParams),
                                        &eb);
-    if (TRUE == Error_check(&eb))
+    if ((bool)TRUE == Error_check(&eb))
     {
         System_printf("HWI Create Failed\n",Error_getCode(&eb));
     }
@@ -158,7 +169,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
                 (const Hwi_Params *) (&hwiParams),
                 &eb);
 
-    if (TRUE == Error_check(&eb))
+    if ((bool)TRUE == Error_check(&eb))
     {
         System_printf("HWI Create Failed\n",Error_getCode(&eb));
     }
@@ -176,7 +187,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
                     (ptrEdma3TcIsrHandler[numTc]),
                     (const Hwi_Params *) (&hwiParams),
                     &eb);
-        if (TRUE == Error_check(&eb))
+        if ((bool)TRUE == Error_check(&eb))
         {
             System_printf("HWI Create Failed\n",Error_getCode(&eb));
         }
@@ -212,11 +223,11 @@ void registerEdma3Interrupts (uint32_t edma3Id)
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
-       static UInt32 cookie = 0;
+       static UInt32 cookiee = 0;
     uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
-    cookie = Hwi_disable();
+    cookiee = Hwi_disable();
 
     Hwi_delete(&hwiCCXferCompInt);
     Hwi_delete(&hwiCCErrInt);
@@ -226,7 +237,7 @@ void unregisterEdma3Interrupts (uint32_t edma3Id)
         numTc++;
        }
     /* Restore interrupts */
-    Hwi_restore(cookie);
+    Hwi_restore(cookiee);
     }
 
 /**
@@ -282,17 +293,17 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
                (chanNum < EDMA3_NUM_TCC))
                {
-               scrRegOffset = chanNum / 2;
-               scrChanOffset = chanNum - (scrRegOffset * 2);
-               xBarEvtNum = eventNum + 1;
-
+               scrRegOffset = chanNum / 2U;
+               scrChanOffset = chanNum - (scrRegOffset * 2U);
+               xBarEvtNum = eventNum + 1U;
+               
                switch(scrChanOffset)
                        {
                        case 0:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
                                break;
-                       case 1:
+                       case 1U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
@@ -328,5 +339,8 @@ EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
 
 void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
     {
+#ifdef EDMA3_RM_DEBUG
+    /*  Added to fix Misra C error */
     printf("memory Protection error");
+#endif
     }
index 4a3dbdc5a984efa838be222dd508b819476bf105..788472fe4115f2187135552b1d47195d2faf4db7 100644 (file)
@@ -57,44 +57,81 @@ int32_t myCoreNum;
 #define PID0_ADDRESS 0xE00FFFE0
 #define CORE_ID_C0 0x0
 #define CORE_ID_C1 0x1
-uint16_t determineProcId()
-{
-uint16_t regionNo = numEdma3Instances;
-#ifdef BUILD_TDA2XX_DSP
-extern __cregister volatile uint32_t DNUM;
-#endif
-myCoreNum = numDsps;
-#ifdef BUILD_TDA2XX_MPU
 
+#ifdef BUILD_DRA72X_MPU
+void __inline readProcFeatureReg(void);
+void __inline readProcFeatureReg(void)
+{
     asm ("    push    {r0-r2} \n\t"
             "    MRC p15, 0, r0, c0, c0, 5\n\t"
                 "    LDR      r1, =myCoreNum\n\t"
                 "    STR      r0, [r1]\n\t"
                 "    pop    {r0-r2}\n\t");
-       if((myCoreNum & 0x03) == 1)
-               regionNo = 1;
-       else
-               regionNo = 0;
+}
+#endif
+
+int8_t*  getGlobalAddr(int8_t* addr);
+
+uint16_t isGblConfigRequired(uint32_t dspNum);
+
+uint16_t determineProcId(void);
+
+uint16_t determineProcId(void)
+{
+uint16_t regionNo = (uint16_t)numEdma3Instances;
+#ifdef BUILD_DRA72X_DSP
+extern __cregister volatile uint32_t DNUM;
+#endif
+myCoreNum = (int32_t)numDsps;
+#ifdef BUILD_DRA72X_MPU
+
+    readProcFeatureReg();
+               regionNo = 0U;
+/* myCoreNum is always 1 here, fix for klocwork error(Unreachable code) */
+       if(((uint32_t)myCoreNum & 0x03U) == 1U)
+    {
+               regionNo = 1U;
+    }
 #elif defined(BUILD_TDA2XX_IPU)
 myCoreNum = (*(uint32_t *)(PID0_ADDRESS));
 if(Core_getIpuId() == 1){
        if(myCoreNum == CORE_ID_C0)
-               regionNo = 4;
+    {
+               regionNo = 4U;
+    }
        else if (myCoreNum == CORE_ID_C1)
-               regionNo = 5;
+    {
+               regionNo = 5U;
+    }
+    else
+    {
+        ;/* Nothing to be done */
+    }
 }
 if(Core_getIpuId() == 2){
        if(myCoreNum == CORE_ID_C0)
-               regionNo = 6;
+    {
+               regionNo = 6U;
+    }
        else if (myCoreNum == CORE_ID_C1)
-               regionNo = 7;
+    {
+               regionNo = 7U;
+    }
+    else
+    {
+        ;/* Nothing to be done */
+    }
 }
-#elif defined BUILD_TDA2XX_DSP
+#elif defined BUILD_DRA72X_DSP
        myCoreNum = DNUM;
        if(myCoreNum == 0)
-               regionNo = 2;
+    {
+               regionNo = 2U;
+    }
        else
-               regionNo = 3;
+    {
+               regionNo = 3U;
+    }
 #endif
        return regionNo;
 }
@@ -107,7 +144,7 @@ uint16_t isGblConfigRequired(uint32_t dspNum)
 {
     (void) dspNum;
 
-    return 1;
+    return 1U;
 }
 
 /* Semaphore handles */
@@ -173,31 +210,31 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)
 
 #ifdef BUILD_DRA72X_MPU
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A15
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_A15_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A15
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_A15
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_A15)
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_A15)
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_A15_XBAR_INST_NO)
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_A15)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_A15)
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)
 
 #elif defined BUILD_DRA72X_DSP
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_DSP_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_DSP
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_DSP
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_DSP_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_DSP_XBAR_INST_NO
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_DSP)
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_DSP)
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_DSP_XBAR_INST_NO)
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_DSP)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_DSP)
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_DSP_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_DSP_XBAR_INST_NO)
 
 #elif defined BUILD_DRA72X_IPU
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU_C0
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_IPU)
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_IPU_XBAR_INST_NO)
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_IPU)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_IPU)
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_IPU_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_IPU_XBAR_INST_NO)
 
 #else
 #define EDMA3_CC_XFER_COMPLETION_INT                    (0U)
@@ -205,8 +242,8 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define CC_ERROR_INT_XBAR_INST_NO                       (0U)
 #define EDMA3_TC0_ERROR_INT                             (0U)
 #define EDMA3_TC1_ERROR_INT                             (0U)
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)
 #endif
 
 #define EDMA3_TC2_ERROR_INT                             (0U)
@@ -302,6 +339,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 /* Variable which will be used internally for referring number of Event Queues*/
 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
                                                         EDMA3_NUM_EVTQUE,
+                                                        EDMA3_NUM_EVTQUE
                                                     };
 
 /* Variable which will be used internally for referring number of TCs.        */
@@ -395,14 +433,22 @@ uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
         EDMA3_HWI_INT_TC0_ERR,
         EDMA3_HWI_INT_TC1_ERR,
         EDMA3_HWI_INT_TC2_ERR,
-        EDMA3_HWI_INT_TC3_ERR
+        EDMA3_HWI_INT_TC3_ERR,
+        0,
+        0,
+        0,
+        0
     },
     /* EDMA3 INSTANCE# 1 */
     {
         EDMA3_HWI_INT_TC0_ERR,
         EDMA3_HWI_INT_TC1_ERR,
         EDMA3_HWI_INT_TC2_ERR,
-        EDMA3_HWI_INT_TC3_ERR
+        EDMA3_HWI_INT_TC3_ERR,
+        0,
+        0,
+        0,
+        0
     }
 };
 
@@ -1577,6 +1623,97 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 /* Driver Instance Cross bar event to channel map Initialization Configuration */
 EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Event to channel map for region 0 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 1 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 2 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 3 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 4 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 5 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 6 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 7 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+    },
     /* EDMA3 INSTANCE# 0 */
     {
         /* Event to channel map for region 0 */
index 7aaf43c01ef81b1d7fcb7af8876cba096d0dc3f6..ff661dd22d4e2d854b6785a7ec05c9a97095d1d0 100644 (file)
 #define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)
 
 #ifdef BUILD_DRA72X_MPU
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A15
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_A15_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A15
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_A15
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_A15)
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_A15)
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_A15_XBAR_INST_NO)
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_A15)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_A15)
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)
 
 #elif defined BUILD_DRA72X_DSP
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_DSP_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_DSP
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_DSP
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_DSP_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_DSP_XBAR_INST_NO
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_DSP)
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_DSP)
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_DSP_XBAR_INST_NO)
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_DSP)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_DSP)
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_DSP_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_DSP_XBAR_INST_NO)
 
 #elif defined BUILD_DRA72X_IPU
-#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU_C0
-#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU
-#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU_XBAR_INST_NO
-#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU
-#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_IPU)
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_IPU_XBAR_INST_NO)
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_IPU)
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_IPU)
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_IPU_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_IPU_XBAR_INST_NO)
 
 #else
 #define EDMA3_CC_XFER_COMPLETION_INT                    (0U)
 #define CC_ERROR_INT_XBAR_INST_NO                       (0U)
 #define EDMA3_TC0_ERROR_INT                             (0U)
 #define EDMA3_TC1_ERROR_INT                             (0U)
-#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
-#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)
 #endif
 
 #define EDMA3_TC2_ERROR_INT                             (0U)
 #define EDMA3_TC6_ERROR_INT                             (0U)
 #define EDMA3_TC7_ERROR_INT                             (0U)
 
-#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19u)
-#define DSP1_EDMA3_CC_ERROR_INT                         (27u)
-#define DSP1_EDMA3_TC0_ERROR_INT                        (28u)
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19U)
+#define DSP1_EDMA3_CC_ERROR_INT                         (27U)
+#define DSP1_EDMA3_TC0_ERROR_INT                        (28U)
 #define DSP1_EDMA3_TC1_ERROR_INT                        (29U)
 
 /** XBAR interrupt source index numbers for EDMA interrupts */
-#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)
-#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)
-#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)
-#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)
-#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)
-#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)
-#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)
-#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)
-
-#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)
-#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)
-#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361U)
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362U)
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363U)
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364U)
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365U)
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366U)
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367U)
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368U)
+
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359U)
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370U)
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371U)
 
 /**
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                       /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06Eu)  /* TBD */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFu)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06EU)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFU)  /* TBD */
 
 
 /**
  *
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCu) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCU) /* TBD */
 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000U) /* TBD */