Support of OMAP Tesla platform DEV_EDMA3_LLD_02_11_02_03_RC03
authorVillarreal Jesse <jesse.villarreal@ti.com>
Thu, 19 May 2011 12:22:40 +0000 (17:52 +0530)
committerPrasad Konnur <x0153534@palin02.india.ti.com>
Thu, 19 May 2011 12:22:40 +0000 (17:52 +0530)
15 files changed:
edma3_lld_release.bat
examples/edma3_driver/evmOMAP4/makefile [new file with mode: 0644]
examples/edma3_driver/evmOMAP4/rtsc_config/edma3_drv_bios6_omap4_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmOMAP4/sample_app/linker.cmd [new file with mode: 0644]
makerules/env.mk
makerules/platform.mk
makerules/rules_64t.mk [new file with mode: 0644]
makerules/rules_m3.mk
packages/config.bld
packages/makefile
packages/ti/sdo/edma3/drv/sample/makefile
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omap4_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omap4_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/makefile
packages/ti/sdo/edma3/rm/src/configs/edma3_omap4_cfg.c [new file with mode: 0644]

index 62c6df0e280a1c77402ab63f16901aca3d2e495f..7e42d05c245c43cad85653a4331a7087d711626e 100755 (executable)
@@ -1,6 +1,6 @@
 set PATH=C:/PROGRA~1/TEXASI~1/xdctools_3_20_07_86\r
 \r
-set ROOTDIR=E:/EDMA/edma3_lld_02_11_01_02\r
+set ROOTDIR=E:/EDMA/edma3_lld_02_11_02_03\r
 \r
 cd packages\r
 \r
diff --git a/examples/edma3_driver/evmOMAP4/makefile b/examples/edma3_driver/evmOMAP4/makefile
new file mode 100644 (file)
index 0000000..6ca3ccd
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_omap4_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files 
+#  need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_omap4_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
+              qdma_link_test.c
+CFLAGS_LOCAL_COMMON = 
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example: 
+#   SRCS_<core/SoC/platform-name> = 
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk 
+#     and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evmOMAP4/rtsc_config/edma3_drv_bios6_omap4_st_sample.cfg b/examples/edma3_driver/evmOMAP4/rtsc_config/edma3_drv_bios6_omap4_st_sample.cfg
new file mode 100644 (file)
index 0000000..a48aea8
--- /dev/null
@@ -0,0 +1,19 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
+var ECM       = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi   = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Startup   = xdc.useModule ("xdc.runtime.Startup");
+var System    = xdc.useModule ("xdc.runtime.System");
+var Log       = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+
+ECM.eventGroupHwiNum[0] = 9;
+ECM.eventGroupHwiNum[1] = 9;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 9;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
diff --git a/examples/edma3_driver/evmOMAP4/sample_app/linker.cmd b/examples/edma3_driver/evmOMAP4/sample_app/linker.cmd
new file mode 100644 (file)
index 0000000..c8fd4c0
--- /dev/null
@@ -0,0 +1,5 @@
+SECTIONS
+{
+       .my_sect_iram  > IRAM
+       .my_sect_ddr  > SDRAM
+}
index d786f35e843632677b368cc50397d7b7d06a9fa1..7242dbc765a0cec0dd445cd00a4b85e2799f90d8 100755 (executable)
@@ -7,7 +7,7 @@
 # Directory where all internal software packages are located; typically 
 #  those that are checked into version controlled repository. In this case all
 #  the OMX components and SDK/OMX demo.
-INTERNAL_SW_ROOT = E:/EDMA/edma3_lld_02_11_01_02
+INTERNAL_SW_ROOT = D:/PSP/EDMA3_BIOS6/edma_drv/edma3_lld_02_11_02_03
 
 # Directory where all external (imported) software packages are located; typically 
 #  those that are NOT checked into version controlled repository. In this case,
@@ -18,7 +18,7 @@ EXTERNAL_SW_ROOT = C:/PROGRA~1/TEXASI~1
 #   - specify the directory where you want to place the object, archive/library,
 #     binary and other generated files in a different location than source tree
 #   - or leave it blank to place then in the same tree as the source
-#DEST_ROOT = E:/Temp/sdk5008_outfiles
+#DEST_ROOT = E:/Temp/edma3_lld_02_11_02_03
 
 # Utilities directory. This is required only if the build machine is Windows.
 #   - specify the installation directory of utility which supports POSIX commands
@@ -50,18 +50,18 @@ include $(edma3_lld_PATH)/packages/component.mk
 # Tools paths
 #
 # Cortex-M3
-CODEGEN_PATH_M3 = $(EXTERNAL_SW_ROOT)/TMS470~1.3
+CODEGEN_PATH_M3 = $(EXTERNAL_SW_ROOT)/TMS470~1.4
 
 # Cortex-A8
-CODEGEN_PATH_A8 = $(EXTERNAL_SW_ROOT)/TMS470~1.3
+CODEGEN_PATH_A8 = $(EXTERNAL_SW_ROOT)/TMS470~1.4
 
 # ARM-9
-CODEGEN_PATH_ARM9 = $(EXTERNAL_SW_ROOT)/TMS470~1.3
+CODEGEN_PATH_ARM9 = $(EXTERNAL_SW_ROOT)/TMS470~1.4
 
 # DSP - Since same toolchain does not support COFF and ELF, there are two entries
 #        This would go away when one version supports both formats
 CODEGEN_PATH_DSP = $(EXTERNAL_SW_ROOT)/C6000C~1.4
-CODEGEN_PATH_DSPELF = $(EXTERNAL_SW_ROOT)/C6000C~1.0
+CODEGEN_PATH_DSPELF = $(EXTERNAL_SW_ROOT)/C6000C~2.0
 
 
 # Commands commonly used within the make files
@@ -88,6 +88,7 @@ endif
 # XDC Config.bld file (required for configuro) ; Derives from top-level omx_PATH
 CONFIG_BLD_XDC_674 = $(edma3_lld_PATH)/packages/_config.bld
 CONFIG_BLD_XDC_64p = $(edma3_lld_PATH)/packages/_config.bld
+CONFIG_BLD_XDC_64t = $(edma3_lld_PATH)/packages/_config.bld
 CONFIG_BLD_XDC_a8 = $(edma3_lld_PATH)/packages/_config.bld
 CONFIG_BLD_XDC_arm9 = $(edma3_lld_PATH)/packages/_config.bld
 CONFIG_BLD_XDC_66 = $(edma3_lld_PATH)/packages/_config.bld
index 7e2f53857d5dfa835d7c0732accc40d736ebfb92..05c9a181b920328ef9e61012f8de2414d98966fd 100755 (executable)
@@ -92,6 +92,12 @@ ifeq ($(PLATFORM),da830-evm)
  PLATFORM_XDC = "ti.platforms.evmDA830"
 endif
 
+# omap4 EVM
+ifeq ($(PLATFORM),omap4-evm)
+ SOC = omap4
+ PLATFORM_XDC = "ti.platforms.sdp4430"
+endif
+
 # Generic platform
 ifeq ($(PLATFORM),generic)
  SOC = generic
@@ -149,6 +155,9 @@ ifeq ($(CORE),c6xdsp)
  ifeq ($(SOC),c6678)
   ISA = 66
  endif
+ ifeq ($(SOC),omap4)
+  ISA = 64t
+ endif
 endif
 
 # Platform and SOC is generic; use the core name same as ISA (eg: 674)
@@ -236,6 +245,35 @@ ifeq ($(ISA),64p)
   ASMEXT = s$(FORMAT_EXT)64P$(ENDIAN_EXT)
 endif
 
+ifeq ($(ISA),64t)
+  ifeq ($(FORMAT),ELF)
+   ifeq ($(ENDIAN),big)
+    TARGET_XDC = ti.targets.elf.C64T_big_endian
+   else
+    TARGET_XDC = ti.targets.elf.C64T
+   endif
+    FORMAT_EXT = e
+  else
+   ifeq ($(ENDIAN),big)
+    TARGET_XDC = ti.targets.C64T_big_endian
+   else
+    TARGET_XDC = ti.targets.C64T
+   endif
+  endif
+  
+  # If ENDIAN is set to "big", set ENDIAN_EXT to "e", that would be used in
+  #    in the filename extension of object/library/executable files
+  ifeq ($(ENDIAN),big)
+    ENDIAN_EXT = e
+  endif
+
+  # Define the file extensions
+  OBJEXT = o$(FORMAT_EXT)64T$(ENDIAN_EXT)
+  LIBEXT = a$(FORMAT_EXT)64T$(ENDIAN_EXT)
+  EXEEXT = x$(FORMAT_EXT)64T$(ENDIAN_EXT)
+  ASMEXT = s$(FORMAT_EXT)64T$(ENDIAN_EXT)
+endif
+
 ifeq ($(ISA),66)
   ifeq ($(FORMAT),ELF)
    ifeq ($(ENDIAN),big)
diff --git a/makerules/rules_64t.mk b/makerules/rules_64t.mk
new file mode 100644 (file)
index 0000000..54df424
--- /dev/null
@@ -0,0 +1,222 @@
+# Filename: rules_64p.mk
+#
+# Make rules for 64p - This file has all the common rules and defines required
+#                     for DSP c64+ ISA
+#
+# This file needs to change when:
+#     1. Code generation tool chain changes (currently it uses TI CGT)
+#     2. Internal switches (which are normally not touched) has to change
+#     3. XDC specific switches change
+#     4. a rule common for c64p ISA has to be added or modified
+
+# Set compiler/archiver/linker commands and include paths - Currently different
+#  for ELF and COFF. In a future release of the toolchain, it would merge.
+ifeq ($(FORMAT),COFF)
+ CODEGEN_PATH = $(CODEGEN_PATH_DSP)
+ CODEGEN_INCLUDE = $(CODEGEN_PATH_DSP)/include
+ CC = $(CODEGEN_PATH_DSP)/bin/cl6x
+ AR = $(CODEGEN_PATH_DSP)/bin/ar6x
+ LNK = $(CODEGEN_PATH_DSP)/bin/lnk6x
+endif
+ifeq ($(FORMAT),ELF)
+ CODEGEN_PATH = $(CODEGEN_PATH_DSPELF)
+ CODEGEN_INCLUDE = $(CODEGEN_PATH_DSPELF)/include
+ CC = $(CODEGEN_PATH_DSPELF)/bin/cl6x
+ AR = $(CODEGEN_PATH_DSPELF)/bin/ar6x
+ LNK = $(CODEGEN_PATH_DSPELF)/bin/lnk6x
+endif
+
+# Derive a part of RTS Library name based on ENDIAN: little/big
+ifeq ($(ENDIAN),little)
+  #RTSLIB_ENDIAN = 
+  XDCINTERNAL_DEFINES += -Dxdc_target_name__=C64P
+else
+  CSWITCH_ENDIAN = -me
+  RTSLIB_ENDIAN = e
+  XDCINTERNAL_DEFINES += -DBIG_ENDIAN_MODE -Dxdc_target_name__=C64P_big_endian
+endif
+
+# Derive compiler switch and part of RTS Library name based on FORMAT: COFF/ELF
+ifeq ($(FORMAT),COFF)
+  CSWITCH_FORMAT = 
+  #RTSLIB_FORMAT = 
+  XDCINTERNAL_DEFINES += -Dxdc_target_types__=ti/targets/std.h -Dxdc_bld__vers_1_0_7_0_0
+endif
+ifeq ($(FORMAT),ELF)
+  CSWITCH_FORMAT = --abi=elfabi 
+  RTSLIB_FORMAT = _elf
+  XDCINTERNAL_DEFINES += -Dxdc_target_types__=ti/targets/elf/std.h -Dxdc_bld__vers_1_0_7_2_0_10271
+endif
+
+# XDC Specific defines
+ifneq ($(XDC_CFG_FILE_$(CORE)),)
+  ifeq ($(PROFILE_$(CORE)),debug)
+    CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)$(ISA)$(RTSLIB_ENDIAN)
+  endif
+  ifeq ($(PROFILE_$(CORE)),release)
+    CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)$(ISA)$(RTSLIB_ENDIAN)
+  endif
+  ifeq ($(PROFILE_$(CORE)),whole_program_debug)
+    CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+    CFG_LNKFILENAMEPART_XDC=_x
+  endif
+  CFG_CFILE_XDC =$(patsubst %.cfg,%_$(CFG_CFILENAMEPART_XDC).c,$(notdir $(XDC_CFG_FILE_$(CORE))))
+  CFG_C_XDC = $(addprefix $(CONFIGURO_DIR)/package/cfg/,$(CFG_CFILE_XDC))
+  XDCLNKCMD_FILE =$(patsubst %.c, %$(CFG_LNKFILENAMEPART_XDC)_x.xdl, $(CFG_C_XDC))
+  CFG_COBJ_XDC = $(patsubst %.c,%.$(OBJEXT),$(CFG_CFILE_XDC))
+#  OBJ_PATHS += $(CFG_COBJ_XDC)
+  LNKCMD_FILE = $(CONFIGURO_DIR)/linker_mod.cmd
+  SPACE := 
+  SPACE += 
+  XDC_GREP_STRING = $(CONFIGURO_DIRNAME)
+#  XDC_GREP_STRING = $(subst $(SPACE),\|,$(COMP_LIST_$(CORE)))
+#  XDC_GREP_STRING += \|$(CONFIGURO_DIRNAME)
+endif
+
+# Internal CFLAGS - normally doesn't change
+CFLAGS_INTERNAL = -c -qq -pdsw225 -mvtesla $(CSWITCH_FORMAT) $(CSWITCH_ENDIAN) -mo -eo.$(OBJEXT) -ea.$(ASMEXT)
+CFLAGS_DIROPTS = -fr=$(OBJDIR) -fs=$(OBJDIR)
+
+# CFLAGS based on profile selected
+ifeq ($(PROFILE_$(CORE)), debug)
+ CFLAGS_INTERNAL += --symdebug:dwarf
+ CFLAGS_XDCINTERNAL = -Dxdc_bld__profile_debug -D_DEBUG_=1 
+ ifndef MODULE_NAME
+  CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_CFG_BASE_FILE_NAME)_xem3.h' 
+ endif
+ LNKFLAGS_INTERNAL_PROFILE = 
+endif
+ifeq ($(PROFILE_$(CORE)), release)
+ CFLAGS_INTERNAL += -O2
+ CFLAGS_XDCINTERNAL = -Dxdc_bld__profile_release -DGENERIC
+ ifndef MODULE_NAME
+  CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_CFG_BASE_FILE_NAME)_pem3.h' 
+ endif
+ LNKFLAGS_INTERNAL_PROFILE = -o2
+# LNKFLAGS_INTERNAL_PROFILE = 
+endif
+CFLAGS_XDCINTERNAL += $(XDCINTERNAL_DEFINES)
+
+# Following 'if...' block is for an application; to add a #define for each
+#   component in the build. This is required to know - at compile time - which
+#   components are on which core.
+ifndef MODULE_NAME
+  # Derive list of all packages from each of the components needed by the app
+  PKG_LIST_M3_LOCAL = $(foreach COMP,$(COMP_LIST_$(CORE)),$($(COMP)_PKG_LIST))
+  
+  # Defines for the app and cfg source code to know which components/packages
+  # are included in the build for the local CORE...
+  CFLAGS_APP_DEFINES = $(foreach PKG,$(PKG_LIST_M3_LOCAL),-D_LOCAL_$(PKG)_)
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_M3_LOCAL),-D_BUILD_$(PKG)_)
+  
+  ifeq ($(CORE),m3vpss)
+    PKG_LIST_M3_REMOTE = $(foreach COMP,$(COMP_LIST_m3video),$($(COMP)_PKG_LIST))
+    CFLAGS_APP_DEFINES += -D_LOCAL_CORE_m3vpss_
+  endif
+  ifeq ($(CORE),m3video)
+    PKG_LIST_M3_REMOTE = $(foreach COMP,$(COMP_LIST_m3vpss),$($(COMP)_PKG_LIST))
+    CFLAGS_APP_DEFINES += -D_LOCAL_CORE_m3video_
+  endif
+  PKG_LIST_A8_REMOTE = $(foreach COMP,$(COMP_LIST_a8host),$($(COMP)_PKG_LIST))
+
+  # Defines for the app and cfg source code to know which components/packages
+  # are included in the build for the remote CORE...
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_M3_REMOTE),-D_REMOTE_$(PKG)_)
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_M3_REMOTE),-D_BUILD_$(PKG)_)
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_A8_REMOTE),-D_REMOTE_$(PKG)_)
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_A8_REMOTE),-D_BUILD_$(PKG)_)
+endif
+
+# Assemble CFLAGS from all other CFLAGS definitions
+_CFLAGS = $(CFLAGS_INTERNAL) $(CFLAGS_GLOBAL_$(CORE)) $(CFLAGS_XDCINTERNAL) $(CFLAGS_LOCAL_COMMON) $(CFLAGS_LOCAL_$(CORE)) $(CFLAGS_LOCAL_$(PLATFORM)) $(CFLAGS_LOCAL_$(SOC)) $(CFLAGS_APP_DEFINES) $(CFLAGS_COMP_COMMON) $(CFLAGS_GLOBAL_$(PLATFORM))
+
+# Object file creation
+# The first $(CC) generates the dependency make files for each of the objects
+# The second $(CC) compiles the source to generate object
+$(OBJ_PATHS): $(OBJDIR)/%.$(OBJEXT): %.c
+       $(ECHO) \# Compiling $< to $@ ...
+       $(CC) -ppd=$(DEPFILE).P $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $<
+       $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $<
+
+# Archive flags - normally doesn't change
+ARFLAGS = rq
+
+# Archive/library file creation
+$(LIBDIR)/$(MODULE_NAME).$(LIBEXT) : $(OBJ_PATHS)
+       $(ECHO) \#
+       $(ECHO) \# Archiving $(OBJ_PATHS) into $@...
+       $(ECHO) \#
+       $(AR) $(ARFLAGS) $@ $(OBJ_PATHS)
+
+# Linker options and rules
+LNKFLAGS_INTERNAL_COMMON = --warn_sections -q -e=_c_int00 --silicon_version=64+ -c 
+
+# Assemble Linker flags from all other LNKFLAGS definitions
+_LNKFLAGS = $(LNKFLAGS_INTERNAL_COMMON) $(LNKFLAGS_INTERNAL_PROFILE) $(LNKFLAGS_GLOBAL_$(CORE)) $(LNKFLAGS_LOCAL_COMMON) $(LNKFLAGS_LOCAL_$(CORE)) 
+
+# Path of the RTS library - normally doesn't change for a given tool-chain
+RTSLIB_PATH = $(CODEGEN_PATH)/lib/rts64plus$(RTSLIB_ENDIAN)$(RTSLIB_FORMAT).lib
+LIB_PATHS += $(RTSLIB_PATH)
+
+LNK_LIBS = $(addprefix -l,$(LIB_PATHS))
+ifeq ($(DEST_ROOT),)
+ TMPOBJDIR = .
+else
+ TMPOBJDIR = $(OBJDIR)
+endif
+# Linker - to create executable file
+$(BINDIR)/$(APP_NAME)_$(CORE)_$(PROFILE_$(CORE)).$(EXEEXT) : $(OBJ_PATHS) $(LIB_PATHS) $(LNKCMD_FILE) $(OBJDIR)/$(CFG_COBJ_XDC)
+       $(ECHO) \# Linking into $@
+       $(ECHO) \#
+       cd $(TMPOBJDIR) && $(LNK) $(_LNKFLAGS) $(OBJ_PATHS) $(OBJDIR)/$(CFG_COBJ_XDC) -l$(LNKCMD_FILE) sample_app/linker.cmd -o $@ -m $@.map $(LNK_LIBS)
+       $(ECHO) \#
+       $(ECHO) \# $@ created.
+       $(ECHO) \#
+
+# XDC specific - assemble XDC-Configuro command
+CONFIGURO_CMD = $(xdc_PATH)/xs xdc.tools.configuro --generationOnly -o $(CONFIGURO_DIR) -t $(TARGET_XDC) -p $(PLATFORM_XDC) \
+               -r whole_program -c $(CODEGEN_PATH) -b $(CONFIG_BLD_XDC_$(ISA)) $(XDC_CFG_FILE_NAME)
+_XDC_GREP_STRING = \"$(XDC_GREP_STRING)\"
+EGREP_CMD = $(EGREP) -ivw $(XDC_GREP_STRING) $(XDCLNKCMD_FILE)
+
+ifneq ($(DEST_ROOT),)
+ DEST_ROOT += /
+endif
+# Invoke configuro for the rest of the components
+#  NOTE: 1. String handling is having issues with various make versions when the 
+#           cammand is directly tried to be given below. Hence, as a work-around, 
+#           the command is re-directed to a file (shell or batch file) and then 
+#           executed
+#        2. The linker.cmd file generated, includes the libraries generated by
+#           XDC. An egrep to search for these and omit in the .cmd file is added
+#           after configuro is done
+#$(CFG_CFILE_XDC) : $(XDC_CFG_FILE)
+xdc_configuro : $(XDC_CFG_FILE)
+       $(ECHO) \# Invoking configuro...
+       $(ECHO) -e $(CONFIGURO_CMD) > $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat
+       $(CHMOD) a+x $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat
+       $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat
+       $(CP) $(XDCLNKCMD_FILE) $(LNKCMD_FILE)
+#      $(ECHO) @ $(EGREP_CMD) > maketemp_egrep_cmd.bat
+#      ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)
+#      $(EGREP_CMD) > $(LNKCMD_FILE)
+#      $(EGREP) -iv "$(XDC_GREP_STRING)" $(XDCLNKCMD_FILE) > $(LNKCMD_FILE)
+       $(ECHO) \# Configuro done!
+
+$(LNKCMD_FILE) :
+#      $(CP) $(XDCLNKCMD_FILE) $(LNKCMD_FILE)
+#      $(ECHO) @ $(EGREP_CMD) > maketemp_egrep_cmd.bat
+#      ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)
+#      $(EGREP_CMD) > $(LNKCMD_FILE)
+ifndef MODULE_NAME
+$(OBJDIR)/$(CFG_COBJ_XDC) : $(CFG_C_XDC)
+       $(ECHO) \# Compiling generated $< to $@ ...
+       $(CC) -ppd=$(DEPFILE).P $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $(CFG_C_XDC)
+       $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $(CFG_C_XDC)
+endif
+
+# Include dependency make files that were generated by $(CC)
+-include $(SRCS:%.c=$(DEPDIR)/%.P)
+
+# Nothing beyond this point
index f0afdaf8c1fca4903d61843142e5d367328361c7..0de67aa9e0b230ed1e77771d9ccd0239f10fd06f 100755 (executable)
@@ -158,7 +158,7 @@ endif
 $(BINDIR)/$(APP_NAME)_$(CORE)_$(PROFILE_$(CORE)).$(EXEEXT) : $(OBJ_PATHS) $(LIB_PATHS) $(LNKCMD_FILE) $(OBJDIR)/$(CFG_COBJ_XDC)
        $(ECHO) \# Linking into $@
        $(ECHO) \#
-       cd $(TMPOBJDIR) && $(LNK) $(_LNKFLAGS) $(OBJ_PATHS) $(OBJDIR)/$(CFG_COBJ_XDC) $(LNKCMD_FILE) -o $@ -m $@.map $(LNK_LIBS)
+       cd $(TMPOBJDIR) && $(LNK) $(_LNKFLAGS) $(OBJ_PATHS) $(OBJDIR)/$(CFG_COBJ_XDC) -l$(LNKCMD_FILE) sample_app/linker.cmd -o $@ -m $@.map $(LNK_LIBS)
        $(ECHO) \#
        $(ECHO) \# $@ created.
        $(ECHO) \#
index eda7e8c59367a2bf99afbd3d10d9e8c6ac3db913..1e4d71854045aa6946401e349406fb796b9d8f80 100755 (executable)
@@ -14,6 +14,7 @@ var C66 = xdc.useModule('ti.targets.elf.C66');
 var C66e = xdc.useModule('ti.targets.elf.C66_big_endian');
 var Arm = xdc.useModule('ti.targets.arm.elf.Arm9');
 var cortexA8 = xdc.useModule('ti.targets.arm.elf.A8F');
+var C64T_ELF = xdc.useModule('ti.targets.elf.C64T');
 var M3 = xdc.useModule('ti.targets.arm.elf.M3');
 
 /* compiler paths for the CCS4.0                   */
@@ -25,6 +26,7 @@ C64P.rootDir = cgtools;
 C64Pe.rootDir = cgtools;
 C674.rootDir = cgtools;
 C64P_ELF.rootDir = cgtools_elf;
+C64T_ELF.rootDir = cgtools_elf;
 C64Pe_ELF.rootDir = cgtools_elf;
 C674_ELF.rootDir = cgtools_elf;
 C66.rootDir = cgtools_elf;
@@ -40,6 +42,7 @@ C64P.ccOpts.suffix += " -mi10 -mo ";
 C64Pe.ccOpts.suffix += " -mi10 -mo -me ";
 C674.ccOpts.suffix += " -mi10 -mo ";
 C64P_ELF.ccOpts.suffix += " -mi10 -mo ";
+C64T_ELF.ccOpts.suffix += " -mi10 -mo ";
 C64Pe_ELF.ccOpts.suffix += " -mi10 -mo -me ";
 C674_ELF.ccOpts.suffix += " -mi10 -mo ";
 C66.ccOpts.suffix += " -mi10 -mo ";
@@ -69,6 +72,9 @@ C64P_ELF.platforms = [
                      "ti.platforms.evm6472",
                      "ti.platforms.evmTCI6486",
                  ];
+C64T_ELF.platforms = [
+                     "ti.platforms.sdp4430",
+                 ];
 C64Pe_ELF.platforms = [
                      "ti.platforms.evm6472",
                      "ti.platforms.evmTCI6486",
@@ -110,6 +116,7 @@ C64P.platform = C64P.platforms[0];
 C64Pe.platform = C64Pe.platforms[0];
 C674.platform = C674.platforms[0];
 C64P_ELF.platform = C64P_ELF.platforms[0];
+C64T_ELF.platform = C64T_ELF.platforms[0];
 C64Pe_ELF.platform = C64Pe_ELF.platforms[0];
 C674_ELF.platform = C674_ELF.platforms[0];
 C66.platform = C66.platforms[0];
@@ -120,6 +127,7 @@ M3.platform = M3.platforms[1];
 
 /* list interested targets in Build.targets array  */
 Build.targets = [
+                  C64T_ELF,
                     //C64,
                     C64P,
                     C64Pe,
index a38f87fc33e978925c9499a1511b521ceff3ebb1..4a76d144b6d674fe145d73fa89641ed53043afdb 100755 (executable)
@@ -42,8 +42,6 @@ libs: $(edma3_lld_LIBS_ALL)
 
 examples: $(edma3_lld_EXAMPLES_LIST)
 
-ti816xarm : $(ti816xarm_EXAMPLES)
-
 clean: $(CLEANALL_TARGETS)
 
 cleanall: $(CLEANALL_TARGETS) $(CLEANALL_EXAMPLES)
@@ -93,6 +91,12 @@ ifeq ($(FORMAT),ELF)
        $(ECHO) \# Making m3:release:edma3_lld_drv 
        $(MAKE) -C $($@_PATH) PLATFORM=ti816x-evm CORE=m3video PROFILE_m3video=release  
 endif
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making c64t:debug:edma3_lld_drv
+       $(MAKE) -C $($@_PATH) PLATFORM=omap4-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Making c64t:release:edma3_lld_drv
+       $(MAKE) -C $($@_PATH) PLATFORM=omap4-evm PROFILE_c6xdsp=release
+endif
 
 edma3_lld_rm: edma3_lld_rm_generic
        $(ECHO) \# Making c6472-evm:debug:edma3_lld_rm 
@@ -193,7 +197,12 @@ ifeq ($(FORMAT),ELF)
        $(ECHO) \# Making ti814x-evm:rel:edma3_lld_rm 
        $(MAKE) -C $($@_PATH) PLATFORM=ti816x-evm CORE=m3video PROFILE_m3video=release
 endif
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making omap4-evm:debug:edma3_lld_rm 
+       $(MAKE) -C $($@_PATH) PLATFORM=omap4-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Making omap4-evm:release:edma3_lld_rm 
+       $(MAKE) -C $($@_PATH) PLATFORM=omap4-evm PROFILE_c6xdsp=release
+endif 
 # Generic platform
 edma3_lld_rm_generic:
 
@@ -333,6 +342,12 @@ ifeq ($(FORMAT),ELF)
        $(ECHO) \# Making ti816x-evm:rel:edma3_lld_rm_sample 
        $(MAKE) -C $($@_PATH) PLATFORM=ti816x-evm CORE=m3vpss PROFILE_m3vpss=release
 endif
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making omap4-evm:debug:edma3_lld_rm_sample 
+       $(MAKE) -C $($@_PATH) PLATFORM=omap4-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Making omap4-evm:release:edma3_lld_rm_sample 
+       $(MAKE) -C $($@_PATH) PLATFORM=omap4-evm CORE=c6xdsp PROFILE_c6xdsp=release
+endif
 
 edma3_lld_drv_sample:
        $(ECHO) \# Making c6472-evm:debug:edma3_lld_drv_sample 
@@ -434,6 +449,12 @@ ifeq ($(FORMAT),ELF)
        $(MAKE) -C $($@_PATH) PLATFORM=ti816x-evm CORE=m3video PROFILE_m3video=debug
 
 endif
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making omap4-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $($@_PATH) PLATFORM=omap4-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Making omap4-evm:release:edma3_lld_drv_sample
+       $(MAKE) -C $($@_PATH) PLATFORM=omap4-evm CORE=c6xdsp PROFILE_c6xdsp=release
+endif
 
 #
 # Rule to build all examples
@@ -687,6 +708,10 @@ endif
 # Clean targets
 
 edma3_lld_drv_clean:
+       $(ECHO) \# Cleaning c64t:debug:edma3_lld_drv
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning c64t:release:edma3_lld_drv
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=release
        $(ECHO) \# Cleaning c64p:debug:edma3_lld_drv
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug
        $(ECHO) \# Cleaning c64p:release:edma3_lld_drv
@@ -724,6 +749,10 @@ edma3_lld_drv_clean:
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug
        $(ECHO) \# Cleaning c66:release:edma3_lld_drv
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release
+       $(ECHO) \# Cleaning c64t:debug:edma3_lld_drv
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning c64t:release:edma3_lld_drv
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=release
        $(ECHO) \# Cleaning c66:debug:edma3_lld_drv -for big_endian
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug ENDIAN=big
        $(ECHO) \# Cleaning c66:release:edma3_lld_drv -for big_endian
@@ -754,6 +783,10 @@ endif
 edma3_lld_rm_clean: edma3_lld_rm_generic_clean
        $(ECHO) \# Cleaning c6472-evm:debug:edma3_lld_rm 
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning omap4-evm:debug:edma3_lld_rm 
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning omap4-evm:debug:edma3_lld_rm 
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=release
        $(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_rm 
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=debug
        $(ECHO) \# Cleaning tci6608-sim:debug:edma3_lld_rm 
@@ -885,6 +918,10 @@ ifeq ($(FORMAT),ELF)
 endif
    
 edma3_lld_rm_sample_clean:
+       $(ECHO) \# Cleaning omap4-evm:debug:edma3_lld_rm_sample 
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning omap4-evm:debug:edma3_lld_rm_sample 
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=release
        $(ECHO) \# Cleaning c6472-evm:debug:edma3_lld_rm_sample 
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug
        $(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_rm_sample 
@@ -897,6 +934,8 @@ edma3_lld_rm_sample_clean:
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=debug
        $(ECHO) \# Cleaning c6678-evm:debug:edma3_lld_rm_sample 
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning omap4-evm:debug:edma3_lld_rm_sample 
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=debug
        $(ECHO) \# Cleaning c6472-evm:debug:edma3_lld_rm_sample -for big_endian
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug ENDIAN=big
        $(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_rm_sample -for big_endian
@@ -934,6 +973,8 @@ edma3_lld_rm_sample_clean:
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=release
        $(ECHO) \# Cleaning c6678-evm:release:edma3_lld_rm_sample 
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release
+       $(ECHO) \# Cleaning omap4-evm:release:edma3_lld_rm_sample 
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=release
        $(ECHO) \# Cleaning c6472-evm:release:edma3_lld_rm_sample -for big_endian
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=release ENDIAN=big
        $(ECHO) \# Cleaning tci6486-evm:release:edma3_lld_rm_sample -for big_endian
@@ -978,6 +1019,10 @@ ifeq ($(FORMAT),ELF)
 endif
  
 edma3_lld_drv_sample_clean:
+       $(ECHO) \# Cleaning omap4-evm:debug:edma3_lld_drv_sample 
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning omap4-evm:debug:edma3_lld_drv_sample 
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=release
        $(ECHO) \# Cleaning c6472-evm:debug:edma3_lld_drv_sample 
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug
        $(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_drv_sample 
@@ -990,6 +1035,8 @@ edma3_lld_drv_sample_clean:
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=debug
        $(ECHO) \# Cleaning c6678-evm:debug:edma3_lld_drv_sample 
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning omap4-evm:debug:edma3_lld_drv_sample 
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=debug
        $(ECHO) \# Cleaning c6472-evm:debug:edma3_lld_drv_sample -for big_endian
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug ENDIAN=big
        $(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_drv_sample -for big_endian
@@ -1026,6 +1073,8 @@ edma3_lld_drv_sample_clean:
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=release 
        $(ECHO) \# Cleaning c6678-evm:release:edma3_lld_drv_sample   
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release 
+       $(ECHO) \# Cleaning omap4-evm:release:edma3_lld_drv_sample   
+       $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omap4-evm PROFILE_c6xdsp=release 
 
        $(ECHO) \# Cleaning c6472-evm:release:edma3_lld_drv_sample -for big_endian
        $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=release ENDIAN=big
index ca74bfe56a66bbf28c3624568f102e28be1e9bc5..9844fe42472161496911be38d219195f1a8ded69 100755 (executable)
@@ -30,6 +30,7 @@ SRCS_c6670-evm   = sample_c6670_cfg.c sample_c6670_int_reg.c
 SRCS_c6678-evm   = sample_c6678_cfg.c sample_c6678_int_reg.c
 SRCS_omapl138-evm = sample_omapl138_cfg.c sample_omapl138_int_reg.c
 SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_int_reg.c
+SRCS_omap4-evm   = sample_omap4_cfg.c sample_omap4_int_reg.c
 SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_int_reg.c
 SRCS_ti816x-sim = sample_ti816x_cfg.c sample_ti816x_int_reg.c
 else
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omap4_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omap4_cfg.c
new file mode 100644 (file)
index 0000000..8b74b1f
--- /dev/null
@@ -0,0 +1,757 @@
+/*
+ * sample_omap4_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES                    1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                                       1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+       {
+#if 0
+       volatile unsigned int *addr;
+       unsigned int core_no;
+
+    /* Identify the core number */
+    addr = (unsigned int *)(CGEM_REG_START+0x40000);
+    core_no = ((*addr) & 0x000F0000)>>16;
+
+       return core_no;
+#endif
+       return 1;
+       }
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+unsigned short isGblConfigRequired(unsigned int dspNum)
+       {
+       (void) dspNum;
+
+       return 1;
+       }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET                             (128u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC                                  (64u)
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE                                (2u)
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC                                    (2u)
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT                    (29u)
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT                              (38u)
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT                             (39u)
+#define EDMA3_TC1_ERROR_INT                             (40u)
+#define EDMA3_TC2_ERROR_INT                             (0u)
+#define EDMA3_TC3_ERROR_INT                             (0u)
+#define EDMA3_TC4_ERROR_INT                             (0u)
+#define EDMA3_TC5_ERROR_INT                             (0u)
+#define EDMA3_TC6_ERROR_INT                             (0u)
+#define EDMA3_TC7_ERROR_INT                             (0u)
+
+/**
+* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+* ECM events (SoC specific). These ECM events come
+* under ECM block XXX (handling those specific ECM events). Normally, block
+* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+* is mapped to a specific HWI_INT YYY in the tcf file.
+* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+* to transfer completion interrupt.
+* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+* to CC error interrupts.
+* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+* to TC error interrupts.
+*/
+#define EDMA3_HWI_INT_XFER_COMP                                                        (9u)
+#define EDMA3_HWI_INT_CC_ERR                                                   (9u)
+#define EDMA3_HWI_INT_TC_ERR                                                   (9u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                                                                         /* 31     0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFCFFu)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x00001C1Fu)
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                                                       {
+                                                       0u, EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u,
+                                                       0u, 0u, 0u, 0u,
+                                                       },
+                        };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
+                                {
+                                EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+                                EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+                                EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+                                EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+                                }
+                            };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+
+
+/* Driver Object Initialization Configuration */
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+       {
+           {
+           /** Total number of DMA Channels supported by the EDMA3 Controller */
+           64u,
+           /** Total number of QDMA Channels supported by the EDMA3 Controller */
+           8u,
+           /** Total number of TCCs supported by the EDMA3 Controller */
+           64u,
+           /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+           128u,
+           /** Total number of Event Queues in the EDMA3 Controller */
+           2u,
+           /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+           2u,
+           /** Number of Regions on this EDMA3 controller */
+           8u,
+
+           /**
+            * \brief Channel mapping existence
+            * A value of 0 (No channel mapping) implies that there is fixed association
+            * for a channel number to a parameter entry number or, in other words,
+            * PaRAM entry n corresponds to channel n.
+            */
+           1u,
+
+           /** Existence of memory protection feature */
+           1u,
+
+           /** Global Register Region of CC Registers */
+           (void *)0x01C00000u,
+           /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x01C10000u,
+               (void *)0x01C10400u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+           /** Interrupt no. for Transfer Completion */
+           EDMA3_CC_XFER_COMPLETION_INT,
+           /** Interrupt no. for CC Error */
+           EDMA3_CC_ERROR_INT,
+           /** Interrupt no. for TCs Error */
+               {
+               EDMA3_TC0_ERROR_INT,
+               EDMA3_TC1_ERROR_INT,
+               EDMA3_TC2_ERROR_INT,
+               EDMA3_TC3_ERROR_INT,
+               EDMA3_TC4_ERROR_INT,
+               EDMA3_TC5_ERROR_INT,
+               EDMA3_TC6_ERROR_INT,
+               EDMA3_TC7_ERROR_INT
+               },
+
+           /**
+            * \brief EDMA3 TC priority setting
+            *
+            * User can program the priority of the Event Queues
+            * at a system-wide level.  This means that the user can set the
+            * priority of an IO initiated by either of the TCs (Transfer Controllers)
+            * relative to IO initiated by the other bus masters on the
+            * device (ARM, DSP, USB, etc)
+            */
+               {
+               0u,
+               1u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+           /**
+            * \brief To Configure the Threshold level of number of events
+            * that can be queued up in the Event queues. EDMA3CC error register
+            * (CCERR) will indicate whether or not at any instant of time the
+            * number of events queued up in any of the event queues exceeds
+            * or equals the threshold/watermark value that is set
+            * in the queue watermark threshold register (QWMTHRA).
+            */
+               {
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+           /**
+            * \brief To Configure the Default Burst Size (DBS) of TCs.
+            * An optimally-sized command is defined by the transfer controller
+            * default burst size (DBS). Different TCs can have different
+            * DBS values. It is defined in Bytes.
+            */
+               {
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+           /**
+            * \brief Mapping from each DMA channel to a Parameter RAM set,
+            * if it exists, otherwise of no use.
+            */
+               {
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+               40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+               56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+               },
+
+            /**
+             * \brief Mapping from each DMA channel to a TCC. This specific
+             * TCC code will be returned when the transfer is completed
+             * on the mapped channel.
+             */
+               {
+               0u, 1u, 2u, 3u,
+               4u, 5u, 6u, 7u,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 10u, 11u,
+               12u, 13u, 14u, 15u,
+               16u, 17u, 18u, 19u,
+               20u, 21u, 22u, 23u,
+               24u, 25u, 26u, 27u,
+               28u, 29u, 30u, 31u,
+               32u, 33u, 34u, 35u,
+               36u, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, 42u, 43u,
+               44u, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+               },
+
+           /**
+            * \brief Mapping of DMA channels to Hardware Events from
+            * various peripherals, which use EDMA for data transfer.
+            * All channels need not be mapped, some can be free also.
+            */
+               {
+               EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+               EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
+               },
+               },
+       };
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+       {
+               /* EDMA3 INSTANCE# 0 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                   {
+                       /* ownPaRAMSets */
+                       /* 31     0     63    32     95    64     127   96 */
+                       {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                       /* 159  128     191  160     223  192     255  224 */
+                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       /* 287  256     319  288     351  320     383  352 */
+                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       /* 415  384     447  416     479  448     511  480 */
+                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                       /* ownDmaChannels */
+                       /* 31     0     63    32 */
+                       {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                       /* ownQdmaChannels */
+                       /* 31     0 */
+                       {0x000000FFu},
+
+                       /* ownTccs */
+                       /* 31     0     63    32 */
+                       {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                       /* resvdPaRAMSets */
+                       /* 31     0     63    32     95    64     127   96 */
+                       {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                       /* 159  128     191  160     223  192     255  224 */
+                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       /* 287  256     319  288     351  320     383  352 */
+                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       /* 415  384     447  416     479  448     511  480 */
+                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                       /* resvdDmaChannels */
+                       /* 31                                                       0 */
+                       {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+                       /* 63                                                     32 */
+                           EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+
+                       /* resvdQdmaChannels */
+                       /* 31     0 */
+                       {0x00000000u},
+
+                       /* resvdTccs */
+                       /* 31                                                       0 */
+                       {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+                       /* 63                                                     32 */
+                           EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1}
+                   },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+           },
+       };
+
+
+
+/* End of File */
+
+
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omap4_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omap4_int_reg.c
new file mode 100644 (file)
index 0000000..523acd5
--- /dev/null
@@ -0,0 +1,153 @@
+/*
+ * sample_da830_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+// #include <stdio.h>
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp;
+extern unsigned int hwIntCcErr;
+extern unsigned int hwIntTcErr;
+
+extern unsigned int dsp_num;
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Enable the Xfer Completion Event Interrupt */
+    EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
+                               NULL, 1);
+    EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Enable the CC Error Event Interrupt */
+    EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
+                                               NULL, 1);
+    EventCombiner_enableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
+                            (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
+                            NULL, 1);
+        EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+       Hwi_enableInterrupt(hwIntXferComp);
+       Hwi_enableInterrupt(hwIntCcErr);
+       Hwi_enableInterrupt(hwIntTcErr);
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Disable the Xfer Completion Event Interrupt */
+       EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Disable the CC Error Event Interrupt */
+       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+       {
+        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
index af8732055589eca94eae91f2d222568293ce5d10..b048c3e7a2d74d6e8ec9a9e85dd6d6c70d214290 100644 (file)
@@ -26,6 +26,7 @@ SRCS_c6678-evm = edma3_c6678_cfg.c
 SRCS_omapl138-evm = edma3_omapl138_cfg.c
 SRCS_c6748-evm = edma3_c6748_cfg.c
 SRCS_da830-evm = edma3_da830_cfg.c
+SRCS_omap4-evm = edma3_omap4_cfg.c
 SRCS_ti814x-evm = edma3_ti814x_cfg.c
 SRCS_ti816x-evm = edma3_ti816x_cfg.c
 SRCS_ti816x-sim = edma3_ti816x_cfg.c
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_omap4_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_omap4_cfg.c
new file mode 100644 (file)
index 0000000..def5af1
--- /dev/null
@@ -0,0 +1,510 @@
+/*
+ * edma3_omap4_cfg.c
+ *
+ * EDMA3 Resource Manager Adaptation Configuration File (SoC Specific).
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+#define NUM_EDMA3_INSTANCES                    1u
+
+/** Total number of DMA Channels supported by the EDMA3 Controller */
+#define NUM_DMA_CHANNELS                        (64u)
+/** Total number of QDMA Channels supported by the EDMA3 Controller */
+#define NUM_QDMA_CHANNELS                       (8u)
+/** Total number of TCCs supported by the EDMA3 Controller */
+#define NUM_TCC                                 (64u)
+/** Total number of PaRAM Sets supported by the EDMA3 Controller */
+#define NUM_PARAM_SETS                          (128u)
+/** Total number of Event Queues in the EDMA3 Controller */
+#define NUM_EVENT_QUEUE                         (2u)
+/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+#define NUM_TC                                  (2u)
+/** Number of Regions on this EDMA3 controller */
+#define NUM_REGION                              (8u)
+
+/**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+#define CHANNEL_MAPPING_EXISTENCE               (1u)
+/** Existence of memory protection feature */
+#define MEM_PROTECTION_EXISTENCE                (1u)
+
+/** Global Register Region of CC Registers */
+#define CC_BASE_ADDRESS                         (0x01C00000u)
+/** Transfer Controller 0 Registers */
+#define TC0_BASE_ADDRESS                        (0x01C10000u)
+/** Transfer Controller 1 Registers */
+#define TC1_BASE_ADDRESS                        (0x01C10400u)
+/** Transfer Controller 2 Registers */
+#define TC2_BASE_ADDRESS                        NULL
+/** Transfer Controller 3 Registers */
+#define TC3_BASE_ADDRESS                        NULL
+/** Transfer Controller 4 Registers */
+#define TC4_BASE_ADDRESS                        NULL
+/** Transfer Controller 5 Registers */
+#define TC5_BASE_ADDRESS                        NULL
+/** Transfer Controller 6 Registers */
+#define TC6_BASE_ADDRESS                        NULL
+/** Transfer Controller 7 Registers */
+#define TC7_BASE_ADDRESS                        NULL
+
+/** Interrupt no. for Transfer Completion */
+#define XFER_COMPLETION_INT                     (29u)
+/** Interrupt no. for CC Error */
+#define CC_ERROR_INT                            (38u)
+/** Interrupt no. for TC 0 Error */
+#define TC0_ERROR_INT                           (39u)
+/** Interrupt no. for TC 1 Error */
+#define TC1_ERROR_INT                           (40u)
+/** Interrupt no. for TC 2 Error */
+#define TC2_ERROR_INT                           (0u)
+/** Interrupt no. for TC 3 Error */
+#define TC3_ERROR_INT                           (0u)
+/** Interrupt no. for TC 4 Error */
+#define TC4_ERROR_INT                           (0u)
+/** Interrupt no. for TC 5 Error */
+#define TC5_ERROR_INT                           (0u)
+/** Interrupt no. for TC 6 Error */
+#define TC6_ERROR_INT                           (0u)
+/** Interrupt no. for TC 7 Error */
+#define TC7_ERROR_INT                           (0u)
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                                                               /* 31     0 */
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFCFFu)
+
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in DA830. */
+#define DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x00001C1Fu)
+
+
+EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
+{
+    {
+    /** Total number of DMA Channels supported by the EDMA3 Controller */
+    NUM_DMA_CHANNELS,
+    /** Total number of QDMA Channels supported by the EDMA3 Controller */
+    NUM_QDMA_CHANNELS,
+    /** Total number of TCCs supported by the EDMA3 Controller */
+    NUM_TCC,
+    /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+    NUM_PARAM_SETS,
+    /** Total number of Event Queues in the EDMA3 Controller */
+    NUM_EVENT_QUEUE,
+    /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+    NUM_TC,
+    /** Number of Regions on this EDMA3 controller */
+    NUM_REGION,
+
+    /**
+     * \brief Channel mapping existence
+     * A value of 0 (No channel mapping) implies that there is fixed association
+     * for a channel number to a parameter entry number or, in other words,
+     * PaRAM entry n corresponds to channel n.
+     */
+    CHANNEL_MAPPING_EXISTENCE,
+
+    /** Existence of memory protection feature */
+    MEM_PROTECTION_EXISTENCE,
+
+    /** Global Register Region of CC Registers */
+    (void *)(CC_BASE_ADDRESS),
+    /** Transfer Controller (TC) Registers */
+        {
+        (void *)(TC0_BASE_ADDRESS),
+        (void *)(TC1_BASE_ADDRESS),
+        (void *)(TC2_BASE_ADDRESS),
+        (void *)(TC3_BASE_ADDRESS),
+        (void *)(TC4_BASE_ADDRESS),
+        (void *)(TC5_BASE_ADDRESS),
+        (void *)(TC6_BASE_ADDRESS),
+        (void *)(TC7_BASE_ADDRESS)
+        },
+    /** Interrupt no. for Transfer Completion */
+    XFER_COMPLETION_INT,
+    /** Interrupt no. for CC Error */
+    CC_ERROR_INT,
+    /** Interrupt no. for TCs Error */
+        {
+        TC0_ERROR_INT,
+        TC1_ERROR_INT,
+        TC2_ERROR_INT,
+        TC3_ERROR_INT,
+        TC4_ERROR_INT,
+        TC5_ERROR_INT,
+        TC6_ERROR_INT,
+        TC7_ERROR_INT
+        },
+
+   /**
+     * \brief EDMA3 TC priority setting
+     *
+     * User can program the priority of the Event Queues
+     * at a system-wide level.  This means that the user can set the
+     * priority of an IO initiated by either of the TCs (Transfer Controllers)
+     * relative to IO initiated by the other bus masters on the
+     * device (ARM, DSP, USB, etc)
+     */
+        {
+        0u,
+        1u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+    /**
+     * \brief To Configure the Threshold level of number of events
+     * that can be queued up in the Event queues. EDMA3CC error register
+     * (CCERR) will indicate whether or not at any instant of time the
+     * number of events queued up in any of the event queues exceeds
+     * or equals the threshold/watermark value that is set
+     * in the queue watermark threshold register (QWMTHRA).
+     */
+        {
+        16u,
+        16u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+
+    /**
+     * \brief To Configure the Default Burst Size (DBS) of TCs.
+     * An optimally-sized command is defined by the transfer controller
+     * default burst size (DBS). Different TCs can have different
+     * DBS values. It is defined in Bytes.
+     */
+        {
+        16u,
+        16u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+
+    /**
+     * \brief Mapping from each DMA channel to a Parameter RAM set,
+     * if it exists, otherwise of no use.
+     */
+        {
+        0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+        16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+        32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+        40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+        48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+        56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+        },
+
+     /**
+      * \brief Mapping from each DMA channel to a TCC. This specific
+      * TCC code will be returned when the transfer is completed
+      * on the mapped channel.
+      */
+        {
+        0u, 1u, 2u, 3u,
+        4u, 5u, 6u, 7u,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 10u, 11u,
+        12u, 13u, 14u, 15u,
+        16u, 17u, 18u, 19u,
+        20u, 21u, 22u, 23u,
+        24u, 25u, 26u, 27u,
+        28u, 29u, 30u, 31u,
+        32u, 33u, 34u, 35u,
+        36u, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, 42u, 43u,
+        44u, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+        },
+
+    /**
+     * \brief Mapping of DMA channels to Hardware Events from
+     * various peripherals, which use EDMA for data transfer.
+     * All channels need not be mapped, some can be free also.
+     */
+        {
+        DMA_CHANNEL_TO_EVENT_MAPPING_0,
+        DMA_CHANNEL_TO_EVENT_MAPPING_1
+        }
+    }
+};
+
+
+/* Default RM Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][NUM_REGION] =
+{
+        {
+          {
+            /* Resources owned by Region 0 */
+             /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* Resources reserved by Region 0 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+          },
+
+          {
+            /* Resources owned by Region 1 */
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31                                        0  63                                                  32 */
+            {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31                                        0  63                                                  32 */
+            {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
+          },
+
+          {
+            /* Resources owned by Region 2 */
+             /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* Resources reserved by Region 2 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+          },
+
+          {
+            /* Resources owned by Region 3 */
+             /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* Resources reserved by Region 3 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+          }
+        }
+};
+
+/* End of File */
+
+
+