summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 6c800b8)
raw | patch | inline | side by side (parent: 6c800b8)
author | Raghu Nambiath <rnambiath@ti.com> | |
Mon, 14 Feb 2011 11:15:05 +0000 (16:45 +0530) | ||
committer | Sundaram Raju <sundaram@ti.com> | |
Mon, 14 Feb 2011 11:18:20 +0000 (16:48 +0530) |
- Also removed the old Ny simulator TCI6498
Signed-off-by: Sundaram Raju <sundaram@ti.com>
Signed-off-by: Sundaram Raju <sundaram@ti.com>
158 files changed:
diff --git a/examples/edma3_driver/evm6670/makefile b/examples/edma3_driver/evm6670/makefile
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_6670_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_c6670_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+ dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \
+ qdma_link_test.c
+CFLAGS_LOCAL_COMMON =
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evm6670/rtsc_config/.ccsproject b/examples/edma3_driver/evm6670/rtsc_config/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<deviceEndianness value="little"/>
+<codegenToolVersion value="6.1.12"/>
+<linkerCommandFile value=""/>
+<rts value="rts64plus.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evm6670/rtsc_config/.cdtbuild b/examples/edma3_driver/evm6670/rtsc_config/.cdtbuild
--- /dev/null
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_c6670_st_sample_configuration.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.342693649" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Release.943131545" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.549809610" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.1152394885">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1606377512" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.12" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.521386405" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="IS_ELF=false"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.2"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.16.03.36"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.02.19;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.1152394885" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH.553340492" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR.1478255202" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET.1015906177" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET" value="ti.targets.C64P" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM.880875036" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM" value="ti.platforms.evm6670" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR.488350228" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.848397052" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.803481204">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1678396723" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.12" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1863597223" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="IS_ELF=false"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.2"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.16.03.36"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.02.19;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.803481204" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH.2036408717" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR.400881455" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET.1602580966" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET" value="ti.targets.C64P" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM.1480175884" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM" value="ti.platforms.evm6670" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE.28640752" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE" value="debug" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR.533294420" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/simTCI6498/rtsc_config/.cdtproject b/examples/edma3_driver/evm6670/rtsc_config/.cdtproject
similarity index 100%
rename from examples/edma3_driver/simTCI6498/rtsc_config/.cdtproject
rename to examples/edma3_driver/evm6670/rtsc_config/.cdtproject
rename from examples/edma3_driver/simTCI6498/rtsc_config/.cdtproject
rename to examples/edma3_driver/evm6670/rtsc_config/.cdtproject
diff --git a/examples/edma3_driver/simTCI6498/rtsc_config/.project b/examples/edma3_driver/evm6670/rtsc_config/.project
similarity index 91%
rename from examples/edma3_driver/simTCI6498/rtsc_config/.project
rename to examples/edma3_driver/evm6670/rtsc_config/.project
index b97728852c842e01cfc142fbb92ad4bb3a9c6e09..7ceb6ae83a1f22442047be69f99e9a178ac3cdcb 100644 (file)
rename from examples/edma3_driver/simTCI6498/rtsc_config/.project
rename to examples/edma3_driver/evm6670/rtsc_config/.project
index b97728852c842e01cfc142fbb92ad4bb3a9c6e09..7ceb6ae83a1f22442047be69f99e9a178ac3cdcb 100644 (file)
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
- <name>edma3_drv_bios6_tci6498_st_sample_configuration</name>
+ <name>edma3_drv_bios6_c6472_st_sample_configuration</name>
<comment></comment>
<projects>
<project>ti.sdo.edma3.drv</project>
diff --git a/examples/edma3_driver/simTCI6498/rtsc_config/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evm6670/rtsc_config/.settings/org.eclipse.cdt.core.prefs
similarity index 100%
rename from examples/edma3_driver/simTCI6498/rtsc_config/.settings/org.eclipse.cdt.core.prefs
rename to examples/edma3_driver/evm6670/rtsc_config/.settings/org.eclipse.cdt.core.prefs
rename from examples/edma3_driver/simTCI6498/rtsc_config/.settings/org.eclipse.cdt.core.prefs
rename to examples/edma3_driver/evm6670/rtsc_config/.settings/org.eclipse.cdt.core.prefs
diff --git a/examples/edma3_driver/simTCI6498/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evm6670/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
old mode 100755 (executable)
new mode 100644 (file)
similarity index 98%
rename from examples/edma3_driver/simTCI6498/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
rename to examples/edma3_driver/evm6670/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
index 18fb15f..f62df2b
new mode 100644 (file)
similarity index 98%
rename from examples/edma3_driver/simTCI6498/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
rename to examples/edma3_driver/evm6670/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
index 18fb15f..f62df2b
--- a/examples/edma3_driver/simTCI6498/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
-#Sat Sep 12 13:39:19 IST 2009\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.329256125/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.329256125/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.348160522/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.348160522/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.766962715/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.766962715/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.880090332/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.880090332/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.1052936504/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.1052936504/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.1689121304/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.1689121304/internalBuilder/ignoreErr=true\r
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-com.ti.ccstudio.buildDefinitions.C6000.Release.1771625523/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.1914376102/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.1914376102/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.2093499111/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.2093499111/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.943131545/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.943131545/internalBuilder/ignoreErr=true\r
-eclipse.preferences.version=1\r
-environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
-environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
-environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
-environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.943131545=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
+#Sat Sep 12 13:39:19 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.329256125/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.329256125/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.348160522/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.348160522/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.766962715/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.766962715/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.880090332/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.880090332/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1052936504/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1052936504/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1689121304/internalBuilder/enabled=false
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+com.ti.ccstudio.buildDefinitions.C6000.Release.1914376102/internalBuilder/ignoreErr=true
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diff --git a/examples/edma3_driver/simTCI6498/rtsc_config/edma3_drv_bios6_tci6498_st_sample.cfg b/examples/edma3_driver/evm6670/rtsc_config/edma3_drv_bios6_c6670_st_sample.cfg
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from examples/edma3_driver/simTCI6498/rtsc_config/edma3_drv_bios6_tci6498_st_sample.cfg
rename to examples/edma3_driver/evm6670/rtsc_config/edma3_drv_bios6_c6670_st_sample.cfg
new mode 100644 (file)
similarity index 100%
rename from examples/edma3_driver/simTCI6498/rtsc_config/edma3_drv_bios6_tci6498_st_sample.cfg
rename to examples/edma3_driver/evm6670/rtsc_config/edma3_drv_bios6_c6670_st_sample.cfg
diff --git a/examples/edma3_driver/evm6670/sample_app/.ccsproject b/examples/edma3_driver/evm6670/sample_app/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value=""/>
+<deviceEndianness value="little"/>
+<codegenToolVersion value="6.1.12"/>
+<linkerCommandFile value=""/>
+<rts value="rts64plus.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evm6670/sample_app/.cdtbuild b/examples/edma3_driver/evm6670/sample_app/.cdtbuild
--- /dev/null
@@ -0,0 +1,92 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
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diff --git a/examples/edma3_driver/simTCI6498/sample_app/.cdtproject b/examples/edma3_driver/evm6670/sample_app/.cdtproject
similarity index 100%
rename from examples/edma3_driver/simTCI6498/sample_app/.cdtproject
rename to examples/edma3_driver/evm6670/sample_app/.cdtproject
rename from examples/edma3_driver/simTCI6498/sample_app/.cdtproject
rename to examples/edma3_driver/evm6670/sample_app/.cdtproject
diff --git a/examples/edma3_driver/evm6670/sample_app/.project b/examples/edma3_driver/evm6670/sample_app/.project
--- /dev/null
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_c6670_st_sample</name>
+ <comment></comment>
+ <projects>
+ <project>edma3_drv_bios6_c6670_st_sample_configuration</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>dma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_poll_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>
+ </link>
+ <link>
+ <name>main.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>
+ </link>
+ <link>
+ <name>dma_misc_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_ping_pong_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>common.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>
+ </link>
+ <link>
+ <name>dma_chain_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/examples/edma3_driver/simTCI6498/sample_app/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evm6670/sample_app/.settings/org.eclipse.cdt.core.prefs
similarity index 100%
rename from examples/edma3_driver/simTCI6498/sample_app/.settings/org.eclipse.cdt.core.prefs
rename to examples/edma3_driver/evm6670/sample_app/.settings/org.eclipse.cdt.core.prefs
rename from examples/edma3_driver/simTCI6498/sample_app/.settings/org.eclipse.cdt.core.prefs
rename to examples/edma3_driver/evm6670/sample_app/.settings/org.eclipse.cdt.core.prefs
diff --git a/examples/edma3_driver/simTCI6498/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evm6670/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
old mode 100755 (executable)
new mode 100644 (file)
similarity index 98%
rename from examples/edma3_driver/simTCI6498/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
rename to examples/edma3_driver/evm6670/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
index 1d93939..486ccc0
new mode 100644 (file)
similarity index 98%
rename from examples/edma3_driver/simTCI6498/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
rename to examples/edma3_driver/evm6670/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
index 1d93939..486ccc0
--- a/examples/edma3_driver/simTCI6498/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
-#Mon Sep 07 22:07:14 IST 2009\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.1503849319/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.1503849319/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.610287652/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.610287652/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.763317674/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Debug.763317674/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.1542466517/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.1542466517/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.319340500/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.319340500/internalBuilder/ignoreErr=true\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.396130192/internalBuilder/enabled=false\r
-com.ti.ccstudio.buildDefinitions.C6000.Release.396130192/internalBuilder/ignoreErr=true\r
-eclipse.preferences.version=1\r
-environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
-environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
-environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
+#Mon Sep 07 22:07:14 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823/internalBuilder/ignoreErr=true
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+com.ti.ccstudio.buildDefinitions.C6000.Debug.610287652/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.610287652/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.763317674/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.763317674/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1542466517/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1542466517/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.319340500/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.319340500/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.396130192/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.396130192/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/evm6670/sample_app/linker.cmd b/examples/edma3_driver/evm6670/sample_app/linker.cmd
--- /dev/null
@@ -0,0 +1,6 @@
+
+SECTIONS
+{
+ .my_sect_iram > L2SRAM
+ .my_sect_ddr > L2SRAM
+}
similarity index 90%
rename from examples/edma3_driver/simTCI6498/makefile
rename to examples/edma3_driver/evm6670BE/makefile
index 5dda19e92fd60b50200e492f306aa4c07f884136..5715f1532ac45470e0ed8a39b533bf2cc89f1bef 100644 (file)
rename from examples/edma3_driver/simTCI6498/makefile
rename to examples/edma3_driver/evm6670BE/makefile
index 5dda19e92fd60b50200e492f306aa4c07f884136..5715f1532ac45470e0ed8a39b533bf2cc89f1bef 100644 (file)
# Makefile for edma3 lld app
-APP_NAME = edma3_drv_tci6498_sample
+APP_NAME = edma3_drv_c6670be_sample
SRCDIR = ../src
INCDIR = ../src
COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
# XDC CFG File
-XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tci6498_st_sample.cfg
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_c6670be_st_sample.cfg
# Common source files and CFLAGS across all platforms and cores
SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
diff --git a/examples/edma3_driver/evm6670BE/rtsc_config/.ccsproject b/examples/edma3_driver/evm6670BE/rtsc_config/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<deviceEndianness value="big"/>
+<codegenToolVersion value="6.1.12"/>
+<linkerCommandFile value=""/>
+<rts value="rts64pluse.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evm6670BE/rtsc_config/.cdtbuild b/examples/edma3_driver/evm6670BE/rtsc_config/.cdtbuild
--- /dev/null
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_c6670be_st_sample_configuration.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.637606372" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
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+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.859743144" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
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+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>
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+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64pluse.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.2"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.16.03.36"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.02.19;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.1949682123" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH.1665487776" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages/""/>
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+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR.812396436" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
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+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Default">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.1374505078" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.9432576">
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diff --git a/examples/edma3_driver/simTCI6498BE/rtsc_config/.cdtproject b/examples/edma3_driver/evm6670BE/rtsc_config/.cdtproject
similarity index 100%
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.cdtproject
rename to examples/edma3_driver/evm6670BE/rtsc_config/.cdtproject
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.cdtproject
rename to examples/edma3_driver/evm6670BE/rtsc_config/.cdtproject
diff --git a/examples/edma3_driver/simTCI6498BE/rtsc_config/.project b/examples/edma3_driver/evm6670BE/rtsc_config/.project
similarity index 91%
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.project
rename to examples/edma3_driver/evm6670BE/rtsc_config/.project
index f8df7178019bf2460c5acbff0c272d716cfbd40c..28ba8d7bee13012bab8d133874ff9a155ec0718a 100644 (file)
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.project
rename to examples/edma3_driver/evm6670BE/rtsc_config/.project
index f8df7178019bf2460c5acbff0c272d716cfbd40c..28ba8d7bee13012bab8d133874ff9a155ec0718a 100644 (file)
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
- <name>edma3_drv_bios6_tci6498be_st_sample_configuration</name>
+ <name>edma3_drv_bios6_c6670be_st_sample_configuration</name>
<comment></comment>
<projects>
<project>ti.sdo.edma3.drv</project>
diff --git a/examples/edma3_driver/simTCI6498BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evm6670BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs
similarity index 100%
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs
rename to examples/edma3_driver/evm6670BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs
rename to examples/edma3_driver/evm6670BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs
diff --git a/examples/edma3_driver/simTCI6498BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evm6670BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
old mode 100755 (executable)
new mode 100644 (file)
similarity index 98%
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
rename to examples/edma3_driver/evm6670BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
index 3c93481..88c958c
new mode 100644 (file)
similarity index 98%
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
rename to examples/edma3_driver/evm6670BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
index 3c93481..88c958c
--- a/examples/edma3_driver/simTCI6498BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
+++ b/examples/edma3_driver/evm6670BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
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-environment/project/com.ti.ccstudio.buildDefinitions.C6000.Default.818303754=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
+#Fri Sep 11 22:09:00 IST 2009
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+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
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diff --git a/examples/edma3_driver/simTCI6498BE/rtsc_config/edma3_drv_bios6_tci6498be_st_sample.cfg b/examples/edma3_driver/evm6670BE/rtsc_config/edma3_drv_bios6_c6670be_st_sample.cfg
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/edma3_drv_bios6_tci6498be_st_sample.cfg
rename to examples/edma3_driver/evm6670BE/rtsc_config/edma3_drv_bios6_c6670be_st_sample.cfg
new mode 100644 (file)
similarity index 100%
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/edma3_drv_bios6_tci6498be_st_sample.cfg
rename to examples/edma3_driver/evm6670BE/rtsc_config/edma3_drv_bios6_c6670be_st_sample.cfg
diff --git a/examples/edma3_driver/evm6670BE/sample_app/.ccsproject b/examples/edma3_driver/evm6670BE/sample_app/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
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+<rts value="rts64pluse.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evm6670BE/sample_app/.cdtbuild b/examples/edma3_driver/evm6670BE/sample_app/.cdtbuild
--- /dev/null
@@ -0,0 +1,91 @@
+<?xml version="1.0" encoding="UTF-8"?>
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diff --git a/examples/edma3_driver/simTCI6498BE/sample_app/.cdtproject b/examples/edma3_driver/evm6670BE/sample_app/.cdtproject
similarity index 100%
rename from examples/edma3_driver/simTCI6498BE/sample_app/.cdtproject
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rename to examples/edma3_driver/evm6670BE/sample_app/.cdtproject
diff --git a/examples/edma3_driver/simTCI6498/sample_app/.project b/examples/edma3_driver/evm6670BE/sample_app/.project
old mode 100755 (executable)
new mode 100644 (file)
similarity index 92%
rename from examples/edma3_driver/simTCI6498/sample_app/.project
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index 0e1234b..3af4173
new mode 100644 (file)
similarity index 92%
rename from examples/edma3_driver/simTCI6498/sample_app/.project
rename to examples/edma3_driver/evm6670BE/sample_app/.project
index 0e1234b..3af4173
-<?xml version="1.0" encoding="UTF-8"?>\r
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- </link>\r
- <link>\r
- <name>dma_poll_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>main.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>\r
- </link>\r
- <link>\r
- <name>dma_misc_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>dma_link_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>qdma_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>dma_ping_pong_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>qdma_link_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>common.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>\r
- </link>\r
- <link>\r
- <name>dma_chain_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>\r
- </link>\r
- </linkedResources>\r
-</projectDescription>\r
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_c6670be_st_sample</name>
+ <comment></comment>
+ <projects>
+ <project>edma3_drv_bios6_c6670be_st_sample_configuration</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>dma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_poll_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>
+ </link>
+ <link>
+ <name>main.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_misc_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_ping_pong_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>common.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>
+ </link>
+ <link>
+ <name>dma_chain_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/examples/edma3_driver/simTCI6498BE/sample_app/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evm6670BE/sample_app/.settings/org.eclipse.cdt.core.prefs
similarity index 100%
rename from examples/edma3_driver/simTCI6498BE/sample_app/.settings/org.eclipse.cdt.core.prefs
rename to examples/edma3_driver/evm6670BE/sample_app/.settings/org.eclipse.cdt.core.prefs
rename from examples/edma3_driver/simTCI6498BE/sample_app/.settings/org.eclipse.cdt.core.prefs
rename to examples/edma3_driver/evm6670BE/sample_app/.settings/org.eclipse.cdt.core.prefs
diff --git a/examples/edma3_driver/evm6670BE/sample_app/linker.cmd b/examples/edma3_driver/evm6670BE/sample_app/linker.cmd
--- /dev/null
@@ -0,0 +1,6 @@
+
+SECTIONS
+{
+ .my_sect_iram > L2SRAM
+ .my_sect_ddr > L2SRAM
+}
diff --git a/examples/edma3_driver/evm6678/makefile b/examples/edma3_driver/evm6678/makefile
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_6678_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_c6678_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+ dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \
+ qdma_link_test.c
+CFLAGS_LOCAL_COMMON =
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evm6678/rtsc_config/.ccsproject b/examples/edma3_driver/evm6678/rtsc_config/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<deviceEndianness value="little"/>
+<codegenToolVersion value="6.1.12"/>
+<linkerCommandFile value=""/>
+<rts value="rts64plus.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evm6678/rtsc_config/.cdtbuild b/examples/edma3_driver/evm6678/rtsc_config/.cdtbuild
--- /dev/null
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_c6678_st_sample_configuration.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.342693649" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Release.943131545" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.549809610" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.1152394885">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1606377512" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.12" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.521386405" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="IS_ELF=false"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.2"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.16.03.36"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.02.19;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.1152394885" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH.553340492" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR.1478255202" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET.1015906177" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET" value="ti.targets.C64P" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM.880875036" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM" value="ti.platforms.evm6678" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR.488350228" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.848397052" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.803481204">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1678396723" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.12" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1863597223" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="IS_ELF=false"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.2"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.16.03.36"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.02.19;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.803481204" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH.2036408717" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR.400881455" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET.1602580966" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET" value="ti.targets.C64P" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM.1480175884" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM" value="ti.platforms.evm6678" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE.28640752" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE" value="debug" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR.533294420" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/evm6678/rtsc_config/.cdtproject b/examples/edma3_driver/evm6678/rtsc_config/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.rtsc.xdctools.buildDefinitions.XDC.XDCROOT_CONTAINER"/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/evm6678/rtsc_config/.project b/examples/edma3_driver/evm6678/rtsc_config/.project
--- /dev/null
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_c6472_st_sample_configuration</name>
+ <comment></comment>
+ <projects>
+ <project>ti.sdo.edma3.drv</project>
+ <project>ti.sdo.edma3.drv.sample</project>
+ <project>ti.sdo.edma3.rm</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature</nature>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ </natures>
+</projectDescription>
diff --git a/examples/edma3_driver/evm6678/rtsc_config/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evm6678/rtsc_config/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Wed Jul 15 12:11:28 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.domsourceindexer
diff --git a/examples/edma3_driver/evm6678/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evm6678/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
@@ -0,0 +1,30 @@
+#Sat Sep 12 13:39:19 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.329256125/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.329256125/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.348160522/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.348160522/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.766962715/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.766962715/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.880090332/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.880090332/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1052936504/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1052936504/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1689121304/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1689121304/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1771625523/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1771625523/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1914376102/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1914376102/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.2093499111/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.2093499111/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.943131545/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.943131545/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.943131545=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/evm6678/rtsc_config/edma3_drv_bios6_c6678_st_sample.cfg b/examples/edma3_driver/evm6678/rtsc_config/edma3_drv_bios6_c6678_st_sample.cfg
--- /dev/null
@@ -0,0 +1,20 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Log = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
diff --git a/examples/edma3_driver/evm6678/sample_app/.ccsproject b/examples/edma3_driver/evm6678/sample_app/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value=""/>
+<deviceEndianness value="little"/>
+<codegenToolVersion value="6.1.12"/>
+<linkerCommandFile value=""/>
+<rts value="rts64plus.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evm6678/sample_app/.cdtbuild b/examples/edma3_driver/evm6678/sample_app/.cdtbuild
--- /dev/null
@@ -0,0 +1,92 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
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+<configuration artifactExtension="out" artifactName="edma3_drv_bios6_c6678_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
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+<listOptionValue builtIn="false" value="225"/>
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+<listOptionValue builtIn="false" value=""libc.a""/>
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+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.generatedLinkerCommandFiles.1412540746" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.generatedLinkerCommandFiles" valueType="libs">
+<listOptionValue builtIn="false" value=""$(GEN_CMDS_QUOTED)""/>
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+</tool>
+<macros expandEnvironmentMacros="true"/>
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+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/evm6678/sample_app/.cdtproject b/examples/edma3_driver/evm6678/sample_app/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/evm6678/sample_app/.project b/examples/edma3_driver/evm6678/sample_app/.project
--- /dev/null
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_c6678_st_sample</name>
+ <comment></comment>
+ <projects>
+ <project>edma3_drv_bios6_c6678_st_sample_configuration</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>dma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_poll_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>
+ </link>
+ <link>
+ <name>main.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>
+ </link>
+ <link>
+ <name>dma_misc_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_ping_pong_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>common.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>
+ </link>
+ <link>
+ <name>dma_chain_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/examples/edma3_driver/evm6678/sample_app/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evm6678/sample_app/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Thu Jul 30 16:08:39 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/evm6678/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evm6678/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
@@ -0,0 +1,21 @@
+#Mon Sep 07 22:07:14 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1503849319/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1503849319/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.610287652/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.610287652/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.763317674/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.763317674/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1542466517/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1542466517/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.319340500/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.319340500/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.396130192/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.396130192/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/evm6678/sample_app/linker.cmd b/examples/edma3_driver/evm6678/sample_app/linker.cmd
--- /dev/null
@@ -0,0 +1,6 @@
+
+SECTIONS
+{
+ .my_sect_iram > L2SRAM
+ .my_sect_ddr > L2SRAM
+}
diff --git a/examples/edma3_driver/evm6678BE/makefile b/examples/edma3_driver/evm6678BE/makefile
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_c6678be_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_c6678be_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+ dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \
+ qdma_link_test.c
+CFLAGS_LOCAL_COMMON =
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evm6678BE/rtsc_config/.ccsproject b/examples/edma3_driver/evm6678BE/rtsc_config/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<deviceEndianness value="big"/>
+<codegenToolVersion value="6.1.12"/>
+<linkerCommandFile value=""/>
+<rts value="rts64pluse.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evm6678BE/rtsc_config/.cdtbuild b/examples/edma3_driver/evm6678BE/rtsc_config/.cdtbuild
--- /dev/null
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
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+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>
+<listOptionValue builtIn="false" value="IS_ELF=false"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64pluse.lib"/>
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+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.2"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.16.03.36"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.02.19;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.1949682123" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
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+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages/""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR.812396436" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
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+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Default">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.1374505078" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.9432576">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1661896610" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.12" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.278956118" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>
+<listOptionValue builtIn="false" value="IS_ELF=false"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64pluse.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.2"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.16.03.36"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.02.19;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.9432576" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH.26484299" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR.529317250" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET.417294690" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET" value="ti.targets.C64P_big_endian" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM.1233666595" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM" value="ti.platforms.evm6678" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR.1706261699" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/evm6678BE/rtsc_config/.cdtproject b/examples/edma3_driver/evm6678BE/rtsc_config/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.rtsc.xdctools.buildDefinitions.XDC.XDCROOT_CONTAINER"/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/evm6678BE/rtsc_config/.project b/examples/edma3_driver/evm6678BE/rtsc_config/.project
--- /dev/null
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_c6678be_st_sample_configuration</name>
+ <comment></comment>
+ <projects>
+ <project>ti.sdo.edma3.drv</project>
+ <project>ti.sdo.edma3.drv.sample</project>
+ <project>ti.sdo.edma3.rm</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature</nature>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ </natures>
+</projectDescription>
diff --git a/examples/edma3_driver/evm6678BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evm6678BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Mon Aug 03 19:13:16 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/evm6678BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evm6678BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/evm6678BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,21 @@
+#Fri Sep 11 22:09:00 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.1944506020/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1944506020/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.2023113450/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.2023113450/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.2087575148/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.2087575148/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.512050187/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.512050187/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.778469771/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.778469771/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.818303754/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.818303754/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.867093800/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.867093800/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Default.818303754=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/evm6678BE/rtsc_config/edma3_drv_bios6_c6678be_st_sample.cfg b/examples/edma3_driver/evm6678BE/rtsc_config/edma3_drv_bios6_c6678be_st_sample.cfg
--- /dev/null
@@ -0,0 +1,20 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Log = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
diff --git a/examples/edma3_driver/evm6678BE/sample_app/.ccsproject b/examples/edma3_driver/evm6678BE/sample_app/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<deviceEndianness value="big"/>
+<codegenToolVersion value="6.1.12"/>
+<linkerCommandFile value=""/>
+<rts value="rts64pluse.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evm6678BE/sample_app/.cdtbuild b/examples/edma3_driver/evm6678BE/sample_app/.cdtbuild
--- /dev/null
@@ -0,0 +1,91 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_c6678be_st_sample.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.540132789" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="out" artifactName="edma3_drv_bios6_c6678be_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.1819584752" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug.958867513">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1688412677" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.12" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1624944058" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>
+<listOptionValue builtIn="false" value="IS_ELF=false"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.2"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerDebug.1177337365" name="C6000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION.700584684" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION" value="64+" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH.644792901" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING.1978224774" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING" valueType="stringList">
+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.BIG_ENDIAN.1593824405" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.BIG_ENDIAN" value="true" valueType="boolean"/>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug.958867513" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE.1688473989" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE" value=""edma3_drv_bios6_c6678be_st_sample.out"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE.1919047637" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE" value=""edma3_drv_bios6_c6678be_st_sample.map"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH.1384159534" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY.1572998235" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value=""libc.a""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.generatedLinkerCommandFiles.944788862" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.generatedLinkerCommandFiles" valueType="libs">
+<listOptionValue builtIn="false" value=""$(GEN_CMDS_QUOTED)""/>
+</option>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="out" artifactName="edma3_drv_bios6_c6678be_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.1217479267" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2070518307">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.408423457" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.12" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.750079244" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>
+<listOptionValue builtIn="false" value="IS_ELF=false"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.1.2"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerRelease.1943723681" name="C6000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION.1482261186" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION" value="64+" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH.746446765" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING.1992467490" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING" valueType="stringList">
+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.BIG_ENDIAN.775024288" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.BIG_ENDIAN" value="true" valueType="boolean"/>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2070518307" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE.1940677293" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE" value=""edma3_drv_bios6_c6678be_st_sample.out"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE.51856197" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE" value=""edma3_drv_bios6_c6678be_st_sample.map"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH.490436039" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY.1580442076" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value=""libc.a""/>
+</option>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/evm6678BE/sample_app/.cdtproject b/examples/edma3_driver/evm6678BE/sample_app/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/evm6678BE/sample_app/.project b/examples/edma3_driver/evm6678BE/sample_app/.project
--- /dev/null
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_c6678be_st_sample</name>
+ <comment></comment>
+ <projects>
+ <project>edma3_drv_bios6_c6678be_st_sample_configuration</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>dma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_poll_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>
+ </link>
+ <link>
+ <name>main.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_misc_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_ping_pong_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>common.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>
+ </link>
+ <link>
+ <name>dma_chain_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/examples/edma3_driver/evm6678BE/sample_app/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evm6678BE/sample_app/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Mon Aug 03 19:13:16 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/evm6678BE/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evm6678BE/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/evm6678BE/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,9 @@
+#Fri Aug 14 19:45:21 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/evm6678BE/sample_app/linker.cmd b/examples/edma3_driver/evm6678BE/sample_app/linker.cmd
--- /dev/null
@@ -0,0 +1,6 @@
+
+SECTIONS
+{
+ .my_sect_iram > L2SRAM
+ .my_sect_ddr > L2SRAM
+}
diff --git a/examples/edma3_driver/simTCI6498/sample_app/linker.cmd b/examples/edma3_driver/simTCI6498/sample_app/linker.cmd
+++ /dev/null
@@ -1,13 +0,0 @@
-MEMORY
-{
- GEM0_L2MEM: o=0x10880000, l=40000h
- GEM1_L2MEM: o=0x11880000, l=40000h
- GEM2_L2MEM: o=0x12880000, l=40000h
- GEM3_L2MEM: o=0x13880000, l=40000h
-}
-
-SECTIONS
-{
- .my_sect_iram > GEM0_L2MEM
- .my_sect_ddr > GEM0_L2MEM
-}
diff --git a/examples/edma3_driver/simTCI6498BE/sample_app/linker.cmd b/examples/edma3_driver/simTCI6498BE/sample_app/linker.cmd
+++ /dev/null
@@ -1,13 +0,0 @@
-MEMORY
-{
- GEM0_L2MEM: o=0x10880000, l=40000h
- GEM1_L2MEM: o=0x11880000, l=40000h
- GEM2_L2MEM: o=0x12880000, l=40000h
- GEM3_L2MEM: o=0x13880000, l=40000h
-}
-
-SECTIONS
-{
- .my_sect_iram > GEM0_L2MEM
- .my_sect_ddr > GEM0_L2MEM
-}
diff --git a/examples/edma3_driver/simTCI6608/makefile b/examples/edma3_driver/simTCI6608/makefile
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_tci6608_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tci6608_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+ dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \
+ qdma_link_test.c
+CFLAGS_LOCAL_COMMON =
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/simTCI6498/rtsc_config/.ccsproject b/examples/edma3_driver/simTCI6608/rtsc_config/.ccsproject
old mode 100755 (executable)
new mode 100644 (file)
similarity index 96%
rename from examples/edma3_driver/simTCI6498/rtsc_config/.ccsproject
rename to examples/edma3_driver/simTCI6608/rtsc_config/.ccsproject
index 01c2d04..1b6a74c
new mode 100644 (file)
similarity index 96%
rename from examples/edma3_driver/simTCI6498/rtsc_config/.ccsproject
rename to examples/edma3_driver/simTCI6608/rtsc_config/.ccsproject
index 01c2d04..1b6a74c
-<?xml version="1.0" encoding="UTF-8"?>\r
-<?ccsproject version="1.0"?>\r
-\r
-<projectOptions>\r
-<deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>\r
-<deviceEndianness value="little"/>\r
-<codegenToolVersion value="6.1.10"/>\r
-<linkerCommandFile value=""/>\r
-<rts value="rts64plus.lib"/>\r
-<defaultAssemblyOnly value="false"/>\r
-</projectOptions>\r
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<deviceEndianness value="little"/>
+<codegenToolVersion value="6.1.10"/>
+<linkerCommandFile value=""/>
+<rts value="rts64plus.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/simTCI6498/rtsc_config/.cdtbuild b/examples/edma3_driver/simTCI6608/rtsc_config/.cdtbuild
old mode 100755 (executable)
new mode 100644 (file)
similarity index 96%
rename from examples/edma3_driver/simTCI6498/rtsc_config/.cdtbuild
rename to examples/edma3_driver/simTCI6608/rtsc_config/.cdtbuild
index c563206..22a2ba6
new mode 100644 (file)
similarity index 96%
rename from examples/edma3_driver/simTCI6498/rtsc_config/.cdtbuild
rename to examples/edma3_driver/simTCI6608/rtsc_config/.cdtbuild
index c563206..22a2ba6
-<?xml version="1.0" encoding="UTF-8"?>\r
-<?fileVersion 3.1.0?>\r
-\r
-<ManagedProjectBuildInfo>\r
-<project id="edma3_drv_bios6_tci6498_st_sample_configuration.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.342693649" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">\r
-<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Release.943131545" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">\r
-<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.1563963858" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1134204148">\r
-<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1154018327" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.11" valueType="string"/>\r
-<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1883300211" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">\r
-<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC67xPlusDevice"/>\r
-<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>\r
-<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>\r
-<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>\r
-<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>\r
-<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>\r
-<listOptionValue builtIn="false" value="XDC_VERSION=3.15.02.62"/>\r
-<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>\r
-<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>\r
-</option>\r
-<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1134204148" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.1770670681" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">\r
-<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>\r
-<listOptionValue builtIn="false" value=""../../../../../packages""/>\r
-</option>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.1246521365" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.837994107" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.1571201647" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.simTCI6498" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.1365815017" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>\r
-</tool>\r
-<macros expandEnvironmentMacros="true"/>\r
-</toolChain>\r
-</configuration>\r
-<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">\r
-<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.890447493" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1970878876">\r
-<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.366366805" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.11" valueType="string"/>\r
-<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.699258970" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">\r
-<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>\r
-<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>\r
-<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>\r
-<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>\r
-<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>\r
-<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>\r
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-<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>\r
-<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>\r
-</option>\r
-<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1970878876" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.1202211094" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">\r
-<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>\r
-<listOptionValue builtIn="false" value=""../../../../../packages""/>\r
-</option>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.325184681" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.1214798586" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.973623826" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.simTCI6498" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE.223734638" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE" value="debug" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.1984079746" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>\r
-</tool>\r
-<macros/>\r
-</toolChain>\r
-</configuration>\r
-<macros/>\r
-</project>\r
-</ManagedProjectBuildInfo>\r
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_tci6608_st_sample_configuration.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.342693649" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Release.943131545" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">
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+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
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+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1134204148" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.1770670681" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.1246521365" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
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+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
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+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1970878876" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">
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+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/simTCI6608/rtsc_config/.cdtproject b/examples/edma3_driver/simTCI6608/rtsc_config/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.rtsc.xdctools.buildDefinitions.XDC.XDCROOT_CONTAINER"/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/simTCI6608/rtsc_config/.project b/examples/edma3_driver/simTCI6608/rtsc_config/.project
--- /dev/null
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_tci6608_st_sample_configuration</name>
+ <comment></comment>
+ <projects>
+ <project>ti.sdo.edma3.drv</project>
+ <project>ti.sdo.edma3.drv.sample</project>
+ <project>ti.sdo.edma3.rm</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature</nature>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ </natures>
+</projectDescription>
diff --git a/examples/edma3_driver/simTCI6608/rtsc_config/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/simTCI6608/rtsc_config/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Wed Jul 15 12:11:28 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.domsourceindexer
diff --git a/examples/edma3_driver/simTCI6608/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/simTCI6608/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/simTCI6608/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,30 @@
+#Sat Sep 12 13:39:19 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.329256125/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.329256125/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.348160522/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.348160522/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.766962715/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.766962715/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.880090332/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.880090332/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1052936504/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1052936504/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1689121304/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1689121304/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1771625523/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1771625523/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1914376102/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1914376102/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.2093499111/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.2093499111/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.943131545/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.943131545/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.943131545=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/simTCI6608/rtsc_config/edma3_drv_bios6_tci6608_st_sample.cfg b/examples/edma3_driver/simTCI6608/rtsc_config/edma3_drv_bios6_tci6608_st_sample.cfg
--- /dev/null
@@ -0,0 +1,20 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Log = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
diff --git a/examples/edma3_driver/simTCI6498/sample_app/.ccsproject b/examples/edma3_driver/simTCI6608/sample_app/.ccsproject
similarity index 100%
rename from examples/edma3_driver/simTCI6498/sample_app/.ccsproject
rename to examples/edma3_driver/simTCI6608/sample_app/.ccsproject
rename from examples/edma3_driver/simTCI6498/sample_app/.ccsproject
rename to examples/edma3_driver/simTCI6608/sample_app/.ccsproject
diff --git a/examples/edma3_driver/simTCI6498/sample_app/.cdtbuild b/examples/edma3_driver/simTCI6608/sample_app/.cdtbuild
old mode 100755 (executable)
new mode 100644 (file)
similarity index 91%
rename from examples/edma3_driver/simTCI6498/sample_app/.cdtbuild
rename to examples/edma3_driver/simTCI6608/sample_app/.cdtbuild
index 271620d..f896c3b
new mode 100644 (file)
similarity index 91%
rename from examples/edma3_driver/simTCI6498/sample_app/.cdtbuild
rename to examples/edma3_driver/simTCI6608/sample_app/.cdtbuild
index 271620d..f896c3b
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+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.409541288" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2086845964">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1716500704" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.10" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1179762671" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+<listOptionValue builtIn="false" value="DEPENDENCIES=edma3_drv_bios6_tci6608_st_sample_configuration:Release;"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerRelease.970508825" name="C6000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION.592066712" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION" value="64+" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH.383955403" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING.623946889" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING" valueType="stringList">
+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE.343769706" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE" valueType="stringList">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6608_st_sample_configuration/Release/configPkg/compiler.opt}""/>
+</option>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2086845964" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE.500257992" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE" value=""edma3_drv_bios6_tci6608_st_sample.out"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE.1657894292" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE" value=""edma3_drv_bios6_tci6608_st_sample.map"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY.452265586" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6608_st_sample_configuration/Release/configPkg/linker.cmd}""/>
+<listOptionValue builtIn="false" value=""rts64plus.lib""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH.217717418" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/simTCI6608/sample_app/.cdtproject b/examples/edma3_driver/simTCI6608/sample_app/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/simTCI6608/sample_app/.project b/examples/edma3_driver/simTCI6608/sample_app/.project
--- /dev/null
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_tci6608_st_sample</name>
+ <comment></comment>
+ <projects>
+ <project>edma3_drv_bios6_tci6608_st_sample_configuration</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>dma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_poll_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>
+ </link>
+ <link>
+ <name>main.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>
+ </link>
+ <link>
+ <name>dma_misc_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_ping_pong_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>common.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>
+ </link>
+ <link>
+ <name>dma_chain_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/examples/edma3_driver/simTCI6608/sample_app/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/simTCI6608/sample_app/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Thu Jul 30 16:08:39 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/simTCI6608/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/simTCI6608/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/simTCI6608/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,21 @@
+#Mon Sep 07 22:07:14 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1503849319/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1503849319/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.610287652/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.610287652/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.763317674/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.763317674/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1542466517/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1542466517/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.319340500/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.319340500/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.396130192/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.396130192/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/simTCI6608/sample_app/linker.cmd b/examples/edma3_driver/simTCI6608/sample_app/linker.cmd
--- /dev/null
@@ -0,0 +1,6 @@
+
+SECTIONS
+{
+ .my_sect_iram > L2SRAM
+ .my_sect_ddr > L2SRAM
+}
diff --git a/examples/edma3_driver/simTCI6498BE/makefile b/examples/edma3_driver/simTCI6608BE/makefile
similarity index 90%
rename from examples/edma3_driver/simTCI6498BE/makefile
rename to examples/edma3_driver/simTCI6608BE/makefile
index bfdb676c3cfd48bb76ef4ebf1991c48173d4da62..5784d6546c4db9a89573f0374db8336b89f6adfd 100644 (file)
rename from examples/edma3_driver/simTCI6498BE/makefile
rename to examples/edma3_driver/simTCI6608BE/makefile
index bfdb676c3cfd48bb76ef4ebf1991c48173d4da62..5784d6546c4db9a89573f0374db8336b89f6adfd 100644 (file)
# Makefile for edma3 lld app
-APP_NAME = edma3_drv_tci6498be_sample
+APP_NAME = edma3_drv_tci6608be_sample
SRCDIR = ../src
INCDIR = ../src
COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
# XDC CFG File
-XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tci6498be_st_sample.cfg
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tci6608be_st_sample.cfg
# Common source files and CFLAGS across all platforms and cores
SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
diff --git a/examples/edma3_driver/simTCI6498BE/rtsc_config/.ccsproject b/examples/edma3_driver/simTCI6608BE/rtsc_config/.ccsproject
similarity index 100%
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.ccsproject
rename to examples/edma3_driver/simTCI6608BE/rtsc_config/.ccsproject
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.ccsproject
rename to examples/edma3_driver/simTCI6608BE/rtsc_config/.ccsproject
diff --git a/examples/edma3_driver/simTCI6498BE/rtsc_config/.cdtbuild b/examples/edma3_driver/simTCI6608BE/rtsc_config/.cdtbuild
old mode 100755 (executable)
new mode 100644 (file)
similarity index 96%
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.cdtbuild
rename to examples/edma3_driver/simTCI6608BE/rtsc_config/.cdtbuild
index 769e5d5..85a25f0
new mode 100644 (file)
similarity index 96%
rename from examples/edma3_driver/simTCI6498BE/rtsc_config/.cdtbuild
rename to examples/edma3_driver/simTCI6608BE/rtsc_config/.cdtbuild
index 769e5d5..85a25f0
-<?xml version="1.0" encoding="UTF-8"?>\r
-<?fileVersion 3.1.0?>\r
-\r
-<ManagedProjectBuildInfo>\r
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-<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Default.818303754" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Default">\r
-<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.2010627901" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.767241745">\r
-<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.912257569" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.11" valueType="string"/>\r
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-<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>\r
-<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>\r
-<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>\r
-<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64pluse.lib"/>\r
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-<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>\r
-</option>\r
-<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.767241745" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.1128948338" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">\r
-<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>\r
-<listOptionValue builtIn="false" value=""../../../../../packages/""/>\r
-</option>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.1652754745" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.1267879973" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P_big_endian" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.1641911520" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.simTCI6498" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE.1037670294" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE" value="debug" valueType="string"/>\r
-<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.1265722300" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>\r
-</tool>\r
-<macros/>\r
-</toolChain>\r
-</configuration>\r
-<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Default">\r
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-<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.185181509" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">\r
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-</tool>\r
-<macros expandEnvironmentMacros="true"/>\r
-</toolChain>\r
-</configuration>\r
-<macros/>\r
-</project>\r
-</ManagedProjectBuildInfo>\r
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_tci6608be_st_sample_configuration.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.637606372" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Default.818303754" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Default">
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+<listOptionValue builtIn="false" value="XDC_VERSION=3.15.02.62"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.767241745" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.1128948338" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages/""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.1652754745" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.1267879973" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P_big_endian" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.1641911520" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.simTCI6608" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE.1037670294" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE" value="debug" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.1265722300" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Default">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.557257468" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1801068721">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1453482417" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.11" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.185181509" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64pluse.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.15.02.62"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1801068721" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.597983079" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.2125256667" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.61311076" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P_big_endian" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.538887117" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.simTCI6608" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.684138018" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/simTCI6608BE/rtsc_config/.cdtproject b/examples/edma3_driver/simTCI6608BE/rtsc_config/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.rtsc.xdctools.buildDefinitions.XDC.XDCROOT_CONTAINER"/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/simTCI6608BE/rtsc_config/.project b/examples/edma3_driver/simTCI6608BE/rtsc_config/.project
--- /dev/null
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_tci6608be_st_sample_configuration</name>
+ <comment></comment>
+ <projects>
+ <project>ti.sdo.edma3.drv</project>
+ <project>ti.sdo.edma3.drv.sample</project>
+ <project>ti.sdo.edma3.rm</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature</nature>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ </natures>
+</projectDescription>
diff --git a/examples/edma3_driver/simTCI6608BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/simTCI6608BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Mon Aug 03 19:13:16 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/simTCI6608BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/simTCI6608BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/simTCI6608BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,21 @@
+#Fri Sep 11 22:09:00 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.1944506020/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1944506020/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.2023113450/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.2023113450/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.2087575148/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.2087575148/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.512050187/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.512050187/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.778469771/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.778469771/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.818303754/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.818303754/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.867093800/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.867093800/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Default.818303754=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/simTCI6608BE/rtsc_config/edma3_drv_bios6_tci6608be_st_sample.cfg b/examples/edma3_driver/simTCI6608BE/rtsc_config/edma3_drv_bios6_tci6608be_st_sample.cfg
--- /dev/null
@@ -0,0 +1,20 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Log = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
diff --git a/examples/edma3_driver/simTCI6498BE/sample_app/.ccsproject b/examples/edma3_driver/simTCI6608BE/sample_app/.ccsproject
similarity index 100%
rename from examples/edma3_driver/simTCI6498BE/sample_app/.ccsproject
rename to examples/edma3_driver/simTCI6608BE/sample_app/.ccsproject
rename from examples/edma3_driver/simTCI6498BE/sample_app/.ccsproject
rename to examples/edma3_driver/simTCI6608BE/sample_app/.ccsproject
diff --git a/examples/edma3_driver/simTCI6498BE/sample_app/.cdtbuild b/examples/edma3_driver/simTCI6608BE/sample_app/.cdtbuild
old mode 100755 (executable)
new mode 100644 (file)
similarity index 91%
rename from examples/edma3_driver/simTCI6498BE/sample_app/.cdtbuild
rename to examples/edma3_driver/simTCI6608BE/sample_app/.cdtbuild
index 88bfed7..2295194
new mode 100644 (file)
similarity index 91%
rename from examples/edma3_driver/simTCI6498BE/sample_app/.cdtbuild
rename to examples/edma3_driver/simTCI6608BE/sample_app/.cdtbuild
index 88bfed7..2295194
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+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="out" artifactName="edma3_drv_bios6_tci6608be_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.1334202182" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2077986563">
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+<listOptionValue builtIn="false" value="225"/>
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+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE.1710409320" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE" valueType="stringList">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6608be_st_sample_configuration/Release/configPkg/compiler.opt}""/>
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+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DEFINE.1893019243" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DEFINE" valueType="definedSymbols"/>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2077986563" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE.710504412" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE" value=""edma3_drv_bios6_tci6608be_st_sample.out"" valueType="string"/>
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+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6608be_st_sample_configuration/Release/configPkg/linker.cmd}""/>
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+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH.1215685616" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH" valueType="stringList">
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+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/simTCI6608BE/sample_app/.cdtproject b/examples/edma3_driver/simTCI6608BE/sample_app/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/simTCI6498BE/sample_app/.project b/examples/edma3_driver/simTCI6608BE/sample_app/.project
old mode 100755 (executable)
new mode 100644 (file)
similarity index 92%
rename from examples/edma3_driver/simTCI6498BE/sample_app/.project
rename to examples/edma3_driver/simTCI6608BE/sample_app/.project
index 8a4cd4e..e56e6aa
new mode 100644 (file)
similarity index 92%
rename from examples/edma3_driver/simTCI6498BE/sample_app/.project
rename to examples/edma3_driver/simTCI6608BE/sample_app/.project
index 8a4cd4e..e56e6aa
-<?xml version="1.0" encoding="UTF-8"?>\r
-<projectDescription>\r
- <name>edma3_drv_bios6_tci6498be_st_sample</name>\r
- <comment></comment>\r
- <projects>\r
- <project>edma3_drv_bios6_tci6498be_st_sample_configuration</project>\r
- </projects>\r
- <buildSpec>\r
- <buildCommand>\r
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
- <arguments>\r
- </arguments>\r
- </buildCommand>\r
- </buildSpec>\r
- <natures>\r
- <nature>org.eclipse.cdt.core.cnature</nature>\r
- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
- <nature>org.eclipse.cdt.core.ccnature</nature>\r
- </natures>\r
- <linkedResources>\r
- <link>\r
- <name>dma_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>dma_poll_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>main.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>\r
- </link>\r
- <link>\r
- <name>qdma_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>dma_link_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>dma_misc_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>dma_ping_pong_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>qdma_link_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>\r
- </link>\r
- <link>\r
- <name>common.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>\r
- </link>\r
- <link>\r
- <name>dma_chain_test.c</name>\r
- <type>1</type>\r
- <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>\r
- </link>\r
- </linkedResources>\r
-</projectDescription>\r
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_tci6608be_st_sample</name>
+ <comment></comment>
+ <projects>
+ <project>edma3_drv_bios6_tci6608be_st_sample_configuration</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>dma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_poll_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>
+ </link>
+ <link>
+ <name>main.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_misc_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_ping_pong_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>common.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>
+ </link>
+ <link>
+ <name>dma_chain_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/examples/edma3_driver/simTCI6608BE/sample_app/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/simTCI6608BE/sample_app/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Mon Aug 03 19:13:16 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/simTCI6608BE/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/simTCI6608BE/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/simTCI6608BE/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,9 @@
+#Fri Aug 14 19:45:21 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/simTCI6608BE/sample_app/linker.cmd b/examples/edma3_driver/simTCI6608BE/sample_app/linker.cmd
--- /dev/null
@@ -0,0 +1,6 @@
+
+SECTIONS
+{
+ .my_sect_iram > L2SRAM
+ .my_sect_ddr > L2SRAM
+}
diff --git a/examples/edma3_driver/simTCI6616/makefile b/examples/edma3_driver/simTCI6616/makefile
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_tci6616_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tci6616_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+ dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \
+ qdma_link_test.c
+CFLAGS_LOCAL_COMMON =
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/simTCI6616/rtsc_config/.ccsproject b/examples/edma3_driver/simTCI6616/rtsc_config/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<deviceEndianness value="little"/>
+<codegenToolVersion value="6.1.10"/>
+<linkerCommandFile value=""/>
+<rts value="rts64plus.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/simTCI6616/rtsc_config/.cdtbuild b/examples/edma3_driver/simTCI6616/rtsc_config/.cdtbuild
--- /dev/null
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_tci6616_st_sample_configuration.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.342693649" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Release.943131545" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.1563963858" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1134204148">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1154018327" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.11" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1883300211" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC67xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.15.02.62"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1134204148" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.1770670681" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.1246521365" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.837994107" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.1571201647" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.simTCI6616" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.1365815017" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.890447493" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1970878876">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.366366805" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.11" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.699258970" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.15.02.62"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1970878876" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.1202211094" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.325184681" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.1214798586" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.973623826" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.simTCI6616" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE.223734638" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE" value="debug" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.1984079746" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/simTCI6616/rtsc_config/.cdtproject b/examples/edma3_driver/simTCI6616/rtsc_config/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.rtsc.xdctools.buildDefinitions.XDC.XDCROOT_CONTAINER"/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/simTCI6616/rtsc_config/.project b/examples/edma3_driver/simTCI6616/rtsc_config/.project
--- /dev/null
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_tci6616_st_sample_configuration</name>
+ <comment></comment>
+ <projects>
+ <project>ti.sdo.edma3.drv</project>
+ <project>ti.sdo.edma3.drv.sample</project>
+ <project>ti.sdo.edma3.rm</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature</nature>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ </natures>
+</projectDescription>
diff --git a/examples/edma3_driver/simTCI6616/rtsc_config/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/simTCI6616/rtsc_config/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Wed Jul 15 12:11:28 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.domsourceindexer
diff --git a/examples/edma3_driver/simTCI6616/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/simTCI6616/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/simTCI6616/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,30 @@
+#Sat Sep 12 13:39:19 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.329256125/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.329256125/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.348160522/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.348160522/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.766962715/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.766962715/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.880090332/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.880090332/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1052936504/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1052936504/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1689121304/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1689121304/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1771625523/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1771625523/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1914376102/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1914376102/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.2093499111/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.2093499111/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.943131545/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.943131545/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.113456611=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.943131545=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/simTCI6616/rtsc_config/edma3_drv_bios6_tci6616_st_sample.cfg b/examples/edma3_driver/simTCI6616/rtsc_config/edma3_drv_bios6_tci6616_st_sample.cfg
--- /dev/null
@@ -0,0 +1,20 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Log = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
diff --git a/examples/edma3_driver/simTCI6616/sample_app/.ccsproject b/examples/edma3_driver/simTCI6616/sample_app/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value=""/>
+<deviceEndianness value="little"/>
+<codegenToolVersion value="6.1.10"/>
+<linkerCommandFile value=""/>
+<rts value="rts64plus.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/simTCI6616/sample_app/.cdtbuild b/examples/edma3_driver/simTCI6616/sample_app/.cdtbuild
--- /dev/null
@@ -0,0 +1,94 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_tci6616_st_sample.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.2056179817" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="out" artifactName="edma3_drv_bios6_tci6616_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.1095429107" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug.1009459640">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.689753528" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.10" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1272193492" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+<listOptionValue builtIn="false" value="DEPENDENCIES=edma3_drv_bios6_tci6616_st_sample_configuration:Debug;"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerDebug.82874858" name="C6000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerDebug">
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+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
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+<listOptionValue builtIn="false" value="225"/>
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+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE.1133990629" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE" valueType="stringList">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6616_st_sample_configuration/Debug/configPkg/compiler.opt}""/>
+</option>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug.1009459640" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE.554395848" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE" value=""edma3_drv_bios6_tci6616_st_sample.out"" valueType="string"/>
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+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY.1901031176" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6616_st_sample_configuration/Debug/configPkg/linker.cmd}""/>
+<listOptionValue builtIn="false" value=""rts64plus.lib""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH.1195541588" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/lib""/>
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+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="out" artifactName="edma3_drv_bios6_tci6616_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.409541288" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2086845964">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1716500704" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.10" valueType="string"/>
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+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE.343769706" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE" valueType="stringList">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6616_st_sample_configuration/Release/configPkg/compiler.opt}""/>
+</option>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2086845964" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE.500257992" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE" value=""edma3_drv_bios6_tci6616_st_sample.out"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE.1657894292" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE" value=""edma3_drv_bios6_tci6616_st_sample.map"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY.452265586" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6616_st_sample_configuration/Release/configPkg/linker.cmd}""/>
+<listOptionValue builtIn="false" value=""rts64plus.lib""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH.217717418" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/simTCI6616/sample_app/.cdtproject b/examples/edma3_driver/simTCI6616/sample_app/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/simTCI6616/sample_app/.project b/examples/edma3_driver/simTCI6616/sample_app/.project
--- /dev/null
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_tci6616_st_sample</name>
+ <comment></comment>
+ <projects>
+ <project>edma3_drv_bios6_tci6616_st_sample_configuration</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>dma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_poll_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>
+ </link>
+ <link>
+ <name>main.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>
+ </link>
+ <link>
+ <name>dma_misc_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_ping_pong_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>common.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>
+ </link>
+ <link>
+ <name>dma_chain_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/examples/edma3_driver/simTCI6616/sample_app/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/simTCI6616/sample_app/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Thu Jul 30 16:08:39 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/simTCI6616/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/simTCI6616/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/simTCI6616/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,21 @@
+#Mon Sep 07 22:07:14 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1503849319/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1503849319/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.610287652/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.610287652/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Debug.763317674/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.763317674/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1542466517/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1542466517/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.319340500/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.319340500/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.396130192/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.396130192/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/simTCI6616/sample_app/linker.cmd b/examples/edma3_driver/simTCI6616/sample_app/linker.cmd
--- /dev/null
@@ -0,0 +1,6 @@
+
+SECTIONS
+{
+ .my_sect_iram > L2SRAM
+ .my_sect_ddr > L2SRAM
+}
diff --git a/examples/edma3_driver/simTCI6616BE/makefile b/examples/edma3_driver/simTCI6616BE/makefile
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_tci6616be_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tci6616be_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+ dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \
+ qdma_link_test.c
+CFLAGS_LOCAL_COMMON =
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/simTCI6616BE/rtsc_config/.ccsproject b/examples/edma3_driver/simTCI6616BE/rtsc_config/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<deviceEndianness value="big"/>
+<codegenToolVersion value="6.1.10"/>
+<linkerCommandFile value=""/>
+<rts value="rts64pluse.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/simTCI6616BE/rtsc_config/.cdtbuild b/examples/edma3_driver/simTCI6616BE/rtsc_config/.cdtbuild
--- /dev/null
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_tci6616be_st_sample_configuration.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.637606372" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Default.818303754" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Default">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.2010627901" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.767241745">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.912257569" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.11" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1532518256" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64pluse.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.15.02.62"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.767241745" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.1128948338" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages/""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.1652754745" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.1267879973" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P_big_endian" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.1641911520" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.simTCI6616" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE.1037670294" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE" value="debug" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.1265722300" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Default">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.557257468" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1801068721">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1453482417" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.11" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.185181509" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64pluse.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.15.02.62"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1801068721" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.597983079" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${BIOS_CG_ROOT}/packages""/>
+<listOptionValue builtIn="false" value=""../../../../../packages""/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.2125256667" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value=""configPkg"" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.61311076" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P_big_endian" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.538887117" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.simTCI6616" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.684138018" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value=""${CG_TOOL_ROOT}"" valueType="string"/>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/simTCI6616BE/rtsc_config/.cdtproject b/examples/edma3_driver/simTCI6616BE/rtsc_config/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.rtsc.xdctools.buildDefinitions.XDC.XDCROOT_CONTAINER"/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/simTCI6616BE/rtsc_config/.project b/examples/edma3_driver/simTCI6616BE/rtsc_config/.project
--- /dev/null
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_tci6616be_st_sample_configuration</name>
+ <comment></comment>
+ <projects>
+ <project>ti.sdo.edma3.drv</project>
+ <project>ti.sdo.edma3.drv.sample</project>
+ <project>ti.sdo.edma3.rm</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature</nature>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ </natures>
+</projectDescription>
diff --git a/examples/edma3_driver/simTCI6616BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/simTCI6616BE/rtsc_config/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Mon Aug 03 19:13:16 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/simTCI6616BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/simTCI6616BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/simTCI6616BE/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,21 @@
+#Fri Sep 11 22:09:00 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.1944506020/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.1944506020/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.2023113450/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.2023113450/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.2087575148/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.2087575148/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.512050187/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.512050187/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.778469771/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.778469771/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.818303754/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.818303754/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Default.867093800/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Default.867093800/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Default.1180814983=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Default.818303754=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/simTCI6616BE/rtsc_config/edma3_drv_bios6_tci6616be_st_sample.cfg b/examples/edma3_driver/simTCI6616BE/rtsc_config/edma3_drv_bios6_tci6616be_st_sample.cfg
--- /dev/null
@@ -0,0 +1,20 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Log = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
diff --git a/examples/edma3_driver/simTCI6616BE/sample_app/.ccsproject b/examples/edma3_driver/simTCI6616BE/sample_app/.ccsproject
--- /dev/null
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?ccsproject version="1.0"?>
+
+<projectOptions>
+<deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<deviceEndianness value="big"/>
+<codegenToolVersion value="6.1.10"/>
+<linkerCommandFile value=""/>
+<rts value="rts64pluse.lib"/>
+<defaultAssemblyOnly value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/simTCI6616BE/sample_app/.cdtbuild b/examples/edma3_driver/simTCI6616BE/sample_app/.cdtbuild
--- /dev/null
@@ -0,0 +1,98 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_tci6616be_st_sample.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.540132789" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="out" artifactName="edma3_drv_bios6_tci6616be_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.382436713" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug.956648193">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1546733629" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.10" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.408510960" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64pluse.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+<listOptionValue builtIn="false" value="DEPENDENCIES=edma3_drv_bios6_tci6616be_st_sample_configuration:$;"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerDebug.1827433791" name="C6000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.BIG_ENDIAN.1076834631" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.BIG_ENDIAN" value="true" valueType="boolean"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING.1042849327" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING" valueType="stringList">
+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION.1616765720" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION" value="64+" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH.1870746375" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE.1987300183" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE" valueType="stringList">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6616be_st_sample_configuration/Debug/configPkg/compiler.opt}""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DEFINE.71389094" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DEFINE" valueType="definedSymbols"/>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug.956648193" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE.223278000" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE" value=""edma3_drv_bios6_tci6616be_st_sample.out"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE.510068372" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE" value=""edma3_drv_bios6_tci6616be_st_sample.map"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY.1189184312" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6616be_st_sample_configuration/Debug/configPkg/linker.cmd}""/>
+<listOptionValue builtIn="false" value=""rts64pluse.lib""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH.721287581" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="out" artifactName="edma3_drv_bios6_tci6616be_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.1334202182" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2077986563">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.163120684" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.10" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1037237972" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=big"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64pluse.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+<listOptionValue builtIn="false" value="DEPENDENCIES=edma3_drv_bios6_tci6616be_st_sample_configuration:$;"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerRelease.725899542" name="C6000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.BIG_ENDIAN.1470720491" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.BIG_ENDIAN" value="true" valueType="boolean"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING.1579112283" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING" valueType="stringList">
+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION.1836032039" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION" value="64+" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH.1103146682" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE.1710409320" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE" valueType="stringList">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6616be_st_sample_configuration/Release/configPkg/compiler.opt}""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DEFINE.1893019243" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DEFINE" valueType="definedSymbols"/>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2077986563" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE.710504412" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE" value=""edma3_drv_bios6_tci6616be_st_sample.out"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE.1705155931" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE" value=""edma3_drv_bios6_tci6616be_st_sample.map"" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY.315490869" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value=""${workspace_loc:/edma3_drv_bios6_tci6616be_st_sample_configuration/Release/configPkg/linker.cmd}""/>
+<listOptionValue builtIn="false" value=""rts64pluse.lib""/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH.1215685616" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${CG_TOOL_ROOT}/include""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/lib""/>
+<listOptionValue builtIn="false" value=""${C6000_CG_ROOT}/include""/>
+</option>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/simTCI6616BE/sample_app/.cdtproject b/examples/edma3_driver/simTCI6616BE/sample_app/.cdtproject
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/simTCI6616BE/sample_app/.project b/examples/edma3_driver/simTCI6616BE/sample_app/.project
--- /dev/null
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>edma3_drv_bios6_tci6616be_st_sample</name>
+ <comment></comment>
+ <projects>
+ <project>edma3_drv_bios6_tci6616be_st_sample_configuration</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>dma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_poll_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>
+ </link>
+ <link>
+ <name>main.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_misc_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>
+ </link>
+ <link>
+ <name>dma_ping_pong_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>
+ </link>
+ <link>
+ <name>qdma_link_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>
+ </link>
+ <link>
+ <name>common.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>
+ </link>
+ <link>
+ <name>dma_chain_test.c</name>
+ <type>1</type>
+ <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/examples/edma3_driver/simTCI6616BE/sample_app/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/simTCI6616BE/sample_app/.settings/org.eclipse.cdt.core.prefs
--- /dev/null
@@ -0,0 +1,3 @@
+#Mon Aug 03 19:13:16 IST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.nullindexer
diff --git a/examples/edma3_driver/simTCI6616BE/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/simTCI6616BE/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
--- /dev/null
+++ b/examples/edma3_driver/simTCI6616BE/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,9 @@
+#Fri Aug 14 19:45:21 IST 2009
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080/internalBuilder/ignoreErr=true
+com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352/internalBuilder/enabled=false
+com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352/internalBuilder/ignoreErr=true
+eclipse.preferences.version=1
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.1057171080=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.2041166352=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n
diff --git a/examples/edma3_driver/simTCI6616BE/sample_app/linker.cmd b/examples/edma3_driver/simTCI6616BE/sample_app/linker.cmd
--- /dev/null
@@ -0,0 +1,6 @@
+
+SECTIONS
+{
+ .my_sect_iram > L2SRAM
+ .my_sect_ddr > L2SRAM
+}
diff --git a/makerules/platform.mk b/makerules/platform.mk
index 0412d74f7e335f4f428a834c379534f2be6523ca..cc24d135eee370302863d35aa67417e2a2cbd4a9 100755 (executable)
--- a/makerules/platform.mk
+++ b/makerules/platform.mk
PLATFORM_XDC = "ti.platforms.evmTCI6486"
endif
-# tci6498 (Nyquist) Simulator - This might change
-ifeq ($(PLATFORM),tci6498-sim)
- SOC = c6498
- PLATFORM_XDC = "ti.platforms.simTCI6498"
+# tci6608 (Shannon) Simulator
+ifeq ($(PLATFORM),tci6608-sim)
+ SOC = c6608
+ PLATFORM_XDC = "ti.platforms.simTCI6608"
endif
+# tci6616 (Nyquist) Simulator
+ifeq ($(PLATFORM),tci6616-sim)
+ SOC = c6616
+ PLATFORM_XDC = "ti.platforms.simTCI6616"
+endif
+
+# c6670 (Nyquist) EVM
+ifeq ($(PLATFORM),c6670-evm)
+ SOC = c6670
+ PLATFORM_XDC = "ti.platforms.evm6670"
+endif
+
+# c6678 (Shannon) EVM
+ifeq ($(PLATFORM),c6678-evm)
+ SOC = c6678
+ PLATFORM_XDC = "ti.platforms.evm6678"
+endif
+
+
# omapl138 (Freon) EVM
ifeq ($(PLATFORM),omapl138-evm)
SOC = omapl138
ifeq ($(SOC),c6472)
ISA = 64p
endif
- # Note: The below is for Nyqyist Simulator - might change
- ifeq ($(SOC),c6498)
- ISA = 64p
+ ifeq ($(SOC),c6608)
+ ISA = 66
+ endif
+ ifeq ($(SOC),c6616)
+ ISA = 66
+ endif
+ ifeq ($(SOC),c6670)
+ ISA = 66
+ endif
+ ifeq ($(SOC),c6678)
+ ISA = 66
endif
endif
ASMEXT = s$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
endif
+ifeq ($(ISA),66)
+ ifeq ($(FORMAT),ELF)
+ ifeq ($(ENDIAN),big)
+ TARGET_XDC = ti.targets.elf.C66_big_endian
+ else
+ TARGET_XDC = ti.targets.elf.C66
+ endif
+ FORMAT_EXT = e
+ else
+ ifeq ($(ENDIAN),big)
+ TARGET_XDC = ti.targets.C66_big_endian
+ else
+ TARGET_XDC = ti.targets.C66
+ endif
+ endif
+
+ # If ENDIAN is set to "big", set ENDIAN_EXT to "e", that would be used in
+ # in the filename extension of object/library/executable files
+ ifeq ($(ENDIAN),big)
+ ENDIAN_EXT = e
+ endif
+
+ # Define the file extensions
+ OBJEXT = o$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+ LIBEXT = a$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+ EXEEXT = x$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+ ASMEXT = s$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+
+endif
+
ifeq ($(ISA),a8)
ifeq ($(TOOLCHAIN_a8),TI)
TARGET_XDC = ti.targets.arm.elf.A8F
diff --git a/makerules/rules_66.mk b/makerules/rules_66.mk
--- /dev/null
+++ b/makerules/rules_66.mk
@@ -0,0 +1,222 @@
+# Filename: rules_c66.mk
+#
+# Make rules for c66 - This file has all the common rules and defines required
+# for DSP c66 ISA
+#
+# This file needs to change when:
+# 1. Code generation tool chain changes (currently it uses TI CGT)
+# 2. Internal switches (which are normally not touched) has to change
+# 3. XDC specific switches change
+# 4. a rule common for c66 ISA has to be added or modified
+
+# Set compiler/archiver/linker commands and include paths - Currently different
+# for ELF and COFF. In a future release of the toolchain, it would merge.
+ifeq ($(FORMAT),COFF)
+ CODEGEN_PATH = $(CODEGEN_PATH_DSP)
+ CODEGEN_INCLUDE = $(CODEGEN_PATH_DSP)/include
+ CC = $(CODEGEN_PATH_DSP)/bin/cl6x
+ AR = $(CODEGEN_PATH_DSP)/bin/ar6x
+ LNK = $(CODEGEN_PATH_DSP)/bin/lnk6x
+endif
+ifeq ($(FORMAT),ELF)
+ CODEGEN_PATH = $(CODEGEN_PATH_DSPELF)
+ CODEGEN_INCLUDE = $(CODEGEN_PATH_DSPELF)/include
+ CC = $(CODEGEN_PATH_DSPELF)/bin/cl6x
+ AR = $(CODEGEN_PATH_DSPELF)/bin/ar6x
+ LNK = $(CODEGEN_PATH_DSPELF)/bin/lnk6x
+endif
+
+# Derive a part of RTS Library name based on ENDIAN: little/big
+ifeq ($(ENDIAN),little)
+ #RTSLIB_ENDIAN =
+ XDCINTERNAL_DEFINES += -Dxdc_target_name__=C66
+else
+ CSWITCH_ENDIAN = -me
+ RTSLIB_ENDIAN = e
+ XDCINTERNAL_DEFINES += -DBIG_ENDIAN_MODE -Dxdc_target_name__=C66_big_endian
+endif
+
+# Derive compiler switch and part of RTS Library name based on FORMAT: COFF/ELF
+ifeq ($(FORMAT),COFF)
+ CSWITCH_FORMAT =
+ #RTSLIB_FORMAT =
+ XDCINTERNAL_DEFINES += -Dxdc_target_types__=ti/targets/std.h -Dxdc_bld__vers_1_0_7_0_0
+endif
+ifeq ($(FORMAT),ELF)
+ CSWITCH_FORMAT = --abi=elfabi
+ RTSLIB_FORMAT = _elf
+ XDCINTERNAL_DEFINES += -Dxdc_target_types__=ti/targets/elf/std.h -Dxdc_bld__vers_1_0_7_2_0_10271
+endif
+
+# XDC Specific defines
+ifneq ($(XDC_CFG_FILE_$(CORE)),)
+ ifeq ($(PROFILE_$(CORE)),debug)
+ CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)66$(RTSLIB_ENDIAN)
+ endif
+ ifeq ($(PROFILE_$(CORE)),release)
+ CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)66$(RTSLIB_ENDIAN)
+ endif
+ ifeq ($(PROFILE_$(CORE)),whole_program_debug)
+ CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+ CFG_LNKFILENAMEPART_XDC=_x
+ endif
+ CFG_CFILE_XDC =$(patsubst %.cfg,%_$(CFG_CFILENAMEPART_XDC).c,$(notdir $(XDC_CFG_FILE_$(CORE))))
+ CFG_C_XDC = $(addprefix $(CONFIGURO_DIR)/package/cfg/,$(CFG_CFILE_XDC))
+ XDCLNKCMD_FILE =$(patsubst %.c, %$(CFG_LNKFILENAMEPART_XDC)_x.xdl, $(CFG_C_XDC))
+ CFG_COBJ_XDC = $(patsubst %.c,%.$(OBJEXT),$(CFG_CFILE_XDC))
+# OBJ_PATHS += $(CFG_COBJ_XDC)
+ LNKCMD_FILE = $(CONFIGURO_DIR)/linker_mod.cmd
+ SPACE :=
+ SPACE +=
+ XDC_GREP_STRING = $(CONFIGURO_DIRNAME)
+# XDC_GREP_STRING = $(subst $(SPACE),\|,$(COMP_LIST_$(CORE)))
+# XDC_GREP_STRING += \|$(CONFIGURO_DIRNAME)
+endif
+
+# Internal CFLAGS - normally doesn't change
+CFLAGS_INTERNAL = -c -qq -pdsw225 -mv6600 $(CSWITCH_FORMAT) $(CSWITCH_ENDIAN) -mo -eo.$(OBJEXT) -ea.$(ASMEXT)
+CFLAGS_DIROPTS = -fr=$(OBJDIR) -fs=$(OBJDIR)
+
+# CFLAGS based on profile selected
+ifeq ($(PROFILE_$(CORE)), debug)
+ CFLAGS_INTERNAL += --symdebug:dwarf
+ CFLAGS_XDCINTERNAL = -Dxdc_bld__profile_debug -D_DEBUG_=1
+ ifndef MODULE_NAME
+ CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/VpsAppMain_xem3.h'
+ endif
+ LNKFLAGS_INTERNAL_PROFILE =
+endif
+ifeq ($(PROFILE_$(CORE)), release)
+ CFLAGS_INTERNAL += -O2
+ CFLAGS_XDCINTERNAL = -Dxdc_bld__profile_release -DGENERIC
+ ifndef MODULE_NAME
+ CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/VpsAppMain_pem3.h'
+ endif
+ LNKFLAGS_INTERNAL_PROFILE = -o2
+# LNKFLAGS_INTERNAL_PROFILE =
+endif
+CFLAGS_XDCINTERNAL += $(XDCINTERNAL_DEFINES)
+
+# Following 'if...' block is for an application; to add a #define for each
+# component in the build. This is required to know - at compile time - which
+# components are on which core.
+ifndef MODULE_NAME
+ # Derive list of all packages from each of the components needed by the app
+ PKG_LIST_M3_LOCAL = $(foreach COMP,$(COMP_LIST_$(CORE)),$($(COMP)_PKG_LIST))
+
+ # Defines for the app and cfg source code to know which components/packages
+ # are included in the build for the local CORE...
+ CFLAGS_APP_DEFINES = $(foreach PKG,$(PKG_LIST_M3_LOCAL),-D_LOCAL_$(PKG)_)
+ CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_M3_LOCAL),-D_BUILD_$(PKG)_)
+
+ ifeq ($(CORE),m3vpss)
+ PKG_LIST_M3_REMOTE = $(foreach COMP,$(COMP_LIST_m3video),$($(COMP)_PKG_LIST))
+ CFLAGS_APP_DEFINES += -D_LOCAL_CORE_m3vpss_
+ endif
+ ifeq ($(CORE),m3video)
+ PKG_LIST_M3_REMOTE = $(foreach COMP,$(COMP_LIST_m3vpss),$($(COMP)_PKG_LIST))
+ CFLAGS_APP_DEFINES += -D_LOCAL_CORE_m3video_
+ endif
+ PKG_LIST_A8_REMOTE = $(foreach COMP,$(COMP_LIST_a8host),$($(COMP)_PKG_LIST))
+
+ # Defines for the app and cfg source code to know which components/packages
+ # are included in the build for the remote CORE...
+ CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_M3_REMOTE),-D_REMOTE_$(PKG)_)
+ CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_M3_REMOTE),-D_BUILD_$(PKG)_)
+ CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_A8_REMOTE),-D_REMOTE_$(PKG)_)
+ CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_A8_REMOTE),-D_BUILD_$(PKG)_)
+endif
+
+# Assemble CFLAGS from all other CFLAGS definitions
+_CFLAGS = $(CFLAGS_INTERNAL) $(CFLAGS_GLOBAL_$(CORE)) $(CFLAGS_XDCINTERNAL) $(CFLAGS_LOCAL_COMMON) $(CFLAGS_LOCAL_$(CORE)) $(CFLAGS_LOCAL_$(PLATFORM)) $(CFLAGS_LOCAL_$(SOC)) $(CFLAGS_APP_DEFINES) $(CFLAGS_COMP_COMMON) $(CFLAGS_GLOBAL_$(PLATFORM))
+
+# Object file creation
+# The first $(CC) generates the dependency make files for each of the objects
+# The second $(CC) compiles the source to generate object
+$(OBJ_PATHS): $(OBJDIR)/%.$(OBJEXT): %.c
+ $(ECHO) \# Compiling $< to $@ ...
+ $(CC) -ppd=$(DEPFILE).P $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $<
+ $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $<
+
+# Archive flags - normally doesn't change
+ARFLAGS = rq
+
+# Archive/library file creation
+$(LIBDIR)/$(MODULE_NAME).$(LIBEXT) : $(OBJ_PATHS)
+ $(ECHO) \#
+ $(ECHO) \# Archiving $(OBJ_PATHS) into $@...
+ $(ECHO) \#
+ $(AR) $(ARFLAGS) $@ $(OBJ_PATHS)
+
+# Linker options and rules
+LNKFLAGS_INTERNAL_COMMON = --warn_sections -q -e=_c_int00 --silicon_version=64+ -c
+
+# Assemble Linker flags from all other LNKFLAGS definitions
+_LNKFLAGS = $(LNKFLAGS_INTERNAL_COMMON) $(LNKFLAGS_INTERNAL_PROFILE) $(LNKFLAGS_GLOBAL_$(CORE)) $(LNKFLAGS_LOCAL_COMMON) $(LNKFLAGS_LOCAL_$(CORE))
+
+# Path of the RTS library - normally doesn't change for a given tool-chain
+RTSLIB_PATH = $(CODEGEN_PATH)/lib/rts6600$(RTSLIB_ENDIAN)$(RTSLIB_FORMAT).lib
+LIB_PATHS += $(RTSLIB_PATH)
+
+LNK_LIBS = $(addprefix -l,$(LIB_PATHS))
+ifeq ($(DEST_ROOT),)
+ TMPOBJDIR = .
+else
+ TMPOBJDIR = $(OBJDIR)
+endif
+# Linker - to create executable file
+$(BINDIR)/$(APP_NAME)_$(CORE)_$(PROFILE_$(CORE)).$(EXEEXT) : $(OBJ_PATHS) $(LIB_PATHS) $(LNKCMD_FILE) $(OBJDIR)/$(CFG_COBJ_XDC)
+ $(ECHO) \# Linking into $@
+ $(ECHO) \#
+ cd $(TMPOBJDIR) && $(LNK) $(_LNKFLAGS) $(OBJ_PATHS) $(OBJDIR)/$(CFG_COBJ_XDC) -l$(LNKCMD_FILE) sample_app/linker.cmd -o $@ -m $@.map $(LNK_LIBS)
+ $(ECHO) \#
+ $(ECHO) \# $@ created.
+ $(ECHO) \#
+
+# XDC specific - assemble XDC-Configuro command
+CONFIGURO_CMD = $(xdc_PATH)/xs xdc.tools.configuro --generationOnly -o $(CONFIGURO_DIR) -t $(TARGET_XDC) -p $(PLATFORM_XDC) \
+ -r whole_program -c $(CODEGEN_PATH) -b $(CONFIG_BLD_XDC_$(ISA)) $(XDC_CFG_FILE_NAME)
+_XDC_GREP_STRING = \"$(XDC_GREP_STRING)\"
+EGREP_CMD = $(EGREP) -ivw $(XDC_GREP_STRING) $(XDCLNKCMD_FILE)
+
+ifneq ($(DEST_ROOT),)
+ DEST_ROOT += /
+endif
+# Invoke configuro for the rest of the components
+# NOTE: 1. String handling is having issues with various make versions when the
+# cammand is directly tried to be given below. Hence, as a work-around,
+# the command is re-directed to a file (shell or batch file) and then
+# executed
+# 2. The linker.cmd file generated, includes the libraries generated by
+# XDC. An egrep to search for these and omit in the .cmd file is added
+# after configuro is done
+#$(CFG_CFILE_XDC) : $(XDC_CFG_FILE)
+xdc_configuro : $(XDC_CFG_FILE)
+ $(ECHO) \# Invoking configuro...
+ $(ECHO) -e $(CONFIGURO_CMD) > $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat
+ $(CHMOD) a+x $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat
+ $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat
+ $(CP) $(XDCLNKCMD_FILE) $(LNKCMD_FILE)
+# $(ECHO) @ $(EGREP_CMD) > maketemp_egrep_cmd.bat
+# ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)
+# $(EGREP_CMD) > $(LNKCMD_FILE)
+# $(EGREP) -iv "$(XDC_GREP_STRING)" $(XDCLNKCMD_FILE) > $(LNKCMD_FILE)
+ $(ECHO) \# Configuro done!
+
+$(LNKCMD_FILE) :
+# $(CP) $(XDCLNKCMD_FILE) $(LNKCMD_FILE)
+# $(ECHO) @ $(EGREP_CMD) > maketemp_egrep_cmd.bat
+# ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)
+# $(EGREP_CMD) > $(LNKCMD_FILE)
+
+ifndef MODULE_NAME
+$(OBJDIR)/$(CFG_COBJ_XDC) : $(CFG_C_XDC)
+ $(ECHO) \# Compiling generated $< to $@ ...
+ $(CC) -ppd=$(DEPFILE).P $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $(CFG_C_XDC)
+ $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $(CFG_C_XDC)
+endif
+
+# Include dependency make files that were generated by $(CC)
+-include $(SRCS:%.c=$(DEPDIR)/%.P)
+
+# Nothing beyond this point
diff --git a/packages/component.mk b/packages/component.mk
index 5a049e82db38a2ce56b78c4dca023cb907793f28..3290845d0ec8df91c79c9d4c702d6afc38e71879 100755 (executable)
--- a/packages/component.mk
+++ b/packages/component.mk
edma3_lld_EXAMPLES_LIST = edma3_drv_c6472_sample edma3_drv_c6472be_sample edma3_drv_c6748_sample \
edma3_drv_da830_sample edma3_drv_omapl138_sample \
edma3_drv_tci6486_sample edma3_drv_tci6486be_sample edma3_drv_ti816x_sample \
- edma3_drv_ti816x_sim_sample edma3_drv_tci6498_sample edma3_drv_tci6498be_sample \
+ edma3_drv_ti816x_sim_sample \
edma3_drv_ti814x_sample edma3_drv_arm_ti814x_sample \
+ edma3_drv_tci6608_sample edma3_drv_tci6608be_sample \
+ edma3_drv_tci6616_sample edma3_drv_tci6616be_sample \
+ edma3_drv_c6670_sample edma3_drv_c6670be_sample \
+ edma3_drv_c6678_sample edma3_drv_c6678be_sample \
# edma3_drv_arm_omapl138_sample
# List of libraries
@@ -113,10 +117,27 @@ edma3_drv_ti816x_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_ti816x_sam
edma3_drv_ti816x_sim_sample_EXAMPLES_RELPATH = examples/edma3_driver/simTI816x
edma3_drv_ti816x_sim_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_ti816x_sim_sample_EXAMPLES_RELPATH)
-edma3_drv_tci6498_sample_EXAMPLES_RELPATH = examples/edma3_driver/simTCI6498
-edma3_drv_tci6498_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tci6498_sample_EXAMPLES_RELPATH)
+edma3_drv_tci6608_sample_EXAMPLES_RELPATH = examples/edma3_driver/simTCI6608
+edma3_drv_tci6608_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tci6608_sample_EXAMPLES_RELPATH)
-edma3_drv_tci6498be_sample_EXAMPLES_RELPATH = examples/edma3_driver/simTCI6498BE
-edma3_drv_tci6498be_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tci6498be_sample_EXAMPLES_RELPATH)
+edma3_drv_tci6608be_sample_EXAMPLES_RELPATH = examples/edma3_driver/simTCI6608BE
+edma3_drv_tci6608be_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tci6608be_sample_EXAMPLES_RELPATH)
+edma3_drv_tci6616_sample_EXAMPLES_RELPATH = examples/edma3_driver/simTCI6616
+edma3_drv_tci6616_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tci6616_sample_EXAMPLES_RELPATH)
+
+edma3_drv_tci6616be_sample_EXAMPLES_RELPATH = examples/edma3_driver/simTCI6616BE
+edma3_drv_tci6616be_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tci6616be_sample_EXAMPLES_RELPATH)
+
+edma3_drv_c6670_sample_EXAMPLES_RELPATH = examples/edma3_driver/evm6670
+edma3_drv_c6670_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_c6670_sample_EXAMPLES_RELPATH)
+
+edma3_drv_c6670be_sample_EXAMPLES_RELPATH = examples/edma3_driver/evm6670BE
+edma3_drv_c6670be_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_c6670be_sample_EXAMPLES_RELPATH)
+
+edma3_drv_c6678_sample_EXAMPLES_RELPATH = examples/edma3_driver/evm6678
+edma3_drv_c6678_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_c6678_sample_EXAMPLES_RELPATH)
+
+edma3_drv_c6678be_sample_EXAMPLES_RELPATH = examples/edma3_driver/evm6678BE
+edma3_drv_c6678be_sample_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_c6678be_sample_EXAMPLES_RELPATH)
# Nothing beyond this point
diff --git a/packages/config.bld b/packages/config.bld
index 02d9c01f05790b50baf4e1a66d3c5536bf6a667c..6d217d3e726342186406ea48c80398eee3df0d53 100755 (executable)
--- a/packages/config.bld
+++ b/packages/config.bld
/* set default platform and list of all interested platforms */
C64P.platforms = [
- "ti.platforms.simTCI6498",
"ti.platforms.evm6472",
"ti.platforms.evmTCI6486",
];
C64Pe.platforms = [
- "ti.platforms.simTCI6498",
"ti.platforms.evm6472",
"ti.platforms.evmTCI6486",
];
"ti.platforms.evmDM8148",
];
C64P_ELF.platforms = [
- "ti.platforms.simTCI6498",
"ti.platforms.evm6472",
"ti.platforms.evmTCI6486",
];
C64Pe_ELF.platforms = [
- "ti.platforms.simTCI6498",
"ti.platforms.evm6472",
"ti.platforms.evmTCI6486",
];
"ti.platforms.evmDM8148",
];
C66.platforms = [
- /*empty*/
+ "ti.platforms.simTCI6608",
+ "ti.platforms.simTCI6616",
+ "ti.platforms.evm6670",
+ "ti.platforms.evm6678",
];
C66e.platforms = [
- /*empty*/
+ "ti.platforms.simTCI6608",
+ "ti.platforms.simTCI6616",
+ "ti.platforms.evm6670",
+ "ti.platforms.evm6678",
];
Arm.platforms = [
"ti.platforms.evmOMAPL138",
C64P_ELF.platform = C64P_ELF.platforms[0];
C64Pe_ELF.platform = C64Pe_ELF.platforms[0];
C674_ELF.platform = C674_ELF.platforms[0];
-C66.platform = null;
-C66e.platform = null;
+C66.platform = C66.platforms[0];
+C66e.platform = C66e.platforms[0];
Arm.platform = Arm.platforms[0];
cortexA8.platform = cortexA8.platforms[0];
C64P_ELF,
C64Pe_ELF,
C674_ELF,
- //C66,
- //C66e,
+ C66,
+ C66e,
Arm,
cortexA8,
//Win32,
diff --git a/packages/makefile b/packages/makefile
index 85d0fdb71c2a44daf04ba774609fbd299ee8551c..46cf8b1d845d096ea670468026ecd1e435c24b6d 100755 (executable)
--- a/packages/makefile
+++ b/packages/makefile
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Making c64p:release:edma3_lld_drv -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making c66:debug:edma3_lld_drv
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=debug
+ $(ECHO) \# Making c66:release:edma3_lld_drv
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=release
+ $(ECHO) \# Making c66:debug:edma3_lld_drv -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making c66:release:edma3_lld_drv -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Making c674:debug:edma3_lld_drv
$(MAKE) -C $($@_PATH) PLATFORM=ti816x-evm PROFILE_c6xdsp=debug
$(ECHO) \# Making c674:release:edma3_lld_drv
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm PROFILE_c6xdsp=debug
$(ECHO) \# Making tci6486-evm:debug:edma3_lld_rm
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm PROFILE_c6xdsp=debug
- $(ECHO) \# Making tci6498-sim:debug:edma3_lld_rm
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Making tci6608-sim:debug:edma3_lld_rm
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Making tci6616-sim:debug:edma3_lld_rm
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Making c6670-evm:debug:edma3_lld_rm
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm PROFILE_c6xdsp=debug
+ $(ECHO) \# Making c6678-evm:debug:edma3_lld_rm
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=debug
$(ECHO) \# Making c6472-evm:debug:edma3_lld_rm -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Making tci6486-evm:debug:edma3_lld_rm -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm PROFILE_c6xdsp=debug ENDIAN=big
- $(ECHO) \# Making tci6498-sim:debug:edma3_lld_rm -for big_endian
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making tci6608-sim:debug:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making tci6616-sim:debug:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making c6670-evm:debug:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making c6678-evm:debug:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Making omapl138-evm:debug:edma3_lld_rm
$(MAKE) -C $($@_PATH) PLATFORM=omapl138-evm PROFILE_c6xdsp=debug
$(ECHO) \# Making c6748-evm:debug:edma3_lld_rm
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm PROFILE_c6xdsp=release
$(ECHO) \# Making tci6486-evm:release:edma3_lld_rm
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm PROFILE_c6xdsp=release
- $(ECHO) \# Making tci6498-sim:release:edma3_lld_rm
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Making tci6608-sim:release:edma3_lld_rm
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Making tci6616-sim:release:edma3_lld_rm
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Making c6670-evm:release:edma3_lld_rm
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm PROFILE_c6xdsp=release
+ $(ECHO) \# Making c6678-evm:release:edma3_lld_rm
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=release
$(ECHO) \# Making c6472-evm:release:edma3_lld_rm -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Making tci6486-evm:release:edma3_lld_rm -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm PROFILE_c6xdsp=release ENDIAN=big
- $(ECHO) \# Making tci6498-sim:release:edma3_lld_rm -for big_endian
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making tci6608-sim:release:edma3_lld_rm for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making tci6616-sim:release:edma3_lld_rm for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making c6670-evm:release:edma3_lld_rm for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making c6678-evm:release:edma3_lld_rm for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Making omapl138-evm:release:edma3_lld_rm
$(MAKE) -C $($@_PATH) PLATFORM=omapl138-evm PROFILE_c6xdsp=release
$(ECHO) \# Making c6748-evm:release:edma3_lld_rm
$(MAKE) -C $($(subst _generic,,$@)_PATH) PLATFORM=generic CORE=64p PROFILE_64p=debug ENDIAN=little
$(ECHO) \# Making generic/c64p:release:edma3_lld_rm
$(MAKE) -C $($(subst _generic,,$@)_PATH) PLATFORM=generic CORE=64p PROFILE_64p=release ENDIAN=little
+ $(ECHO) \# Making generic/c66:debug:edma3_lld_rm: -for big_endian
+ $(MAKE) -C $($(subst _generic,,$@)_PATH) PLATFORM=generic CORE=66 PROFILE_66=debug ENDIAN=big
+ $(ECHO) \# Making generic/c66:release:edma3_lld_rm: -for big_endian
+ $(MAKE) -C $($(subst _generic,,$@)_PATH) PLATFORM=generic CORE=66 PROFILE_66=release ENDIAN=big
+ $(ECHO) \# Making generic/c66:debug:edma3_lld_rm
+ $(MAKE) -C $($(subst _generic,,$@)_PATH) PLATFORM=generic CORE=66 PROFILE_66=debug ENDIAN=little
+ $(ECHO) \# Making generic/c66:release:edma3_lld_rm
+ $(MAKE) -C $($(subst _generic,,$@)_PATH) PLATFORM=generic CORE=66 PROFILE_66=release ENDIAN=little
$(ECHO) \# Making generic/m3:debug:edma3_lld_rm
$(MAKE) -C $($(subst _generic,,$@)_PATH) PLATFORM=generic CORE=m3 PROFILE_m3=debug
$(ECHO) \# Making generic/m3:release:edma3_lld_rm
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm CORE=c6xdsp PROFILE_c6xdsp=debug
$(ECHO) \# Making tci6486-evm:debug:edma3_lld_rm_sample
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm CORE=c6xdsp PROFILE_c6xdsp=debug
- $(ECHO) \# Making tci6498-sim:debug:edma3_lld_rm_sample
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making tci6608-sim:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making tci6616-sim:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making c6670-evm:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making c6678-evm:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=debug
$(ECHO) \# Making c6472-evm:debug:edma3_lld_rm_sample -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Making tci6486-evm:debug:edma3_lld_rm_sample -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
- $(ECHO) \# Making tci6498-sim:debug:edma3_lld_rm_sample -for big_endian
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making tci6608-sim:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making tci6616-sim:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making c6670-evm:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making c6678-evm:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Making omapl138-evm:debug:edma3_lld_rm_sample
$(MAKE) -C $($@_PATH) PLATFORM=omapl138-evm CORE=c6xdsp PROFILE_c6xdsp=debug
$(ECHO) \# Making c6748-evm:debug:edma3_lld_rm_sample
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm CORE=c6xdsp PROFILE_c6xdsp=release
$(ECHO) \# Making tci6486-evm:release:edma3_lld_rm_sample
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm CORE=c6xdsp PROFILE_c6xdsp=release
- $(ECHO) \# Making tci6498-sim:release:edma3_lld_rm_sample
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making tci6608-sim:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making tci6616-sim:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making c6670-evm:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making c6678-evm:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=release
$(ECHO) \# Making c6472-evm:release:edma3_lld_rm_sample -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Making tci6486-evm:release:edma3_lld_rm_sample -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
- $(ECHO) \# Making tci6498-sim:release:edma3_lld_rm_sample -for big_endian
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making tci6608-sim:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making tci6616-sim:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making c6670-evm:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making c6678-evm:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Making omapl138-evm:release:edma3_lld_rm_sample
$(MAKE) -C $($@_PATH) PLATFORM=omapl138-evm CORE=c6xdsp PROFILE_c6xdsp=release
$(ECHO) \# Making c6748-evm:release:edma3_lld_rm_sample
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm CORE=c6xdsp PROFILE_c6xdsp=debug
$(ECHO) \# Making tci6486-evm:debug:edma3_lld_drv_sample
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm CORE=c6xdsp PROFILE_c6xdsp=debug
- $(ECHO) \# Making tci6498-sim:debug:edma3_lld_drv_sample
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making tci6608-sim:debug:edma3_lld_drv_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making tci6616-sim:debug:edma3_lld_drv_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making c6670-evm:debug:edma3_lld_drv_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making c6678-evm:debug:edma3_lld_drv_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=debug
$(ECHO) \# Making c6472-evm:debug:edma3_lld_drv_sample -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Making tci6486-evm:debug:edma3_lld_drv_sample -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
- $(ECHO) \# Making tci6498-sim:debug:edma3_lld_drv_sample -for big_endian
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making tci6608-sim:debug:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making tci6616-sim:debug:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making c6670-evm:debug:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making c6678-evm:debug:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Making omapl138-evm:debug:edma3_lld_drv_sample
$(MAKE) -C $($@_PATH) PLATFORM=omapl138-evm CORE=c6xdsp PROFILE_c6xdsp=debug
$(ECHO) \# Making c6748-evm:debug:edma3_lld_drv_sample
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm CORE=c6xdsp PROFILE_c6xdsp=release
$(ECHO) \# Making tci6486-evm:release:edma3_lld_drv_sample
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm CORE=c6xdsp PROFILE_c6xdsp=release
- $(ECHO) \# Making tci6498-sim:release:edma3_lld_drv_sample
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making tci6608-sim:release:edma3_lld_drv_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making tci6616-sim:release:edma3_lld_drv_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making c6670-evm:release:edma3_lld_drv_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making c6678-evm:release:edma3_lld_drv_sample
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=release
$(ECHO) \# Making c6472-evm:release:edma3_lld_drv_sample -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=c6472-evm CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Making tci6486-evm:release:edma3_lld_drv_sample -for big_endian
$(MAKE) -C $($@_PATH) PLATFORM=tci6486-evm CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
- $(ECHO) \# Making tci6498-sim:release:edma3_lld_drv_sample -for big_endian
- $(MAKE) -C $($@_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making tci6608-sim:release:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making tci6616-sim:release:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making c6670-evm:release:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making c6678-evm:release:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($@_PATH) PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Making omapl138-evm:release:edma3_lld_drv_sample
$(MAKE) -C $($@_PATH) PLATFORM=omapl138-evm CORE=c6xdsp PROFILE_c6xdsp=release
$(ECHO) \# Making c6748-evm:release:edma3_lld_drv_sample
$(ECHO) \# Making example $@:release
$(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=ti816x-sim CORE=c6xdsp PROFILE_c6xdsp=release
-edma3_drv_tci6498_sample:
+edma3_drv_tci6608_sample:
$(ECHO) \# Configuring XDC packages for $@:c6xdsp:debug
- $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=debug
$(ECHO) \# Making example $@:debug
- $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6608-sim PROFILE_c6xdsp=debug
$(ECHO) \# Configuring XDC packages for $@:c6xdsp:release
- $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=release
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=release
$(ECHO) \# Making example $@:release
- $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=release
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6608-sim PROFILE_c6xdsp=release
-edma3_drv_tci6498be_sample:
+edma3_drv_tci6608be_sample:
$(ECHO) \# Configuring XDC packages for $@:c6xdsp:debug
- $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Making example $@:debug
- $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6608-sim PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Configuring XDC packages for $@:c6xdsp:release
- $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6608-sim CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Making example $@:release
- $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6498-sim CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6608-sim PROFILE_c6xdsp=release ENDIAN=big
+
+edma3_drv_tci6616_sample:
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making example $@:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6616-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making example $@:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6616-sim PROFILE_c6xdsp=release
+
+edma3_drv_tci6616be_sample:
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making example $@:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6616-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tci6616-sim CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making example $@:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tci6616-sim PROFILE_c6xdsp=release ENDIAN=big
+
+edma3_drv_c6670_sample:
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making example $@:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6670-evm PROFILE_c6xdsp=debug
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making example $@:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6670-evm PROFILE_c6xdsp=release
+
+edma3_drv_c6670be_sample:
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making example $@:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6670-evm PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=c6670-evm CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making example $@:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6670-evm PROFILE_c6xdsp=release ENDIAN=big
+
+
+edma3_drv_c6678_sample:
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+ $(ECHO) \# Making example $@:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=debug
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=release
+ $(ECHO) \# Making example $@:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=release
+
+edma3_drv_c6678be_sample:
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Making example $@:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Configuring XDC packages for $@:c6xdsp:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=c6678-evm CORE=c6xdsp PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Making example $@:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6678-evm PROFILE_c6xdsp=release ENDIAN=big
+
edma3_drv_arm_omapl138_sample:
ifeq ($(FORMAT),ELF)
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Cleaning c64p:release:edma3_lld_drv -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=release ENDIAN=big
+
+ $(ECHO) \# Cleaning c66:debug:edma3_lld_drv
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning c66:release:edma3_lld_drv
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning c66:debug:edma3_lld_drv -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning c66:release:edma3_lld_drv -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning c66:debug:edma3_lld_drv
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning c66:release:edma3_lld_drv
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning c66:debug:edma3_lld_drv -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning c66:release:edma3_lld_drv -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning c66:debug:edma3_lld_drv
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning c66:release:edma3_lld_drv
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning c66:debug:edma3_lld_drv -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning c66:release:edma3_lld_drv -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning c66:debug:edma3_lld_drv
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning c66:release:edma3_lld_drv
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning c66:debug:edma3_lld_drv -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning c66:release:edma3_lld_drv -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Cleaning c674:debug:edma3_lld_drv
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=ti816x-evm PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning c674:release:edma3_lld_drv
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_rm
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=debug
- $(ECHO) \# Cleaning tci6498-sim:debug:edma3_lld_rm
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning tci6608-sim:debug:edma3_lld_rm
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning tci6616-sim:debug:edma3_lld_rm
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning c6670-evm:debug:edma3_lld_rm
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning c6678-evm:debug:edma3_lld_rm
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug
+
$(ECHO) \# Cleaning c6472-evm:debug:edma3_lld_rm -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_rm -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=debug ENDIAN=big
- $(ECHO) \# Cleaning tci6498-sim:debug:edma3_lld_rm -for big_endian
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning tci6608-sim:debug:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning tci6616-sim:debug:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning c6670-evm:debug:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning c6678-evm:debug:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Cleaning omapl138-evm:debug:edma3_lld_rm
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omapl138-evm PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning c6748-evm:debug:edma3_lld_rm
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=release
$(ECHO) \# Cleaning tci6486-evm:release:edma3_lld_rm
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=release
- $(ECHO) \# Cleaning tci6498-sim:release:edma3_lld_rm
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning tci6608-sim:release:edma3_lld_rm
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning tci6616-sim:release:edma3_lld_rm
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning c6670-evm:release:edma3_lld_rm
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning c6678-evm:release:edma3_lld_rm
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release
+
$(ECHO) \# Cleaning c6472-evm:release:edma3_lld_rm -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Cleaning tci6486-evm:release:edma3_lld_rm -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=release ENDIAN=big
- $(ECHO) \# Cleaning tci6498-sim:release:edma3_lld_rm -for big_endian
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning tci6608-sim:release:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning tci6616-sim:release:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning c6670-evm:release:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning c6678-evm:release:edma3_lld_rm -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release ENDIAN=big
+
$(ECHO) \# Cleaning omapl138-evm:release:edma3_lld_rm
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omapl138-evm PROFILE_c6xdsp=release
$(ECHO) \# Cleaning c6748-evm:release:edma3_lld_rm
$(MAKE) -C $($(subst _generic_clean,,$@)_PATH) PLATFORM=generic CORE=64p PROFILE_64p=debug ENDIAN=little
$(ECHO) \# Cleaning generic/c64p:release:edma3_lld_rm
$(MAKE) -C $($(subst _generic_clean,,$@)_PATH) PLATFORM=generic CORE=64p PROFILE_64p=release ENDIAN=little
+ $(ECHO) \# Cleaning generic/c66:debug:edma3_lld_rm: -for big_endian
+ $(MAKE) -C $($(subst _generic_clean,,$@)_PATH) PLATFORM=generic CORE=66 PROFILE_66=debug ENDIAN=big
+ $(ECHO) \# Cleaning generic/c66:release:edma3_lld_rm: -for big_endian
+ $(MAKE) -C $($(subst _generic_clean,,$@)_PATH) PLATFORM=generic CORE=66 PROFILE_66=release ENDIAN=big
+ $(ECHO) \# Cleaning generic/c66:debug:edma3_lld_rm
+ $(MAKE) -C $($(subst _generic_clean,,$@)_PATH) PLATFORM=generic CORE=66 PROFILE_66=debug ENDIAN=little
+ $(ECHO) \# Cleaning generic/c66:release:edma3_lld_rm
+ $(MAKE) -C $($(subst _generic_clean,,$@)_PATH) PLATFORM=generic CORE=66 PROFILE_66=release ENDIAN=little
$(ECHO) \# Cleaning generic/m3:debug:edma3_lld_rm
$(MAKE) -C $($(subst _generic_clean,,$@)_PATH) PLATFORM=generic CORE=m3 PROFILE_m3=debug
$(ECHO) \# Cleaning generic/m3:release:edma3_lld_rm
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_rm_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=debug
- $(ECHO) \# Cleaning tci6498-sim:debug:edma3_lld_rm_sample
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning tci6608-sim:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning tci6616-sim:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning c6670-evm:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning c6678-evm:debug:edma3_lld_rm_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning c6472-evm:debug:edma3_lld_rm_sample -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_rm_sample -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=debug ENDIAN=big
- $(ECHO) \# CleaningCleaningtci6498-sim:debug:edma3_lld_rm_sample -for big_endian
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning tci6608-sim:release:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning tci6616-sim:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning c6670-evm:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning c6678-evm:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug ENDIAN=big
+
$(ECHO) \# Cleaning omapl138-evm:debug:edma3_lld_rm_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omapl138-evm PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning c6748-evm:debug:edma3_lld_rm_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=release
$(ECHO) \# Cleaning tci6486-evm:release:edma3_lld_rm_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=release
- $(ECHO) \# Cleaning tci6498-sim:release:edma3_lld_rm_sample
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning tci6608-sim:release:edma3_lld_rm_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning tci6616-sim:release:edma3_lld_rm_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning c6670-evm:release:edma3_lld_rm_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning c6678-evm:release:edma3_lld_rm_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release
$(ECHO) \# Cleaning c6472-evm:release:edma3_lld_rm_sample -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Cleaning tci6486-evm:release:edma3_lld_rm_sample -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=release ENDIAN=big
- $(ECHO) \# Cleaning tci6498-sim:release:edma3_lld_rm_sample -for big_endian
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning tci6608-sim:release:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning tci6616-sim:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning c6670-evm:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning c6678-evm:debug:edma3_lld_rm_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Cleaning omapl138-evm:release:edma3_lld_rm_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omapl138-evm PROFILE_c6xdsp=release
$(ECHO) \# Cleaning c6748-evm:release:edma3_lld_rm_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_drv_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=debug
- $(ECHO) \# Cleaning tci6498-sim:debug:edma3_lld_drv_sample
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning tci6608-sim:debug:edma3_lld_drv_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning tci6616-sim:debug:edma3_lld_drv_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning c6670-evm:debug:edma3_lld_drv_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning c6678-evm:debug:edma3_lld_drv_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning c6472-evm:debug:edma3_lld_drv_sample -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Cleaning tci6486-evm:debug:edma3_lld_drv_sample -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=debug ENDIAN=big
- $(ECHO) \# Cleaning tci6498-sim:debug:edma3_lld_drv_sample -for big_endian
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning tci6608-sim:debug:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning tci6616-sim:debug:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning c6670-evm:debug:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning c6678-evm:debug:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=debug ENDIAN=big
$(ECHO) \# Cleaning omapl138-evm:debug:edma3_lld_drv_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omapl138-evm PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning c6748-evm:debug:edma3_lld_drv_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=release
$(ECHO) \# Cleaning tci6486-evm:release:edma3_lld_drv_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=release
- $(ECHO) \# Cleaning tci6498-sim:release:edma3_lld_drv_sample
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning tci6608-sim:release:edma3_lld_drv_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning tci6616-sim:release:edma3_lld_drv_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning c6670-evm:release:edma3_lld_drv_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=release
+ $(ECHO) \# Cleaning c6678-evm:release:edma3_lld_drv_sample
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release
+
$(ECHO) \# Cleaning c6472-evm:release:edma3_lld_drv_sample -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6472-evm PROFILE_c6xdsp=release ENDIAN=big
$(ECHO) \# Cleaning tci6486-evm:release:edma3_lld_drv_sample -for big_endian
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6486-evm PROFILE_c6xdsp=release ENDIAN=big
- $(ECHO) \# Cleaning tci6498-sim:release:edma3_lld_drv_sample -for big_endian
- $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning tci6608-sim:release:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning tci6616-sim:release:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning c6670-evm:release:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6670-evm PROFILE_c6xdsp=release ENDIAN=big
+ $(ECHO) \# Cleaning c6678-evm:release:edma3_lld_drv_sample -for big_endian
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=c6678-evm PROFILE_c6xdsp=release ENDIAN=big
+
$(ECHO) \# Cleaning omapl138-evm:release:edma3_lld_drv_sample
$(MAKE) -C $($(subst _clean,,$@)_PATH) clean PLATFORM=omapl138-evm PROFILE_c6xdsp=release
$(ECHO) \# Cleaning c6748-evm:release:edma3_lld_drv_sample
$(ECHO) \# Cleaning example $@:release
$(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=ti816x-sim PROFILE_c6xdsp=release
-edma3_drv_tci6498_sample_clean:
+edma3_drv_tci6608_sample_clean:
+ $(ECHO) \# Cleaning example $@:debug
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning example $@:release
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=release
+
+edma3_drv_tci6608be_sample_clean:
+ $(ECHO) \# Cleaning example $@:debug
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning example $@:release
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6608-sim PROFILE_c6xdsp=release ENDIAN=big
+
+edma3_drv_tci6616_sample_clean:
+ $(ECHO) \# Cleaning example $@:debug
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=debug
+ $(ECHO) \# Cleaning example $@:release
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=release
+
+edma3_drv_tci6616be_sample_clean:
+ $(ECHO) \# Cleaning example $@:debug
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning example $@:release
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6616-sim PROFILE_c6xdsp=release ENDIAN=big
+
+edma3_drv_c6670_sample_clean:
$(ECHO) \# Cleaning example $@:debug
- $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=debug
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=c6670-sim PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning example $@:release
- $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=release
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=c6670-sim PROFILE_c6xdsp=release
-edma3_drv_tci6498be_sample_clean:
+edma3_drv_c6670be_sample_clean:
+ $(ECHO) \# Cleaning example $@:debug
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=c6670-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning example $@:release
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=c6670-sim PROFILE_c6xdsp=release ENDIAN=big
+
+edma3_drv_c6678_sample_clean:
$(ECHO) \# Cleaning example $@:debug
- $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=c6678-sim PROFILE_c6xdsp=debug
$(ECHO) \# Cleaning example $@:release
- $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tci6498-sim PROFILE_c6xdsp=release ENDIAN=big
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=c6678-sim PROFILE_c6xdsp=release
+edma3_drv_c6678be_sample_clean:
+ $(ECHO) \# Cleaning example $@:debug
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=c6678-sim PROFILE_c6xdsp=debug ENDIAN=big
+ $(ECHO) \# Cleaning example $@:release
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=c6678-sim PROFILE_c6xdsp=release ENDIAN=big
+
+
# Help
help:
$(ECHO) EDMA3 LLD Driver Help page
index 3ff74fa36876849bc1fca9e5b9ce0d5ad7fbe169..6382c39fb6648b33c6a543d9a5e2b84a7dbcdefc 100755 (executable)
'C674',
'Arm9',
'A8F',
+ 'C66',
+ 'C66_big_endian',
];
/* Directories for each target */
'674/',
'arm9/',
'a8/',
+ '66/',
+ '66/',
];
for each (var targ in Build.targets)
Pkg.addLibrary(lib + "release/" + Pkg.name, targ,
{ defs:"-DBIG_ENDIAN_MODE", profile: "release"}
).addObjects(objList);
+ benchmark("lib/release/" + Pkg.name, targ);
} else {
Pkg.addLibrary(lib + "debug/" + Pkg.name, targ,
{ defs:"", profile: "debug"}
Pkg.addLibrary(lib + "release/" + Pkg.name, targ,
{ defs:"", profile: "release"}
).addObjects(objList);
+ benchmark("lib/release/" + Pkg.name, targ);
}
}
+function benchmark(lldFullLibraryPath, target)
+{
+ /* Create the Epilogue; which executes after all the builds are completed.
+ * This is used to generate the benchmark information for the built library.
+ * Also add the benchmarking information file to the package. */
+ Pkg.makeEpilogue += ".libraries: benchmarking_" + target.suffix + "\n";
+ Pkg.makeEpilogue += "benchmarking_" + target.suffix + ":";
+ Pkg.makeEpilogue += "\n\t ofd6x.exe -x " + lldFullLibraryPath + ".a" + target.suffix + " > tmp.xml";
+ Pkg.makeEpilogue += "\n\t sectti.exe tmp.xml > " + lldFullLibraryPath + ".a" + target.suffix + "_size.txt";
+ Pkg.makeEpilogue += "\n\t $(RM) tmp.xml\n\n";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix + "_size.txt";
+
+ /* We need to clean after ourselves; extend the 'clean' target to take care of this. */
+ Pkg.makeEpilogue += "clean::\n\t";
+ Pkg.makeEpilogue += "$(RM) " + lldFullLibraryPath + ".a" + target.suffix + "_size.txt\n\n";
+}
Pkg.otherFiles=[
'.settings/org.eclipse.cdt.core.prefs',
'docs',
'lib/release/ti.sdo.edma3.drv.ae64P',
'lib/release/ti.sdo.edma3.drv.ae64Pe',
'lib/release/ti.sdo.edma3.drv.ae674',
+ 'lib/debug/ti.sdo.edma3.drv.ae66',
+ 'lib/debug/ti.sdo.edma3.drv.ae66e',
+ 'lib/release/ti.sdo.edma3.drv.ae66',
+ 'lib/release/ti.sdo.edma3.drv.ae66e',
+ 'lib/release/ti.sdo.edma3.drv.a64P_size.txt',
+ 'lib/release/ti.sdo.edma3.drv.a64Pe_size.txt',
+ 'lib/release/ti.sdo.edma3.drv.ae64P_size.txt',
+ 'lib/release/ti.sdo.edma3.drv.ae64Pe_size.txt',
+ 'lib/release/ti.sdo.edma3.drv.ae66_size.txt',
+ 'lib/release/ti.sdo.edma3.drv.ae66e_size.txt',
'src',
'.cdtproject',
'.project',
index 0f5085ec2b672459ad9c107b804744fa02898a9a..a1ca7abdaa840d4870a2391670649014575b8cbf 100755 (executable)
/* Boards supported */
var boards = [
'evmDA830',
- 'simTCI6498',
+ 'simTCI6608',
+ 'simTCI6616',
+ 'evm6670',
+ 'evm6678',
'evm6748',
'evmOMAPL138',
'simDM8168',
target = "674/";
if (java.lang.String(Program.build.target.suffix).contains('64p'))
target = "64p/";
+ if (java.lang.String(Program.build.target.suffix).contains('66'))
+ target = "66/";
if (java.lang.String(Program.build.target.suffix).contains('a8'))
target = "a8/";
if (java.lang.String(Program.build.target.suffix).contains('m3'))
index 93963284e29eef49cfa3599285278d2d3027289c..456735c0a4503286c9316b813377598cf97b3ca2 100755 (executable)
# Example:
# SRCS_<core/SoC/platform-name> =
# CFLAGS_LOCAL_<core/SoC/platform-name> =
+ifeq ($(CORE),c6xdsp)
SRCS_c6472-evm = sample_c6472_cfg.c sample_c6472_int_reg.c
SRCS_tci6486-evm = sample_tci6486_cfg.c sample_tci6486_int_reg.c
-SRCS_tci6498-sim = sample_tci6498_cfg.c sample_tci6498_int_reg.c
-ifeq ($(CORE),c6xdsp)
+SRCS_tci6608-sim = sample_tci6608_cfg.c sample_tci6608_int_reg.c
+SRCS_tci6616-sim = sample_tci6616_cfg.c sample_tci6616_int_reg.c
+SRCS_c6670-evm = sample_c6670_cfg.c sample_c6670_int_reg.c
+SRCS_c6678-evm = sample_c6678_cfg.c sample_c6678_int_reg.c
SRCS_omapl138-evm = sample_omapl138_cfg.c sample_omapl138_int_reg.c
SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_int_reg.c
else
diff --git a/packages/ti/sdo/edma3/drv/sample/package.bld b/packages/ti/sdo/edma3/drv/sample/package.bld
index 9344fbaa99a65c1608141c89d4c9b22805376dcd..d26e637649b6cb8422df54ea3c90082b6a16f622 100755 (executable)
"src/sample_arm_cs.c",
"src/sample_arm_init.c",
];
+var objListSimTCI6608 = [
+ "src/platforms/sample_tci6608_cfg.c",
+ "src/platforms/sample_tci6608_int_reg.c",
+ "src/sample_cs.c",
+ "src/sample_init.c",
+];
+var objListSimTCI6616 = [
+ "src/platforms/sample_tci6616_cfg.c",
+ "src/platforms/sample_tci6616_int_reg.c",
+ "src/sample_cs.c",
+ "src/sample_init.c",
+];
-var objListSimTCI6498 = [
- "src/platforms/sample_tci6498_cfg.c",
- "src/platforms/sample_tci6498_int_reg.c",
+var objListEVM6670 = [
+ "src/platforms/sample_c6670_cfg.c",
+ "src/platforms/sample_c6670_int_reg.c",
+ "src/sample_cs.c",
+ "src/sample_init.c",
+];
+
+var objListEVM6678 = [
+ "src/platforms/sample_c6678_cfg.c",
+ "src/platforms/sample_c6678_int_reg.c",
"src/sample_cs.c",
"src/sample_init.c",
];
var chipdefines = [
'CHIP_DA830',
- 'SIMTCI6498',
- 'SIMTCI6498',
+ 'SIMTCI6608',
+ 'SIMTCI6608',
+ 'SIMTCI6616',
+ 'SIMTCI6616',
+ 'CHIP_C6670',
+ 'CHIP_C6670',
+ 'CHIP_C6678',
+ 'CHIP_C6678',
'CHIP_C6748',
'CHIP_OMAPL138',
'CHIP_OMAPL138',
platform: 'ti.platforms.evmDA830', targ : 'C674', objList: objListDA830, dir : 'da830-evm/674/'
},
{
- platform: 'ti.platforms.simTCI6498', targ : 'C64P',objList: objListSimTCI6498, dir : 'tci6498-sim/64p/'
+ platform: 'ti.platforms.simTCI6608', targ : 'C66',objList: objListSimTCI6608, dir : 'tci6608-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.simTCI6608', targ : 'C66_big_endian',objList: objListSimTCI6608, dir : 'tci6608-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.simTCI6616', targ : 'C66',objList: objListSimTCI6616, dir : 'tci6616-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.simTCI6616', targ : 'C66_big_endian',objList: objListSimTCI6616, dir : 'tci6616-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.evm6670', targ : 'C66',objList: objListEVM6670, dir : 'c6670-evm/66'
+ },
+ {
+ platform: 'ti.platforms.evm6670', targ : 'C66_big_endian',objList: objListEVM6670, dir : 'c6670-evm/66'
+ },
+ {
+ platform: 'ti.platforms.evm6678', targ : 'C66',objList: objListEVM6678, dir : 'c6678-evm/66'
},
{
- platform: 'ti.platforms.simTCI6498', targ : 'C64P_big_endian',objList: objListSimTCI6498, dir : 'tci6498-sim/64p/'
+ platform: 'ti.platforms.evm6678', targ : 'C66_big_endian',objList: objListEVM6678, dir : 'c6678-evm/66'
},
{
platform: 'ti.platforms.evm6748', targ : 'C674', objList: objListC6748, dir : 'c6748-evm/674/'
'lib/ti814x/release/ti.sdo.edma3.drv.sample.a674',
'lib/ti814x/debug/ti.sdo.edma3.drv.sample.aea8f',
'lib/ti814x/release/ti.sdo.edma3.drv.sample.aea8f',
- 'lib/tci6498/debug/ti.sdo.edma3.drv.sample.a64P',
- 'lib/tci6498/debug/ti.sdo.edma3.drv.sample.a64Pe',
- 'lib/tci6498/release/ti.sdo.edma3.drv.sample.a64P',
- 'lib/tci6498/release/ti.sdo.edma3.drv.sample.a64Pe',
+ 'lib/tci6608/debug/ti.sdo.edma3.drv.sample.ae66',
+ 'lib/tci6608/debug/ti.sdo.edma3.drv.sample.ae66e',
+ 'lib/tci6608/release/ti.sdo.edma3.drv.sample.ae66',
+ 'lib/tci6608/release/ti.sdo.edma3.drv.sample.ae66e',
+ 'lib/tci6616/debug/ti.sdo.edma3.drv.sample.ae66',
+ 'lib/tci6616/debug/ti.sdo.edma3.drv.sample.ae66e',
+ 'lib/tci6616/release/ti.sdo.edma3.drv.sample.ae66',
+ 'lib/tci6616/release/ti.sdo.edma3.drv.sample.ae66e',
+ 'lib/c6670/debug/ti.sdo.edma3.drv.sample.ae66',
+ 'lib/c6670/debug/ti.sdo.edma3.drv.sample.ae66e',
+ 'lib/c6670/release/ti.sdo.edma3.drv.sample.ae66',
+ 'lib/c6670/release/ti.sdo.edma3.drv.sample.ae66e',
+ 'lib/c6678/debug/ti.sdo.edma3.drv.sample.ae66',
+ 'lib/c6678/debug/ti.sdo.edma3.drv.sample.ae66e',
+ 'lib/c6678/release/ti.sdo.edma3.drv.sample.ae66',
+ 'lib/c6678/release/ti.sdo.edma3.drv.sample.ae66e',
'lib/simti816x/debug/ti.sdo.edma3.drv.sample.a674',
'lib/simti816x/release/ti.sdo.edma3.drv.sample.a674',
'lib/evmti816x/debug/ti.sdo.edma3.drv.sample.a674',
'src/platforms/sample_ti814x_int_reg.c',
'src/platforms/sample_ti814x_arm_cfg.c',
'src/platforms/sample_ti814x_arm_int_reg.c',
- 'src/platforms/sample_tci6498_cfg.c',
- 'src/platforms/sample_tci6498_int_reg.c',
+ 'src/platforms/sample_tci6608_cfg.c',
+ 'src/platforms/sample_tci6608_int_reg.c',
+ 'src/platforms/sample_tci6616_cfg.c',
+ 'src/platforms/sample_tci6616_int_reg.c',
+ 'src/platforms/sample_c6670_cfg.c',
+ 'src/platforms/sample_c6670_int_reg.c',
+ 'src/platforms/sample_c6678_cfg.c',
+ 'src/platforms/sample_c6678_int_reg.c',
'src/platforms/sample_ti816x_cfg.c',
'src/platforms/sample_ti816x_int_reg.c',
'src/platforms/sample_c6472_cfg.c',
diff --git a/packages/ti/sdo/edma3/drv/sample/package.xs b/packages/ti/sdo/edma3/drv/sample/package.xs
index bed80ed19e0c1738b2472ec4bec3087ac52584a0..3e5b5b0aaa43d1c69d180c553c28b059b4d35f22 100755 (executable)
/* Boards supported */
var boards = [
'evmDA830',
- 'simTCI6498',
+ 'simTCI6608',
+ 'simTCI6616',
+ 'evm6670',
+ 'evm6678',
'evm6748',
'evmOMAPL138',
'simDM8168',
/* Directories for each platform */
var dir = [
'da830-evm/',
- 'tci6498-sim/',
+ 'tci6608-sim/',
+ 'tci6616-sim/',
+ 'c6670-evm/',
+ 'c6678-evm/',
'c6748-evm/',
'omapl138-evm/',
'ti816x-sim/',
target = "674/";
if (java.lang.String(Program.build.target.suffix).contains('64p'))
target = "64p/";
+ if (java.lang.String(Program.build.target.suffix).contains('66'))
+ target = "66/";
if (java.lang.String(Program.build.target.suffix).contains('a8'))
target = "a8/";
if (java.lang.String(Program.build.target.suffix).contains('m3'))
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6498_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6670_cfg.c
old mode 100755 (executable)
new mode 100644 (file)
similarity index 96%
rename from packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6498_cfg.c
rename to packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6670_cfg.c
index 5fae2c1..a0e30d7
new mode 100644 (file)
similarity index 96%
rename from packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6498_cfg.c
rename to packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6670_cfg.c
index 5fae2c1..a0e30d7
-/*\r
- * sample_tci6498_cfg.c\r
- *\r
- * Platform specific EDMA3 hardware related information like number of transfer\r
- * controllers, various interrupt ids etc. It is used while interrupts\r
- * enabling / disabling. It needs to be ported for different SoCs.\r
- *\r
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
- *\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
- *\r
- * Neither the name of Texas Instruments Incorporated nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
-*/\r
-\r
-#include <ti/sdo/edma3/drv/edma3_drv.h>\r
-\r
-/* Number of EDMA3 controllers present in the system */\r
-#define NUM_EDMA3_INSTANCES 3u\r
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
-\r
-/* Number of DSPs present in the system */\r
-#define NUM_DSPS 4u\r
-//const unsigned int numDsps = NUM_DSPS;\r
-\r
-#define CGEM_REG_START (0x01800000)\r
-\r
-/* Determine the processor id by reading DNUM register. */\r
-unsigned short determineProcId()\r
- {\r
- volatile unsigned int *addr;\r
- unsigned int core_no;\r
-\r
- /* Identify the core number */\r
- addr = (unsigned int *)(CGEM_REG_START+0x40000);\r
- core_no = ((*addr) & 0x000F0000)>>16;\r
-\r
- return core_no;\r
- }\r
-\r
-/** Whether global configuration required for EDMA3 or not.\r
- * This configuration should be done only once for the EDMA3 hardware by\r
- * any one of the masters (i.e. DSPs).\r
- * It can be changed depending on the use-case.\r
- */\r
-unsigned int gblCfgReqdArray [NUM_DSPS] = {\r
- 0, /* DSP#0 is Master, will do the global init */\r
- 1, /* DSP#1 is Slave, will not do the global init */\r
- 1, /* DSP#2 is Slave, will not do the global init */\r
- 1, /* DSP#3 is Slave, will not do the global init */\r
- };\r
-\r
-unsigned short isGblConfigRequired(unsigned int dspNum)\r
- {\r
- return gblCfgReqdArray[dspNum];\r
- }\r
-\r
-/* Semaphore handles */\r
-EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};\r
-\r
-\r
-/* Variable which will be used internally for referring number of Event Queues. */\r
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};\r
-\r
-/* Variable which will be used internally for referring number of TCs. */\r
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};\r
-\r
-/**\r
- * Variable which will be used internally for referring transfer completion\r
- * interrupt. Completion interrupts for all the shadow regions and all the\r
- * EDMA3 controllers are captured since it is a multi-DSP platform.\r
- */\r
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {\r
- {\r
- 38u, 39u, 40u, 41u,\r
- 42u, 43u, 44u, 45u,\r
- },\r
- {\r
- 8u, 9u, 10u, 11u,\r
- 12u, 13u, 14u, 15u,\r
- },\r
- {\r
- 24u, 25u, 26u, 27u,\r
- 28u, 29u, 30u, 31u,\r
- },\r
- };\r
-\r
-/**\r
- * Variable which will be used internally for referring channel controller's\r
- * error interrupt.\r
- */\r
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};\r
-\r
-/**\r
- * Variable which will be used internally for referring transfer controllers'\r
- * error interrupts.\r
- */\r
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {\r
- {\r
- 34u, 35u, 0u, 0u,\r
- 0u, 0u, 0u, 0u,\r
- },\r
- {\r
- 2u, 3u, 4u, 5u,\r
- 0u, 0u, 0u, 0u,\r
- },\r
- {\r
- 18u, 19u, 20u, 21u,\r
- 0u, 0u, 0u, 0u,\r
- },\r
- };\r
-\r
-/* Driver Object Initialization Configuration */\r
-EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
- {\r
- {\r
- /* EDMA3 INSTANCE# 0 */\r
- /** Total number of DMA Channels supported by the EDMA3 Controller */\r
- 16u,\r
- /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
- 8u,\r
- /** Total number of TCCs supported by the EDMA3 Controller */\r
- 16u,\r
- /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
- 128u,\r
- /** Total number of Event Queues in the EDMA3 Controller */\r
- 2u,\r
- /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
- 2u,\r
- /** Number of Regions on this EDMA3 controller */\r
- 8u,\r
-\r
- /**\r
- * \brief Channel mapping existence\r
- * A value of 0 (No channel mapping) implies that there is fixed association\r
- * for a channel number to a parameter entry number or, in other words,\r
- * PaRAM entry n corresponds to channel n.\r
- */\r
- 1u,\r
-\r
- /** Existence of memory protection feature */\r
- 1u,\r
-\r
- /** Global Register Region of CC Registers */\r
- (void *)0x02700000u,\r
- /** Transfer Controller (TC) Registers */\r
- {\r
- (void *)0x02760000u,\r
- (void *)0x02768000u,\r
- (void *)NULL,\r
- (void *)NULL,\r
- (void *)NULL,\r
- (void *)NULL,\r
- (void *)NULL,\r
- (void *)NULL\r
- },\r
- /** Interrupt no. for Transfer Completion */\r
- 38u,\r
- /** Interrupt no. for CC Error */\r
- 32u,\r
- /** Interrupt no. for TCs Error */\r
- {\r
- 34u,\r
- 35u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- },\r
-\r
- /**\r
- * \brief EDMA3 TC priority setting\r
- *\r
- * User can program the priority of the Event Queues\r
- * at a system-wide level. This means that the user can set the\r
- * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
- * relative to IO initiated by the other bus masters on the\r
- * device (ARM, DSP, USB, etc)\r
- */\r
- {\r
- 0u,\r
- 1u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
- },\r
- /**\r
- * \brief To Configure the Threshold level of number of events\r
- * that can be queued up in the Event queues. EDMA3CC error register\r
- * (CCERR) will indicate whether or not at any instant of time the\r
- * number of events queued up in any of the event queues exceeds\r
- * or equals the threshold/watermark value that is set\r
- * in the queue watermark threshold register (QWMTHRA).\r
- */\r
- {\r
- 16u,\r
- 16u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
- },\r
-\r
- /**\r
- * \brief To Configure the Default Burst Size (DBS) of TCs.\r
- * An optimally-sized command is defined by the transfer controller\r
- * default burst size (DBS). Different TCs can have different\r
- * DBS values. It is defined in Bytes.\r
- */\r
- {\r
- 128u,\r
- 128u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
- },\r
-\r
- /**\r
- * \brief Mapping from each DMA channel to a Parameter RAM set,\r
- * if it exists, otherwise of no use.\r
- */\r
- {\r
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
- /* DMA channels 16-63 DOES NOT exist */\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS\r
- },\r
-\r
- /**\r
- * \brief Mapping from each DMA channel to a TCC. This specific\r
- * TCC code will be returned when the transfer is completed\r
- * on the mapped channel.\r
- */\r
- {\r
- 0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
- 4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
- 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
- 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
- /* DMA channels 16-63 DOES NOT exist */\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC\r
- },\r
-\r
- /**\r
- * \brief Mapping of DMA channels to Hardware Events from\r
- * various peripherals, which use EDMA for data transfer.\r
- * All channels need not be mapped, some can be free also.\r
- */\r
- {\r
- 0x00003333u,\r
- 0x00000000u\r
- }\r
- },\r
-\r
- {\r
- /* EDMA3 INSTANCE# 1 */\r
- /** Total number of DMA Channels supported by the EDMA3 Controller */\r
- 64u,\r
- /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
- 8u,\r
- /** Total number of TCCs supported by the EDMA3 Controller */\r
- 64u,\r
- /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
- 512u,\r
- /** Total number of Event Queues in the EDMA3 Controller */\r
- 4u,\r
- /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
- 4u,\r
- /** Number of Regions on this EDMA3 controller */\r
- 8u,\r
-\r
- /**\r
- * \brief Channel mapping existence\r
- * A value of 0 (No channel mapping) implies that there is fixed association\r
- * for a channel number to a parameter entry number or, in other words,\r
- * PaRAM entry n corresponds to channel n.\r
- */\r
- 1u,\r
-\r
- /** Existence of memory protection feature */\r
- 1u,\r
-\r
- /** Global Register Region of CC Registers */\r
- (void *)0x02720000u,\r
- /** Transfer Controller (TC) Registers */\r
- {\r
- (void *)0x02770000u,\r
- (void *)0x02778000u,\r
- (void *)0x02780000u,\r
- (void *)0x02788000u,\r
- (void *)NULL,\r
- (void *)NULL,\r
- (void *)NULL,\r
- (void *)NULL\r
- },\r
- /** Interrupt no. for Transfer Completion */\r
- 8u,\r
- /** Interrupt no. for CC Error */\r
- 0u,\r
- /** Interrupt no. for TCs Error */\r
- {\r
- 2u,\r
- 3u,\r
- 4u,\r
- 5u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- },\r
-\r
- /**\r
- * \brief EDMA3 TC priority setting\r
- *\r
- * User can program the priority of the Event Queues\r
- * at a system-wide level. This means that the user can set the\r
- * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
- * relative to IO initiated by the other bus masters on the\r
- * device (ARM, DSP, USB, etc)\r
- */\r
- {\r
- 0u,\r
- 1u,\r
- 2u,\r
- 3u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
- },\r
- /**\r
- * \brief To Configure the Threshold level of number of events\r
- * that can be queued up in the Event queues. EDMA3CC error register\r
- * (CCERR) will indicate whether or not at any instant of time the\r
- * number of events queued up in any of the event queues exceeds\r
- * or equals the threshold/watermark value that is set\r
- * in the queue watermark threshold register (QWMTHRA).\r
- */\r
- {\r
- 16u,\r
- 16u,\r
- 16u,\r
- 16u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
- },\r
-\r
- /**\r
- * \brief To Configure the Default Burst Size (DBS) of TCs.\r
- * An optimally-sized command is defined by the transfer controller\r
- * default burst size (DBS). Different TCs can have different\r
- * DBS values. It is defined in Bytes.\r
- */\r
- {\r
- 64u,\r
- 64u,\r
- 64u,\r
- 64u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
- },\r
-\r
- /**\r
- * \brief Mapping from each DMA channel to a Parameter RAM set,\r
- * if it exists, otherwise of no use.\r
- */\r
- {\r
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
- 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
- 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
- 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
- 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
- },\r
-\r
- /**\r
- * \brief Mapping from each DMA channel to a TCC. This specific\r
- * TCC code will be returned when the transfer is completed\r
- * on the mapped channel.\r
- */\r
- {\r
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
- 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
- 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
- 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
- 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
- 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP\r
- },\r
-\r
- /**\r
- * \brief Mapping of DMA channels to Hardware Events from\r
- * various peripherals, which use EDMA for data transfer.\r
- * All channels need not be mapped, some can be free also.\r
- */\r
- {\r
- 0x3FFF3FFFu,\r
- 0x3FFF3FFFu\r
- }\r
- },\r
-\r
- {\r
- /* EDMA3 INSTANCE# 2 */\r
- /** Total number of DMA Channels supported by the EDMA3 Controller */\r
- 64u,\r
- /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
- 8u,\r
- /** Total number of TCCs supported by the EDMA3 Controller */\r
- 64u,\r
- /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
- 512u,\r
- /** Total number of Event Queues in the EDMA3 Controller */\r
- 4u,\r
- /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
- 4u,\r
- /** Number of Regions on this EDMA3 controller */\r
- 8u,\r
-\r
- /**\r
- * \brief Channel mapping existence\r
- * A value of 0 (No channel mapping) implies that there is fixed association\r
- * for a channel number to a parameter entry number or, in other words,\r
- * PaRAM entry n corresponds to channel n.\r
- */\r
- 1u,\r
-\r
- /** Existence of memory protection feature */\r
- 1u,\r
-\r
- /** Global Register Region of CC Registers */\r
- (void *)0x02740000u,\r
- /** Transfer Controller (TC) Registers */\r
- {\r
- (void *)0x02790000u,\r
- (void *)0x02798000u,\r
- (void *)0x027A0000u,\r
- (void *)0x027A8000u,\r
- (void *)NULL,\r
- (void *)NULL,\r
- (void *)NULL,\r
- (void *)NULL\r
- },\r
- /** Interrupt no. for Transfer Completion */\r
- 24u,\r
- /** Interrupt no. for CC Error */\r
- 16u,\r
- /** Interrupt no. for TCs Error */\r
- {\r
- 18u,\r
- 19u,\r
- 20u,\r
- 21u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- },\r
-\r
- /**\r
- * \brief EDMA3 TC priority setting\r
- *\r
- * User can program the priority of the Event Queues\r
- * at a system-wide level. This means that the user can set the\r
- * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
- * relative to IO initiated by the other bus masters on the\r
- * device (ARM, DSP, USB, etc)\r
- */\r
- {\r
- 0u,\r
- 1u,\r
- 2u,\r
- 3u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
- },\r
- /**\r
- * \brief To Configure the Threshold level of number of events\r
- * that can be queued up in the Event queues. EDMA3CC error register\r
- * (CCERR) will indicate whether or not at any instant of time the\r
- * number of events queued up in any of the event queues exceeds\r
- * or equals the threshold/watermark value that is set\r
- * in the queue watermark threshold register (QWMTHRA).\r
- */\r
- {\r
- 16u,\r
- 16u,\r
- 16u,\r
- 16u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
- },\r
-\r
- /**\r
- * \brief To Configure the Default Burst Size (DBS) of TCs.\r
- * An optimally-sized command is defined by the transfer controller\r
- * default burst size (DBS). Different TCs can have different\r
- * DBS values. It is defined in Bytes.\r
- */\r
- {\r
- 64u,\r
- 64u,\r
- 64u,\r
- 64u,\r
- 0u,\r
- 0u,\r
- 0u,\r
- 0u\r
- },\r
-\r
- /**\r
- * \brief Mapping from each DMA channel to a Parameter RAM set,\r
- * if it exists, otherwise of no use.\r
- */\r
- {\r
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
- 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
- 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
- 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
- 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
- },\r
-\r
- /**\r
- * \brief Mapping from each DMA channel to a TCC. This specific\r
- * TCC code will be returned when the transfer is completed\r
- * on the mapped channel.\r
- */\r
- {\r
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
- 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
- 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
- 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
- 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
- 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
- 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP\r
- },\r
-\r
- /**\r
- * \brief Mapping of DMA channels to Hardware Events from\r
- * various peripherals, which use EDMA for data transfer.\r
- * All channels need not be mapped, some can be free also.\r
- */\r
- {\r
- 0x3FFF3FFFu,\r
- 0x3FFF3FFFu\r
- }\r
- },\r
- };\r
-\r
-EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
- {\r
- /* EDMA3 INSTANCE# 0 */\r
- {\r
- /* Resources owned/reserved by region 0 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x0000000Fu, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000003u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x0000000Fu, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 */\r
- {0x00000003u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 */\r
- {0x00000003u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 1 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x000000F0u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x0000000Cu},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x000000F0u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000030u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000030u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 2 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000F00u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000030u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000F00u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000300u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000300u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 3 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x0000F000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x000000C0u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x0000F000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00003000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00003000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 4 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 5 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 6 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 7 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
- },\r
-\r
- /* EDMA3 INSTANCE# 1 */\r
- {\r
- /* Resources owned/reserved by region 0 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x0000FFFFu, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000003u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x0000FFFFu, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00003FFFu, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00003FFFu, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 1 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0xFFFF0000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x0000000Cu},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0xFFFF0000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x3FFF0000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x3FFF0000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 2 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x0000FFFFu},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000030u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x0000FFFFu},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00003FFFu},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00003FFFu},\r
- },\r
-\r
- /* Resources owned/reserved by region 3 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0xFFFF0000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x000000C0u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0xFFFF0000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x3FFF0000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x3FFF0000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 4 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 5 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 6 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 7 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
- },\r
-\r
- /* EDMA3 INSTANCE# 2 */\r
- {\r
- /* Resources owned/reserved by region 0 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x0000FFFFu, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000003u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x0000FFFFu, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00003FFFu, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00003FFFu, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 1 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0xFFFF0000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x0000000Cu},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0xFFFF0000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x3FFF0000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x3FFF0000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 2 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x0000FFFFu},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000030u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x0000FFFFu},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00003FFFu},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00003FFFu},\r
- },\r
-\r
- /* Resources owned/reserved by region 3 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0xFFFF0000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x000000C0u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0xFFFF0000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x3FFF0000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x3FFF0000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 4 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 5 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 6 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
-\r
- /* Resources owned/reserved by region 7 */\r
- {\r
- /* ownPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* ownDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* ownQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* ownTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdPaRAMSets */\r
- /* 31 0 63 32 95 64 127 96 */\r
- {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 159 128 191 160 223 192 255 224 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 287 256 319 288 351 320 383 352 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
- /* 415 384 447 416 479 448 511 480 */\r
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
-\r
- /* resvdDmaChannels */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
-\r
- /* resvdQdmaChannels */\r
- /* 31 0 */\r
- {0x00000000u},\r
-\r
- /* resvdTccs */\r
- /* 31 0 63 32 */\r
- {0x00000000u, 0x00000000u},\r
- },\r
- },\r
- };\r
-\r
-/* End of File */\r
+/*
+ * sample_c6670_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 3u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 4u
+//const unsigned int numDsps = NUM_DSPS;
+
+#define CGEM_REG_START (0x01800000)
+
+
+extern cregister volatile unsigned int DNUM;
+
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
+
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+ {
+ return (addr); /* The address is already a global address */
+ }
+
+ return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+/** Whether global configuration required for EDMA3 or not.
+ * This configuration should be done only once for the EDMA3 hardware by
+ * any one of the masters (i.e. DSPs).
+ * It can be changed depending on the use-case.
+ */
+unsigned int gblCfgReqdArray [NUM_DSPS] = {
+ 0, /* DSP#0 is Master, will do the global init */
+ 1, /* DSP#1 is Slave, will not do the global init */
+ 1, /* DSP#2 is Slave, will not do the global init */
+ 1, /* DSP#3 is Slave, will not do the global init */
+ };
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ return gblCfgReqdArray[dspNum];
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
+
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt. Completion interrupts for all the shadow regions and all the
+ * EDMA3 controllers are captured since it is a multi-DSP platform.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ 38u, 39u, 40u, 41u,
+ 42u, 43u, 44u, 45u,
+ },
+ {
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ },
+ {
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
+ {
+ 34u, 35u, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 2u, 3u, 4u, 5u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 18u, 19u, 20u, 21u,
+ 0u, 0u, 0u, 0u,
+ },
+ };
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00003333u,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 64u,
+ 64u,
+ 64u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x3FFF3FFFu,
+ 0x3FFF3FFFu
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 64u,
+ 64u,
+ 64u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x3FFF3FFFu,
+ 0x3FFF3FFFu
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000000Fu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000003u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000000Fu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 */
+ {0x00000003u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 */
+ {0x00000003u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x000000F0u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Cu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x000000F0u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000F00u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000030u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000F00u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000F000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000F000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000003u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Cu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000030u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000003u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Cu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000030u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
+
+/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6498_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6670_int_reg.c
old mode 100755 (executable)
new mode 100644 (file)
similarity index 96%
rename from packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6498_int_reg.c
rename to packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6670_int_reg.c
index d7eb17d..51c4a6c
new mode 100644 (file)
similarity index 96%
rename from packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6498_int_reg.c
rename to packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6670_int_reg.c
index d7eb17d..51c4a6c
/*
- * sample_tci6498_int_reg.c
+ * sample_c6670_int_reg.c
*
* Platform specific interrupt registration and un-registration routines.
*
/* Host interrupts for transfer completion */
//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
unsigned int ccXferHostInt[3][4] = {
- {0u, 16u, 32u, 48u},
- {1u, 17u, 33u, 49u},
- {2u, 18u, 34u, 50u},
+ {8u, 24u, 40u, 56u},
+ {9u, 25u, 41u, 57u},
+ {10u, 26u, 42u, 58u},
};
unsigned int edma3ErrHostInt[3][4] = {
- {3u, 19u, 35u, 51u},
- {4u, 20u, 36u, 52u},
- {5u, 21u, 37u, 53u},
+ {11u, 27u, 43u, 59u},
+ {12u, 28u, 44u, 60u},
+ {13u, 29u, 45u, 61u},
};
Hwi_restore(cookie);
}
-
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6678_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6678_cfg.c
--- /dev/null
@@ -0,0 +1,1794 @@
+/*
+ * sample_tci6678_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 3u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 8u
+//const unsigned int numDsps = NUM_DSPS;
+
+#define CGEM_REG_START (0x01800000)
+
+extern cregister volatile unsigned int DNUM;
+
+
+
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+ {
+ return (addr); /* The address is already a global address */
+ }
+
+ return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+/** Whether global configuration required for EDMA3 or not.
+ * This configuration should be done only once for the EDMA3 hardware by
+ * any one of the masters (i.e. DSPs).
+ * It can be changed depending on the use-case.
+ */
+unsigned int gblCfgReqdArray [NUM_DSPS] = {
+ 0, /* DSP#0 is Master, will do the global init */
+ 1, /* DSP#1 is Slave, will not do the global init */
+ 1, /* DSP#2 is Slave, will not do the global init */
+ 1, /* DSP#3 is Slave, will not do the global init */
+ 1, /* DSP#4 is Slave, will not do the global init */
+ 1, /* DSP#5 is Slave, will not do the global init */
+ 1, /* DSP#6 is Slave, will not do the global init */
+ 1, /* DSP#7 is Slave, will not do the global init */
+ };
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ return gblCfgReqdArray[dspNum];
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
+
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt. Completion interrupts for all the shadow regions and all the
+ * EDMA3 controllers are captured since it is a multi-DSP platform.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ 38u, 39u, 40u, 41u,
+ 42u, 43u, 44u, 45u,
+ },
+ {
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ },
+ {
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
+ {
+ 34u, 35u, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 2u, 3u, 4u, 5u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 18u, 19u, 20u, 21u,
+ 0u, 0u, 0u, 0u,
+ },
+ };
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 128u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFFFF0000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 64u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFFFF0000u
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x3FFF0003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000003u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000003u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xC000000Cu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000000Cu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000000Cu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000030u, 0x03FFF000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x000000C0u, 0xFC000000u, 0x000000FFu, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x000000C0u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x000000C0u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000300u, 0x00000000u, 0x003FFF00u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000C00u, 0x00000000u, 0xFFC00000u, 0x0000000Fu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000C00u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000C00u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003000u, 0x00000000u, 0x00000000u, 0x0003FFF0u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000C000u, 0x00000000u, 0x00000000u, 0xFFFC0000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000C000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000C000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00030000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x000C0000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00300000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00C00000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x03000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0C000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x30000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xC0000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00030000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x000C0000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00300000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00C00000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x03000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0C000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x30000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xC0000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+ },
+ };
+
+/* End of File */
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6678_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6678_int_reg.c
--- /dev/null
@@ -0,0 +1,165 @@
+/*
+ * sample_c6678_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+unsigned int hwiInterrupt = 8;
+
+/* Host interrupts for transfer completion */
+//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
+unsigned int ccXferHostInt[3][8] = {
+ {2u, 10u, 18u, 26u, 2u, 10u, 18u, 26u},
+ {3u, 11u, 19u, 27u, 3u, 11u, 19u, 27u},
+ {4u, 12u, 20u, 28u, 4u, 12u, 20u, 28u},
+ };
+unsigned int edma3ErrHostInt[3][8] = {
+ {5u, 13u, 21u, 29u, 5u, 13u, 21u, 29u},
+ {6u, 14u, 22u, 30u, 6u, 14u, 22u, 30u},
+ {7u, 15u, 23u, 31u, 7u, 15u, 23u, 31u},
+ };
+
+
+extern unsigned int dsp_num;
+
+/** To Register the ISRs with the underlying OS, if required */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ unsigned int numTc = 0;
+ UInt cpIntcId= 0;
+ if (dsp_num > 3)
+ {
+ cpIntcId = 1;
+ }
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+ lisrEdma3ComplHandler0,
+ edma3Id,
+ TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, ccXferCompInt[edma3Id][dsp_num],
+ ccXferHostInt[edma3Id][dsp_num]);
+ CpIntc_enableHostInt(cpIntcId, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ ccXferHostInt[edma3Id][dsp_num], TRUE);
+
+ /* CC Error ISR */
+ CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, ccErrorInt[edma3Id],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ /* TC Error ISR */
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
+ (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, tcErrorInt[edma3Id][numTc],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ numTc++;
+ }
+ /* Enable the host interrupt which is common for both CC and TC error */
+ CpIntc_enableHostInt(cpIntcId, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ edma3ErrHostInt[edma3Id][dsp_num], TRUE);
+
+ Hwi_enableInterrupt(hwiInterrupt);
+
+ /* enable the 'global' switch */
+ CpIntc_enableAllHostInts(cpIntcId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ UInt cpIntcId= 0;
+ if (dsp_num > 3)
+ {
+ cpIntcId = 1;
+ }
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_disableHostInt(cpIntcId, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* CC/TC Error ISR */
+ CpIntc_disableHostInt(cpIntcId, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6608_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6608_cfg.c
--- /dev/null
@@ -0,0 +1,1794 @@
+/*
+ * sample_tci6608_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 3u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 8u
+//const unsigned int numDsps = NUM_DSPS;
+
+#define CGEM_REG_START (0x01800000)
+
+extern cregister volatile unsigned int DNUM;
+
+
+
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+ {
+ return (addr); /* The address is already a global address */
+ }
+
+ return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+/** Whether global configuration required for EDMA3 or not.
+ * This configuration should be done only once for the EDMA3 hardware by
+ * any one of the masters (i.e. DSPs).
+ * It can be changed depending on the use-case.
+ */
+unsigned int gblCfgReqdArray [NUM_DSPS] = {
+ 0, /* DSP#0 is Master, will do the global init */
+ 1, /* DSP#1 is Slave, will not do the global init */
+ 1, /* DSP#2 is Slave, will not do the global init */
+ 1, /* DSP#3 is Slave, will not do the global init */
+ 1, /* DSP#4 is Slave, will not do the global init */
+ 1, /* DSP#5 is Slave, will not do the global init */
+ 1, /* DSP#6 is Slave, will not do the global init */
+ 1, /* DSP#7 is Slave, will not do the global init */
+ };
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ return gblCfgReqdArray[dspNum];
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
+
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt. Completion interrupts for all the shadow regions and all the
+ * EDMA3 controllers are captured since it is a multi-DSP platform.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ 38u, 39u, 40u, 41u,
+ 42u, 43u, 44u, 45u,
+ },
+ {
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ },
+ {
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
+ {
+ 34u, 35u, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 2u, 3u, 4u, 5u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 18u, 19u, 20u, 21u,
+ 0u, 0u, 0u, 0u,
+ },
+ };
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 128u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFFFF0000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 64u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFFFF0000u
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x3FFF0003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000003u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000003u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xC000000Cu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000000Cu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000000Cu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000030u, 0x03FFF000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x000000C0u, 0xFC000000u, 0x000000FFu, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x000000C0u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x000000C0u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000300u, 0x00000000u, 0x003FFF00u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000C00u, 0x00000000u, 0xFFC00000u, 0x0000000Fu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000C00u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000C00u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003000u, 0x00000000u, 0x00000000u, 0x0003FFF0u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000C000u, 0x00000000u, 0x00000000u, 0xFFFC0000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000C000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000C000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00030000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x000C0000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00300000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00C00000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x03000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0C000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x30000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xC0000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00030000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x000C0000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00300000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00C00000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x03000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0C000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x30000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xC0000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+ },
+ };
+
+/* End of File */
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6608_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6608_int_reg.c
--- /dev/null
@@ -0,0 +1,165 @@
+/*
+ * sample_tci6608_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+unsigned int hwiInterrupt = 8;
+
+/* Host interrupts for transfer completion */
+//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
+unsigned int ccXferHostInt[3][8] = {
+ {2u, 10u, 18u, 26u, 2u, 10u, 18u, 26u},
+ {3u, 11u, 19u, 27u, 3u, 11u, 19u, 27u},
+ {4u, 12u, 20u, 28u, 4u, 12u, 20u, 28u},
+ };
+unsigned int edma3ErrHostInt[3][8] = {
+ {5u, 13u, 21u, 29u, 5u, 13u, 21u, 29u},
+ {6u, 14u, 22u, 30u, 6u, 14u, 22u, 30u},
+ {7u, 15u, 23u, 31u, 7u, 15u, 23u, 31u},
+ };
+
+
+extern unsigned int dsp_num;
+
+/** To Register the ISRs with the underlying OS, if required */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ unsigned int numTc = 0;
+ UInt cpIntcId= 0;
+ if (dsp_num > 3)
+ {
+ cpIntcId = 1;
+ }
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+ lisrEdma3ComplHandler0,
+ edma3Id,
+ TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, ccXferCompInt[edma3Id][dsp_num],
+ ccXferHostInt[edma3Id][dsp_num]);
+ CpIntc_enableHostInt(cpIntcId, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ ccXferHostInt[edma3Id][dsp_num], TRUE);
+
+ /* CC Error ISR */
+ CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, ccErrorInt[edma3Id],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ /* TC Error ISR */
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
+ (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, tcErrorInt[edma3Id][numTc],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ numTc++;
+ }
+ /* Enable the host interrupt which is common for both CC and TC error */
+ CpIntc_enableHostInt(cpIntcId, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ edma3ErrHostInt[edma3Id][dsp_num], TRUE);
+
+ Hwi_enableInterrupt(hwiInterrupt);
+
+ /* enable the 'global' switch */
+ CpIntc_enableAllHostInts(cpIntcId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ UInt cpIntcId= 0;
+ if (dsp_num > 3)
+ {
+ cpIntcId = 1;
+ }
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_disableHostInt(cpIntcId, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* CC/TC Error ISR */
+ CpIntc_disableHostInt(cpIntcId, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6498_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6616_cfg.c
old mode 100755 (executable)
new mode 100644 (file)
similarity index 92%
rename from packages/ti/sdo/edma3/rm/src/configs/edma3_tci6498_cfg.c
rename to packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6616_cfg.c
index e057841..51e1ad7
new mode 100644 (file)
similarity index 92%
rename from packages/ti/sdo/edma3/rm/src/configs/edma3_tci6498_cfg.c
rename to packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6616_cfg.c
index e057841..51e1ad7
/*
- * edma3_tci6498_cfg.c
+ * sample_tci616_cfg.c
*
- * EDMA3 Resource Manager Adaptation Configuration File (SoC Specific).
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
*
* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
*
#include <ti/sdo/edma3/rm/edma3_rm.h>
+/* Number of EDMA3 controllers present in the system */
#define NUM_EDMA3_INSTANCES 3u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 4u
+//const unsigned int numDsps = NUM_DSPS;
+
+#define CGEM_REG_START (0x01800000)
+
+
+extern cregister volatile unsigned int DNUM;
+
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
+
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+ {
+ return (addr); /* The address is already a global address */
+ }
+
+ return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+/** Whether global configuration required for EDMA3 or not.
+ * This configuration should be done only once for the EDMA3 hardware by
+ * any one of the masters (i.e. DSPs).
+ * It can be changed depending on the use-case.
+ */
+unsigned int gblCfgReqdArray [NUM_DSPS] = {
+ 0, /* DSP#0 is Master, will do the global init */
+ 1, /* DSP#1 is Slave, will not do the global init */
+ 1, /* DSP#2 is Slave, will not do the global init */
+ 1, /* DSP#3 is Slave, will not do the global init */
+ };
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ return gblCfgReqdArray[dspNum];
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
+
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt. Completion interrupts for all the shadow regions and all the
+ * EDMA3 controllers are captured since it is a multi-DSP platform.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ 38u, 39u, 40u, 41u,
+ 42u, 43u, 44u, 45u,
+ },
+ {
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ },
+ {
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
+ {
+ 34u, 35u, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 2u, 3u, 4u, 5u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 18u, 19u, 20u, 21u,
+ 0u, 0u, 0u, 0u,
+ },
+ };
/* Driver Object Initialization Configuration */
-EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
{
{
/* EDMA3 INSTANCE# 0 */
},
};
-EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
/* EDMA3 INSTANCE# 0 */
{
@@ -1109,7 +1219,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1156,7 +1266,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1203,7 +1313,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
@@ -1250,7 +1360,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
{
/* ownPaRAMSets */
/* 31 0 63 32 95 64 127 96 */
- {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 159 128 191 160 223 192 255 224 */
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
/* 287 256 319 288 351 320 383 352 */
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6616_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6616_int_reg.c
--- /dev/null
@@ -0,0 +1,157 @@
+/*
+ * sample_tci6616_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+unsigned int hwiInterrupt = 8;
+
+/* Host interrupts for transfer completion */
+//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
+unsigned int ccXferHostInt[3][4] = {
+ {8u, 24u, 40u, 56u},
+ {9u, 25u, 41u, 57u},
+ {10u, 26u, 42u, 58u},
+ };
+unsigned int edma3ErrHostInt[3][4] = {
+ {11u, 27u, 43u, 59u},
+ {12u, 28u, 44u, 60u},
+ {13u, 29u, 45u, 61u},
+ };
+
+
+extern unsigned int dsp_num;
+
+/** To Register the ISRs with the underlying OS, if required */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ unsigned int numTc = 0;
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+ lisrEdma3ComplHandler0,
+ edma3Id,
+ TRUE);
+ CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num],
+ ccXferHostInt[edma3Id][dsp_num]);
+ CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ ccXferHostInt[edma3Id][dsp_num], TRUE);
+ EventCombiner_enableEvent(eventId);
+
+ /* CC Error ISR */
+ CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(0, ccErrorInt[edma3Id],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ /* TC Error ISR */
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
+ (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(0, tcErrorInt[edma3Id][numTc],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ numTc++;
+ }
+ /* Enable the host interrupt which is common for both CC and TC error */
+ CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ edma3ErrHostInt[edma3Id][dsp_num], TRUE);
+ EventCombiner_enableEvent(eventId);
+
+ Hwi_enableInterrupt(hwiInterrupt);
+
+ /* enable the 'global' switch */
+ CpIntc_enableAllHostInts(0);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_disableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* CC/TC Error ISR */
+ CpIntc_disableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
index f2b4c1312ec621d5d8cd90ea2007378656120f9d..45a20e8741f649913e2ef79054ae5c663ba92fbc 100644 (file)
# CFLAGS_LOCAL_<core/SoC/platform-name> =
SRCS_c6472-evm = edma3_c6472_cfg.c
SRCS_tci6486-evm = edma3_tci6486_cfg.c
-SRCS_tci6498-sim = edma3_tci6498_cfg.c
+SRCS_tci6608-sim = edma3_tci6608_cfg.c
+SRCS_tci6616-sim = edma3_tci6616_cfg.c
+SRCS_c6670-evm = edma3_c6670_cfg.c
+SRCS_c6678-evm = edma3_c6678_cfg.c
SRCS_omapl138-evm = edma3_omapl138_cfg.c
SRCS_c6748-evm = edma3_c6748_cfg.c
SRCS_da830-evm = edma3_da830_cfg.c
index b86ec64946b1fad65db7c485867fc3f34d67f5e3..7498201b74c5c0d52557427f7560c5fa19ac31c3 100755 (executable)
"src/edma3_rm_gbl_data.c",
];
-var objListSimTCI6498 = [
+var objListC6748 = [
/* The configuration file. */
- "src/configs/edma3_tci6498_cfg.c",
+ "src/configs/edma3_c6748_cfg.c",
/* Common file. */
"src/edma3resmgr.c",
/* File defining internal data structures. */
"src/edma3_rm_gbl_data.c",
];
-var objListC6748 = [
+var objListOMAPL138 = [
/* The configuration file. */
- "src/configs/edma3_c6748_cfg.c",
+ "src/configs/edma3_omapl138_cfg.c",
/* Common file. */
"src/edma3resmgr.c",
/* File defining internal data structures. */
"src/edma3_rm_gbl_data.c",
];
-var objListOMAPL138 = [
+var objListSimTCI6608 = [
/* The configuration file. */
- "src/configs/edma3_omapl138_cfg.c",
+ "src/configs/edma3_tci6608_cfg.c",
+ /* Common file. */
+ "src/edma3resmgr.c",
+ /* File defining internal data structures. */
+ "src/edma3_rm_gbl_data.c",
+];
+
+var objListSimTCI6616 = [
+ /* The configuration file. */
+ "src/configs/edma3_tci6616_cfg.c",
+ /* Common file. */
+ "src/edma3resmgr.c",
+ /* File defining internal data structures. */
+ "src/edma3_rm_gbl_data.c",
+];
+
+var objListEVM6670 = [
+ /* The configuration file. */
+ "src/configs/edma3_c6670_cfg.c",
+ /* Common file. */
+ "src/edma3resmgr.c",
+ /* File defining internal data structures. */
+ "src/edma3_rm_gbl_data.c",
+];
+
+var objListEVM6678 = [
+ /* The configuration file. */
+ "src/configs/edma3_c6678_cfg.c",
/* Common file. */
"src/edma3resmgr.c",
/* File defining internal data structures. */
platform: 'ti.platforms.evmDA830', targ : 'C674', objList: objListDA830, dir : 'da830-evm/674/'
},
{
- platform: 'ti.platforms.simTCI6498', targ : 'C64P',objList: objListSimTCI6498, dir : 'tci6498-sim/64p/'
+ platform: 'ti.platforms.simTCI6608', targ : 'C66',objList: objListSimTCI6608, dir : 'tci6608-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.simTCI6608', targ : 'C66_big_endian',objList: objListSimTCI6608, dir : 'tci6608-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.simTCI6616', targ : 'C66',objList: objListSimTCI6616, dir : 'tci6616-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.simTCI6616', targ : 'C66_big_endian',objList: objListSimTCI6616, dir : 'tci6616-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.evm6670', targ : 'C66',objList: objListEVM6670, dir : 'c6670-evm/66/'
+ },
+ {
+ platform: 'ti.platforms.evm6670', targ : 'C66_big_endian',objList: objListEVM6670, dir : 'c6670-evm/66/'
+ },
+ {
+ platform: 'ti.platforms.evm6678', targ : 'C66',objList: objListEVM6678, dir : 'c6678-evm/66/'
},
{
- platform: 'ti.platforms.simTCI6498', targ : 'C64P_big_endian',objList: objListSimTCI6498, dir : 'tci6498-sim/64p/'
+ platform: 'ti.platforms.evm6678', targ : 'C66_big_endian',objList: objListEVM6678, dir : 'c6678-evm/66/'
},
{
platform: 'ti.platforms.evm6748', targ : 'C674', objList: objListC6748, dir : 'c6748-evm/674/'
'C674',
'Arm9',
'A8F',
+ 'C66',
+ 'C66_big_endian',
];
/* Directories for each target */
'674/',
'arm9/',
'a8/',
+ '66/',
+ '66/',
];
for each (var targ in Build.targets)
'lib/ti814x/release/ti.sdo.edma3.rm.a674',
'lib/ti814x/debug/ti.sdo.edma3.rm.aea8f',
'lib/ti814x/release/ti.sdo.edma3.rm.aea8f',
- 'lib/tci6498/debug/ti.sdo.edma3.rm.a64P',
- 'lib/tci6498/debug/ti.sdo.edma3.rm.a64Pe',
- 'lib/tci6498/release/ti.sdo.edma3.rm.a64P',
- 'lib/tci6498/release/ti.sdo.edma3.rm.a64Pe',
+ 'lib/tci6608/debug/ti.sdo.edma3.rm.ae66',
+ 'lib/tci6608/debug/ti.sdo.edma3.rm.ae66e',
+ 'lib/tci6608/release/ti.sdo.edma3.rm.ae66',
+ 'lib/tci6608/release/ti.sdo.edma3.rm.ae66e',
+ 'lib/tci6616/debug/ti.sdo.edma3.rm.ae66',
+ 'lib/tci6616/debug/ti.sdo.edma3.rm.ae66e',
+ 'lib/tci6616/release/ti.sdo.edma3.rm.ae66',
+ 'lib/tci6616/release/ti.sdo.edma3.rm.ae66e',
+ 'lib/c6670/debug/ti.sdo.edma3.rm.ae66',
+ 'lib/c6670/debug/ti.sdo.edma3.rm.ae66e',
+ 'lib/c6670/release/ti.sdo.edma3.rm.ae66',
+ 'lib/c6670/release/ti.sdo.edma3.rm.ae66e',
+ 'lib/c6678/debug/ti.sdo.edma3.rm.ae66',
+ 'lib/c6678/debug/ti.sdo.edma3.rm.ae66e',
+ 'lib/c6678/release/ti.sdo.edma3.rm.ae66',
+ 'lib/c6678/release/ti.sdo.edma3.rm.ae66e',
'lib/simti816x/debug/ti.sdo.edma3.rm.a674',
'lib/simti816x/release/ti.sdo.edma3.rm.a674',
'lib/evmti816x/debug/ti.sdo.edma3.rm.a674',
index d0b44b705bcd446e921c80b305982beb919ae402..839049dcef41f25fd9eab0cbab7f2c51929c0fe0 100755 (executable)
/* Boards supported */
var boards = [
'evmDA830',
- 'simTCI6498',
+ 'simTCI6608',
+ 'simTCI6616',
+ 'evm6670',
+ 'evm6678',
'evm6748',
'evmOMAPL138',
'simDM8168',
/* Directories for each platform */
var dir = [
'da830-evm/',
- 'tci6498-sim/',
+ 'tci6608-sim/',
+ 'tci6616-sim/',
+ 'c6670-evm/',
+ 'c6678-evm/',
'c6748-evm/',
'omapl138-evm/',
'ti816x-sim/',
target = "674/";
if (java.lang.String(Program.build.target.suffix).contains('64p'))
target = "64p/";
+ if (java.lang.String(Program.build.target.suffix).contains('66'))
+ target = "66/";
if (java.lang.String(Program.build.target.suffix).contains('a8'))
target = "a8/";
if (java.lang.String(Program.build.target.suffix).contains('m3'))
target = "674/";
if (java.lang.String(Program.build.target.suffix).contains('64p'))
target = "64p/";
+ if (java.lang.String(Program.build.target.suffix).contains('66'))
+ target = "66/";
if (java.lang.String(Program.build.target.suffix).contains('a8'))
target = "a8/";
if (java.lang.String(Program.build.target.suffix).contains('m9'))
index 652a8c17c7a2d7cdc97ad0043c3069a7fdbf73c7..d65cc120939a78fc7e8fbff7d4193d80443f3b03 100755 (executable)
# Example:
# SRCS_<core/SoC/platform-name> =
# CFLAGS_LOCAL_<core/SoC/platform-name> =
+ifeq ($(CORE),c6xdsp)
SRCS_c6472-evm = sample_c6472_cfg.c sample_c6472_int_reg.c
SRCS_tci6486-evm = sample_tci6486_cfg.c sample_tci6486_int_reg.c
-SRCS_tci6498-sim = sample_tci6498_cfg.c sample_tci6498_int_reg.c
-ifeq ($(CORE),c6xdsp)
+SRCS_tci6608-sim = sample_tci6608_cfg.c sample_tci6608_int_reg.c
+SRCS_tci6616-sim = sample_tci6616_cfg.c sample_tci6616_int_reg.c
+SRCS_c6670-evm = sample_c6670_cfg.c sample_c6670_int_reg.c
+SRCS_c6678-evm = sample_c6678_cfg.c sample_c6678_int_reg.c
SRCS_omapl138-evm = sample_omapl138_cfg.c sample_omapl138_int_reg.c
SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_int_reg.c
else
diff --git a/packages/ti/sdo/edma3/rm/sample/package.bld b/packages/ti/sdo/edma3/rm/sample/package.bld
index df463a8ee0580694e5409ec442a7ef0f60ca294f..f910371b5b3d534a4aaf4f71aba3f05659c03ec5 100755 (executable)
"src/sample_init.c",
];
-var objListSimTCI6498 = [
- "src/platforms/sample_tci6498_cfg.c",
- "src/platforms/sample_tci6498_int_reg.c",
+var objListSimTCI6608 = [
+ "src/platforms/sample_tci6608_cfg.c",
+ "src/platforms/sample_tci6608_int_reg.c",
+ "src/sample_cs.c",
+ "src/sample_init.c",
+];
+var objListSimTCI6616 = [
+ "src/platforms/sample_tci6616_cfg.c",
+ "src/platforms/sample_tci6616_int_reg.c",
+ "src/sample_cs.c",
+ "src/sample_init.c",
+];
+
+var objListEVM6670 = [
+ "src/platforms/sample_c6670_cfg.c",
+ "src/platforms/sample_c6670_int_reg.c",
+ "src/sample_cs.c",
+ "src/sample_init.c",
+];
+var objListEVM6678 = [
+ "src/platforms/sample_c6678_cfg.c",
+ "src/platforms/sample_c6678_int_reg.c",
"src/sample_cs.c",
"src/sample_init.c",
];
var chipdefines = [
'CHIP_DA830',
- 'SIMTCI6498',
- 'SIMTCI6498',
+ 'SIMTCI6608',
+ 'SIMTCI6608',
+ 'SIMTCI6616',
+ 'SIMTCI6616',
+ 'CHIP_C6670',
+ 'CHIP_C6670',
+ 'CHIP_C6678',
+ 'CHIP_C6678',
'CHIP_C6748',
'CHIP_OMAPL138',
'CHIP_OMAPL138',
platform: 'ti.platforms.evmDA830', targ : 'C674', objList: objListDA830, dir : 'da830-evm/674/'
},
{
- platform: 'ti.platforms.simTCI6498', targ : 'C64P',objList: objListSimTCI6498, dir : 'tci6498-sim/64p/'
+ platform: 'ti.platforms.simTCI6608', targ : 'C66',objList: objListSimTCI6608, dir : 'tci6608-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.simTCI6608', targ : 'C66_big_endian',objList: objListSimTCI6608, dir : 'tci6608-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.simTCI6616', targ : 'C66',objList: objListSimTCI6616, dir : 'tci6616-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.simTCI6616', targ : 'C66_big_endian',objList: objListSimTCI6616, dir : 'tci6616-sim/66/'
+ },
+ {
+ platform: 'ti.platforms.evm6670', targ : 'C66',objList: objListEVM6670, dir : 'c6670-evm/66/'
+ },
+ {
+ platform: 'ti.platforms.evm6670', targ : 'C66_big_endian',objList: objListEVM6670, dir : 'c6670-evm/66/'
+ },
+ {
+ platform: 'ti.platforms.evm6678', targ : 'C66',objList: objListEVM6678, dir : 'c6678-evm/66/'
},
{
- platform: 'ti.platforms.simTCI6498', targ : 'C64P_big_endian',objList: objListSimTCI6498, dir : 'tci6498-sim/64p/'
+ platform: 'ti.platforms.evm6678', targ : 'C66_big_endian',objList: objListEVM6678, dir : 'c6678-evm/66/'
},
{
platform: 'ti.platforms.evm6748', targ : 'C674', objList: objListC6748, dir : 'c6748-evm/674/'
'lib/ti814x/release/ti.sdo.edma3.rm.sample.a674',
'lib/ti814x/debug/ti.sdo.edma3.rm.sample.aea8f',
'lib/ti814x/release/ti.sdo.edma3.rm.sample.aea8f',
- 'lib/tci6498/debug/ti.sdo.edma3.rm.sample.a64P',
- 'lib/tci6498/debug/ti.sdo.edma3.rm.sample.a64Pe',
- 'lib/tci6498/release/ti.sdo.edma3.rm.sample.a64P',
- 'lib/tci6498/release/ti.sdo.edma3.rm.sample.a64Pe',
+ 'lib/tci6608/debug/ti.sdo.edma3.rm.sample.ae66',
+ 'lib/tci6608/debug/ti.sdo.edma3.rm.sample.ae66e',
+ 'lib/tci6608/release/ti.sdo.edma3.rm.sample.ae66',
+ 'lib/tci6608/release/ti.sdo.edma3.rm.sample.ae66e',
+ 'lib/tci6616/debug/ti.sdo.edma3.rm.sample.ae66',
+ 'lib/tci6616/debug/ti.sdo.edma3.rm.sample.ae66e',
+ 'lib/tci6616/release/ti.sdo.edma3.rm.sample.ae66',
+ 'lib/tci6616/release/ti.sdo.edma3.rm.sample.ae66e',
+ 'lib/c6670/debug/ti.sdo.edma3.rm.sample.ae66',
+ 'lib/c6670/debug/ti.sdo.edma3.rm.sample.ae66e',
+ 'lib/c6670/release/ti.sdo.edma3.rm.sample.ae66',
+ 'lib/c6670/release/ti.sdo.edma3.rm.sample.ae66e',
+ 'lib/c6678/debug/ti.sdo.edma3.rm.sample.ae66',
+ 'lib/c6678/debug/ti.sdo.edma3.rm.sample.ae66e',
+ 'lib/c6678/release/ti.sdo.edma3.rm.sample.ae66',
+ 'lib/c6678/release/ti.sdo.edma3.rm.sample.ae66e',
'lib/simti816x/debug/ti.sdo.edma3.rm.sample.a674',
'lib/simti816x/release/ti.sdo.edma3.rm.sample.a674',
'lib/evmti816x/debug/ti.sdo.edma3.rm.sample.a674',
'src/platforms/sample_ti814x_int_reg.c',
'src/platforms/sample_ti814x_arm_cfg.c',
'src/platforms/sample_ti814x_arm_int_reg.c',
- 'src/platforms/sample_tci6498_cfg.c',
- 'src/platforms/sample_tci6498_int_reg.c',
+ 'src/platforms/sample_tci6608_cfg.c',
+ 'src/platforms/sample_tci6608_int_reg.c',
+ 'src/platforms/sample_tci6616_cfg.c',
+ 'src/platforms/sample_tci6616_int_reg.c',
+ 'src/platforms/sample_c6670_cfg.c',
+ 'src/platforms/sample_c6670_int_reg.c',
+ 'src/platforms/sample_c6678_cfg.c',
+ 'src/platforms/sample_c6678_int_reg.c',
'src/platforms/sample_ti816x_cfg.c',
'src/platforms/sample_ti816x_int_reg.c',
'src/platforms/sample_c6472_cfg.c',
diff --git a/packages/ti/sdo/edma3/rm/sample/package.xs b/packages/ti/sdo/edma3/rm/sample/package.xs
index a553775639bfb077d4d0aae0e58e33a21ae831c7..4db022861ad0cb5c899975e204ddf3cc42acc3ad 100755 (executable)
/* Boards supported */
var boards = [
'evmDA830',
+ 'simTCI6608',
+ 'simTCI6616',
+ 'evm6670',
+ 'evm6678',
'simTCI6498',
'evm6748',
'evmOMAPL138',
/* Directories for each platform */
var dir = [
'da830-evm/',
- 'tci6498-sim/',
+ 'tci6608-sim/',
+ 'tci6616-sim/',
+ 'c6670-evm/',
+ 'c6678-evm/',
'c6748-evm/',
'omapl138-evm/',
'ti816x-sim/',
target = "674/";
if (java.lang.String(Program.build.target.suffix).contains('64p'))
target = "64p/";
+ if (java.lang.String(Program.build.target.suffix).contains('66'))
+ target = "66/";
if (java.lang.String(Program.build.target.suffix).contains('a8'))
target = "a8/";
if (java.lang.String(Program.build.target.suffix).contains('m3'))
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6498_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6670_cfg.c
old mode 100755 (executable)
new mode 100644 (file)
similarity index 99%
rename from packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6498_cfg.c
rename to packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6670_cfg.c
index e7ee42b..dee29ef
new mode 100644 (file)
similarity index 99%
rename from packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6498_cfg.c
rename to packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6670_cfg.c
index e7ee42b..dee29ef
/*
- * sample_tci6498_cfg.c
+ * sample_c6670_cfg.c
*
* Platform specific EDMA3 hardware related information like number of transfer
* controllers, various interrupt ids etc. It is used while interrupts
#define CGEM_REG_START (0x01800000)
+
+extern cregister volatile unsigned int DNUM;
+
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
+
+
/* Determine the processor id by reading DNUM register. */
unsigned short determineProcId()
{
return core_no;
}
+signed char* getGlobalAddr(signed char* addr)
+{
+ if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+ {
+ return (addr); /* The address is already a global address */
+ }
+
+ return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
/** Whether global configuration required for EDMA3 or not.
* This configuration should be done only once for the EDMA3 hardware by
* any one of the masters (i.e. DSPs).
},
};
-
/**
* Variable which will be used internally for referring channel controller's
* error interrupt.
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6498_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6670_int_reg.c
old mode 100755 (executable)
new mode 100644 (file)
similarity index 94%
rename from packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6498_int_reg.c
rename to packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6670_int_reg.c
index ac398b3..51c4a6c
new mode 100644 (file)
similarity index 94%
rename from packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6498_int_reg.c
rename to packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6670_int_reg.c
index ac398b3..51c4a6c
/*
- * sample_tci6498_int_reg.c
+ * sample_c6670_int_reg.c
*
* Platform specific interrupt registration and un-registration routines.
*
#include <ti/sysbios/family/c64p/EventCombiner.h>
#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
-#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
extern unsigned int ccErrorInt[];
/* Host interrupts for transfer completion */
//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
unsigned int ccXferHostInt[3][4] = {
- {0u, 16u, 32u, 48u},
- {1u, 17u, 33u, 49u},
- {2u, 18u, 34u, 50u},
+ {8u, 24u, 40u, 56u},
+ {9u, 25u, 41u, 57u},
+ {10u, 26u, 42u, 58u},
};
unsigned int edma3ErrHostInt[3][4] = {
- {3u, 19u, 35u, 51u},
- {4u, 20u, 36u, 52u},
- {5u, 21u, 37u, 53u},
+ {11u, 27u, 43u, 59u},
+ {12u, 28u, 44u, 60u},
+ {13u, 29u, 45u, 61u},
};
eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
ccXferHostInt[edma3Id][dsp_num], TRUE);
+ EventCombiner_enableEvent(eventId);
/* CC Error ISR */
CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
edma3ErrHostInt[edma3Id][dsp_num], TRUE);
+ EventCombiner_enableEvent(eventId);
Hwi_enableInterrupt(hwiInterrupt);
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6678_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6678_cfg.c
--- /dev/null
@@ -0,0 +1,1794 @@
+/*
+ * sample_tci6678_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 3u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 8u
+//const unsigned int numDsps = NUM_DSPS;
+
+#define CGEM_REG_START (0x01800000)
+
+extern cregister volatile unsigned int DNUM;
+
+
+
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+ {
+ return (addr); /* The address is already a global address */
+ }
+
+ return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+/** Whether global configuration required for EDMA3 or not.
+ * This configuration should be done only once for the EDMA3 hardware by
+ * any one of the masters (i.e. DSPs).
+ * It can be changed depending on the use-case.
+ */
+unsigned int gblCfgReqdArray [NUM_DSPS] = {
+ 0, /* DSP#0 is Master, will do the global init */
+ 1, /* DSP#1 is Slave, will not do the global init */
+ 1, /* DSP#2 is Slave, will not do the global init */
+ 1, /* DSP#3 is Slave, will not do the global init */
+ 1, /* DSP#4 is Slave, will not do the global init */
+ 1, /* DSP#5 is Slave, will not do the global init */
+ 1, /* DSP#6 is Slave, will not do the global init */
+ 1, /* DSP#7 is Slave, will not do the global init */
+ };
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ return gblCfgReqdArray[dspNum];
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
+
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt. Completion interrupts for all the shadow regions and all the
+ * EDMA3 controllers are captured since it is a multi-DSP platform.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ 38u, 39u, 40u, 41u,
+ 42u, 43u, 44u, 45u,
+ },
+ {
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ },
+ {
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
+ {
+ 34u, 35u, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 2u, 3u, 4u, 5u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 18u, 19u, 20u, 21u,
+ 0u, 0u, 0u, 0u,
+ },
+ };
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 128u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFFFF0000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 64u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFFFF0000u
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x3FFF0003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000003u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000003u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xC000000Cu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000000Cu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000000Cu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000030u, 0x03FFF000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x000000C0u, 0xFC000000u, 0x000000FFu, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x000000C0u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x000000C0u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000300u, 0x00000000u, 0x003FFF00u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000C00u, 0x00000000u, 0xFFC00000u, 0x0000000Fu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000C00u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000C00u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003000u, 0x00000000u, 0x00000000u, 0x0003FFF0u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000C000u, 0x00000000u, 0x00000000u, 0xFFFC0000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000C000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000C000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00030000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x000C0000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00300000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00C00000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x03000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0C000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x30000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xC0000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00030000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x000C0000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00300000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00C00000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x03000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0C000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x30000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xC0000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+ },
+ };
+
+/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6678_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6678_int_reg.c
--- /dev/null
@@ -0,0 +1,165 @@
+/*
+ * sample_c6678_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+unsigned int hwiInterrupt = 8;
+
+/* Host interrupts for transfer completion */
+//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
+unsigned int ccXferHostInt[3][8] = {
+ {2u, 10u, 18u, 26u, 2u, 10u, 18u, 26u},
+ {3u, 11u, 19u, 27u, 3u, 11u, 19u, 27u},
+ {4u, 12u, 20u, 28u, 4u, 12u, 20u, 28u},
+ };
+unsigned int edma3ErrHostInt[3][8] = {
+ {5u, 13u, 21u, 29u, 5u, 13u, 21u, 29u},
+ {6u, 14u, 22u, 30u, 6u, 14u, 22u, 30u},
+ {7u, 15u, 23u, 31u, 7u, 15u, 23u, 31u},
+ };
+
+
+extern unsigned int dsp_num;
+
+/** To Register the ISRs with the underlying OS, if required */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ unsigned int numTc = 0;
+ UInt cpIntcId= 0;
+ if (dsp_num > 3)
+ {
+ cpIntcId = 1;
+ }
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+ lisrEdma3ComplHandler0,
+ edma3Id,
+ TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, ccXferCompInt[edma3Id][dsp_num],
+ ccXferHostInt[edma3Id][dsp_num]);
+ CpIntc_enableHostInt(cpIntcId, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ ccXferHostInt[edma3Id][dsp_num], TRUE);
+
+ /* CC Error ISR */
+ CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, ccErrorInt[edma3Id],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ /* TC Error ISR */
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
+ (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, tcErrorInt[edma3Id][numTc],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ numTc++;
+ }
+ /* Enable the host interrupt which is common for both CC and TC error */
+ CpIntc_enableHostInt(cpIntcId, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ edma3ErrHostInt[edma3Id][dsp_num], TRUE);
+
+ Hwi_enableInterrupt(hwiInterrupt);
+
+ /* enable the 'global' switch */
+ CpIntc_enableAllHostInts(cpIntcId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ UInt cpIntcId= 0;
+ if (dsp_num > 3)
+ {
+ cpIntcId = 1;
+ }
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_disableHostInt(cpIntcId, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* CC/TC Error ISR */
+ CpIntc_disableHostInt(cpIntcId, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6608_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6608_cfg.c
--- /dev/null
@@ -0,0 +1,1794 @@
+/*
+ * sample_tci6608_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 3u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 8u
+//const unsigned int numDsps = NUM_DSPS;
+
+#define CGEM_REG_START (0x01800000)
+
+extern cregister volatile unsigned int DNUM;
+
+
+
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+ {
+ return (addr); /* The address is already a global address */
+ }
+
+ return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+/** Whether global configuration required for EDMA3 or not.
+ * This configuration should be done only once for the EDMA3 hardware by
+ * any one of the masters (i.e. DSPs).
+ * It can be changed depending on the use-case.
+ */
+unsigned int gblCfgReqdArray [NUM_DSPS] = {
+ 0, /* DSP#0 is Master, will do the global init */
+ 1, /* DSP#1 is Slave, will not do the global init */
+ 1, /* DSP#2 is Slave, will not do the global init */
+ 1, /* DSP#3 is Slave, will not do the global init */
+ 1, /* DSP#4 is Slave, will not do the global init */
+ 1, /* DSP#5 is Slave, will not do the global init */
+ 1, /* DSP#6 is Slave, will not do the global init */
+ 1, /* DSP#7 is Slave, will not do the global init */
+ };
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ return gblCfgReqdArray[dspNum];
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
+
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt. Completion interrupts for all the shadow regions and all the
+ * EDMA3 controllers are captured since it is a multi-DSP platform.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ 38u, 39u, 40u, 41u,
+ 42u, 43u, 44u, 45u,
+ },
+ {
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ },
+ {
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
+ {
+ 34u, 35u, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 2u, 3u, 4u, 5u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 18u, 19u, 20u, 21u,
+ 0u, 0u, 0u, 0u,
+ },
+ };
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 128u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFFFF0000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 64u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFFFF0000u
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x3FFF0003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000003u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000003u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xC000000Cu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000000Cu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000000Cu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000030u, 0x03FFF000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x000000C0u, 0xFC000000u, 0x000000FFu, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x000000C0u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x000000C0u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000300u, 0x00000000u, 0x003FFF00u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000C00u, 0x00000000u, 0xFFC00000u, 0x0000000Fu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000C00u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000C00u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003000u, 0x00000000u, 0x00000000u, 0x0003FFF0u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000C000u, 0x00000000u, 0x00000000u, 0xFFFC0000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000C000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000C000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00030000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x000C0000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00300000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00C00000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x03000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0C000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x30000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xC0000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00030000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000001u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00030000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x000C0000u, 0x00000000u, 0xFF000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000002u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x000C0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00300000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000004u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00300000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00C00000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000008u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00C00000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x03000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000010u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x03000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0C000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000020u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0C000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x30000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000040u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x30000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xC0000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000080u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xC0000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+ },
+ };
+
+/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6608_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6608_int_reg.c
--- /dev/null
@@ -0,0 +1,165 @@
+/*
+ * sample_tci6608_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+unsigned int hwiInterrupt = 8;
+
+/* Host interrupts for transfer completion */
+//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
+unsigned int ccXferHostInt[3][8] = {
+ {2u, 10u, 18u, 26u, 2u, 10u, 18u, 26u},
+ {3u, 11u, 19u, 27u, 3u, 11u, 19u, 27u},
+ {4u, 12u, 20u, 28u, 4u, 12u, 20u, 28u},
+ };
+unsigned int edma3ErrHostInt[3][8] = {
+ {5u, 13u, 21u, 29u, 5u, 13u, 21u, 29u},
+ {6u, 14u, 22u, 30u, 6u, 14u, 22u, 30u},
+ {7u, 15u, 23u, 31u, 7u, 15u, 23u, 31u},
+ };
+
+
+extern unsigned int dsp_num;
+
+/** To Register the ISRs with the underlying OS, if required */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ unsigned int numTc = 0;
+ UInt cpIntcId= 0;
+ if (dsp_num > 3)
+ {
+ cpIntcId = 1;
+ }
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+ lisrEdma3ComplHandler0,
+ edma3Id,
+ TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, ccXferCompInt[edma3Id][dsp_num],
+ ccXferHostInt[edma3Id][dsp_num]);
+ CpIntc_enableHostInt(cpIntcId, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ ccXferHostInt[edma3Id][dsp_num], TRUE);
+
+ /* CC Error ISR */
+ CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, ccErrorInt[edma3Id],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ /* TC Error ISR */
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
+ (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(cpIntcId, tcErrorInt[edma3Id][numTc],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ numTc++;
+ }
+ /* Enable the host interrupt which is common for both CC and TC error */
+ CpIntc_enableHostInt(cpIntcId, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ edma3ErrHostInt[edma3Id][dsp_num], TRUE);
+
+ Hwi_enableInterrupt(hwiInterrupt);
+
+ /* enable the 'global' switch */
+ CpIntc_enableAllHostInts(cpIntcId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ UInt cpIntcId= 0;
+ if (dsp_num > 3)
+ {
+ cpIntcId = 1;
+ }
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_disableHostInt(cpIntcId, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* CC/TC Error ISR */
+ CpIntc_disableHostInt(cpIntcId, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6616_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6616_cfg.c
--- /dev/null
@@ -0,0 +1,1787 @@
+/*
+ * sample_tci616_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 3u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 4u
+//const unsigned int numDsps = NUM_DSPS;
+
+#define CGEM_REG_START (0x01800000)
+
+
+extern cregister volatile unsigned int DNUM;
+
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
+
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+ }
+
+signed char* getGlobalAddr(signed char* addr)
+{
+ if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+ {
+ return (addr); /* The address is already a global address */
+ }
+
+ return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+/** Whether global configuration required for EDMA3 or not.
+ * This configuration should be done only once for the EDMA3 hardware by
+ * any one of the masters (i.e. DSPs).
+ * It can be changed depending on the use-case.
+ */
+unsigned int gblCfgReqdArray [NUM_DSPS] = {
+ 0, /* DSP#0 is Master, will do the global init */
+ 1, /* DSP#1 is Slave, will not do the global init */
+ 1, /* DSP#2 is Slave, will not do the global init */
+ 1, /* DSP#3 is Slave, will not do the global init */
+ };
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ return gblCfgReqdArray[dspNum];
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle rmSemHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
+
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt. Completion interrupts for all the shadow regions and all the
+ * EDMA3 controllers are captured since it is a multi-DSP platform.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ 38u, 39u, 40u, 41u,
+ 42u, 43u, 44u, 45u,
+ },
+ {
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ },
+ {
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
+ {
+ 34u, 35u, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 2u, 3u, 4u, 5u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 18u, 19u, 20u, 21u,
+ 0u, 0u, 0u, 0u,
+ },
+ };
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00003333u,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 64u,
+ 64u,
+ 64u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x3FFF3FFFu,
+ 0x3FFF3FFFu
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 64u,
+ 64u,
+ 64u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x3FFF3FFFu,
+ 0x3FFF3FFFu
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000000Fu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000003u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000000Fu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 */
+ {0x00000003u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 */
+ {0x00000003u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x000000F0u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Cu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x000000F0u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000F00u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000030u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000F00u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000F000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000F000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000003u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Cu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000030u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000003u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Cu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000030u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
+
+/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6616_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6616_int_reg.c
--- /dev/null
@@ -0,0 +1,157 @@
+/*
+ * sample_tci6616_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+unsigned int hwiInterrupt = 8;
+
+/* Host interrupts for transfer completion */
+//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
+unsigned int ccXferHostInt[3][4] = {
+ {8u, 24u, 40u, 56u},
+ {9u, 25u, 41u, 57u},
+ {10u, 26u, 42u, 58u},
+ };
+unsigned int edma3ErrHostInt[3][4] = {
+ {11u, 27u, 43u, 59u},
+ {12u, 28u, 44u, 60u},
+ {13u, 29u, 45u, 61u},
+ };
+
+
+extern unsigned int dsp_num;
+
+/** To Register the ISRs with the underlying OS, if required */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ unsigned int numTc = 0;
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+ lisrEdma3ComplHandler0,
+ edma3Id,
+ TRUE);
+ CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num],
+ ccXferHostInt[edma3Id][dsp_num]);
+ CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ ccXferHostInt[edma3Id][dsp_num], TRUE);
+ EventCombiner_enableEvent(eventId);
+
+ /* CC Error ISR */
+ CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(0, ccErrorInt[edma3Id],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ /* TC Error ISR */
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
+ (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(0, tcErrorInt[edma3Id][numTc],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ numTc++;
+ }
+ /* Enable the host interrupt which is common for both CC and TC error */
+ CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ edma3ErrHostInt[edma3Id][dsp_num], TRUE);
+ EventCombiner_enableEvent(eventId);
+
+ Hwi_enableInterrupt(hwiInterrupt);
+
+ /* enable the 'global' switch */
+ CpIntc_enableAllHostInts(0);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_disableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* CC/TC Error ISR */
+ CpIntc_disableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_c6670_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_c6670_cfg.c
--- /dev/null
@@ -0,0 +1,1735 @@
+/*
+ * edma3_c6670_cfg.c
+ *
+ * EDMA3 Resource Manager Adaptation Configuration File (SoC Specific).
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+#define NUM_EDMA3_INSTANCES 3u
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u,
+ 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x0000FFFFu,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 64u,
+ 64u,
+ 64u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0x0000FFFFu
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 64u,
+ 64u,
+ 64u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFF0000FFu
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x000000FFu},
+
+ /* resvdTccs */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x000000FFu},
+
+ /* resvdTccs */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x000000FFu},
+
+ /* resvdTccs */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x000000FFu},
+
+ /* resvdTccs */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Fu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000F0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Fu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000F0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
+
+/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_c6678_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_c6678_cfg.c
--- /dev/null
@@ -0,0 +1,1737 @@
+/*
+ * edma3_c6678_cfg.c
+ *
+ * EDMA3 Resource Manager Adaptation Configuration File (SoC Specific).
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+#define NUM_EDMA3_INSTANCES 3u
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 128u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFF000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 64u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFF000000u
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x000000FFu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Fu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x000000FFu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000FF00u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000F0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000FF00u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000007u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000038u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000007u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000038u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+ },
+ };
+
+/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6608_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6608_cfg.c
--- /dev/null
@@ -0,0 +1,1737 @@
+/*
+ * edma3_tci6608_cfg.c
+ *
+ * EDMA3 Resource Manager Adaptation Configuration File (SoC Specific).
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+#define NUM_EDMA3_INSTANCES 3u
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 128u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFF000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 64u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFF000000u
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x000000FFu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Fu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x000000FFu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000FF00u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000F0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000FF00u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000007u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000038u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000007u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000038u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x000000FFu},
+ },
+ },
+ };
+
+/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6616_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6616_cfg.c
--- /dev/null
@@ -0,0 +1,1735 @@
+/*
+ * edma3_tci6616_cfg.c
+ *
+ * EDMA3 Resource Manager Adaptation Configuration File (SoC Specific).
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+#define NUM_EDMA3_INSTANCES 3u
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u,
+ 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x0000FFFFu,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 64u,
+ 64u,
+ 64u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0x0000FFFFu
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 64u,
+ 64u,
+ 64u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFF0000FFu
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x000000FFu},
+
+ /* resvdTccs */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x000000FFu},
+
+ /* resvdTccs */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x000000FFu},
+
+ /* resvdTccs */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x000000FFu},
+
+ /* resvdTccs */
+ /* 31 0 63 32*/
+ {0x0000FFFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Fu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000F0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFF000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x0000FFFFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Fu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FF00u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000F0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00FF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0xFF0000FFu},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
+
+/* End of File */