Misra C Fixes:
authorSunil MS <x0190988@ti.com>
Wed, 15 Oct 2014 09:56:30 +0000 (15:26 +0530)
committerSunil MS <x0190988@ti.com>
Thu, 16 Oct 2014 05:04:58 +0000 (10:34 +0530)
MISRA.CVALUE.IMPL.CAST
MISRA.DECL.ARRAY_SIZE
MISRA.DEFINE.BADEXP
MISRA.FUNC.NOPROT.DEF
MISRA.INIT.BRACES
MISRA.LITERAL.UNSIGNED.SUFFIX
MISRA.VAR.UNIQUE.STATIC

Change-Id: Ic5dfaf5902eaf9478afe7369b3c6222602848720
Signed-off-by: Sunil MS <x0190988@ti.com>
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_int_reg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_int_reg.c

index 9c76005e3d75e4d5bbb985c2029d381e709408f2..8d4fa6b34bb7c977bdc66dc1347dfa59f8165a20 100755 (executable)
@@ -48,8 +48,15 @@ const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
 #define NUM_DSPS                    0U
 const uint32_t numDsps = NUM_DSPS;
 
+int8_t*  getGlobalAddr(int8_t* addr);
+
+uint16_t isGblConfigRequired(uint32_t dspNum);
+
+/* Determine the processor id by reading DNUM register. */
+uint16_t determineProcId(void);
+
 /* Determine the processor id by reading DNUM register. */
-uint16_t determineProcId()
+uint16_t determineProcId(void)
 {
     return 0;
 }
@@ -223,7 +230,11 @@ uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
                                                         EDMA3_0_HWI_INT_TC0_ERR,
                                                         EDMA3_0_HWI_INT_TC1_ERR,
                                                         EDMA3_0_HWI_INT_TC2_ERR,
-                                                        EDMA3_0_HWI_INT_TC3_ERR
+                                                        EDMA3_0_HWI_INT_TC3_ERR,
+                                                        0,
+                                                        0,
+                                                        0,
+                                                        0
                                                      }
                                                };
 
index 8b612581d76d9fac2bcee0b90a2c7675874c98c2..0ef69f390b31bd107ead667dba042898681414f3 100755 (executable)
   */
 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 {
-                                                (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,
-                                                (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorInt[];
-extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
-extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern uint32_t hwIntXferComp[];
-extern uint32_t hwIntCcErr[];
-extern uint32_t hwIntTcErr[];
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
 
 extern uint32_t dsp_num;
 /* This variable has to be used as an extern */
@@ -83,7 +83,7 @@ Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
 
 /* External Instance Specific Configuration Structure */
 extern EDMA3_DRV_GblXbarToChanConfigParams 
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+                                                               sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
 
 typedef struct  {
     volatile Uint32 DSP_INTMUX[21];
@@ -130,6 +130,15 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
 
 void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
 
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (uint32_t edma3Id);
+
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
+                                   uint32_t edma3Id);
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (uint32_t edma3Id);
+
 /**  To Register the ISRs with the underlying OS, if required. */
 void registerEdma3Interrupts (uint32_t edma3Id)
     {
@@ -156,7 +165,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
                                        (&lisrEdma3ComplHandler0),
                                        (const Hwi_Params *) (&hwiParams),
                                        &eb);
-    if (TRUE == Error_check(&eb))
+    if ((bool)TRUE == Error_check(&eb))
     {
         System_printf("HWI Create Failed\n",Error_getCode(&eb));
     }
@@ -173,7 +182,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
                 (const Hwi_Params *) (&hwiParams),
                 &eb);
 
-    if (TRUE == Error_check(&eb))
+    if ((bool)TRUE == Error_check(&eb))
     {
         System_printf("HWI Create Failed\n",Error_getCode(&eb));
     }
@@ -191,7 +200,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
                     (ptrEdma3TcIsrHandler[numTc]),
                     (const Hwi_Params *) (&hwiParams),
                     &eb);
-        if (TRUE == Error_check(&eb))
+        if ((bool)TRUE == Error_check(&eb))
         {
             System_printf("HWI Create Failed\n",Error_getCode(&eb));
         }
@@ -227,11 +236,11 @@ void registerEdma3Interrupts (uint32_t edma3Id)
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
-       static UInt32 cookie = 0;
+       static UInt32 cookiee = 0;
     uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
-    cookie = Hwi_disable();
+    cookiee = Hwi_disable();
 
     Hwi_delete(&hwiCCXferCompInt);
     Hwi_delete(&hwiCCErrInt);
@@ -241,7 +250,7 @@ void unregisterEdma3Interrupts (uint32_t edma3Id)
         numTc++;
        }
     /* Restore interrupts */
-    Hwi_restore(cookie);
+    Hwi_restore(cookiee);
     }
 
 /**
@@ -297,9 +306,9 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
                (chanNum < EDMA3_NUM_TCC))
                {
-               scrRegOffset = chanNum / 4;
-               scrChanOffset = chanNum - (scrRegOffset * 4);
-               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+               scrRegOffset = chanNum / 4U;
+               scrChanOffset = chanNum - (scrRegOffset * 4U);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1U;
                
                switch(scrChanOffset)
                        {
@@ -307,17 +316,17 @@ EDMA3_DRV_Result sampleConfigScr (uint32_t eventNum,
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
                                break;
-                       case 1:
+                       case 1U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
                                break;
-                       case 2:
+                       case 2U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
                                break;
-                       case 3:
+                       case 3U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
@@ -353,5 +362,8 @@ EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
 
 void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
     {
+#ifdef EDMA3_RM_DEBUG
+    /*  Added to fix Misra C error */
     printf("memory Protection error");
+#endif
     }
index d182b5e1be11d974d070ba2ad3686c075420089b..628d4a5092fedd91b2254ffb52839f2fe6faec1d 100755 (executable)
@@ -48,10 +48,17 @@ const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;
 #define NUM_DSPS                    1U
 const uint32_t numDsps = NUM_DSPS;
 
+int8_t*  getGlobalAddr(int8_t* addr);
+
+uint16_t isGblConfigRequired(uint32_t dspNum);
+
+/* Determine the processor id by reading DNUM register. */
+uint16_t determineProcId(void);
+
 /* Determine the processor id by reading DNUM register. */
-uint16_t determineProcId()
+uint16_t determineProcId(void)
 {
-    return 1;
+    return 1U;
 }
 
 int8_t*  getGlobalAddr(int8_t* addr)
@@ -62,7 +69,7 @@ uint16_t isGblConfigRequired(uint32_t dspNum)
 {
     (void) dspNum;
 
-    return 1;
+    return 1U;
 }
 
 /* Semaphore handles */
@@ -224,7 +231,11 @@ uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
                                                         EDMA3_0_HWI_INT_TC0_ERR,
                                                         EDMA3_0_HWI_INT_TC1_ERR,
                                                         EDMA3_0_HWI_INT_TC2_ERR,
-                                                        EDMA3_0_HWI_INT_TC3_ERR
+                                                        EDMA3_0_HWI_INT_TC3_ERR,
+                                                        0,
+                                                        0,
+                                                        0,
+                                                        0
                                                      }
                                                };
 
index 86a23970c9dfcddf37e16c5b7cdd532aa5d96985..e09f3ead56258e14dbbe0e572c36c820e9b15da8 100755 (executable)
@@ -59,24 +59,24 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
                                                 &lisrEdma3TC7ErrHandler0,
                                                 };
 
-extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorInt[];
-extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
-extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-extern uint32_t hwIntXferComp[];
-extern uint32_t hwIntCcErr[];
-extern uint32_t hwIntTcErr[];
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
 
 extern uint32_t dsp_num;
 
 /* External Instance Specific Configuration Structure */
 extern EDMA3_RM_GblXbarToChanConfigParams 
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+                                                               sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
 
 typedef struct  {
     volatile Uint32 DSP_INTMUX[21];
@@ -121,6 +121,14 @@ EDMA3_RM_Result sampleMapXbarEvtToChan (uint32_t eventNum,
 EDMA3_RM_Result sampleConfigScr (uint32_t eventNum,
                                   uint32_t chanNum);
 
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (uint32_t edma3Id);
+
+EDMA3_RM_Result sampleInitXbarEvt(EDMA3_RM_Handle hEdma, 
+                                   uint32_t edma3Id);
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (uint32_t edma3Id);
 
 /**  To Register the ISRs with the underlying OS, if required. */
 void registerEdma3Interrupts (uint32_t edma3Id)
@@ -134,13 +142,13 @@ void registerEdma3Interrupts (uint32_t edma3Id)
     /* Enable the Xfer Completion Event Interrupt */
     EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
                                                (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
-                               edma3Id, 1);
+                               edma3Id, (Bool)1);
     EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
 
     /* Enable the CC Error Event Interrupt */
     EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
                                                (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
-                                               edma3Id, 1);
+                                               edma3Id, (Bool)1);
     EventCombiner_enableEvent(ccErrorInt[edma3Id]);
 
     /* Enable the TC Error Event Interrupt, according to the number of TCs. */
@@ -148,7 +156,7 @@ void registerEdma3Interrupts (uint32_t edma3Id)
            {
         EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
                             (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
-                            edma3Id, 1);
+                            edma3Id, (Bool)1);
         EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
         numTc++;
        }
@@ -175,11 +183,11 @@ void registerEdma3Interrupts (uint32_t edma3Id)
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
 void unregisterEdma3Interrupts (uint32_t edma3Id)
     {
-       static UInt32 cookie = 0;
+       static UInt32 cookiee = 0;
     uint32_t numTc = 0;
 
     /* Disabling the global interrupts */
-    cookie = Hwi_disable();
+    cookiee = Hwi_disable();
 
     /* Disable the Xfer Completion Event Interrupt */
        EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
@@ -195,7 +203,7 @@ void unregisterEdma3Interrupts (uint32_t edma3Id)
        }
 
     /* Restore interrupts */
-    Hwi_restore(cookie);
+    Hwi_restore(cookiee);
     }
 
 /**
@@ -251,9 +259,9 @@ EDMA3_RM_Result sampleConfigScr (uint32_t eventNum,
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
                (chanNum < EDMA3_NUM_TCC))
                {
-               scrRegOffset = chanNum / 4;
-               scrChanOffset = chanNum - (scrRegOffset * 4);
-               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+               scrRegOffset = chanNum / 4U;
+               scrChanOffset = chanNum - (scrRegOffset * 4U);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1U;
                
                switch(scrChanOffset)
                        {
@@ -261,17 +269,17 @@ EDMA3_RM_Result sampleConfigScr (uint32_t eventNum,
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
                                break;
-                       case 1:
+                       case 1U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
                                break;
-                       case 2:
+                       case 2U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
                                break;
-                       case 3:
+                       case 3U:
                                scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));