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raw | patch | inline | side by side (parent: 8a3368c)
| author | Anuj Aggarwal <anuj.aggarwal@ti.com> | |
| Sun, 13 Sep 2009 05:30:19 +0000 (11:00 +0530) | ||
| committer | Anuj Aggarwal <anuj.aggarwal@ti.com> | |
| Sun, 13 Sep 2009 05:30:19 +0000 (11:00 +0530) |
- add TCI6498 support in source files
- modify .xs and .bld files
- code clean up
- modify .xs and .bld files
- code clean up
diff --git a/packages/ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h b/packages/ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**| **** |**
-**| **** |**
-**| ******o*** |**
-**| ********_///_**** |**
-**| ***** /_//_/ **** |**
-**| ** ** (__/ **** |**
-**| ********* |**
-**| **** |**
-**| *** |**
-**| |**
-**| Copyright (c) 1998-2006 Texas Instruments Incorporated |**
-**| ALL RIGHTS RESERVED |**
-**| |**
-**| Permission is hereby granted to licensees of Texas Instruments |**
-**| Incorporated (TI) products to use this computer program for the sole |**
-**| purpose of implementing a licensee product based on TI products. |**
-**| No other rights to reproduce, use, or disseminate this computer |**
-**| program, whether in part or in whole, are granted. |**
-**| |**
-**| TI makes no representation or warranties with respect to the |**
-**| performance of this computer program, and specifically disclaims |**
-**| any responsibility for any damages, special or consequential, |**
-**| connected with the use of this program. |**
-**| |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/** \file bios6_edma3_rm_sample.h
-
- \brief Header file for the Demo application for the EDMA3 Resource Manager.
-
- (C) Copyright 2006, Texas Instruments, Inc
-
- \version 1.0 Anuj Aggarwal - Created
- 1.1 Anuj Aggarwal - Made the sample app generic
- - Removed redundant arguments
- from Cache-related APIs
- - Added new function for Poll mode
- testing
-
- */
+/*
+ * bios6_edma3_rm_sample.h
+ *
+ * Header file for the Demo application for the EDMA3 Resource Manager.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
#ifndef _BIOS6_EDMA3_RM_SAMPLE_H_
#define _BIOS6_EDMA3_RM_SAMPLE_H_
#endif /* EDMA3_DEBUG_PRINT */
/**
- * \brief SoC specific TC related information. Specified in the sample
- * configuration file (bios_edma3_sample_cfg.c).
+ * Cache line size on the underlying SoC. It needs to be modified
+ * for different cache line sizes, if the Cache is Enabled.
*/
-extern unsigned int numEdma3Tc;
-extern unsigned int ccXferCompInt;
-extern unsigned int ccErrorInt;
-extern unsigned int tcErrorInt[8];
+#define EDMA3_CACHE_LINE_SIZE_IN_BYTES (128u)
+
+/* Error returned in case of buffers are not aligned on the cache boundary */
+#define EDMA3_NON_ALIGNED_BUFFERS_ERROR (-1)
-extern unsigned int hwIntXferComp;
-extern unsigned int hwIntCcErr;
-extern unsigned int hwIntTcErr;
+/* Error returned in case of data mismatch */
+#define EDMA3_DATA_MISMATCH_ERROR (-2)
-EDMA3_RM_Result edma3init();
-EDMA3_RM_Result edma3deinit();
+/**
+ * \brief EDMA3 Initialization
+ *
+ * This function initializes the EDMA3 Resource Manager for the given EDMA3 controller
+ * and opens a EDMA3 RM instance. It internally calls EDMA3_RM_create() and
+ * EDMA3_RM_open(), in that order.
+ *
+ * It also registers interrupt handlers for various EDMA3 interrupts like
+ * transfer completion or error interrupts.
+ *
+ * \param edma3Id [IN] EDMA3 Controller Instance Id (Hardware
+ * instance id, starting from 0)
+ * \param errorCode [IN/OUT] Error code while opening RM instance
+ * \return EDMA3_RM_Handle: If successfully opened, the API will return the
+ * associated RM's instance handle.
+ */
+EDMA3_RM_Handle edma3init (unsigned int edma3Id, EDMA3_RM_Result *errorCode);
+/**
+ * \brief EDMA3 De-initialization
+ *
+ * This function de-initializes the EDMA3 RM for the given EDMA3 controller
+ * and closes the previously opened EDMA3 RM instance. It internally calls
+ * EDMA3_RM_close and EDMA3_RM_delete(), in that order.
+ *
+ * It also un-registers the previously registered interrupt handlers for various
+ * EDMA3 interrupts.
+ *
+ * \param edma3Id [IN] EDMA3 Controller Instance Id (Hardware
+ * instance id, starting from 0)
+ * \param hEdma [IN] EDMA3 RM handle, returned while using
+ * edma3init().
+ * \return EDMA3_RM_SOK if success, else error code
+ */
+EDMA3_RM_Result edma3deinit (unsigned int edma3Id, EDMA3_RM_Handle hEdma);
/**
* Counting Semaphore related functions (OS dependent) should be
const Semaphore_Params *semParams,
EDMA3_OS_Sem_Handle *hSem);
-
-
/**
* \brief EDMA3 OS Semaphore Delete
*
diff --git a/packages/ti/sdo/edma3/rm/sample/package.bld b/packages/ti/sdo/edma3/rm/sample/package.bld
var Pkg = xdc.useModule('xdc.bld.PackageContents');
var objListDA830 = [
- "src/bios6_edma3_rm_sample_da830_cfg.c",
- "src/bios6_edma3_rm_sample_cs.c",
- "src/bios6_edma3_rm_sample_init.c",
+ "src/platforms/sample_da830_cfg.c",
+ "src/platforms/sample_da830_int_reg.c",
+ "src/sample_cs.c",
+ "src/sample_init.c",
+];
+
+var objListSimTCI6498 = [
+ "src/platforms/sample_tci6498_cfg.c",
+ "src/platforms/sample_tci6498_int_reg.c",
+ "src/sample_cs.c",
+ "src/sample_init.c",
];
var objList = [
objListDA830,
+ objListSimTCI6498,
];
/* Platforms supported */
var plat_supported = [
'ti.platforms.evmDA830',
- ];
+ 'ti.platforms.simTCI6498',
+ ];
/* Directories for each platform */
var dir = [
'da830/',
+ 'tci6498/',
];
for each (var targ in Build.targets)
if (bool == 0)
throw new Error('Unexpected value in "platform" parameter')
- Pkg.addLibrary(lib + "Debug/" + Pkg.name, targ, { profile: "debug"}).addObjects(objList[i]);
- Pkg.addLibrary(lib + "Release/" + Pkg.name, targ, { profile: "release"}).addObjects(objList[i]);
+ if (java.lang.String(targ.model.endian).equals("big")) {
+ Pkg.addLibrary(lib + "Debug/" + Pkg.name, targ,
+ { defs:"-DBIG_ENDIAN_MODE", profile: "debug"}
+ ).addObjects(objList[i]);
+ Pkg.addLibrary(lib + "Release/" + Pkg.name, targ,
+ { defs:"-DBIG_ENDIAN_MODE", profile: "release"}
+ ).addObjects(objList[i]);
+ } else {
+ Pkg.addLibrary(lib + "Debug/" + Pkg.name, targ,
+ { defs:"", profile: "debug"}
+ ).addObjects(objList[i]);
+ Pkg.addLibrary(lib + "Release/" + Pkg.name, targ,
+ { defs:"", profile: "release"}
+ ).addObjects(objList[i]);
+ }
}
}
Pkg.otherFiles=[
+ '.settings/org.eclipse.cdt.core.prefs',
'lib/da830/Debug/ti.sdo.edma3.rm.sample.a674',
'lib/da830/Release/ti.sdo.edma3.rm.sample.a674',
- 'src',
+ 'lib/tci6498/Debug/ti.sdo.edma3.rm.sample.a64P',
+ 'lib/tci6498/Debug/ti.sdo.edma3.rm.sample.a64Pe',
+ 'lib/tci6498/Release/ti.sdo.edma3.rm.sample.a64P',
+ 'lib/tci6498/Release/ti.sdo.edma3.rm.sample.a64Pe',
+ 'src/sample_cs.c',
+ 'src/sample_init.c',
+ 'src/platforms/sample_da830_cfg.c',
+ 'src/platforms/sample_da830_int_reg.c',
+ 'src/platforms/sample_tci6498_cfg.c',
+ 'src/platforms/sample_tci6498_int_reg.c',
+ '.cdtproject',
+ '.project',
'bios6_edma3_rm_sample.h',
'package.bld',
'package.xs',
diff --git a/packages/ti/sdo/edma3/rm/sample/package.xs b/packages/ti/sdo/edma3/rm/sample/package.xs
print ("Inside EDMA3 RM Sample App getLibs");
/* Prepare variables to form the library path within this package */
- var name = "ti.sdo.edma3.rm.sample.a674";
+ var name = "ti.sdo.edma3.rm.sample";
var lib = "lib/";
+ var target;
/* Devices supported */
var devices = [
'TMS320DA830',
+ 'TMS320CTCI6498',
];
/* Directories for each platform */
var dir = [
'da830/',
+ 'tci6498/',
+ ];
+
+ /* Target name for each supported platform (as coming in the library name) */
+ var targ = [
+ '.a674',
+ '.a64P',
];
for (var i = 0; i < devices.length; i++)
{
/* Choose the selected platform */
lib = lib + dir[i];
+ target = targ[i];
bool = 1;
break;
}
if (bool == 0)
throw new Error('Unexpected value in "platform" parameter')
+ if (java.lang.String(Program.endian).equals("big")) {
+ print ("Big Endian Mode Selected");
+ target += "e";
+ }
+
switch (this.profile) {
case 'debug':
/* enable debug build for debug profile only */
- lib = lib + "Debug/" + name;
+ print("i = " + i + ", target = " + target);
+ lib = lib + "Debug/" + name + target;
break;
default:
/* release profile for everything else */
- lib = lib + "Release/" + name;
+ print("i = " + i + ", target = " + target);
+ lib = lib + "Release/" + name + target;
}
print(" will link with " + this.$name + ":" + lib);
diff --git a/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_da830_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_da830_cfg.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**| **** |**
-**| **** |**
-**| ******o*** |**
-**| ********_///_**** |**
-**| ***** /_//_/ **** |**
-**| ** ** (__/ **** |**
-**| ********* |**
-**| **** |**
-**| *** |**
-**| |**
-**| Copyright (c) 1998-2006 Texas Instruments Incorporated |**
-**| ALL RIGHTS RESERVED |**
-**| |**
-**| Permission is hereby granted to licensees of Texas Instruments |**
-**| Incorporated (TI) products to use this computer program for the sole |**
-**| purpose of implementing a licensee product based on TI products. |**
-**| No other rights to reproduce, use, or disseminate this computer |**
-**| program, whether in part or in whole, are granted. |**
-**| |**
-**| TI makes no representation or warranties with respect to the |**
-**| performance of this computer program, and specifically disclaims |**
-**| any responsibility for any damages, special or consequential, |**
-**| connected with the use of this program. |**
-**| |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/** \file bios6_edma3_rm_sample_da830_cfg.c
-
- \brief SoC specific EDMA3 hardware related information like number of
- transfer controllers, various interrupt ids etc. It is used while
- interrupts enabling / disabling. It needs to be ported for different
- SoCs.
-
- (C) Copyright 2008, Texas Instruments, Inc
-
- \version 1.0 Anuj Aggarwal - Created
-
- */
-
-#include <ti/sdo/edma3/rm/edma3_rm.h>
-
-
-/* DA830 Specific EDMA3 Information */
-
-/** Number of Event Queues available */
-#define EDMA3_NUM_EVTQUE (2u)
-
-/** Number of Transfer Controllers available */
-#define EDMA3_NUM_TC (2u)
-
-/** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT (8u)
-
-/** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT (56u)
-
-/** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT (57u)
-#define EDMA3_TC1_ERROR_INT (58u)
-#define EDMA3_TC2_ERROR_INT (0u)
-#define EDMA3_TC3_ERROR_INT (0u)
-#define EDMA3_TC4_ERROR_INT (0u)
-#define EDMA3_TC5_ERROR_INT (0u)
-#define EDMA3_TC6_ERROR_INT (0u)
-#define EDMA3_TC7_ERROR_INT (0u)
-
-/**
-* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
-* ECM events (SoC specific). These ECM events come
-* under ECM block XXX (handling those specific ECM events). Normally, block
-* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
-* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
-* is mapped to a specific HWI_INT YYY in the tcf file.
-* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
-* to transfer completion interrupt.
-* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
-* to CC error interrupts.
-* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
-* to TC error interrupts.
-*/
-#define EDMA3_HWI_INT_XFER_COMP (7u)
-#define EDMA3_HWI_INT_CC_ERR (8u)
-#define EDMA3_HWI_INT_TC_ERR (8u)
-
-
-/**
- * \brief Mapping of DMA channels 0-31 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
- /* 31 0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xCF3FFFFFu)
-
-/**
- * \brief Mapping of DMA channels 32-63 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-/* DMA channels 32-63 DOES NOT exist in DA830. */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u)
-
-/* Variable which will be used internally for referring number of Event Queues. */
-unsigned int numEdma3EvtQue = EDMA3_NUM_EVTQUE;
-
-/* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc = EDMA3_NUM_TC;
-
-/**
- * Variable which will be used internally for referring transfer completion
- * interrupt.
- */
-unsigned int ccXferCompInt = EDMA3_CC_XFER_COMPLETION_INT;
-
-/**
- * Variable which will be used internally for referring channel controller's
- * error interrupt.
- */
-unsigned int ccErrorInt = EDMA3_CC_ERROR_INT;
-
-/**
- * Variable which will be used internally for referring transfer controllers'
- * error interrupts.
- */
-unsigned int tcErrorInt[8] = {
- EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
- EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
- EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
- EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT
- };
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
-unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
-unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
-
-
-/* Driver Object Initialization Configuration */
-EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams =
- {
- /** Total number of DMA Channels supported by the EDMA3 Controller */
- 32u,
- /** Total number of QDMA Channels supported by the EDMA3 Controller */
- 8u,
- /** Total number of TCCs supported by the EDMA3 Controller */
- 32u,
- /** Total number of PaRAM Sets supported by the EDMA3 Controller */
- 128u,
- /** Total number of Event Queues in the EDMA3 Controller */
- 2u,
- /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
- 2u,
- /** Number of Regions on this EDMA3 controller */
- 4u,
-
- /**
- * \brief Channel mapping existence
- * A value of 0 (No channel mapping) implies that there is fixed association
- * for a channel number to a parameter entry number or, in other words,
- * PaRAM entry n corresponds to channel n.
- */
- 0u,
-
- /** Existence of memory protection feature */
- 0u,
-
- /** Global Register Region of CC Registers */
- (void *)0x01C00000u,
- /** Transfer Controller (TC) Registers */
- {
- (void *)0x01C08000u,
- (void *)0x01C08400u,
- (void *)NULL,
- (void *)NULL,
- (void *)NULL,
- (void *)NULL,
- (void *)NULL,
- (void *)NULL
- },
- /** Interrupt no. for Transfer Completion */
- EDMA3_CC_XFER_COMPLETION_INT,
- /** Interrupt no. for CC Error */
- EDMA3_CC_ERROR_INT,
- /** Interrupt no. for TCs Error */
- {
- EDMA3_TC0_ERROR_INT,
- EDMA3_TC1_ERROR_INT,
- EDMA3_TC2_ERROR_INT,
- EDMA3_TC3_ERROR_INT,
- EDMA3_TC4_ERROR_INT,
- EDMA3_TC5_ERROR_INT,
- EDMA3_TC6_ERROR_INT,
- EDMA3_TC7_ERROR_INT
- },
-
- /**
- * \brief EDMA3 TC priority setting
- *
- * User can program the priority of the Event Queues
- * at a system-wide level. This means that the user can set the
- * priority of an IO initiated by either of the TCs (Transfer Controllers)
- * relative to IO initiated by the other bus masters on the
- * device (ARM, DSP, USB, etc)
- */
- {
- 0u,
- 1u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
- },
- /**
- * \brief To Configure the Threshold level of number of events
- * that can be queued up in the Event queues. EDMA3CC error register
- * (CCERR) will indicate whether or not at any instant of time the
- * number of events queued up in any of the event queues exceeds
- * or equals the threshold/watermark value that is set
- * in the queue watermark threshold register (QWMTHRA).
- */
- {
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
- },
-
- /**
- * \brief To Configure the Default Burst Size (DBS) of TCs.
- * An optimally-sized command is defined by the transfer controller
- * default burst size (DBS). Different TCs can have different
- * DBS values. It is defined in Bytes.
- */
- {
- 16u,
- 16u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u,
- 0u
- },
-
- /**
- * \brief Mapping from each DMA channel to a Parameter RAM set,
- * if it exists, otherwise of no use.
- */
- {
- 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
- 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
- /* DMA channels 32-63 DOES NOT exist in DA830. */
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
- EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
- },
-
- /**
- * \brief Mapping from each DMA channel to a TCC. This specific
- * TCC code will be returned when the transfer is completed
- * on the mapped channel.
- */
- {
- 0u, 1u, 2u, 3u,
- 4u, 5u, 6u, 7u,
- 8u, 9u, 10u, 11u,
- 12u, 13u, 14u, 15u,
- 16u, 17u, 18u, 19u,
- 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
- 24u, 25u, 26u, 27u,
- EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31,
- /* DMA channels 32-63 DOES NOT exist in DA830. */
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
- EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
- },
-
- /**
- * \brief Mapping of DMA channels to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- */
- {
- EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
- EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
- }
- };
-
-
-/* Driver Instance Initialization Configuration */
-EDMA3_RM_InstanceInitConfig sampleInstInitConfig =
- {
- /* Resources owned by Region 1 */
- /* ownPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* ownDmaChannels */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
-
- /* ownQdmaChannels */
- /* 31 0 */
- {0x000000FFu},
-
- /* ownTccs */
- /* 31 0 63 32 */
- {0xFFFFFFFFu, 0x00000000u},
-
- /* Resources reserved by Region 1 */
- /* resvdPaRAMSets */
- /* 31 0 63 32 95 64 127 96 */
- {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 159 128 191 160 223 192 255 224 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 287 256 319 288 351 320 383 352 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
- /* 415 384 447 416 479 448 511 480 */
- 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
- /* resvdDmaChannels */
- /* 31 0 */
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
- /* 63 32 */
- EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1},
-
- /* resvdQdmaChannels */
- /* 31 0 */
- {0x00000000u},
-
- /* resvdTccs */
- /* 31 0 */
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
- /* 63 32 */
- EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1}
- };
-
-
-/* End of File */
-
-
diff --git a/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_init.c b/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_init.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**| **** |**
-**| **** |**
-**| ******o*** |**
-**| ********_///_**** |**
-**| ***** /_//_/ **** |**
-**| ** ** (__/ **** |**
-**| ********* |**
-**| **** |**
-**| *** |**
-**| |**
-**| Copyright (c) 1998-2006 Texas Instruments Incorporated |**
-**| ALL RIGHTS RESERVED |**
-**| |**
-**| Permission is hereby granted to licensees of Texas Instruments |**
-**| Incorporated (TI) products to use this computer program for the sole |**
-**| purpose of implementing a licensee product based on TI products. |**
-**| No other rights to reproduce, use, or disseminate this computer |**
-**| program, whether in part or in whole, are granted. |**
-**| |**
-**| TI makes no representation or warranties with respect to the |**
-**| performance of this computer program, and specifically disclaims |**
-**| any responsibility for any damages, special or consequential, |**
-**| connected with the use of this program. |**
-**| |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/** \file bios6_edma3_rm_sample_init.c
-
- \brief Sample Initialization for the EDMA3 RM for BIOS 6 based
- applications. It should be MANDATORILY done once before EDMA3 usage.
-
- (C) Copyright 2006, Texas Instruments, Inc
-
- \version 1.0 Anuj Aggarwal - Created
-
- */
-
-#include <ti/sysbios/hal/Hwi.h>
-#include <ti/sysbios/ipc/Semaphore.h>
-#include <ti/sysbios/family/c64p/EventCombiner.h>
-
-#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
-
-/** @brief EDMA3 RM Handle, used to call all the RM APIs */
-EDMA3_RM_Handle hEdmaResMgr = NULL;
-
-/** @brief EDMA3 RM Instance specific Semaphore handle */
-static EDMA3_OS_Sem_Handle rmSemHandle = NULL;
-
-
-/**
- * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
- * (Not all TC error ISRs need to be registered, register only for the
- * available Transfer Controllers).
- */
-void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
- {
- &lisrEdma3TC0ErrHandler0,
- &lisrEdma3TC1ErrHandler0,
- &lisrEdma3TC2ErrHandler0,
- &lisrEdma3TC3ErrHandler0,
- &lisrEdma3TC4ErrHandler0,
- &lisrEdma3TC5ErrHandler0,
- &lisrEdma3TC6ErrHandler0,
- &lisrEdma3TC7ErrHandler0,
- };
-
-
-/** To Register the ISRs with the underlying OS, if required. */
-static void registerEdma3Interrupts (void);
-/** To Unregister the ISRs with the underlying OS, if previously registered. */
-static void unregisterEdma3Interrupts (void);
-
-/* External Global Configuration Structure */
-extern EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams;
-
-/* External Instance Specific Configuration Structure */
-extern EDMA3_RM_InstanceInitConfig sampleInstInitConfig;
-
-
-/**
- * \brief EDMA3 Initialization
- *
- * This function initializes the EDMA3 RM and registers the
- * interrupt handlers.
- *
- * \return EDMA3_RM_SOK if success, else error code
- */
- EDMA3_RM_Result edma3init (void)
- {
- unsigned int edma3InstanceId = 0;
- EDMA3_RM_Param initParam;
- EDMA3_RM_Result edma3Result = EDMA3_RM_SOK;
- Semaphore_Params semParams;
- EDMA3_RM_MiscParam miscParam;
-
- if (NULL == hEdmaResMgr)
- {
- /* Configuration structure for the RM */
- initParam.regionId = (EDMA3_RM_RegionId)1u;
- initParam.isMaster = TRUE;
- initParam.rmInstInitConfig = &sampleInstInitConfig;
- initParam.rmSemHandle = NULL;
- initParam.regionInitEnable = TRUE;
- initParam.gblerrCbParams.gblerrCb = (EDMA3_RM_GblErrCallback)NULL;
- initParam.gblerrCbParams.gblerrData = (void *)NULL;
-
- miscParam.isSlave = FALSE;
-
- /* Create EDMA3 RM Object first. */
- edma3Result = EDMA3_RM_create(edma3InstanceId,
- (EDMA3_RM_GblConfigParams *)&sampleEdma3GblCfgParams,
- (void *)&miscParam);
-
- if (edma3Result != EDMA3_RM_SOK)
- {
-#ifdef EDMA3_RM_DEBUG
- EDMA3_RM_PRINTF("edma3init: EDMA3_RM_create FAILED\r\n");
-#endif
- }
- else
- {
- /**
- * RM Object created successfully.
- * Create a semaphore now for RM instance.
- */
- Semaphore_Params_init(&semParams);
-
- edma3Result = edma3OsSemCreate(1, &semParams, &initParam.rmSemHandle );
- if (edma3Result != EDMA3_RM_SOK)
- {
-#ifdef EDMA3_RM_DEBUG
- EDMA3_RM_PRINTF("edma3init: edma3OsSemCreate FAILED\r\n");
-#endif
- }
- else
- {
- /* Save the semaphore handle for future use */
- rmSemHandle = initParam.rmSemHandle;
-
- /* Open the RM Instance */
- hEdmaResMgr = EDMA3_RM_open (edma3InstanceId, (EDMA3_RM_Param *)&initParam, &edma3Result);
-
- if(NULL == hEdmaResMgr)
- {
-#ifdef EDMA3_RM_DEBUG
- EDMA3_RM_PRINTF("edma3init: EDMA3_RM_open FAILED\r\n");
-#endif
- }
- else
- {
- /**
- * Register Interrupt Handlers for various interrupts
- * like transfer completion interrupt, CC error
- * interrupt, TC error interrupts etc, if required.
- */
- registerEdma3Interrupts();
- }
- }
- }
- }
- else
- {
- /* EDMA3 RM already initialized, no need to do that again. */
-#ifdef EDMA3_RM_DEBUG
- EDMA3_RM_PRINTF("edma3init: EDMA3 RM Already Initialized...Init failed\r\n");
-#endif
- edma3Result = EDMA3_RM_E_INVALID_STATE;
- }
-
- return edma3Result;
- }
-
-
-/** To Register the ISRs with the underlying OS, if required. */
-static void registerEdma3Interrupts (void)
- {
- static UInt32 cookie = 0;
- unsigned int numTc = 0;
-
- /* Disabling the global interrupts */
- cookie = Hwi_disable();
-
- /* Enable the Xfer Completion Event Interrupt */
- EventCombiner_dispatchPlug(ccXferCompInt, (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
- NULL, 0);
- EventCombiner_enableEvent(ccXferCompInt);
-
- /* Enable the CC Error Event Interrupt */
- EventCombiner_dispatchPlug(ccErrorInt, (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
- NULL, 0);
- EventCombiner_enableEvent(ccErrorInt);
-
- /* Enable the TC Error Event Interrupt, according to the number of TCs. */
- while (numTc < numEdma3Tc)
- {
- EventCombiner_dispatchPlug(tcErrorInt[numTc],
- (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
- NULL, 0);
- EventCombiner_enableEvent(tcErrorInt[numTc]);
- numTc++;
- }
-
-
- /**
- * Enabling the HWI_ID.
- * EDMA3 interrupts (transfer completion, CC error etc.)
- * correspond to different ECM events (SoC specific). These ECM events come
- * under ECM block XXX (handling those specific ECM events). Normally, block
- * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
- * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
- * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
- * mapped HWI_INT YYY, one should use the corresponding bitmask in the
- * API C64_enableIER(), in which the YYY bit is SET.
- */
- Hwi_enableInterrupt(hwIntXferComp);
- Hwi_enableInterrupt(hwIntCcErr);
- Hwi_enableInterrupt(hwIntTcErr);
-
- /* Restore interrupts */
- Hwi_restore(cookie);
- }
-
-
-/**
- * \brief EDMA3 De-initialization
- *
- * This function removes the EDMA3 RM Instance and unregisters the
- * interrupt handlers. It also deletes the RM Object.
- *
- * \return EDMA3_RM_SOK if success, else error code
- */
- EDMA3_RM_Result edma3deinit (void)
- {
- unsigned int edmaInstanceId = 0;
- EDMA3_RM_Result edma3Result = EDMA3_RM_SOK;
-
- /* Unregister Interrupt Handlers first */
- unregisterEdma3Interrupts();
-
- /* Delete the semaphore */
- edma3Result = edma3OsSemDelete (rmSemHandle);
- if (EDMA3_RM_SOK != edma3Result )
- {
-#ifdef EDMA3_RM_DEBUG
- EDMA3_RM_PRINTF("edma3deinit: edma3OsSemDelete FAILED\r\n");
-#endif
- }
- else
- {
- /* Make the semaphore handle as NULL. */
- rmSemHandle = NULL;
-
- /* Now, close the EDMA3 RM Instance */
- edma3Result = EDMA3_RM_close (hEdmaResMgr, NULL);
- if (EDMA3_RM_SOK != edma3Result )
- {
-#ifdef EDMA3_RM_DEBUG
- EDMA3_RM_PRINTF("edma3deinit: EDMA3_RM_close FAILED\r\n");
-#endif
- }
- else
- {
- /* Make the RM handle as NULL. */
- hEdmaResMgr = NULL;
-
- /* Now, delete the EDMA3 RM Object */
- edma3Result = EDMA3_RM_delete (edmaInstanceId, NULL);
- if (EDMA3_RM_SOK != edma3Result )
- {
-#ifdef EDMA3_RM_DEBUG
- EDMA3_RM_PRINTF("edma3deinit: EDMA3_RM_delete FAILED\r\n");
-#endif
- }
- else
- {
-#ifdef EDMA3_RM_DEBUG
- EDMA3_RM_PRINTF("edma3deinit: EDMA3 Deinitialization" \
- " Completed...\r\n");
-#endif
- }
- }
- }
-
- return edma3Result;
- }
-
-
-/** To Unregister the ISRs with the underlying OS, if previously registered. */
-static void unregisterEdma3Interrupts (void)
- {
- static UInt32 cookie = 0;
- unsigned int numTc = 0;
-
- /* Disabling the global interrupts */
- cookie = Hwi_disable();
-
- /* Disable the Xfer Completion Event Interrupt */
- EventCombiner_disableEvent(ccXferCompInt);
-
- /* Disable the CC Error Event Interrupt */
- EventCombiner_disableEvent(ccErrorInt);
-
- /* Enable the TC Error Event Interrupt, according to the number of TCs. */
- while (numTc < numEdma3Tc)
- {
- EventCombiner_disableEvent(tcErrorInt[numTc]);
- numTc++;
- }
-
- /* Restore interrupts */
- Hwi_restore(cookie);
- }
-
-/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_da830_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_da830_cfg.c
--- /dev/null
@@ -0,0 +1,765 @@
+/*
+ * sample_da830_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+#if 0
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+#endif
+ return 1;
+ }
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ (void) dspNum;
+
+ return 1;
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle rmSemHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET (128u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC (32u)
+/** Number of Event Queues available */
+#define EDMA3_NUM_EVTQUE (2u)
+/** Number of Transfer Controllers available */
+#define EDMA3_NUM_TC (2u)
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT (8u)
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT (56u)
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT (57u)
+#define EDMA3_TC1_ERROR_INT (58u)
+#define EDMA3_TC2_ERROR_INT (0u)
+#define EDMA3_TC3_ERROR_INT (0u)
+#define EDMA3_TC4_ERROR_INT (0u)
+#define EDMA3_TC5_ERROR_INT (0u)
+#define EDMA3_TC6_ERROR_INT (0u)
+#define EDMA3_TC7_ERROR_INT (0u)
+
+/**
+* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+* ECM events (SoC specific). These ECM events come
+* under ECM block XXX (handling those specific ECM events). Normally, block
+* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+* is mapped to a specific HWI_INT YYY in the tcf file.
+* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+* to transfer completion interrupt.
+* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+* to CC error interrupts.
+* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+* to TC error interrupts.
+*/
+#define EDMA3_HWI_INT_XFER_COMP (7u)
+#define EDMA3_HWI_INT_CC_ERR (8u)
+#define EDMA3_HWI_INT_TC_ERR (8u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+ /* 31 0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xCF3FFFFFu)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in DA830. */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x0u)
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ 0u, EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
+ };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
+ {
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+ }
+ };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
+unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
+unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
+
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 32u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 32u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 4u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 0u,
+
+ /** Existence of memory protection feature */
+ 0u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x01C00000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x01C08000u,
+ (void *)0x01C08400u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ EDMA3_CC_XFER_COMPLETION_INT,
+ /** Interrupt no. for CC Error */
+ EDMA3_CC_ERROR_INT,
+ /** Interrupt no. for TCs Error */
+ {
+ EDMA3_TC0_ERROR_INT,
+ EDMA3_TC1_ERROR_INT,
+ EDMA3_TC2_ERROR_INT,
+ EDMA3_TC3_ERROR_INT,
+ EDMA3_TC4_ERROR_INT,
+ EDMA3_TC5_ERROR_INT,
+ EDMA3_TC6_ERROR_INT,
+ EDMA3_TC7_ERROR_INT
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ /* DMA channels 32-63 DOES NOT exist in DA830. */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u,
+ 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u,
+ 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 24u, 25u, 26u, 27u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 30, 31,
+ /* DMA channels 32-63 DOES NOT exist in DA830. */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
+ },
+ },
+ };
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000FFu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFFFFFFu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 */
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+ /* 63 32 */
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 */
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+ /* 63 32 */
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1}
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
+
+/* End of File */
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_da830_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_da830_int_reg.c
--- /dev/null
@@ -0,0 +1,153 @@
+/*
+ * sample_da830_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/ipc/Semaphore.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+// #include <stdio.h>
+/**
+ * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+ * (Not all TC error ISRs need to be registered, register only for the
+ * available Transfer Controllers).
+ */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp;
+extern unsigned int hwIntCcErr;
+extern unsigned int hwIntTcErr;
+
+extern unsigned int dsp_num;
+
+/** To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ unsigned int numTc = 0;
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Enable the Xfer Completion Event Interrupt */
+ EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+ (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
+ NULL, 1);
+ EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+ /* Enable the CC Error Event Interrupt */
+ EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
+ (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
+ NULL, 1);
+ EventCombiner_enableEvent(ccErrorInt[edma3Id]);
+
+ /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
+ (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
+ NULL, 1);
+ EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
+ numTc++;
+ }
+
+ /**
+ * Enabling the HWI_ID.
+ * EDMA3 interrupts (transfer completion, CC error etc.)
+ * correspond to different ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+ * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+ * API C64_enableIER(), in which the YYY bit is SET.
+ */
+ Hwi_enableInterrupt(hwIntXferComp);
+ Hwi_enableInterrupt(hwIntCcErr);
+ Hwi_enableInterrupt(hwIntTcErr);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ unsigned int numTc = 0;
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Disable the Xfer Completion Event Interrupt */
+ EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+ /* Disable the CC Error Event Interrupt */
+ EventCombiner_disableEvent(ccErrorInt[edma3Id]);
+
+ /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
+ numTc++;
+ }
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6498_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6498_cfg.c
--- /dev/null
@@ -0,0 +1,1773 @@
+/*
+ * sample_tci6498_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES 3u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS 4u
+//const unsigned int numDsps = NUM_DSPS;
+
+#define CGEM_REG_START (0x01800000)
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+ {
+ volatile unsigned int *addr;
+ unsigned int core_no;
+
+ /* Identify the core number */
+ addr = (unsigned int *)(CGEM_REG_START+0x40000);
+ core_no = ((*addr) & 0x000F0000)>>16;
+
+ return core_no;
+ }
+
+/** Whether global configuration required for EDMA3 or not.
+ * This configuration should be done only once for the EDMA3 hardware by
+ * any one of the masters (i.e. DSPs).
+ * It can be changed depending on the use-case.
+ */
+unsigned int gblCfgReqdArray [NUM_DSPS] = {
+ 0, /* DSP#0 is Master, will do the global init */
+ 1, /* DSP#1 is Slave, will not do the global init */
+ 1, /* DSP#2 is Slave, will not do the global init */
+ 1, /* DSP#3 is Slave, will not do the global init */
+ };
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+ {
+ return gblCfgReqdArray[dspNum];
+ }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle rmSemHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
+
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt. Completion interrupts for all the shadow regions and all the
+ * EDMA3 controllers are captured since it is a multi-DSP platform.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+ {
+ 38u, 39u, 40u, 41u,
+ 42u, 43u, 44u, 45u,
+ },
+ {
+ 8u, 9u, 10u, 11u,
+ 12u, 13u, 14u, 15u,
+ },
+ {
+ 24u, 25u, 26u, 27u,
+ 28u, 29u, 30u, 31u,
+ },
+ };
+
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
+ {
+ 34u, 35u, 0u, 0u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 2u, 3u, 4u, 5u,
+ 0u, 0u, 0u, 0u,
+ },
+ {
+ 18u, 19u, 20u, 21u,
+ 0u, 0u, 0u, 0u,
+ },
+ };
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00003333u,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 8u,
+ 8u,
+ 8u,
+ 8u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x3FFF3FFFu,
+ 0x3FFF3FFFu
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 8u,
+ 8u,
+ 8u,
+ 8u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+ 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x3FFF3FFFu,
+ 0x3FFF3FFFu
+ }
+ },
+ };
+
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+ {
+ /* EDMA3 INSTANCE# 0 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000000Fu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000003u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000000Fu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 */
+ {0x00000003u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 */
+ {0x00000003u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x000000F0u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Cu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x000000F0u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000030u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000F00u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000030u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000F00u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000300u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000F000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000F000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00003000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 1 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000003u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Cu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000030u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+
+ /* EDMA3 INSTANCE# 2 */
+ {
+ /* Resources owned/reserved by region 0 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 159 128 191 160 223 192 255 224 */
+ 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000003u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x0000FFFFu, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00003FFFu, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 1 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 287 256 319 288 351 320 383 352 */
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x0000000Cu},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0xFFFF0000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x3FFF0000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 2 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000030u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x0000FFFFu},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00003FFFu},
+ },
+
+ /* Resources owned/reserved by region 3 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x000000C0u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0xFFFF0000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x3FFF0000u},
+ },
+
+ /* Resources owned/reserved by region 4 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 5 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 6 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+
+ /* Resources owned/reserved by region 7 */
+ {
+ /* ownPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* ownDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* ownQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* ownTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdPaRAMSets */
+ /* 31 0 63 32 95 64 127 96 */
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 159 128 191 160 223 192 255 224 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 287 256 319 288 351 320 383 352 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+ /* 415 384 447 416 479 448 511 480 */
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+ /* resvdDmaChannels */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+
+ /* resvdQdmaChannels */
+ /* 31 0 */
+ {0x00000000u},
+
+ /* resvdTccs */
+ /* 31 0 63 32 */
+ {0x00000000u, 0x00000000u},
+ },
+ },
+ };
+
+/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6498_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6498_int_reg.c
--- /dev/null
@@ -0,0 +1,158 @@
+/*
+ * sample_tci6498_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/ipc/Semaphore.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/tci6498/CpIntc.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+ {
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
+ };
+
+unsigned int hwiInterrupt = 8;
+
+/* Host interrupts for transfer completion */
+//unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
+unsigned int ccXferHostInt[3][4] = {
+ {0u, 16u, 32u, 48u},
+ {1u, 17u, 33u, 49u},
+ {2u, 18u, 34u, 50u},
+ };
+unsigned int edma3ErrHostInt[3][4] = {
+ {3u, 19u, 35u, 51u},
+ {4u, 20u, 36u, 52u},
+ {5u, 21u, 37u, 53u},
+ };
+
+
+extern unsigned int dsp_num;
+
+/** To Register the ISRs with the underlying OS, if required */
+void registerEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+ unsigned int numTc = 0;
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+ lisrEdma3ComplHandler0,
+ edma3Id,
+ TRUE);
+ CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num],
+ ccXferHostInt[edma3Id][dsp_num]);
+ CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ ccXferHostInt[edma3Id][dsp_num], TRUE);
+ EventCombiner_enableEvent(eventId);
+
+ /* CC Error ISR */
+ CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(0, ccErrorInt[edma3Id],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ /* TC Error ISR */
+ while (numTc < numEdma3Tc[edma3Id])
+ {
+ CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
+ (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
+ edma3Id, TRUE);
+ CpIntc_mapSysIntToHostInt(0, tcErrorInt[edma3Id][numTc],
+ edma3ErrHostInt[edma3Id][dsp_num]);
+ numTc++;
+ }
+ /* Enable the host interrupt which is common for both CC and TC error */
+ CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
+ edma3ErrHostInt[edma3Id][dsp_num], TRUE);
+ EventCombiner_enableEvent(eventId);
+
+ Hwi_enableInterrupt(hwiInterrupt);
+
+ /* enable the 'global' switch */
+ CpIntc_enableAllHostInts(0);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+ {
+ static UInt32 cookie = 0;
+ Int eventId = 0; /* GEM event id */
+
+ /* Disabling the global interrupts */
+ cookie = Hwi_disable();
+
+ /* Transfer completion ISR */
+ CpIntc_disableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* CC/TC Error ISR */
+ CpIntc_disableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
+ eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
+ EventCombiner_disableEvent(eventId);
+
+ /* Restore interrupts */
+ Hwi_restore(cookie);
+ }
+
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_cs.c b/packages/ti/sdo/edma3/rm/sample/src/sample_cs.c
old mode 100644 (file)
new mode 100755 (executable)
similarity index 71%
rename from packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_cs.c
rename to packages/ti/sdo/edma3/rm/sample/src/sample_cs.c
index ed83e91..d9eb756
new mode 100755 (executable)
similarity index 71%
rename from packages/ti/sdo/edma3/rm/sample/src/bios6_edma3_rm_sample_cs.c
rename to packages/ti/sdo/edma3/rm/sample/src/sample_cs.c
index ed83e91..d9eb756
-/*******************************************************************************
-**+--------------------------------------------------------------------------+**
-**| **** |**
-**| **** |**
-**| ******o*** |**
-**| ********_///_**** |**
-**| ***** /_//_/ **** |**
-**| ** ** (__/ **** |**
-**| ********* |**
-**| **** |**
-**| *** |**
-**| |**
-**| Copyright (c) 1998-2006 Texas Instruments Incorporated |**
-**| ALL RIGHTS RESERVED |**
-**| |**
-**| Permission is hereby granted to licensees of Texas Instruments |**
-**| Incorporated (TI) products to use this computer program for the sole |**
-**| purpose of implementing a licensee product based on TI products. |**
-**| No other rights to reproduce, use, or disseminate this computer |**
-**| program, whether in part or in whole, are granted. |**
-**| |**
-**| TI makes no representation or warranties with respect to the |**
-**| performance of this computer program, and specifically disclaims |**
-**| any responsibility for any damages, special or consequential, |**
-**| connected with the use of this program. |**
-**| |**
-**+--------------------------------------------------------------------------+**
-*******************************************************************************/
-
-/** \file bios6_edma3_rm_sample_cs.c
-
- \brief Sample functions showing the implementation of Critical section
- entry/exit routines and various semaphore related routines (all OS
- depenedent). These implementations MUST be provided by the user /
- application, using the EDMA3 Resource Manager, for its
- correct functioning.
-
- (C) Copyright 2006, Texas Instruments, Inc
-
- \version 1.0 Anuj Aggarwal - Created
-
- */
-
-#include <ti/sysbios/family/c64p/EventCombiner.h>
-#include <ti/sysbios/hal/Hwi.h>
-#include <ti/sysbios/knl/Task.h>
-#include <ti/sysbios/ipc/Semaphore.h>
-
-#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
-
-
-
-/**
- * \brief EDMA3 OS Protect Entry
- *
- * This function saves the current state of protection in 'intState'
- * variable passed by caller, if the protection level is
- * EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of
- * protection.
- * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and
- * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored,
- * and the requested interrupt is disabled.
- * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the
- * Transfer Controller number whose interrupt needs to be disabled.
- *
- * \param level is numeric identifier of the desired degree of protection.
- * \param intState is memory location where current state of protection is
- * saved for future use while restoring it via edma3OsProtectExit() (Only
- * for EDMA3_OS_PROTECT_INTERRUPT protection level).
- * \return None
- */
-void edma3OsProtectEntry (int level, unsigned int *intState)
- {
- if (((level == EDMA3_OS_PROTECT_INTERRUPT)
- || (level == EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR))
- && (intState == NULL))
- {
- return;
- }
- else
- {
- switch (level)
- {
- /* Disable all (global) interrupts */
- case EDMA3_OS_PROTECT_INTERRUPT :
- *intState = Hwi_disable();
- break;
-
- /* Disable scheduler */
- case EDMA3_OS_PROTECT_SCHEDULER :
- Task_disable();
- break;
-
- /* Disable EDMA3 transfer completion interrupt only */
- case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION :
- EventCombiner_disableEvent(ccXferCompInt);
- break;
-
- /* Disable EDMA3 CC error interrupt only */
- case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR :
- EventCombiner_disableEvent(ccErrorInt);
- break;
-
- /* Disable EDMA3 TC error interrupt only */
- case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR :
- switch (*intState)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- /* Fall through... */
- /* Disable the corresponding interrupt */
- EventCombiner_disableEvent(tcErrorInt[*intState]);
- break;
-
- default:
- break;
- }
-
- break;
-
- default:
- break;
- }
- }
- }
-
-
-/**
- * \brief EDMA3 OS Protect Exit
- *
- * This function undoes the protection enforced to original state
- * as is specified by the variable 'intState' passed, if the protection
- * level is EDMA3_OS_PROTECT_INTERRUPT.
- * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and
- * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored,
- * and the requested interrupt is enabled.
- * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the
- * Transfer Controller number whose interrupt needs to be enabled.
- * \param level is numeric identifier of the desired degree of protection.
- * \param intState is original state of protection at time when the
- * corresponding edma3OsProtectEntry() was called (Only
- * for EDMA3_OS_PROTECT_INTERRUPT protection level).
- * \return None
- */
-void edma3OsProtectExit (int level, unsigned int intState)
- {
- switch (level)
- {
- /* Enable all (global) interrupts */
- case EDMA3_OS_PROTECT_INTERRUPT :
- Hwi_restore(intState);
- break;
-
- /* Enable scheduler */
- case EDMA3_OS_PROTECT_SCHEDULER :
- Task_enable();
- break;
-
- /* Enable EDMA3 transfer completion interrupt only */
- case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION :
- EventCombiner_enableEvent(ccXferCompInt);
- break;
-
- /* Enable EDMA3 CC error interrupt only */
- case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR :
- EventCombiner_enableEvent(ccErrorInt);
- break;
-
- /* Enable EDMA3 TC error interrupt only */
- case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR :
- switch (intState)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- /* Fall through... */
- /* Enable the corresponding interrupt */
- EventCombiner_enableEvent(tcErrorInt[intState]);
- break;
-
- default:
- break;
- }
-
- break;
-
- default:
- break;
- }
- }
-
-
-/**
- * Counting Semaphore related functions (OS dependent) should be
- * called/implemented by the application. A handle to the semaphore
- * is required while opening the resource manager instance.
- */
-
-/**
- * \brief EDMA3 OS Semaphore Create
- *
- * This function creates a counting semaphore with specified
- * attributes and initial value. It should be used to create a semaphore
- * with initial value as '1'. The semaphore is then passed by the user
- * to the EDMA3 RM for proper sharing of resources.
- * \param initVal [IN] is initial value for semaphore
- * \param semParams [IN] is the semaphore attributes.
- * \param hSem [OUT] is location to recieve the handle to just created
- * semaphore
- * \return EDMA3_RM_SOK if succesful, else a suitable error code.
- */
-EDMA3_RM_Result edma3OsSemCreate(int initVal,
- const Semaphore_Params *semParams,
- EDMA3_OS_Sem_Handle *hSem)
- {
- EDMA3_RM_Result semCreateResult = EDMA3_RM_SOK;
-
- if(NULL == hSem)
- {
- semCreateResult = EDMA3_RM_E_INVALID_PARAM;
- }
- else
- {
- *hSem = (EDMA3_OS_Sem_Handle)Semaphore_create(initVal, semParams, NULL);
- if ( (*hSem) == NULL )
- {
- semCreateResult = EDMA3_RM_E_SEMAPHORE;
- }
- }
-
- return semCreateResult;
- }
-
-
-/**
- * \brief EDMA3 OS Semaphore Delete
- *
- * This function deletes or removes the specified semaphore
- * from the system. Associated dynamically allocated memory
- * if any is also freed up.
- * \param hSem [IN] handle to the semaphore to be deleted
- * \return EDMA3_RM_SOK if succesful else a suitable error code
- */
-EDMA3_RM_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem)
- {
- EDMA3_RM_Result semDeleteResult = EDMA3_RM_SOK;
-
- if(NULL == hSem)
- {
- semDeleteResult = EDMA3_RM_E_INVALID_PARAM;
- }
- else
- {
- Semaphore_delete(hSem);
- }
-
- return semDeleteResult;
- }
-
-
-/**
- * \brief EDMA3 OS Semaphore Take
- *
- * This function takes a semaphore token if available.
- * If a semaphore is unavailable, it blocks currently
- * running thread in wait (for specified duration) for
- * a free semaphore.
- * \param hSem [IN] is the handle of the specified semaphore
- * \param mSecTimeout [IN] is wait time in milliseconds
- * \return EDMA3_RM_Result if successful else a suitable error code
- */
-EDMA3_RM_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int mSecTimeout)
- {
- EDMA3_RM_Result semTakeResult = EDMA3_RM_SOK;
- unsigned short semPendResult;
-
- if(NULL == hSem)
- {
- semTakeResult = EDMA3_RM_E_INVALID_PARAM;
- }
- else
- {
- semPendResult = Semaphore_pend(hSem, mSecTimeout);
- if (semPendResult == FALSE)
- {
- semTakeResult = EDMA3_RM_E_SEMAPHORE;
- }
- }
-
- return semTakeResult;
- }
-
-
-/**
- * \brief EDMA3 OS Semaphore Give
- *
- * This function gives or relinquishes an already
- * acquired semaphore token
- * \param hSem [IN] is the handle of the specified semaphore
- * \return EDMA3_RM_Result if successful else a suitable error code
- */
-EDMA3_RM_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem)
- {
- EDMA3_RM_Result semGiveResult = EDMA3_RM_SOK;
-
- if(NULL == hSem)
- {
- semGiveResult = EDMA3_RM_E_INVALID_PARAM;
- }
- else
- {
- Semaphore_post(hSem);
- }
-
- return semGiveResult;
- }
-
-
-
-
-
+/*\r
+ * sample_cs.c\r
+ *\r
+ * Sample functions showing the implementation of critical section entry/exit\r
+ * routines and various semaphore related routines (all OS depenedent). These\r
+ * implementations MUST be provided by the user / application, using the EDMA3\r
+ * Resource Manager, for its correct functioning.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include <ti/sysbios/family/c64p/EventCombiner.h>\r
+#include <ti/sysbios/hal/Hwi.h>\r
+#include <ti/sysbios/knl/Task.h>\r
+#include <ti/sysbios/ipc/Semaphore.h>\r
+\r
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>\r
+\r
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];\r
+extern unsigned int ccErrorInt[];\r
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];\r
+\r
+/**\r
+ * DSP instance number on which the executable is running. Its value is\r
+ * determined by reading the processor specific register DNUM.\r
+ */\r
+extern unsigned int dsp_num;\r
+\r
+/**\r
+ * \brief EDMA3 OS Protect Entry\r
+ *\r
+ * This function saves the current state of protection in 'intState'\r
+ * variable passed by caller, if the protection level is\r
+ * EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of\r
+ * protection.\r
+ * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and\r
+ * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored,\r
+ * and the requested interrupt is disabled.\r
+ * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the\r
+ * Transfer Controller number whose interrupt needs to be disabled.\r
+ *\r
+ * \param level is numeric identifier of the desired degree of protection.\r
+ * \param intState is memory location where current state of protection is\r
+ * saved for future use while restoring it via edma3OsProtectExit() (Only\r
+ * for EDMA3_OS_PROTECT_INTERRUPT protection level).\r
+ * \return None\r
+ */\r
+void edma3OsProtectEntry (unsigned int edma3InstanceId, \r
+ int level, unsigned int *intState)\r
+ {\r
+ if (((level == EDMA3_OS_PROTECT_INTERRUPT)\r
+ || (level == EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR))\r
+ && (intState == NULL))\r
+ {\r
+ return;\r
+ }\r
+ else\r
+ {\r
+ switch (level)\r
+ {\r
+ /* Disable all (global) interrupts */\r
+ case EDMA3_OS_PROTECT_INTERRUPT :\r
+ *intState = Hwi_disable();\r
+ break;\r
+\r
+ /* Disable scheduler */\r
+ case EDMA3_OS_PROTECT_SCHEDULER :\r
+ Task_disable();\r
+ break;\r
+\r
+ /* Disable EDMA3 transfer completion interrupt only */\r
+ case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION :\r
+ EventCombiner_disableEvent(ccXferCompInt[edma3InstanceId][dsp_num]);\r
+ break;\r
+\r
+ /* Disable EDMA3 CC error interrupt only */\r
+ case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR :\r
+ EventCombiner_disableEvent(ccErrorInt[edma3InstanceId]);\r
+ break;\r
+\r
+ /* Disable EDMA3 TC error interrupt only */\r
+ case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR :\r
+ switch (*intState)\r
+ {\r
+ case 0:\r
+ case 1:\r
+ case 2:\r
+ case 3:\r
+ case 4:\r
+ case 5:\r
+ case 6:\r
+ case 7:\r
+ /* Fall through... */\r
+ /* Disable the corresponding interrupt */\r
+ EventCombiner_disableEvent(tcErrorInt[edma3InstanceId][*intState]);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+\r
+/**\r
+ * \brief EDMA3 OS Protect Exit\r
+ *\r
+ * This function undoes the protection enforced to original state\r
+ * as is specified by the variable 'intState' passed, if the protection\r
+ * level is EDMA3_OS_PROTECT_INTERRUPT.\r
+ * For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and\r
+ * EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored,\r
+ * and the requested interrupt is enabled.\r
+ * For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the\r
+ * Transfer Controller number whose interrupt needs to be enabled.\r
+ * \param level is numeric identifier of the desired degree of protection.\r
+ * \param intState is original state of protection at time when the\r
+ * corresponding edma3OsProtectEntry() was called (Only\r
+ * for EDMA3_OS_PROTECT_INTERRUPT protection level).\r
+ * \return None\r
+ */\r
+void edma3OsProtectExit (unsigned int edma3InstanceId,\r
+ int level, unsigned int intState)\r
+ {\r
+ switch (level)\r
+ {\r
+ /* Enable all (global) interrupts */\r
+ case EDMA3_OS_PROTECT_INTERRUPT :\r
+ Hwi_restore(intState);\r
+ break;\r
+\r
+ /* Enable scheduler */\r
+ case EDMA3_OS_PROTECT_SCHEDULER :\r
+ Task_enable();\r
+ break;\r
+\r
+ /* Enable EDMA3 transfer completion interrupt only */\r
+ case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION :\r
+ EventCombiner_enableEvent(ccXferCompInt[edma3InstanceId][dsp_num]);\r
+ break;\r
+\r
+ /* Enable EDMA3 CC error interrupt only */\r
+ case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR :\r
+ EventCombiner_enableEvent(ccErrorInt[edma3InstanceId]);\r
+ break;\r
+\r
+ /* Enable EDMA3 TC error interrupt only */\r
+ case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR :\r
+ switch (intState)\r
+ {\r
+ case 0:\r
+ case 1:\r
+ case 2:\r
+ case 3:\r
+ case 4:\r
+ case 5:\r
+ case 6:\r
+ case 7:\r
+ /* Fall through... */\r
+ /* Enable the corresponding interrupt */\r
+ EventCombiner_enableEvent(tcErrorInt[edma3InstanceId][intState]);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+\r
+\r
+/**\r
+ * Counting Semaphore related functions (OS dependent) should be\r
+ * called/implemented by the application. A handle to the semaphore\r
+ * is required while opening the resource manager instance.\r
+ */\r
+\r
+/**\r
+ * \brief EDMA3 OS Semaphore Create\r
+ *\r
+ * This function creates a counting semaphore with specified\r
+ * attributes and initial value. It should be used to create a semaphore\r
+ * with initial value as '1'. The semaphore is then passed by the user\r
+ * to the EDMA3 RM for proper sharing of resources.\r
+ * \param initVal [IN] is initial value for semaphore\r
+ * \param semParams [IN] is the semaphore attributes.\r
+ * \param hSem [OUT] is location to recieve the handle to just created\r
+ * semaphore\r
+ * \return EDMA3_RM_SOK if succesful, else a suitable error code.\r
+ */\r
+EDMA3_RM_Result edma3OsSemCreate(int initVal,\r
+ const Semaphore_Params *semParams,\r
+ EDMA3_OS_Sem_Handle *hSem)\r
+ {\r
+ EDMA3_RM_Result semCreateResult = EDMA3_RM_SOK;\r
+\r
+ if(NULL == hSem)\r
+ {\r
+ semCreateResult = EDMA3_RM_E_INVALID_PARAM;\r
+ }\r
+ else\r
+ {\r
+ *hSem = (EDMA3_OS_Sem_Handle)Semaphore_create(initVal, semParams, NULL);\r
+ if ( (*hSem) == NULL )\r
+ {\r
+ semCreateResult = EDMA3_RM_E_SEMAPHORE;\r
+ }\r
+ }\r
+\r
+ return semCreateResult;\r
+ }\r
+\r
+\r
+/**\r
+ * \brief EDMA3 OS Semaphore Delete\r
+ *\r
+ * This function deletes or removes the specified semaphore\r
+ * from the system. Associated dynamically allocated memory\r
+ * if any is also freed up.\r
+ * \param hSem [IN] handle to the semaphore to be deleted\r
+ * \return EDMA3_RM_SOK if succesful else a suitable error code\r
+ */\r
+EDMA3_RM_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem)\r
+ {\r
+ EDMA3_RM_Result semDeleteResult = EDMA3_RM_SOK;\r
+\r
+ if(NULL == hSem)\r
+ {\r
+ semDeleteResult = EDMA3_RM_E_INVALID_PARAM;\r
+ }\r
+ else\r
+ {\r
+ Semaphore_delete(hSem);\r
+ }\r
+\r
+ return semDeleteResult;\r
+ }\r
+\r
+\r
+/**\r
+ * \brief EDMA3 OS Semaphore Take\r
+ *\r
+ * This function takes a semaphore token if available.\r
+ * If a semaphore is unavailable, it blocks currently\r
+ * running thread in wait (for specified duration) for\r
+ * a free semaphore.\r
+ * \param hSem [IN] is the handle of the specified semaphore\r
+ * \param mSecTimeout [IN] is wait time in milliseconds\r
+ * \return EDMA3_RM_Result if successful else a suitable error code\r
+ */\r
+EDMA3_RM_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int mSecTimeout)\r
+ {\r
+ EDMA3_RM_Result semTakeResult = EDMA3_RM_SOK;\r
+ unsigned short semPendResult;\r
+\r
+ if(NULL == hSem)\r
+ {\r
+ semTakeResult = EDMA3_RM_E_INVALID_PARAM;\r
+ }\r
+ else\r
+ {\r
+ semPendResult = Semaphore_pend(hSem, mSecTimeout);\r
+ if (semPendResult == FALSE)\r
+ {\r
+ semTakeResult = EDMA3_RM_E_SEMAPHORE;\r
+ }\r
+ }\r
+\r
+ return semTakeResult;\r
+ }\r
+\r
+\r
+/**\r
+ * \brief EDMA3 OS Semaphore Give\r
+ *\r
+ * This function gives or relinquishes an already\r
+ * acquired semaphore token\r
+ * \param hSem [IN] is the handle of the specified semaphore\r
+ * \return EDMA3_RM_Result if successful else a suitable error code\r
+ */\r
+EDMA3_RM_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem)\r
+ {\r
+ EDMA3_RM_Result semGiveResult = EDMA3_RM_SOK;\r
+\r
+ if(NULL == hSem)\r
+ {\r
+ semGiveResult = EDMA3_RM_E_INVALID_PARAM;\r
+ }\r
+ else\r
+ {\r
+ Semaphore_post(hSem);\r
+ }\r
+\r
+ return semGiveResult;\r
+ }\r
+\r
+/* End of File */\r
+\r
diff --git a/packages/ti/sdo/edma3/rm/sample/src/sample_init.c b/packages/ti/sdo/edma3/rm/sample/src/sample_init.c
--- /dev/null
@@ -0,0 +1,200 @@
+/*\r
+ * sample_init.c\r
+ *\r
+ * Sample Initialization for the EDMA3 RM for BIOS 6 based applications. It\r
+ * should be MANDATORILY done once before EDMA3 usage.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include <ti/sysbios/hal/Hwi.h>\r
+#include <ti/sysbios/ipc/Semaphore.h>\r
+#include <ti/sysbios/family/c64p/EventCombiner.h>\r
+\r
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>\r
+\r
+/** @brief EDMA3 Driver Instance specific Semaphore handle */\r
+extern EDMA3_OS_Sem_Handle rmSemHandle[];\r
+\r
+/** To Register the ISRs with the underlying OS, if required. */\r
+extern void registerEdma3Interrupts (unsigned int edma3Id);\r
+/** To Unregister the ISRs with the underlying OS, if previously registered. */\r
+extern void unregisterEdma3Interrupts (unsigned int edma3Id);\r
+\r
+/* To find out the DSP# */\r
+extern unsigned short determineProcId();\r
+\r
+/**\r
+ * To check whether the global EDMA3 configuration is required or not.\r
+ * It should be done ONCE by any of the masters present in the system.\r
+ * This function checks whether the global configuration is required by the\r
+ * current master or not. In case of many masters, it should be done only\r
+ * by one of the masters. Hence this function will return TRUE only once\r
+ * and FALSE for all other masters. \r
+ */\r
+extern unsigned short isGblConfigRequired(unsigned int dspNum);\r
+\r
+/**\r
+ * DSP instance number on which the executable is running. Its value is\r
+ * determined by reading the processor specific register DNUM.\r
+ */\r
+unsigned int dsp_num;\r
+\r
+/* Number of EDMA3 controllers present in the system */\r
+extern const unsigned int numEdma3Instances;\r
+\r
+/* External Global Configuration Structure */\r
+extern EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[];\r
+\r
+/* External Instance Specific Configuration Structure */\r
+extern EDMA3_RM_InstanceInitConfig sampleInstInitConfig[][EDMA3_MAX_REGIONS];\r
+\r
+/**\r
+ * \brief EDMA3 Initialization\r
+ *\r
+ * This function initializes the EDMA3 RM and registers the\r
+ * interrupt handlers.\r
+ *\r
+ * \return EDMA3_RM_SOK if success, else error code\r
+ */\r
+EDMA3_RM_Handle edma3init (unsigned int edma3Id, EDMA3_RM_Result *errorCode)\r
+ {\r
+ EDMA3_RM_Param initParam;\r
+ EDMA3_RM_Result edma3Result = EDMA3_RM_SOK;\r
+ Semaphore_Params semParams;\r
+ EDMA3_RM_MiscParam miscParam;\r
+ EDMA3_RM_GblConfigParams *globalConfig = NULL;\r
+ EDMA3_RM_InstanceInitConfig *instanceConfig = NULL;\r
+ EDMA3_RM_Handle hEdmaResMgr = NULL;\r
+\r
+ if ((edma3Id >= numEdma3Instances) || (errorCode == NULL))\r
+ return hEdmaResMgr;\r
+\r
+ /* DSP instance number */\r
+ dsp_num = determineProcId();\r
+\r
+ globalConfig = &sampleEdma3GblCfgParams[edma3Id];\r
+\r
+ /* Configure it as master, if required */\r
+ miscParam.isSlave = isGblConfigRequired(dsp_num);\r
+ \r
+ edma3Result = EDMA3_RM_create (edma3Id, globalConfig ,\r
+ (void *)&miscParam);\r
+\r
+ if (edma3Result == EDMA3_DRV_SOK)\r
+ {\r
+ /**\r
+ * Driver Object created successfully.\r
+ * Create a semaphore now for driver instance.\r
+ */\r
+ Semaphore_Params_init(&semParams);\r
+\r
+ initParam.rmSemHandle = NULL;\r
+ edma3Result = edma3OsSemCreate(1, &semParams, &initParam.rmSemHandle);\r
+ }\r
+\r
+ if (edma3Result == EDMA3_DRV_SOK)\r
+ {\r
+ /* Save the semaphore handle for future use */\r
+ rmSemHandle[edma3Id] = initParam.rmSemHandle;\r
+\r
+ /* configuration structure for the Driver */\r
+ instanceConfig = &sampleInstInitConfig[edma3Id][dsp_num];\r
+\r
+ initParam.isMaster = TRUE;\r
+ /* Choose shadow region according to the DSP# */\r
+ initParam.regionId = (EDMA3_RM_RegionId)dsp_num;\r
+ /* Driver instance specific config NULL */\r
+ initParam.rmInstInitConfig = instanceConfig;\r
+\r
+ initParam.regionInitEnable = TRUE;\r
+ initParam.gblerrCbParams.gblerrCb = (EDMA3_RM_GblErrCallback)NULL;\r
+ initParam.gblerrCbParams.gblerrData = (void *)NULL;\r
+\r
+ /* Open the Driver Instance */\r
+ hEdmaResMgr = EDMA3_RM_open (edma3Id, (EDMA3_RM_Param *)&initParam, \r
+ &edma3Result);\r
+ }\r
+\r
+ if(hEdmaResMgr && (edma3Result == EDMA3_DRV_SOK))\r
+ {\r
+ /**\r
+ * Register Interrupt Handlers for various interrupts\r
+ * like transfer completion interrupt, CC error\r
+ * interrupt, TC error interrupts etc, if required.\r
+ */\r
+ registerEdma3Interrupts(edma3Id);\r
+ }\r
+\r
+ *errorCode = edma3Result; \r
+ return hEdmaResMgr;\r
+ }\r
+\r
+/**\r
+ * \brief EDMA3 De-initialization\r
+ *\r
+ * This function removes the EDMA3 RM Instance and unregisters the\r
+ * interrupt handlers. It also deletes the RM Object.\r
+ *\r
+ * \return EDMA3_RM_SOK if success, else error code\r
+ */\r
+EDMA3_RM_Result edma3deinit (unsigned int edma3Id, EDMA3_RM_Handle hEdmaResMgr)\r
+ {\r
+ EDMA3_RM_Result edma3Result = EDMA3_RM_SOK;\r
+\r
+ /* Unregister Interrupt Handlers first */\r
+ unregisterEdma3Interrupts(edma3Id);\r
+\r
+ /* Delete the semaphore */\r
+ edma3Result = edma3OsSemDelete (rmSemHandle[edma3Id]);\r
+\r
+ if (EDMA3_RM_SOK == edma3Result)\r
+ {\r
+ /* Make the semaphore handle as NULL. */\r
+ rmSemHandle[edma3Id] = NULL;\r
+\r
+ /* Now, close the EDMA3 RM Instance */\r
+ edma3Result = EDMA3_RM_close (hEdmaResMgr, NULL);\r
+ }\r
+ \r
+ if (EDMA3_RM_SOK == edma3Result)\r
+ {\r
+ /* Now, delete the EDMA3 RM Object */\r
+ edma3Result = EDMA3_RM_delete (edma3Id, NULL);\r
+ }\r
+\r
+ return edma3Result;\r
+ }\r
+\r
+/* End of File */\r
+\r