Addition of platform dra72x
authorPrasad Konnur <prasadkonnur@ti.com>
Wed, 5 Mar 2014 09:27:24 +0000 (14:57 +0530)
committerPrasad <prasadkonnur@ti.com>
Tue, 20 May 2014 08:48:57 +0000 (14:18 +0530)
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
32 files changed:
examples/edma3_driver/evmDRA72x_A15/makefile [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_A15/rtsc_config/edma3_drv_bios6_dra72x_a15_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_A15/sample_app/linker.cmd [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_DSP/dsp_timer.c [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_DSP/makefile [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_DSP/rtsc_config/app_mem_seg_placement.cfg [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_DSP/rtsc_config/custom_config.bld [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_DSP/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_DSP/rtsc_config/mem_segment_definition.xs [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_DSP/rtsc_config/platform.xs [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_DSP/sample_app/linker.cmd [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_M4/makefile [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/custom_config.bld [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/mem_segment_definition.xs [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_M4/rtsc_config/platform.xs [new file with mode: 0644]
examples/edma3_driver/evmDRA72x_M4/sample_app/linker.cmd [new file with mode: 0644]
makerules/platform.mk
packages/component.mk
packages/ti/sdo/edma3/drv/sample/makefile
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/sample_arm_cs.c
packages/ti/sdo/edma3/rm/makefile
packages/ti/sdo/edma3/rm/sample/makefile
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_arm_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c [new file with mode: 0644]

diff --git a/examples/edma3_driver/evmDRA72x_A15/makefile b/examples/edma3_driver/evmDRA72x_A15/makefile
new file mode 100644 (file)
index 0000000..fd80a1f
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_arm_dra72x_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files
+#  need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_a15host = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_a15host = rtsc_config/edma3_drv_bios6_dra72x_a15_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
+              qdma_link_test.c
+CFLAGS_LOCAL_COMMON = -DBUILD_DRA72X_MPU
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+#   SRCS_<core/SoC/platform-name> =
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+#     and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evmDRA72x_A15/rtsc_config/edma3_drv_bios6_dra72x_a15_st_sample.cfg b/examples/edma3_driver/evmDRA72x_A15/rtsc_config/edma3_drv_bios6_dra72x_a15_st_sample.cfg
new file mode 100644 (file)
index 0000000..4a79b29
--- /dev/null
@@ -0,0 +1,53 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
+var Startup   = xdc.useModule ("xdc.runtime.Startup");
+var System    = xdc.useModule ("xdc.runtime.System");
+var Log       = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Program     = xdc.useModule("xdc.cfg.Program");
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+var Error = xdc.useModule('xdc.runtime.Error');
+
+//BIOS.libType = BIOS.LibType_Custom;
+/* Heap used when creating semaphore's, TSK's or malloc() ... */
+Program.heap            = 0x1000;
+
+/* ISR/SWI stack        */
+Program.stack           = 0x4000;
+
+Program.sectMap[".cio"] = new Program.SectionSpec();
+Program.sectMap[".cio"].loadSegment = "EXT_RAM";
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+/* MMU/Cache related configurations                                           */
+
+var Cache1  = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
+var Mmu    = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
+var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
+var GnuSupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
+
+/* Enable the cache                                                           */
+Cache1.enableCache = false;
+
+/* Enable the MMU (Required for L1 data caching)                              */
+Mmu.enableMMU = true;
+
+var attrs = new Mmu.DescriptorAttrs();
+Mmu.initDescAttrsMeta(attrs);
+attrs.type = Mmu.DescriptorType_BLOCK;
+attrs.noExecute = true;
+attrs.accPerm = 0;       // R/W at PL1
+attrs.attrIndx = 2;       // Use MAIR0 Byte2
+Mmu.setMAIRMeta(2, 0x04);
+Mmu.setSecondLevelDescMeta(0x43200000, 0x43200000, attrs);
+//Mmu.setSecondLevelDescMeta(0x43400000, 0x43400000, attrs);
+
+Task.initStackFlag = false;
+Task.checkStackFlag = false;
+
+Hwi.initStackFlag = false;
+Hwi.checkStackFlag = false;
\ No newline at end of file
diff --git a/examples/edma3_driver/evmDRA72x_A15/sample_app/linker.cmd b/examples/edma3_driver/evmDRA72x_A15/sample_app/linker.cmd
new file mode 100644 (file)
index 0000000..436a797
--- /dev/null
@@ -0,0 +1,5 @@
+SECTIONS
+{
+    .my_sect_iram > EXT_RAM
+    .my_sect_ddr  > EXT_RAM
+}
diff --git a/examples/edma3_driver/evmDRA72x_DSP/dsp_timer.c b/examples/edma3_driver/evmDRA72x_DSP/dsp_timer.c
new file mode 100644 (file)
index 0000000..5b6bc5a
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * dsp_timer.c
+ *
+ * This file contains the test / demo code to demonstrate the EDMA3 driver
+ * functionality on DSP/BIOS 6.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Clock.h>
+
+/*
+ * mainDsp1TimerTick()   Enable Timer Tick.
+ * The DSP timer does not run when
+ * the host (A15) is halted because of the emulation suspend signal.
+ */
+void mainDsp1TimerTick(UArg arg)
+{
+    Clock_tick();
+}
diff --git a/examples/edma3_driver/evmDRA72x_DSP/makefile b/examples/edma3_driver/evmDRA72x_DSP/makefile
new file mode 100644 (file)
index 0000000..24b4b14
--- /dev/null
@@ -0,0 +1,39 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_tda2xx_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files
+#  need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
+
+CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
+
+PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:DSP_1
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
+              qdma_link_test.c dsp_timer.c
+CFLAGS_LOCAL_COMMON = -DBUILD_TDA2XX_DSP
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+#   SRCS_<core/SoC/platform-name> =
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+#     and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/app_mem_seg_placement.cfg b/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/app_mem_seg_placement.cfg
new file mode 100644 (file)
index 0000000..ceda3f0
--- /dev/null
@@ -0,0 +1,35 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *   @file  app_mem_seg_placement.cfg
+ *
+ *   @brief
+ */
+
+function init()
+{
+    var Program = xdc.useModule('xdc.cfg.Program');
+
+        Program.sectMap[".vecs"]                    = "CODE_CORE_DSP1";
+        Program.sectMap[".text"]                    = "CODE_CORE_DSP1";
+        Program.sectMap[".text:_c_int00"]           = new Program.SectionSpec();
+        Program.sectMap[".text:_c_int00"].loadSegment = "CODE_CORE_DSP1";
+               Program.sectMap[".text:_c_int00"].loadAlign = 0x400;
+        Program.sectMap[".far"]                     = "CODE_CORE_DSP1";
+        Program.sectMap[".cinit"]                   = "CODE_CORE_DSP1";
+        Program.sectMap[".args"]                    = "CODE_CORE_DSP1";
+        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".my_sect_iram"]            = "PRIVATE_DATA_CORE_DSP1";
+        Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_DSP1";
+}
diff --git a/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/custom_config.bld b/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/custom_config.bld
new file mode 100644 (file)
index 0000000..75b856a
--- /dev/null
@@ -0,0 +1,49 @@
+/*
+ *  ======== config.bld ========
+ *  Sample Build configuration script
+ */
+
+/* load the required modules for the configuration */
+
+var platform_xs = xdc.loadCapsule("platform.xs");
+
+/**********************************c66******************************/
+var C66_ELF = xdc.useModule('ti.targets.elf.C66');
+
+C66_ELF.rootDir = java.lang.System.getenv("CGTOOLS_ELF");
+
+C66_ELF.ccOpts.suffix += " -mi10 -mo --symdebug:none -O3";
+
+/* linker options */
+
+C66_ELF.lnkOpts.suffix += " --zero_init=off ";
+C66_ELF.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";
+
+C66_ELF.platforms = ["ti.platforms.evmDRA7XX:DSP_1"];
+
+C66_ELF.platform = C66_ELF.platforms[0];
+/**********************************c66******************************/
+
+/**********************************c66******************************/
+var C66e = xdc.useModule('ti.targets.elf.C66_big_endian');
+
+C66e.rootDir = java.lang.System.getenv("CGTOOLS_ELF");
+
+C66e.ccOpts.suffix += " -mi10 -mo -me --symdebug:none -O3";
+
+/* linker options */
+
+C66e.lnkOpts.suffix += " --zero_init=off ";
+C66e.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";
+
+C66e.platforms = ["ti.platforms.evmDRA7XX:DSP_1"];
+
+C66e.platform = C66e.platforms[0];
+/**********************************c66******************************/
+
+
+/* list interested targets in Build.targets array  */
+Build.targets = [
+                    C66_ELF,
+                    C66e
+                ];
diff --git a/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg b/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
new file mode 100644 (file)
index 0000000..2381124
--- /dev/null
@@ -0,0 +1,53 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
+var halCache = xdc.useModule('ti.sysbios.hal.Cache');
+var InitXbar = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+halCache.CacheProxy = Cache;
+
+/***********************************************
+ *          CLOCK Module Configuraion          *
+ ***********************************************/
+var Clock = xdc.useModule("ti.sysbios.knl.Clock");
+Clock.tickMode = Clock.TickMode_PERIODIC;
+Clock.tickSource = Clock.TickSource_USER;
+
+/* allocate timer 5 to DSP1 */
+var TimerSupport = xdc.useModule('ti.sysbios.family.shared.vayu.TimerSupport');
+TimerSupport.availMask = 0x0020;
+
+/***********************************************
+*           Timer Module Configuraion         *
+***********************************************/
+/* Turn off the timer frequency check. The DSP timer does not run when
+ * the host is halted because of the emulation suspend signal.
+ */
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+
+Timer.intFreq.hi = 0;
+/* system clock runs at 38.4 MHz */
+Timer.intFreq.lo = 38400000;
+
+var timerParams = new Timer.Params();
+timerParams.period = 1000;
+timerParams.twer.ovf_wup_ena = 1;
+timerParams.tiocpCfg.emufree = 1;
+
+Timer.create(5, '&mainDsp1TimerTick', timerParams);
+
+var segPlacement = xdc.loadCapsule("app_mem_seg_placement.cfg");
+segPlacement.init();
diff --git a/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/mem_segment_definition.xs
new file mode 100644 (file)
index 0000000..e617408
--- /dev/null
@@ -0,0 +1,264 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *  ======== mem_segment_definition.xs ========
+ */
+
+
+function getMemSegmentDefinitionIPU_1_0()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_IPU1_0",
+    {
+          name: "CODE_CORE_IPU1_0",
+          base: 0x84000000,
+          len:  0x01000000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",
+    {
+          name: "PRIVATE_DATA_CORE_IPU1_0",
+          base: 0x85000000,
+          len:  0x01800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",
+    {
+          name: "HDVPSS_DESCRIPTOR_NON_CACHED",
+          base: 0xA1800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[6] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    return (memory);
+}
+
+function getMemSegmentDefinitionIPU_1_1()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_IPU1_1",
+    {
+          name: "CODE_CORE_IPU1_1",
+          base: 0x86800000,
+          len:  0x01000000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",
+    {
+          name: "PRIVATE_DATA_CORE_IPU1_1",
+          base: 0x87800000,
+          len:  0x01800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    return (memory);
+}
+
+function getMemSegmentDefinitionDSP_1()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_DSP1",
+    {
+          name: "CODE_CORE_DSP1",
+          base: 0x83100000,
+          len:  0x00700000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_DSP1",
+    {
+          name: "PRIVATE_DATA_CORE_DSP1",
+          base: 0x83800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    return (memory);
+}
+
+function getMemSegmentDefinitionHOST()
+{
+    var memory = new Array();
+
+    memory[8] = ["CODE_CORE_HOST",
+    {
+          name: "CODE_CORE_HOST",
+          base: 0x89000000,
+          len:  0x00800000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[9] = ["PRIVATE_DATA_CORE_HOST",
+    {
+          name: "PRIVATE_DATA_CORE_HOST",
+          base: 0x89800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[10] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[11] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[12] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[13] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    return (memory);
+}
diff --git a/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/platform.xs b/examples/edma3_driver/evmDRA72x_DSP/rtsc_config/platform.xs
new file mode 100644 (file)
index 0000000..4f1b3df
--- /dev/null
@@ -0,0 +1,46 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *  ======== platform.xs ========
+ */
+
+var Build = xdc.useModule('xdc.bld.BuildEnvironment');
+
+var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
+
+Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_0"] =
+{
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
+       codeMemory:"CODE_CORE_IPU1_0",
+       dataMemory:"PRIVATE_DATA_CORE_IPU1_0",
+       stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
+};
+
+Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_1"] =
+{
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
+       codeMemory:"CODE_CORE_IPU1_1",
+       dataMemory:"PRIVATE_DATA_CORE_IPU1_1",
+       stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
+};
+
+Build.platformTable["ti.platforms.evmDRA7XX:DSP_1"] =
+{
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
+    codeMemory:"CODE_CORE_DSP1",
+    dataMemory:"PRIVATE_DATA_CORE_DSP1",
+    stackMemory:"PRIVATE_DATA_CORE_DSP1"
+};
+
+Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
+{
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
+    codeMemory:"CODE_CORE_HOST",
+    dataMemory:"PRIVATE_DATA_CORE_HOST",
+    stackMemory:"PRIVATE_DATA_CORE_HOST"
+};
diff --git a/examples/edma3_driver/evmDRA72x_DSP/sample_app/linker.cmd b/examples/edma3_driver/evmDRA72x_DSP/sample_app/linker.cmd
new file mode 100644 (file)
index 0000000..6ca6627
--- /dev/null
@@ -0,0 +1,7 @@
+SECTIONS
+{
+//     .my_sect_iram  > EXT_RAM
+//     .my_sect_ddr  > EXT_RAM
+}
+
+
diff --git a/examples/edma3_driver/evmDRA72x_M4/makefile b/examples/edma3_driver/evmDRA72x_M4/makefile
new file mode 100644 (file)
index 0000000..a3cf5d8
--- /dev/null
@@ -0,0 +1,47 @@
+# Makefile for edma3 lld app
+ifeq ($(IPUCORE),1)
+APP_NAME = edma3_drv_arm_tda2xx_core1_sample
+else
+APP_NAME = edma3_drv_arm_tda2xx_core0_sample
+endif
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files
+#  need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_m4 = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+ifeq ($(IPUCORE),1)
+XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg
+CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
+PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:IPU_1_1
+else
+XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg
+CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
+PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:IPU_1_0
+endif
+
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
+              qdma_link_test.c
+CFLAGS_LOCAL_COMMON = -DBUILD_TDA2XX_IPU
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+#   SRCS_<core/SoC/platform-name> =
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+#     and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_0.cfg
new file mode 100644 (file)
index 0000000..351c89a
--- /dev/null
@@ -0,0 +1,37 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *   @file  app_mem_seg_placement.cfg
+ *
+ *   @brief
+ */
+
+function init()
+{
+    var Program = xdc.useModule('xdc.cfg.Program');
+
+        Program.sectMap[".text"]                    = "CODE_CORE_IPU1_0";
+        Program.sectMap[".cinit"]                   = "CODE_CORE_IPU1_0";
+        Program.sectMap[".pinit"]                   = "CODE_CORE_IPU1_0";
+        Program.sectMap[".args"]                    = "CODE_CORE_IPU1_0";
+        Program.sectMap[".const"]                   = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".stack"]                   = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_IPU1_0";
+        //BSP memory section placement
+        Program.sectMap[".bss:extMemNonCache:heap"] = "HDVPSS_DESCRIPTOR_NON_CACHED";
+        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".data"]                    = "PRIVATE_DATA_CORE_IPU1_0";
+        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_IPU1_0";
+               Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_IPU1_0";
+
+}
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/app_mem_seg_placement_ipu1_1.cfg
new file mode 100644 (file)
index 0000000..bdd0275
--- /dev/null
@@ -0,0 +1,38 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *   @file  app_mem_seg_placement.cfg
+ *
+ *   @brief
+ */
+
+function init()
+{
+    var Program = xdc.useModule('xdc.cfg.Program');
+        Program.sectMap[".text"]                    = "CODE_CORE_IPU1_1";
+        Program.sectMap[".cinit"]                   = "CODE_CORE_IPU1_1";
+        Program.sectMap[".pinit"]                   = "CODE_CORE_IPU1_1";
+        Program.sectMap[".args"]                    = "CODE_CORE_IPU1_1";
+        Program.sectMap[".const"]                   = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".systemHeap"]              = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".stack"]                   = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".stackMemory"]             = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_IPU1_1";
+        //BSP memory section placement
+        Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".neardata"]                = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".data"]                    = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".plt"]                     = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".far:NDK_MMBUFFER"]        = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".far:NDK_MMBUFFER1"]       = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".far:NDK_OBJMEM"]          = "PRIVATE_DATA_CORE_IPU1_1";
+        Program.sectMap[".far:NDK_PACKETMEM"]       = "PRIVATE_DATA_CORE_IPU1_1";
+               Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_IPU1_1";
+}
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/custom_config.bld b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/custom_config.bld
new file mode 100644 (file)
index 0000000..3c31ec6
--- /dev/null
@@ -0,0 +1,6 @@
+/*
+ *  ======== config.bld ========
+ *  Sample Build configuration script
+ */
+
+var platform_xs = xdc.loadCapsule("platform.xs");
\ No newline at end of file
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg
new file mode 100644 (file)
index 0000000..3872ad7
--- /dev/null
@@ -0,0 +1,74 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
+var Startup   = xdc.useModule ("xdc.runtime.Startup");
+var System    = xdc.useModule ("xdc.runtime.System");
+var Log       = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
+var Error = xdc.useModule('xdc.runtime.Error');
+var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+var Program     = xdc.useModule("xdc.cfg.Program");
+var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
+
+/* ISR/SWI stack        */
+Program.stack           = 0x4000;
+
+/* Heap used when creating semaphore's, TSK's or malloc() ... */
+Program.heap            = 0x15000;
+
+/*Program.sectMap[".ducatiBoot"]          = "L2_RAM";
+Program.sectMap[".bootVecs"]            = "L2_RAM";
+Program.sectMap[".ducatiGates"]         = "L2_RAM";
+*/
+
+/* enable print of exception handing info */
+HwiM3.enableException = true;
+
+/* DSP/BIOS expects this to set to 1 */
+var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.id = 0;
+Core.ipuId = 1;
+/*
+var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;
+M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress;
+*/
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+/* MMU/Cache related configurations                                           */
+var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+
+/* Enable the cache                                                           */
+Cache1.enableCache = true;
+
+//if (Core.id == 0)
+/*{
+       AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
+       AMMU.mediumPages[1].logicalAddress = 0x60000000;
+       AMMU.mediumPages[1].translatedAddress = 0x43300000;
+       AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
+       AMMU.mediumPages[1].size = AMMU.Medium_256K;
+       AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+       AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
+       AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+       AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+}*/
+
+if (Core.id == 1)
+{
+       var GateDualCore = xdc.useModule('ti.sysbios.family.arm.ducati.GateDualCore');
+       GateDualCore.initGates = true;
+}
+
+Task.initStackFlag = false;
+Task.checkStackFlag = false;
+
+Hwi.initStackFlag = false;
+Hwi.checkStackFlag = false;
+
+var segPlacement = xdc.loadCapsule("app_mem_seg_placement_ipu1_0.cfg");
+segPlacement.init();
\ No newline at end of file
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg
new file mode 100644 (file)
index 0000000..aaa9efe
--- /dev/null
@@ -0,0 +1,73 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
+var Startup   = xdc.useModule ("xdc.runtime.Startup");
+var System    = xdc.useModule ("xdc.runtime.System");
+var Log       = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');
+var Error = xdc.useModule('xdc.runtime.Error');
+var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+var Program     = xdc.useModule("xdc.cfg.Program");
+var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
+
+/* ISR/SWI stack        */
+Program.stack           = 0x4000;
+
+/* Heap used when creating semaphore's, TSK's or malloc() ... */
+Program.heap            = 0x15000;
+
+/*Program.sectMap[".ducatiBoot"]          = "L2_RAM";
+Program.sectMap[".bootVecs"]            = "L2_RAM";
+Program.sectMap[".ducatiGates"]         = "L2_RAM";
+*/
+
+/* enable print of exception handing info */
+HwiM3.enableException = true;
+
+/* DSP/BIOS expects this to set to 1 */
+var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.id = 1;
+/*
+var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;
+M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress;
+*/
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+/* MMU/Cache related configurations                                           */
+var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+
+/* Enable the cache                                                           */
+Cache1.enableCache = true;
+
+//if (Core.id == 0)
+/*{
+       AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
+       AMMU.mediumPages[1].logicalAddress = 0x60000000;
+       AMMU.mediumPages[1].translatedAddress = 0x43300000;
+       AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
+       AMMU.mediumPages[1].size = AMMU.Medium_256K;
+       AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+       AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
+       AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+       AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
+}*/
+
+if (Core.id == 1)
+{
+       var GateDualCore = xdc.useModule('ti.sysbios.family.arm.ducati.GateDualCore');
+       GateDualCore.initGates = true;
+}
+
+Task.initStackFlag = false;
+Task.checkStackFlag = false;
+
+Hwi.initStackFlag = false;
+Hwi.checkStackFlag = false;
+
+var segPlacement = xdc.loadCapsule("app_mem_seg_placement_ipu1_1.cfg");
+segPlacement.init();
\ No newline at end of file
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/mem_segment_definition.xs
new file mode 100644 (file)
index 0000000..e617408
--- /dev/null
@@ -0,0 +1,264 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *  ======== mem_segment_definition.xs ========
+ */
+
+
+function getMemSegmentDefinitionIPU_1_0()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_IPU1_0",
+    {
+          name: "CODE_CORE_IPU1_0",
+          base: 0x84000000,
+          len:  0x01000000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",
+    {
+          name: "PRIVATE_DATA_CORE_IPU1_0",
+          base: 0x85000000,
+          len:  0x01800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",
+    {
+          name: "HDVPSS_DESCRIPTOR_NON_CACHED",
+          base: 0xA1800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[6] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    return (memory);
+}
+
+function getMemSegmentDefinitionIPU_1_1()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_IPU1_1",
+    {
+          name: "CODE_CORE_IPU1_1",
+          base: 0x86800000,
+          len:  0x01000000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",
+    {
+          name: "PRIVATE_DATA_CORE_IPU1_1",
+          base: 0x87800000,
+          len:  0x01800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    return (memory);
+}
+
+function getMemSegmentDefinitionDSP_1()
+{
+    var memory = new Array();
+
+    memory[0] = ["CODE_CORE_DSP1",
+    {
+          name: "CODE_CORE_DSP1",
+          base: 0x83100000,
+          len:  0x00700000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[1] = ["PRIVATE_DATA_CORE_DSP1",
+    {
+          name: "PRIVATE_DATA_CORE_DSP1",
+          base: 0x83800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[2] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[3] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[4] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[5] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    return (memory);
+}
+
+function getMemSegmentDefinitionHOST()
+{
+    var memory = new Array();
+
+    memory[8] = ["CODE_CORE_HOST",
+    {
+          name: "CODE_CORE_HOST",
+          base: 0x89000000,
+          len:  0x00800000,
+          space: "code",
+          access: "RWX"
+    }];
+
+    memory[9] = ["PRIVATE_DATA_CORE_HOST",
+    {
+          name: "PRIVATE_DATA_CORE_HOST",
+          base: 0x89800000,
+          len:  0x00800000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[10] = ["SHARED_MEM",
+    {
+          name: "SHARED_MEM",
+          base: 0xA2000000,
+          len:  0x01000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[11] = ["SHARED_FRAME_BUFFER",
+    {
+          name: "SHARED_FRAME_BUFFER",
+          base: 0x8A000000,
+          len:  0x04000000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    memory[12] = ["SHARED_CTRL",
+    {
+          name: "SHARED_CTRL",
+          base: 0xA0000000,
+          len:  0x01000000,
+          space: "code/data",
+          access: "RWX"
+    }];
+
+    memory[13] = ["SHARED_LOG_MEM",
+    {
+          name: "SHARED_LOG_MEM",
+          base: 0xA1000000,
+          len:  0x00700000,
+          space: "data",
+          access: "RWX"
+    }];
+
+    return (memory);
+}
diff --git a/examples/edma3_driver/evmDRA72x_M4/rtsc_config/platform.xs b/examples/edma3_driver/evmDRA72x_M4/rtsc_config/platform.xs
new file mode 100644 (file)
index 0000000..4f1b3df
--- /dev/null
@@ -0,0 +1,46 @@
+/*******************************************************************************
+ *                                                                             *
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *
+ *                        ALL RIGHTS RESERVED                                  *
+ *                                                                             *
+ ******************************************************************************/
+
+/*
+ *  ======== platform.xs ========
+ */
+
+var Build = xdc.useModule('xdc.bld.BuildEnvironment');
+
+var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
+
+Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_0"] =
+{
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
+       codeMemory:"CODE_CORE_IPU1_0",
+       dataMemory:"PRIVATE_DATA_CORE_IPU1_0",
+       stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
+};
+
+Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_1"] =
+{
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
+       codeMemory:"CODE_CORE_IPU1_1",
+       dataMemory:"PRIVATE_DATA_CORE_IPU1_1",
+       stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
+};
+
+Build.platformTable["ti.platforms.evmDRA7XX:DSP_1"] =
+{
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
+    codeMemory:"CODE_CORE_DSP1",
+    dataMemory:"PRIVATE_DATA_CORE_DSP1",
+    stackMemory:"PRIVATE_DATA_CORE_DSP1"
+};
+
+Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
+{
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
+    codeMemory:"CODE_CORE_HOST",
+    dataMemory:"PRIVATE_DATA_CORE_HOST",
+    stackMemory:"PRIVATE_DATA_CORE_HOST"
+};
diff --git a/examples/edma3_driver/evmDRA72x_M4/sample_app/linker.cmd b/examples/edma3_driver/evmDRA72x_M4/sample_app/linker.cmd
new file mode 100644 (file)
index 0000000..5062f6d
--- /dev/null
@@ -0,0 +1,6 @@
+SECTIONS
+{
+//    .my_sect_iram > EXT_RAM
+//    .my_sect_ddr  > EXT_RAM
+//    .resetVecs  > L2_RAM
+}
index d4e8086ce7b39572a4e197b616a8a7045745ca9b..cde47ea60d82276e369abe6ffd076a47acc34440 100755 (executable)
@@ -22,6 +22,12 @@ ifeq ($(PLATFORM),tda3xx-evm)
  PLATFORM_XDC = "ti.platforms.evmDRA7XX"
 endif
 
+#  dra72x (j6Eco)
+ifeq ($(PLATFORM),dra72x-evm)
+ SOC = dra72x
+ PLATFORM_XDC = "ti.platforms.evmDRA7XX"
+endif
+
 # ti816x (Netra) catalog EVM
 ifeq ($(PLATFORM),ti816x-evm)
  SOC = ti816x
@@ -215,6 +221,9 @@ ifeq ($(CORE),c6xdsp)
  ifeq ($(SOC),tda3xx)
   ISA = 66
  endif
+ ifeq ($(SOC),dra72x)
+  ISA = 66
+ endif
  ifeq ($(SOC),ti814x)
   ISA = 674
  endif
index 444bbe3e61a7369a6963f00a0996029a1455c903..450ca486d8d04c97766d141bddb7bbb0f14dc192 100755 (executable)
@@ -65,7 +65,7 @@ edma3_lld_EXAMPLES_LIST = edma3_drv_ti816x-evm_m3_example edma3_drv_c6472-evm_64
 
 
 ifeq ($(PLATFORM),)
-PLATFORM = tda3xx-evm tda2xx-evm ti816x-evm ti814x-evm c6a811x-evm c6472-evm c6670-evm c6678-evm c6748-evm da830-evm omapl138-evm tci6486-evm tci6608-sim tci6616-sim tci6614-evm tci6614-sim c6657-evm c66ak2e-evm c6657-sim tci6638k2k-evm tci6630k2l-evm tci6638k2k-sim tci6636k2h-evm
+PLATFORM = dra72x-evm tda3xx-evm tda2xx-evm ti816x-evm ti814x-evm c6a811x-evm c6472-evm c6670-evm c6678-evm c6748-evm da830-evm omapl138-evm tci6486-evm tci6608-sim tci6616-sim tci6614-evm tci6614-sim c6657-evm c66ak2e-evm c6657-sim tci6638k2k-evm tci6630k2l-evm tci6638k2k-sim tci6636k2h-evm
 endif
 
 ifeq ($(TARGET),)
@@ -93,6 +93,13 @@ tda3xx-evm_m4_format_support = ELF
 tda3xx-evm_66_format_support = ELF
 tda3xx-evm_eve_format_support = ELF
 
+dra72x-evm_supported_targets = a15 m4 66
+dra72x-evm_a15_cores = a15host
+dra72x-evm_m4_cores = m4
+dra72x-evm_66_cores = c6xdsp
+dra72x-evm_a15_format_support = ELF
+dra72x-evm_m4_format_support = ELF
+dra72x-evm_66_format_support = ELF
 
 #Prepare library list to build from the PLATFORM and TARGET
 ifeq ($(PLATFORM),generic)
@@ -300,4 +307,11 @@ edma3_drv_tda3xx-evm_m4_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_td
 edma3_drv_tda3xx-evm_eve_example_EXAMPLES_RELPATH = examples/edma3_driver/evmTDA3xx_EVE
 edma3_drv_tda3xx-evm_eve_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda3xx-evm_eve_example_EXAMPLES_RELPATH)
 
+edma3_drv_dra72x-evm_a15_example_EXAMPLES_RELPATH = examples/edma3_driver/evmDRA72x_a15
+edma3_drv_dra72x-evm_a15_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_dra72x-evm_a15_example_EXAMPLES_RELPATH)
+edma3_drv_dra72x-evm_66_example_EXAMPLES_RELPATH = examples/edma3_driver/evmDRA72x_DSP
+edma3_drv_dra72x-evm_66_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_dra72x-evm_66_example_EXAMPLES_RELPATH)
+edma3_drv_dra72x-evm_m4_example_EXAMPLES_RELPATH = examples/edma3_driver/evmDRA72x_M4
+edma3_drv_dra72x-evm_m4_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_dra72x-evm_m4_example_EXAMPLES_RELPATH)
+
 # Nothing beyond this point
index f491324197fddfaac15c4ec5c1f746806f981d7f..868ebaa01e6daca8bd7bd26efc89f4bb0dc6ba40 100755 (executable)
@@ -51,10 +51,13 @@ SRCS_tda2xx-evm = sample_tda2xx_cfg.c sample_tda2xx_int_reg.c
 CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_DSP
 SRCS_tda3xx-evm = sample_tda3xx_cfg.c sample_tda3xx_int_reg.c
 CFLAGS_LOCAL_tda3xx-evm = -DBUILD_TDA3XX_DSP
+SRCS_dra72x-evm = sample_dra72x_cfg.c sample_dra72x_int_reg.c
+CFLAGS_LOCAL_dra72x-evm = -DBUILD_DRA72X_DSP
 else
 SRCS_omapl138-evm = sample_omapl138_arm_cfg.c sample_omapl138_arm_int_reg.c
 SRCS_tda2xx-evm = sample_tda2xx_cfg.c sample_tda2xx_arm_int_reg.c
 SRCS_tda3xx-evm = sample_tda3xx_cfg.c sample_tda3xx_arm_int_reg.c
+SRCS_dra72x-evm = sample_dra72x_cfg.c sample_dra72x_arm_int_reg.c
 endif
 
 ifeq ($(CORE),a8host)
@@ -87,15 +90,18 @@ endif
 ifeq ($(CORE),m4)
 CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_IPU
 CFLAGS_LOCAL_tda3xx-evm = -DBUILD_TDA3XX_IPU
+CFLAGS_LOCAL_dra72x-evm = -DBUILD_DRA72X_IPU
 endif
 
 ifeq ($(CORE),a15host)
 CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_MPU
+CFLAGS_LOCAL_dra72x-evm = -DBUILD_DRA72X_MPU
 endif
 
 ifeq ($(CORE),eve)
 CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_EVE
 CFLAGS_LOCAL_tda3xx-evm = -DBUILD_TDA3XX_EVE
+CFLAGS_LOCAL_dra72x-evm = -DBUILD_DRA72X_EVE
 endif
 
 SRCS_c6748-evm = sample_c6748_cfg.c sample_c6748_int_reg.c
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_arm_int_reg.c
new file mode 100644 (file)
index 0000000..e2cdaf5
--- /dev/null
@@ -0,0 +1,339 @@
+/*
+ * sample_tda2xx_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/family/shared/vayu/IntXbar.h>
+#include <ti/sysbios/family/arm/a15/Mmu.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
+                                                {
+                                                (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
+extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorIntXbarInstNo[];
+extern unsigned int ccErrEdmaXbarIndex[];
+extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
+extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+unsigned int gpp_num = 0;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/* External Instance Specific Configuration Structure */
+extern EDMA3_DRV_GblXbarToChanConfigParams
+                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+
+typedef struct  {
+    volatile Uint32 TPCC_EVTMUX[32];
+} CSL_IntmuxRegs;
+
+typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+
+
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)
+#define EDMA3_NUM_TCC                     (64u)
+
+#define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
+/*
+ * Forward decleration
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum);
+
+void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /*
+     * Skip these interrupt xbar configuration.
+     * if it is accessing EVE internal edma instance ie edma3id = 2 and dsp_num = 1.
+     */
+    if (edma3Id != 2 && dsp_num != 1)
+    {
+        IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
+        IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
+        IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
+        IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
+    }
+
+    Hwi_Params hwiParams;
+    Error_Block      eb;
+
+    /* Initialize the Error Block                                             */
+    Error_init(&eb);
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       //hwiParams.priority = hwIntXferComp[edma3Id];
+
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
+                                       ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
+                                       (const Hwi_Params *) (&hwiParams),
+                                       &eb);
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       //hwiParams.priority = hwIntCcErr[edma3Id];
+
+       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+                ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
+                (const Hwi_Params *) (&hwiParams),
+                &eb);
+
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        /* Initialize the HWI parameters with user specified values */
+        Hwi_Params_init(&hwiParams);
+        /* argument for the ISR */
+        hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+        //hwiParams.priority = hwIntTcErr[edma3Id];
+
+        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+                    (ptrEdma3TcIsrHandler[numTc]),
+                    (const Hwi_Params *) (&hwiParams),
+                    &eb);
+        if (TRUE == Error_check(&eb))
+        {
+            System_printf("HWI Create Failed\n",Error_getCode(&eb));
+        }
+        numTc++;
+       }
+
+    Hwi_enableInterrupt(ccErrorInt[edma3Id]);
+    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
+    numTc = 0;
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    Hwi_delete(&hwiCCXferCompInt);
+    Hwi_delete(&hwiCCErrInt);
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_delete(&hwiTCErrInt[numTc]);
+        numTc++;
+       }
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**
+ * \brief   sampleMapXbarEvtToChan
+ *
+ * This function reads from the sample configuration structure which specifies
+ * cross bar events mapped to DMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+    unsigned int xbarEvtNum = 0;
+    int          edmaChanNum = 0;
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum != NULL) &&
+               (edmaGblXbarConfig != NULL))
+               {
+               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
+               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
+               if (edmaChanNum != -1)
+                       {
+                       *chanNum = edmaChanNum;
+                       edma3Result = EDMA3_DRV_SOK;
+                       }
+               }
+       return (edma3Result);
+       }
+
+
+/**
+ * \brief   sampleConfigScr
+ *
+ * This function configures control config registers for the cross bar events
+ * mapped to the EDMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
+    unsigned int scrChanOffset = 0;
+    unsigned int scrRegOffset  = 0;
+    unsigned int xBarEvtNum    = 0;
+    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
+
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum < EDMA3_NUM_TCC))
+               {
+               scrRegOffset = chanNum / 2;
+               scrChanOffset = chanNum - (scrRegOffset * 2);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+
+               switch(scrChanOffset)
+                       {
+                       case 0:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
+                               break;
+                       case 1:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
+                               break;
+                       default:
+                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+                               break;
+                       }
+               }
+       else
+               {
+               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+               }
+       return edma3Result;
+       }
+
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
+                                   unsigned int edma3Id)
+    {
+    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
+    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
+                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
+    if (hEdma != NULL)
+        {
+        retVal = EDMA3_DRV_initXbarEventMap(hEdma,
+                                                                       sampleXbarToChanConfig,
+                                                                       (EDMA3_DRV_mapXbarEvtToChan)&sampleMapXbarEvtToChan,
+                                                                       (EDMA3_DRV_xbarConfigScr)&sampleConfigScr);
+        }
+
+    return retVal;
+    }
+
+void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
+    {
+    printf("memory Protection error");
+    }
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c
new file mode 100644 (file)
index 0000000..87229c0
--- /dev/null
@@ -0,0 +1,1768 @@
+/*
+ * sample_dra72x_cfg.c
+ *
+ * SoC specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+#ifdef BUILD_DRA72X_IPU
+#include <ti/sysbios/family/arm/ducati/Core.h>
+
+#endif
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         2u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                    1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+/* Statically allocate the region numbers with cores. */
+int myCoreNum;
+#define PID0_ADDRESS 0xE00FFFE0
+#define CORE_ID_C0 0x0
+#define CORE_ID_C1 0x1
+
+unsigned short determineProcId()
+{
+    unsigned short regionNo = numEdma3Instances;
+#ifdef BUILD_DRA72X_DSP
+    extern __cregister volatile unsigned int DNUM;
+#endif
+
+    myCoreNum = numDsps;
+
+#ifdef BUILD_DRA72X_MPU
+    asm ("    push    {r0-r2} \n\t"
+            "    MRC p15, 0, r0, c0, c0, 5\n\t"
+                "    LDR      r1, =myCoreNum\n\t"
+                "    STR      r0, [r1]\n\t"
+                "    pop    {r0-r2}\n\t");
+       if((myCoreNum & 0x03) == 1)
+               regionNo = 1;
+       else
+               regionNo = 0;
+#elif defined(BUILD_DRA72X_IPU)
+    myCoreNum = (*(unsigned int *)(PID0_ADDRESS));
+    if(Core_getIpuId() == 1){
+        if(myCoreNum == CORE_ID_C0)
+            regionNo = 4;
+        else if (myCoreNum == CORE_ID_C1)
+            regionNo = 5;
+    }
+    if(Core_getIpuId() == 2){
+        if(myCoreNum == CORE_ID_C0)
+            regionNo = 6;
+        else if (myCoreNum == CORE_ID_C1)
+            regionNo = 7;
+    }
+#elif defined(BUILD_DRA72X_DSP)
+       regionNo = 2;
+#endif
+       return regionNo;
+}
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+unsigned short isGblConfigRequired(unsigned int dspNum)
+{
+    (void) dspNum;
+       return 1;
+}
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available                                            */
+#define EDMA3_NUM_PARAMSET                              (512u)
+
+/** Number of TCCS available                                                  */
+#define EDMA3_NUM_TCC                                   (64u)
+
+/** Number of DMA Channels available                                          */
+#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+
+/** Number of QDMA Channels available                                         */
+#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_NUM_EVTQUE                                (4u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_NUM_TC                                    (2u)
+
+/** Number of Regions                                                         */
+#define EDMA3_NUM_REGIONS                               (8u)
+
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38u)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34u)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33u)
+
+/** Based on the interrupt number to be mapped define the XBAR instance number */
+#define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)
+#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7u)
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12u)
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11u)
+
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT_A15                          (67u)
+#define EDMA3_CC_ERROR_INT_DSP                          (39u)
+#define EDMA3_CC_ERROR_INT_IPU                          (35u)
+
+/** Based on the interrupt number to be mapped define the XBAR instance number */
+#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)
+#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8u)
+#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13u)
+
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT_A15                         (68u)
+#define EDMA3_TC0_ERROR_INT_DSP                         (40u)
+#define EDMA3_TC0_ERROR_INT_IPU                         (36u)
+#define EDMA3_TC1_ERROR_INT_A15                         (69u)
+#define EDMA3_TC1_ERROR_INT_DSP                         (41u)
+#define EDMA3_TC1_ERROR_INT_IPU                         (37u)
+
+/** Based on the interrupt number to be mapped define the XBAR instance number */
+#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9u)
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14u)
+#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10u)
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15u)
+
+#ifdef BUILD_DRA72X_MPU
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A15
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_A15_XBAR_INST_NO
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A15
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_A15
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+
+#elif defined BUILD_DRA72X_DSP
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_DSP_XBAR_INST_NO
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_DSP
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_DSP
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_DSP_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_DSP_XBAR_INST_NO
+
+#elif defined BUILD_DRA72X_IPU
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU_C0
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU_XBAR_INST_NO
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO
+
+#else
+#define EDMA3_CC_XFER_COMPLETION_INT                    (0u)
+#define EDMA3_CC_ERROR_INT                              (0u)
+#define CC_ERROR_INT_XBAR_INST_NO                       (0u)
+#define EDMA3_TC0_ERROR_INT                             (0u)
+#define EDMA3_TC1_ERROR_INT                             (0u)
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+#endif
+
+#define EDMA3_TC2_ERROR_INT                             (0u)
+#define EDMA3_TC3_ERROR_INT                             (0u)
+#define EDMA3_TC4_ERROR_INT                             (0u)
+#define EDMA3_TC5_ERROR_INT                             (0u)
+#define EDMA3_TC6_ERROR_INT                             (0u)
+#define EDMA3_TC7_ERROR_INT                             (0u)
+
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19u)
+#define DSP1_EDMA3_CC_ERROR_INT                         (27u)
+#define DSP1_EDMA3_TC0_ERROR_INT                        (28u)
+#define DSP1_EDMA3_TC1_ERROR_INT                        (29u)
+
+/** XBAR interrupt source index numbers for EDMA interrupts */
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)
+
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)
+
+/**
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+ * ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file.
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+ * to transfer completion interrupt.
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+ * to CC error interrupts.
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+ * to TC error interrupts.
+ */
+/* EDMA 0 */
+
+#define EDMA3_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_HWI_INT_CC_ERR                              (7u)
+#define EDMA3_HWI_INT_TC0_ERR                             (10u)
+#define EDMA3_HWI_INT_TC1_ERR                             (10u)
+#define EDMA3_HWI_INT_TC2_ERR                             (10u)
+#define EDMA3_HWI_INT_TC3_ERR                             (10u)
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped (channel available)
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * For Vayu Since the xbar can be used to map event to any EDMA channel,
+ * If the application is assigning events to other channel this variable
+ * should be modified
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                      /* 31     0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA       (0x3FC0C06Eu)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFu)  /* TBD */
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped (channel available)
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA       (0xF3FFFFFCu) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000u) /* TBD */
+
+
+/* Variable which will be used internally for referring number of Event Queues*/
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+                                                        EDMA3_NUM_EVTQUE,
+                                                    };
+
+/* Variable which will be used internally for referring number of TCs.        */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+                                                    EDMA3_NUM_TC,
+                                                    EDMA3_NUM_TC
+                                                };
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        EDMA3_CC_XFER_COMPLETION_INT_A15,
+        EDMA3_CC_XFER_COMPLETION_INT_A15,
+               EDMA3_CC_XFER_COMPLETION_INT_DSP,
+        0u,
+               EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
+        EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,
+        EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
+        EDMA3_CC_XFER_COMPLETION_INT_IPU_C1
+    },
+    /* EDMA3 INSTANCE# 1 */
+    {
+        0u,
+        0u,
+        DSP1_EDMA3_CC_XFER_COMPLETION_INT,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u
+    }
+};
+/** These are the Xbar instance numbers corresponding to interrupt numbers */
+unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        COMPLETION_INT_A15_XBAR_INST_NO,
+        COMPLETION_INT_A15_XBAR_INST_NO,
+               COMPLETION_INT_DSP_XBAR_INST_NO,
+        0u,
+               COMPLETION_INT_IPU_C0_XBAR_INST_NO,
+        COMPLETION_INT_IPU_C1_XBAR_INST_NO,
+        COMPLETION_INT_IPU_C0_XBAR_INST_NO,
+        COMPLETION_INT_IPU_C1_XBAR_INST_NO,
+    },
+    /* EDMA3 INSTANCE# 1 */
+    {
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u
+    }
+};
+
+/** These are the Interrupt Crossbar Index For EDMA Completion for different regions */
+unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+       {
+               XBAR_EDMA_TPCC_IRQ_REGION0,
+        XBAR_EDMA_TPCC_IRQ_REGION1,
+        XBAR_EDMA_TPCC_IRQ_REGION2,
+        XBAR_EDMA_TPCC_IRQ_REGION3,
+               XBAR_EDMA_TPCC_IRQ_REGION4,
+        XBAR_EDMA_TPCC_IRQ_REGION5,
+        XBAR_EDMA_TPCC_IRQ_REGION6,
+        XBAR_EDMA_TPCC_IRQ_REGION7
+       },
+    /* EDMA3 INSTANCE# 1 */
+    {
+               XBAR_EDMA_TPCC_IRQ_REGION0,
+        XBAR_EDMA_TPCC_IRQ_REGION1,
+        XBAR_EDMA_TPCC_IRQ_REGION2,
+        XBAR_EDMA_TPCC_IRQ_REGION3,
+               XBAR_EDMA_TPCC_IRQ_REGION4,
+        XBAR_EDMA_TPCC_IRQ_REGION5,
+        XBAR_EDMA_TPCC_IRQ_REGION6,
+        XBAR_EDMA_TPCC_IRQ_REGION7
+       }
+};
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] =
+{
+    EDMA3_CC_ERROR_INT,
+    DSP1_EDMA3_CC_ERROR_INT
+};
+unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =
+{
+    CC_ERROR_INT_XBAR_INST_NO,
+    CC_ERROR_INT_XBAR_INST_NO
+};
+unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] =
+{
+       XBAR_EDMA_TPCC_IRQ_ERR,
+    XBAR_EDMA_TPCC_IRQ_ERR
+};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+        EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+    },
+    /* EDMA3 INSTANCE# 1 */
+    {
+        EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+        DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,
+    }
+};
+unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+       TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
+       0u, 0u,
+       0u, 0u,
+       0u, 0u,
+    },
+    /* EDMA3 INSTANCE# 1 */
+    {
+       TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,
+       0u, 0u,
+       0u, 0u,
+       0u, 0u,
+    }
+};
+
+unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+       XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
+       0u, 0u,
+       0u, 0u, 0u, 0u,
+    },
+    /* EDMA3 INSTANCE# 1 */
+    {
+       XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,
+       0u, 0u,
+       0u, 0u, 0u, 0u,
+    }
+};
+
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] =
+{
+    EDMA3_HWI_INT_XFER_COMP,
+    EDMA3_HWI_INT_XFER_COMP
+};
+
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] =
+{
+    EDMA3_HWI_INT_CC_ERR,
+    EDMA3_HWI_INT_CC_ERR
+};
+
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        EDMA3_HWI_INT_TC0_ERR,
+        EDMA3_HWI_INT_TC1_ERR,
+        EDMA3_HWI_INT_TC2_ERR,
+        EDMA3_HWI_INT_TC3_ERR
+    },
+    /* EDMA3 INSTANCE# 1 */
+    {
+        EDMA3_HWI_INT_TC0_ERR,
+        EDMA3_HWI_INT_TC1_ERR,
+        EDMA3_HWI_INT_TC2_ERR,
+        EDMA3_HWI_INT_TC3_ERR
+    }
+};
+
+/**
+ * \brief Base address as seen from the different cores may be different
+ * And is defined based on the core
+ */
+#if ((defined BUILD_DRA72X_MPU) || (defined BUILD_DRA72X_DSP))
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))
+#elif (defined BUILD_DRA72X_IPU)
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x63300000))
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x63400000))
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x63500000))
+#else
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x0))
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x0))
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x0))
+#endif
+
+#define DSP1_EDMA3_CC_BASE_ADDR                     ((void *)(0x01D10000))
+#define DSP1_EDMA3_TC0_BASE_ADDR                    ((void *)(0x01D05000))
+#define DSP1_EDMA3_TC1_BASE_ADDR                    ((void *)(0x01D06000))
+
+/* Driver Object Initialization Configuration */
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+{
+    {
+        /* EDMA3 INSTANCE# 0 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        EDMA3_NUM_DMA_CHANNELS,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        EDMA3_NUM_QDMA_CHANNELS,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        EDMA3_NUM_TCC,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        EDMA3_NUM_PARAMSET,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        EDMA3_NUM_EVTQUE,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        EDMA3_NUM_TC,
+        /** Number of Regions on this EDMA3 controller                        */
+        EDMA3_NUM_REGIONS,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        1u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        EDMA3_CC_BASE_ADDR,
+        /** Transfer Controller (TC) Registers */
+        {
+               EDMA3_TC0_BASE_ADDR,
+               EDMA3_TC1_BASE_ADDR,
+               (void *)NULL,
+               (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            EDMA3_TC0_ERROR_INT,
+            EDMA3_TC1_ERROR_INT,
+            EDMA3_TC2_ERROR_INT,
+            EDMA3_TC3_ERROR_INT,
+            EDMA3_TC4_ERROR_INT,
+            EDMA3_TC5_ERROR_INT,
+            EDMA3_TC6_ERROR_INT,
+            EDMA3_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+                       },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA,
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA
+            }
+        },
+    {
+        /* EDMA3 INSTANCE# 1 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        EDMA3_NUM_DMA_CHANNELS,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        EDMA3_NUM_QDMA_CHANNELS,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        EDMA3_NUM_TCC,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        EDMA3_NUM_PARAMSET,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        EDMA3_NUM_EVTQUE,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        EDMA3_NUM_TC,
+        /** Number of Regions on this EDMA3 controller                        */
+        EDMA3_NUM_REGIONS,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        1u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        DSP1_EDMA3_CC_BASE_ADDR,
+        /** Transfer Controller (TC) Registers */
+        {
+               DSP1_EDMA3_TC0_BASE_ADDR,
+               DSP1_EDMA3_TC1_BASE_ADDR,
+               (void *)NULL,
+               (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        DSP1_EDMA3_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        DSP1_EDMA3_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            DSP1_EDMA3_TC0_ERROR_INT,
+            DSP1_EDMA3_TC1_ERROR_INT,
+            EDMA3_TC2_ERROR_INT,
+            EDMA3_TC3_ERROR_INT,
+            EDMA3_TC4_ERROR_INT,
+            EDMA3_TC5_ERROR_INT,
+            EDMA3_TC6_ERROR_INT,
+            EDMA3_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+            },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA
+            }
+    }
+};
+
+/**
+ * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
+ * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
+ * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
+ * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
+ *
+ * Only Resources owned by a perticular core are allocated by Driver
+ * Reserved resources are not allocated if requested for any available resource
+ */
+
+/* Driver Instance Initialization Configuration */
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+    {
+               /* EDMA3 INSTANCE# 0 */
+               {
+                       /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+                       /* Resources owned/reserved by region 1 (Associated to MPU core 1) */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                 /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 2 (Associated to DSP1)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+           },
+               /* EDMA3 INSTANCE# 1 DSP1 EDMA*/
+               {
+               /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+                       /* Resources owned/reserved by region 1 (Not Associated to any core supported) */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 2 (Associated to DSP core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+           }
+};
+
+/* Driver Instance Cross bar event to channel map Initialization Configuration */
+EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Event to channel map for region 0 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 1 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 2 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 3 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 4 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 5 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 6 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 7 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+    }
+};
+
+/* End of File */
+
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_int_reg.c
new file mode 100644 (file)
index 0000000..b15f0f8
--- /dev/null
@@ -0,0 +1,301 @@
+/*
+ * sample_tda2xx_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/family/shared/vayu/IntXbar.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
+extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorIntXbarInstNo[];
+extern unsigned int ccErrEdmaXbarIndex[];
+extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
+extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+extern unsigned int dsp_num;
+
+/* External Instance Specific Configuration Structure */
+extern EDMA3_DRV_GblXbarToChanConfigParams
+                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+
+typedef struct  {
+    volatile Uint32 TPCC_EVTMUX[32];
+} CSL_IntmuxRegs;
+
+typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+
+
+#define EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X (127u)
+#define EDMA3_NUM_TCC                     (64u)
+
+#define EDMA3_EVENT_MUX_REG_BASE_ADDR               (0x4a002c78)
+
+/*
+ * Forward decleration
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum);
+
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+    /* Do the xbar configuration only for edma inst 0 */
+       /* EDMA inst 1 is for DSP1 EDMA which has direct interrupt mapping */
+       if(edma3Id == 0)
+       {
+           IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
+           IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
+           IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
+           IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
+       }
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Enable the Xfer Completion Event Interrupt */
+    EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
+                               edma3Id, 1);
+    EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Enable the CC Error Event Interrupt */
+    EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
+                                               edma3Id, 1);
+    EventCombiner_enableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
+                            (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
+                            edma3Id, 1);
+        EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+       if(edma3Id == 0)
+       {
+    Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
+    Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
+    Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Disable the Xfer Completion Event Interrupt */
+       EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Disable the CC Error Event Interrupt */
+       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+       {
+        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**
+ * \brief   sampleMapXbarEvtToChan
+ *
+ * This function reads from the sample configuration structure which specifies
+ * cross bar events mapped to DMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+    unsigned int xbarEvtNum = 0;
+    int          edmaChanNum = 0;
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
+               (chanNum != NULL) &&
+               (edmaGblXbarConfig != NULL))
+               {
+               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
+               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
+               if (edmaChanNum != -1)
+                       {
+                       *chanNum = edmaChanNum;
+                       edma3Result = EDMA3_DRV_SOK;
+                       }
+               }
+       return (edma3Result);
+       }
+
+
+/**
+ * \brief   sampleConfigScr
+ *
+ * This function configures control config registers for the cross bar events
+ * mapped to the EDMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
+    unsigned int scrChanOffset = 0;
+    unsigned int scrRegOffset  = 0;
+    unsigned int xBarEvtNum    = 0;
+    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(EDMA3_EVENT_MUX_REG_BASE_ADDR);
+
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DRA72X) &&
+               (chanNum < EDMA3_NUM_TCC))
+               {
+               scrRegOffset = chanNum / 2;
+               scrChanOffset = chanNum - (scrRegOffset * 2);
+               xBarEvtNum = (eventNum  + 1);
+
+               switch(scrChanOffset)
+                       {
+                       case 0:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
+                               break;
+                       case 1:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
+                               break;
+                       default:
+                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+                               break;
+                       }
+               }
+       else
+               {
+               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+               }
+       return edma3Result;
+       }
+
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
+                                   unsigned int edma3Id)
+    {
+    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
+    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
+                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
+    if (hEdma != NULL)
+        {
+        retVal = EDMA3_DRV_initXbarEventMap(hEdma,
+                                                                       sampleXbarToChanConfig,
+                                                                       &sampleMapXbarEvtToChan,
+                                                                       &sampleConfigScr);
+        }
+
+    return retVal;
+    }
index 3b76d8ea2d8262d51a4d8e68bd608cdd96365880..bdb9b900a31d16ae8aad5ee19645f73213e7837b 100644 (file)
@@ -39,7 +39,7 @@
  *
 */
 #ifdef GCC_BUILD
-#if defined(BUILD_TDA2XX_MPU)
+#if (defined(BUILD_TDA2XX_MPU) || defined(BUILD_DRA72X_MPU))
 #include <ti/sysbios/family/arm/a15/Cache.h>
 #elif defined (BUILD_CENTAURUS_A8)
 #include <ti/sysbios/family/arm/a8/Cache.h>
index cfa8cf8c6210eef562d83429057ac0e9f37f2df2..4998277b90d753f95d4ed22fc2279f14a998a3c0 100644 (file)
@@ -58,6 +58,7 @@ SRCS_omap4-evm = edma3_omap4_cfg.c
 SRCS_ti814x-evm = edma3_ti814x_cfg.c
 SRCS_tda2xx-evm = edma3_tda2xx_cfg.c
 SRCS_tda3xx-evm = edma3_tda3xx_cfg.c
+SRCS_dra72x-evm = edma3_dra72x_cfg.c
 SRCS_ti816x-evm = edma3_ti816x_cfg.c
 SRCS_c6a811x-evm = edma3_c6a811x_cfg.c
 SRCS_ti816x-sim = edma3_ti816x_cfg.c
index 583ce4423bba17ef51c0f74d155645fc62303bb3..58308e1fc0d676c4e73a21287038704db4662a8c 100755 (executable)
@@ -49,6 +49,7 @@ else
 SRCS_omapl138-evm = sample_omapl138_arm_cfg.c sample_omapl138_arm_int_reg.c
 SRCS_tda2xx-evm = sample_tda2xx_cfg.c sample_tda2xx_arm_int_reg.c
 SRCS_tda3xx-evm = sample_tda3xx_cfg.c sample_tda3xx_arm_int_reg.c
+SRCS_dra72x-evm = sample_dra72x_cfg.c sample_dra72x_arm_int_reg.c
 endif
 ifeq ($(CORE),a8host)
 CFLAGS_LOCAL_c6a811x-evm = -DBUILD_C6A811X_A8
@@ -72,6 +73,7 @@ SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_arm_int_reg.c
 endif
 ifeq ($(CORE),a15host)
 CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_MPU
+CFLAGS_LOCAL_dra72x-evm = -DBUILD_DRA72X_MPU
 endif
 SRCS_c6748-evm = sample_c6748_cfg.c sample_c6748_int_reg.c
 SRCS_da830-evm = sample_da830_cfg.c sample_da830_int_reg.c
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_arm_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_arm_int_reg.c
new file mode 100644 (file)
index 0000000..bd15d4d
--- /dev/null
@@ -0,0 +1,357 @@
+/*
+ * sample_ti814x_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
+                                                {
+                                                (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,
+                                                (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+unsigned int gpp_num = 0;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/* External Instance Specific Configuration Structure */
+extern EDMA3_DRV_GblXbarToChanConfigParams
+                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+
+typedef struct  {
+    volatile Uint32 DSP_INTMUX[21];
+    volatile Uint32 DUCATI_INTMUX[15];
+    volatile Uint32 TPCC_EVTMUX[16];
+    volatile Uint32 TIMER_EVTCAPT;
+    volatile Uint32 GPIO_MUX;
+} CSL_IntmuxRegs;
+
+typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+
+
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)
+#define EDMA3_NUM_TCC                     (64u)
+
+/*
+ * Forward decleration
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum);
+
+void Edma3MemProtectionHandler(unsigned int edma3InstanceId);
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+    Hwi_Params hwiParams;
+    Error_Block      eb;
+
+    /* Initialize the Error Block                                             */
+    Error_init(&eb);
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntXferComp[edma3Id];
+
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num],
+                                       ((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
+                                       (const Hwi_Params *) (&hwiParams),
+                                       &eb);
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntCcErr[edma3Id];
+
+       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+                ((Hwi_FuncPtr)&lisrEdma3CCErrHandler0),
+                (const Hwi_Params *) (&hwiParams),
+                &eb);
+
+    if (TRUE == Error_check(&eb))
+    {
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));
+    }
+
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        /* Initialize the HWI parameters with user specified values */
+        Hwi_Params_init(&hwiParams);
+        /* argument for the ISR */
+        hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+        hwiParams.priority = hwIntTcErr[edma3Id];
+
+        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+                    (ptrEdma3TcIsrHandler[numTc]),
+                    (const Hwi_Params *) (&hwiParams),
+                    &eb);
+        if (TRUE == Error_check(&eb))
+        {
+            System_printf("HWI Create Failed\n",Error_getCode(&eb));
+        }
+        numTc++;
+       }
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(ccErrorInt[edma3Id]);
+#if 0
+    Hwi_enableInterrupt(13);
+#endif
+    Hwi_enableInterrupt(ccXferCompInt[edma3Id][gpp_num]);
+    numTc = 0;
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    Hwi_delete(&hwiCCXferCompInt);
+    Hwi_delete(&hwiCCErrInt);
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_delete(&hwiTCErrInt[numTc]);
+        numTc++;
+       }
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**
+ * \brief   sampleMapXbarEvtToChan
+ *
+ * This function reads from the sample configuration structure which specifies
+ * cross bar events mapped to DMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+    unsigned int xbarEvtNum = 0;
+    int          edmaChanNum = 0;
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum != NULL) &&
+               (edmaGblXbarConfig != NULL))
+               {
+               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
+               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
+               if (edmaChanNum != -1)
+                       {
+                       *chanNum = edmaChanNum;
+                       edma3Result = EDMA3_DRV_SOK;
+                       }
+               }
+       return (edma3Result);
+       }
+
+
+/**
+ * \brief   sampleConfigScr
+ *
+ * This function configures control config registers for the cross bar events
+ * mapped to the EDMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
+    unsigned int scrChanOffset = 0;
+    unsigned int scrRegOffset  = 0;
+    unsigned int xBarEvtNum    = 0;
+    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);
+
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum < EDMA3_NUM_TCC))
+               {
+               scrRegOffset = chanNum / 4;
+               scrChanOffset = chanNum - (scrRegOffset * 4);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+
+               switch(scrChanOffset)
+                       {
+                       case 0:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
+                               break;
+                       case 1:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
+                               break;
+                       case 2:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) &
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
+                               break;
+                       case 3:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) &
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
+                               break;
+                       default:
+                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+                               break;
+                       }
+               }
+       else
+               {
+               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+               }
+       return edma3Result;
+       }
+
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
+                                   unsigned int edma3Id)
+    {
+    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
+    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
+                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
+    if (hEdma != NULL)
+        {
+        retVal = EDMA3_DRV_initXbarEventMap(hEdma,
+                                                                       sampleXbarToChanConfig,
+                                                                       (EDMA3_DRV_mapXbarEvtToChan)&sampleMapXbarEvtToChan,
+                                                                       (EDMA3_DRV_xbarConfigScr)&sampleConfigScr);
+        }
+
+    return retVal;
+    }
+
+void Edma3MemProtectionHandler(unsigned int edma3InstanceId)
+    {
+    printf("memory Protection error");
+    }
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c
new file mode 100644 (file)
index 0000000..d919b14
--- /dev/null
@@ -0,0 +1,891 @@
+/*
+ * sample_omapl138_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                    1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+/* Statically allocate the region numbers with cores. */
+int myCoreNum;
+#define PID0_ADDRESS 0xE00FFFE0
+#define CORE_ID_C0 0x0
+#define CORE_ID_C1 0x1
+unsigned short determineProcId()
+{
+unsigned short regionNo = numEdma3Instances;
+#ifdef BUILD_TDA2XX_DSP
+extern __cregister volatile unsigned int DNUM;
+#endif
+myCoreNum = numDsps;
+#ifdef BUILD_TDA2XX_MPU
+
+    asm ("    push    {r0-r2} \n\t"
+            "    MRC p15, 0, r0, c0, c0, 5\n\t"
+                "    LDR      r1, =myCoreNum\n\t"
+                "    STR      r0, [r1]\n\t"
+                "    pop    {r0-r2}\n\t");
+       if((myCoreNum & 0x03) == 1)
+               regionNo = 1;
+       else
+               regionNo = 0;
+#elif defined(BUILD_TDA2XX_IPU)
+myCoreNum = (*(unsigned int *)(PID0_ADDRESS));
+if(Core_getIpuId() == 1){
+       if(myCoreNum == CORE_ID_C0)
+               regionNo = 4;
+       else if (myCoreNum == CORE_ID_C1)
+               regionNo = 5;
+}
+if(Core_getIpuId() == 2){
+       if(myCoreNum == CORE_ID_C0)
+               regionNo = 6;
+       else if (myCoreNum == CORE_ID_C1)
+               regionNo = 7;
+}
+#elif defined BUILD_TDA2XX_DSP
+       myCoreNum = DNUM;
+       if(myCoreNum == 0)
+               regionNo = 2;
+       else
+               regionNo = 3;
+#endif
+       return regionNo;
+}
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+unsigned short isGblConfigRequired(unsigned int dspNum)
+{
+    (void) dspNum;
+
+    return 1;
+}
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available                                            */
+#define EDMA3_NUM_PARAMSET                              (512u)
+
+/** Number of TCCS available                                                  */
+#define EDMA3_NUM_TCC                                   (64u)
+
+/** Number of DMA Channels available                                          */
+#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+
+/** Number of QDMA Channels available                                         */
+#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_0_NUM_EVTQUE                              (4u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_0_NUM_TC                                  (4u)
+
+/** Number of Regions                                                         */
+#define EDMA3_0_NUM_REGIONS                             (2u)
+
+
+/** Interrupt no. for Transfer Completion                                     */
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34u)
+/** Interrupt no. for CC Error                                                */
+#define EDMA3_0_CC_ERROR_INT                            (35u)
+/** Interrupt no. for TCs Error                                               */
+#define EDMA3_0_TC0_ERROR_INT                           (36u)
+#define EDMA3_0_TC1_ERROR_INT                           (37u)
+#define EDMA3_0_TC2_ERROR_INT                           (0u)
+#define EDMA3_0_TC3_ERROR_INT                           (0u)
+#define EDMA3_0_TC4_ERROR_INT                           (0u)
+#define EDMA3_0_TC5_ERROR_INT                           (0u)
+#define EDMA3_0_TC6_ERROR_INT                           (0u)
+#define EDMA3_0_TC7_ERROR_INT                           (0u)
+
+/**
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+ * ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file.
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+ * to transfer completion interrupt.
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+ * to CC error interrupts.
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+ * to TC error interrupts.
+ */
+/* EDMA 0 */
+
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_0_HWI_INT_CC_ERR                              (7u)
+#define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC2_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC3_ERR                             (7u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                      /* 31     0 */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x3FC0C06Eu)  /* TBD */
+
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xF3FFFFFCu) /* TBD */
+
+
+/* Variable which will be used internally for referring number of Event Queues*/
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+                                                        EDMA3_0_NUM_EVTQUE,
+                                                    };
+
+/* Variable which will be used internally for referring number of TCs.        */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+                                                    EDMA3_0_NUM_TC,
+                                                };
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    {
+        0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+    },
+};
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_CC_ERROR_INT,
+                                               };
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
+{
+   {
+       EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
+       EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
+       EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
+       EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
+   }
+};
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_HWI_INT_XFER_COMP
+                                                  };
+
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+                                                   EDMA3_0_HWI_INT_CC_ERR
+                                               };
+
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+                                                     {
+                                                        EDMA3_0_HWI_INT_TC0_ERR,
+                                                        EDMA3_0_HWI_INT_TC1_ERR,
+                                                        EDMA3_0_HWI_INT_TC2_ERR,
+                                                        EDMA3_0_HWI_INT_TC3_ERR
+                                                     }
+                                               };
+
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))
+/* Driver Object Initialization Configuration                                 */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+{
+    {
+        /* EDMA3 INSTANCE# 0 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        EDMA3_NUM_DMA_CHANNELS,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        EDMA3_NUM_QDMA_CHANNELS,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        EDMA3_NUM_TCC,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        EDMA3_NUM_PARAMSET,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        EDMA3_0_NUM_EVTQUE,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        EDMA3_0_NUM_TC,
+        /** Number of Regions on this EDMA3 controller                        */
+        EDMA3_0_NUM_REGIONS,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        1u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        EDMA3_CC_BASE_ADDR,
+        /** Transfer Controller (TC) Registers */
+        {
+               EDMA3_TC0_BASE_ADDR,
+               EDMA3_TC1_BASE_ADDR,
+               (void *)NULL,
+               (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_0_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_0_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            EDMA3_0_TC0_ERROR_INT,
+            EDMA3_0_TC1_ERROR_INT,
+            EDMA3_0_TC2_ERROR_INT,
+            EDMA3_0_TC3_ERROR_INT,
+            EDMA3_0_TC4_ERROR_INT,
+            EDMA3_0_TC5_ERROR_INT,
+            EDMA3_0_TC6_ERROR_INT,
+            EDMA3_0_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            2u,
+            3u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            16u,
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u,
+            36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u,
+            44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u,
+            52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u,
+            60u, 61u, 62u, 63u
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            }
+        },
+
+};
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+               {
+                       /* Resources owned/reserved by region 0 (Associated to any MPU core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+                       /* Resources owned/reserved by region 1 (Associated to any DSP core) */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+        },
+    },
+};
+
+/* Driver Instance Cross bar event to channel map Initialization Configuration */
+EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Event to channel map for region 0 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 1 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, 26, 27, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 2 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 3 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 4 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 5 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 6 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 7 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+    }
+};
+
+/* End of File */
+
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c
new file mode 100644 (file)
index 0000000..568ce0d
--- /dev/null
@@ -0,0 +1,755 @@
+/*
+ * edma3_tda2xx_cfg.c
+ *
+ * EDMA3 Driver Adaptation Configuration File (Soc Specific) for OMAPL138.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+#define NUM_SHADOW_REGIONS                      (8u)
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         1u
+
+/** Number of PaRAM Sets available                                            */
+#define EDMA3_NUM_PARAMSET                              (512u)
+
+/** Number of TCCS available                                                  */
+#define EDMA3_NUM_TCC                                   (64u)
+
+/** Number of DMA Channels available                                          */
+#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+
+/** Number of QDMA Channels available                                         */
+#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_0_NUM_EVTQUE                              (4u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_0_NUM_TC                                  (4u)
+
+/** Number of Regions                                                         */
+#define EDMA3_0_NUM_REGIONS                             (2u)
+
+/** Interrupt no. for Transfer Completion                                     */
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34u)
+/** Interrupt no. for CC Error                                                */
+#define EDMA3_0_CC_ERROR_INT                            (35u)
+/** Interrupt no. for TCs Error                                               */
+#define EDMA3_0_TC0_ERROR_INT                           (36u)
+#define EDMA3_0_TC1_ERROR_INT                           (37u)
+#define EDMA3_0_TC2_ERROR_INT                           (0u)
+#define EDMA3_0_TC3_ERROR_INT                           (0u)
+#define EDMA3_0_TC4_ERROR_INT                           (0u)
+#define EDMA3_0_TC5_ERROR_INT                           (0u)
+#define EDMA3_0_TC6_ERROR_INT                           (0u)
+#define EDMA3_0_TC7_ERROR_INT                           (0u)
+
+/** XBAR interrupt source index numbers for EDMA interrupts */
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)
+
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                /* 31     0 */
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0        (0x00000000u)
+
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1        (0x00000000u)
+
+
+
+
+/**
+ * \brief Base address as seen from the different cores may be different
+ * And is defined based on the core
+ */
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))
+EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+    /** Total number of DMA Channels supported by the EDMA3 Controller */
+    EDMA3_NUM_DMA_CHANNELS,
+    /** Total number of QDMA Channels supported by the EDMA3 Controller */
+    EDMA3_NUM_QDMA_CHANNELS,
+    /** Total number of TCCs supported by the EDMA3 Controller */
+    EDMA3_NUM_TCC,
+    /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+    EDMA3_NUM_PARAMSET,
+    /** Total number of Event Queues in the EDMA3 Controller */
+    EDMA3_0_NUM_EVTQUE,
+    /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+    EDMA3_0_NUM_TC,
+    /** Number of Regions on this EDMA3 controller */
+    EDMA3_0_NUM_REGIONS,
+
+    /**
+     * \brief Channel mapping existence
+     * A value of 0 (No channel mapping) implies that there is fixed association
+     * for a channel number to a parameter entry number or, in other words,
+     * PaRAM entry n corresponds to channel n.
+     */
+    0u,
+
+    /** Existence of memory protection feature */
+    0u,
+
+        /** Global Register Region of CC Registers */
+        EDMA3_CC_BASE_ADDR,
+        /** Transfer Controller (TC) Registers */
+        {
+               EDMA3_TC0_BASE_ADDR,
+               EDMA3_TC1_BASE_ADDR,
+               (void *)NULL,
+               (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+    /** Interrupt no. for Transfer Completion */
+    EDMA3_0_CC_XFER_COMPLETION_INT,
+    /** Interrupt no. for CC Error */
+    EDMA3_0_CC_ERROR_INT,
+    /** Interrupt no. for TCs Error */
+        {
+        EDMA3_0_TC0_ERROR_INT,
+        EDMA3_0_TC1_ERROR_INT,
+        EDMA3_0_TC2_ERROR_INT,
+        EDMA3_0_TC3_ERROR_INT,
+        EDMA3_0_TC4_ERROR_INT,
+        EDMA3_0_TC5_ERROR_INT,
+        EDMA3_0_TC6_ERROR_INT,
+        EDMA3_0_TC7_ERROR_INT
+        },
+
+   /**
+     * \brief EDMA3 TC priority setting
+     *
+     * User can program the priority of the Event Queues
+     * at a system-wide level.  This means that the user can set the
+     * priority of an IO initiated by either of the TCs (Transfer Controllers)
+     * relative to IO initiated by the other bus masters on the
+     * device (ARM, DSP, USB, etc)
+     */
+        {
+        0u,
+        1u,
+        2u,
+        3u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+    /**
+     * \brief To Configure the Threshold level of number of events
+     * that can be queued up in the Event queues. EDMA3CC error register
+     * (CCERR) will indicate whether or not at any instant of time the
+     * number of events queued up in any of the event queues exceeds
+     * or equals the threshold/watermark value that is set
+     * in the queue watermark threshold register (QWMTHRA).
+     */
+        {
+        16u,
+        16u,
+        16u,
+        16u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+
+    /**
+     * \brief To Configure the Default Burst Size (DBS) of TCs.
+     * An optimally-sized command is defined by the transfer controller
+     * default burst size (DBS). Different TCs can have different
+     * DBS values. It is defined in Bytes.
+     */
+        {
+        16u,
+        16u,
+        16u,
+        16u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+
+    /**
+     * \brief Mapping from each DMA channel to a Parameter RAM set,
+     * if it exists, otherwise of no use.
+     */
+        {
+        0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+        16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+        },
+
+     /**
+      * \brief Mapping from each DMA channel to a TCC. This specific
+      * TCC code will be returned when the transfer is completed
+      * on the mapped channel.
+      */
+        {
+        0u, 1u, 2u, 3u,
+        4u, 5u, 6u, 7u,
+        8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        12u, 13u, 14u, 15u,
+        16u, 17u, 18u, 19u,
+        20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        24u, 25u, 26u, 27u,
+        28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u,
+            36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u,
+            44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u,
+            52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u,
+            60u, 61u, 62u, 63u
+        },
+
+    /**
+     * \brief Mapping of DMA channels to Hardware Events from
+     * various peripherals, which use EDMA for data transfer.
+     * All channels need not be mapped, some can be free also.
+     */
+        {
+        DMA_CHANNEL_TO_EVENT_MAPPING_0_0,
+        DMA_CHANNEL_TO_EVENT_MAPPING_0_1
+        }
+    },
+};
+
+
+/* Default RM Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SHADOW_REGIONS] =
+{
+        /* EDMA3 INSTANCE# 0 */
+        {
+                       /* Resources owned/reserved by region 0 (Associated to any MPU core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+                       /* Resources owned/reserved by region 1 (Associated to any DSP core) */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+        },
+};
+
+/* Driver Instance Cross bar event to channel map Initialization Configuration */
+EDMA3_RM_GblXbarToChanConfigParams defXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Event to channel map for region 0 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 1 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 2 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 3 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 4 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 5 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 6 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 7 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+    }
+};
+
+/* End of File */
+
+
+