review comments fixed and test suite run on the code.
authorImtiaz SMA <imtiaz.syed@ti.com>
Mon, 12 Apr 2010 03:18:00 +0000 (08:48 +0530)
committerImtiaz SMA <imtiaz.syed@ti.com>
Mon, 12 Apr 2010 03:18:00 +0000 (08:48 +0530)
Signed-off-by: Imtiaz SMA <imtiaz.syed@ti.com>
package.xdc
packages/ti/sdo/edma3/drv/package.xdc
packages/ti/sdo/edma3/drv/sample/package.xdc
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c6748_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl138_cfg.c
packages/ti/sdo/edma3/rm/package.xdc
packages/ti/sdo/edma3/rm/sample/package.xdc
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c6748_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl138_cfg.c

index e2a3db21a512f59948872c23981e2d1c0495770b..14a76306dede715da847f93a207a2647ee17d943 100755 (executable)
@@ -9,7 +9,7 @@ requires ti.sdo.edma3.drv;
 requires ti.sdo.edma3.drv.sample;
 
 /*!
- *  ======== edma3_lld_02_01_00_06 ========
+ *  ======== edma3_lld_02_01_01_06 ========
  */
-package edma3_lld_02_01_00_06 [02, 01, 00] {
+package edma3_lld_02_01_01_06 [02, 01, 01] {
 }
index 5299344c422711fc7f7adda2bf6f3e8e00f09ce3..9f99c6300ee2232c951a1f8ffabfa130f06d371c 100755 (executable)
@@ -46,6 +46,6 @@ requires ti.sdo.edma3.rm;
 /*!
  *  ======== ti.sdo.edma3.drv ========
  */
-package ti.sdo.edma3.drv [02, 01, 00] {
+package ti.sdo.edma3.drv [02, 01, 01] {
     module DRV;
 }
index 8b2da090e47d97a3aeb1c90d311ce9d76d475d08..f8b47a2157802ff75b18f3e0509b9813fd65d4c8 100755 (executable)
@@ -55,6 +55,6 @@ requires ti.sdo.edma3.drv;
 /*!
  *  ======== ti.sdo.edma3.drv.sample ========
  */
-package ti.sdo.edma3.drv.sample [02, 01, 00] {
+package ti.sdo.edma3.drv.sample [02, 01, 01] {
     module DrvSample;
 }
index 56238d077130719be2a4f3e4b08b4e251c9a2862..1f21dd6c3f79836559b6de8d6a06f26fb7b2a5de 100755 (executable)
@@ -699,9 +699,9 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
             /* resvdTccs */
             /* 31       0 */
-            {0xFF3FF3FFu,
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
             /* 63..32 */
-            0x00000000u},
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
         },
         /* Resources owned/reserved by region 2 */
         {
@@ -1076,9 +1076,9 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
             /* resvdDmaChannels */
                 /* 31      0  */
             {
-                0x3F07FFFFu,
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0,
                 /* 63..32   */
-                0x00000000u
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1
             },
 
             /* resvdQdmaChannels */
index becc675ffe628cc6fabdede6f0753306ccadfe7e..fbda7ccfb7d77c723683195b6b17bb67b8a2a234 100755 (executable)
@@ -703,9 +703,9 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
             /* resvdTccs */
             /* 31       0 */
-            {0xFF3FF3FFu,
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
             /* 63..32 */
-            0x00000000u},
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
         },
         /* Resources owned/reserved by region 2 */
         {
@@ -1080,9 +1080,9 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
             /* resvdDmaChannels */
                 /* 31      0  */
             {
-                0x3F07FFFFu,
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0,
                 /* 63..32   */
-                0x00000000u
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1
             },
 
             /* resvdQdmaChannels */
index e82a419b9480591967de0bbdd42b57ad09aa7598..53047933c0aa3bb6fd1dd1fe255b820dd6f77a25 100755 (executable)
@@ -51,6 +51,6 @@
 /*!
  *  ======== ti.sdo.edma3.rm ========
  */
-package ti.sdo.edma3.rm [02, 01, 00] {
+package ti.sdo.edma3.rm [02, 01, 01] {
     module RM;
 }
index 3e83b366d5d60c62360f8abd1d66c88efd0c63ac..c7bb634147f3ac35f54486632558958c9f51c915 100755 (executable)
@@ -58,6 +58,6 @@ requires ti.sdo.edma3.rm;
 /*!
  *  ======== ti.sdo.edma3.rm.sample ========
  */
-package ti.sdo.edma3.rm.sample [02, 01, 00] {
+package ti.sdo.edma3.rm.sample [02, 01, 01] {
     module RmSample;
 }
index f5dfac14c420ea462e1323ee99baa8091ab2079f..db23c1127740e5194364681d6dce6b28e105dff8 100755 (executable)
@@ -689,9 +689,9 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
             /* resvdDmaChannels */
             /* 31       0 */
-            {0xFF3FF3FFu,
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
             /* 63..32 */
-            0x00000000u},
+             EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
 
             /* resvdQdmaChannels */
             /* 31     0 */
@@ -699,9 +699,9 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
             /* resvdTccs */
             /* 31       0 */
-            {0xFF3FF3FFu,
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
             /* 63..32 */
-            0x00000000u},
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
         },
         /* Resources owned/reserved by region 2 */
         {
@@ -1076,9 +1076,9 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
             /* resvdDmaChannels */
                 /* 31      0  */
             {
-                0x3F07FFFFu,
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0,
                 /* 63..32   */
-                0x00000000u
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1
             },
 
             /* resvdQdmaChannels */
@@ -1090,9 +1090,9 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
             /* resvdTccs */
             /* 31      0 */
             {
-                0x3F07FFFFu,
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0,
                 /* 63..32 */
-                0x00000000u
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1
             },
         },
         /* Resources owned/reserved by region 2 */
index 33df24990da0c9537f657d94bd9b71cc58c93d63..96f553be96707e42aadc5f4cea62ff4909507f07 100755 (executable)
@@ -51,16 +51,6 @@ const unsigned int numDsps = NUM_DSPS;
 /* Determine the processor id by reading DNUM register. */
 unsigned short determineProcId()
 {
-#if 0
-    volatile unsigned int *addr;
-    unsigned int core_no;
-
-    /* Identify the core number */
-    addr = (unsigned int *)(CGEM_REG_START+0x40000);
-    core_no = ((*addr) & 0x000F0000)>>16;
-
-    return core_no;
-#endif
     return 1;
 }
 
@@ -703,9 +693,9 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
             /* resvdDmaChannels */
             /* 31       0 */
-            {0xFF3FF3FFu,
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
             /* 63..32 */
-            0x00000000u},
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
 
             /* resvdQdmaChannels */
             /* 31     0 */
@@ -713,9 +703,9 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
             /* resvdTccs */
             /* 31       0 */
-            {0xFF3FF3FFu,
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
             /* 63..32 */
-            0x00000000u},
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
         },
         /* Resources owned/reserved by region 2 */
         {
@@ -1090,9 +1080,9 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
             /* resvdDmaChannels */
                 /* 31      0  */
             {
-                0x3F07FFFFu,
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0,
                 /* 63..32   */
-                0x00000000u
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1
             },
 
             /* resvdQdmaChannels */
@@ -1104,9 +1094,9 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
             /* resvdTccs */
             /* 31      0 */
             {
-                0x3F07FFFFu,
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0,
                 /* 63..32 */
-                0x00000000u
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1
             },
         },
         /* Resources owned/reserved by region 2 */