Misra C fixes:
authorSunil MS <x0190988@ti.com>
Wed, 13 Aug 2014 14:06:30 +0000 (19:36 +0530)
committerSunil MS <x0190988@ti.com>
Thu, 9 Oct 2014 14:09:21 +0000 (19:39 +0530)
Unsigned Suffix
Built in numeric
Usage of Reserved Keyword

Change-Id: I76ddbb4a3e1770671c80c45beb491ca88d1dad72
Signed-off-by: Sunil MS <x0190988@ti.com>
packages/ti/sdo/edma3/drv/edma3_drv.h
packages/ti/sdo/edma3/drv/src/edma3.h
packages/ti/sdo/edma3/drv/src/edma3_drv_adv.c
packages/ti/sdo/edma3/rm/edma3_common.h
packages/ti/sdo/edma3/rm/edma3_rm.h
packages/ti/sdo/edma3/rm/src/edma3_rl_cc.h
packages/ti/sdo/edma3/rm/src/edma3_rl_tc.h
packages/ti/sdo/edma3/rm/src/edma3resmgr.h

index 3d322e6940a54b8ee6611dd9a521f71068998176..9b58113c0403857ff3708d980326a40b7a147b68 100755 (executable)
@@ -47,8 +47,8 @@
  *  scheduling and synchronizing with EDMA transfers and many more.
  */
 
-#ifndef _EDMA3_DRV_H_
-#define _EDMA3_DRV_H_
+#ifndef EDMA3_DRV_H_
+#define EDMA3_DRV_H_
 
 #include <stdint.h>
 
@@ -189,7 +189,7 @@ extern "C" {
  * This value should mandatorily be used to mark DMA channels with no initial
  * mapping to specific PaRAM Sets.
  */
-#define EDMA3_DRV_CH_NO_PARAM_MAP           EDMA3_RM_CH_NO_PARAM_MAP
+#define EDMA3_DRV_CH_NO_PARAM_MAP           (EDMA3_RM_CH_NO_PARAM_MAP)
 
 /**
  * This define is used to specify that the DMA/QDMA channel is not tied to any
@@ -200,7 +200,7 @@ extern "C" {
  * This value should mandatorily be used to mark DMA channels with no initial
  * mapping to specific TCCs.
  */
-#define EDMA3_DRV_CH_NO_TCC_MAP             EDMA3_RM_CH_NO_TCC_MAP
+#define EDMA3_DRV_CH_NO_TCC_MAP             (EDMA3_RM_CH_NO_TCC_MAP)
 
 /**
 @}
index 6c7ff02ddad3d83b97c23a2aec7c85dd64479f2c..4bcf4c0db0f8536d2e1b67b03dc2f9872de9503c 100755 (executable)
@@ -36,8 +36,8 @@
  *
 */
 
-#ifndef _EDMA3_H_
-#define _EDMA3_H_
+#ifndef EDMA3_H_
+#define EDMA3_H_
 
 /** Include EDMA3 Driver header file */
 #include <ti/sdo/edma3/drv/edma3_drv.h>
@@ -107,36 +107,36 @@ extern "C" {
 #define EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen)     (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)
 
 /** OPT-SAM bit Get */
-#define EDMA3_DRV_OPT_SAM_GET_MASK(mode)            ((mode)&1u)
+#define EDMA3_DRV_OPT_SAM_GET_MASK(mode)            ((mode)&1U)
 /** OPT-DAM bit Get */
-#define EDMA3_DRV_OPT_DAM_GET_MASK(mode)            (((mode)&(1u<<1u))>>1u)
+#define EDMA3_DRV_OPT_DAM_GET_MASK(mode)            (((mode)&(1U<<1U))>>1U)
 /** OPT-SYNCDIM bit Get */
-#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)    (((synctype)&(1u<<2u))>>2u)
+#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)    (((synctype)&(1U<<2U))>>2U)
 /** OPT-STATIC bit Get */
-#define EDMA3_DRV_OPT_STATIC_GET_MASK(en)           (((en)&(1u<<3u))>>3u)
+#define EDMA3_DRV_OPT_STATIC_GET_MASK(en)           (((en)&(1U<<3U))>>3U)
 /** OPT-FWID bitfield Get */
-#define EDMA3_DRV_OPT_FWID_GET_MASK(width)          (((width)&(0x7u<<8u))>>8u)
+#define EDMA3_DRV_OPT_FWID_GET_MASK(width)          (((width)&(0x7U<<8U))>>8U)
 /** OPT-TCCMODE bit Get */
-#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)       (((early)&(1u<<11u))>>11u)
+#define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)       (((early)&(1U<<11U))>>11U)
 /** OPT-TCC bitfield Get */
-#define EDMA3_DRV_OPT_TCC_GET_MASK(tcc)             (((tcc)&(0x3fu<<12u))>>12u)
+#define EDMA3_DRV_OPT_TCC_GET_MASK(tcc)             (((tcc)&((uint32_t)0x3fU<<12U))>>12U)
 /** OPT-TCINTEN bit Get */
-#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)     (((tcinten)&(1u<<20u))>>20u)
+#define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)     (((tcinten)&(1U<<20U))>>20U)
 /** OPT-ITCINTEN bit Get */
-#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)   (((itcinten)&(1u<<21u))>>21u)
+#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)   (((itcinten)&(1U<<21U))>>21U)
 /** OPT-TCCHEN bit Get */
-#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)       (((tcchen)&(1u<<22u))>>22u)
+#define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)       (((tcchen)&(1U<<22U))>>22U)
 /** OPT-ITCCHEN bit Get */
-#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)     (((itcchen)&(1u<<23u))>>23u)
+#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)     (((itcchen)&(1U<<23U))>>23U)
 
 /** DMAQNUM bits Clear */
-#define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum)           (~(0x7u<<(((chNum)%8u)*4u)))
+#define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum)           (~((uint32_t)0x7U<<(((chNum)%8U)*4U)))
 /** DMAQNUM bits Set */
-#define EDMA3_DRV_DMAQNUM_SET_MASK(chNum,queNum)    ((0x7u & (queNum)) << (((chNum)%8u)*4u))
+#define EDMA3_DRV_DMAQNUM_SET_MASK(chNum,queNum)    ((0x7U & (queNum)) << (((chNum)%8U)*4U))
 /** QDMAQNUM bits Clear */
-#define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum)          (~(0x7u<<((chNum)*4u)))
+#define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum)          (~((uint32_t)0x7U<<((chNum)*4U)))
 /** QDMAQNUM bits Set */
-#define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum,queNum)   ((0x7u & (queNum)) << ((chNum)*4u))
+#define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum,queNum)   ((0x7U & (queNum)) << ((chNum)*4U))
 
 
 /* Other Mask defines */
@@ -157,13 +157,13 @@ extern "C" {
 #define EDMA3_DRV_QCH_PARAM_TRWORD_CLR_MASK         (EDMA3_DRV_QCH_PARAM_CLR_MASK | EDMA3_DRV_QCH_TRWORD_CLR_MASK)
 
 /** Max value of ACnt */
-#define EDMA3_DRV_ACNT_MAX_VAL              (0xFFFFu)
+#define EDMA3_DRV_ACNT_MAX_VAL              (0xFFFFU)
 /** Max value of BCnt */
-#define EDMA3_DRV_BCNT_MAX_VAL              (0xFFFFu)
+#define EDMA3_DRV_BCNT_MAX_VAL              (0xFFFFU)
 /** Max value of CCnt */
-#define EDMA3_DRV_CCNT_MAX_VAL              (0xFFFFu)
+#define EDMA3_DRV_CCNT_MAX_VAL              (0xFFFFU)
 /** Max value of BCntReld */
-#define EDMA3_DRV_BCNTRELD_MAX_VAL          (0xFFFFu)
+#define EDMA3_DRV_BCNTRELD_MAX_VAL          (0xFFFFU)
 /** Max value of SrcBIdx */
 #define EDMA3_DRV_SRCBIDX_MAX_VAL           (0x7FFF)
 /** Min value of SrcBIdx */
@@ -181,9 +181,9 @@ extern "C" {
 /** Min value of DestCIdx */
 #define EDMA3_DRV_DSTCIDX_MIN_VAL           (-32768)
 /** Max value of Queue Priority */
-#define EDMA3_DRV_QPRIORITY_MAX_VAL         (7u)
+#define EDMA3_DRV_QPRIORITY_MAX_VAL         (7U)
 /** Min value of Queue Priority */
-#define EDMA3_DRV_QPRIORITY_MIN_VAL         (0u)
+#define EDMA3_DRV_QPRIORITY_MIN_VAL         (0U)
 
 
 /** To maintain the state of the EDMA3 Driver object */
index b4b593249f46de827670beebceaaff73ef6c6971..aa770d2e3ca5208c21dfb9720d8592a1d850dd93 100755 (executable)
@@ -233,7 +233,7 @@ EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma,
                             EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
         linkBcntReld &= 0xFFFF0000U;
         /* Update the Link field with lch2 PaRAM set */
-        linkBcntReld |= (0xFFFFu & (uint32_t)(&(globalRegs->PARAMENTRY [paRAM2Id].OPT)));
+        linkBcntReld |= (0xFFFFU & (uint32_t)(&(globalRegs->PARAMENTRY [paRAM2Id].OPT)));
 
         /* Store it back */
         *((&globalRegs->PARAMENTRY[paRAM1Id].OPT)
@@ -335,7 +335,7 @@ EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, uint32_t lCh)
                                                        + EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
 
                /* Remove any linking */
-               linkBcntReld |= 0xFFFFu;
+               linkBcntReld |= 0xFFFFU;
 
                /* Store it back */
                *((&globalRegs->PARAMENTRY[paRAMId].OPT)
@@ -429,7 +429,7 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
         /* set Transfer complete chaining */
         if (chainOptions->tcchEn == EDMA3_DRV_TCCHEN_EN)
             {
-            opt |= EDMA3_DRV_OPT_TCCHEN_SET_MASK(1u);
+            opt |= EDMA3_DRV_OPT_TCCHEN_SET_MASK(1U);
             }
         else
             {
@@ -439,7 +439,7 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
         /*set Intermediate transfer completion chaining */
         if (chainOptions->itcchEn == EDMA3_DRV_ITCCHEN_EN)
             {
-            opt |= EDMA3_DRV_OPT_ITCCHEN_SET_MASK(1u);
+            opt |= EDMA3_DRV_OPT_ITCCHEN_SET_MASK(1U);
             }
         else
             {
@@ -449,7 +449,7 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
         /*set Transfer complete interrupt */
         if (chainOptions->tcintEn == EDMA3_DRV_TCINTEN_EN)
             {
-            opt |= EDMA3_DRV_OPT_TCINTEN_SET_MASK(1u);
+            opt |= EDMA3_DRV_OPT_TCINTEN_SET_MASK(1U);
             }
         else
             {
@@ -459,7 +459,7 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
         /*set Intermediate transfer completion interrupt */
         if (chainOptions->itcintEn == EDMA3_DRV_ITCINTEN_EN)
             {
-            opt |= EDMA3_DRV_OPT_ITCINTEN_SET_MASK(1u);
+            opt |= EDMA3_DRV_OPT_ITCINTEN_SET_MASK(1U);
             }
         else
             {
@@ -1445,9 +1445,9 @@ EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ(EDMA3_DRV_Handle hEdma,
                                                EDMA3_OS_PROTECT_INTERRUPT,
                                                &intState);
 
-            globalRegs->DMAQNUM[channelId >> 3u] &=
+            globalRegs->DMAQNUM[channelId >> 3U] &=
                                         EDMA3_DRV_DMAQNUM_CLR_MASK(channelId);
-            globalRegs->DMAQNUM[channelId >> 3u] |=
+            globalRegs->DMAQNUM[channelId >> 3U] |=
                                 EDMA3_DRV_DMAQNUM_SET_MASK(channelId, eventQ);
 
             edma3OsProtectExit(edma3Id,
@@ -1537,9 +1537,9 @@ EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
 
         if (channelId <= edma3_dma_ch_max_val [edma3Id])
             {
-            *mappedEvtQ = ((globalRegs->DMAQNUM[channelId >> 3u])
+            *mappedEvtQ = ((globalRegs->DMAQNUM[channelId >> 3U])
                             & (~(EDMA3_DRV_DMAQNUM_CLR_MASK(channelId))))
-                              >> ((channelId%8u)*4u);
+                              >> ((channelId%8U)*4U);
             }
         else
             {
@@ -1548,7 +1548,7 @@ EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
                 {
                 *mappedEvtQ = ((globalRegs->QDMAQNUM)
                                 & (~(EDMA3_DRV_QDMAQNUM_CLR_MASK(channelId - edma3_qdma_ch_min_val[edma3Id]))))
-                               >> (channelId*4u);
+                               >> (channelId*4U);
                 }
             else
                 {
@@ -1577,7 +1577,7 @@ EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
     EDMA3_DRV_Instance *drvInst = NULL;
     EDMA3_DRV_Object *drvObject = NULL;
-    volatile uint32_t regPhyAddr = 0x0u;
+    volatile uint32_t regPhyAddr = 0x0U;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1590,7 +1590,7 @@ EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
 
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
-    if ((hEdma == NULL) || ((regOffset % 4u) != 0))
+    if ((hEdma == NULL) || ((regOffset % 4U) != 0))
         {
         result = EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -1656,7 +1656,7 @@ EDMA3_DRV_Result EDMA3_DRV_getCCRegister ( EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Result result = EDMA3_DRV_SOK;
     EDMA3_DRV_Instance *drvInst = NULL;
     EDMA3_DRV_Object *drvObject = NULL;
-    volatile uint32_t regPhyAddr = 0x0u;
+    volatile uint32_t regPhyAddr = 0x0U;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1669,7 +1669,7 @@ EDMA3_DRV_Result EDMA3_DRV_getCCRegister ( EDMA3_DRV_Handle hEdma,
        /* If parameter checking is enabled... */
 #ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
     if (((hEdma == NULL) || (regValue == NULL))
-        || ((regOffset % 4u) != 0))
+        || ((regOffset % 4U) != 0))
         {
         result =  EDMA3_DRV_E_INVALID_PARAM;
         }
@@ -1715,7 +1715,7 @@ EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
     volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
-    uint32_t tccBitMask = 0x0u;
+    uint32_t tccBitMask = 0x0U;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1762,9 +1762,9 @@ EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
 
                 if (shadowRegs != NULL)
                     {
-                    if(tccNo < 32u)
+                    if(tccNo < 32U)
                         {
-                        tccBitMask = 1u << tccNo;
+                        tccBitMask = 1U << tccNo;
 
                         /* Check the status of the IPR[tccNo] bit. */
                         while (FALSE == (shadowRegs->IPR & tccBitMask))
@@ -1780,7 +1780,7 @@ EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
                         }
                     else
                         {
-                        tccBitMask = 1u << (tccNo - 32u);
+                        tccBitMask = 1U << (tccNo - 32U);
 
                         /* Check the status of the IPRH[tccNo-32] bit. */
                         while (FALSE == (shadowRegs->IPRH & tccBitMask))
@@ -1819,7 +1819,7 @@ EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
     EDMA3_DRV_Object *drvObject = NULL;
     volatile EDMA3_CCRL_Regs *globalRegs = NULL;
     volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
-    uint32_t tccBitMask = 0x0u;
+    uint32_t tccBitMask = 0x0U;
 
 #ifdef EDMA3_INSTRUMENTATION_ENABLED
     EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1870,9 +1870,9 @@ EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
 
                 if (shadowRegs != NULL)
                     {
-                    if(tccNo < 32u)
+                    if(tccNo < 32U)
                         {
-                        tccBitMask = 1u << tccNo;
+                        tccBitMask = 1U << tccNo;
 
                         /* Check the status of the IPR[tccNo] bit. */
                         if ((shadowRegs->IPR & tccBitMask) != FALSE)
@@ -1886,7 +1886,7 @@ EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
                         }
                     else
                         {
-                        tccBitMask = 1u << (tccNo - 32u);
+                        tccBitMask = 1U << (tccNo - 32U);
 
                         /* Check the status of the IPRH[tccNo-32] bit. */
                         if ((shadowRegs->IPRH & tccBitMask) != FALSE)
@@ -2369,27 +2369,27 @@ EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(uint32_t phyCtrllerInstId,
         switch (tcErr)
                {
                case EDMA3_DRV_TC_ERR_BUSERR_DIS:
-                               tcRegs->ERREN &= ~(1 << EDMA3_TCRL_ERREN_BUSERR_SHIFT);
+                               tcRegs->ERREN &= ~((uint32_t)1 << EDMA3_TCRL_ERREN_BUSERR_SHIFT);
                                break;
 
                case EDMA3_DRV_TC_ERR_BUSERR_EN:
-                               tcRegs->ERREN = tcRegs->ERREN | (1 << EDMA3_TCRL_ERREN_BUSERR_SHIFT);
+                               tcRegs->ERREN |= ((uint32_t)1 << EDMA3_TCRL_ERREN_BUSERR_SHIFT);
                                break;
 
                case EDMA3_DRV_TC_ERR_TRERR_DIS:
-                               tcRegs->ERREN &= ~(1 << EDMA3_TCRL_ERREN_TRERR_SHIFT);
+                               tcRegs->ERREN &= ~((uint32_t)1 << EDMA3_TCRL_ERREN_TRERR_SHIFT);
                                break;
 
                case EDMA3_DRV_TC_ERR_TRERR_EN:
-                               tcRegs->ERREN = tcRegs->ERREN | (1 << EDMA3_TCRL_ERREN_TRERR_SHIFT);
+                               tcRegs->ERREN |= ((uint32_t)1 << EDMA3_TCRL_ERREN_TRERR_SHIFT);
                                break;
 
                case EDMA3_DRV_TC_ERR_MMRAERR_DIS:
-                               tcRegs->ERREN &= ~(1 << EDMA3_TCRL_ERREN_MMRAERR_SHIFT);
+                               tcRegs->ERREN &= ~((uint32_t)1 << EDMA3_TCRL_ERREN_MMRAERR_SHIFT);
                                break;
 
                case EDMA3_DRV_TC_ERR_MMRAERR_EN:
-                               tcRegs->ERREN = tcRegs->ERREN | (1 << EDMA3_TCRL_ERREN_MMRAERR_SHIFT);
+                               tcRegs->ERREN |= ((uint32_t)1 << EDMA3_TCRL_ERREN_MMRAERR_SHIFT);
                                break;
 
                case EDMA3_DRV_TC_ERR_DIS:
@@ -2498,26 +2498,25 @@ EDMA3_DRV_Result EDMA3_DRV_getChannelStatus(EDMA3_DRV_Handle hEdma,
        /* DMA Channel, check for event pending and event miss */
                if (lCh <= edma3_dma_ch_max_val[edma3Id])
                        {
-                       if (lCh < 32u)
+                       if (lCh < 32U)
                                {
-                       if((globalRegs->EMR & (1u << lCh)) != FALSE)
+                       if((globalRegs->EMR & ((uint32_t)1U << lCh)) != FALSE)
                            {
                            status |= EDMA3_DRV_CHANNEL_ERR;
                            }
 
-                       if((shadowRegs->ER & (1u << lCh)) != FALSE)
+                       if((shadowRegs->ER & ((uint32_t)1U << lCh)) != FALSE)
                            {
                            status |= EDMA3_DRV_CHANNEL_EVENT_PENDING;
                            }
                                }
                        else
                                {
-                if((globalRegs->EMRH & (1u << (lCh-32u))) != FALSE)
+                if((globalRegs->EMRH & ((uint32_t)1U << (lCh-32U))) != FALSE)
                     {
                     status |= EDMA3_DRV_CHANNEL_ERR;
                     }
-
-                       if((shadowRegs->ERH & (1u << (lCh-32u))) != FALSE)
+                       if((shadowRegs->ERH & ((uint32_t)1U << (lCh-32U))) != FALSE)
                            {
                            status |= EDMA3_DRV_CHANNEL_EVENT_PENDING;
                            }
@@ -2530,23 +2529,23 @@ EDMA3_DRV_Result EDMA3_DRV_getChannelStatus(EDMA3_DRV_Handle hEdma,
                        {
                        uint32_t qdma_ch = lCh - edma3_qdma_ch_min_val[edma3Id];
 
-               if((globalRegs->QEMR & (1u << qdma_ch)) != FALSE)
+               if((globalRegs->QEMR & ((uint32_t)1U << qdma_ch)) != FALSE)
                    {
                    status |= EDMA3_DRV_CHANNEL_ERR;
                    }
                        }
 
                /* Check for xfer completion interrupt */
-               if (tcc < 32u)
+               if (tcc < 32U)
                        {
-               if((shadowRegs->IPR & (1u << tcc)) != FALSE)
+               if((shadowRegs->IPR & ((uint32_t)1U << tcc)) != FALSE)
                    {
                    status |= EDMA3_DRV_CHANNEL_XFER_COMPLETE;
                    }
                        }
                else
                        {
-               if((shadowRegs->IPRH & (1u << (tcc-32u))) != FALSE)
+               if((shadowRegs->IPRH & ((uint32_t)1U << (tcc-32U))) != FALSE)
                    {
                    status |= EDMA3_DRV_CHANNEL_XFER_COMPLETE;
                    }
index 48badc1363be02868a929be3dea11a4e8543e688..e7087060deb38c71ed12dcb1e0427eda4e6be0a2 100755 (executable)
@@ -36,8 +36,8 @@
  *
 */
 
-#ifndef _EDMA3_COMMON_H_
-#define _EDMA3_COMMON_H_
+#ifndef EDMA3_COMMON_H_
+#define EDMA3_COMMON_H_
 
 /***************************************************************\
 * Standard Definition Header File For Null Definition *
@@ -49,12 +49,10 @@ extern "C" {
 #endif
 
 /** define to enable/disable Resource Manager debug messages*/
-#define EDMA3_RM_DEBUG
-#undef EDMA3_RM_DEBUG
+/* #define EDMA3_RM_DEBUG */
 
 /** define to enable/disable EDMA3 Driver debug messages*/
-#define EDMA3_DRV_DEBUG
-#undef EDMA3_DRV_DEBUG
+/* #define EDMA3_DRV_DEBUG */
 
 /** Debug mechanism used for Resource Manager */
 #ifdef EDMA3_RM_DEBUG
@@ -76,11 +74,6 @@ extern "C" {
   #define FALSE (0U)
 #endif
 
-/** Define for NULL values*/
-#ifndef NULL
-#define NULL 0u
-#endif
-
 /** EDMA3_RM Result - return value of a function  */
 typedef int32_t             EDMA3_RM_Result;
 /** EDMA3_DRV Result - return value of a function  */
index 8906c35358a117b79089ff7577ca99cc7e2dca5d..4731d8dca1e11e37906e0d0362d4cd28ac86e176 100755 (executable)
@@ -46,8 +46,8 @@
  * PaRAM Sets, TCCs etc.) and DMA Interrupt Service Routines.
  */
 
-#ifndef _EDMA3_RM_H_
-#define _EDMA3_RM_H_
+#ifndef EDMA3_RM_H_
+#define EDMA3_RM_H_
 
 #include <stdint.h>
 /** Include common header file */
index 03854cc5e67234edc0ef5364c43f3632514cdcba..830da1cdb87eec3d26956d9011cad7dd23f54d40 100644 (file)
@@ -36,8 +36,8 @@
  *
 */
 
-#ifndef _EDMA3_RL_CC_H_
-#define _EDMA3_RL_CC_H_
+#ifndef EDMA3_RL_CC_H_
+#define EDMA3_RL_CC_H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -217,7833 +217,7833 @@ typedef volatile EDMA3_CCRL_Regs  *EDMA3_CCRL_RegsOvly;
 
 /* REV */
 
-#define EDMA3_CCRL_REV_TYPE_MASK         (0x00FF0000u)
-#define EDMA3_CCRL_REV_TYPE_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_REV_TYPE_RESETVAL     (0x00000007u)
+#define EDMA3_CCRL_REV_TYPE_MASK         (0x00FF0000U)
+#define EDMA3_CCRL_REV_TYPE_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_REV_TYPE_RESETVAL     (0x00000007U)
 
-#define EDMA3_CCRL_REV_CLASS_MASK        (0x0000FF00u)
-#define EDMA3_CCRL_REV_CLASS_SHIFT       (0x00000008u)
-#define EDMA3_CCRL_REV_CLASS_RESETVAL    (0x00000004u)
+#define EDMA3_CCRL_REV_CLASS_MASK        (0x0000FF00U)
+#define EDMA3_CCRL_REV_CLASS_SHIFT       (0x00000008U)
+#define EDMA3_CCRL_REV_CLASS_RESETVAL    (0x00000004U)
 
-#define EDMA3_CCRL_REV_RESERVED_MASK     (0x000000FFu)
-#define EDMA3_CCRL_REV_RESERVED_SHIFT    (0x00000000u)
-#define EDMA3_CCRL_REV_RESERVED_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_REV_RESERVED_MASK     (0x000000FFU)
+#define EDMA3_CCRL_REV_RESERVED_SHIFT    (0x00000000U)
+#define EDMA3_CCRL_REV_RESERVED_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_REV_RESETVAL          (0x00070400u)
+#define EDMA3_CCRL_REV_RESETVAL          (0x00070400U)
 
 /* CCCFG */
 
-#define EDMA3_CCRL_CCCFG_MP_EXIST_MASK   (0x02000000u)
-#define EDMA3_CCRL_CCCFG_MP_EXIST_SHIFT  (0x00000019u)
-#define EDMA3_CCRL_CCCFG_MP_EXIST_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCCFG_MP_EXIST_MASK   (0x02000000U)
+#define EDMA3_CCRL_CCCFG_MP_EXIST_SHIFT  (0x00000019U)
+#define EDMA3_CCRL_CCCFG_MP_EXIST_RESETVAL (0x00000000U)
 
 /*----MP_EXIST Tokens----*/
-#define EDMA3_CCRL_CCCFG_MP_EXIST_NONE   (0x00000000u)
-#define EDMA3_CCRL_CCCFG_MP_EXIST_INCLUDED (0x00000001u)
+#define EDMA3_CCRL_CCCFG_MP_EXIST_NONE   (0x00000000U)
+#define EDMA3_CCRL_CCCFG_MP_EXIST_INCLUDED (0x00000001U)
 
-#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_MASK (0x01000000u)
-#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_SHIFT (0x00000018u)
-#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_MASK (0x01000000U)
+#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_SHIFT (0x00000018U)
+#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_RESETVAL (0x00000000U)
 
 /*----CHMAP_EXIST Tokens----*/
-#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_NONE (0x00000000u)
-#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_INCLUDED (0x00000001u)
+#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_NONE (0x00000000U)
+#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_INCLUDED (0x00000001U)
 
-#define EDMA3_CCRL_CCCFG_NUM_REGN_MASK   (0x00300000u)
-#define EDMA3_CCRL_CCCFG_NUM_REGN_SHIFT  (0x00000014u)
-#define EDMA3_CCRL_CCCFG_NUM_REGN_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_MASK   (0x00300000U)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_SHIFT  (0x00000014U)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_RESETVAL (0x00000000U)
 
 /*----NUM_REGN Tokens----*/
-#define EDMA3_CCRL_CCCFG_NUM_REGN_0      (0x00000000u)
-#define EDMA3_CCRL_CCCFG_NUM_REGN_2      (0x00000001u)
-#define EDMA3_CCRL_CCCFG_NUM_REGN_4      (0x00000002u)
-#define EDMA3_CCRL_CCCFG_NUM_REGN_8      (0x00000003u)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_0      (0x00000000U)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_2      (0x00000001U)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_4      (0x00000002U)
+#define EDMA3_CCRL_CCCFG_NUM_REGN_8      (0x00000003U)
 
-#define EDMA3_CCRL_CCCFG_NUM_TC_MASK     (0x00070000u)
-#define EDMA3_CCRL_CCCFG_NUM_TC_SHIFT    (0x00000010u)
-#define EDMA3_CCRL_CCCFG_NUM_TC_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_MASK     (0x00070000U)
+#define EDMA3_CCRL_CCCFG_NUM_TC_SHIFT    (0x00000010U)
+#define EDMA3_CCRL_CCCFG_NUM_TC_RESETVAL (0x00000000U)
 
 /*----NUM_TC Tokens----*/
-#define EDMA3_CCRL_CCCFG_NUM_TC_1        (0x00000000u)
-#define EDMA3_CCRL_CCCFG_NUM_TC_2        (0x00000001u)
-#define EDMA3_CCRL_CCCFG_NUM_TC_3        (0x00000002u)
-#define EDMA3_CCRL_CCCFG_NUM_TC_4        (0x00000003u)
-#define EDMA3_CCRL_CCCFG_NUM_TC_5        (0x00000004u)
-#define EDMA3_CCRL_CCCFG_NUM_TC_6        (0x00000005u)
-#define EDMA3_CCRL_CCCFG_NUM_TC_7        (0x00000006u)
-#define EDMA3_CCRL_CCCFG_NUM_TC_8        (0x00000007u)
-
-#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_MASK (0x00007000u)
-#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_SHIFT (0x0000000Cu)
-#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_TC_1        (0x00000000U)
+#define EDMA3_CCRL_CCCFG_NUM_TC_2        (0x00000001U)
+#define EDMA3_CCRL_CCCFG_NUM_TC_3        (0x00000002U)
+#define EDMA3_CCRL_CCCFG_NUM_TC_4        (0x00000003U)
+#define EDMA3_CCRL_CCCFG_NUM_TC_5        (0x00000004U)
+#define EDMA3_CCRL_CCCFG_NUM_TC_6        (0x00000005U)
+#define EDMA3_CCRL_CCCFG_NUM_TC_7        (0x00000006U)
+#define EDMA3_CCRL_CCCFG_NUM_TC_8        (0x00000007U)
+
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_MASK (0x00007000U)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_SHIFT (0x0000000CU)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_RESETVAL (0x00000000U)
 
 /*----NUM_PAENTRY Tokens----*/
-#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_16  (0x00000000u)
-#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_32  (0x00000001u)
-#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_64  (0x00000002u)
-#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_128 (0x00000003u)
-#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_256 (0x00000004u)
-#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_512 (0x00000005u)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_16  (0x00000000U)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_32  (0x00000001U)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_64  (0x00000002U)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_128 (0x00000003U)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_256 (0x00000004U)
+#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_512 (0x00000005U)
 
-#define EDMA3_CCRL_CCCFG_NUM_INTCH_MASK  (0x00000700u)
-#define EDMA3_CCRL_CCCFG_NUM_INTCH_SHIFT (0x00000008u)
-#define EDMA3_CCRL_CCCFG_NUM_INTCH_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_MASK  (0x00000700U)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_SHIFT (0x00000008U)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_RESETVAL (0x00000000U)
 
 /*----NUM_INTCH Tokens----*/
-#define EDMA3_CCRL_CCCFG_NUM_INTCH_8     (0x00000001u)
-#define EDMA3_CCRL_CCCFG_NUM_INTCH_16    (0x00000002u)
-#define EDMA3_CCRL_CCCFG_NUM_INTCH_32    (0x00000003u)
-#define EDMA3_CCRL_CCCFG_NUM_INTCH_64    (0x00000004u)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_8     (0x00000001U)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_16    (0x00000002U)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_32    (0x00000003U)
+#define EDMA3_CCRL_CCCFG_NUM_INTCH_64    (0x00000004U)
 
-#define EDMA3_CCRL_CCCFG_NUM_QDMACH_MASK (0x00000070u)
-#define EDMA3_CCRL_CCCFG_NUM_QDMACH_SHIFT (0x00000004u)
-#define EDMA3_CCRL_CCCFG_NUM_QDMACH_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_MASK (0x00000070U)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_SHIFT (0x00000004U)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_RESETVAL (0x00000000U)
 
 /*----NUM_QDMACH Tokens----*/
-#define EDMA3_CCRL_CCCFG_NUM_QDMACH_NONE (0x00000000u)
-#define EDMA3_CCRL_CCCFG_NUM_QDMACH_2    (0x00000001u)
-#define EDMA3_CCRL_CCCFG_NUM_QDMACH_4    (0x00000002u)
-#define EDMA3_CCRL_CCCFG_NUM_QDMACH_6    (0x00000003u)
-#define EDMA3_CCRL_CCCFG_NUM_QDMACH_8    (0x00000004u)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_NONE (0x00000000U)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_2    (0x00000001U)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_4    (0x00000002U)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_6    (0x00000003U)
+#define EDMA3_CCRL_CCCFG_NUM_QDMACH_8    (0x00000004U)
 
-#define EDMA3_CCRL_CCCFG_NUM_DMACH_MASK  (0x00000007u)
-#define EDMA3_CCRL_CCCFG_NUM_DMACH_SHIFT (0x00000000u)
-#define EDMA3_CCRL_CCCFG_NUM_DMACH_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_MASK  (0x00000007U)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_SHIFT (0x00000000U)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_RESETVAL (0x00000000U)
 
 /*----NUM_DMACH Tokens----*/
-#define EDMA3_CCRL_CCCFG_NUM_DMACH_NONE  (0x00000000u)
-#define EDMA3_CCRL_CCCFG_NUM_DMACH_4     (0x00000001u)
-#define EDMA3_CCRL_CCCFG_NUM_DMACH_8     (0x00000002u)
-#define EDMA3_CCRL_CCCFG_NUM_DMACH_16    (0x00000003u)
-#define EDMA3_CCRL_CCCFG_NUM_DMACH_32    (0x00000004u)
-#define EDMA3_CCRL_CCCFG_NUM_DMACH_64    (0x00000005u)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_NONE  (0x00000000U)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_4     (0x00000001U)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_8     (0x00000002U)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_16    (0x00000003U)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_32    (0x00000004U)
+#define EDMA3_CCRL_CCCFG_NUM_DMACH_64    (0x00000005U)
 
-#define EDMA3_CCRL_CCCFG_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_CCCFG_RESETVAL        (0x00000000U)
 
 /* DCHMAP */
 
-#define EDMA3_CCRL_DCHMAP_PAENTRY_MASK   (0x00003FE0u)
-#define EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT  (0x00000005u)
-#define EDMA3_CCRL_DCHMAP_PAENTRY_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_DCHMAP_PAENTRY_MASK   (0x00003FE0U)
+#define EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT  (0x00000005U)
+#define EDMA3_CCRL_DCHMAP_PAENTRY_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_DCHMAP_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_DCHMAP_RESETVAL       (0x00000000U)
 
 /* QCHMAP */
 
-#define EDMA3_CCRL_QCHMAP_PAENTRY_MASK   (0x00003FE0u)
-#define EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT  (0x00000005u)
-#define EDMA3_CCRL_QCHMAP_PAENTRY_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QCHMAP_PAENTRY_MASK   (0x00003FE0U)
+#define EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT  (0x00000005U)
+#define EDMA3_CCRL_QCHMAP_PAENTRY_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QCHMAP_TRWORD_MASK    (0x0000001Cu)
-#define EDMA3_CCRL_QCHMAP_TRWORD_SHIFT   (0x00000002u)
-#define EDMA3_CCRL_QCHMAP_TRWORD_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QCHMAP_TRWORD_MASK    (0x0000001CU)
+#define EDMA3_CCRL_QCHMAP_TRWORD_SHIFT   (0x00000002U)
+#define EDMA3_CCRL_QCHMAP_TRWORD_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QCHMAP_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_QCHMAP_RESETVAL       (0x00000000U)
 
 /* DMAQNUM */
 
-#define EDMA3_CCRL_DMAQNUM_E7_MASK       (0x70000000u)
-#define EDMA3_CCRL_DMAQNUM_E7_SHIFT      (0x0000001Cu)
-#define EDMA3_CCRL_DMAQNUM_E7_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E7_MASK       (0x70000000U)
+#define EDMA3_CCRL_DMAQNUM_E7_SHIFT      (0x0000001CU)
+#define EDMA3_CCRL_DMAQNUM_E7_RESETVAL   (0x00000000U)
 
-#define EDMA3_CCRL_DMAQNUM_E6_MASK       (0x07000000u)
-#define EDMA3_CCRL_DMAQNUM_E6_SHIFT      (0x00000018u)
-#define EDMA3_CCRL_DMAQNUM_E6_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E6_MASK       (0x07000000U)
+#define EDMA3_CCRL_DMAQNUM_E6_SHIFT      (0x00000018U)
+#define EDMA3_CCRL_DMAQNUM_E6_RESETVAL   (0x00000000U)
 
-#define EDMA3_CCRL_DMAQNUM_E5_MASK       (0x00700000u)
-#define EDMA3_CCRL_DMAQNUM_E5_SHIFT      (0x00000014u)
-#define EDMA3_CCRL_DMAQNUM_E5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E5_MASK       (0x00700000U)
+#define EDMA3_CCRL_DMAQNUM_E5_SHIFT      (0x00000014U)
+#define EDMA3_CCRL_DMAQNUM_E5_RESETVAL   (0x00000000U)
 
-#define EDMA3_CCRL_DMAQNUM_E4_MASK       (0x00070000u)
-#define EDMA3_CCRL_DMAQNUM_E4_SHIFT      (0x00000010u)
-#define EDMA3_CCRL_DMAQNUM_E4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E4_MASK       (0x00070000U)
+#define EDMA3_CCRL_DMAQNUM_E4_SHIFT      (0x00000010U)
+#define EDMA3_CCRL_DMAQNUM_E4_RESETVAL   (0x00000000U)
 
-#define EDMA3_CCRL_DMAQNUM_E3_MASK       (0x00007000u)
-#define EDMA3_CCRL_DMAQNUM_E3_SHIFT      (0x0000000Cu)
-#define EDMA3_CCRL_DMAQNUM_E3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E3_MASK       (0x00007000U)
+#define EDMA3_CCRL_DMAQNUM_E3_SHIFT      (0x0000000CU)
+#define EDMA3_CCRL_DMAQNUM_E3_RESETVAL   (0x00000000U)
 
-#define EDMA3_CCRL_DMAQNUM_E2_MASK       (0x00000700u)
-#define EDMA3_CCRL_DMAQNUM_E2_SHIFT      (0x00000008u)
-#define EDMA3_CCRL_DMAQNUM_E2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E2_MASK       (0x00000700U)
+#define EDMA3_CCRL_DMAQNUM_E2_SHIFT      (0x00000008U)
+#define EDMA3_CCRL_DMAQNUM_E2_RESETVAL   (0x00000000U)
 
-#define EDMA3_CCRL_DMAQNUM_E1_MASK       (0x00000070u)
-#define EDMA3_CCRL_DMAQNUM_E1_SHIFT      (0x00000004u)
-#define EDMA3_CCRL_DMAQNUM_E1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E1_MASK       (0x00000070U)
+#define EDMA3_CCRL_DMAQNUM_E1_SHIFT      (0x00000004U)
+#define EDMA3_CCRL_DMAQNUM_E1_RESETVAL   (0x00000000U)
 
-#define EDMA3_CCRL_DMAQNUM_E0_MASK       (0x00000007u)
-#define EDMA3_CCRL_DMAQNUM_E0_SHIFT      (0x00000000u)
-#define EDMA3_CCRL_DMAQNUM_E0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_E0_MASK       (0x00000007U)
+#define EDMA3_CCRL_DMAQNUM_E0_SHIFT      (0x00000000U)
+#define EDMA3_CCRL_DMAQNUM_E0_RESETVAL   (0x00000000U)
 
-#define EDMA3_CCRL_DMAQNUM_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DMAQNUM_RESETVAL      (0x00000000U)
 
 /* QDMAQNUM */
 
-#define EDMA3_CCRL_QDMAQNUM_E7_MASK      (0x70000000u)
-#define EDMA3_CCRL_QDMAQNUM_E7_SHIFT     (0x0000001Cu)
-#define EDMA3_CCRL_QDMAQNUM_E7_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E7_MASK      (0x70000000U)
+#define EDMA3_CCRL_QDMAQNUM_E7_SHIFT     (0x0000001CU)
+#define EDMA3_CCRL_QDMAQNUM_E7_RESETVAL  (0x00000000U)
 
-#define EDMA3_CCRL_QDMAQNUM_E6_MASK      (0x07000000u)
-#define EDMA3_CCRL_QDMAQNUM_E6_SHIFT     (0x00000018u)
-#define EDMA3_CCRL_QDMAQNUM_E6_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E6_MASK      (0x07000000U)
+#define EDMA3_CCRL_QDMAQNUM_E6_SHIFT     (0x00000018U)
+#define EDMA3_CCRL_QDMAQNUM_E6_RESETVAL  (0x00000000U)
 
-#define EDMA3_CCRL_QDMAQNUM_E5_MASK      (0x00700000u)
-#define EDMA3_CCRL_QDMAQNUM_E5_SHIFT     (0x00000014u)
-#define EDMA3_CCRL_QDMAQNUM_E5_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E5_MASK      (0x00700000U)
+#define EDMA3_CCRL_QDMAQNUM_E5_SHIFT     (0x00000014U)
+#define EDMA3_CCRL_QDMAQNUM_E5_RESETVAL  (0x00000000U)
 
-#define EDMA3_CCRL_QDMAQNUM_E4_MASK      (0x00070000u)
-#define EDMA3_CCRL_QDMAQNUM_E4_SHIFT     (0x00000010u)
-#define EDMA3_CCRL_QDMAQNUM_E4_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E4_MASK      (0x00070000U)
+#define EDMA3_CCRL_QDMAQNUM_E4_SHIFT     (0x00000010U)
+#define EDMA3_CCRL_QDMAQNUM_E4_RESETVAL  (0x00000000U)
 
-#define EDMA3_CCRL_QDMAQNUM_E3_MASK      (0x00007000u)
-#define EDMA3_CCRL_QDMAQNUM_E3_SHIFT     (0x0000000Cu)
-#define EDMA3_CCRL_QDMAQNUM_E3_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E3_MASK      (0x00007000U)
+#define EDMA3_CCRL_QDMAQNUM_E3_SHIFT     (0x0000000CU)
+#define EDMA3_CCRL_QDMAQNUM_E3_RESETVAL  (0x00000000U)
 
-#define EDMA3_CCRL_QDMAQNUM_E2_MASK      (0x00000700u)
-#define EDMA3_CCRL_QDMAQNUM_E2_SHIFT     (0x00000008u)
-#define EDMA3_CCRL_QDMAQNUM_E2_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E2_MASK      (0x00000700U)
+#define EDMA3_CCRL_QDMAQNUM_E2_SHIFT     (0x00000008U)
+#define EDMA3_CCRL_QDMAQNUM_E2_RESETVAL  (0x00000000U)
 
-#define EDMA3_CCRL_QDMAQNUM_E1_MASK      (0x00000070u)
-#define EDMA3_CCRL_QDMAQNUM_E1_SHIFT     (0x00000004u)
-#define EDMA3_CCRL_QDMAQNUM_E1_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E1_MASK      (0x00000070U)
+#define EDMA3_CCRL_QDMAQNUM_E1_SHIFT     (0x00000004U)
+#define EDMA3_CCRL_QDMAQNUM_E1_RESETVAL  (0x00000000U)
 
-#define EDMA3_CCRL_QDMAQNUM_E0_MASK      (0x00000007u)
-#define EDMA3_CCRL_QDMAQNUM_E0_SHIFT     (0x00000000u)
-#define EDMA3_CCRL_QDMAQNUM_E0_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_E0_MASK      (0x00000007U)
+#define EDMA3_CCRL_QDMAQNUM_E0_SHIFT     (0x00000000U)
+#define EDMA3_CCRL_QDMAQNUM_E0_RESETVAL  (0x00000000U)
 
-#define EDMA3_CCRL_QDMAQNUM_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QDMAQNUM_RESETVAL     (0x00000000U)
 
 /* QUETCMAP */
 
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_MASK (0x70000000u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_SHIFT (0x0000001Cu)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_MASK (0x70000000U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_SHIFT (0x0000001CU)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_MASK (0x07000000u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_SHIFT (0x00000018u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_MASK (0x07000000U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_SHIFT (0x00000018U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_MASK (0x00700000u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_SHIFT (0x00000014u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_MASK (0x00700000U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_SHIFT (0x00000014U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_MASK (0x00070000u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_SHIFT (0x00000010u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_MASK (0x00070000U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_SHIFT (0x00000010U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_MASK (0x00007000u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_SHIFT (0x0000000Cu)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_MASK (0x00007000U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_SHIFT (0x0000000CU)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_MASK (0x00000700u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_SHIFT (0x00000008u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_MASK (0x00000700U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_SHIFT (0x00000008U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_MASK (0x00000070u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_SHIFT (0x00000004u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_MASK (0x00000070U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_SHIFT (0x00000004U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_MASK (0x00000007u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_SHIFT (0x00000000u)
-#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_MASK (0x00000007U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_SHIFT (0x00000000U)
+#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUETCMAP_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QUETCMAP_RESETVAL     (0x00000000U)
 
 /* QUEPRI */
 
-#define EDMA3_CCRL_QUEPRI_PRIQ7_MASK     (0x70000000u)
-#define EDMA3_CCRL_QUEPRI_PRIQ7_SHIFT    (0x0000001Cu)
-#define EDMA3_CCRL_QUEPRI_PRIQ7_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ7_MASK     (0x70000000U)
+#define EDMA3_CCRL_QUEPRI_PRIQ7_SHIFT    (0x0000001CU)
+#define EDMA3_CCRL_QUEPRI_PRIQ7_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEPRI_PRIQ6_MASK     (0x07000000u)
-#define EDMA3_CCRL_QUEPRI_PRIQ6_SHIFT    (0x00000018u)
-#define EDMA3_CCRL_QUEPRI_PRIQ6_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ6_MASK     (0x07000000U)
+#define EDMA3_CCRL_QUEPRI_PRIQ6_SHIFT    (0x00000018U)
+#define EDMA3_CCRL_QUEPRI_PRIQ6_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEPRI_PRIQ5_MASK     (0x00700000u)
-#define EDMA3_CCRL_QUEPRI_PRIQ5_SHIFT    (0x00000014u)
-#define EDMA3_CCRL_QUEPRI_PRIQ5_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ5_MASK     (0x00700000U)
+#define EDMA3_CCRL_QUEPRI_PRIQ5_SHIFT    (0x00000014U)
+#define EDMA3_CCRL_QUEPRI_PRIQ5_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEPRI_PRIQ4_MASK     (0x00070000u)
-#define EDMA3_CCRL_QUEPRI_PRIQ4_SHIFT    (0x00000010u)
-#define EDMA3_CCRL_QUEPRI_PRIQ4_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ4_MASK     (0x00070000U)
+#define EDMA3_CCRL_QUEPRI_PRIQ4_SHIFT    (0x00000010U)
+#define EDMA3_CCRL_QUEPRI_PRIQ4_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEPRI_PRIQ3_MASK     (0x00007000u)
-#define EDMA3_CCRL_QUEPRI_PRIQ3_SHIFT    (0x0000000Cu)
-#define EDMA3_CCRL_QUEPRI_PRIQ3_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ3_MASK     (0x00007000U)
+#define EDMA3_CCRL_QUEPRI_PRIQ3_SHIFT    (0x0000000CU)
+#define EDMA3_CCRL_QUEPRI_PRIQ3_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEPRI_PRIQ2_MASK     (0x00000700u)
-#define EDMA3_CCRL_QUEPRI_PRIQ2_SHIFT    (0x00000008u)
-#define EDMA3_CCRL_QUEPRI_PRIQ2_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ2_MASK     (0x00000700U)
+#define EDMA3_CCRL_QUEPRI_PRIQ2_SHIFT    (0x00000008U)
+#define EDMA3_CCRL_QUEPRI_PRIQ2_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEPRI_PRIQ1_MASK     (0x00000070u)
-#define EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT    (0x00000004u)
-#define EDMA3_CCRL_QUEPRI_PRIQ1_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ1_MASK     (0x00000070U)
+#define EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT    (0x00000004U)
+#define EDMA3_CCRL_QUEPRI_PRIQ1_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEPRI_PRIQ0_MASK     (0x00000007u)
-#define EDMA3_CCRL_QUEPRI_PRIQ0_SHIFT    (0x00000000u)
-#define EDMA3_CCRL_QUEPRI_PRIQ0_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_PRIQ0_MASK     (0x00000007U)
+#define EDMA3_CCRL_QUEPRI_PRIQ0_SHIFT    (0x00000000U)
+#define EDMA3_CCRL_QUEPRI_PRIQ0_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEPRI_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_QUEPRI_RESETVAL       (0x00000000U)
 
 /* EMR */
 
-#define EDMA3_CCRL_EMR_E31_MASK          (0x80000000u)
-#define EDMA3_CCRL_EMR_E31_SHIFT         (0x0000001Fu)
-#define EDMA3_CCRL_EMR_E31_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E31_MASK          (0x80000000U)
+#define EDMA3_CCRL_EMR_E31_SHIFT         (0x0000001FU)
+#define EDMA3_CCRL_EMR_E31_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E30_MASK          (0x40000000u)
-#define EDMA3_CCRL_EMR_E30_SHIFT         (0x0000001Eu)
-#define EDMA3_CCRL_EMR_E30_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E30_MASK          (0x40000000U)
+#define EDMA3_CCRL_EMR_E30_SHIFT         (0x0000001EU)
+#define EDMA3_CCRL_EMR_E30_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E29_MASK          (0x20000000u)
-#define EDMA3_CCRL_EMR_E29_SHIFT         (0x0000001Du)
-#define EDMA3_CCRL_EMR_E29_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E29_MASK          (0x20000000U)
+#define EDMA3_CCRL_EMR_E29_SHIFT         (0x0000001DU)
+#define EDMA3_CCRL_EMR_E29_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E28_MASK          (0x10000000u)
-#define EDMA3_CCRL_EMR_E28_SHIFT         (0x0000001Cu)
-#define EDMA3_CCRL_EMR_E28_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E28_MASK          (0x10000000U)
+#define EDMA3_CCRL_EMR_E28_SHIFT         (0x0000001CU)
+#define EDMA3_CCRL_EMR_E28_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E27_MASK          (0x08000000u)
-#define EDMA3_CCRL_EMR_E27_SHIFT         (0x0000001Bu)
-#define EDMA3_CCRL_EMR_E27_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E27_MASK          (0x08000000U)
+#define EDMA3_CCRL_EMR_E27_SHIFT         (0x0000001BU)
+#define EDMA3_CCRL_EMR_E27_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E26_MASK          (0x04000000u)
-#define EDMA3_CCRL_EMR_E26_SHIFT         (0x0000001Au)
-#define EDMA3_CCRL_EMR_E26_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E26_MASK          (0x04000000U)
+#define EDMA3_CCRL_EMR_E26_SHIFT         (0x0000001AU)
+#define EDMA3_CCRL_EMR_E26_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E25_MASK          (0x02000000u)
-#define EDMA3_CCRL_EMR_E25_SHIFT         (0x00000019u)
-#define EDMA3_CCRL_EMR_E25_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E25_MASK          (0x02000000U)
+#define EDMA3_CCRL_EMR_E25_SHIFT         (0x00000019U)
+#define EDMA3_CCRL_EMR_E25_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E24_MASK          (0x01000000u)
-#define EDMA3_CCRL_EMR_E24_SHIFT         (0x00000018u)
-#define EDMA3_CCRL_EMR_E24_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E24_MASK          (0x01000000U)
+#define EDMA3_CCRL_EMR_E24_SHIFT         (0x00000018U)
+#define EDMA3_CCRL_EMR_E24_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E23_MASK          (0x00800000u)
-#define EDMA3_CCRL_EMR_E23_SHIFT         (0x00000017u)
-#define EDMA3_CCRL_EMR_E23_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E23_MASK          (0x00800000U)
+#define EDMA3_CCRL_EMR_E23_SHIFT         (0x00000017U)
+#define EDMA3_CCRL_EMR_E23_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E22_MASK          (0x00400000u)
-#define EDMA3_CCRL_EMR_E22_SHIFT         (0x00000016u)
-#define EDMA3_CCRL_EMR_E22_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E22_MASK          (0x00400000U)
+#define EDMA3_CCRL_EMR_E22_SHIFT         (0x00000016U)
+#define EDMA3_CCRL_EMR_E22_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E21_MASK          (0x00200000u)
-#define EDMA3_CCRL_EMR_E21_SHIFT         (0x00000015u)
-#define EDMA3_CCRL_EMR_E21_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E21_MASK          (0x00200000U)
+#define EDMA3_CCRL_EMR_E21_SHIFT         (0x00000015U)
+#define EDMA3_CCRL_EMR_E21_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E20_MASK          (0x00100000u)
-#define EDMA3_CCRL_EMR_E20_SHIFT         (0x00000014u)
-#define EDMA3_CCRL_EMR_E20_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E20_MASK          (0x00100000U)
+#define EDMA3_CCRL_EMR_E20_SHIFT         (0x00000014U)
+#define EDMA3_CCRL_EMR_E20_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E19_MASK          (0x00080000u)
-#define EDMA3_CCRL_EMR_E19_SHIFT         (0x00000013u)
-#define EDMA3_CCRL_EMR_E19_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E19_MASK          (0x00080000U)
+#define EDMA3_CCRL_EMR_E19_SHIFT         (0x00000013U)
+#define EDMA3_CCRL_EMR_E19_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E18_MASK          (0x00040000u)
-#define EDMA3_CCRL_EMR_E18_SHIFT         (0x00000012u)
-#define EDMA3_CCRL_EMR_E18_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E18_MASK          (0x00040000U)
+#define EDMA3_CCRL_EMR_E18_SHIFT         (0x00000012U)
+#define EDMA3_CCRL_EMR_E18_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E17_MASK          (0x00020000u)
-#define EDMA3_CCRL_EMR_E17_SHIFT         (0x00000011u)
-#define EDMA3_CCRL_EMR_E17_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E17_MASK          (0x00020000U)
+#define EDMA3_CCRL_EMR_E17_SHIFT         (0x00000011U)
+#define EDMA3_CCRL_EMR_E17_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E16_MASK          (0x00010000u)
-#define EDMA3_CCRL_EMR_E16_SHIFT         (0x00000010u)
-#define EDMA3_CCRL_EMR_E16_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E16_MASK          (0x00010000U)
+#define EDMA3_CCRL_EMR_E16_SHIFT         (0x00000010U)
+#define EDMA3_CCRL_EMR_E16_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E15_MASK          (0x00008000u)
-#define EDMA3_CCRL_EMR_E15_SHIFT         (0x0000000Fu)
-#define EDMA3_CCRL_EMR_E15_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E15_MASK          (0x00008000U)
+#define EDMA3_CCRL_EMR_E15_SHIFT         (0x0000000FU)
+#define EDMA3_CCRL_EMR_E15_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E14_MASK          (0x00004000u)
-#define EDMA3_CCRL_EMR_E14_SHIFT         (0x0000000Eu)
-#define EDMA3_CCRL_EMR_E14_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E14_MASK          (0x00004000U)
+#define EDMA3_CCRL_EMR_E14_SHIFT         (0x0000000EU)
+#define EDMA3_CCRL_EMR_E14_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E13_MASK          (0x00002000u)
-#define EDMA3_CCRL_EMR_E13_SHIFT         (0x0000000Du)
-#define EDMA3_CCRL_EMR_E13_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E13_MASK          (0x00002000U)
+#define EDMA3_CCRL_EMR_E13_SHIFT         (0x0000000DU)
+#define EDMA3_CCRL_EMR_E13_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E12_MASK          (0x00001000u)
-#define EDMA3_CCRL_EMR_E12_SHIFT         (0x0000000Cu)
-#define EDMA3_CCRL_EMR_E12_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E12_MASK          (0x00001000U)
+#define EDMA3_CCRL_EMR_E12_SHIFT         (0x0000000CU)
+#define EDMA3_CCRL_EMR_E12_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E11_MASK          (0x00000800u)
-#define EDMA3_CCRL_EMR_E11_SHIFT         (0x0000000Bu)
-#define EDMA3_CCRL_EMR_E11_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E11_MASK          (0x00000800U)
+#define EDMA3_CCRL_EMR_E11_SHIFT         (0x0000000BU)
+#define EDMA3_CCRL_EMR_E11_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E10_MASK          (0x00000400u)
-#define EDMA3_CCRL_EMR_E10_SHIFT         (0x0000000Au)
-#define EDMA3_CCRL_EMR_E10_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMR_E10_MASK          (0x00000400U)
+#define EDMA3_CCRL_EMR_E10_SHIFT         (0x0000000AU)
+#define EDMA3_CCRL_EMR_E10_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E9_MASK           (0x00000200u)
-#define EDMA3_CCRL_EMR_E9_SHIFT          (0x00000009u)
-#define EDMA3_CCRL_EMR_E9_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EMR_E9_MASK           (0x00000200U)
+#define EDMA3_CCRL_EMR_E9_SHIFT          (0x00000009U)
+#define EDMA3_CCRL_EMR_E9_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E8_MASK           (0x00000100u)
-#define EDMA3_CCRL_EMR_E8_SHIFT          (0x00000008u)
-#define EDMA3_CCRL_EMR_E8_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EMR_E8_MASK           (0x00000100U)
+#define EDMA3_CCRL_EMR_E8_SHIFT          (0x00000008U)
+#define EDMA3_CCRL_EMR_E8_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E7_MASK           (0x00000080u)
-#define EDMA3_CCRL_EMR_E7_SHIFT          (0x00000007u)
-#define EDMA3_CCRL_EMR_E7_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EMR_E7_MASK           (0x00000080U)
+#define EDMA3_CCRL_EMR_E7_SHIFT          (0x00000007U)
+#define EDMA3_CCRL_EMR_E7_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E6_MASK           (0x00000040u)
-#define EDMA3_CCRL_EMR_E6_SHIFT          (0x00000006u)
-#define EDMA3_CCRL_EMR_E6_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EMR_E6_MASK           (0x00000040U)
+#define EDMA3_CCRL_EMR_E6_SHIFT          (0x00000006U)
+#define EDMA3_CCRL_EMR_E6_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E5_MASK           (0x00000020u)
-#define EDMA3_CCRL_EMR_E5_SHIFT          (0x00000005u)
-#define EDMA3_CCRL_EMR_E5_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EMR_E5_MASK           (0x00000020U)
+#define EDMA3_CCRL_EMR_E5_SHIFT          (0x00000005U)
+#define EDMA3_CCRL_EMR_E5_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E4_MASK           (0x00000010u)
-#define EDMA3_CCRL_EMR_E4_SHIFT          (0x00000004u)
-#define EDMA3_CCRL_EMR_E4_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EMR_E4_MASK           (0x00000010U)
+#define EDMA3_CCRL_EMR_E4_SHIFT          (0x00000004U)
+#define EDMA3_CCRL_EMR_E4_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E3_MASK           (0x00000008u)
-#define EDMA3_CCRL_EMR_E3_SHIFT          (0x00000003u)
-#define EDMA3_CCRL_EMR_E3_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EMR_E3_MASK           (0x00000008U)
+#define EDMA3_CCRL_EMR_E3_SHIFT          (0x00000003U)
+#define EDMA3_CCRL_EMR_E3_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E2_MASK           (0x00000004u)
-#define EDMA3_CCRL_EMR_E2_SHIFT          (0x00000002u)
-#define EDMA3_CCRL_EMR_E2_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EMR_E2_MASK           (0x00000004U)
+#define EDMA3_CCRL_EMR_E2_SHIFT          (0x00000002U)
+#define EDMA3_CCRL_EMR_E2_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E1_MASK           (0x00000002u)
-#define EDMA3_CCRL_EMR_E1_SHIFT          (0x00000001u)
-#define EDMA3_CCRL_EMR_E1_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EMR_E1_MASK           (0x00000002U)
+#define EDMA3_CCRL_EMR_E1_SHIFT          (0x00000001U)
+#define EDMA3_CCRL_EMR_E1_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EMR_E0_MASK           (0x00000001u)
-#define EDMA3_CCRL_EMR_E0_SHIFT          (0x00000000u)
-#define EDMA3_CCRL_EMR_E0_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EMR_E0_MASK           (0x00000001U)
+#define EDMA3_CCRL_EMR_E0_SHIFT          (0x00000000U)
+#define EDMA3_CCRL_EMR_E0_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EMR_RESETVAL          (0x00000000u)
+#define EDMA3_CCRL_EMR_RESETVAL          (0x00000000U)
 
 /* EMRH */
 
-#define EDMA3_CCRL_EMRH_E63_MASK         (0x80000000u)
-#define EDMA3_CCRL_EMRH_E63_SHIFT        (0x0000001Fu)
-#define EDMA3_CCRL_EMRH_E63_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E63_MASK         (0x80000000U)
+#define EDMA3_CCRL_EMRH_E63_SHIFT        (0x0000001FU)
+#define EDMA3_CCRL_EMRH_E63_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E62_MASK         (0x40000000u)
-#define EDMA3_CCRL_EMRH_E62_SHIFT        (0x0000001Eu)
-#define EDMA3_CCRL_EMRH_E62_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E62_MASK         (0x40000000U)
+#define EDMA3_CCRL_EMRH_E62_SHIFT        (0x0000001EU)
+#define EDMA3_CCRL_EMRH_E62_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E61_MASK         (0x20000000u)
-#define EDMA3_CCRL_EMRH_E61_SHIFT        (0x0000001Du)
-#define EDMA3_CCRL_EMRH_E61_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E61_MASK         (0x20000000U)
+#define EDMA3_CCRL_EMRH_E61_SHIFT        (0x0000001DU)
+#define EDMA3_CCRL_EMRH_E61_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E60_MASK         (0x10000000u)
-#define EDMA3_CCRL_EMRH_E60_SHIFT        (0x0000001Cu)
-#define EDMA3_CCRL_EMRH_E60_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E60_MASK         (0x10000000U)
+#define EDMA3_CCRL_EMRH_E60_SHIFT        (0x0000001CU)
+#define EDMA3_CCRL_EMRH_E60_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E59_MASK         (0x08000000u)
-#define EDMA3_CCRL_EMRH_E59_SHIFT        (0x0000001Bu)
-#define EDMA3_CCRL_EMRH_E59_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E59_MASK         (0x08000000U)
+#define EDMA3_CCRL_EMRH_E59_SHIFT        (0x0000001BU)
+#define EDMA3_CCRL_EMRH_E59_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E58_MASK         (0x04000000u)
-#define EDMA3_CCRL_EMRH_E58_SHIFT        (0x0000001Au)
-#define EDMA3_CCRL_EMRH_E58_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E58_MASK         (0x04000000U)
+#define EDMA3_CCRL_EMRH_E58_SHIFT        (0x0000001AU)
+#define EDMA3_CCRL_EMRH_E58_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E57_MASK         (0x02000000u)
-#define EDMA3_CCRL_EMRH_E57_SHIFT        (0x00000019u)
-#define EDMA3_CCRL_EMRH_E57_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E57_MASK         (0x02000000U)
+#define EDMA3_CCRL_EMRH_E57_SHIFT        (0x00000019U)
+#define EDMA3_CCRL_EMRH_E57_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E56_MASK         (0x01000000u)
-#define EDMA3_CCRL_EMRH_E56_SHIFT        (0x00000018u)
-#define EDMA3_CCRL_EMRH_E56_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E56_MASK         (0x01000000U)
+#define EDMA3_CCRL_EMRH_E56_SHIFT        (0x00000018U)
+#define EDMA3_CCRL_EMRH_E56_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E55_MASK         (0x00800000u)
-#define EDMA3_CCRL_EMRH_E55_SHIFT        (0x00000017u)
-#define EDMA3_CCRL_EMRH_E55_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E55_MASK         (0x00800000U)
+#define EDMA3_CCRL_EMRH_E55_SHIFT        (0x00000017U)
+#define EDMA3_CCRL_EMRH_E55_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E54_MASK         (0x00400000u)
-#define EDMA3_CCRL_EMRH_E54_SHIFT        (0x00000016u)
-#define EDMA3_CCRL_EMRH_E54_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E54_MASK         (0x00400000U)
+#define EDMA3_CCRL_EMRH_E54_SHIFT        (0x00000016U)
+#define EDMA3_CCRL_EMRH_E54_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E53_MASK         (0x00200000u)
-#define EDMA3_CCRL_EMRH_E53_SHIFT        (0x00000015u)
-#define EDMA3_CCRL_EMRH_E53_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E53_MASK         (0x00200000U)
+#define EDMA3_CCRL_EMRH_E53_SHIFT        (0x00000015U)
+#define EDMA3_CCRL_EMRH_E53_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E52_MASK         (0x00100000u)
-#define EDMA3_CCRL_EMRH_E52_SHIFT        (0x00000014u)
-#define EDMA3_CCRL_EMRH_E52_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E52_MASK         (0x00100000U)
+#define EDMA3_CCRL_EMRH_E52_SHIFT        (0x00000014U)
+#define EDMA3_CCRL_EMRH_E52_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E51_MASK         (0x00080000u)
-#define EDMA3_CCRL_EMRH_E51_SHIFT        (0x00000013u)
-#define EDMA3_CCRL_EMRH_E51_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E51_MASK         (0x00080000U)
+#define EDMA3_CCRL_EMRH_E51_SHIFT        (0x00000013U)
+#define EDMA3_CCRL_EMRH_E51_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E50_MASK         (0x00040000u)
-#define EDMA3_CCRL_EMRH_E50_SHIFT        (0x00000012u)
-#define EDMA3_CCRL_EMRH_E50_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E50_MASK         (0x00040000U)
+#define EDMA3_CCRL_EMRH_E50_SHIFT        (0x00000012U)
+#define EDMA3_CCRL_EMRH_E50_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E49_MASK         (0x00020000u)
-#define EDMA3_CCRL_EMRH_E49_SHIFT        (0x00000011u)
-#define EDMA3_CCRL_EMRH_E49_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E49_MASK         (0x00020000U)
+#define EDMA3_CCRL_EMRH_E49_SHIFT        (0x00000011U)
+#define EDMA3_CCRL_EMRH_E49_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E48_MASK         (0x00010000u)
-#define EDMA3_CCRL_EMRH_E48_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_EMRH_E48_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E48_MASK         (0x00010000U)
+#define EDMA3_CCRL_EMRH_E48_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_EMRH_E48_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E47_MASK         (0x00008000u)
-#define EDMA3_CCRL_EMRH_E47_SHIFT        (0x0000000Fu)
-#define EDMA3_CCRL_EMRH_E47_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E47_MASK         (0x00008000U)
+#define EDMA3_CCRL_EMRH_E47_SHIFT        (0x0000000FU)
+#define EDMA3_CCRL_EMRH_E47_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E46_MASK         (0x00004000u)
-#define EDMA3_CCRL_EMRH_E46_SHIFT        (0x0000000Eu)
-#define EDMA3_CCRL_EMRH_E46_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E46_MASK         (0x00004000U)
+#define EDMA3_CCRL_EMRH_E46_SHIFT        (0x0000000EU)
+#define EDMA3_CCRL_EMRH_E46_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E45_MASK         (0x00002000u)
-#define EDMA3_CCRL_EMRH_E45_SHIFT        (0x0000000Du)
-#define EDMA3_CCRL_EMRH_E45_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E45_MASK         (0x00002000U)
+#define EDMA3_CCRL_EMRH_E45_SHIFT        (0x0000000DU)
+#define EDMA3_CCRL_EMRH_E45_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E44_MASK         (0x00001000u)
-#define EDMA3_CCRL_EMRH_E44_SHIFT        (0x0000000Cu)
-#define EDMA3_CCRL_EMRH_E44_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E44_MASK         (0x00001000U)
+#define EDMA3_CCRL_EMRH_E44_SHIFT        (0x0000000CU)
+#define EDMA3_CCRL_EMRH_E44_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E43_MASK         (0x00000800u)
-#define EDMA3_CCRL_EMRH_E43_SHIFT        (0x0000000Bu)
-#define EDMA3_CCRL_EMRH_E43_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E43_MASK         (0x00000800U)
+#define EDMA3_CCRL_EMRH_E43_SHIFT        (0x0000000BU)
+#define EDMA3_CCRL_EMRH_E43_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E42_MASK         (0x00000400u)
-#define EDMA3_CCRL_EMRH_E42_SHIFT        (0x0000000Au)
-#define EDMA3_CCRL_EMRH_E42_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E42_MASK         (0x00000400U)
+#define EDMA3_CCRL_EMRH_E42_SHIFT        (0x0000000AU)
+#define EDMA3_CCRL_EMRH_E42_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E41_MASK         (0x00000200u)
-#define EDMA3_CCRL_EMRH_E41_SHIFT        (0x00000009u)
-#define EDMA3_CCRL_EMRH_E41_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E41_MASK         (0x00000200U)
+#define EDMA3_CCRL_EMRH_E41_SHIFT        (0x00000009U)
+#define EDMA3_CCRL_EMRH_E41_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E40_MASK         (0x00000100u)
-#define EDMA3_CCRL_EMRH_E40_SHIFT        (0x00000008u)
-#define EDMA3_CCRL_EMRH_E40_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E40_MASK         (0x00000100U)
+#define EDMA3_CCRL_EMRH_E40_SHIFT        (0x00000008U)
+#define EDMA3_CCRL_EMRH_E40_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E39_MASK         (0x00000080u)
-#define EDMA3_CCRL_EMRH_E39_SHIFT        (0x00000007u)
-#define EDMA3_CCRL_EMRH_E39_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E39_MASK         (0x00000080U)
+#define EDMA3_CCRL_EMRH_E39_SHIFT        (0x00000007U)
+#define EDMA3_CCRL_EMRH_E39_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E38_MASK         (0x00000040u)
-#define EDMA3_CCRL_EMRH_E38_SHIFT        (0x00000006u)
-#define EDMA3_CCRL_EMRH_E38_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E38_MASK         (0x00000040U)
+#define EDMA3_CCRL_EMRH_E38_SHIFT        (0x00000006U)
+#define EDMA3_CCRL_EMRH_E38_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E37_MASK         (0x00000020u)
-#define EDMA3_CCRL_EMRH_E37_SHIFT        (0x00000005u)
-#define EDMA3_CCRL_EMRH_E37_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E37_MASK         (0x00000020U)
+#define EDMA3_CCRL_EMRH_E37_SHIFT        (0x00000005U)
+#define EDMA3_CCRL_EMRH_E37_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E36_MASK         (0x00000010u)
-#define EDMA3_CCRL_EMRH_E36_SHIFT        (0x00000004u)
-#define EDMA3_CCRL_EMRH_E36_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E36_MASK         (0x00000010U)
+#define EDMA3_CCRL_EMRH_E36_SHIFT        (0x00000004U)
+#define EDMA3_CCRL_EMRH_E36_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E35_MASK         (0x00000008u)
-#define EDMA3_CCRL_EMRH_E35_SHIFT        (0x00000003u)
-#define EDMA3_CCRL_EMRH_E35_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E35_MASK         (0x00000008U)
+#define EDMA3_CCRL_EMRH_E35_SHIFT        (0x00000003U)
+#define EDMA3_CCRL_EMRH_E35_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E34_MASK         (0x00000004u)
-#define EDMA3_CCRL_EMRH_E34_SHIFT        (0x00000002u)
-#define EDMA3_CCRL_EMRH_E34_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E34_MASK         (0x00000004U)
+#define EDMA3_CCRL_EMRH_E34_SHIFT        (0x00000002U)
+#define EDMA3_CCRL_EMRH_E34_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E33_MASK         (0x00000002u)
-#define EDMA3_CCRL_EMRH_E33_SHIFT        (0x00000001u)
-#define EDMA3_CCRL_EMRH_E33_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E33_MASK         (0x00000002U)
+#define EDMA3_CCRL_EMRH_E33_SHIFT        (0x00000001U)
+#define EDMA3_CCRL_EMRH_E33_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_E32_MASK         (0x00000001u)
-#define EDMA3_CCRL_EMRH_E32_SHIFT        (0x00000000u)
-#define EDMA3_CCRL_EMRH_E32_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMRH_E32_MASK         (0x00000001U)
+#define EDMA3_CCRL_EMRH_E32_SHIFT        (0x00000000U)
+#define EDMA3_CCRL_EMRH_E32_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMRH_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_EMRH_RESETVAL         (0x00000000U)
 
 /* EMCR */
 
-#define EDMA3_CCRL_EMCR_E31_MASK         (0x80000000u)
-#define EDMA3_CCRL_EMCR_E31_SHIFT        (0x0000001Fu)
-#define EDMA3_CCRL_EMCR_E31_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E31_MASK         (0x80000000U)
+#define EDMA3_CCRL_EMCR_E31_SHIFT        (0x0000001FU)
+#define EDMA3_CCRL_EMCR_E31_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E30_MASK         (0x40000000u)
-#define EDMA3_CCRL_EMCR_E30_SHIFT        (0x0000001Eu)
-#define EDMA3_CCRL_EMCR_E30_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E30_MASK         (0x40000000U)
+#define EDMA3_CCRL_EMCR_E30_SHIFT        (0x0000001EU)
+#define EDMA3_CCRL_EMCR_E30_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E29_MASK         (0x20000000u)
-#define EDMA3_CCRL_EMCR_E29_SHIFT        (0x0000001Du)
-#define EDMA3_CCRL_EMCR_E29_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E29_MASK         (0x20000000U)
+#define EDMA3_CCRL_EMCR_E29_SHIFT        (0x0000001DU)
+#define EDMA3_CCRL_EMCR_E29_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E28_MASK         (0x10000000u)
-#define EDMA3_CCRL_EMCR_E28_SHIFT        (0x0000001Cu)
-#define EDMA3_CCRL_EMCR_E28_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E28_MASK         (0x10000000U)
+#define EDMA3_CCRL_EMCR_E28_SHIFT        (0x0000001CU)
+#define EDMA3_CCRL_EMCR_E28_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E27_MASK         (0x08000000u)
-#define EDMA3_CCRL_EMCR_E27_SHIFT        (0x0000001Bu)
-#define EDMA3_CCRL_EMCR_E27_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E27_MASK         (0x08000000U)
+#define EDMA3_CCRL_EMCR_E27_SHIFT        (0x0000001BU)
+#define EDMA3_CCRL_EMCR_E27_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E26_MASK         (0x04000000u)
-#define EDMA3_CCRL_EMCR_E26_SHIFT        (0x0000001Au)
-#define EDMA3_CCRL_EMCR_E26_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E26_MASK         (0x04000000U)
+#define EDMA3_CCRL_EMCR_E26_SHIFT        (0x0000001AU)
+#define EDMA3_CCRL_EMCR_E26_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E25_MASK         (0x02000000u)
-#define EDMA3_CCRL_EMCR_E25_SHIFT        (0x00000019u)
-#define EDMA3_CCRL_EMCR_E25_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E25_MASK         (0x02000000U)
+#define EDMA3_CCRL_EMCR_E25_SHIFT        (0x00000019U)
+#define EDMA3_CCRL_EMCR_E25_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E24_MASK         (0x01000000u)
-#define EDMA3_CCRL_EMCR_E24_SHIFT        (0x00000018u)
-#define EDMA3_CCRL_EMCR_E24_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E24_MASK         (0x01000000U)
+#define EDMA3_CCRL_EMCR_E24_SHIFT        (0x00000018U)
+#define EDMA3_CCRL_EMCR_E24_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E23_MASK         (0x00800000u)
-#define EDMA3_CCRL_EMCR_E23_SHIFT        (0x00000017u)
-#define EDMA3_CCRL_EMCR_E23_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E23_MASK         (0x00800000U)
+#define EDMA3_CCRL_EMCR_E23_SHIFT        (0x00000017U)
+#define EDMA3_CCRL_EMCR_E23_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E22_MASK         (0x00400000u)
-#define EDMA3_CCRL_EMCR_E22_SHIFT        (0x00000016u)
-#define EDMA3_CCRL_EMCR_E22_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E22_MASK         (0x00400000U)
+#define EDMA3_CCRL_EMCR_E22_SHIFT        (0x00000016U)
+#define EDMA3_CCRL_EMCR_E22_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E21_MASK         (0x00200000u)
-#define EDMA3_CCRL_EMCR_E21_SHIFT        (0x00000015u)
-#define EDMA3_CCRL_EMCR_E21_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E21_MASK         (0x00200000U)
+#define EDMA3_CCRL_EMCR_E21_SHIFT        (0x00000015U)
+#define EDMA3_CCRL_EMCR_E21_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E20_MASK         (0x00100000u)
-#define EDMA3_CCRL_EMCR_E20_SHIFT        (0x00000014u)
-#define EDMA3_CCRL_EMCR_E20_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E20_MASK         (0x00100000U)
+#define EDMA3_CCRL_EMCR_E20_SHIFT        (0x00000014U)
+#define EDMA3_CCRL_EMCR_E20_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E19_MASK         (0x00080000u)
-#define EDMA3_CCRL_EMCR_E19_SHIFT        (0x00000013u)
-#define EDMA3_CCRL_EMCR_E19_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E19_MASK         (0x00080000U)
+#define EDMA3_CCRL_EMCR_E19_SHIFT        (0x00000013U)
+#define EDMA3_CCRL_EMCR_E19_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E18_MASK         (0x00040000u)
-#define EDMA3_CCRL_EMCR_E18_SHIFT        (0x00000012u)
-#define EDMA3_CCRL_EMCR_E18_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E18_MASK         (0x00040000U)
+#define EDMA3_CCRL_EMCR_E18_SHIFT        (0x00000012U)
+#define EDMA3_CCRL_EMCR_E18_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E17_MASK         (0x00020000u)
-#define EDMA3_CCRL_EMCR_E17_SHIFT        (0x00000011u)
-#define EDMA3_CCRL_EMCR_E17_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E17_MASK         (0x00020000U)
+#define EDMA3_CCRL_EMCR_E17_SHIFT        (0x00000011U)
+#define EDMA3_CCRL_EMCR_E17_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E16_MASK         (0x00010000u)
-#define EDMA3_CCRL_EMCR_E16_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_EMCR_E16_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E16_MASK         (0x00010000U)
+#define EDMA3_CCRL_EMCR_E16_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_EMCR_E16_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E15_MASK         (0x00008000u)
-#define EDMA3_CCRL_EMCR_E15_SHIFT        (0x0000000Fu)
-#define EDMA3_CCRL_EMCR_E15_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E15_MASK         (0x00008000U)
+#define EDMA3_CCRL_EMCR_E15_SHIFT        (0x0000000FU)
+#define EDMA3_CCRL_EMCR_E15_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E14_MASK         (0x00004000u)
-#define EDMA3_CCRL_EMCR_E14_SHIFT        (0x0000000Eu)
-#define EDMA3_CCRL_EMCR_E14_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E14_MASK         (0x00004000U)
+#define EDMA3_CCRL_EMCR_E14_SHIFT        (0x0000000EU)
+#define EDMA3_CCRL_EMCR_E14_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E13_MASK         (0x00002000u)
-#define EDMA3_CCRL_EMCR_E13_SHIFT        (0x0000000Du)
-#define EDMA3_CCRL_EMCR_E13_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E13_MASK         (0x00002000U)
+#define EDMA3_CCRL_EMCR_E13_SHIFT        (0x0000000DU)
+#define EDMA3_CCRL_EMCR_E13_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E12_MASK         (0x00001000u)
-#define EDMA3_CCRL_EMCR_E12_SHIFT        (0x0000000Cu)
-#define EDMA3_CCRL_EMCR_E12_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E12_MASK         (0x00001000U)
+#define EDMA3_CCRL_EMCR_E12_SHIFT        (0x0000000CU)
+#define EDMA3_CCRL_EMCR_E12_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E11_MASK         (0x00000800u)
-#define EDMA3_CCRL_EMCR_E11_SHIFT        (0x0000000Bu)
-#define EDMA3_CCRL_EMCR_E11_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E11_MASK         (0x00000800U)
+#define EDMA3_CCRL_EMCR_E11_SHIFT        (0x0000000BU)
+#define EDMA3_CCRL_EMCR_E11_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E10_MASK         (0x00000400u)
-#define EDMA3_CCRL_EMCR_E10_SHIFT        (0x0000000Au)
-#define EDMA3_CCRL_EMCR_E10_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EMCR_E10_MASK         (0x00000400U)
+#define EDMA3_CCRL_EMCR_E10_SHIFT        (0x0000000AU)
+#define EDMA3_CCRL_EMCR_E10_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E9_MASK          (0x00000200u)
-#define EDMA3_CCRL_EMCR_E9_SHIFT         (0x00000009u)
-#define EDMA3_CCRL_EMCR_E9_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMCR_E9_MASK          (0x00000200U)
+#define EDMA3_CCRL_EMCR_E9_SHIFT         (0x00000009U)
+#define EDMA3_CCRL_EMCR_E9_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E8_MASK          (0x00000100u)
-#define EDMA3_CCRL_EMCR_E8_SHIFT         (0x00000008u)
-#define EDMA3_CCRL_EMCR_E8_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMCR_E8_MASK          (0x00000100U)
+#define EDMA3_CCRL_EMCR_E8_SHIFT         (0x00000008U)
+#define EDMA3_CCRL_EMCR_E8_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E7_MASK          (0x00000080u)
-#define EDMA3_CCRL_EMCR_E7_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_EMCR_E7_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMCR_E7_MASK          (0x00000080U)
+#define EDMA3_CCRL_EMCR_E7_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_EMCR_E7_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E6_MASK          (0x00000040u)
-#define EDMA3_CCRL_EMCR_E6_SHIFT         (0x00000006u)
-#define EDMA3_CCRL_EMCR_E6_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMCR_E6_MASK          (0x00000040U)
+#define EDMA3_CCRL_EMCR_E6_SHIFT         (0x00000006U)
+#define EDMA3_CCRL_EMCR_E6_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E5_MASK          (0x00000020u)
-#define EDMA3_CCRL_EMCR_E5_SHIFT         (0x00000005u)
-#define EDMA3_CCRL_EMCR_E5_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMCR_E5_MASK          (0x00000020U)
+#define EDMA3_CCRL_EMCR_E5_SHIFT         (0x00000005U)
+#define EDMA3_CCRL_EMCR_E5_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E4_MASK          (0x00000010u)
-#define EDMA3_CCRL_EMCR_E4_SHIFT         (0x00000004u)
-#define EDMA3_CCRL_EMCR_E4_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMCR_E4_MASK          (0x00000010U)
+#define EDMA3_CCRL_EMCR_E4_SHIFT         (0x00000004U)
+#define EDMA3_CCRL_EMCR_E4_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E3_MASK          (0x00000008u)
-#define EDMA3_CCRL_EMCR_E3_SHIFT         (0x00000003u)
-#define EDMA3_CCRL_EMCR_E3_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMCR_E3_MASK          (0x00000008U)
+#define EDMA3_CCRL_EMCR_E3_SHIFT         (0x00000003U)
+#define EDMA3_CCRL_EMCR_E3_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E2_MASK          (0x00000004u)
-#define EDMA3_CCRL_EMCR_E2_SHIFT         (0x00000002u)
-#define EDMA3_CCRL_EMCR_E2_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMCR_E2_MASK          (0x00000004U)
+#define EDMA3_CCRL_EMCR_E2_SHIFT         (0x00000002U)
+#define EDMA3_CCRL_EMCR_E2_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E1_MASK          (0x00000002u)
-#define EDMA3_CCRL_EMCR_E1_SHIFT         (0x00000001u)
-#define EDMA3_CCRL_EMCR_E1_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMCR_E1_MASK          (0x00000002U)
+#define EDMA3_CCRL_EMCR_E1_SHIFT         (0x00000001U)
+#define EDMA3_CCRL_EMCR_E1_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_E0_MASK          (0x00000001u)
-#define EDMA3_CCRL_EMCR_E0_SHIFT         (0x00000000u)
-#define EDMA3_CCRL_EMCR_E0_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EMCR_E0_MASK          (0x00000001U)
+#define EDMA3_CCRL_EMCR_E0_SHIFT         (0x00000000U)
+#define EDMA3_CCRL_EMCR_E0_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EMCR_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_EMCR_RESETVAL         (0x00000000U)
 
 /* EMCRH */
 
-#define EDMA3_CCRL_EMCRH_E63_MASK        (0x80000000u)
-#define EDMA3_CCRL_EMCRH_E63_SHIFT       (0x0000001Fu)
-#define EDMA3_CCRL_EMCRH_E63_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E63_MASK        (0x80000000U)
+#define EDMA3_CCRL_EMCRH_E63_SHIFT       (0x0000001FU)
+#define EDMA3_CCRL_EMCRH_E63_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E62_MASK        (0x40000000u)
-#define EDMA3_CCRL_EMCRH_E62_SHIFT       (0x0000001Eu)
-#define EDMA3_CCRL_EMCRH_E62_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E62_MASK        (0x40000000U)
+#define EDMA3_CCRL_EMCRH_E62_SHIFT       (0x0000001EU)
+#define EDMA3_CCRL_EMCRH_E62_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E61_MASK        (0x20000000u)
-#define EDMA3_CCRL_EMCRH_E61_SHIFT       (0x0000001Du)
-#define EDMA3_CCRL_EMCRH_E61_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E61_MASK        (0x20000000U)
+#define EDMA3_CCRL_EMCRH_E61_SHIFT       (0x0000001DU)
+#define EDMA3_CCRL_EMCRH_E61_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E60_MASK        (0x10000000u)
-#define EDMA3_CCRL_EMCRH_E60_SHIFT       (0x0000001Cu)
-#define EDMA3_CCRL_EMCRH_E60_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E60_MASK        (0x10000000U)
+#define EDMA3_CCRL_EMCRH_E60_SHIFT       (0x0000001CU)
+#define EDMA3_CCRL_EMCRH_E60_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E59_MASK        (0x08000000u)
-#define EDMA3_CCRL_EMCRH_E59_SHIFT       (0x0000001Bu)
-#define EDMA3_CCRL_EMCRH_E59_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E59_MASK        (0x08000000U)
+#define EDMA3_CCRL_EMCRH_E59_SHIFT       (0x0000001BU)
+#define EDMA3_CCRL_EMCRH_E59_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E58_MASK        (0x04000000u)
-#define EDMA3_CCRL_EMCRH_E58_SHIFT       (0x0000001Au)
-#define EDMA3_CCRL_EMCRH_E58_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E58_MASK        (0x04000000U)
+#define EDMA3_CCRL_EMCRH_E58_SHIFT       (0x0000001AU)
+#define EDMA3_CCRL_EMCRH_E58_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E57_MASK        (0x02000000u)
-#define EDMA3_CCRL_EMCRH_E57_SHIFT       (0x00000019u)
-#define EDMA3_CCRL_EMCRH_E57_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E57_MASK        (0x02000000U)
+#define EDMA3_CCRL_EMCRH_E57_SHIFT       (0x00000019U)
+#define EDMA3_CCRL_EMCRH_E57_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E56_MASK        (0x01000000u)
-#define EDMA3_CCRL_EMCRH_E56_SHIFT       (0x00000018u)
-#define EDMA3_CCRL_EMCRH_E56_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E56_MASK        (0x01000000U)
+#define EDMA3_CCRL_EMCRH_E56_SHIFT       (0x00000018U)
+#define EDMA3_CCRL_EMCRH_E56_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E55_MASK        (0x00800000u)
-#define EDMA3_CCRL_EMCRH_E55_SHIFT       (0x00000017u)
-#define EDMA3_CCRL_EMCRH_E55_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E55_MASK        (0x00800000U)
+#define EDMA3_CCRL_EMCRH_E55_SHIFT       (0x00000017U)
+#define EDMA3_CCRL_EMCRH_E55_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E54_MASK        (0x00400000u)
-#define EDMA3_CCRL_EMCRH_E54_SHIFT       (0x00000016u)
-#define EDMA3_CCRL_EMCRH_E54_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E54_MASK        (0x00400000U)
+#define EDMA3_CCRL_EMCRH_E54_SHIFT       (0x00000016U)
+#define EDMA3_CCRL_EMCRH_E54_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E53_MASK        (0x00200000u)
-#define EDMA3_CCRL_EMCRH_E53_SHIFT       (0x00000015u)
-#define EDMA3_CCRL_EMCRH_E53_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E53_MASK        (0x00200000U)
+#define EDMA3_CCRL_EMCRH_E53_SHIFT       (0x00000015U)
+#define EDMA3_CCRL_EMCRH_E53_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E52_MASK        (0x00100000u)
-#define EDMA3_CCRL_EMCRH_E52_SHIFT       (0x00000014u)
-#define EDMA3_CCRL_EMCRH_E52_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E52_MASK        (0x00100000U)
+#define EDMA3_CCRL_EMCRH_E52_SHIFT       (0x00000014U)
+#define EDMA3_CCRL_EMCRH_E52_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E51_MASK        (0x00080000u)
-#define EDMA3_CCRL_EMCRH_E51_SHIFT       (0x00000013u)
-#define EDMA3_CCRL_EMCRH_E51_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E51_MASK        (0x00080000U)
+#define EDMA3_CCRL_EMCRH_E51_SHIFT       (0x00000013U)
+#define EDMA3_CCRL_EMCRH_E51_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E50_MASK        (0x00040000u)
-#define EDMA3_CCRL_EMCRH_E50_SHIFT       (0x00000012u)
-#define EDMA3_CCRL_EMCRH_E50_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E50_MASK        (0x00040000U)
+#define EDMA3_CCRL_EMCRH_E50_SHIFT       (0x00000012U)
+#define EDMA3_CCRL_EMCRH_E50_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E49_MASK        (0x00020000u)
-#define EDMA3_CCRL_EMCRH_E49_SHIFT       (0x00000011u)
-#define EDMA3_CCRL_EMCRH_E49_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E49_MASK        (0x00020000U)
+#define EDMA3_CCRL_EMCRH_E49_SHIFT       (0x00000011U)
+#define EDMA3_CCRL_EMCRH_E49_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E48_MASK        (0x00010000u)
-#define EDMA3_CCRL_EMCRH_E48_SHIFT       (0x00000010u)
-#define EDMA3_CCRL_EMCRH_E48_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E48_MASK        (0x00010000U)
+#define EDMA3_CCRL_EMCRH_E48_SHIFT       (0x00000010U)
+#define EDMA3_CCRL_EMCRH_E48_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E47_MASK        (0x00008000u)
-#define EDMA3_CCRL_EMCRH_E47_SHIFT       (0x0000000Fu)
-#define EDMA3_CCRL_EMCRH_E47_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E47_MASK        (0x00008000U)
+#define EDMA3_CCRL_EMCRH_E47_SHIFT       (0x0000000FU)
+#define EDMA3_CCRL_EMCRH_E47_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E46_MASK        (0x00004000u)
-#define EDMA3_CCRL_EMCRH_E46_SHIFT       (0x0000000Eu)
-#define EDMA3_CCRL_EMCRH_E46_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E46_MASK        (0x00004000U)
+#define EDMA3_CCRL_EMCRH_E46_SHIFT       (0x0000000EU)
+#define EDMA3_CCRL_EMCRH_E46_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E45_MASK        (0x00002000u)
-#define EDMA3_CCRL_EMCRH_E45_SHIFT       (0x0000000Du)
-#define EDMA3_CCRL_EMCRH_E45_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E45_MASK        (0x00002000U)
+#define EDMA3_CCRL_EMCRH_E45_SHIFT       (0x0000000DU)
+#define EDMA3_CCRL_EMCRH_E45_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E44_MASK        (0x00001000u)
-#define EDMA3_CCRL_EMCRH_E44_SHIFT       (0x0000000Cu)
-#define EDMA3_CCRL_EMCRH_E44_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E44_MASK        (0x00001000U)
+#define EDMA3_CCRL_EMCRH_E44_SHIFT       (0x0000000CU)
+#define EDMA3_CCRL_EMCRH_E44_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E43_MASK        (0x00000800u)
-#define EDMA3_CCRL_EMCRH_E43_SHIFT       (0x0000000Bu)
-#define EDMA3_CCRL_EMCRH_E43_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E43_MASK        (0x00000800U)
+#define EDMA3_CCRL_EMCRH_E43_SHIFT       (0x0000000BU)
+#define EDMA3_CCRL_EMCRH_E43_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E42_MASK        (0x00000400u)
-#define EDMA3_CCRL_EMCRH_E42_SHIFT       (0x0000000Au)
-#define EDMA3_CCRL_EMCRH_E42_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E42_MASK        (0x00000400U)
+#define EDMA3_CCRL_EMCRH_E42_SHIFT       (0x0000000AU)
+#define EDMA3_CCRL_EMCRH_E42_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E41_MASK        (0x00000200u)
-#define EDMA3_CCRL_EMCRH_E41_SHIFT       (0x00000009u)
-#define EDMA3_CCRL_EMCRH_E41_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E41_MASK        (0x00000200U)
+#define EDMA3_CCRL_EMCRH_E41_SHIFT       (0x00000009U)
+#define EDMA3_CCRL_EMCRH_E41_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E40_MASK        (0x00000100u)
-#define EDMA3_CCRL_EMCRH_E40_SHIFT       (0x00000008u)
-#define EDMA3_CCRL_EMCRH_E40_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E40_MASK        (0x00000100U)
+#define EDMA3_CCRL_EMCRH_E40_SHIFT       (0x00000008U)
+#define EDMA3_CCRL_EMCRH_E40_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E39_MASK        (0x00000080u)
-#define EDMA3_CCRL_EMCRH_E39_SHIFT       (0x00000007u)
-#define EDMA3_CCRL_EMCRH_E39_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E39_MASK        (0x00000080U)
+#define EDMA3_CCRL_EMCRH_E39_SHIFT       (0x00000007U)
+#define EDMA3_CCRL_EMCRH_E39_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E38_MASK        (0x00000040u)
-#define EDMA3_CCRL_EMCRH_E38_SHIFT       (0x00000006u)
-#define EDMA3_CCRL_EMCRH_E38_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E38_MASK        (0x00000040U)
+#define EDMA3_CCRL_EMCRH_E38_SHIFT       (0x00000006U)
+#define EDMA3_CCRL_EMCRH_E38_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E37_MASK        (0x00000020u)
-#define EDMA3_CCRL_EMCRH_E37_SHIFT       (0x00000005u)
-#define EDMA3_CCRL_EMCRH_E37_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E37_MASK        (0x00000020U)
+#define EDMA3_CCRL_EMCRH_E37_SHIFT       (0x00000005U)
+#define EDMA3_CCRL_EMCRH_E37_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E36_MASK        (0x00000010u)
-#define EDMA3_CCRL_EMCRH_E36_SHIFT       (0x00000004u)
-#define EDMA3_CCRL_EMCRH_E36_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E36_MASK        (0x00000010U)
+#define EDMA3_CCRL_EMCRH_E36_SHIFT       (0x00000004U)
+#define EDMA3_CCRL_EMCRH_E36_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E35_MASK        (0x00000008u)
-#define EDMA3_CCRL_EMCRH_E35_SHIFT       (0x00000003u)
-#define EDMA3_CCRL_EMCRH_E35_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E35_MASK        (0x00000008U)
+#define EDMA3_CCRL_EMCRH_E35_SHIFT       (0x00000003U)
+#define EDMA3_CCRL_EMCRH_E35_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E34_MASK        (0x00000004u)
-#define EDMA3_CCRL_EMCRH_E34_SHIFT       (0x00000002u)
-#define EDMA3_CCRL_EMCRH_E34_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E34_MASK        (0x00000004U)
+#define EDMA3_CCRL_EMCRH_E34_SHIFT       (0x00000002U)
+#define EDMA3_CCRL_EMCRH_E34_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E33_MASK        (0x00000002u)
-#define EDMA3_CCRL_EMCRH_E33_SHIFT       (0x00000001u)
-#define EDMA3_CCRL_EMCRH_E33_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E33_MASK        (0x00000002U)
+#define EDMA3_CCRL_EMCRH_E33_SHIFT       (0x00000001U)
+#define EDMA3_CCRL_EMCRH_E33_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_E32_MASK        (0x00000001u)
-#define EDMA3_CCRL_EMCRH_E32_SHIFT       (0x00000000u)
-#define EDMA3_CCRL_EMCRH_E32_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EMCRH_E32_MASK        (0x00000001U)
+#define EDMA3_CCRL_EMCRH_E32_SHIFT       (0x00000000U)
+#define EDMA3_CCRL_EMCRH_E32_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_EMCRH_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_EMCRH_RESETVAL        (0x00000000U)
 
 /* QEMR */
 
-#define EDMA3_CCRL_QEMR_E7_MASK          (0x00000080u)
-#define EDMA3_CCRL_QEMR_E7_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_QEMR_E7_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QEMR_E7_MASK          (0x00000080U)
+#define EDMA3_CCRL_QEMR_E7_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_QEMR_E7_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QEMR_E6_MASK          (0x00000040u)
-#define EDMA3_CCRL_QEMR_E6_SHIFT         (0x00000006u)
-#define EDMA3_CCRL_QEMR_E6_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QEMR_E6_MASK          (0x00000040U)
+#define EDMA3_CCRL_QEMR_E6_SHIFT         (0x00000006U)
+#define EDMA3_CCRL_QEMR_E6_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QEMR_E5_MASK          (0x00000020u)
-#define EDMA3_CCRL_QEMR_E5_SHIFT         (0x00000005u)
-#define EDMA3_CCRL_QEMR_E5_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QEMR_E5_MASK          (0x00000020U)
+#define EDMA3_CCRL_QEMR_E5_SHIFT         (0x00000005U)
+#define EDMA3_CCRL_QEMR_E5_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QEMR_E4_MASK          (0x00000010u)
-#define EDMA3_CCRL_QEMR_E4_SHIFT         (0x00000004u)
-#define EDMA3_CCRL_QEMR_E4_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QEMR_E4_MASK          (0x00000010U)
+#define EDMA3_CCRL_QEMR_E4_SHIFT         (0x00000004U)
+#define EDMA3_CCRL_QEMR_E4_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QEMR_E3_MASK          (0x00000008u)
-#define EDMA3_CCRL_QEMR_E3_SHIFT         (0x00000003u)
-#define EDMA3_CCRL_QEMR_E3_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QEMR_E3_MASK          (0x00000008U)
+#define EDMA3_CCRL_QEMR_E3_SHIFT         (0x00000003U)
+#define EDMA3_CCRL_QEMR_E3_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QEMR_E2_MASK          (0x00000004u)
-#define EDMA3_CCRL_QEMR_E2_SHIFT         (0x00000002u)
-#define EDMA3_CCRL_QEMR_E2_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QEMR_E2_MASK          (0x00000004U)
+#define EDMA3_CCRL_QEMR_E2_SHIFT         (0x00000002U)
+#define EDMA3_CCRL_QEMR_E2_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QEMR_E1_MASK          (0x00000002u)
-#define EDMA3_CCRL_QEMR_E1_SHIFT         (0x00000001u)
-#define EDMA3_CCRL_QEMR_E1_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QEMR_E1_MASK          (0x00000002U)
+#define EDMA3_CCRL_QEMR_E1_SHIFT         (0x00000001U)
+#define EDMA3_CCRL_QEMR_E1_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QEMR_E0_MASK          (0x00000001u)
-#define EDMA3_CCRL_QEMR_E0_SHIFT         (0x00000000u)
-#define EDMA3_CCRL_QEMR_E0_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QEMR_E0_MASK          (0x00000001U)
+#define EDMA3_CCRL_QEMR_E0_SHIFT         (0x00000000U)
+#define EDMA3_CCRL_QEMR_E0_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QEMR_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_QEMR_RESETVAL         (0x00000000U)
 
 /* QEMCR */
 
-#define EDMA3_CCRL_QEMCR_E7_MASK         (0x00000080u)
-#define EDMA3_CCRL_QEMCR_E7_SHIFT        (0x00000007u)
-#define EDMA3_CCRL_QEMCR_E7_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E7_MASK         (0x00000080U)
+#define EDMA3_CCRL_QEMCR_E7_SHIFT        (0x00000007U)
+#define EDMA3_CCRL_QEMCR_E7_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_QEMCR_E6_MASK         (0x00000040u)
-#define EDMA3_CCRL_QEMCR_E6_SHIFT        (0x00000006u)
-#define EDMA3_CCRL_QEMCR_E6_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E6_MASK         (0x00000040U)
+#define EDMA3_CCRL_QEMCR_E6_SHIFT        (0x00000006U)
+#define EDMA3_CCRL_QEMCR_E6_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_QEMCR_E5_MASK         (0x00000020u)
-#define EDMA3_CCRL_QEMCR_E5_SHIFT        (0x00000005u)
-#define EDMA3_CCRL_QEMCR_E5_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E5_MASK         (0x00000020U)
+#define EDMA3_CCRL_QEMCR_E5_SHIFT        (0x00000005U)
+#define EDMA3_CCRL_QEMCR_E5_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_QEMCR_E4_MASK         (0x00000010u)
-#define EDMA3_CCRL_QEMCR_E4_SHIFT        (0x00000004u)
-#define EDMA3_CCRL_QEMCR_E4_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E4_MASK         (0x00000010U)
+#define EDMA3_CCRL_QEMCR_E4_SHIFT        (0x00000004U)
+#define EDMA3_CCRL_QEMCR_E4_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_QEMCR_E3_MASK         (0x00000008u)
-#define EDMA3_CCRL_QEMCR_E3_SHIFT        (0x00000003u)
-#define EDMA3_CCRL_QEMCR_E3_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E3_MASK         (0x00000008U)
+#define EDMA3_CCRL_QEMCR_E3_SHIFT        (0x00000003U)
+#define EDMA3_CCRL_QEMCR_E3_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_QEMCR_E2_MASK         (0x00000004u)
-#define EDMA3_CCRL_QEMCR_E2_SHIFT        (0x00000002u)
-#define EDMA3_CCRL_QEMCR_E2_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E2_MASK         (0x00000004U)
+#define EDMA3_CCRL_QEMCR_E2_SHIFT        (0x00000002U)
+#define EDMA3_CCRL_QEMCR_E2_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_QEMCR_E1_MASK         (0x00000002u)
-#define EDMA3_CCRL_QEMCR_E1_SHIFT        (0x00000001u)
-#define EDMA3_CCRL_QEMCR_E1_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E1_MASK         (0x00000002U)
+#define EDMA3_CCRL_QEMCR_E1_SHIFT        (0x00000001U)
+#define EDMA3_CCRL_QEMCR_E1_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_QEMCR_E0_MASK         (0x00000001u)
-#define EDMA3_CCRL_QEMCR_E0_SHIFT        (0x00000000u)
-#define EDMA3_CCRL_QEMCR_E0_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QEMCR_E0_MASK         (0x00000001U)
+#define EDMA3_CCRL_QEMCR_E0_SHIFT        (0x00000000U)
+#define EDMA3_CCRL_QEMCR_E0_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_QEMCR_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_QEMCR_RESETVAL        (0x00000000U)
 
 /* CCERR */
 
-#define EDMA3_CCRL_CCERR_TCCERR_MASK     (0x00010000u)
-#define EDMA3_CCRL_CCERR_TCCERR_SHIFT    (0x00000010u)
-#define EDMA3_CCRL_CCERR_TCCERR_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERR_TCCERR_MASK     (0x00010000U)
+#define EDMA3_CCRL_CCERR_TCCERR_SHIFT    (0x00000010U)
+#define EDMA3_CCRL_CCERR_TCCERR_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERR_QTHRXCD7_MASK   (0x00000080u)
-#define EDMA3_CCRL_CCERR_QTHRXCD7_SHIFT  (0x00000007u)
-#define EDMA3_CCRL_CCERR_QTHRXCD7_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD7_MASK   (0x00000080U)
+#define EDMA3_CCRL_CCERR_QTHRXCD7_SHIFT  (0x00000007U)
+#define EDMA3_CCRL_CCERR_QTHRXCD7_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERR_QTHRXCD6_MASK   (0x00000040u)
-#define EDMA3_CCRL_CCERR_QTHRXCD6_SHIFT  (0x00000006u)
-#define EDMA3_CCRL_CCERR_QTHRXCD6_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD6_MASK   (0x00000040U)
+#define EDMA3_CCRL_CCERR_QTHRXCD6_SHIFT  (0x00000006U)
+#define EDMA3_CCRL_CCERR_QTHRXCD6_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERR_QTHRXCD5_MASK   (0x00000020u)
-#define EDMA3_CCRL_CCERR_QTHRXCD5_SHIFT  (0x00000005u)
-#define EDMA3_CCRL_CCERR_QTHRXCD5_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD5_MASK   (0x00000020U)
+#define EDMA3_CCRL_CCERR_QTHRXCD5_SHIFT  (0x00000005U)
+#define EDMA3_CCRL_CCERR_QTHRXCD5_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERR_QTHRXCD4_MASK   (0x00000010u)
-#define EDMA3_CCRL_CCERR_QTHRXCD4_SHIFT  (0x00000004u)
-#define EDMA3_CCRL_CCERR_QTHRXCD4_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD4_MASK   (0x00000010U)
+#define EDMA3_CCRL_CCERR_QTHRXCD4_SHIFT  (0x00000004U)
+#define EDMA3_CCRL_CCERR_QTHRXCD4_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERR_QTHRXCD3_MASK   (0x00000008u)
-#define EDMA3_CCRL_CCERR_QTHRXCD3_SHIFT  (0x00000003u)
-#define EDMA3_CCRL_CCERR_QTHRXCD3_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD3_MASK   (0x00000008U)
+#define EDMA3_CCRL_CCERR_QTHRXCD3_SHIFT  (0x00000003U)
+#define EDMA3_CCRL_CCERR_QTHRXCD3_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERR_QTHRXCD2_MASK   (0x00000004u)
-#define EDMA3_CCRL_CCERR_QTHRXCD2_SHIFT  (0x00000002u)
-#define EDMA3_CCRL_CCERR_QTHRXCD2_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD2_MASK   (0x00000004U)
+#define EDMA3_CCRL_CCERR_QTHRXCD2_SHIFT  (0x00000002U)
+#define EDMA3_CCRL_CCERR_QTHRXCD2_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERR_QTHRXCD1_MASK   (0x00000002u)
-#define EDMA3_CCRL_CCERR_QTHRXCD1_SHIFT  (0x00000001u)
-#define EDMA3_CCRL_CCERR_QTHRXCD1_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD1_MASK   (0x00000002U)
+#define EDMA3_CCRL_CCERR_QTHRXCD1_SHIFT  (0x00000001U)
+#define EDMA3_CCRL_CCERR_QTHRXCD1_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERR_QTHRXCD0_MASK   (0x00000001u)
-#define EDMA3_CCRL_CCERR_QTHRXCD0_SHIFT  (0x00000000u)
-#define EDMA3_CCRL_CCERR_QTHRXCD0_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERR_QTHRXCD0_MASK   (0x00000001U)
+#define EDMA3_CCRL_CCERR_QTHRXCD0_SHIFT  (0x00000000U)
+#define EDMA3_CCRL_CCERR_QTHRXCD0_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERR_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_CCERR_RESETVAL        (0x00000000U)
 
 /* CCERRCLR */
 
-#define EDMA3_CCRL_CCERRCLR_TCCERR_MASK  (0x00010000u)
-#define EDMA3_CCRL_CCERRCLR_TCCERR_SHIFT (0x00000010u)
-#define EDMA3_CCRL_CCERRCLR_TCCERR_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_TCCERR_MASK  (0x00010000U)
+#define EDMA3_CCRL_CCERRCLR_TCCERR_SHIFT (0x00000010U)
+#define EDMA3_CCRL_CCERRCLR_TCCERR_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_MASK (0x00000080u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_SHIFT (0x00000007u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_MASK (0x00000080U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_SHIFT (0x00000007U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD7_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_MASK (0x00000040u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_SHIFT (0x00000006u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_MASK (0x00000040U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_SHIFT (0x00000006U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD6_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_MASK (0x00000020u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_SHIFT (0x00000005u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_MASK (0x00000020U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_SHIFT (0x00000005U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD5_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_MASK (0x00000010u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_SHIFT (0x00000004u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_MASK (0x00000010U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_SHIFT (0x00000004U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD4_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_MASK (0x00000008u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_SHIFT (0x00000003u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_MASK (0x00000008U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_SHIFT (0x00000003U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD3_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_MASK (0x00000004u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_SHIFT (0x00000002u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_MASK (0x00000004U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_SHIFT (0x00000002U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD2_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_MASK (0x00000002u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_SHIFT (0x00000001u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_MASK (0x00000002U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_SHIFT (0x00000001U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD1_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_MASK (0x00000001u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_SHIFT (0x00000000u)
-#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_MASK (0x00000001U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_SHIFT (0x00000000U)
+#define EDMA3_CCRL_CCERRCLR_QTHRXCD0_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_CCERRCLR_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CCERRCLR_RESETVAL     (0x00000000U)
 
 /* EEVAL */
 
-#define EDMA3_CCRL_EEVAL_SET_MASK        (0x00000002u)
-#define EDMA3_CCRL_EEVAL_SET_SHIFT       (0x00000001u)
-#define EDMA3_CCRL_EEVAL_SET_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EEVAL_SET_MASK        (0x00000002U)
+#define EDMA3_CCRL_EEVAL_SET_SHIFT       (0x00000001U)
+#define EDMA3_CCRL_EEVAL_SET_RESETVAL    (0x00000000U)
 
 /*----SET Tokens----*/
-#define EDMA3_CCRL_EEVAL_SET_SET         (0x00000001u)
+#define EDMA3_CCRL_EEVAL_SET_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EEVAL_EVAL_MASK       (0x00000001u)
-#define EDMA3_CCRL_EEVAL_EVAL_SHIFT      (0x00000000u)
-#define EDMA3_CCRL_EEVAL_EVAL_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_EEVAL_EVAL_MASK       (0x00000001U)
+#define EDMA3_CCRL_EEVAL_EVAL_SHIFT      (0x00000000U)
+#define EDMA3_CCRL_EEVAL_EVAL_RESETVAL   (0x00000000U)
 
 /*----EVAL Tokens----*/
-#define EDMA3_CCRL_EEVAL_EVAL_EVAL       (0x00000001u)
+#define EDMA3_CCRL_EEVAL_EVAL_EVAL       (0x00000001U)
 
-#define EDMA3_CCRL_EEVAL_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_EEVAL_RESETVAL        (0x00000000U)
 
 /* DRAE */
 
-#define EDMA3_CCRL_DRAE_E31_MASK         (0x80000000u)
-#define EDMA3_CCRL_DRAE_E31_SHIFT        (0x0000001Fu)
-#define EDMA3_CCRL_DRAE_E31_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E31_MASK         (0x80000000U)
+#define EDMA3_CCRL_DRAE_E31_SHIFT        (0x0000001FU)
+#define EDMA3_CCRL_DRAE_E31_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E30_MASK         (0x40000000u)
-#define EDMA3_CCRL_DRAE_E30_SHIFT        (0x0000001Eu)
-#define EDMA3_CCRL_DRAE_E30_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E30_MASK         (0x40000000U)
+#define EDMA3_CCRL_DRAE_E30_SHIFT        (0x0000001EU)
+#define EDMA3_CCRL_DRAE_E30_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E29_MASK         (0x20000000u)
-#define EDMA3_CCRL_DRAE_E29_SHIFT        (0x0000001Du)
-#define EDMA3_CCRL_DRAE_E29_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E29_MASK         (0x20000000U)
+#define EDMA3_CCRL_DRAE_E29_SHIFT        (0x0000001DU)
+#define EDMA3_CCRL_DRAE_E29_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E28_MASK         (0x10000000u)
-#define EDMA3_CCRL_DRAE_E28_SHIFT        (0x0000001Cu)
-#define EDMA3_CCRL_DRAE_E28_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E28_MASK         (0x10000000U)
+#define EDMA3_CCRL_DRAE_E28_SHIFT        (0x0000001CU)
+#define EDMA3_CCRL_DRAE_E28_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E27_MASK         (0x08000000u)
-#define EDMA3_CCRL_DRAE_E27_SHIFT        (0x0000001Bu)
-#define EDMA3_CCRL_DRAE_E27_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E27_MASK         (0x08000000U)
+#define EDMA3_CCRL_DRAE_E27_SHIFT        (0x0000001BU)
+#define EDMA3_CCRL_DRAE_E27_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E26_MASK         (0x04000000u)
-#define EDMA3_CCRL_DRAE_E26_SHIFT        (0x0000001Au)
-#define EDMA3_CCRL_DRAE_E26_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E26_MASK         (0x04000000U)
+#define EDMA3_CCRL_DRAE_E26_SHIFT        (0x0000001AU)
+#define EDMA3_CCRL_DRAE_E26_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E25_MASK         (0x02000000u)
-#define EDMA3_CCRL_DRAE_E25_SHIFT        (0x00000019u)
-#define EDMA3_CCRL_DRAE_E25_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E25_MASK         (0x02000000U)
+#define EDMA3_CCRL_DRAE_E25_SHIFT        (0x00000019U)
+#define EDMA3_CCRL_DRAE_E25_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E24_MASK         (0x01000000u)
-#define EDMA3_CCRL_DRAE_E24_SHIFT        (0x00000018u)
-#define EDMA3_CCRL_DRAE_E24_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E24_MASK         (0x01000000U)
+#define EDMA3_CCRL_DRAE_E24_SHIFT        (0x00000018U)
+#define EDMA3_CCRL_DRAE_E24_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E23_MASK         (0x00800000u)
-#define EDMA3_CCRL_DRAE_E23_SHIFT        (0x00000017u)
-#define EDMA3_CCRL_DRAE_E23_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E23_MASK         (0x00800000U)
+#define EDMA3_CCRL_DRAE_E23_SHIFT        (0x00000017U)
+#define EDMA3_CCRL_DRAE_E23_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E22_MASK         (0x00400000u)
-#define EDMA3_CCRL_DRAE_E22_SHIFT        (0x00000016u)
-#define EDMA3_CCRL_DRAE_E22_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E22_MASK         (0x00400000U)
+#define EDMA3_CCRL_DRAE_E22_SHIFT        (0x00000016U)
+#define EDMA3_CCRL_DRAE_E22_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E21_MASK         (0x00200000u)
-#define EDMA3_CCRL_DRAE_E21_SHIFT        (0x00000015u)
-#define EDMA3_CCRL_DRAE_E21_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E21_MASK         (0x00200000U)
+#define EDMA3_CCRL_DRAE_E21_SHIFT        (0x00000015U)
+#define EDMA3_CCRL_DRAE_E21_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E20_MASK         (0x00100000u)
-#define EDMA3_CCRL_DRAE_E20_SHIFT        (0x00000014u)
-#define EDMA3_CCRL_DRAE_E20_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E20_MASK         (0x00100000U)
+#define EDMA3_CCRL_DRAE_E20_SHIFT        (0x00000014U)
+#define EDMA3_CCRL_DRAE_E20_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E19_MASK         (0x00080000u)
-#define EDMA3_CCRL_DRAE_E19_SHIFT        (0x00000013u)
-#define EDMA3_CCRL_DRAE_E19_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E19_MASK         (0x00080000U)
+#define EDMA3_CCRL_DRAE_E19_SHIFT        (0x00000013U)
+#define EDMA3_CCRL_DRAE_E19_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E18_MASK         (0x00040000u)
-#define EDMA3_CCRL_DRAE_E18_SHIFT        (0x00000012u)
-#define EDMA3_CCRL_DRAE_E18_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E18_MASK         (0x00040000U)
+#define EDMA3_CCRL_DRAE_E18_SHIFT        (0x00000012U)
+#define EDMA3_CCRL_DRAE_E18_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E17_MASK         (0x00020000u)
-#define EDMA3_CCRL_DRAE_E17_SHIFT        (0x00000011u)
-#define EDMA3_CCRL_DRAE_E17_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E17_MASK         (0x00020000U)
+#define EDMA3_CCRL_DRAE_E17_SHIFT        (0x00000011U)
+#define EDMA3_CCRL_DRAE_E17_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E16_MASK         (0x00010000u)
-#define EDMA3_CCRL_DRAE_E16_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_DRAE_E16_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E16_MASK         (0x00010000U)
+#define EDMA3_CCRL_DRAE_E16_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_DRAE_E16_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E15_MASK         (0x00008000u)
-#define EDMA3_CCRL_DRAE_E15_SHIFT        (0x0000000Fu)
-#define EDMA3_CCRL_DRAE_E15_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E15_MASK         (0x00008000U)
+#define EDMA3_CCRL_DRAE_E15_SHIFT        (0x0000000FU)
+#define EDMA3_CCRL_DRAE_E15_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E14_MASK         (0x00004000u)
-#define EDMA3_CCRL_DRAE_E14_SHIFT        (0x0000000Eu)
-#define EDMA3_CCRL_DRAE_E14_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E14_MASK         (0x00004000U)
+#define EDMA3_CCRL_DRAE_E14_SHIFT        (0x0000000EU)
+#define EDMA3_CCRL_DRAE_E14_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E13_MASK         (0x00002000u)
-#define EDMA3_CCRL_DRAE_E13_SHIFT        (0x0000000Du)
-#define EDMA3_CCRL_DRAE_E13_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E13_MASK         (0x00002000U)
+#define EDMA3_CCRL_DRAE_E13_SHIFT        (0x0000000DU)
+#define EDMA3_CCRL_DRAE_E13_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E12_MASK         (0x00001000u)
-#define EDMA3_CCRL_DRAE_E12_SHIFT        (0x0000000Cu)
-#define EDMA3_CCRL_DRAE_E12_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E12_MASK         (0x00001000U)
+#define EDMA3_CCRL_DRAE_E12_SHIFT        (0x0000000CU)
+#define EDMA3_CCRL_DRAE_E12_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E11_MASK         (0x00000800u)
-#define EDMA3_CCRL_DRAE_E11_SHIFT        (0x0000000Bu)
-#define EDMA3_CCRL_DRAE_E11_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E11_MASK         (0x00000800U)
+#define EDMA3_CCRL_DRAE_E11_SHIFT        (0x0000000BU)
+#define EDMA3_CCRL_DRAE_E11_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E10_MASK         (0x00000400u)
-#define EDMA3_CCRL_DRAE_E10_SHIFT        (0x0000000Au)
-#define EDMA3_CCRL_DRAE_E10_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_DRAE_E10_MASK         (0x00000400U)
+#define EDMA3_CCRL_DRAE_E10_SHIFT        (0x0000000AU)
+#define EDMA3_CCRL_DRAE_E10_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E9_MASK          (0x00000200u)
-#define EDMA3_CCRL_DRAE_E9_SHIFT         (0x00000009u)
-#define EDMA3_CCRL_DRAE_E9_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DRAE_E9_MASK          (0x00000200U)
+#define EDMA3_CCRL_DRAE_E9_SHIFT         (0x00000009U)
+#define EDMA3_CCRL_DRAE_E9_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E8_MASK          (0x00000100u)
-#define EDMA3_CCRL_DRAE_E8_SHIFT         (0x00000008u)
-#define EDMA3_CCRL_DRAE_E8_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DRAE_E8_MASK          (0x00000100U)
+#define EDMA3_CCRL_DRAE_E8_SHIFT         (0x00000008U)
+#define EDMA3_CCRL_DRAE_E8_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E7_MASK          (0x00000080u)
-#define EDMA3_CCRL_DRAE_E7_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_DRAE_E7_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DRAE_E7_MASK          (0x00000080U)
+#define EDMA3_CCRL_DRAE_E7_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_DRAE_E7_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E6_MASK          (0x00000040u)
-#define EDMA3_CCRL_DRAE_E6_SHIFT         (0x00000006u)
-#define EDMA3_CCRL_DRAE_E6_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DRAE_E6_MASK          (0x00000040U)
+#define EDMA3_CCRL_DRAE_E6_SHIFT         (0x00000006U)
+#define EDMA3_CCRL_DRAE_E6_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E5_MASK          (0x00000020u)
-#define EDMA3_CCRL_DRAE_E5_SHIFT         (0x00000005u)
-#define EDMA3_CCRL_DRAE_E5_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DRAE_E5_MASK          (0x00000020U)
+#define EDMA3_CCRL_DRAE_E5_SHIFT         (0x00000005U)
+#define EDMA3_CCRL_DRAE_E5_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E4_MASK          (0x00000010u)
-#define EDMA3_CCRL_DRAE_E4_SHIFT         (0x00000004u)
-#define EDMA3_CCRL_DRAE_E4_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DRAE_E4_MASK          (0x00000010U)
+#define EDMA3_CCRL_DRAE_E4_SHIFT         (0x00000004U)
+#define EDMA3_CCRL_DRAE_E4_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E3_MASK          (0x00000008u)
-#define EDMA3_CCRL_DRAE_E3_SHIFT         (0x00000003u)
-#define EDMA3_CCRL_DRAE_E3_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DRAE_E3_MASK          (0x00000008U)
+#define EDMA3_CCRL_DRAE_E3_SHIFT         (0x00000003U)
+#define EDMA3_CCRL_DRAE_E3_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E2_MASK          (0x00000004u)
-#define EDMA3_CCRL_DRAE_E2_SHIFT         (0x00000002u)
-#define EDMA3_CCRL_DRAE_E2_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DRAE_E2_MASK          (0x00000004U)
+#define EDMA3_CCRL_DRAE_E2_SHIFT         (0x00000002U)
+#define EDMA3_CCRL_DRAE_E2_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E1_MASK          (0x00000002u)
-#define EDMA3_CCRL_DRAE_E1_SHIFT         (0x00000001u)
-#define EDMA3_CCRL_DRAE_E1_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DRAE_E1_MASK          (0x00000002U)
+#define EDMA3_CCRL_DRAE_E1_SHIFT         (0x00000001U)
+#define EDMA3_CCRL_DRAE_E1_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_E0_MASK          (0x00000001u)
-#define EDMA3_CCRL_DRAE_E0_SHIFT         (0x00000000u)
-#define EDMA3_CCRL_DRAE_E0_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_DRAE_E0_MASK          (0x00000001U)
+#define EDMA3_CCRL_DRAE_E0_SHIFT         (0x00000000U)
+#define EDMA3_CCRL_DRAE_E0_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_DRAE_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_DRAE_RESETVAL         (0x00000000U)
 
 /* DRAEH */
 
-#define EDMA3_CCRL_DRAEH_E63_MASK        (0x80000000u)
-#define EDMA3_CCRL_DRAEH_E63_SHIFT       (0x0000001Fu)
-#define EDMA3_CCRL_DRAEH_E63_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E63_MASK        (0x80000000U)
+#define EDMA3_CCRL_DRAEH_E63_SHIFT       (0x0000001FU)
+#define EDMA3_CCRL_DRAEH_E63_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E62_MASK        (0x40000000u)
-#define EDMA3_CCRL_DRAEH_E62_SHIFT       (0x0000001Eu)
-#define EDMA3_CCRL_DRAEH_E62_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E62_MASK        (0x40000000U)
+#define EDMA3_CCRL_DRAEH_E62_SHIFT       (0x0000001EU)
+#define EDMA3_CCRL_DRAEH_E62_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E61_MASK        (0x20000000u)
-#define EDMA3_CCRL_DRAEH_E61_SHIFT       (0x0000001Du)
-#define EDMA3_CCRL_DRAEH_E61_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E61_MASK        (0x20000000U)
+#define EDMA3_CCRL_DRAEH_E61_SHIFT       (0x0000001DU)
+#define EDMA3_CCRL_DRAEH_E61_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E60_MASK        (0x10000000u)
-#define EDMA3_CCRL_DRAEH_E60_SHIFT       (0x0000001Cu)
-#define EDMA3_CCRL_DRAEH_E60_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E60_MASK        (0x10000000U)
+#define EDMA3_CCRL_DRAEH_E60_SHIFT       (0x0000001CU)
+#define EDMA3_CCRL_DRAEH_E60_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E59_MASK        (0x08000000u)
-#define EDMA3_CCRL_DRAEH_E59_SHIFT       (0x0000001Bu)
-#define EDMA3_CCRL_DRAEH_E59_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E59_MASK        (0x08000000U)
+#define EDMA3_CCRL_DRAEH_E59_SHIFT       (0x0000001BU)
+#define EDMA3_CCRL_DRAEH_E59_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E58_MASK        (0x04000000u)
-#define EDMA3_CCRL_DRAEH_E58_SHIFT       (0x0000001Au)
-#define EDMA3_CCRL_DRAEH_E58_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E58_MASK        (0x04000000U)
+#define EDMA3_CCRL_DRAEH_E58_SHIFT       (0x0000001AU)
+#define EDMA3_CCRL_DRAEH_E58_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E57_MASK        (0x02000000u)
-#define EDMA3_CCRL_DRAEH_E57_SHIFT       (0x00000019u)
-#define EDMA3_CCRL_DRAEH_E57_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E57_MASK        (0x02000000U)
+#define EDMA3_CCRL_DRAEH_E57_SHIFT       (0x00000019U)
+#define EDMA3_CCRL_DRAEH_E57_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E56_MASK        (0x01000000u)
-#define EDMA3_CCRL_DRAEH_E56_SHIFT       (0x00000018u)
-#define EDMA3_CCRL_DRAEH_E56_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E56_MASK        (0x01000000U)
+#define EDMA3_CCRL_DRAEH_E56_SHIFT       (0x00000018U)
+#define EDMA3_CCRL_DRAEH_E56_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E55_MASK        (0x00800000u)
-#define EDMA3_CCRL_DRAEH_E55_SHIFT       (0x00000017u)
-#define EDMA3_CCRL_DRAEH_E55_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E55_MASK        (0x00800000U)
+#define EDMA3_CCRL_DRAEH_E55_SHIFT       (0x00000017U)
+#define EDMA3_CCRL_DRAEH_E55_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E54_MASK        (0x00400000u)
-#define EDMA3_CCRL_DRAEH_E54_SHIFT       (0x00000016u)
-#define EDMA3_CCRL_DRAEH_E54_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E54_MASK        (0x00400000U)
+#define EDMA3_CCRL_DRAEH_E54_SHIFT       (0x00000016U)
+#define EDMA3_CCRL_DRAEH_E54_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E53_MASK        (0x00200000u)
-#define EDMA3_CCRL_DRAEH_E53_SHIFT       (0x00000015u)
-#define EDMA3_CCRL_DRAEH_E53_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E53_MASK        (0x00200000U)
+#define EDMA3_CCRL_DRAEH_E53_SHIFT       (0x00000015U)
+#define EDMA3_CCRL_DRAEH_E53_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E52_MASK        (0x00100000u)
-#define EDMA3_CCRL_DRAEH_E52_SHIFT       (0x00000014u)
-#define EDMA3_CCRL_DRAEH_E52_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E52_MASK        (0x00100000U)
+#define EDMA3_CCRL_DRAEH_E52_SHIFT       (0x00000014U)
+#define EDMA3_CCRL_DRAEH_E52_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E51_MASK        (0x00080000u)
-#define EDMA3_CCRL_DRAEH_E51_SHIFT       (0x00000013u)
-#define EDMA3_CCRL_DRAEH_E51_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E51_MASK        (0x00080000U)
+#define EDMA3_CCRL_DRAEH_E51_SHIFT       (0x00000013U)
+#define EDMA3_CCRL_DRAEH_E51_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E50_MASK        (0x00040000u)
-#define EDMA3_CCRL_DRAEH_E50_SHIFT       (0x00000012u)
-#define EDMA3_CCRL_DRAEH_E50_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E50_MASK        (0x00040000U)
+#define EDMA3_CCRL_DRAEH_E50_SHIFT       (0x00000012U)
+#define EDMA3_CCRL_DRAEH_E50_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E49_MASK        (0x00020000u)
-#define EDMA3_CCRL_DRAEH_E49_SHIFT       (0x00000011u)
-#define EDMA3_CCRL_DRAEH_E49_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E49_MASK        (0x00020000U)
+#define EDMA3_CCRL_DRAEH_E49_SHIFT       (0x00000011U)
+#define EDMA3_CCRL_DRAEH_E49_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E48_MASK        (0x00010000u)
-#define EDMA3_CCRL_DRAEH_E48_SHIFT       (0x00000010u)
-#define EDMA3_CCRL_DRAEH_E48_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E48_MASK        (0x00010000U)
+#define EDMA3_CCRL_DRAEH_E48_SHIFT       (0x00000010U)
+#define EDMA3_CCRL_DRAEH_E48_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E47_MASK        (0x00008000u)
-#define EDMA3_CCRL_DRAEH_E47_SHIFT       (0x0000000Fu)
-#define EDMA3_CCRL_DRAEH_E47_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E47_MASK        (0x00008000U)
+#define EDMA3_CCRL_DRAEH_E47_SHIFT       (0x0000000FU)
+#define EDMA3_CCRL_DRAEH_E47_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E46_MASK        (0x00004000u)
-#define EDMA3_CCRL_DRAEH_E46_SHIFT       (0x0000000Eu)
-#define EDMA3_CCRL_DRAEH_E46_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E46_MASK        (0x00004000U)
+#define EDMA3_CCRL_DRAEH_E46_SHIFT       (0x0000000EU)
+#define EDMA3_CCRL_DRAEH_E46_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E45_MASK        (0x00002000u)
-#define EDMA3_CCRL_DRAEH_E45_SHIFT       (0x0000000Du)
-#define EDMA3_CCRL_DRAEH_E45_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E45_MASK        (0x00002000U)
+#define EDMA3_CCRL_DRAEH_E45_SHIFT       (0x0000000DU)
+#define EDMA3_CCRL_DRAEH_E45_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E44_MASK        (0x00001000u)
-#define EDMA3_CCRL_DRAEH_E44_SHIFT       (0x0000000Cu)
-#define EDMA3_CCRL_DRAEH_E44_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E44_MASK        (0x00001000U)
+#define EDMA3_CCRL_DRAEH_E44_SHIFT       (0x0000000CU)
+#define EDMA3_CCRL_DRAEH_E44_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E43_MASK        (0x00000800u)
-#define EDMA3_CCRL_DRAEH_E43_SHIFT       (0x0000000Bu)
-#define EDMA3_CCRL_DRAEH_E43_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E43_MASK        (0x00000800U)
+#define EDMA3_CCRL_DRAEH_E43_SHIFT       (0x0000000BU)
+#define EDMA3_CCRL_DRAEH_E43_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E42_MASK        (0x00000400u)
-#define EDMA3_CCRL_DRAEH_E42_SHIFT       (0x0000000Au)
-#define EDMA3_CCRL_DRAEH_E42_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E42_MASK        (0x00000400U)
+#define EDMA3_CCRL_DRAEH_E42_SHIFT       (0x0000000AU)
+#define EDMA3_CCRL_DRAEH_E42_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E41_MASK        (0x00000200u)
-#define EDMA3_CCRL_DRAEH_E41_SHIFT       (0x00000009u)
-#define EDMA3_CCRL_DRAEH_E41_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E41_MASK        (0x00000200U)
+#define EDMA3_CCRL_DRAEH_E41_SHIFT       (0x00000009U)
+#define EDMA3_CCRL_DRAEH_E41_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E40_MASK        (0x00000100u)
-#define EDMA3_CCRL_DRAEH_E40_SHIFT       (0x00000008u)
-#define EDMA3_CCRL_DRAEH_E40_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E40_MASK        (0x00000100U)
+#define EDMA3_CCRL_DRAEH_E40_SHIFT       (0x00000008U)
+#define EDMA3_CCRL_DRAEH_E40_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E39_MASK        (0x00000080u)
-#define EDMA3_CCRL_DRAEH_E39_SHIFT       (0x00000007u)
-#define EDMA3_CCRL_DRAEH_E39_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E39_MASK        (0x00000080U)
+#define EDMA3_CCRL_DRAEH_E39_SHIFT       (0x00000007U)
+#define EDMA3_CCRL_DRAEH_E39_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E38_MASK        (0x00000040u)
-#define EDMA3_CCRL_DRAEH_E38_SHIFT       (0x00000006u)
-#define EDMA3_CCRL_DRAEH_E38_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E38_MASK        (0x00000040U)
+#define EDMA3_CCRL_DRAEH_E38_SHIFT       (0x00000006U)
+#define EDMA3_CCRL_DRAEH_E38_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E37_MASK        (0x00000020u)
-#define EDMA3_CCRL_DRAEH_E37_SHIFT       (0x00000005u)
-#define EDMA3_CCRL_DRAEH_E37_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E37_MASK        (0x00000020U)
+#define EDMA3_CCRL_DRAEH_E37_SHIFT       (0x00000005U)
+#define EDMA3_CCRL_DRAEH_E37_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E36_MASK        (0x00000010u)
-#define EDMA3_CCRL_DRAEH_E36_SHIFT       (0x00000004u)
-#define EDMA3_CCRL_DRAEH_E36_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E36_MASK        (0x00000010U)
+#define EDMA3_CCRL_DRAEH_E36_SHIFT       (0x00000004U)
+#define EDMA3_CCRL_DRAEH_E36_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E35_MASK        (0x00000008u)
-#define EDMA3_CCRL_DRAEH_E35_SHIFT       (0x00000003u)
-#define EDMA3_CCRL_DRAEH_E35_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E35_MASK        (0x00000008U)
+#define EDMA3_CCRL_DRAEH_E35_SHIFT       (0x00000003U)
+#define EDMA3_CCRL_DRAEH_E35_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E34_MASK        (0x00000004u)
-#define EDMA3_CCRL_DRAEH_E34_SHIFT       (0x00000002u)
-#define EDMA3_CCRL_DRAEH_E34_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E34_MASK        (0x00000004U)
+#define EDMA3_CCRL_DRAEH_E34_SHIFT       (0x00000002U)
+#define EDMA3_CCRL_DRAEH_E34_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E33_MASK        (0x00000002u)
-#define EDMA3_CCRL_DRAEH_E33_SHIFT       (0x00000001u)
-#define EDMA3_CCRL_DRAEH_E33_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E33_MASK        (0x00000002U)
+#define EDMA3_CCRL_DRAEH_E33_SHIFT       (0x00000001U)
+#define EDMA3_CCRL_DRAEH_E33_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_E32_MASK        (0x00000001u)
-#define EDMA3_CCRL_DRAEH_E32_SHIFT       (0x00000000u)
-#define EDMA3_CCRL_DRAEH_E32_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_DRAEH_E32_MASK        (0x00000001U)
+#define EDMA3_CCRL_DRAEH_E32_SHIFT       (0x00000000U)
+#define EDMA3_CCRL_DRAEH_E32_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_DRAEH_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_DRAEH_RESETVAL        (0x00000000U)
 
 /* QRAE */
 
-#define EDMA3_CCRL_QRAE_E7_MASK          (0x00000080u)
-#define EDMA3_CCRL_QRAE_E7_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_QRAE_E7_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QRAE_E7_MASK          (0x00000080U)
+#define EDMA3_CCRL_QRAE_E7_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_QRAE_E7_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QRAE_E6_MASK          (0x00000080u)
-#define EDMA3_CCRL_QRAE_E6_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_QRAE_E6_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QRAE_E6_MASK          (0x00000080U)
+#define EDMA3_CCRL_QRAE_E6_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_QRAE_E6_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QRAE_E5_MASK          (0x00000080u)
-#define EDMA3_CCRL_QRAE_E5_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_QRAE_E5_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QRAE_E5_MASK          (0x00000080U)
+#define EDMA3_CCRL_QRAE_E5_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_QRAE_E5_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QRAE_E4_MASK          (0x00000080u)
-#define EDMA3_CCRL_QRAE_E4_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_QRAE_E4_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QRAE_E4_MASK          (0x00000080U)
+#define EDMA3_CCRL_QRAE_E4_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_QRAE_E4_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QRAE_E3_MASK          (0x00000080u)
-#define EDMA3_CCRL_QRAE_E3_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_QRAE_E3_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QRAE_E3_MASK          (0x00000080U)
+#define EDMA3_CCRL_QRAE_E3_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_QRAE_E3_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QRAE_E2_MASK          (0x00000080u)
-#define EDMA3_CCRL_QRAE_E2_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_QRAE_E2_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QRAE_E2_MASK          (0x00000080U)
+#define EDMA3_CCRL_QRAE_E2_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_QRAE_E2_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QRAE_E1_MASK          (0x00000080u)
-#define EDMA3_CCRL_QRAE_E1_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_QRAE_E1_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QRAE_E1_MASK          (0x00000080U)
+#define EDMA3_CCRL_QRAE_E1_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_QRAE_E1_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QRAE_E0_MASK          (0x00000080u)
-#define EDMA3_CCRL_QRAE_E0_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_QRAE_E0_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_QRAE_E0_MASK          (0x00000080U)
+#define EDMA3_CCRL_QRAE_E0_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_QRAE_E0_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_QRAE_RESERVED_MASK    (0x0000007Fu)
-#define EDMA3_CCRL_QRAE_RESERVED_SHIFT   (0x00000000u)
-#define EDMA3_CCRL_QRAE_RESERVED_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QRAE_RESERVED_MASK    (0x0000007FU)
+#define EDMA3_CCRL_QRAE_RESERVED_SHIFT   (0x00000000U)
+#define EDMA3_CCRL_QRAE_RESERVED_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QRAE_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_QRAE_RESETVAL         (0x00000000U)
 
 /* QUEEVT_ENTRY */
 
-#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_MASK (0xFFFFFF00u)
-#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_SHIFT (0x00000008u)
-#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_MASK (0xFFFFFF00U)
+#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_SHIFT (0x00000008U)
+#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_MASK (0x000000C0u)
-#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_SHIFT (0x00000006u)
-#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_MASK (0x000000C0U)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_SHIFT (0x00000006U)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_MASK (0x0000003Fu)
-#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SHIFT (0x00000000u)
-#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_MASK (0x0000003FU)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SHIFT (0x00000000U)
+#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QUEEVT_ENTRY_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QUEEVT_ENTRY_RESETVAL (0x00000000U)
 
 /* QSTAT */
 
-#define EDMA3_CCRL_QSTAT_THRXD_MASK      (0x01000000u)
-#define EDMA3_CCRL_QSTAT_THRXD_SHIFT     (0x00000018u)
-#define EDMA3_CCRL_QSTAT_THRXD_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_QSTAT_THRXD_MASK      (0x01000000U)
+#define EDMA3_CCRL_QSTAT_THRXD_SHIFT     (0x00000018U)
+#define EDMA3_CCRL_QSTAT_THRXD_RESETVAL  (0x00000000U)
 
-#define EDMA3_CCRL_QSTAT_RESERVED_MASK   (0x00600000u)
-#define EDMA3_CCRL_QSTAT_RESERVED_SHIFT  (0x00000015u)
-#define EDMA3_CCRL_QSTAT_RESERVED_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QSTAT_RESERVED_MASK   (0x00600000U)
+#define EDMA3_CCRL_QSTAT_RESERVED_SHIFT  (0x00000015U)
+#define EDMA3_CCRL_QSTAT_RESERVED_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QSTAT_WM_MASK         (0x001F0000u)
-#define EDMA3_CCRL_QSTAT_WM_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_QSTAT_WM_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_QSTAT_WM_MASK         (0x001F0000U)
+#define EDMA3_CCRL_QSTAT_WM_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_QSTAT_WM_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_QSTAT_NUMVAL_MASK     (0x00001F00u)
-#define EDMA3_CCRL_QSTAT_NUMVAL_SHIFT    (0x00000008u)
-#define EDMA3_CCRL_QSTAT_NUMVAL_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QSTAT_NUMVAL_MASK     (0x00001F00U)
+#define EDMA3_CCRL_QSTAT_NUMVAL_SHIFT    (0x00000008U)
+#define EDMA3_CCRL_QSTAT_NUMVAL_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QSTAT_STRTPTR_MASK    (0x0000000Fu)
-#define EDMA3_CCRL_QSTAT_STRTPTR_SHIFT   (0x00000000u)
-#define EDMA3_CCRL_QSTAT_STRTPTR_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_QSTAT_STRTPTR_MASK    (0x0000000FU)
+#define EDMA3_CCRL_QSTAT_STRTPTR_SHIFT   (0x00000000U)
+#define EDMA3_CCRL_QSTAT_STRTPTR_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_QSTAT_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_QSTAT_RESETVAL        (0x00000000U)
 
 /* QWMTHRA */
 
-#define EDMA3_CCRL_QWMTHRA_Q3_MASK       (0x1F000000u)
-#define EDMA3_CCRL_QWMTHRA_Q3_SHIFT      (0x00000018u)
-#define EDMA3_CCRL_QWMTHRA_Q3_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRA_Q3_MASK       (0x1F000000U)
+#define EDMA3_CCRL_QWMTHRA_Q3_SHIFT      (0x00000018U)
+#define EDMA3_CCRL_QWMTHRA_Q3_RESETVAL   (0x00000010U)
 
-#define EDMA3_CCRL_QWMTHRA_Q2_MASK       (0x001F0000u)
-#define EDMA3_CCRL_QWMTHRA_Q2_SHIFT      (0x00000010u)
-#define EDMA3_CCRL_QWMTHRA_Q2_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRA_Q2_MASK       (0x001F0000U)
+#define EDMA3_CCRL_QWMTHRA_Q2_SHIFT      (0x00000010U)
+#define EDMA3_CCRL_QWMTHRA_Q2_RESETVAL   (0x00000010U)
 
-#define EDMA3_CCRL_QWMTHRA_Q1_MASK       (0x00001F00u)
-#define EDMA3_CCRL_QWMTHRA_Q1_SHIFT      (0x00000008u)
-#define EDMA3_CCRL_QWMTHRA_Q1_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRA_Q1_MASK       (0x00001F00U)
+#define EDMA3_CCRL_QWMTHRA_Q1_SHIFT      (0x00000008U)
+#define EDMA3_CCRL_QWMTHRA_Q1_RESETVAL   (0x00000010U)
 
-#define EDMA3_CCRL_QWMTHRA_Q0_MASK       (0x0000001Fu)
-#define EDMA3_CCRL_QWMTHRA_Q0_SHIFT      (0x00000000u)
-#define EDMA3_CCRL_QWMTHRA_Q0_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRA_Q0_MASK       (0x0000001FU)
+#define EDMA3_CCRL_QWMTHRA_Q0_SHIFT      (0x00000000U)
+#define EDMA3_CCRL_QWMTHRA_Q0_RESETVAL   (0x00000010U)
 
-#define EDMA3_CCRL_QWMTHRA_RESETVAL      (0x10101010u)
+#define EDMA3_CCRL_QWMTHRA_RESETVAL      (0x10101010U)
 
 /* QWMTHRB */
 
-#define EDMA3_CCRL_QWMTHRB_Q7_MASK       (0x1F000000u)
-#define EDMA3_CCRL_QWMTHRB_Q7_SHIFT      (0x00000018u)
-#define EDMA3_CCRL_QWMTHRB_Q7_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRB_Q7_MASK       (0x1F000000U)
+#define EDMA3_CCRL_QWMTHRB_Q7_SHIFT      (0x00000018U)
+#define EDMA3_CCRL_QWMTHRB_Q7_RESETVAL   (0x00000010U)
 
-#define EDMA3_CCRL_QWMTHRB_Q6_MASK       (0x001F0000u)
-#define EDMA3_CCRL_QWMTHRB_Q6_SHIFT      (0x00000010u)
-#define EDMA3_CCRL_QWMTHRB_Q6_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRB_Q6_MASK       (0x001F0000U)
+#define EDMA3_CCRL_QWMTHRB_Q6_SHIFT      (0x00000010U)
+#define EDMA3_CCRL_QWMTHRB_Q6_RESETVAL   (0x00000010U)
 
-#define EDMA3_CCRL_QWMTHRB_Q5_MASK       (0x00001F00u)
-#define EDMA3_CCRL_QWMTHRB_Q5_SHIFT      (0x00000008u)
-#define EDMA3_CCRL_QWMTHRB_Q5_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRB_Q5_MASK       (0x00001F00U)
+#define EDMA3_CCRL_QWMTHRB_Q5_SHIFT      (0x00000008U)
+#define EDMA3_CCRL_QWMTHRB_Q5_RESETVAL   (0x00000010U)
 
-#define EDMA3_CCRL_QWMTHRB_Q4_MASK       (0x0000001Fu)
-#define EDMA3_CCRL_QWMTHRB_Q4_SHIFT      (0x00000000u)
-#define EDMA3_CCRL_QWMTHRB_Q4_RESETVAL   (0x00000010u)
+#define EDMA3_CCRL_QWMTHRB_Q4_MASK       (0x0000001FU)
+#define EDMA3_CCRL_QWMTHRB_Q4_SHIFT      (0x00000000U)
+#define EDMA3_CCRL_QWMTHRB_Q4_RESETVAL   (0x00000010U)
 
-#define EDMA3_CCRL_QWMTHRB_RESETVAL      (0x10101010u)
+#define EDMA3_CCRL_QWMTHRB_RESETVAL      (0x10101010U)
 
 /* CCSTAT */
 
-#define EDMA3_CCRL_CCSTAT_QUEACTV7_MASK  (0x00800000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV7_SHIFT (0x00000017u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV7_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV7_MASK  (0x00800000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV7_SHIFT (0x00000017U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV7_RESETVAL (0x00000000U)
 
 /*----QUEACTV7 Tokens----*/
-#define EDMA3_CCRL_CCSTAT_QUEACTV7_NONE  (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV7_ACTIVE (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV7_NONE  (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV7_ACTIVE (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_QUEACTV6_MASK  (0x00400000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV6_SHIFT (0x00000016u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV6_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV6_MASK  (0x00400000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV6_SHIFT (0x00000016U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV6_RESETVAL (0x00000000U)
 
 /*----QUEACTV6 Tokens----*/
-#define EDMA3_CCRL_CCSTAT_QUEACTV6_NONE  (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV6_ACTIVE (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV6_NONE  (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV6_ACTIVE (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_QUEACTV5_MASK  (0x00200000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV5_SHIFT (0x00000015u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV5_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV5_MASK  (0x00200000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV5_SHIFT (0x00000015U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV5_RESETVAL (0x00000000U)
 
 /*----QUEACTV5 Tokens----*/
-#define EDMA3_CCRL_CCSTAT_QUEACTV5_NONE  (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV5_ACTIVE (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV5_NONE  (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV5_ACTIVE (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_QUEACTV4_MASK  (0x00100000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV4_SHIFT (0x00000014u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV4_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV4_MASK  (0x00100000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV4_SHIFT (0x00000014U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV4_RESETVAL (0x00000000U)
 
 /*----QUEACTV4 Tokens----*/
-#define EDMA3_CCRL_CCSTAT_QUEACTV4_NONE  (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV4_ACTIVE (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV4_NONE  (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV4_ACTIVE (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_QUEACTV3_MASK  (0x00080000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV3_SHIFT (0x00000013u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV3_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV3_MASK  (0x00080000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV3_SHIFT (0x00000013U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV3_RESETVAL (0x00000000U)
 
 /*----QUEACTV3 Tokens----*/
-#define EDMA3_CCRL_CCSTAT_QUEACTV3_NONE  (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV3_ACTIVE (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV3_NONE  (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV3_ACTIVE (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_QUEACTV2_MASK  (0x00040000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV2_SHIFT (0x00000012u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV2_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV2_MASK  (0x00040000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV2_SHIFT (0x00000012U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV2_RESETVAL (0x00000000U)
 
 /*----QUEACTV2 Tokens----*/
-#define EDMA3_CCRL_CCSTAT_QUEACTV2_NONE  (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV2_ACTIVE (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV2_NONE  (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV2_ACTIVE (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_QUEACTV1_MASK  (0x00020000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV1_SHIFT (0x00000011u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV1_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV1_MASK  (0x00020000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV1_SHIFT (0x00000011U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV1_RESETVAL (0x00000000U)
 
 /*----QUEACTV1 Tokens----*/
-#define EDMA3_CCRL_CCSTAT_QUEACTV1_NONE  (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV1_ACTIVE (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV1_NONE  (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV1_ACTIVE (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_QUEACTV0_MASK  (0x00010000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV0_SHIFT (0x00000010u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV0_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV0_MASK  (0x00010000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV0_SHIFT (0x00000010U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV0_RESETVAL (0x00000000U)
 
 /*----QUEACTV0 Tokens----*/
-#define EDMA3_CCRL_CCSTAT_QUEACTV0_NONE  (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_QUEACTV0_ACTIVE (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QUEACTV0_NONE  (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_QUEACTV0_ACTIVE (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_COMPACT_MASK   (0x00003F00u)
-#define EDMA3_CCRL_CCSTAT_COMPACT_SHIFT  (0x00000008u)
-#define EDMA3_CCRL_CCSTAT_COMPACT_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_COMPACT_MASK   (0x00003F00U)
+#define EDMA3_CCRL_CCSTAT_COMPACT_SHIFT  (0x00000008U)
+#define EDMA3_CCRL_CCSTAT_COMPACT_RESETVAL (0x00000000U)
 
 /*----COMPACT Tokens----*/
-#define EDMA3_CCRL_CCSTAT_COMPACT_NONE   (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_COMPACT_NONE   (0x00000000U)
 
-#define EDMA3_CCRL_CCSTAT_ACTV_MASK      (0x00000010u)
-#define EDMA3_CCRL_CCSTAT_ACTV_SHIFT     (0x00000004u)
-#define EDMA3_CCRL_CCSTAT_ACTV_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_ACTV_MASK      (0x00000010U)
+#define EDMA3_CCRL_CCSTAT_ACTV_SHIFT     (0x00000004U)
+#define EDMA3_CCRL_CCSTAT_ACTV_RESETVAL  (0x00000000U)
 
 /*----ACTV Tokens----*/
-#define EDMA3_CCRL_CCSTAT_ACTV_IDLE      (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_ACTV_BUSY      (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_ACTV_IDLE      (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_ACTV_BUSY      (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_TRACTV_MASK    (0x00000004u)
-#define EDMA3_CCRL_CCSTAT_TRACTV_SHIFT   (0x00000002u)
-#define EDMA3_CCRL_CCSTAT_TRACTV_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_TRACTV_MASK    (0x00000004U)
+#define EDMA3_CCRL_CCSTAT_TRACTV_SHIFT   (0x00000002U)
+#define EDMA3_CCRL_CCSTAT_TRACTV_RESETVAL (0x00000000U)
 
 /*----TRACTV Tokens----*/
-#define EDMA3_CCRL_CCSTAT_TRACTV_NONE    (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_TRACTV_ACTIVE  (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_TRACTV_NONE    (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_TRACTV_ACTIVE  (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_QEVTACTV_MASK  (0x00000002u)
-#define EDMA3_CCRL_CCSTAT_QEVTACTV_SHIFT (0x00000001u)
-#define EDMA3_CCRL_CCSTAT_QEVTACTV_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_QEVTACTV_MASK  (0x00000002U)
+#define EDMA3_CCRL_CCSTAT_QEVTACTV_SHIFT (0x00000001U)
+#define EDMA3_CCRL_CCSTAT_QEVTACTV_RESETVAL (0x00000000U)
 
 /*----QEVTACTV Tokens----*/
-#define EDMA3_CCRL_CCSTAT_QEVTACTV_NONE  (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_QEVTACTV_ACTIVE (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_QEVTACTV_NONE  (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_QEVTACTV_ACTIVE (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_EVTACTV_MASK   (0x00000001u)
-#define EDMA3_CCRL_CCSTAT_EVTACTV_SHIFT  (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_EVTACTV_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_EVTACTV_MASK   (0x00000001U)
+#define EDMA3_CCRL_CCSTAT_EVTACTV_SHIFT  (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_EVTACTV_RESETVAL (0x00000000U)
 
 /*----EVTACTV Tokens----*/
-#define EDMA3_CCRL_CCSTAT_EVTACTV_NONE   (0x00000000u)
-#define EDMA3_CCRL_CCSTAT_EVTACTV_ACTIVE (0x00000001u)
+#define EDMA3_CCRL_CCSTAT_EVTACTV_NONE   (0x00000000U)
+#define EDMA3_CCRL_CCSTAT_EVTACTV_ACTIVE (0x00000001U)
 
-#define EDMA3_CCRL_CCSTAT_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CCSTAT_RESETVAL       (0x00000000U)
 
 /* AETCTL */
 
-#define EDMA3_CCRL_AETCTL_EN_MASK        (0x80000000u)
-#define EDMA3_CCRL_AETCTL_EN_SHIFT       (0x0000001Fu)
-#define EDMA3_CCRL_AETCTL_EN_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_AETCTL_EN_MASK        (0x80000000U)
+#define EDMA3_CCRL_AETCTL_EN_SHIFT       (0x0000001FU)
+#define EDMA3_CCRL_AETCTL_EN_RESETVAL    (0x00000000U)
 
 /*----EN Tokens----*/
-#define EDMA3_CCRL_AETCTL_EN_DISABLE     (0x00000000u)
-#define EDMA3_CCRL_AETCTL_EN_ENABLE      (0x00000001u)
+#define EDMA3_CCRL_AETCTL_EN_DISABLE     (0x00000000U)
+#define EDMA3_CCRL_AETCTL_EN_ENABLE      (0x00000001U)
 
-#define EDMA3_CCRL_AETCTL_ENDINT_MASK    (0x00003F00u)
-#define EDMA3_CCRL_AETCTL_ENDINT_SHIFT   (0x00000008u)
-#define EDMA3_CCRL_AETCTL_ENDINT_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_AETCTL_ENDINT_MASK    (0x00003F00U)
+#define EDMA3_CCRL_AETCTL_ENDINT_SHIFT   (0x00000008U)
+#define EDMA3_CCRL_AETCTL_ENDINT_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_AETCTL_TYPE_MASK      (0x00000040u)
-#define EDMA3_CCRL_AETCTL_TYPE_SHIFT     (0x00000006u)
-#define EDMA3_CCRL_AETCTL_TYPE_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_AETCTL_TYPE_MASK      (0x00000040U)
+#define EDMA3_CCRL_AETCTL_TYPE_SHIFT     (0x00000006U)
+#define EDMA3_CCRL_AETCTL_TYPE_RESETVAL  (0x00000000U)
 
 /*----TYPE Tokens----*/
-#define EDMA3_CCRL_AETCTL_TYPE_DMA       (0x00000000u)
-#define EDMA3_CCRL_AETCTL_TYPE_QDMA      (0x00000001u)
+#define EDMA3_CCRL_AETCTL_TYPE_DMA       (0x00000000U)
+#define EDMA3_CCRL_AETCTL_TYPE_QDMA      (0x00000001U)
 
-#define EDMA3_CCRL_AETCTL_STRTEVT_MASK   (0x0000003Fu)
-#define EDMA3_CCRL_AETCTL_STRTEVT_SHIFT  (0x00000000u)
-#define EDMA3_CCRL_AETCTL_STRTEVT_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_AETCTL_STRTEVT_MASK   (0x0000003FU)
+#define EDMA3_CCRL_AETCTL_STRTEVT_SHIFT  (0x00000000U)
+#define EDMA3_CCRL_AETCTL_STRTEVT_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_AETCTL_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_AETCTL_RESETVAL       (0x00000000U)
 
 /* AETSTAT */
 
-#define EDMA3_CCRL_AETSTAT_STAT_MASK     (0x00000001u)
-#define EDMA3_CCRL_AETSTAT_STAT_SHIFT    (0x00000000u)
-#define EDMA3_CCRL_AETSTAT_STAT_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_AETSTAT_STAT_MASK     (0x00000001U)
+#define EDMA3_CCRL_AETSTAT_STAT_SHIFT    (0x00000000U)
+#define EDMA3_CCRL_AETSTAT_STAT_RESETVAL (0x00000000U)
 
 /*----STAT Tokens----*/
-#define EDMA3_CCRL_AETSTAT_STAT_LOW      (0x00000000u)
-#define EDMA3_CCRL_AETSTAT_STAT_HIGH     (0x00000001u)
+#define EDMA3_CCRL_AETSTAT_STAT_LOW      (0x00000000U)
+#define EDMA3_CCRL_AETSTAT_STAT_HIGH     (0x00000001U)
 
-#define EDMA3_CCRL_AETSTAT_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_AETSTAT_RESETVAL      (0x00000000U)
 
 /* AETCMD */
 
-#define EDMA3_CCRL_AETCMD_CLR_MASK       (0x00000001u)
-#define EDMA3_CCRL_AETCMD_CLR_SHIFT      (0x00000000u)
-#define EDMA3_CCRL_AETCMD_CLR_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_AETCMD_CLR_MASK       (0x00000001U)
+#define EDMA3_CCRL_AETCMD_CLR_SHIFT      (0x00000000U)
+#define EDMA3_CCRL_AETCMD_CLR_RESETVAL   (0x00000000U)
 
 /*----CLR Tokens----*/
-#define EDMA3_CCRL_AETCMD_CLR_CLEAR      (0x00000001u)
+#define EDMA3_CCRL_AETCMD_CLR_CLEAR      (0x00000001U)
 
-#define EDMA3_CCRL_AETCMD_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_AETCMD_RESETVAL       (0x00000000U)
 
 /* MPFAR */
 
-#define EDMA3_CCRL_MPFAR_FADDR_MASK      (0xFFFFFFFFu)
-#define EDMA3_CCRL_MPFAR_FADDR_SHIFT     (0x00000000u)
-#define EDMA3_CCRL_MPFAR_FADDR_RESETVAL  (0x00000000u)
+#define EDMA3_CCRL_MPFAR_FADDR_MASK      (0xFFFFFFFFU)
+#define EDMA3_CCRL_MPFAR_FADDR_SHIFT     (0x00000000U)
+#define EDMA3_CCRL_MPFAR_FADDR_RESETVAL  (0x00000000U)
 
-#define EDMA3_CCRL_MPFAR_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_MPFAR_RESETVAL        (0x00000000U)
 
 /* MPFSR */
 
-#define EDMA3_CCRL_MPFSR_FID_MASK        (0x00001E00u)
-#define EDMA3_CCRL_MPFSR_FID_SHIFT       (0x00000009u)
-#define EDMA3_CCRL_MPFSR_FID_RESETVAL    (0x00000009u)
+#define EDMA3_CCRL_MPFSR_FID_MASK        (0x00001E00U)
+#define EDMA3_CCRL_MPFSR_FID_SHIFT       (0x00000009U)
+#define EDMA3_CCRL_MPFSR_FID_RESETVAL    (0x00000009U)
 
-#define EDMA3_CCRL_MPFSR_SECE_MASK       (0x00000080u)
-#define EDMA3_CCRL_MPFSR_SECE_SHIFT      (0x00000007u)
-#define EDMA3_CCRL_MPFSR_SECE_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPFSR_SECE_MASK       (0x00000080U)
+#define EDMA3_CCRL_MPFSR_SECE_SHIFT      (0x00000007U)
+#define EDMA3_CCRL_MPFSR_SECE_RESETVAL   (0x00000000U)
 
-#define EDMA3_CCRL_MPFSR_SRE_MASK        (0x00000020u)
-#define EDMA3_CCRL_MPFSR_SRE_SHIFT       (0x00000005u)
-#define EDMA3_CCRL_MPFSR_SRE_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPFSR_SRE_MASK        (0x00000020U)
+#define EDMA3_CCRL_MPFSR_SRE_SHIFT       (0x00000005U)
+#define EDMA3_CCRL_MPFSR_SRE_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_MPFSR_SWE_MASK        (0x00000010u)
-#define EDMA3_CCRL_MPFSR_SWE_SHIFT       (0x00000004u)
-#define EDMA3_CCRL_MPFSR_SWE_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPFSR_SWE_MASK        (0x00000010U)
+#define EDMA3_CCRL_MPFSR_SWE_SHIFT       (0x00000004U)
+#define EDMA3_CCRL_MPFSR_SWE_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_MPFSR_SXE_MASK        (0x00000008u)
-#define EDMA3_CCRL_MPFSR_SXE_SHIFT       (0x00000003u)
-#define EDMA3_CCRL_MPFSR_SXE_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPFSR_SXE_MASK        (0x00000008U)
+#define EDMA3_CCRL_MPFSR_SXE_SHIFT       (0x00000003U)
+#define EDMA3_CCRL_MPFSR_SXE_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_MPFSR_URE_MASK        (0x00000004u)
-#define EDMA3_CCRL_MPFSR_URE_SHIFT       (0x00000002u)
-#define EDMA3_CCRL_MPFSR_URE_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPFSR_URE_MASK        (0x00000004U)
+#define EDMA3_CCRL_MPFSR_URE_SHIFT       (0x00000002U)
+#define EDMA3_CCRL_MPFSR_URE_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_MPFSR_UWE_MASK        (0x00000002u)
-#define EDMA3_CCRL_MPFSR_UWE_SHIFT       (0x00000001u)
-#define EDMA3_CCRL_MPFSR_UWE_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPFSR_UWE_MASK        (0x00000002U)
+#define EDMA3_CCRL_MPFSR_UWE_SHIFT       (0x00000001U)
+#define EDMA3_CCRL_MPFSR_UWE_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_MPFSR_UXE_MASK        (0x00000001u)
-#define EDMA3_CCRL_MPFSR_UXE_SHIFT       (0x00000000u)
-#define EDMA3_CCRL_MPFSR_UXE_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPFSR_UXE_MASK        (0x00000001U)
+#define EDMA3_CCRL_MPFSR_UXE_SHIFT       (0x00000000U)
+#define EDMA3_CCRL_MPFSR_UXE_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_MPFSR_RESETVAL        (0x00001200u)
+#define EDMA3_CCRL_MPFSR_RESETVAL        (0x00001200U)
 
 /* MPFCR */
 
-#define EDMA3_CCRL_MPFCR_MPFCLR_MASK     (0x00000001u)
-#define EDMA3_CCRL_MPFCR_MPFCLR_SHIFT    (0x00000000u)
-#define EDMA3_CCRL_MPFCR_MPFCLR_RESETVAL (0x00000000u)
+#define EDMA3_CCRL_MPFCR_MPFCLR_MASK     (0x00000001U)
+#define EDMA3_CCRL_MPFCR_MPFCLR_SHIFT    (0x00000000U)
+#define EDMA3_CCRL_MPFCR_MPFCLR_RESETVAL (0x00000000U)
 
-#define EDMA3_CCRL_MPFCR_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_MPFCR_RESETVAL        (0x00000000U)
 
 /* MPPAG */
 
-#define EDMA3_CCRL_MPPAG_AID5_MASK       (0x00008000u)
-#define EDMA3_CCRL_MPPAG_AID5_SHIFT      (0x0000000Fu)
-#define EDMA3_CCRL_MPPAG_AID5_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID5_MASK       (0x00008000U)
+#define EDMA3_CCRL_MPPAG_AID5_SHIFT      (0x0000000FU)
+#define EDMA3_CCRL_MPPAG_AID5_RESETVAL   (0x00000000U)
 
 /*----AID5 Tokens----*/
-#define EDMA3_CCRL_MPPAG_AID5_BLOCK      (0x00000000u)
-#define EDMA3_CCRL_MPPAG_AID5_PERMIT     (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID5_BLOCK      (0x00000000U)
+#define EDMA3_CCRL_MPPAG_AID5_PERMIT     (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_AID4_MASK       (0x00004000u)
-#define EDMA3_CCRL_MPPAG_AID4_SHIFT      (0x0000000Eu)
-#define EDMA3_CCRL_MPPAG_AID4_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID4_MASK       (0x00004000U)
+#define EDMA3_CCRL_MPPAG_AID4_SHIFT      (0x0000000EU)
+#define EDMA3_CCRL_MPPAG_AID4_RESETVAL   (0x00000000U)
 
 /*----AID4 Tokens----*/
-#define EDMA3_CCRL_MPPAG_AID4_BLOCK      (0x00000000u)
-#define EDMA3_CCRL_MPPAG_AID4_PERMIT     (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID4_BLOCK      (0x00000000U)
+#define EDMA3_CCRL_MPPAG_AID4_PERMIT     (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_AID3_MASK       (0x00002000u)
-#define EDMA3_CCRL_MPPAG_AID3_SHIFT      (0x0000000Du)
-#define EDMA3_CCRL_MPPAG_AID3_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID3_MASK       (0x00002000U)
+#define EDMA3_CCRL_MPPAG_AID3_SHIFT      (0x0000000DU)
+#define EDMA3_CCRL_MPPAG_AID3_RESETVAL   (0x00000000U)
 
 /*----AID3 Tokens----*/
-#define EDMA3_CCRL_MPPAG_AID3_BLOCK      (0x00000000u)
-#define EDMA3_CCRL_MPPAG_AID3_PERMIT     (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID3_BLOCK      (0x00000000U)
+#define EDMA3_CCRL_MPPAG_AID3_PERMIT     (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_AID2_MASK       (0x00001000u)
-#define EDMA3_CCRL_MPPAG_AID2_SHIFT      (0x0000000Cu)
-#define EDMA3_CCRL_MPPAG_AID2_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID2_MASK       (0x00001000U)
+#define EDMA3_CCRL_MPPAG_AID2_SHIFT      (0x0000000CU)
+#define EDMA3_CCRL_MPPAG_AID2_RESETVAL   (0x00000000U)
 
 /*----AID2 Tokens----*/
-#define EDMA3_CCRL_MPPAG_AID2_BLOCK      (0x00000000u)
-#define EDMA3_CCRL_MPPAG_AID2_PERMIT     (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID2_BLOCK      (0x00000000U)
+#define EDMA3_CCRL_MPPAG_AID2_PERMIT     (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_AID1_MASK       (0x00000800u)
-#define EDMA3_CCRL_MPPAG_AID1_SHIFT      (0x0000000Bu)
-#define EDMA3_CCRL_MPPAG_AID1_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID1_MASK       (0x00000800U)
+#define EDMA3_CCRL_MPPAG_AID1_SHIFT      (0x0000000BU)
+#define EDMA3_CCRL_MPPAG_AID1_RESETVAL   (0x00000000U)
 
 /*----AID1 Tokens----*/
-#define EDMA3_CCRL_MPPAG_AID1_BLOCK      (0x00000000u)
-#define EDMA3_CCRL_MPPAG_AID1_PERMIT     (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID1_BLOCK      (0x00000000U)
+#define EDMA3_CCRL_MPPAG_AID1_PERMIT     (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_AID0_MASK       (0x00000400u)
-#define EDMA3_CCRL_MPPAG_AID0_SHIFT      (0x0000000Au)
-#define EDMA3_CCRL_MPPAG_AID0_RESETVAL   (0x00000000u)
+#define EDMA3_CCRL_MPPAG_AID0_MASK       (0x00000400U)
+#define EDMA3_CCRL_MPPAG_AID0_SHIFT      (0x0000000AU)
+#define EDMA3_CCRL_MPPAG_AID0_RESETVAL   (0x00000000U)
 
 /*----AID0 Tokens----*/
-#define EDMA3_CCRL_MPPAG_AID0_BLOCK      (0x00000000u)
-#define EDMA3_CCRL_MPPAG_AID0_PERMIT     (0x00000001u)
+#define EDMA3_CCRL_MPPAG_AID0_BLOCK      (0x00000000U)
+#define EDMA3_CCRL_MPPAG_AID0_PERMIT     (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_EXT_MASK        (0x00000200u)
-#define EDMA3_CCRL_MPPAG_EXT_SHIFT       (0x00000009u)
-#define EDMA3_CCRL_MPPAG_EXT_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPPAG_EXT_MASK        (0x00000200U)
+#define EDMA3_CCRL_MPPAG_EXT_SHIFT       (0x00000009U)
+#define EDMA3_CCRL_MPPAG_EXT_RESETVAL    (0x00000000U)
 
 /*----EXT Tokens----*/
-#define EDMA3_CCRL_MPPAG_EXT_BLOCK       (0x00000000u)
-#define EDMA3_CCRL_MPPAG_EXT_PERMIT      (0x00000001u)
+#define EDMA3_CCRL_MPPAG_EXT_BLOCK       (0x00000000U)
+#define EDMA3_CCRL_MPPAG_EXT_PERMIT      (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_LCL_MASK        (0x00000100u)
-#define EDMA3_CCRL_MPPAG_LCL_SHIFT       (0x00000008u)
-#define EDMA3_CCRL_MPPAG_LCL_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPPAG_LCL_MASK        (0x00000100U)
+#define EDMA3_CCRL_MPPAG_LCL_SHIFT       (0x00000008U)
+#define EDMA3_CCRL_MPPAG_LCL_RESETVAL    (0x00000000U)
 
-#define EDMA3_CCRL_MPPAG_NS_MASK         (0x00000080u)
-#define EDMA3_CCRL_MPPAG_NS_SHIFT        (0x00000007u)
-#define EDMA3_CCRL_MPPAG_NS_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_MPPAG_NS_MASK         (0x00000080U)
+#define EDMA3_CCRL_MPPAG_NS_SHIFT        (0x00000007U)
+#define EDMA3_CCRL_MPPAG_NS_RESETVAL     (0x00000000U)
 
 /*----NS Tokens----*/
-#define EDMA3_CCRL_MPPAG_NS_SECURE       (0x00000000u)
-#define EDMA3_CCRL_MPPAG_NS_NONSECURE    (0x00000001u)
+#define EDMA3_CCRL_MPPAG_NS_SECURE       (0x00000000U)
+#define EDMA3_CCRL_MPPAG_NS_NONSECURE    (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_EMU_MASK        (0x00000040u)
-#define EDMA3_CCRL_MPPAG_EMU_SHIFT       (0x00000006u)
-#define EDMA3_CCRL_MPPAG_EMU_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPPAG_EMU_MASK        (0x00000040U)
+#define EDMA3_CCRL_MPPAG_EMU_SHIFT       (0x00000006U)
+#define EDMA3_CCRL_MPPAG_EMU_RESETVAL    (0x00000000U)
 
 /*----EMU Tokens----*/
-#define EDMA3_CCRL_MPPAG_EMU_BLOCK       (0x00000000u)
-#define EDMA3_CCRL_MPPAG_EMU_PERMIT      (0x00000001u)
+#define EDMA3_CCRL_MPPAG_EMU_BLOCK       (0x00000000U)
+#define EDMA3_CCRL_MPPAG_EMU_PERMIT      (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_SR_MASK         (0x00000020u)
-#define EDMA3_CCRL_MPPAG_SR_SHIFT        (0x00000005u)
-#define EDMA3_CCRL_MPPAG_SR_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_MPPAG_SR_MASK         (0x00000020U)
+#define EDMA3_CCRL_MPPAG_SR_SHIFT        (0x00000005U)
+#define EDMA3_CCRL_MPPAG_SR_RESETVAL     (0x00000000U)
 
 /*----SR Tokens----*/
-#define EDMA3_CCRL_MPPAG_SR_BLOCK        (0x00000000u)
-#define EDMA3_CCRL_MPPAG_SR_PERMIT       (0x00000001u)
+#define EDMA3_CCRL_MPPAG_SR_BLOCK        (0x00000000U)
+#define EDMA3_CCRL_MPPAG_SR_PERMIT       (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_SW_MASK         (0x00000010u)
-#define EDMA3_CCRL_MPPAG_SW_SHIFT        (0x00000004u)
-#define EDMA3_CCRL_MPPAG_SW_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_MPPAG_SW_MASK         (0x00000010U)
+#define EDMA3_CCRL_MPPAG_SW_SHIFT        (0x00000004U)
+#define EDMA3_CCRL_MPPAG_SW_RESETVAL     (0x00000000U)
 
 /*----SW Tokens----*/
-#define EDMA3_CCRL_MPPAG_SW_BLOCK        (0x00000000u)
-#define EDMA3_CCRL_MPPAG_SW_PERMIT       (0x00000001u)
+#define EDMA3_CCRL_MPPAG_SW_BLOCK        (0x00000000U)
+#define EDMA3_CCRL_MPPAG_SW_PERMIT       (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_SX_MASK         (0x00000008u)
-#define EDMA3_CCRL_MPPAG_SX_SHIFT        (0x00000003u)
-#define EDMA3_CCRL_MPPAG_SX_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_MPPAG_SX_MASK         (0x00000008U)
+#define EDMA3_CCRL_MPPAG_SX_SHIFT        (0x00000003U)
+#define EDMA3_CCRL_MPPAG_SX_RESETVAL     (0x00000000U)
 
 /*----SX Tokens----*/
-#define EDMA3_CCRL_MPPAG_SX_BLOCK        (0x00000000u)
-#define EDMA3_CCRL_MPPAG_SX_PERMIT       (0x00000001u)
+#define EDMA3_CCRL_MPPAG_SX_BLOCK        (0x00000000U)
+#define EDMA3_CCRL_MPPAG_SX_PERMIT       (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_UR_MASK         (0x00000004u)
-#define EDMA3_CCRL_MPPAG_UR_SHIFT        (0x00000002u)
-#define EDMA3_CCRL_MPPAG_UR_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_MPPAG_UR_MASK         (0x00000004U)
+#define EDMA3_CCRL_MPPAG_UR_SHIFT        (0x00000002U)
+#define EDMA3_CCRL_MPPAG_UR_RESETVAL     (0x00000000U)
 
 /*----UR Tokens----*/
-#define EDMA3_CCRL_MPPAG_UR_BLOCK        (0x00000000u)
-#define EDMA3_CCRL_MPPAG_UR_PERMIT       (0x00000001u)
+#define EDMA3_CCRL_MPPAG_UR_BLOCK        (0x00000000U)
+#define EDMA3_CCRL_MPPAG_UR_PERMIT       (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_UW_MASK         (0x00000002u)
-#define EDMA3_CCRL_MPPAG_UW_SHIFT        (0x00000001u)
-#define EDMA3_CCRL_MPPAG_UW_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_MPPAG_UW_MASK         (0x00000002U)
+#define EDMA3_CCRL_MPPAG_UW_SHIFT        (0x00000001U)
+#define EDMA3_CCRL_MPPAG_UW_RESETVAL     (0x00000000U)
 
 /*----UW Tokens----*/
-#define EDMA3_CCRL_MPPAG_UW_BLOCK        (0x00000000u)
-#define EDMA3_CCRL_MPPAG_UW_PERMIT       (0x00000001u)
+#define EDMA3_CCRL_MPPAG_UW_BLOCK        (0x00000000U)
+#define EDMA3_CCRL_MPPAG_UW_PERMIT       (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_UX_MASK         (0x00000001u)
-#define EDMA3_CCRL_MPPAG_UX_SHIFT        (0x00000000u)
-#define EDMA3_CCRL_MPPAG_UX_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_MPPAG_UX_MASK         (0x00000001U)
+#define EDMA3_CCRL_MPPAG_UX_SHIFT        (0x00000000U)
+#define EDMA3_CCRL_MPPAG_UX_RESETVAL     (0x00000000U)
 
 /*----UX Tokens----*/
-#define EDMA3_CCRL_MPPAG_UX_BLOCK        (0x00000000u)
-#define EDMA3_CCRL_MPPAG_UX_PERMIT       (0x00000001u)
+#define EDMA3_CCRL_MPPAG_UX_BLOCK        (0x00000000U)
+#define EDMA3_CCRL_MPPAG_UX_PERMIT       (0x00000001U)
 
-#define EDMA3_CCRL_MPPAG_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_MPPAG_RESETVAL        (0x00000000U)
 
 /* MPPA */
 
-#define EDMA3_CCRL_MPPA_AID5_MASK        (0x00008000u)
-#define EDMA3_CCRL_MPPA_AID5_SHIFT       (0x0000000Fu)
-#define EDMA3_CCRL_MPPA_AID5_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID5_MASK        (0x00008000U)
+#define EDMA3_CCRL_MPPA_AID5_SHIFT       (0x0000000FU)
+#define EDMA3_CCRL_MPPA_AID5_RESETVAL    (0x00000000U)
 
 /*----AID5 Tokens----*/
-#define EDMA3_CCRL_MPPA_AID5_BLOCK       (0x00000000u)
-#define EDMA3_CCRL_MPPA_AID5_PERMIT      (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID5_BLOCK       (0x00000000U)
+#define EDMA3_CCRL_MPPA_AID5_PERMIT      (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_AID4_MASK        (0x00004000u)
-#define EDMA3_CCRL_MPPA_AID4_SHIFT       (0x0000000Eu)
-#define EDMA3_CCRL_MPPA_AID4_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID4_MASK        (0x00004000U)
+#define EDMA3_CCRL_MPPA_AID4_SHIFT       (0x0000000EU)
+#define EDMA3_CCRL_MPPA_AID4_RESETVAL    (0x00000000U)
 
 /*----AID4 Tokens----*/
-#define EDMA3_CCRL_MPPA_AID4_BLOCK       (0x00000000u)
-#define EDMA3_CCRL_MPPA_AID4_PERMIT      (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID4_BLOCK       (0x00000000U)
+#define EDMA3_CCRL_MPPA_AID4_PERMIT      (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_AID3_MASK        (0x00002000u)
-#define EDMA3_CCRL_MPPA_AID3_SHIFT       (0x0000000Du)
-#define EDMA3_CCRL_MPPA_AID3_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID3_MASK        (0x00002000U)
+#define EDMA3_CCRL_MPPA_AID3_SHIFT       (0x0000000DU)
+#define EDMA3_CCRL_MPPA_AID3_RESETVAL    (0x00000000U)
 
 /*----AID3 Tokens----*/
-#define EDMA3_CCRL_MPPA_AID3_BLOCK       (0x00000000u)
-#define EDMA3_CCRL_MPPA_AID3_PERMIT      (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID3_BLOCK       (0x00000000U)
+#define EDMA3_CCRL_MPPA_AID3_PERMIT      (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_AID2_MASK        (0x00001000u)
-#define EDMA3_CCRL_MPPA_AID2_SHIFT       (0x0000000Cu)
-#define EDMA3_CCRL_MPPA_AID2_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID2_MASK        (0x00001000U)
+#define EDMA3_CCRL_MPPA_AID2_SHIFT       (0x0000000CU)
+#define EDMA3_CCRL_MPPA_AID2_RESETVAL    (0x00000000U)
 
 /*----AID2 Tokens----*/
-#define EDMA3_CCRL_MPPA_AID2_BLOCK       (0x00000000u)
-#define EDMA3_CCRL_MPPA_AID2_PERMIT      (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID2_BLOCK       (0x00000000U)
+#define EDMA3_CCRL_MPPA_AID2_PERMIT      (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_AID1_MASK        (0x00000800u)
-#define EDMA3_CCRL_MPPA_AID1_SHIFT       (0x0000000Bu)
-#define EDMA3_CCRL_MPPA_AID1_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID1_MASK        (0x00000800U)
+#define EDMA3_CCRL_MPPA_AID1_SHIFT       (0x0000000BU)
+#define EDMA3_CCRL_MPPA_AID1_RESETVAL    (0x00000000U)
 
 /*----AID1 Tokens----*/
-#define EDMA3_CCRL_MPPA_AID1_BLOCK       (0x00000000u)
-#define EDMA3_CCRL_MPPA_AID1_PERMIT      (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID1_BLOCK       (0x00000000U)
+#define EDMA3_CCRL_MPPA_AID1_PERMIT      (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_AID0_MASK        (0x00000400u)
-#define EDMA3_CCRL_MPPA_AID0_SHIFT       (0x0000000Au)
-#define EDMA3_CCRL_MPPA_AID0_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_MPPA_AID0_MASK        (0x00000400U)
+#define EDMA3_CCRL_MPPA_AID0_SHIFT       (0x0000000AU)
+#define EDMA3_CCRL_MPPA_AID0_RESETVAL    (0x00000000U)
 
 /*----AID0 Tokens----*/
-#define EDMA3_CCRL_MPPA_AID0_BLOCK       (0x00000000u)
-#define EDMA3_CCRL_MPPA_AID0_PERMIT      (0x00000001u)
+#define EDMA3_CCRL_MPPA_AID0_BLOCK       (0x00000000U)
+#define EDMA3_CCRL_MPPA_AID0_PERMIT      (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_EXT_MASK         (0x00000200u)
-#define EDMA3_CCRL_MPPA_EXT_SHIFT        (0x00000009u)
-#define EDMA3_CCRL_MPPA_EXT_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_MPPA_EXT_MASK         (0x00000200U)
+#define EDMA3_CCRL_MPPA_EXT_SHIFT        (0x00000009U)
+#define EDMA3_CCRL_MPPA_EXT_RESETVAL     (0x00000000U)
 
 /*----EXT Tokens----*/
-#define EDMA3_CCRL_MPPA_EXT_BLOCK        (0x00000000u)
-#define EDMA3_CCRL_MPPA_EXT_PERMIT       (0x00000001u)
+#define EDMA3_CCRL_MPPA_EXT_BLOCK        (0x00000000U)
+#define EDMA3_CCRL_MPPA_EXT_PERMIT       (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_LCL_MASK         (0x00000100u)
-#define EDMA3_CCRL_MPPA_LCL_SHIFT        (0x00000008u)
-#define EDMA3_CCRL_MPPA_LCL_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_MPPA_LCL_MASK         (0x00000100U)
+#define EDMA3_CCRL_MPPA_LCL_SHIFT        (0x00000008U)
+#define EDMA3_CCRL_MPPA_LCL_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_MPPA_NS_MASK          (0x00000080u)
-#define EDMA3_CCRL_MPPA_NS_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_MPPA_NS_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_MPPA_NS_MASK          (0x00000080U)
+#define EDMA3_CCRL_MPPA_NS_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_MPPA_NS_RESETVAL      (0x00000000U)
 
 /*----NS Tokens----*/
-#define EDMA3_CCRL_MPPA_NS_SECURE        (0x00000000u)
-#define EDMA3_CCRL_MPPA_NS_NONSECURE     (0x00000001u)
+#define EDMA3_CCRL_MPPA_NS_SECURE        (0x00000000U)
+#define EDMA3_CCRL_MPPA_NS_NONSECURE     (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_EMU_MASK         (0x00000040u)
-#define EDMA3_CCRL_MPPA_EMU_SHIFT        (0x00000006u)
-#define EDMA3_CCRL_MPPA_EMU_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_MPPA_EMU_MASK         (0x00000040U)
+#define EDMA3_CCRL_MPPA_EMU_SHIFT        (0x00000006U)
+#define EDMA3_CCRL_MPPA_EMU_RESETVAL     (0x00000000U)
 
 /*----EMU Tokens----*/
-#define EDMA3_CCRL_MPPA_EMU_BLOCK        (0x00000000u)
-#define EDMA3_CCRL_MPPA_EMU_PERMIT       (0x00000001u)
+#define EDMA3_CCRL_MPPA_EMU_BLOCK        (0x00000000U)
+#define EDMA3_CCRL_MPPA_EMU_PERMIT       (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_SR_MASK          (0x00000020u)
-#define EDMA3_CCRL_MPPA_SR_SHIFT         (0x00000005u)
-#define EDMA3_CCRL_MPPA_SR_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_MPPA_SR_MASK          (0x00000020U)
+#define EDMA3_CCRL_MPPA_SR_SHIFT         (0x00000005U)
+#define EDMA3_CCRL_MPPA_SR_RESETVAL      (0x00000000U)
 
 /*----SR Tokens----*/
-#define EDMA3_CCRL_MPPA_SR_BLOCK         (0x00000000u)
-#define EDMA3_CCRL_MPPA_SR_PERMIT        (0x00000001u)
+#define EDMA3_CCRL_MPPA_SR_BLOCK         (0x00000000U)
+#define EDMA3_CCRL_MPPA_SR_PERMIT        (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_SW_MASK          (0x00000010u)
-#define EDMA3_CCRL_MPPA_SW_SHIFT         (0x00000004u)
-#define EDMA3_CCRL_MPPA_SW_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_MPPA_SW_MASK          (0x00000010U)
+#define EDMA3_CCRL_MPPA_SW_SHIFT         (0x00000004U)
+#define EDMA3_CCRL_MPPA_SW_RESETVAL      (0x00000000U)
 
 /*----SW Tokens----*/
-#define EDMA3_CCRL_MPPA_SW_BLOCK         (0x00000000u)
-#define EDMA3_CCRL_MPPA_SW_PERMIT        (0x00000001u)
+#define EDMA3_CCRL_MPPA_SW_BLOCK         (0x00000000U)
+#define EDMA3_CCRL_MPPA_SW_PERMIT        (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_SX_MASK          (0x00000008u)
-#define EDMA3_CCRL_MPPA_SX_SHIFT         (0x00000003u)
-#define EDMA3_CCRL_MPPA_SX_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_MPPA_SX_MASK          (0x00000008U)
+#define EDMA3_CCRL_MPPA_SX_SHIFT         (0x00000003U)
+#define EDMA3_CCRL_MPPA_SX_RESETVAL      (0x00000000U)
 
 /*----SX Tokens----*/
-#define EDMA3_CCRL_MPPA_SX_BLOCK         (0x00000000u)
-#define EDMA3_CCRL_MPPA_SX_PERMIT        (0x00000001u)
+#define EDMA3_CCRL_MPPA_SX_BLOCK         (0x00000000U)
+#define EDMA3_CCRL_MPPA_SX_PERMIT        (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_UR_MASK          (0x00000004u)
-#define EDMA3_CCRL_MPPA_UR_SHIFT         (0x00000002u)
-#define EDMA3_CCRL_MPPA_UR_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_MPPA_UR_MASK          (0x00000004U)
+#define EDMA3_CCRL_MPPA_UR_SHIFT         (0x00000002U)
+#define EDMA3_CCRL_MPPA_UR_RESETVAL      (0x00000000U)
 
 /*----UR Tokens----*/
-#define EDMA3_CCRL_MPPA_UR_BLOCK         (0x00000000u)
-#define EDMA3_CCRL_MPPA_UR_PERMIT        (0x00000001u)
+#define EDMA3_CCRL_MPPA_UR_BLOCK         (0x00000000U)
+#define EDMA3_CCRL_MPPA_UR_PERMIT        (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_UW_MASK          (0x00000002u)
-#define EDMA3_CCRL_MPPA_UW_SHIFT         (0x00000001u)
-#define EDMA3_CCRL_MPPA_UW_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_MPPA_UW_MASK          (0x00000002U)
+#define EDMA3_CCRL_MPPA_UW_SHIFT         (0x00000001U)
+#define EDMA3_CCRL_MPPA_UW_RESETVAL      (0x00000000U)
 
 /*----UW Tokens----*/
-#define EDMA3_CCRL_MPPA_UW_BLOCK         (0x00000000u)
-#define EDMA3_CCRL_MPPA_UW_PERMIT        (0x00000001u)
+#define EDMA3_CCRL_MPPA_UW_BLOCK         (0x00000000U)
+#define EDMA3_CCRL_MPPA_UW_PERMIT        (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_UX_MASK          (0x00000001u)
-#define EDMA3_CCRL_MPPA_UX_SHIFT         (0x00000000u)
-#define EDMA3_CCRL_MPPA_UX_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_MPPA_UX_MASK          (0x00000001U)
+#define EDMA3_CCRL_MPPA_UX_SHIFT         (0x00000000U)
+#define EDMA3_CCRL_MPPA_UX_RESETVAL      (0x00000000U)
 
 /*----UX Tokens----*/
-#define EDMA3_CCRL_MPPA_UX_BLOCK         (0x00000000u)
-#define EDMA3_CCRL_MPPA_UX_PERMIT        (0x00000001u)
+#define EDMA3_CCRL_MPPA_UX_BLOCK         (0x00000000U)
+#define EDMA3_CCRL_MPPA_UX_PERMIT        (0x00000001U)
 
-#define EDMA3_CCRL_MPPA_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_MPPA_RESETVAL         (0x00000000U)
 
 /* ER */
 
-#define EDMA3_CCRL_ER_E31_MASK           (0x80000000u)
-#define EDMA3_CCRL_ER_E31_SHIFT          (0x0000001Fu)
-#define EDMA3_CCRL_ER_E31_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E31_MASK           (0x80000000U)
+#define EDMA3_CCRL_ER_E31_SHIFT          (0x0000001FU)
+#define EDMA3_CCRL_ER_E31_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E30_MASK           (0x40000000u)
-#define EDMA3_CCRL_ER_E30_SHIFT          (0x0000001Eu)
-#define EDMA3_CCRL_ER_E30_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E30_MASK           (0x40000000U)
+#define EDMA3_CCRL_ER_E30_SHIFT          (0x0000001EU)
+#define EDMA3_CCRL_ER_E30_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E29_MASK           (0x20000000u)
-#define EDMA3_CCRL_ER_E29_SHIFT          (0x0000001Du)
-#define EDMA3_CCRL_ER_E29_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E29_MASK           (0x20000000U)
+#define EDMA3_CCRL_ER_E29_SHIFT          (0x0000001DU)
+#define EDMA3_CCRL_ER_E29_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E28_MASK           (0x10000000u)
-#define EDMA3_CCRL_ER_E28_SHIFT          (0x0000001Cu)
-#define EDMA3_CCRL_ER_E28_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E28_MASK           (0x10000000U)
+#define EDMA3_CCRL_ER_E28_SHIFT          (0x0000001CU)
+#define EDMA3_CCRL_ER_E28_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E27_MASK           (0x08000000u)
-#define EDMA3_CCRL_ER_E27_SHIFT          (0x0000001Bu)
-#define EDMA3_CCRL_ER_E27_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E27_MASK           (0x08000000U)
+#define EDMA3_CCRL_ER_E27_SHIFT          (0x0000001BU)
+#define EDMA3_CCRL_ER_E27_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E26_MASK           (0x04000000u)
-#define EDMA3_CCRL_ER_E26_SHIFT          (0x0000001Au)
-#define EDMA3_CCRL_ER_E26_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E26_MASK           (0x04000000U)
+#define EDMA3_CCRL_ER_E26_SHIFT          (0x0000001AU)
+#define EDMA3_CCRL_ER_E26_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E25_MASK           (0x02000000u)
-#define EDMA3_CCRL_ER_E25_SHIFT          (0x00000019u)
-#define EDMA3_CCRL_ER_E25_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E25_MASK           (0x02000000U)
+#define EDMA3_CCRL_ER_E25_SHIFT          (0x00000019U)
+#define EDMA3_CCRL_ER_E25_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E24_MASK           (0x01000000u)
-#define EDMA3_CCRL_ER_E24_SHIFT          (0x00000018u)
-#define EDMA3_CCRL_ER_E24_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E24_MASK           (0x01000000U)
+#define EDMA3_CCRL_ER_E24_SHIFT          (0x00000018U)
+#define EDMA3_CCRL_ER_E24_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E23_MASK           (0x00800000u)
-#define EDMA3_CCRL_ER_E23_SHIFT          (0x00000017u)
-#define EDMA3_CCRL_ER_E23_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E23_MASK           (0x00800000U)
+#define EDMA3_CCRL_ER_E23_SHIFT          (0x00000017U)
+#define EDMA3_CCRL_ER_E23_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E22_MASK           (0x00400000u)
-#define EDMA3_CCRL_ER_E22_SHIFT          (0x00000016u)
-#define EDMA3_CCRL_ER_E22_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E22_MASK           (0x00400000U)
+#define EDMA3_CCRL_ER_E22_SHIFT          (0x00000016U)
+#define EDMA3_CCRL_ER_E22_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E21_MASK           (0x00200000u)
-#define EDMA3_CCRL_ER_E21_SHIFT          (0x00000015u)
-#define EDMA3_CCRL_ER_E21_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E21_MASK           (0x00200000U)
+#define EDMA3_CCRL_ER_E21_SHIFT          (0x00000015U)
+#define EDMA3_CCRL_ER_E21_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E20_MASK           (0x00100000u)
-#define EDMA3_CCRL_ER_E20_SHIFT          (0x00000014u)
-#define EDMA3_CCRL_ER_E20_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E20_MASK           (0x00100000U)
+#define EDMA3_CCRL_ER_E20_SHIFT          (0x00000014U)
+#define EDMA3_CCRL_ER_E20_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E19_MASK           (0x00080000u)
-#define EDMA3_CCRL_ER_E19_SHIFT          (0x00000013u)
-#define EDMA3_CCRL_ER_E19_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E19_MASK           (0x00080000U)
+#define EDMA3_CCRL_ER_E19_SHIFT          (0x00000013U)
+#define EDMA3_CCRL_ER_E19_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E18_MASK           (0x00040000u)
-#define EDMA3_CCRL_ER_E18_SHIFT          (0x00000012u)
-#define EDMA3_CCRL_ER_E18_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E18_MASK           (0x00040000U)
+#define EDMA3_CCRL_ER_E18_SHIFT          (0x00000012U)
+#define EDMA3_CCRL_ER_E18_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E17_MASK           (0x00020000u)
-#define EDMA3_CCRL_ER_E17_SHIFT          (0x00000011u)
-#define EDMA3_CCRL_ER_E17_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E17_MASK           (0x00020000U)
+#define EDMA3_CCRL_ER_E17_SHIFT          (0x00000011U)
+#define EDMA3_CCRL_ER_E17_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E16_MASK           (0x00010000u)
-#define EDMA3_CCRL_ER_E16_SHIFT          (0x00000010u)
-#define EDMA3_CCRL_ER_E16_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E16_MASK           (0x00010000U)
+#define EDMA3_CCRL_ER_E16_SHIFT          (0x00000010U)
+#define EDMA3_CCRL_ER_E16_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E15_MASK           (0x00008000u)
-#define EDMA3_CCRL_ER_E15_SHIFT          (0x0000000Fu)
-#define EDMA3_CCRL_ER_E15_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E15_MASK           (0x00008000U)
+#define EDMA3_CCRL_ER_E15_SHIFT          (0x0000000FU)
+#define EDMA3_CCRL_ER_E15_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E14_MASK           (0x00004000u)
-#define EDMA3_CCRL_ER_E14_SHIFT          (0x0000000Eu)
-#define EDMA3_CCRL_ER_E14_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E14_MASK           (0x00004000U)
+#define EDMA3_CCRL_ER_E14_SHIFT          (0x0000000EU)
+#define EDMA3_CCRL_ER_E14_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E13_MASK           (0x00002000u)
-#define EDMA3_CCRL_ER_E13_SHIFT          (0x0000000Du)
-#define EDMA3_CCRL_ER_E13_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E13_MASK           (0x00002000U)
+#define EDMA3_CCRL_ER_E13_SHIFT          (0x0000000DU)
+#define EDMA3_CCRL_ER_E13_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E12_MASK           (0x00001000u)
-#define EDMA3_CCRL_ER_E12_SHIFT          (0x0000000Cu)
-#define EDMA3_CCRL_ER_E12_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E12_MASK           (0x00001000U)
+#define EDMA3_CCRL_ER_E12_SHIFT          (0x0000000CU)
+#define EDMA3_CCRL_ER_E12_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E11_MASK           (0x00000800u)
-#define EDMA3_CCRL_ER_E11_SHIFT          (0x0000000Bu)
-#define EDMA3_CCRL_ER_E11_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E11_MASK           (0x00000800U)
+#define EDMA3_CCRL_ER_E11_SHIFT          (0x0000000BU)
+#define EDMA3_CCRL_ER_E11_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E10_MASK           (0x00000400u)
-#define EDMA3_CCRL_ER_E10_SHIFT          (0x0000000Au)
-#define EDMA3_CCRL_ER_E10_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ER_E10_MASK           (0x00000400U)
+#define EDMA3_CCRL_ER_E10_SHIFT          (0x0000000AU)
+#define EDMA3_CCRL_ER_E10_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_ER_E9_MASK            (0x00000200u)
-#define EDMA3_CCRL_ER_E9_SHIFT           (0x00000009u)
-#define EDMA3_CCRL_ER_E9_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_ER_E9_MASK            (0x00000200U)
+#define EDMA3_CCRL_ER_E9_SHIFT           (0x00000009U)
+#define EDMA3_CCRL_ER_E9_RESETVAL        (0x00000000U)
 
-#define EDMA3_CCRL_ER_E8_MASK            (0x00000100u)
-#define EDMA3_CCRL_ER_E8_SHIFT           (0x00000008u)
-#define EDMA3_CCRL_ER_E8_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_ER_E8_MASK            (0x00000100U)
+#define EDMA3_CCRL_ER_E8_SHIFT           (0x00000008U)
+#define EDMA3_CCRL_ER_E8_RESETVAL        (0x00000000U)
 
-#define EDMA3_CCRL_ER_E7_MASK            (0x00000080u)
-#define EDMA3_CCRL_ER_E7_SHIFT           (0x00000007u)
-#define EDMA3_CCRL_ER_E7_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_ER_E7_MASK            (0x00000080U)
+#define EDMA3_CCRL_ER_E7_SHIFT           (0x00000007U)
+#define EDMA3_CCRL_ER_E7_RESETVAL        (0x00000000U)
 
-#define EDMA3_CCRL_ER_E6_MASK            (0x00000040u)
-#define EDMA3_CCRL_ER_E6_SHIFT           (0x00000006u)
-#define EDMA3_CCRL_ER_E6_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_ER_E6_MASK            (0x00000040U)
+#define EDMA3_CCRL_ER_E6_SHIFT           (0x00000006U)
+#define EDMA3_CCRL_ER_E6_RESETVAL        (0x00000000U)
 
-#define EDMA3_CCRL_ER_E5_MASK            (0x00000020u)
-#define EDMA3_CCRL_ER_E5_SHIFT           (0x00000005u)
-#define EDMA3_CCRL_ER_E5_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_ER_E5_MASK            (0x00000020U)
+#define EDMA3_CCRL_ER_E5_SHIFT           (0x00000005U)
+#define EDMA3_CCRL_ER_E5_RESETVAL        (0x00000000U)
 
-#define EDMA3_CCRL_ER_E4_MASK            (0x00000010u)
-#define EDMA3_CCRL_ER_E4_SHIFT           (0x00000004u)
-#define EDMA3_CCRL_ER_E4_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_ER_E4_MASK            (0x00000010U)
+#define EDMA3_CCRL_ER_E4_SHIFT           (0x00000004U)
+#define EDMA3_CCRL_ER_E4_RESETVAL        (0x00000000U)
 
-#define EDMA3_CCRL_ER_E3_MASK            (0x00000008u)
-#define EDMA3_CCRL_ER_E3_SHIFT           (0x00000003u)
-#define EDMA3_CCRL_ER_E3_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_ER_E3_MASK            (0x00000008U)
+#define EDMA3_CCRL_ER_E3_SHIFT           (0x00000003U)
+#define EDMA3_CCRL_ER_E3_RESETVAL        (0x00000000U)
 
-#define EDMA3_CCRL_ER_E2_MASK            (0x00000004u)
-#define EDMA3_CCRL_ER_E2_SHIFT           (0x00000002u)
-#define EDMA3_CCRL_ER_E2_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_ER_E2_MASK            (0x00000004U)
+#define EDMA3_CCRL_ER_E2_SHIFT           (0x00000002U)
+#define EDMA3_CCRL_ER_E2_RESETVAL        (0x00000000U)
 
-#define EDMA3_CCRL_ER_E1_MASK            (0x00000002u)
-#define EDMA3_CCRL_ER_E1_SHIFT           (0x00000001u)
-#define EDMA3_CCRL_ER_E1_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_ER_E1_MASK            (0x00000002U)
+#define EDMA3_CCRL_ER_E1_SHIFT           (0x00000001U)
+#define EDMA3_CCRL_ER_E1_RESETVAL        (0x00000000U)
 
-#define EDMA3_CCRL_ER_E0_MASK            (0x00000001u)
-#define EDMA3_CCRL_ER_E0_SHIFT           (0x00000000u)
-#define EDMA3_CCRL_ER_E0_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_ER_E0_MASK            (0x00000001U)
+#define EDMA3_CCRL_ER_E0_SHIFT           (0x00000000U)
+#define EDMA3_CCRL_ER_E0_RESETVAL        (0x00000000U)
 
-#define EDMA3_CCRL_ER_RESETVAL           (0x00000000u)
+#define EDMA3_CCRL_ER_RESETVAL           (0x00000000U)
 
 /* ERH */
 
-#define EDMA3_CCRL_ERH_E63_MASK          (0x80000000u)
-#define EDMA3_CCRL_ERH_E63_SHIFT         (0x0000001Fu)
-#define EDMA3_CCRL_ERH_E63_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E63_MASK          (0x80000000U)
+#define EDMA3_CCRL_ERH_E63_SHIFT         (0x0000001FU)
+#define EDMA3_CCRL_ERH_E63_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E62_MASK          (0x40000000u)
-#define EDMA3_CCRL_ERH_E62_SHIFT         (0x0000001Eu)
-#define EDMA3_CCRL_ERH_E62_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E62_MASK          (0x40000000U)
+#define EDMA3_CCRL_ERH_E62_SHIFT         (0x0000001EU)
+#define EDMA3_CCRL_ERH_E62_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E61_MASK          (0x20000000u)
-#define EDMA3_CCRL_ERH_E61_SHIFT         (0x0000001Du)
-#define EDMA3_CCRL_ERH_E61_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E61_MASK          (0x20000000U)
+#define EDMA3_CCRL_ERH_E61_SHIFT         (0x0000001DU)
+#define EDMA3_CCRL_ERH_E61_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E60_MASK          (0x10000000u)
-#define EDMA3_CCRL_ERH_E60_SHIFT         (0x0000001Cu)
-#define EDMA3_CCRL_ERH_E60_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E60_MASK          (0x10000000U)
+#define EDMA3_CCRL_ERH_E60_SHIFT         (0x0000001CU)
+#define EDMA3_CCRL_ERH_E60_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E59_MASK          (0x08000000u)
-#define EDMA3_CCRL_ERH_E59_SHIFT         (0x0000001Bu)
-#define EDMA3_CCRL_ERH_E59_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E59_MASK          (0x08000000U)
+#define EDMA3_CCRL_ERH_E59_SHIFT         (0x0000001BU)
+#define EDMA3_CCRL_ERH_E59_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E58_MASK          (0x04000000u)
-#define EDMA3_CCRL_ERH_E58_SHIFT         (0x0000001Au)
-#define EDMA3_CCRL_ERH_E58_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E58_MASK          (0x04000000U)
+#define EDMA3_CCRL_ERH_E58_SHIFT         (0x0000001AU)
+#define EDMA3_CCRL_ERH_E58_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E57_MASK          (0x02000000u)
-#define EDMA3_CCRL_ERH_E57_SHIFT         (0x00000019u)
-#define EDMA3_CCRL_ERH_E57_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E57_MASK          (0x02000000U)
+#define EDMA3_CCRL_ERH_E57_SHIFT         (0x00000019U)
+#define EDMA3_CCRL_ERH_E57_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E56_MASK          (0x01000000u)
-#define EDMA3_CCRL_ERH_E56_SHIFT         (0x00000018u)
-#define EDMA3_CCRL_ERH_E56_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E56_MASK          (0x01000000U)
+#define EDMA3_CCRL_ERH_E56_SHIFT         (0x00000018U)
+#define EDMA3_CCRL_ERH_E56_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E55_MASK          (0x00800000u)
-#define EDMA3_CCRL_ERH_E55_SHIFT         (0x00000017u)
-#define EDMA3_CCRL_ERH_E55_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E55_MASK          (0x00800000U)
+#define EDMA3_CCRL_ERH_E55_SHIFT         (0x00000017U)
+#define EDMA3_CCRL_ERH_E55_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E54_MASK          (0x00400000u)
-#define EDMA3_CCRL_ERH_E54_SHIFT         (0x00000016u)
-#define EDMA3_CCRL_ERH_E54_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E54_MASK          (0x00400000U)
+#define EDMA3_CCRL_ERH_E54_SHIFT         (0x00000016U)
+#define EDMA3_CCRL_ERH_E54_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E53_MASK          (0x00200000u)
-#define EDMA3_CCRL_ERH_E53_SHIFT         (0x00000015u)
-#define EDMA3_CCRL_ERH_E53_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E53_MASK          (0x00200000U)
+#define EDMA3_CCRL_ERH_E53_SHIFT         (0x00000015U)
+#define EDMA3_CCRL_ERH_E53_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E52_MASK          (0x00100000u)
-#define EDMA3_CCRL_ERH_E52_SHIFT         (0x00000014u)
-#define EDMA3_CCRL_ERH_E52_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E52_MASK          (0x00100000U)
+#define EDMA3_CCRL_ERH_E52_SHIFT         (0x00000014U)
+#define EDMA3_CCRL_ERH_E52_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E51_MASK          (0x00080000u)
-#define EDMA3_CCRL_ERH_E51_SHIFT         (0x00000013u)
-#define EDMA3_CCRL_ERH_E51_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E51_MASK          (0x00080000U)
+#define EDMA3_CCRL_ERH_E51_SHIFT         (0x00000013U)
+#define EDMA3_CCRL_ERH_E51_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E50_MASK          (0x00040000u)
-#define EDMA3_CCRL_ERH_E50_SHIFT         (0x00000012u)
-#define EDMA3_CCRL_ERH_E50_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E50_MASK          (0x00040000U)
+#define EDMA3_CCRL_ERH_E50_SHIFT         (0x00000012U)
+#define EDMA3_CCRL_ERH_E50_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E49_MASK          (0x00020000u)
-#define EDMA3_CCRL_ERH_E49_SHIFT         (0x00000011u)
-#define EDMA3_CCRL_ERH_E49_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E49_MASK          (0x00020000U)
+#define EDMA3_CCRL_ERH_E49_SHIFT         (0x00000011U)
+#define EDMA3_CCRL_ERH_E49_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E48_MASK          (0x00010000u)
-#define EDMA3_CCRL_ERH_E48_SHIFT         (0x00000010u)
-#define EDMA3_CCRL_ERH_E48_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E48_MASK          (0x00010000U)
+#define EDMA3_CCRL_ERH_E48_SHIFT         (0x00000010U)
+#define EDMA3_CCRL_ERH_E48_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E47_MASK          (0x00008000u)
-#define EDMA3_CCRL_ERH_E47_SHIFT         (0x0000000Fu)
-#define EDMA3_CCRL_ERH_E47_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E47_MASK          (0x00008000U)
+#define EDMA3_CCRL_ERH_E47_SHIFT         (0x0000000FU)
+#define EDMA3_CCRL_ERH_E47_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E46_MASK          (0x00004000u)
-#define EDMA3_CCRL_ERH_E46_SHIFT         (0x0000000Eu)
-#define EDMA3_CCRL_ERH_E46_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E46_MASK          (0x00004000U)
+#define EDMA3_CCRL_ERH_E46_SHIFT         (0x0000000EU)
+#define EDMA3_CCRL_ERH_E46_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E45_MASK          (0x00002000u)
-#define EDMA3_CCRL_ERH_E45_SHIFT         (0x0000000Du)
-#define EDMA3_CCRL_ERH_E45_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E45_MASK          (0x00002000U)
+#define EDMA3_CCRL_ERH_E45_SHIFT         (0x0000000DU)
+#define EDMA3_CCRL_ERH_E45_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E44_MASK          (0x00001000u)
-#define EDMA3_CCRL_ERH_E44_SHIFT         (0x0000000Cu)
-#define EDMA3_CCRL_ERH_E44_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E44_MASK          (0x00001000U)
+#define EDMA3_CCRL_ERH_E44_SHIFT         (0x0000000CU)
+#define EDMA3_CCRL_ERH_E44_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E43_MASK          (0x00000800u)
-#define EDMA3_CCRL_ERH_E43_SHIFT         (0x0000000Bu)
-#define EDMA3_CCRL_ERH_E43_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E43_MASK          (0x00000800U)
+#define EDMA3_CCRL_ERH_E43_SHIFT         (0x0000000BU)
+#define EDMA3_CCRL_ERH_E43_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E42_MASK          (0x00000400u)
-#define EDMA3_CCRL_ERH_E42_SHIFT         (0x0000000Au)
-#define EDMA3_CCRL_ERH_E42_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E42_MASK          (0x00000400U)
+#define EDMA3_CCRL_ERH_E42_SHIFT         (0x0000000AU)
+#define EDMA3_CCRL_ERH_E42_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E41_MASK          (0x00000200u)
-#define EDMA3_CCRL_ERH_E41_SHIFT         (0x00000009u)
-#define EDMA3_CCRL_ERH_E41_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E41_MASK          (0x00000200U)
+#define EDMA3_CCRL_ERH_E41_SHIFT         (0x00000009U)
+#define EDMA3_CCRL_ERH_E41_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E40_MASK          (0x00000100u)
-#define EDMA3_CCRL_ERH_E40_SHIFT         (0x00000008u)
-#define EDMA3_CCRL_ERH_E40_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E40_MASK          (0x00000100U)
+#define EDMA3_CCRL_ERH_E40_SHIFT         (0x00000008U)
+#define EDMA3_CCRL_ERH_E40_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E39_MASK          (0x00000080u)
-#define EDMA3_CCRL_ERH_E39_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_ERH_E39_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E39_MASK          (0x00000080U)
+#define EDMA3_CCRL_ERH_E39_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_ERH_E39_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E38_MASK          (0x00000040u)
-#define EDMA3_CCRL_ERH_E38_SHIFT         (0x00000006u)
-#define EDMA3_CCRL_ERH_E38_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E38_MASK          (0x00000040U)
+#define EDMA3_CCRL_ERH_E38_SHIFT         (0x00000006U)
+#define EDMA3_CCRL_ERH_E38_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E37_MASK          (0x00000020u)
-#define EDMA3_CCRL_ERH_E37_SHIFT         (0x00000005u)
-#define EDMA3_CCRL_ERH_E37_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E37_MASK          (0x00000020U)
+#define EDMA3_CCRL_ERH_E37_SHIFT         (0x00000005U)
+#define EDMA3_CCRL_ERH_E37_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E36_MASK          (0x00000010u)
-#define EDMA3_CCRL_ERH_E36_SHIFT         (0x00000004u)
-#define EDMA3_CCRL_ERH_E36_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E36_MASK          (0x00000010U)
+#define EDMA3_CCRL_ERH_E36_SHIFT         (0x00000004U)
+#define EDMA3_CCRL_ERH_E36_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E35_MASK          (0x00000008u)
-#define EDMA3_CCRL_ERH_E35_SHIFT         (0x00000003u)
-#define EDMA3_CCRL_ERH_E35_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E35_MASK          (0x00000008U)
+#define EDMA3_CCRL_ERH_E35_SHIFT         (0x00000003U)
+#define EDMA3_CCRL_ERH_E35_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E34_MASK          (0x00000004u)
-#define EDMA3_CCRL_ERH_E34_SHIFT         (0x00000002u)
-#define EDMA3_CCRL_ERH_E34_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E34_MASK          (0x00000004U)
+#define EDMA3_CCRL_ERH_E34_SHIFT         (0x00000002U)
+#define EDMA3_CCRL_ERH_E34_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E33_MASK          (0x00000002u)
-#define EDMA3_CCRL_ERH_E33_SHIFT         (0x00000001u)
-#define EDMA3_CCRL_ERH_E33_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E33_MASK          (0x00000002U)
+#define EDMA3_CCRL_ERH_E33_SHIFT         (0x00000001U)
+#define EDMA3_CCRL_ERH_E33_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_E32_MASK          (0x00000001u)
-#define EDMA3_CCRL_ERH_E32_SHIFT         (0x00000000u)
-#define EDMA3_CCRL_ERH_E32_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ERH_E32_MASK          (0x00000001U)
+#define EDMA3_CCRL_ERH_E32_SHIFT         (0x00000000U)
+#define EDMA3_CCRL_ERH_E32_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_ERH_RESETVAL          (0x00000000u)
+#define EDMA3_CCRL_ERH_RESETVAL          (0x00000000U)
 
 /* ECR */
 
-#define EDMA3_CCRL_ECR_E31_MASK          (0x80000000u)
-#define EDMA3_CCRL_ECR_E31_SHIFT         (0x0000001Fu)
-#define EDMA3_CCRL_ECR_E31_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E31_MASK          (0x80000000U)
+#define EDMA3_CCRL_ECR_E31_SHIFT         (0x0000001FU)
+#define EDMA3_CCRL_ECR_E31_RESETVAL      (0x00000000U)
 
 /*----E31 Tokens----*/
-#define EDMA3_CCRL_ECR_E31_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E31_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E30_MASK          (0x40000000u)
-#define EDMA3_CCRL_ECR_E30_SHIFT         (0x0000001Eu)
-#define EDMA3_CCRL_ECR_E30_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E30_MASK          (0x40000000U)
+#define EDMA3_CCRL_ECR_E30_SHIFT         (0x0000001EU)
+#define EDMA3_CCRL_ECR_E30_RESETVAL      (0x00000000U)
 
 /*----E30 Tokens----*/
-#define EDMA3_CCRL_ECR_E30_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E30_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E29_MASK          (0x20000000u)
-#define EDMA3_CCRL_ECR_E29_SHIFT         (0x0000001Du)
-#define EDMA3_CCRL_ECR_E29_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E29_MASK          (0x20000000U)
+#define EDMA3_CCRL_ECR_E29_SHIFT         (0x0000001DU)
+#define EDMA3_CCRL_ECR_E29_RESETVAL      (0x00000000U)
 
 /*----E29 Tokens----*/
-#define EDMA3_CCRL_ECR_E29_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E29_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E28_MASK          (0x10000000u)
-#define EDMA3_CCRL_ECR_E28_SHIFT         (0x0000001Cu)
-#define EDMA3_CCRL_ECR_E28_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E28_MASK          (0x10000000U)
+#define EDMA3_CCRL_ECR_E28_SHIFT         (0x0000001CU)
+#define EDMA3_CCRL_ECR_E28_RESETVAL      (0x00000000U)
 
 /*----E28 Tokens----*/
-#define EDMA3_CCRL_ECR_E28_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E28_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E27_MASK          (0x08000000u)
-#define EDMA3_CCRL_ECR_E27_SHIFT         (0x0000001Bu)
-#define EDMA3_CCRL_ECR_E27_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E27_MASK          (0x08000000U)
+#define EDMA3_CCRL_ECR_E27_SHIFT         (0x0000001BU)
+#define EDMA3_CCRL_ECR_E27_RESETVAL      (0x00000000U)
 
 /*----E27 Tokens----*/
-#define EDMA3_CCRL_ECR_E27_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E27_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E26_MASK          (0x04000000u)
-#define EDMA3_CCRL_ECR_E26_SHIFT         (0x0000001Au)
-#define EDMA3_CCRL_ECR_E26_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E26_MASK          (0x04000000U)
+#define EDMA3_CCRL_ECR_E26_SHIFT         (0x0000001AU)
+#define EDMA3_CCRL_ECR_E26_RESETVAL      (0x00000000U)
 
 /*----E26 Tokens----*/
-#define EDMA3_CCRL_ECR_E26_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E26_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E25_MASK          (0x02000000u)
-#define EDMA3_CCRL_ECR_E25_SHIFT         (0x00000019u)
-#define EDMA3_CCRL_ECR_E25_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E25_MASK          (0x02000000U)
+#define EDMA3_CCRL_ECR_E25_SHIFT         (0x00000019U)
+#define EDMA3_CCRL_ECR_E25_RESETVAL      (0x00000000U)
 
 /*----E25 Tokens----*/
-#define EDMA3_CCRL_ECR_E25_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E25_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E24_MASK          (0x01000000u)
-#define EDMA3_CCRL_ECR_E24_SHIFT         (0x00000018u)
-#define EDMA3_CCRL_ECR_E24_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E24_MASK          (0x01000000U)
+#define EDMA3_CCRL_ECR_E24_SHIFT         (0x00000018U)
+#define EDMA3_CCRL_ECR_E24_RESETVAL      (0x00000000U)
 
 /*----E24 Tokens----*/
-#define EDMA3_CCRL_ECR_E24_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E24_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E23_MASK          (0x00800000u)
-#define EDMA3_CCRL_ECR_E23_SHIFT         (0x00000017u)
-#define EDMA3_CCRL_ECR_E23_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E23_MASK          (0x00800000U)
+#define EDMA3_CCRL_ECR_E23_SHIFT         (0x00000017U)
+#define EDMA3_CCRL_ECR_E23_RESETVAL      (0x00000000U)
 
 /*----E23 Tokens----*/
-#define EDMA3_CCRL_ECR_E23_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E23_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E22_MASK          (0x00400000u)
-#define EDMA3_CCRL_ECR_E22_SHIFT         (0x00000016u)
-#define EDMA3_CCRL_ECR_E22_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E22_MASK          (0x00400000U)
+#define EDMA3_CCRL_ECR_E22_SHIFT         (0x00000016U)
+#define EDMA3_CCRL_ECR_E22_RESETVAL      (0x00000000U)
 
 /*----E22 Tokens----*/
-#define EDMA3_CCRL_ECR_E22_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E22_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E21_MASK          (0x00200000u)
-#define EDMA3_CCRL_ECR_E21_SHIFT         (0x00000015u)
-#define EDMA3_CCRL_ECR_E21_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E21_MASK          (0x00200000U)
+#define EDMA3_CCRL_ECR_E21_SHIFT         (0x00000015U)
+#define EDMA3_CCRL_ECR_E21_RESETVAL      (0x00000000U)
 
 /*----E21 Tokens----*/
-#define EDMA3_CCRL_ECR_E21_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E21_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E20_MASK          (0x00100000u)
-#define EDMA3_CCRL_ECR_E20_SHIFT         (0x00000014u)
-#define EDMA3_CCRL_ECR_E20_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E20_MASK          (0x00100000U)
+#define EDMA3_CCRL_ECR_E20_SHIFT         (0x00000014U)
+#define EDMA3_CCRL_ECR_E20_RESETVAL      (0x00000000U)
 
 /*----E20 Tokens----*/
-#define EDMA3_CCRL_ECR_E20_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E20_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E19_MASK          (0x00080000u)
-#define EDMA3_CCRL_ECR_E19_SHIFT         (0x00000013u)
-#define EDMA3_CCRL_ECR_E19_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E19_MASK          (0x00080000U)
+#define EDMA3_CCRL_ECR_E19_SHIFT         (0x00000013U)
+#define EDMA3_CCRL_ECR_E19_RESETVAL      (0x00000000U)
 
 /*----E19 Tokens----*/
-#define EDMA3_CCRL_ECR_E19_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E19_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E18_MASK          (0x00040000u)
-#define EDMA3_CCRL_ECR_E18_SHIFT         (0x00000012u)
-#define EDMA3_CCRL_ECR_E18_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E18_MASK          (0x00040000U)
+#define EDMA3_CCRL_ECR_E18_SHIFT         (0x00000012U)
+#define EDMA3_CCRL_ECR_E18_RESETVAL      (0x00000000U)
 
 /*----E18 Tokens----*/
-#define EDMA3_CCRL_ECR_E18_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E18_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E17_MASK          (0x00020000u)
-#define EDMA3_CCRL_ECR_E17_SHIFT         (0x00000011u)
-#define EDMA3_CCRL_ECR_E17_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E17_MASK          (0x00020000U)
+#define EDMA3_CCRL_ECR_E17_SHIFT         (0x00000011U)
+#define EDMA3_CCRL_ECR_E17_RESETVAL      (0x00000000U)
 
 /*----E17 Tokens----*/
-#define EDMA3_CCRL_ECR_E17_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E17_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E16_MASK          (0x00010000u)
-#define EDMA3_CCRL_ECR_E16_SHIFT         (0x00000010u)
-#define EDMA3_CCRL_ECR_E16_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E16_MASK          (0x00010000U)
+#define EDMA3_CCRL_ECR_E16_SHIFT         (0x00000010U)
+#define EDMA3_CCRL_ECR_E16_RESETVAL      (0x00000000U)
 
 /*----E16 Tokens----*/
-#define EDMA3_CCRL_ECR_E16_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E16_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E15_MASK          (0x00008000u)
-#define EDMA3_CCRL_ECR_E15_SHIFT         (0x0000000Fu)
-#define EDMA3_CCRL_ECR_E15_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E15_MASK          (0x00008000U)
+#define EDMA3_CCRL_ECR_E15_SHIFT         (0x0000000FU)
+#define EDMA3_CCRL_ECR_E15_RESETVAL      (0x00000000U)
 
 /*----E15 Tokens----*/
-#define EDMA3_CCRL_ECR_E15_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E15_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E14_MASK          (0x00004000u)
-#define EDMA3_CCRL_ECR_E14_SHIFT         (0x0000000Eu)
-#define EDMA3_CCRL_ECR_E14_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E14_MASK          (0x00004000U)
+#define EDMA3_CCRL_ECR_E14_SHIFT         (0x0000000EU)
+#define EDMA3_CCRL_ECR_E14_RESETVAL      (0x00000000U)
 
 /*----E14 Tokens----*/
-#define EDMA3_CCRL_ECR_E14_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E14_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E13_MASK          (0x00002000u)
-#define EDMA3_CCRL_ECR_E13_SHIFT         (0x0000000Du)
-#define EDMA3_CCRL_ECR_E13_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E13_MASK          (0x00002000U)
+#define EDMA3_CCRL_ECR_E13_SHIFT         (0x0000000DU)
+#define EDMA3_CCRL_ECR_E13_RESETVAL      (0x00000000U)
 
 /*----E13 Tokens----*/
-#define EDMA3_CCRL_ECR_E13_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E13_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E12_MASK          (0x00001000u)
-#define EDMA3_CCRL_ECR_E12_SHIFT         (0x0000000Cu)
-#define EDMA3_CCRL_ECR_E12_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E12_MASK          (0x00001000U)
+#define EDMA3_CCRL_ECR_E12_SHIFT         (0x0000000CU)
+#define EDMA3_CCRL_ECR_E12_RESETVAL      (0x00000000U)
 
 /*----E12 Tokens----*/
-#define EDMA3_CCRL_ECR_E12_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E12_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E11_MASK          (0x00000800u)
-#define EDMA3_CCRL_ECR_E11_SHIFT         (0x0000000Bu)
-#define EDMA3_CCRL_ECR_E11_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E11_MASK          (0x00000800U)
+#define EDMA3_CCRL_ECR_E11_SHIFT         (0x0000000BU)
+#define EDMA3_CCRL_ECR_E11_RESETVAL      (0x00000000U)
 
 /*----E11 Tokens----*/
-#define EDMA3_CCRL_ECR_E11_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E11_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E10_MASK          (0x00000400u)
-#define EDMA3_CCRL_ECR_E10_SHIFT         (0x0000000Au)
-#define EDMA3_CCRL_ECR_E10_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ECR_E10_MASK          (0x00000400U)
+#define EDMA3_CCRL_ECR_E10_SHIFT         (0x0000000AU)
+#define EDMA3_CCRL_ECR_E10_RESETVAL      (0x00000000U)
 
 /*----E10 Tokens----*/
-#define EDMA3_CCRL_ECR_E10_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_ECR_E10_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E9_MASK           (0x00000200u)
-#define EDMA3_CCRL_ECR_E9_SHIFT          (0x00000009u)
-#define EDMA3_CCRL_ECR_E9_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ECR_E9_MASK           (0x00000200U)
+#define EDMA3_CCRL_ECR_E9_SHIFT          (0x00000009U)
+#define EDMA3_CCRL_ECR_E9_RESETVAL       (0x00000000U)
 
 /*----E9 Tokens----*/
-#define EDMA3_CCRL_ECR_E9_CLEAR          (0x00000001u)
+#define EDMA3_CCRL_ECR_E9_CLEAR          (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E8_MASK           (0x00000100u)
-#define EDMA3_CCRL_ECR_E8_SHIFT          (0x00000008u)
-#define EDMA3_CCRL_ECR_E8_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ECR_E8_MASK           (0x00000100U)
+#define EDMA3_CCRL_ECR_E8_SHIFT          (0x00000008U)
+#define EDMA3_CCRL_ECR_E8_RESETVAL       (0x00000000U)
 
 /*----E8 Tokens----*/
-#define EDMA3_CCRL_ECR_E8_CLEAR          (0x00000001u)
+#define EDMA3_CCRL_ECR_E8_CLEAR          (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E7_MASK           (0x00000080u)
-#define EDMA3_CCRL_ECR_E7_SHIFT          (0x00000007u)
-#define EDMA3_CCRL_ECR_E7_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ECR_E7_MASK           (0x00000080U)
+#define EDMA3_CCRL_ECR_E7_SHIFT          (0x00000007U)
+#define EDMA3_CCRL_ECR_E7_RESETVAL       (0x00000000U)
 
 /*----E7 Tokens----*/
-#define EDMA3_CCRL_ECR_E7_CLEAR          (0x00000001u)
+#define EDMA3_CCRL_ECR_E7_CLEAR          (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E6_MASK           (0x00000040u)
-#define EDMA3_CCRL_ECR_E6_SHIFT          (0x00000006u)
-#define EDMA3_CCRL_ECR_E6_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ECR_E6_MASK           (0x00000040U)
+#define EDMA3_CCRL_ECR_E6_SHIFT          (0x00000006U)
+#define EDMA3_CCRL_ECR_E6_RESETVAL       (0x00000000U)
 
 /*----E6 Tokens----*/
-#define EDMA3_CCRL_ECR_E6_CLEAR          (0x00000001u)
+#define EDMA3_CCRL_ECR_E6_CLEAR          (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E5_MASK           (0x00000020u)
-#define EDMA3_CCRL_ECR_E5_SHIFT          (0x00000005u)
-#define EDMA3_CCRL_ECR_E5_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ECR_E5_MASK           (0x00000020U)
+#define EDMA3_CCRL_ECR_E5_SHIFT          (0x00000005U)
+#define EDMA3_CCRL_ECR_E5_RESETVAL       (0x00000000U)
 
 /*----E5 Tokens----*/
-#define EDMA3_CCRL_ECR_E5_CLEAR          (0x00000001u)
+#define EDMA3_CCRL_ECR_E5_CLEAR          (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E4_MASK           (0x00000010u)
-#define EDMA3_CCRL_ECR_E4_SHIFT          (0x00000004u)
-#define EDMA3_CCRL_ECR_E4_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ECR_E4_MASK           (0x00000010U)
+#define EDMA3_CCRL_ECR_E4_SHIFT          (0x00000004U)
+#define EDMA3_CCRL_ECR_E4_RESETVAL       (0x00000000U)
 
 /*----E4 Tokens----*/
-#define EDMA3_CCRL_ECR_E4_CLEAR          (0x00000001u)
+#define EDMA3_CCRL_ECR_E4_CLEAR          (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E3_MASK           (0x00000008u)
-#define EDMA3_CCRL_ECR_E3_SHIFT          (0x00000003u)
-#define EDMA3_CCRL_ECR_E3_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ECR_E3_MASK           (0x00000008U)
+#define EDMA3_CCRL_ECR_E3_SHIFT          (0x00000003U)
+#define EDMA3_CCRL_ECR_E3_RESETVAL       (0x00000000U)
 
 /*----E3 Tokens----*/
-#define EDMA3_CCRL_ECR_E3_CLEAR          (0x00000001u)
+#define EDMA3_CCRL_ECR_E3_CLEAR          (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E2_MASK           (0x00000004u)
-#define EDMA3_CCRL_ECR_E2_SHIFT          (0x00000002u)
-#define EDMA3_CCRL_ECR_E2_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ECR_E2_MASK           (0x00000004U)
+#define EDMA3_CCRL_ECR_E2_SHIFT          (0x00000002U)
+#define EDMA3_CCRL_ECR_E2_RESETVAL       (0x00000000U)
 
 /*----E2 Tokens----*/
-#define EDMA3_CCRL_ECR_E2_CLEAR          (0x00000001u)
+#define EDMA3_CCRL_ECR_E2_CLEAR          (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E1_MASK           (0x00000002u)
-#define EDMA3_CCRL_ECR_E1_SHIFT          (0x00000001u)
-#define EDMA3_CCRL_ECR_E1_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ECR_E1_MASK           (0x00000002U)
+#define EDMA3_CCRL_ECR_E1_SHIFT          (0x00000001U)
+#define EDMA3_CCRL_ECR_E1_RESETVAL       (0x00000000U)
 
 /*----E1 Tokens----*/
-#define EDMA3_CCRL_ECR_E1_CLEAR          (0x00000001u)
+#define EDMA3_CCRL_ECR_E1_CLEAR          (0x00000001U)
 
-#define EDMA3_CCRL_ECR_E0_MASK           (0x00000001u)
-#define EDMA3_CCRL_ECR_E0_SHIFT          (0x00000000u)
-#define EDMA3_CCRL_ECR_E0_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ECR_E0_MASK           (0x00000001U)
+#define EDMA3_CCRL_ECR_E0_SHIFT          (0x00000000U)
+#define EDMA3_CCRL_ECR_E0_RESETVAL       (0x00000000U)
 
 /*----E0 Tokens----*/
-#define EDMA3_CCRL_ECR_E0_CLEAR          (0x00000001u)
+#define EDMA3_CCRL_ECR_E0_CLEAR          (0x00000001U)
 
-#define EDMA3_CCRL_ECR_RESETVAL          (0x00000000u)
+#define EDMA3_CCRL_ECR_RESETVAL          (0x00000000U)
 
 /* ECRH */
 
-#define EDMA3_CCRL_ECRH_E63_MASK         (0x80000000u)
-#define EDMA3_CCRL_ECRH_E63_SHIFT        (0x0000001Fu)
-#define EDMA3_CCRL_ECRH_E63_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E63_MASK         (0x80000000U)
+#define EDMA3_CCRL_ECRH_E63_SHIFT        (0x0000001FU)
+#define EDMA3_CCRL_ECRH_E63_RESETVAL     (0x00000000U)
 
 /*----E63 Tokens----*/
-#define EDMA3_CCRL_ECRH_E63_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E63_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E62_MASK         (0x40000000u)
-#define EDMA3_CCRL_ECRH_E62_SHIFT        (0x0000001Eu)
-#define EDMA3_CCRL_ECRH_E62_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E62_MASK         (0x40000000U)
+#define EDMA3_CCRL_ECRH_E62_SHIFT        (0x0000001EU)
+#define EDMA3_CCRL_ECRH_E62_RESETVAL     (0x00000000U)
 
 /*----E62 Tokens----*/
-#define EDMA3_CCRL_ECRH_E62_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E62_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E61_MASK         (0x20000000u)
-#define EDMA3_CCRL_ECRH_E61_SHIFT        (0x0000001Du)
-#define EDMA3_CCRL_ECRH_E61_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E61_MASK         (0x20000000U)
+#define EDMA3_CCRL_ECRH_E61_SHIFT        (0x0000001DU)
+#define EDMA3_CCRL_ECRH_E61_RESETVAL     (0x00000000U)
 
 /*----E61 Tokens----*/
-#define EDMA3_CCRL_ECRH_E61_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E61_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E60_MASK         (0x10000000u)
-#define EDMA3_CCRL_ECRH_E60_SHIFT        (0x0000001Cu)
-#define EDMA3_CCRL_ECRH_E60_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E60_MASK         (0x10000000U)
+#define EDMA3_CCRL_ECRH_E60_SHIFT        (0x0000001CU)
+#define EDMA3_CCRL_ECRH_E60_RESETVAL     (0x00000000U)
 
 /*----E60 Tokens----*/
-#define EDMA3_CCRL_ECRH_E60_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E60_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E59_MASK         (0x08000000u)
-#define EDMA3_CCRL_ECRH_E59_SHIFT        (0x0000001Bu)
-#define EDMA3_CCRL_ECRH_E59_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E59_MASK         (0x08000000U)
+#define EDMA3_CCRL_ECRH_E59_SHIFT        (0x0000001BU)
+#define EDMA3_CCRL_ECRH_E59_RESETVAL     (0x00000000U)
 
 /*----E59 Tokens----*/
-#define EDMA3_CCRL_ECRH_E59_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E59_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E58_MASK         (0x04000000u)
-#define EDMA3_CCRL_ECRH_E58_SHIFT        (0x0000001Au)
-#define EDMA3_CCRL_ECRH_E58_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E58_MASK         (0x04000000U)
+#define EDMA3_CCRL_ECRH_E58_SHIFT        (0x0000001AU)
+#define EDMA3_CCRL_ECRH_E58_RESETVAL     (0x00000000U)
 
 /*----E58 Tokens----*/
-#define EDMA3_CCRL_ECRH_E58_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E58_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E57_MASK         (0x02000000u)
-#define EDMA3_CCRL_ECRH_E57_SHIFT        (0x00000019u)
-#define EDMA3_CCRL_ECRH_E57_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E57_MASK         (0x02000000U)
+#define EDMA3_CCRL_ECRH_E57_SHIFT        (0x00000019U)
+#define EDMA3_CCRL_ECRH_E57_RESETVAL     (0x00000000U)
 
 /*----E57 Tokens----*/
-#define EDMA3_CCRL_ECRH_E57_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E57_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E56_MASK         (0x01000000u)
-#define EDMA3_CCRL_ECRH_E56_SHIFT        (0x00000018u)
-#define EDMA3_CCRL_ECRH_E56_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E56_MASK         (0x01000000U)
+#define EDMA3_CCRL_ECRH_E56_SHIFT        (0x00000018U)
+#define EDMA3_CCRL_ECRH_E56_RESETVAL     (0x00000000U)
 
 /*----E56 Tokens----*/
-#define EDMA3_CCRL_ECRH_E56_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E56_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E55_MASK         (0x00800000u)
-#define EDMA3_CCRL_ECRH_E55_SHIFT        (0x00000017u)
-#define EDMA3_CCRL_ECRH_E55_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E55_MASK         (0x00800000U)
+#define EDMA3_CCRL_ECRH_E55_SHIFT        (0x00000017U)
+#define EDMA3_CCRL_ECRH_E55_RESETVAL     (0x00000000U)
 
 /*----E55 Tokens----*/
-#define EDMA3_CCRL_ECRH_E55_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E55_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E54_MASK         (0x00400000u)
-#define EDMA3_CCRL_ECRH_E54_SHIFT        (0x00000016u)
-#define EDMA3_CCRL_ECRH_E54_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E54_MASK         (0x00400000U)
+#define EDMA3_CCRL_ECRH_E54_SHIFT        (0x00000016U)
+#define EDMA3_CCRL_ECRH_E54_RESETVAL     (0x00000000U)
 
 /*----E54 Tokens----*/
-#define EDMA3_CCRL_ECRH_E54_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E54_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E53_MASK         (0x00200000u)
-#define EDMA3_CCRL_ECRH_E53_SHIFT        (0x00000015u)
-#define EDMA3_CCRL_ECRH_E53_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E53_MASK         (0x00200000U)
+#define EDMA3_CCRL_ECRH_E53_SHIFT        (0x00000015U)
+#define EDMA3_CCRL_ECRH_E53_RESETVAL     (0x00000000U)
 
 /*----E53 Tokens----*/
-#define EDMA3_CCRL_ECRH_E53_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E53_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E52_MASK         (0x00100000u)
-#define EDMA3_CCRL_ECRH_E52_SHIFT        (0x00000014u)
-#define EDMA3_CCRL_ECRH_E52_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E52_MASK         (0x00100000U)
+#define EDMA3_CCRL_ECRH_E52_SHIFT        (0x00000014U)
+#define EDMA3_CCRL_ECRH_E52_RESETVAL     (0x00000000U)
 
 /*----E52 Tokens----*/
-#define EDMA3_CCRL_ECRH_E52_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E52_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E51_MASK         (0x00080000u)
-#define EDMA3_CCRL_ECRH_E51_SHIFT        (0x00000013u)
-#define EDMA3_CCRL_ECRH_E51_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E51_MASK         (0x00080000U)
+#define EDMA3_CCRL_ECRH_E51_SHIFT        (0x00000013U)
+#define EDMA3_CCRL_ECRH_E51_RESETVAL     (0x00000000U)
 
 /*----E51 Tokens----*/
-#define EDMA3_CCRL_ECRH_E51_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E51_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E50_MASK         (0x00040000u)
-#define EDMA3_CCRL_ECRH_E50_SHIFT        (0x00000012u)
-#define EDMA3_CCRL_ECRH_E50_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E50_MASK         (0x00040000U)
+#define EDMA3_CCRL_ECRH_E50_SHIFT        (0x00000012U)
+#define EDMA3_CCRL_ECRH_E50_RESETVAL     (0x00000000U)
 
 /*----E50 Tokens----*/
-#define EDMA3_CCRL_ECRH_E50_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E50_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E49_MASK         (0x00020000u)
-#define EDMA3_CCRL_ECRH_E49_SHIFT        (0x00000011u)
-#define EDMA3_CCRL_ECRH_E49_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E49_MASK         (0x00020000U)
+#define EDMA3_CCRL_ECRH_E49_SHIFT        (0x00000011U)
+#define EDMA3_CCRL_ECRH_E49_RESETVAL     (0x00000000U)
 
 /*----E49 Tokens----*/
-#define EDMA3_CCRL_ECRH_E49_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E49_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E48_MASK         (0x00010000u)
-#define EDMA3_CCRL_ECRH_E48_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_ECRH_E48_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E48_MASK         (0x00010000U)
+#define EDMA3_CCRL_ECRH_E48_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_ECRH_E48_RESETVAL     (0x00000000U)
 
 /*----E48 Tokens----*/
-#define EDMA3_CCRL_ECRH_E48_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E48_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E47_MASK         (0x00008000u)
-#define EDMA3_CCRL_ECRH_E47_SHIFT        (0x0000000Fu)
-#define EDMA3_CCRL_ECRH_E47_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E47_MASK         (0x00008000U)
+#define EDMA3_CCRL_ECRH_E47_SHIFT        (0x0000000FU)
+#define EDMA3_CCRL_ECRH_E47_RESETVAL     (0x00000000U)
 
 /*----E47 Tokens----*/
-#define EDMA3_CCRL_ECRH_E47_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E47_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E46_MASK         (0x00004000u)
-#define EDMA3_CCRL_ECRH_E46_SHIFT        (0x0000000Eu)
-#define EDMA3_CCRL_ECRH_E46_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E46_MASK         (0x00004000U)
+#define EDMA3_CCRL_ECRH_E46_SHIFT        (0x0000000EU)
+#define EDMA3_CCRL_ECRH_E46_RESETVAL     (0x00000000U)
 
 /*----E46 Tokens----*/
-#define EDMA3_CCRL_ECRH_E46_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E46_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E45_MASK         (0x00002000u)
-#define EDMA3_CCRL_ECRH_E45_SHIFT        (0x0000000Du)
-#define EDMA3_CCRL_ECRH_E45_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E45_MASK         (0x00002000U)
+#define EDMA3_CCRL_ECRH_E45_SHIFT        (0x0000000DU)
+#define EDMA3_CCRL_ECRH_E45_RESETVAL     (0x00000000U)
 
 /*----E45 Tokens----*/
-#define EDMA3_CCRL_ECRH_E45_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E45_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E44_MASK         (0x00001000u)
-#define EDMA3_CCRL_ECRH_E44_SHIFT        (0x0000000Cu)
-#define EDMA3_CCRL_ECRH_E44_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E44_MASK         (0x00001000U)
+#define EDMA3_CCRL_ECRH_E44_SHIFT        (0x0000000CU)
+#define EDMA3_CCRL_ECRH_E44_RESETVAL     (0x00000000U)
 
 /*----E44 Tokens----*/
-#define EDMA3_CCRL_ECRH_E44_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E44_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E43_MASK         (0x00000800u)
-#define EDMA3_CCRL_ECRH_E43_SHIFT        (0x0000000Bu)
-#define EDMA3_CCRL_ECRH_E43_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E43_MASK         (0x00000800U)
+#define EDMA3_CCRL_ECRH_E43_SHIFT        (0x0000000BU)
+#define EDMA3_CCRL_ECRH_E43_RESETVAL     (0x00000000U)
 
 /*----E43 Tokens----*/
-#define EDMA3_CCRL_ECRH_E43_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E43_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E42_MASK         (0x00000400u)
-#define EDMA3_CCRL_ECRH_E42_SHIFT        (0x0000000Au)
-#define EDMA3_CCRL_ECRH_E42_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E42_MASK         (0x00000400U)
+#define EDMA3_CCRL_ECRH_E42_SHIFT        (0x0000000AU)
+#define EDMA3_CCRL_ECRH_E42_RESETVAL     (0x00000000U)
 
 /*----E42 Tokens----*/
-#define EDMA3_CCRL_ECRH_E42_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E42_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E41_MASK         (0x00000200u)
-#define EDMA3_CCRL_ECRH_E41_SHIFT        (0x00000009u)
-#define EDMA3_CCRL_ECRH_E41_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E41_MASK         (0x00000200U)
+#define EDMA3_CCRL_ECRH_E41_SHIFT        (0x00000009U)
+#define EDMA3_CCRL_ECRH_E41_RESETVAL     (0x00000000U)
 
 /*----E41 Tokens----*/
-#define EDMA3_CCRL_ECRH_E41_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E41_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E40_MASK         (0x00000100u)
-#define EDMA3_CCRL_ECRH_E40_SHIFT        (0x00000008u)
-#define EDMA3_CCRL_ECRH_E40_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E40_MASK         (0x00000100U)
+#define EDMA3_CCRL_ECRH_E40_SHIFT        (0x00000008U)
+#define EDMA3_CCRL_ECRH_E40_RESETVAL     (0x00000000U)
 
 /*----E40 Tokens----*/
-#define EDMA3_CCRL_ECRH_E40_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E40_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E39_MASK         (0x00000080u)
-#define EDMA3_CCRL_ECRH_E39_SHIFT        (0x00000007u)
-#define EDMA3_CCRL_ECRH_E39_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E39_MASK         (0x00000080U)
+#define EDMA3_CCRL_ECRH_E39_SHIFT        (0x00000007U)
+#define EDMA3_CCRL_ECRH_E39_RESETVAL     (0x00000000U)
 
 /*----E39 Tokens----*/
-#define EDMA3_CCRL_ECRH_E39_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E39_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E38_MASK         (0x00000040u)
-#define EDMA3_CCRL_ECRH_E38_SHIFT        (0x00000006u)
-#define EDMA3_CCRL_ECRH_E38_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E38_MASK         (0x00000040U)
+#define EDMA3_CCRL_ECRH_E38_SHIFT        (0x00000006U)
+#define EDMA3_CCRL_ECRH_E38_RESETVAL     (0x00000000U)
 
 /*----E38 Tokens----*/
-#define EDMA3_CCRL_ECRH_E38_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E38_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E37_MASK         (0x00000020u)
-#define EDMA3_CCRL_ECRH_E37_SHIFT        (0x00000005u)
-#define EDMA3_CCRL_ECRH_E37_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E37_MASK         (0x00000020U)
+#define EDMA3_CCRL_ECRH_E37_SHIFT        (0x00000005U)
+#define EDMA3_CCRL_ECRH_E37_RESETVAL     (0x00000000U)
 
 /*----E37 Tokens----*/
-#define EDMA3_CCRL_ECRH_E37_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E37_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E36_MASK         (0x00000010u)
-#define EDMA3_CCRL_ECRH_E36_SHIFT        (0x00000004u)
-#define EDMA3_CCRL_ECRH_E36_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E36_MASK         (0x00000010U)
+#define EDMA3_CCRL_ECRH_E36_SHIFT        (0x00000004U)
+#define EDMA3_CCRL_ECRH_E36_RESETVAL     (0x00000000U)
 
 /*----E36 Tokens----*/
-#define EDMA3_CCRL_ECRH_E36_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E36_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E35_MASK         (0x00000008u)
-#define EDMA3_CCRL_ECRH_E35_SHIFT        (0x00000003u)
-#define EDMA3_CCRL_ECRH_E35_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E35_MASK         (0x00000008U)
+#define EDMA3_CCRL_ECRH_E35_SHIFT        (0x00000003U)
+#define EDMA3_CCRL_ECRH_E35_RESETVAL     (0x00000000U)
 
 /*----E35 Tokens----*/
-#define EDMA3_CCRL_ECRH_E35_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E35_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E34_MASK         (0x00000004u)
-#define EDMA3_CCRL_ECRH_E34_SHIFT        (0x00000002u)
-#define EDMA3_CCRL_ECRH_E34_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E34_MASK         (0x00000004U)
+#define EDMA3_CCRL_ECRH_E34_SHIFT        (0x00000002U)
+#define EDMA3_CCRL_ECRH_E34_RESETVAL     (0x00000000U)
 
 /*----E34 Tokens----*/
-#define EDMA3_CCRL_ECRH_E34_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E34_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E33_MASK         (0x00000002u)
-#define EDMA3_CCRL_ECRH_E33_SHIFT        (0x00000001u)
-#define EDMA3_CCRL_ECRH_E33_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E33_MASK         (0x00000002U)
+#define EDMA3_CCRL_ECRH_E33_SHIFT        (0x00000001U)
+#define EDMA3_CCRL_ECRH_E33_RESETVAL     (0x00000000U)
 
 /*----E33 Tokens----*/
-#define EDMA3_CCRL_ECRH_E33_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E33_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_E32_MASK         (0x00000001u)
-#define EDMA3_CCRL_ECRH_E32_SHIFT        (0x00000000u)
-#define EDMA3_CCRL_ECRH_E32_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ECRH_E32_MASK         (0x00000001U)
+#define EDMA3_CCRL_ECRH_E32_SHIFT        (0x00000000U)
+#define EDMA3_CCRL_ECRH_E32_RESETVAL     (0x00000000U)
 
 /*----E32 Tokens----*/
-#define EDMA3_CCRL_ECRH_E32_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_ECRH_E32_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_ECRH_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_ECRH_RESETVAL         (0x00000000U)
 
 /* ESR */
 
-#define EDMA3_CCRL_ESR_E31_MASK          (0x80000000u)
-#define EDMA3_CCRL_ESR_E31_SHIFT         (0x0000001Fu)
-#define EDMA3_CCRL_ESR_E31_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E31_MASK          (0x80000000U)
+#define EDMA3_CCRL_ESR_E31_SHIFT         (0x0000001FU)
+#define EDMA3_CCRL_ESR_E31_RESETVAL      (0x00000000U)
 
 /*----E31 Tokens----*/
-#define EDMA3_CCRL_ESR_E31_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E31_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E30_MASK          (0x40000000u)
-#define EDMA3_CCRL_ESR_E30_SHIFT         (0x0000001Eu)
-#define EDMA3_CCRL_ESR_E30_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E30_MASK          (0x40000000U)
+#define EDMA3_CCRL_ESR_E30_SHIFT         (0x0000001EU)
+#define EDMA3_CCRL_ESR_E30_RESETVAL      (0x00000000U)
 
 /*----E30 Tokens----*/
-#define EDMA3_CCRL_ESR_E30_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E30_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E29_MASK          (0x20000000u)
-#define EDMA3_CCRL_ESR_E29_SHIFT         (0x0000001Du)
-#define EDMA3_CCRL_ESR_E29_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E29_MASK          (0x20000000U)
+#define EDMA3_CCRL_ESR_E29_SHIFT         (0x0000001DU)
+#define EDMA3_CCRL_ESR_E29_RESETVAL      (0x00000000U)
 
 /*----E29 Tokens----*/
-#define EDMA3_CCRL_ESR_E29_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E29_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E28_MASK          (0x10000000u)
-#define EDMA3_CCRL_ESR_E28_SHIFT         (0x0000001Cu)
-#define EDMA3_CCRL_ESR_E28_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E28_MASK          (0x10000000U)
+#define EDMA3_CCRL_ESR_E28_SHIFT         (0x0000001CU)
+#define EDMA3_CCRL_ESR_E28_RESETVAL      (0x00000000U)
 
 /*----E28 Tokens----*/
-#define EDMA3_CCRL_ESR_E28_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E28_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E27_MASK          (0x08000000u)
-#define EDMA3_CCRL_ESR_E27_SHIFT         (0x0000001Bu)
-#define EDMA3_CCRL_ESR_E27_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E27_MASK          (0x08000000U)
+#define EDMA3_CCRL_ESR_E27_SHIFT         (0x0000001BU)
+#define EDMA3_CCRL_ESR_E27_RESETVAL      (0x00000000U)
 
 /*----E27 Tokens----*/
-#define EDMA3_CCRL_ESR_E27_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E27_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E26_MASK          (0x04000000u)
-#define EDMA3_CCRL_ESR_E26_SHIFT         (0x0000001Au)
-#define EDMA3_CCRL_ESR_E26_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E26_MASK          (0x04000000U)
+#define EDMA3_CCRL_ESR_E26_SHIFT         (0x0000001AU)
+#define EDMA3_CCRL_ESR_E26_RESETVAL      (0x00000000U)
 
 /*----E26 Tokens----*/
-#define EDMA3_CCRL_ESR_E26_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E26_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E25_MASK          (0x02000000u)
-#define EDMA3_CCRL_ESR_E25_SHIFT         (0x00000019u)
-#define EDMA3_CCRL_ESR_E25_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E25_MASK          (0x02000000U)
+#define EDMA3_CCRL_ESR_E25_SHIFT         (0x00000019U)
+#define EDMA3_CCRL_ESR_E25_RESETVAL      (0x00000000U)
 
 /*----E25 Tokens----*/
-#define EDMA3_CCRL_ESR_E25_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E25_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E24_MASK          (0x01000000u)
-#define EDMA3_CCRL_ESR_E24_SHIFT         (0x00000018u)
-#define EDMA3_CCRL_ESR_E24_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E24_MASK          (0x01000000U)
+#define EDMA3_CCRL_ESR_E24_SHIFT         (0x00000018U)
+#define EDMA3_CCRL_ESR_E24_RESETVAL      (0x00000000U)
 
 /*----E24 Tokens----*/
-#define EDMA3_CCRL_ESR_E24_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E24_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E23_MASK          (0x00800000u)
-#define EDMA3_CCRL_ESR_E23_SHIFT         (0x00000017u)
-#define EDMA3_CCRL_ESR_E23_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E23_MASK          (0x00800000U)
+#define EDMA3_CCRL_ESR_E23_SHIFT         (0x00000017U)
+#define EDMA3_CCRL_ESR_E23_RESETVAL      (0x00000000U)
 
 /*----E23 Tokens----*/
-#define EDMA3_CCRL_ESR_E23_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E23_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E22_MASK          (0x00400000u)
-#define EDMA3_CCRL_ESR_E22_SHIFT         (0x00000016u)
-#define EDMA3_CCRL_ESR_E22_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E22_MASK          (0x00400000U)
+#define EDMA3_CCRL_ESR_E22_SHIFT         (0x00000016U)
+#define EDMA3_CCRL_ESR_E22_RESETVAL      (0x00000000U)
 
 /*----E22 Tokens----*/
-#define EDMA3_CCRL_ESR_E22_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E22_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E21_MASK          (0x00200000u)
-#define EDMA3_CCRL_ESR_E21_SHIFT         (0x00000015u)
-#define EDMA3_CCRL_ESR_E21_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E21_MASK          (0x00200000U)
+#define EDMA3_CCRL_ESR_E21_SHIFT         (0x00000015U)
+#define EDMA3_CCRL_ESR_E21_RESETVAL      (0x00000000U)
 
 /*----E21 Tokens----*/
-#define EDMA3_CCRL_ESR_E21_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E21_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E20_MASK          (0x00100000u)
-#define EDMA3_CCRL_ESR_E20_SHIFT         (0x00000014u)
-#define EDMA3_CCRL_ESR_E20_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E20_MASK          (0x00100000U)
+#define EDMA3_CCRL_ESR_E20_SHIFT         (0x00000014U)
+#define EDMA3_CCRL_ESR_E20_RESETVAL      (0x00000000U)
 
 /*----E20 Tokens----*/
-#define EDMA3_CCRL_ESR_E20_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E20_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E19_MASK          (0x00080000u)
-#define EDMA3_CCRL_ESR_E19_SHIFT         (0x00000013u)
-#define EDMA3_CCRL_ESR_E19_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E19_MASK          (0x00080000U)
+#define EDMA3_CCRL_ESR_E19_SHIFT         (0x00000013U)
+#define EDMA3_CCRL_ESR_E19_RESETVAL      (0x00000000U)
 
 /*----E19 Tokens----*/
-#define EDMA3_CCRL_ESR_E19_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E19_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E18_MASK          (0x00040000u)
-#define EDMA3_CCRL_ESR_E18_SHIFT         (0x00000012u)
-#define EDMA3_CCRL_ESR_E18_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E18_MASK          (0x00040000U)
+#define EDMA3_CCRL_ESR_E18_SHIFT         (0x00000012U)
+#define EDMA3_CCRL_ESR_E18_RESETVAL      (0x00000000U)
 
 /*----E18 Tokens----*/
-#define EDMA3_CCRL_ESR_E18_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E18_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E17_MASK          (0x00020000u)
-#define EDMA3_CCRL_ESR_E17_SHIFT         (0x00000011u)
-#define EDMA3_CCRL_ESR_E17_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E17_MASK          (0x00020000U)
+#define EDMA3_CCRL_ESR_E17_SHIFT         (0x00000011U)
+#define EDMA3_CCRL_ESR_E17_RESETVAL      (0x00000000U)
 
 /*----E17 Tokens----*/
-#define EDMA3_CCRL_ESR_E17_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E17_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E16_MASK          (0x00010000u)
-#define EDMA3_CCRL_ESR_E16_SHIFT         (0x00000010u)
-#define EDMA3_CCRL_ESR_E16_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E16_MASK          (0x00010000U)
+#define EDMA3_CCRL_ESR_E16_SHIFT         (0x00000010U)
+#define EDMA3_CCRL_ESR_E16_RESETVAL      (0x00000000U)
 
 /*----E16 Tokens----*/
-#define EDMA3_CCRL_ESR_E16_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E16_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E15_MASK          (0x00008000u)
-#define EDMA3_CCRL_ESR_E15_SHIFT         (0x0000000Fu)
-#define EDMA3_CCRL_ESR_E15_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E15_MASK          (0x00008000U)
+#define EDMA3_CCRL_ESR_E15_SHIFT         (0x0000000FU)
+#define EDMA3_CCRL_ESR_E15_RESETVAL      (0x00000000U)
 
 /*----E15 Tokens----*/
-#define EDMA3_CCRL_ESR_E15_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E15_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E14_MASK          (0x00004000u)
-#define EDMA3_CCRL_ESR_E14_SHIFT         (0x0000000Eu)
-#define EDMA3_CCRL_ESR_E14_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E14_MASK          (0x00004000U)
+#define EDMA3_CCRL_ESR_E14_SHIFT         (0x0000000EU)
+#define EDMA3_CCRL_ESR_E14_RESETVAL      (0x00000000U)
 
 /*----E14 Tokens----*/
-#define EDMA3_CCRL_ESR_E14_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E14_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E13_MASK          (0x00002000u)
-#define EDMA3_CCRL_ESR_E13_SHIFT         (0x0000000Du)
-#define EDMA3_CCRL_ESR_E13_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E13_MASK          (0x00002000U)
+#define EDMA3_CCRL_ESR_E13_SHIFT         (0x0000000DU)
+#define EDMA3_CCRL_ESR_E13_RESETVAL      (0x00000000U)
 
 /*----E13 Tokens----*/
-#define EDMA3_CCRL_ESR_E13_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E13_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E12_MASK          (0x00001000u)
-#define EDMA3_CCRL_ESR_E12_SHIFT         (0x0000000Cu)
-#define EDMA3_CCRL_ESR_E12_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E12_MASK          (0x00001000U)
+#define EDMA3_CCRL_ESR_E12_SHIFT         (0x0000000CU)
+#define EDMA3_CCRL_ESR_E12_RESETVAL      (0x00000000U)
 
 /*----E12 Tokens----*/
-#define EDMA3_CCRL_ESR_E12_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E12_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E11_MASK          (0x00000800u)
-#define EDMA3_CCRL_ESR_E11_SHIFT         (0x0000000Bu)
-#define EDMA3_CCRL_ESR_E11_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E11_MASK          (0x00000800U)
+#define EDMA3_CCRL_ESR_E11_SHIFT         (0x0000000BU)
+#define EDMA3_CCRL_ESR_E11_RESETVAL      (0x00000000U)
 
 /*----E11 Tokens----*/
-#define EDMA3_CCRL_ESR_E11_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E11_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E10_MASK          (0x00000400u)
-#define EDMA3_CCRL_ESR_E10_SHIFT         (0x0000000Au)
-#define EDMA3_CCRL_ESR_E10_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_ESR_E10_MASK          (0x00000400U)
+#define EDMA3_CCRL_ESR_E10_SHIFT         (0x0000000AU)
+#define EDMA3_CCRL_ESR_E10_RESETVAL      (0x00000000U)
 
 /*----E10 Tokens----*/
-#define EDMA3_CCRL_ESR_E10_SET           (0x00000001u)
+#define EDMA3_CCRL_ESR_E10_SET           (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E9_MASK           (0x00000200u)
-#define EDMA3_CCRL_ESR_E9_SHIFT          (0x00000009u)
-#define EDMA3_CCRL_ESR_E9_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ESR_E9_MASK           (0x00000200U)
+#define EDMA3_CCRL_ESR_E9_SHIFT          (0x00000009U)
+#define EDMA3_CCRL_ESR_E9_RESETVAL       (0x00000000U)
 
 /*----E9 Tokens----*/
-#define EDMA3_CCRL_ESR_E9_SET            (0x00000001u)
+#define EDMA3_CCRL_ESR_E9_SET            (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E8_MASK           (0x00000100u)
-#define EDMA3_CCRL_ESR_E8_SHIFT          (0x00000008u)
-#define EDMA3_CCRL_ESR_E8_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ESR_E8_MASK           (0x00000100U)
+#define EDMA3_CCRL_ESR_E8_SHIFT          (0x00000008U)
+#define EDMA3_CCRL_ESR_E8_RESETVAL       (0x00000000U)
 
 /*----E8 Tokens----*/
-#define EDMA3_CCRL_ESR_E8_SET            (0x00000001u)
+#define EDMA3_CCRL_ESR_E8_SET            (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E7_MASK           (0x00000080u)
-#define EDMA3_CCRL_ESR_E7_SHIFT          (0x00000007u)
-#define EDMA3_CCRL_ESR_E7_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ESR_E7_MASK           (0x00000080U)
+#define EDMA3_CCRL_ESR_E7_SHIFT          (0x00000007U)
+#define EDMA3_CCRL_ESR_E7_RESETVAL       (0x00000000U)
 
 /*----E7 Tokens----*/
-#define EDMA3_CCRL_ESR_E7_SET            (0x00000001u)
+#define EDMA3_CCRL_ESR_E7_SET            (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E6_MASK           (0x00000040u)
-#define EDMA3_CCRL_ESR_E6_SHIFT          (0x00000006u)
-#define EDMA3_CCRL_ESR_E6_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ESR_E6_MASK           (0x00000040U)
+#define EDMA3_CCRL_ESR_E6_SHIFT          (0x00000006U)
+#define EDMA3_CCRL_ESR_E6_RESETVAL       (0x00000000U)
 
 /*----E6 Tokens----*/
-#define EDMA3_CCRL_ESR_E6_SET            (0x00000001u)
+#define EDMA3_CCRL_ESR_E6_SET            (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E5_MASK           (0x00000020u)
-#define EDMA3_CCRL_ESR_E5_SHIFT          (0x00000005u)
-#define EDMA3_CCRL_ESR_E5_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ESR_E5_MASK           (0x00000020U)
+#define EDMA3_CCRL_ESR_E5_SHIFT          (0x00000005U)
+#define EDMA3_CCRL_ESR_E5_RESETVAL       (0x00000000U)
 
 /*----E5 Tokens----*/
-#define EDMA3_CCRL_ESR_E5_SET            (0x00000001u)
+#define EDMA3_CCRL_ESR_E5_SET            (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E4_MASK           (0x00000010u)
-#define EDMA3_CCRL_ESR_E4_SHIFT          (0x00000004u)
-#define EDMA3_CCRL_ESR_E4_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ESR_E4_MASK           (0x00000010U)
+#define EDMA3_CCRL_ESR_E4_SHIFT          (0x00000004U)
+#define EDMA3_CCRL_ESR_E4_RESETVAL       (0x00000000U)
 
 /*----E4 Tokens----*/
-#define EDMA3_CCRL_ESR_E4_SET            (0x00000001u)
+#define EDMA3_CCRL_ESR_E4_SET            (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E3_MASK           (0x00000008u)
-#define EDMA3_CCRL_ESR_E3_SHIFT          (0x00000003u)
-#define EDMA3_CCRL_ESR_E3_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ESR_E3_MASK           (0x00000008U)
+#define EDMA3_CCRL_ESR_E3_SHIFT          (0x00000003U)
+#define EDMA3_CCRL_ESR_E3_RESETVAL       (0x00000000U)
 
 /*----E3 Tokens----*/
-#define EDMA3_CCRL_ESR_E3_SET            (0x00000001u)
+#define EDMA3_CCRL_ESR_E3_SET            (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E2_MASK           (0x00000004u)
-#define EDMA3_CCRL_ESR_E2_SHIFT          (0x00000002u)
-#define EDMA3_CCRL_ESR_E2_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ESR_E2_MASK           (0x00000004U)
+#define EDMA3_CCRL_ESR_E2_SHIFT          (0x00000002U)
+#define EDMA3_CCRL_ESR_E2_RESETVAL       (0x00000000U)
 
 /*----E2 Tokens----*/
-#define EDMA3_CCRL_ESR_E2_SET            (0x00000001u)
+#define EDMA3_CCRL_ESR_E2_SET            (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E1_MASK           (0x00000002u)
-#define EDMA3_CCRL_ESR_E1_SHIFT          (0x00000001u)
-#define EDMA3_CCRL_ESR_E1_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ESR_E1_MASK           (0x00000002U)
+#define EDMA3_CCRL_ESR_E1_SHIFT          (0x00000001U)
+#define EDMA3_CCRL_ESR_E1_RESETVAL       (0x00000000U)
 
 /*----E1 Tokens----*/
-#define EDMA3_CCRL_ESR_E1_SET            (0x00000001u)
+#define EDMA3_CCRL_ESR_E1_SET            (0x00000001U)
 
-#define EDMA3_CCRL_ESR_E0_MASK           (0x00000001u)
-#define EDMA3_CCRL_ESR_E0_SHIFT          (0x00000000u)
-#define EDMA3_CCRL_ESR_E0_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_ESR_E0_MASK           (0x00000001U)
+#define EDMA3_CCRL_ESR_E0_SHIFT          (0x00000000U)
+#define EDMA3_CCRL_ESR_E0_RESETVAL       (0x00000000U)
 
 /*----E0 Tokens----*/
-#define EDMA3_CCRL_ESR_E0_SET            (0x00000001u)
+#define EDMA3_CCRL_ESR_E0_SET            (0x00000001U)
 
-#define EDMA3_CCRL_ESR_RESETVAL          (0x00000000u)
+#define EDMA3_CCRL_ESR_RESETVAL          (0x00000000U)
 
 /* ESRH */
 
-#define EDMA3_CCRL_ESRH_E63_MASK         (0x80000000u)
-#define EDMA3_CCRL_ESRH_E63_SHIFT        (0x0000001Fu)
-#define EDMA3_CCRL_ESRH_E63_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E63_MASK         (0x80000000U)
+#define EDMA3_CCRL_ESRH_E63_SHIFT        (0x0000001FU)
+#define EDMA3_CCRL_ESRH_E63_RESETVAL     (0x00000000U)
 
 /*----E63 Tokens----*/
-#define EDMA3_CCRL_ESRH_E63_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E63_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E62_MASK         (0x40000000u)
-#define EDMA3_CCRL_ESRH_E62_SHIFT        (0x0000001Eu)
-#define EDMA3_CCRL_ESRH_E62_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E62_MASK         (0x40000000U)
+#define EDMA3_CCRL_ESRH_E62_SHIFT        (0x0000001EU)
+#define EDMA3_CCRL_ESRH_E62_RESETVAL     (0x00000000U)
 
 /*----E62 Tokens----*/
-#define EDMA3_CCRL_ESRH_E62_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E62_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E61_MASK         (0x20000000u)
-#define EDMA3_CCRL_ESRH_E61_SHIFT        (0x0000001Du)
-#define EDMA3_CCRL_ESRH_E61_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E61_MASK         (0x20000000U)
+#define EDMA3_CCRL_ESRH_E61_SHIFT        (0x0000001DU)
+#define EDMA3_CCRL_ESRH_E61_RESETVAL     (0x00000000U)
 
 /*----E61 Tokens----*/
-#define EDMA3_CCRL_ESRH_E61_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E61_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E60_MASK         (0x10000000u)
-#define EDMA3_CCRL_ESRH_E60_SHIFT        (0x0000001Cu)
-#define EDMA3_CCRL_ESRH_E60_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E60_MASK         (0x10000000U)
+#define EDMA3_CCRL_ESRH_E60_SHIFT        (0x0000001CU)
+#define EDMA3_CCRL_ESRH_E60_RESETVAL     (0x00000000U)
 
 /*----E60 Tokens----*/
-#define EDMA3_CCRL_ESRH_E60_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E60_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E59_MASK         (0x08000000u)
-#define EDMA3_CCRL_ESRH_E59_SHIFT        (0x0000001Bu)
-#define EDMA3_CCRL_ESRH_E59_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E59_MASK         (0x08000000U)
+#define EDMA3_CCRL_ESRH_E59_SHIFT        (0x0000001BU)
+#define EDMA3_CCRL_ESRH_E59_RESETVAL     (0x00000000U)
 
 /*----E59 Tokens----*/
-#define EDMA3_CCRL_ESRH_E59_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E59_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E58_MASK         (0x04000000u)
-#define EDMA3_CCRL_ESRH_E58_SHIFT        (0x0000001Au)
-#define EDMA3_CCRL_ESRH_E58_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E58_MASK         (0x04000000U)
+#define EDMA3_CCRL_ESRH_E58_SHIFT        (0x0000001AU)
+#define EDMA3_CCRL_ESRH_E58_RESETVAL     (0x00000000U)
 
 /*----E58 Tokens----*/
-#define EDMA3_CCRL_ESRH_E58_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E58_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E57_MASK         (0x02000000u)
-#define EDMA3_CCRL_ESRH_E57_SHIFT        (0x00000019u)
-#define EDMA3_CCRL_ESRH_E57_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E57_MASK         (0x02000000U)
+#define EDMA3_CCRL_ESRH_E57_SHIFT        (0x00000019U)
+#define EDMA3_CCRL_ESRH_E57_RESETVAL     (0x00000000U)
 
 /*----E57 Tokens----*/
-#define EDMA3_CCRL_ESRH_E57_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E57_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E56_MASK         (0x01000000u)
-#define EDMA3_CCRL_ESRH_E56_SHIFT        (0x00000018u)
-#define EDMA3_CCRL_ESRH_E56_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E56_MASK         (0x01000000U)
+#define EDMA3_CCRL_ESRH_E56_SHIFT        (0x00000018U)
+#define EDMA3_CCRL_ESRH_E56_RESETVAL     (0x00000000U)
 
 /*----E56 Tokens----*/
-#define EDMA3_CCRL_ESRH_E56_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E56_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E55_MASK         (0x00800000u)
-#define EDMA3_CCRL_ESRH_E55_SHIFT        (0x00000017u)
-#define EDMA3_CCRL_ESRH_E55_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E55_MASK         (0x00800000U)
+#define EDMA3_CCRL_ESRH_E55_SHIFT        (0x00000017U)
+#define EDMA3_CCRL_ESRH_E55_RESETVAL     (0x00000000U)
 
 /*----E55 Tokens----*/
-#define EDMA3_CCRL_ESRH_E55_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E55_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E54_MASK         (0x00400000u)
-#define EDMA3_CCRL_ESRH_E54_SHIFT        (0x00000016u)
-#define EDMA3_CCRL_ESRH_E54_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E54_MASK         (0x00400000U)
+#define EDMA3_CCRL_ESRH_E54_SHIFT        (0x00000016U)
+#define EDMA3_CCRL_ESRH_E54_RESETVAL     (0x00000000U)
 
 /*----E54 Tokens----*/
-#define EDMA3_CCRL_ESRH_E54_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E54_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E53_MASK         (0x00200000u)
-#define EDMA3_CCRL_ESRH_E53_SHIFT        (0x00000015u)
-#define EDMA3_CCRL_ESRH_E53_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E53_MASK         (0x00200000U)
+#define EDMA3_CCRL_ESRH_E53_SHIFT        (0x00000015U)
+#define EDMA3_CCRL_ESRH_E53_RESETVAL     (0x00000000U)
 
 /*----E53 Tokens----*/
-#define EDMA3_CCRL_ESRH_E53_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E53_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E52_MASK         (0x00100000u)
-#define EDMA3_CCRL_ESRH_E52_SHIFT        (0x00000014u)
-#define EDMA3_CCRL_ESRH_E52_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E52_MASK         (0x00100000U)
+#define EDMA3_CCRL_ESRH_E52_SHIFT        (0x00000014U)
+#define EDMA3_CCRL_ESRH_E52_RESETVAL     (0x00000000U)
 
 /*----E52 Tokens----*/
-#define EDMA3_CCRL_ESRH_E52_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E52_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E51_MASK         (0x00080000u)
-#define EDMA3_CCRL_ESRH_E51_SHIFT        (0x00000013u)
-#define EDMA3_CCRL_ESRH_E51_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E51_MASK         (0x00080000U)
+#define EDMA3_CCRL_ESRH_E51_SHIFT        (0x00000013U)
+#define EDMA3_CCRL_ESRH_E51_RESETVAL     (0x00000000U)
 
 /*----E51 Tokens----*/
-#define EDMA3_CCRL_ESRH_E51_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E51_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E50_MASK         (0x00040000u)
-#define EDMA3_CCRL_ESRH_E50_SHIFT        (0x00000012u)
-#define EDMA3_CCRL_ESRH_E50_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E50_MASK         (0x00040000U)
+#define EDMA3_CCRL_ESRH_E50_SHIFT        (0x00000012U)
+#define EDMA3_CCRL_ESRH_E50_RESETVAL     (0x00000000U)
 
 /*----E50 Tokens----*/
-#define EDMA3_CCRL_ESRH_E50_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E50_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E49_MASK         (0x00020000u)
-#define EDMA3_CCRL_ESRH_E49_SHIFT        (0x00000011u)
-#define EDMA3_CCRL_ESRH_E49_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E49_MASK         (0x00020000U)
+#define EDMA3_CCRL_ESRH_E49_SHIFT        (0x00000011U)
+#define EDMA3_CCRL_ESRH_E49_RESETVAL     (0x00000000U)
 
 /*----E49 Tokens----*/
-#define EDMA3_CCRL_ESRH_E49_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E49_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E48_MASK         (0x00010000u)
-#define EDMA3_CCRL_ESRH_E48_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_ESRH_E48_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E48_MASK         (0x00010000U)
+#define EDMA3_CCRL_ESRH_E48_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_ESRH_E48_RESETVAL     (0x00000000U)
 
 /*----E48 Tokens----*/
-#define EDMA3_CCRL_ESRH_E48_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E48_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E47_MASK         (0x00008000u)
-#define EDMA3_CCRL_ESRH_E47_SHIFT        (0x0000000Fu)
-#define EDMA3_CCRL_ESRH_E47_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E47_MASK         (0x00008000U)
+#define EDMA3_CCRL_ESRH_E47_SHIFT        (0x0000000FU)
+#define EDMA3_CCRL_ESRH_E47_RESETVAL     (0x00000000U)
 
 /*----E47 Tokens----*/
-#define EDMA3_CCRL_ESRH_E47_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E47_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E46_MASK         (0x00004000u)
-#define EDMA3_CCRL_ESRH_E46_SHIFT        (0x0000000Eu)
-#define EDMA3_CCRL_ESRH_E46_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E46_MASK         (0x00004000U)
+#define EDMA3_CCRL_ESRH_E46_SHIFT        (0x0000000EU)
+#define EDMA3_CCRL_ESRH_E46_RESETVAL     (0x00000000U)
 
 /*----E46 Tokens----*/
-#define EDMA3_CCRL_ESRH_E46_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E46_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E45_MASK         (0x00002000u)
-#define EDMA3_CCRL_ESRH_E45_SHIFT        (0x0000000Du)
-#define EDMA3_CCRL_ESRH_E45_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E45_MASK         (0x00002000U)
+#define EDMA3_CCRL_ESRH_E45_SHIFT        (0x0000000DU)
+#define EDMA3_CCRL_ESRH_E45_RESETVAL     (0x00000000U)
 
 /*----E45 Tokens----*/
-#define EDMA3_CCRL_ESRH_E45_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E45_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E44_MASK         (0x00001000u)
-#define EDMA3_CCRL_ESRH_E44_SHIFT        (0x0000000Cu)
-#define EDMA3_CCRL_ESRH_E44_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E44_MASK         (0x00001000U)
+#define EDMA3_CCRL_ESRH_E44_SHIFT        (0x0000000CU)
+#define EDMA3_CCRL_ESRH_E44_RESETVAL     (0x00000000U)
 
 /*----E44 Tokens----*/
-#define EDMA3_CCRL_ESRH_E44_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E44_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E43_MASK         (0x00000800u)
-#define EDMA3_CCRL_ESRH_E43_SHIFT        (0x0000000Bu)
-#define EDMA3_CCRL_ESRH_E43_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E43_MASK         (0x00000800U)
+#define EDMA3_CCRL_ESRH_E43_SHIFT        (0x0000000BU)
+#define EDMA3_CCRL_ESRH_E43_RESETVAL     (0x00000000U)
 
 /*----E43 Tokens----*/
-#define EDMA3_CCRL_ESRH_E43_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E43_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E42_MASK         (0x00000400u)
-#define EDMA3_CCRL_ESRH_E42_SHIFT        (0x0000000Au)
-#define EDMA3_CCRL_ESRH_E42_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E42_MASK         (0x00000400U)
+#define EDMA3_CCRL_ESRH_E42_SHIFT        (0x0000000AU)
+#define EDMA3_CCRL_ESRH_E42_RESETVAL     (0x00000000U)
 
 /*----E42 Tokens----*/
-#define EDMA3_CCRL_ESRH_E42_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E42_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E41_MASK         (0x00000200u)
-#define EDMA3_CCRL_ESRH_E41_SHIFT        (0x00000009u)
-#define EDMA3_CCRL_ESRH_E41_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E41_MASK         (0x00000200U)
+#define EDMA3_CCRL_ESRH_E41_SHIFT        (0x00000009U)
+#define EDMA3_CCRL_ESRH_E41_RESETVAL     (0x00000000U)
 
 /*----E41 Tokens----*/
-#define EDMA3_CCRL_ESRH_E41_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E41_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E40_MASK         (0x00000100u)
-#define EDMA3_CCRL_ESRH_E40_SHIFT        (0x00000008u)
-#define EDMA3_CCRL_ESRH_E40_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E40_MASK         (0x00000100U)
+#define EDMA3_CCRL_ESRH_E40_SHIFT        (0x00000008U)
+#define EDMA3_CCRL_ESRH_E40_RESETVAL     (0x00000000U)
 
 /*----E40 Tokens----*/
-#define EDMA3_CCRL_ESRH_E40_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E40_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E39_MASK         (0x00000080u)
-#define EDMA3_CCRL_ESRH_E39_SHIFT        (0x00000007u)
-#define EDMA3_CCRL_ESRH_E39_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E39_MASK         (0x00000080U)
+#define EDMA3_CCRL_ESRH_E39_SHIFT        (0x00000007U)
+#define EDMA3_CCRL_ESRH_E39_RESETVAL     (0x00000000U)
 
 /*----E39 Tokens----*/
-#define EDMA3_CCRL_ESRH_E39_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E39_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E38_MASK         (0x00000040u)
-#define EDMA3_CCRL_ESRH_E38_SHIFT        (0x00000006u)
-#define EDMA3_CCRL_ESRH_E38_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E38_MASK         (0x00000040U)
+#define EDMA3_CCRL_ESRH_E38_SHIFT        (0x00000006U)
+#define EDMA3_CCRL_ESRH_E38_RESETVAL     (0x00000000U)
 
 /*----E38 Tokens----*/
-#define EDMA3_CCRL_ESRH_E38_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E38_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E37_MASK         (0x00000020u)
-#define EDMA3_CCRL_ESRH_E37_SHIFT        (0x00000005u)
-#define EDMA3_CCRL_ESRH_E37_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E37_MASK         (0x00000020U)
+#define EDMA3_CCRL_ESRH_E37_SHIFT        (0x00000005U)
+#define EDMA3_CCRL_ESRH_E37_RESETVAL     (0x00000000U)
 
 /*----E37 Tokens----*/
-#define EDMA3_CCRL_ESRH_E37_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E37_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E36_MASK         (0x00000010u)
-#define EDMA3_CCRL_ESRH_E36_SHIFT        (0x00000004u)
-#define EDMA3_CCRL_ESRH_E36_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E36_MASK         (0x00000010U)
+#define EDMA3_CCRL_ESRH_E36_SHIFT        (0x00000004U)
+#define EDMA3_CCRL_ESRH_E36_RESETVAL     (0x00000000U)
 
 /*----E36 Tokens----*/
-#define EDMA3_CCRL_ESRH_E36_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E36_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E35_MASK         (0x00000008u)
-#define EDMA3_CCRL_ESRH_E35_SHIFT        (0x00000003u)
-#define EDMA3_CCRL_ESRH_E35_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E35_MASK         (0x00000008U)
+#define EDMA3_CCRL_ESRH_E35_SHIFT        (0x00000003U)
+#define EDMA3_CCRL_ESRH_E35_RESETVAL     (0x00000000U)
 
 /*----E35 Tokens----*/
-#define EDMA3_CCRL_ESRH_E35_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E35_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E34_MASK         (0x00000004u)
-#define EDMA3_CCRL_ESRH_E34_SHIFT        (0x00000002u)
-#define EDMA3_CCRL_ESRH_E34_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E34_MASK         (0x00000004U)
+#define EDMA3_CCRL_ESRH_E34_SHIFT        (0x00000002U)
+#define EDMA3_CCRL_ESRH_E34_RESETVAL     (0x00000000U)
 
 /*----E34 Tokens----*/
-#define EDMA3_CCRL_ESRH_E34_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E34_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E33_MASK         (0x00000002u)
-#define EDMA3_CCRL_ESRH_E33_SHIFT        (0x00000001u)
-#define EDMA3_CCRL_ESRH_E33_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E33_MASK         (0x00000002U)
+#define EDMA3_CCRL_ESRH_E33_SHIFT        (0x00000001U)
+#define EDMA3_CCRL_ESRH_E33_RESETVAL     (0x00000000U)
 
 /*----E33 Tokens----*/
-#define EDMA3_CCRL_ESRH_E33_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E33_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_E32_MASK         (0x00000001u)
-#define EDMA3_CCRL_ESRH_E32_SHIFT        (0x00000000u)
-#define EDMA3_CCRL_ESRH_E32_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_ESRH_E32_MASK         (0x00000001U)
+#define EDMA3_CCRL_ESRH_E32_SHIFT        (0x00000000U)
+#define EDMA3_CCRL_ESRH_E32_RESETVAL     (0x00000000U)
 
 /*----E32 Tokens----*/
-#define EDMA3_CCRL_ESRH_E32_SET          (0x00000001u)
+#define EDMA3_CCRL_ESRH_E32_SET          (0x00000001U)
 
-#define EDMA3_CCRL_ESRH_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_ESRH_RESETVAL         (0x00000000U)
 
 /* CER */
 
-#define EDMA3_CCRL_CER_E31_MASK          (0x80000000u)
-#define EDMA3_CCRL_CER_E31_SHIFT         (0x0000001Fu)
-#define EDMA3_CCRL_CER_E31_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E31_MASK          (0x80000000U)
+#define EDMA3_CCRL_CER_E31_SHIFT         (0x0000001FU)
+#define EDMA3_CCRL_CER_E31_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E30_MASK          (0x40000000u)
-#define EDMA3_CCRL_CER_E30_SHIFT         (0x0000001Eu)
-#define EDMA3_CCRL_CER_E30_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E30_MASK          (0x40000000U)
+#define EDMA3_CCRL_CER_E30_SHIFT         (0x0000001EU)
+#define EDMA3_CCRL_CER_E30_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E29_MASK          (0x20000000u)
-#define EDMA3_CCRL_CER_E29_SHIFT         (0x0000001Du)
-#define EDMA3_CCRL_CER_E29_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E29_MASK          (0x20000000U)
+#define EDMA3_CCRL_CER_E29_SHIFT         (0x0000001DU)
+#define EDMA3_CCRL_CER_E29_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E28_MASK          (0x10000000u)
-#define EDMA3_CCRL_CER_E28_SHIFT         (0x0000001Cu)
-#define EDMA3_CCRL_CER_E28_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E28_MASK          (0x10000000U)
+#define EDMA3_CCRL_CER_E28_SHIFT         (0x0000001CU)
+#define EDMA3_CCRL_CER_E28_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E27_MASK          (0x08000000u)
-#define EDMA3_CCRL_CER_E27_SHIFT         (0x0000001Bu)
-#define EDMA3_CCRL_CER_E27_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E27_MASK          (0x08000000U)
+#define EDMA3_CCRL_CER_E27_SHIFT         (0x0000001BU)
+#define EDMA3_CCRL_CER_E27_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E26_MASK          (0x04000000u)
-#define EDMA3_CCRL_CER_E26_SHIFT         (0x0000001Au)
-#define EDMA3_CCRL_CER_E26_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E26_MASK          (0x04000000U)
+#define EDMA3_CCRL_CER_E26_SHIFT         (0x0000001AU)
+#define EDMA3_CCRL_CER_E26_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E25_MASK          (0x02000000u)
-#define EDMA3_CCRL_CER_E25_SHIFT         (0x00000019u)
-#define EDMA3_CCRL_CER_E25_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E25_MASK          (0x02000000U)
+#define EDMA3_CCRL_CER_E25_SHIFT         (0x00000019U)
+#define EDMA3_CCRL_CER_E25_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E24_MASK          (0x01000000u)
-#define EDMA3_CCRL_CER_E24_SHIFT         (0x00000018u)
-#define EDMA3_CCRL_CER_E24_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E24_MASK          (0x01000000U)
+#define EDMA3_CCRL_CER_E24_SHIFT         (0x00000018U)
+#define EDMA3_CCRL_CER_E24_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E23_MASK          (0x00800000u)
-#define EDMA3_CCRL_CER_E23_SHIFT         (0x00000017u)
-#define EDMA3_CCRL_CER_E23_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E23_MASK          (0x00800000U)
+#define EDMA3_CCRL_CER_E23_SHIFT         (0x00000017U)
+#define EDMA3_CCRL_CER_E23_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E22_MASK          (0x00400000u)
-#define EDMA3_CCRL_CER_E22_SHIFT         (0x00000016u)
-#define EDMA3_CCRL_CER_E22_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E22_MASK          (0x00400000U)
+#define EDMA3_CCRL_CER_E22_SHIFT         (0x00000016U)
+#define EDMA3_CCRL_CER_E22_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E21_MASK          (0x00200000u)
-#define EDMA3_CCRL_CER_E21_SHIFT         (0x00000015u)
-#define EDMA3_CCRL_CER_E21_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E21_MASK          (0x00200000U)
+#define EDMA3_CCRL_CER_E21_SHIFT         (0x00000015U)
+#define EDMA3_CCRL_CER_E21_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E20_MASK          (0x00100000u)
-#define EDMA3_CCRL_CER_E20_SHIFT         (0x00000014u)
-#define EDMA3_CCRL_CER_E20_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E20_MASK          (0x00100000U)
+#define EDMA3_CCRL_CER_E20_SHIFT         (0x00000014U)
+#define EDMA3_CCRL_CER_E20_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E19_MASK          (0x00080000u)
-#define EDMA3_CCRL_CER_E19_SHIFT         (0x00000013u)
-#define EDMA3_CCRL_CER_E19_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E19_MASK          (0x00080000U)
+#define EDMA3_CCRL_CER_E19_SHIFT         (0x00000013U)
+#define EDMA3_CCRL_CER_E19_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E18_MASK          (0x00040000u)
-#define EDMA3_CCRL_CER_E18_SHIFT         (0x00000012u)
-#define EDMA3_CCRL_CER_E18_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E18_MASK          (0x00040000U)
+#define EDMA3_CCRL_CER_E18_SHIFT         (0x00000012U)
+#define EDMA3_CCRL_CER_E18_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E17_MASK          (0x00020000u)
-#define EDMA3_CCRL_CER_E17_SHIFT         (0x00000011u)
-#define EDMA3_CCRL_CER_E17_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E17_MASK          (0x00020000U)
+#define EDMA3_CCRL_CER_E17_SHIFT         (0x00000011U)
+#define EDMA3_CCRL_CER_E17_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E16_MASK          (0x00010000u)
-#define EDMA3_CCRL_CER_E16_SHIFT         (0x00000010u)
-#define EDMA3_CCRL_CER_E16_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E16_MASK          (0x00010000U)
+#define EDMA3_CCRL_CER_E16_SHIFT         (0x00000010U)
+#define EDMA3_CCRL_CER_E16_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E15_MASK          (0x00008000u)
-#define EDMA3_CCRL_CER_E15_SHIFT         (0x0000000Fu)
-#define EDMA3_CCRL_CER_E15_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E15_MASK          (0x00008000U)
+#define EDMA3_CCRL_CER_E15_SHIFT         (0x0000000FU)
+#define EDMA3_CCRL_CER_E15_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E14_MASK          (0x00004000u)
-#define EDMA3_CCRL_CER_E14_SHIFT         (0x0000000Eu)
-#define EDMA3_CCRL_CER_E14_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E14_MASK          (0x00004000U)
+#define EDMA3_CCRL_CER_E14_SHIFT         (0x0000000EU)
+#define EDMA3_CCRL_CER_E14_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E13_MASK          (0x00002000u)
-#define EDMA3_CCRL_CER_E13_SHIFT         (0x0000000Du)
-#define EDMA3_CCRL_CER_E13_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E13_MASK          (0x00002000U)
+#define EDMA3_CCRL_CER_E13_SHIFT         (0x0000000DU)
+#define EDMA3_CCRL_CER_E13_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E12_MASK          (0x00001000u)
-#define EDMA3_CCRL_CER_E12_SHIFT         (0x0000000Cu)
-#define EDMA3_CCRL_CER_E12_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E12_MASK          (0x00001000U)
+#define EDMA3_CCRL_CER_E12_SHIFT         (0x0000000CU)
+#define EDMA3_CCRL_CER_E12_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E11_MASK          (0x00000800u)
-#define EDMA3_CCRL_CER_E11_SHIFT         (0x0000000Bu)
-#define EDMA3_CCRL_CER_E11_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E11_MASK          (0x00000800U)
+#define EDMA3_CCRL_CER_E11_SHIFT         (0x0000000BU)
+#define EDMA3_CCRL_CER_E11_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E10_MASK          (0x00000400u)
-#define EDMA3_CCRL_CER_E10_SHIFT         (0x0000000Au)
-#define EDMA3_CCRL_CER_E10_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_CER_E10_MASK          (0x00000400U)
+#define EDMA3_CCRL_CER_E10_SHIFT         (0x0000000AU)
+#define EDMA3_CCRL_CER_E10_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_CER_E9_MASK           (0x00000200u)
-#define EDMA3_CCRL_CER_E9_SHIFT          (0x00000009u)
-#define EDMA3_CCRL_CER_E9_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CER_E9_MASK           (0x00000200U)
+#define EDMA3_CCRL_CER_E9_SHIFT          (0x00000009U)
+#define EDMA3_CCRL_CER_E9_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_CER_E8_MASK           (0x00000100u)
-#define EDMA3_CCRL_CER_E8_SHIFT          (0x00000008u)
-#define EDMA3_CCRL_CER_E8_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CER_E8_MASK           (0x00000100U)
+#define EDMA3_CCRL_CER_E8_SHIFT          (0x00000008U)
+#define EDMA3_CCRL_CER_E8_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_CER_E7_MASK           (0x00000080u)
-#define EDMA3_CCRL_CER_E7_SHIFT          (0x00000007u)
-#define EDMA3_CCRL_CER_E7_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CER_E7_MASK           (0x00000080U)
+#define EDMA3_CCRL_CER_E7_SHIFT          (0x00000007U)
+#define EDMA3_CCRL_CER_E7_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_CER_E6_MASK           (0x00000040u)
-#define EDMA3_CCRL_CER_E6_SHIFT          (0x00000006u)
-#define EDMA3_CCRL_CER_E6_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CER_E6_MASK           (0x00000040U)
+#define EDMA3_CCRL_CER_E6_SHIFT          (0x00000006U)
+#define EDMA3_CCRL_CER_E6_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_CER_E5_MASK           (0x00000020u)
-#define EDMA3_CCRL_CER_E5_SHIFT          (0x00000005u)
-#define EDMA3_CCRL_CER_E5_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CER_E5_MASK           (0x00000020U)
+#define EDMA3_CCRL_CER_E5_SHIFT          (0x00000005U)
+#define EDMA3_CCRL_CER_E5_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_CER_E4_MASK           (0x00000010u)
-#define EDMA3_CCRL_CER_E4_SHIFT          (0x00000004u)
-#define EDMA3_CCRL_CER_E4_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CER_E4_MASK           (0x00000010U)
+#define EDMA3_CCRL_CER_E4_SHIFT          (0x00000004U)
+#define EDMA3_CCRL_CER_E4_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_CER_E3_MASK           (0x00000008u)
-#define EDMA3_CCRL_CER_E3_SHIFT          (0x00000003u)
-#define EDMA3_CCRL_CER_E3_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CER_E3_MASK           (0x00000008U)
+#define EDMA3_CCRL_CER_E3_SHIFT          (0x00000003U)
+#define EDMA3_CCRL_CER_E3_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_CER_E2_MASK           (0x00000004u)
-#define EDMA3_CCRL_CER_E2_SHIFT          (0x00000002u)
-#define EDMA3_CCRL_CER_E2_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CER_E2_MASK           (0x00000004U)
+#define EDMA3_CCRL_CER_E2_SHIFT          (0x00000002U)
+#define EDMA3_CCRL_CER_E2_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_CER_E1_MASK           (0x00000002u)
-#define EDMA3_CCRL_CER_E1_SHIFT          (0x00000001u)
-#define EDMA3_CCRL_CER_E1_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CER_E1_MASK           (0x00000002U)
+#define EDMA3_CCRL_CER_E1_SHIFT          (0x00000001U)
+#define EDMA3_CCRL_CER_E1_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_CER_E0_MASK           (0x00000001u)
-#define EDMA3_CCRL_CER_E0_SHIFT          (0x00000000u)
-#define EDMA3_CCRL_CER_E0_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_CER_E0_MASK           (0x00000001U)
+#define EDMA3_CCRL_CER_E0_SHIFT          (0x00000000U)
+#define EDMA3_CCRL_CER_E0_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_CER_RESETVAL          (0x00000000u)
+#define EDMA3_CCRL_CER_RESETVAL          (0x00000000U)
 
 /* CERH */
 
-#define EDMA3_CCRL_CERH_E63_MASK         (0x80000000u)
-#define EDMA3_CCRL_CERH_E63_SHIFT        (0x0000001Fu)
-#define EDMA3_CCRL_CERH_E63_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E63_MASK         (0x80000000U)
+#define EDMA3_CCRL_CERH_E63_SHIFT        (0x0000001FU)
+#define EDMA3_CCRL_CERH_E63_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E62_MASK         (0x40000000u)
-#define EDMA3_CCRL_CERH_E62_SHIFT        (0x0000001Eu)
-#define EDMA3_CCRL_CERH_E62_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E62_MASK         (0x40000000U)
+#define EDMA3_CCRL_CERH_E62_SHIFT        (0x0000001EU)
+#define EDMA3_CCRL_CERH_E62_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E61_MASK         (0x20000000u)
-#define EDMA3_CCRL_CERH_E61_SHIFT        (0x0000001Du)
-#define EDMA3_CCRL_CERH_E61_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E61_MASK         (0x20000000U)
+#define EDMA3_CCRL_CERH_E61_SHIFT        (0x0000001DU)
+#define EDMA3_CCRL_CERH_E61_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E60_MASK         (0x10000000u)
-#define EDMA3_CCRL_CERH_E60_SHIFT        (0x0000001Cu)
-#define EDMA3_CCRL_CERH_E60_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E60_MASK         (0x10000000U)
+#define EDMA3_CCRL_CERH_E60_SHIFT        (0x0000001CU)
+#define EDMA3_CCRL_CERH_E60_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E59_MASK         (0x08000000u)
-#define EDMA3_CCRL_CERH_E59_SHIFT        (0x0000001Bu)
-#define EDMA3_CCRL_CERH_E59_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E59_MASK         (0x08000000U)
+#define EDMA3_CCRL_CERH_E59_SHIFT        (0x0000001BU)
+#define EDMA3_CCRL_CERH_E59_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E58_MASK         (0x04000000u)
-#define EDMA3_CCRL_CERH_E58_SHIFT        (0x0000001Au)
-#define EDMA3_CCRL_CERH_E58_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E58_MASK         (0x04000000U)
+#define EDMA3_CCRL_CERH_E58_SHIFT        (0x0000001AU)
+#define EDMA3_CCRL_CERH_E58_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E57_MASK         (0x02000000u)
-#define EDMA3_CCRL_CERH_E57_SHIFT        (0x00000019u)
-#define EDMA3_CCRL_CERH_E57_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E57_MASK         (0x02000000U)
+#define EDMA3_CCRL_CERH_E57_SHIFT        (0x00000019U)
+#define EDMA3_CCRL_CERH_E57_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E56_MASK         (0x01000000u)
-#define EDMA3_CCRL_CERH_E56_SHIFT        (0x00000018u)
-#define EDMA3_CCRL_CERH_E56_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E56_MASK         (0x01000000U)
+#define EDMA3_CCRL_CERH_E56_SHIFT        (0x00000018U)
+#define EDMA3_CCRL_CERH_E56_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E55_MASK         (0x00800000u)
-#define EDMA3_CCRL_CERH_E55_SHIFT        (0x00000017u)
-#define EDMA3_CCRL_CERH_E55_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E55_MASK         (0x00800000U)
+#define EDMA3_CCRL_CERH_E55_SHIFT        (0x00000017U)
+#define EDMA3_CCRL_CERH_E55_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E54_MASK         (0x00400000u)
-#define EDMA3_CCRL_CERH_E54_SHIFT        (0x00000016u)
-#define EDMA3_CCRL_CERH_E54_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E54_MASK         (0x00400000U)
+#define EDMA3_CCRL_CERH_E54_SHIFT        (0x00000016U)
+#define EDMA3_CCRL_CERH_E54_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E53_MASK         (0x00200000u)
-#define EDMA3_CCRL_CERH_E53_SHIFT        (0x00000015u)
-#define EDMA3_CCRL_CERH_E53_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E53_MASK         (0x00200000U)
+#define EDMA3_CCRL_CERH_E53_SHIFT        (0x00000015U)
+#define EDMA3_CCRL_CERH_E53_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E52_MASK         (0x00100000u)
-#define EDMA3_CCRL_CERH_E52_SHIFT        (0x00000014u)
-#define EDMA3_CCRL_CERH_E52_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E52_MASK         (0x00100000U)
+#define EDMA3_CCRL_CERH_E52_SHIFT        (0x00000014U)
+#define EDMA3_CCRL_CERH_E52_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E51_MASK         (0x00080000u)
-#define EDMA3_CCRL_CERH_E51_SHIFT        (0x00000013u)
-#define EDMA3_CCRL_CERH_E51_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E51_MASK         (0x00080000U)
+#define EDMA3_CCRL_CERH_E51_SHIFT        (0x00000013U)
+#define EDMA3_CCRL_CERH_E51_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E50_MASK         (0x00040000u)
-#define EDMA3_CCRL_CERH_E50_SHIFT        (0x00000012u)
-#define EDMA3_CCRL_CERH_E50_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E50_MASK         (0x00040000U)
+#define EDMA3_CCRL_CERH_E50_SHIFT        (0x00000012U)
+#define EDMA3_CCRL_CERH_E50_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E49_MASK         (0x00020000u)
-#define EDMA3_CCRL_CERH_E49_SHIFT        (0x00000011u)
-#define EDMA3_CCRL_CERH_E49_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E49_MASK         (0x00020000U)
+#define EDMA3_CCRL_CERH_E49_SHIFT        (0x00000011U)
+#define EDMA3_CCRL_CERH_E49_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E48_MASK         (0x00010000u)
-#define EDMA3_CCRL_CERH_E48_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_CERH_E48_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E48_MASK         (0x00010000U)
+#define EDMA3_CCRL_CERH_E48_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_CERH_E48_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E47_MASK         (0x00008000u)
-#define EDMA3_CCRL_CERH_E47_SHIFT        (0x0000000Fu)
-#define EDMA3_CCRL_CERH_E47_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E47_MASK         (0x00008000U)
+#define EDMA3_CCRL_CERH_E47_SHIFT        (0x0000000FU)
+#define EDMA3_CCRL_CERH_E47_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E46_MASK         (0x00004000u)
-#define EDMA3_CCRL_CERH_E46_SHIFT        (0x0000000Eu)
-#define EDMA3_CCRL_CERH_E46_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E46_MASK         (0x00004000U)
+#define EDMA3_CCRL_CERH_E46_SHIFT        (0x0000000EU)
+#define EDMA3_CCRL_CERH_E46_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E45_MASK         (0x00002000u)
-#define EDMA3_CCRL_CERH_E45_SHIFT        (0x0000000Du)
-#define EDMA3_CCRL_CERH_E45_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E45_MASK         (0x00002000U)
+#define EDMA3_CCRL_CERH_E45_SHIFT        (0x0000000DU)
+#define EDMA3_CCRL_CERH_E45_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E44_MASK         (0x00001000u)
-#define EDMA3_CCRL_CERH_E44_SHIFT        (0x0000000Cu)
-#define EDMA3_CCRL_CERH_E44_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E44_MASK         (0x00001000U)
+#define EDMA3_CCRL_CERH_E44_SHIFT        (0x0000000CU)
+#define EDMA3_CCRL_CERH_E44_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E43_MASK         (0x00000800u)
-#define EDMA3_CCRL_CERH_E43_SHIFT        (0x0000000Bu)
-#define EDMA3_CCRL_CERH_E43_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E43_MASK         (0x00000800U)
+#define EDMA3_CCRL_CERH_E43_SHIFT        (0x0000000BU)
+#define EDMA3_CCRL_CERH_E43_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E42_MASK         (0x00000400u)
-#define EDMA3_CCRL_CERH_E42_SHIFT        (0x0000000Au)
-#define EDMA3_CCRL_CERH_E42_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E42_MASK         (0x00000400U)
+#define EDMA3_CCRL_CERH_E42_SHIFT        (0x0000000AU)
+#define EDMA3_CCRL_CERH_E42_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E41_MASK         (0x00000200u)
-#define EDMA3_CCRL_CERH_E41_SHIFT        (0x00000009u)
-#define EDMA3_CCRL_CERH_E41_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E41_MASK         (0x00000200U)
+#define EDMA3_CCRL_CERH_E41_SHIFT        (0x00000009U)
+#define EDMA3_CCRL_CERH_E41_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E40_MASK         (0x00000100u)
-#define EDMA3_CCRL_CERH_E40_SHIFT        (0x00000008u)
-#define EDMA3_CCRL_CERH_E40_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E40_MASK         (0x00000100U)
+#define EDMA3_CCRL_CERH_E40_SHIFT        (0x00000008U)
+#define EDMA3_CCRL_CERH_E40_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E39_MASK         (0x00000080u)
-#define EDMA3_CCRL_CERH_E39_SHIFT        (0x00000007u)
-#define EDMA3_CCRL_CERH_E39_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E39_MASK         (0x00000080U)
+#define EDMA3_CCRL_CERH_E39_SHIFT        (0x00000007U)
+#define EDMA3_CCRL_CERH_E39_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E38_MASK         (0x00000040u)
-#define EDMA3_CCRL_CERH_E38_SHIFT        (0x00000006u)
-#define EDMA3_CCRL_CERH_E38_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E38_MASK         (0x00000040U)
+#define EDMA3_CCRL_CERH_E38_SHIFT        (0x00000006U)
+#define EDMA3_CCRL_CERH_E38_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E37_MASK         (0x00000020u)
-#define EDMA3_CCRL_CERH_E37_SHIFT        (0x00000005u)
-#define EDMA3_CCRL_CERH_E37_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E37_MASK         (0x00000020U)
+#define EDMA3_CCRL_CERH_E37_SHIFT        (0x00000005U)
+#define EDMA3_CCRL_CERH_E37_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E36_MASK         (0x00000010u)
-#define EDMA3_CCRL_CERH_E36_SHIFT        (0x00000004u)
-#define EDMA3_CCRL_CERH_E36_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E36_MASK         (0x00000010U)
+#define EDMA3_CCRL_CERH_E36_SHIFT        (0x00000004U)
+#define EDMA3_CCRL_CERH_E36_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E35_MASK         (0x00000008u)
-#define EDMA3_CCRL_CERH_E35_SHIFT        (0x00000003u)
-#define EDMA3_CCRL_CERH_E35_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E35_MASK         (0x00000008U)
+#define EDMA3_CCRL_CERH_E35_SHIFT        (0x00000003U)
+#define EDMA3_CCRL_CERH_E35_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E34_MASK         (0x00000004u)
-#define EDMA3_CCRL_CERH_E34_SHIFT        (0x00000002u)
-#define EDMA3_CCRL_CERH_E34_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E34_MASK         (0x00000004U)
+#define EDMA3_CCRL_CERH_E34_SHIFT        (0x00000002U)
+#define EDMA3_CCRL_CERH_E34_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E33_MASK         (0x00000002u)
-#define EDMA3_CCRL_CERH_E33_SHIFT        (0x00000001u)
-#define EDMA3_CCRL_CERH_E33_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E33_MASK         (0x00000002U)
+#define EDMA3_CCRL_CERH_E33_SHIFT        (0x00000001U)
+#define EDMA3_CCRL_CERH_E33_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_E32_MASK         (0x00000001u)
-#define EDMA3_CCRL_CERH_E32_SHIFT        (0x00000000u)
-#define EDMA3_CCRL_CERH_E32_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_CERH_E32_MASK         (0x00000001U)
+#define EDMA3_CCRL_CERH_E32_SHIFT        (0x00000000U)
+#define EDMA3_CCRL_CERH_E32_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_CERH_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_CERH_RESETVAL         (0x00000000U)
 
 /* EER */
 
-#define EDMA3_CCRL_EER_E31_MASK          (0x80000000u)
-#define EDMA3_CCRL_EER_E31_SHIFT         (0x0000001Fu)
-#define EDMA3_CCRL_EER_E31_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E31_MASK          (0x80000000U)
+#define EDMA3_CCRL_EER_E31_SHIFT         (0x0000001FU)
+#define EDMA3_CCRL_EER_E31_RESETVAL      (0x00000000U)
 
 /*----E31 Tokens----*/
-#define EDMA3_CCRL_EER_E31_              (0x00000001u)
+#define EDMA3_CCRL_EER_E31_              (0x00000001U)
 
-#define EDMA3_CCRL_EER_E30_MASK          (0x40000000u)
-#define EDMA3_CCRL_EER_E30_SHIFT         (0x0000001Eu)
-#define EDMA3_CCRL_EER_E30_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E30_MASK          (0x40000000U)
+#define EDMA3_CCRL_EER_E30_SHIFT         (0x0000001EU)
+#define EDMA3_CCRL_EER_E30_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E29_MASK          (0x20000000u)
-#define EDMA3_CCRL_EER_E29_SHIFT         (0x0000001Du)
-#define EDMA3_CCRL_EER_E29_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E29_MASK          (0x20000000U)
+#define EDMA3_CCRL_EER_E29_SHIFT         (0x0000001DU)
+#define EDMA3_CCRL_EER_E29_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E28_MASK          (0x10000000u)
-#define EDMA3_CCRL_EER_E28_SHIFT         (0x0000001Cu)
-#define EDMA3_CCRL_EER_E28_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E28_MASK          (0x10000000U)
+#define EDMA3_CCRL_EER_E28_SHIFT         (0x0000001CU)
+#define EDMA3_CCRL_EER_E28_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E27_MASK          (0x08000000u)
-#define EDMA3_CCRL_EER_E27_SHIFT         (0x0000001Bu)
-#define EDMA3_CCRL_EER_E27_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E27_MASK          (0x08000000U)
+#define EDMA3_CCRL_EER_E27_SHIFT         (0x0000001BU)
+#define EDMA3_CCRL_EER_E27_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E26_MASK          (0x04000000u)
-#define EDMA3_CCRL_EER_E26_SHIFT         (0x0000001Au)
-#define EDMA3_CCRL_EER_E26_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E26_MASK          (0x04000000U)
+#define EDMA3_CCRL_EER_E26_SHIFT         (0x0000001AU)
+#define EDMA3_CCRL_EER_E26_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E25_MASK          (0x02000000u)
-#define EDMA3_CCRL_EER_E25_SHIFT         (0x00000019u)
-#define EDMA3_CCRL_EER_E25_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E25_MASK          (0x02000000U)
+#define EDMA3_CCRL_EER_E25_SHIFT         (0x00000019U)
+#define EDMA3_CCRL_EER_E25_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E24_MASK          (0x01000000u)
-#define EDMA3_CCRL_EER_E24_SHIFT         (0x00000018u)
-#define EDMA3_CCRL_EER_E24_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E24_MASK          (0x01000000U)
+#define EDMA3_CCRL_EER_E24_SHIFT         (0x00000018U)
+#define EDMA3_CCRL_EER_E24_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E23_MASK          (0x00800000u)
-#define EDMA3_CCRL_EER_E23_SHIFT         (0x00000017u)
-#define EDMA3_CCRL_EER_E23_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E23_MASK          (0x00800000U)
+#define EDMA3_CCRL_EER_E23_SHIFT         (0x00000017U)
+#define EDMA3_CCRL_EER_E23_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E22_MASK          (0x00400000u)
-#define EDMA3_CCRL_EER_E22_SHIFT         (0x00000016u)
-#define EDMA3_CCRL_EER_E22_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E22_MASK          (0x00400000U)
+#define EDMA3_CCRL_EER_E22_SHIFT         (0x00000016U)
+#define EDMA3_CCRL_EER_E22_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E21_MASK          (0x00200000u)
-#define EDMA3_CCRL_EER_E21_SHIFT         (0x00000015u)
-#define EDMA3_CCRL_EER_E21_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E21_MASK          (0x00200000U)
+#define EDMA3_CCRL_EER_E21_SHIFT         (0x00000015U)
+#define EDMA3_CCRL_EER_E21_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E20_MASK          (0x00100000u)
-#define EDMA3_CCRL_EER_E20_SHIFT         (0x00000014u)
-#define EDMA3_CCRL_EER_E20_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E20_MASK          (0x00100000U)
+#define EDMA3_CCRL_EER_E20_SHIFT         (0x00000014U)
+#define EDMA3_CCRL_EER_E20_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E19_MASK          (0x00080000u)
-#define EDMA3_CCRL_EER_E19_SHIFT         (0x00000013u)
-#define EDMA3_CCRL_EER_E19_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E19_MASK          (0x00080000U)
+#define EDMA3_CCRL_EER_E19_SHIFT         (0x00000013U)
+#define EDMA3_CCRL_EER_E19_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E18_MASK          (0x00040000u)
-#define EDMA3_CCRL_EER_E18_SHIFT         (0x00000012u)
-#define EDMA3_CCRL_EER_E18_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E18_MASK          (0x00040000U)
+#define EDMA3_CCRL_EER_E18_SHIFT         (0x00000012U)
+#define EDMA3_CCRL_EER_E18_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E17_MASK          (0x00020000u)
-#define EDMA3_CCRL_EER_E17_SHIFT         (0x00000011u)
-#define EDMA3_CCRL_EER_E17_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E17_MASK          (0x00020000U)
+#define EDMA3_CCRL_EER_E17_SHIFT         (0x00000011U)
+#define EDMA3_CCRL_EER_E17_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E16_MASK          (0x00010000u)
-#define EDMA3_CCRL_EER_E16_SHIFT         (0x00000010u)
-#define EDMA3_CCRL_EER_E16_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E16_MASK          (0x00010000U)
+#define EDMA3_CCRL_EER_E16_SHIFT         (0x00000010U)
+#define EDMA3_CCRL_EER_E16_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E15_MASK          (0x00008000u)
-#define EDMA3_CCRL_EER_E15_SHIFT         (0x0000000Fu)
-#define EDMA3_CCRL_EER_E15_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E15_MASK          (0x00008000U)
+#define EDMA3_CCRL_EER_E15_SHIFT         (0x0000000FU)
+#define EDMA3_CCRL_EER_E15_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E14_MASK          (0x00004000u)
-#define EDMA3_CCRL_EER_E14_SHIFT         (0x0000000Eu)
-#define EDMA3_CCRL_EER_E14_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E14_MASK          (0x00004000U)
+#define EDMA3_CCRL_EER_E14_SHIFT         (0x0000000EU)
+#define EDMA3_CCRL_EER_E14_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E13_MASK          (0x00002000u)
-#define EDMA3_CCRL_EER_E13_SHIFT         (0x0000000Du)
-#define EDMA3_CCRL_EER_E13_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E13_MASK          (0x00002000U)
+#define EDMA3_CCRL_EER_E13_SHIFT         (0x0000000DU)
+#define EDMA3_CCRL_EER_E13_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E12_MASK          (0x00001000u)
-#define EDMA3_CCRL_EER_E12_SHIFT         (0x0000000Cu)
-#define EDMA3_CCRL_EER_E12_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E12_MASK          (0x00001000U)
+#define EDMA3_CCRL_EER_E12_SHIFT         (0x0000000CU)
+#define EDMA3_CCRL_EER_E12_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E11_MASK          (0x00000800u)
-#define EDMA3_CCRL_EER_E11_SHIFT         (0x0000000Bu)
-#define EDMA3_CCRL_EER_E11_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E11_MASK          (0x00000800U)
+#define EDMA3_CCRL_EER_E11_SHIFT         (0x0000000BU)
+#define EDMA3_CCRL_EER_E11_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E10_MASK          (0x00000400u)
-#define EDMA3_CCRL_EER_E10_SHIFT         (0x0000000Au)
-#define EDMA3_CCRL_EER_E10_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EER_E10_MASK          (0x00000400U)
+#define EDMA3_CCRL_EER_E10_SHIFT         (0x0000000AU)
+#define EDMA3_CCRL_EER_E10_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_EER_E9_MASK           (0x00000200u)
-#define EDMA3_CCRL_EER_E9_SHIFT          (0x00000009u)
-#define EDMA3_CCRL_EER_E9_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EER_E9_MASK           (0x00000200U)
+#define EDMA3_CCRL_EER_E9_SHIFT          (0x00000009U)
+#define EDMA3_CCRL_EER_E9_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EER_E8_MASK           (0x00000100u)
-#define EDMA3_CCRL_EER_E8_SHIFT          (0x00000008u)
-#define EDMA3_CCRL_EER_E8_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EER_E8_MASK           (0x00000100U)
+#define EDMA3_CCRL_EER_E8_SHIFT          (0x00000008U)
+#define EDMA3_CCRL_EER_E8_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EER_E7_MASK           (0x00000080u)
-#define EDMA3_CCRL_EER_E7_SHIFT          (0x00000007u)
-#define EDMA3_CCRL_EER_E7_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EER_E7_MASK           (0x00000080U)
+#define EDMA3_CCRL_EER_E7_SHIFT          (0x00000007U)
+#define EDMA3_CCRL_EER_E7_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EER_E6_MASK           (0x00000040u)
-#define EDMA3_CCRL_EER_E6_SHIFT          (0x00000006u)
-#define EDMA3_CCRL_EER_E6_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EER_E6_MASK           (0x00000040U)
+#define EDMA3_CCRL_EER_E6_SHIFT          (0x00000006U)
+#define EDMA3_CCRL_EER_E6_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EER_E5_MASK           (0x00000020u)
-#define EDMA3_CCRL_EER_E5_SHIFT          (0x00000005u)
-#define EDMA3_CCRL_EER_E5_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EER_E5_MASK           (0x00000020U)
+#define EDMA3_CCRL_EER_E5_SHIFT          (0x00000005U)
+#define EDMA3_CCRL_EER_E5_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EER_E4_MASK           (0x00000010u)
-#define EDMA3_CCRL_EER_E4_SHIFT          (0x00000004u)
-#define EDMA3_CCRL_EER_E4_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EER_E4_MASK           (0x00000010U)
+#define EDMA3_CCRL_EER_E4_SHIFT          (0x00000004U)
+#define EDMA3_CCRL_EER_E4_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EER_E3_MASK           (0x00000008u)
-#define EDMA3_CCRL_EER_E3_SHIFT          (0x00000003u)
-#define EDMA3_CCRL_EER_E3_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EER_E3_MASK           (0x00000008U)
+#define EDMA3_CCRL_EER_E3_SHIFT          (0x00000003U)
+#define EDMA3_CCRL_EER_E3_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EER_E2_MASK           (0x00000004u)
-#define EDMA3_CCRL_EER_E2_SHIFT          (0x00000002u)
-#define EDMA3_CCRL_EER_E2_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EER_E2_MASK           (0x00000004U)
+#define EDMA3_CCRL_EER_E2_SHIFT          (0x00000002U)
+#define EDMA3_CCRL_EER_E2_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EER_E1_MASK           (0x00000002u)
-#define EDMA3_CCRL_EER_E1_SHIFT          (0x00000001u)
-#define EDMA3_CCRL_EER_E1_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EER_E1_MASK           (0x00000002U)
+#define EDMA3_CCRL_EER_E1_SHIFT          (0x00000001U)
+#define EDMA3_CCRL_EER_E1_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EER_E0_MASK           (0x00000001u)
-#define EDMA3_CCRL_EER_E0_SHIFT          (0x00000000u)
-#define EDMA3_CCRL_EER_E0_RESETVAL       (0x00000000u)
+#define EDMA3_CCRL_EER_E0_MASK           (0x00000001U)
+#define EDMA3_CCRL_EER_E0_SHIFT          (0x00000000U)
+#define EDMA3_CCRL_EER_E0_RESETVAL       (0x00000000U)
 
-#define EDMA3_CCRL_EER_RESETVAL          (0x00000000u)
+#define EDMA3_CCRL_EER_RESETVAL          (0x00000000U)
 
 /* EERH */
 
-#define EDMA3_CCRL_EERH_E63_MASK         (0x80000000u)
-#define EDMA3_CCRL_EERH_E63_SHIFT        (0x0000001Fu)
-#define EDMA3_CCRL_EERH_E63_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E63_MASK         (0x80000000U)
+#define EDMA3_CCRL_EERH_E63_SHIFT        (0x0000001FU)
+#define EDMA3_CCRL_EERH_E63_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E62_MASK         (0x40000000u)
-#define EDMA3_CCRL_EERH_E62_SHIFT        (0x0000001Eu)
-#define EDMA3_CCRL_EERH_E62_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E62_MASK         (0x40000000U)
+#define EDMA3_CCRL_EERH_E62_SHIFT        (0x0000001EU)
+#define EDMA3_CCRL_EERH_E62_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E61_MASK         (0x20000000u)
-#define EDMA3_CCRL_EERH_E61_SHIFT        (0x0000001Du)
-#define EDMA3_CCRL_EERH_E61_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E61_MASK         (0x20000000U)
+#define EDMA3_CCRL_EERH_E61_SHIFT        (0x0000001DU)
+#define EDMA3_CCRL_EERH_E61_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E60_MASK         (0x10000000u)
-#define EDMA3_CCRL_EERH_E60_SHIFT        (0x0000001Cu)
-#define EDMA3_CCRL_EERH_E60_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E60_MASK         (0x10000000U)
+#define EDMA3_CCRL_EERH_E60_SHIFT        (0x0000001CU)
+#define EDMA3_CCRL_EERH_E60_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E59_MASK         (0x08000000u)
-#define EDMA3_CCRL_EERH_E59_SHIFT        (0x0000001Bu)
-#define EDMA3_CCRL_EERH_E59_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E59_MASK         (0x08000000U)
+#define EDMA3_CCRL_EERH_E59_SHIFT        (0x0000001BU)
+#define EDMA3_CCRL_EERH_E59_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E58_MASK         (0x04000000u)
-#define EDMA3_CCRL_EERH_E58_SHIFT        (0x0000001Au)
-#define EDMA3_CCRL_EERH_E58_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E58_MASK         (0x04000000U)
+#define EDMA3_CCRL_EERH_E58_SHIFT        (0x0000001AU)
+#define EDMA3_CCRL_EERH_E58_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E57_MASK         (0x02000000u)
-#define EDMA3_CCRL_EERH_E57_SHIFT        (0x00000019u)
-#define EDMA3_CCRL_EERH_E57_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E57_MASK         (0x02000000U)
+#define EDMA3_CCRL_EERH_E57_SHIFT        (0x00000019U)
+#define EDMA3_CCRL_EERH_E57_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E56_MASK         (0x01000000u)
-#define EDMA3_CCRL_EERH_E56_SHIFT        (0x00000018u)
-#define EDMA3_CCRL_EERH_E56_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E56_MASK         (0x01000000U)
+#define EDMA3_CCRL_EERH_E56_SHIFT        (0x00000018U)
+#define EDMA3_CCRL_EERH_E56_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E55_MASK         (0x00800000u)
-#define EDMA3_CCRL_EERH_E55_SHIFT        (0x00000017u)
-#define EDMA3_CCRL_EERH_E55_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E55_MASK         (0x00800000U)
+#define EDMA3_CCRL_EERH_E55_SHIFT        (0x00000017U)
+#define EDMA3_CCRL_EERH_E55_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E54_MASK         (0x00400000u)
-#define EDMA3_CCRL_EERH_E54_SHIFT        (0x00000016u)
-#define EDMA3_CCRL_EERH_E54_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E54_MASK         (0x00400000U)
+#define EDMA3_CCRL_EERH_E54_SHIFT        (0x00000016U)
+#define EDMA3_CCRL_EERH_E54_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E53_MASK         (0x00200000u)
-#define EDMA3_CCRL_EERH_E53_SHIFT        (0x00000015u)
-#define EDMA3_CCRL_EERH_E53_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E53_MASK         (0x00200000U)
+#define EDMA3_CCRL_EERH_E53_SHIFT        (0x00000015U)
+#define EDMA3_CCRL_EERH_E53_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E52_MASK         (0x00100000u)
-#define EDMA3_CCRL_EERH_E52_SHIFT        (0x00000014u)
-#define EDMA3_CCRL_EERH_E52_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E52_MASK         (0x00100000U)
+#define EDMA3_CCRL_EERH_E52_SHIFT        (0x00000014U)
+#define EDMA3_CCRL_EERH_E52_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E51_MASK         (0x00080000u)
-#define EDMA3_CCRL_EERH_E51_SHIFT        (0x00000013u)
-#define EDMA3_CCRL_EERH_E51_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E51_MASK         (0x00080000U)
+#define EDMA3_CCRL_EERH_E51_SHIFT        (0x00000013U)
+#define EDMA3_CCRL_EERH_E51_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E50_MASK         (0x00040000u)
-#define EDMA3_CCRL_EERH_E50_SHIFT        (0x00000012u)
-#define EDMA3_CCRL_EERH_E50_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E50_MASK         (0x00040000U)
+#define EDMA3_CCRL_EERH_E50_SHIFT        (0x00000012U)
+#define EDMA3_CCRL_EERH_E50_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E49_MASK         (0x00020000u)
-#define EDMA3_CCRL_EERH_E49_SHIFT        (0x00000011u)
-#define EDMA3_CCRL_EERH_E49_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E49_MASK         (0x00020000U)
+#define EDMA3_CCRL_EERH_E49_SHIFT        (0x00000011U)
+#define EDMA3_CCRL_EERH_E49_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E48_MASK         (0x00010000u)
-#define EDMA3_CCRL_EERH_E48_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_EERH_E48_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E48_MASK         (0x00010000U)
+#define EDMA3_CCRL_EERH_E48_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_EERH_E48_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E47_MASK         (0x00008000u)
-#define EDMA3_CCRL_EERH_E47_SHIFT        (0x0000000Fu)
-#define EDMA3_CCRL_EERH_E47_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E47_MASK         (0x00008000U)
+#define EDMA3_CCRL_EERH_E47_SHIFT        (0x0000000FU)
+#define EDMA3_CCRL_EERH_E47_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E46_MASK         (0x00004000u)
-#define EDMA3_CCRL_EERH_E46_SHIFT        (0x0000000Eu)
-#define EDMA3_CCRL_EERH_E46_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E46_MASK         (0x00004000U)
+#define EDMA3_CCRL_EERH_E46_SHIFT        (0x0000000EU)
+#define EDMA3_CCRL_EERH_E46_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E45_MASK         (0x00002000u)
-#define EDMA3_CCRL_EERH_E45_SHIFT        (0x0000000Du)
-#define EDMA3_CCRL_EERH_E45_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E45_MASK         (0x00002000U)
+#define EDMA3_CCRL_EERH_E45_SHIFT        (0x0000000DU)
+#define EDMA3_CCRL_EERH_E45_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E44_MASK         (0x00001000u)
-#define EDMA3_CCRL_EERH_E44_SHIFT        (0x0000000Cu)
-#define EDMA3_CCRL_EERH_E44_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E44_MASK         (0x00001000U)
+#define EDMA3_CCRL_EERH_E44_SHIFT        (0x0000000CU)
+#define EDMA3_CCRL_EERH_E44_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E43_MASK         (0x00000800u)
-#define EDMA3_CCRL_EERH_E43_SHIFT        (0x0000000Bu)
-#define EDMA3_CCRL_EERH_E43_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E43_MASK         (0x00000800U)
+#define EDMA3_CCRL_EERH_E43_SHIFT        (0x0000000BU)
+#define EDMA3_CCRL_EERH_E43_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E42_MASK         (0x00000400u)
-#define EDMA3_CCRL_EERH_E42_SHIFT        (0x0000000Au)
-#define EDMA3_CCRL_EERH_E42_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E42_MASK         (0x00000400U)
+#define EDMA3_CCRL_EERH_E42_SHIFT        (0x0000000AU)
+#define EDMA3_CCRL_EERH_E42_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E41_MASK         (0x00000200u)
-#define EDMA3_CCRL_EERH_E41_SHIFT        (0x00000009u)
-#define EDMA3_CCRL_EERH_E41_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E41_MASK         (0x00000200U)
+#define EDMA3_CCRL_EERH_E41_SHIFT        (0x00000009U)
+#define EDMA3_CCRL_EERH_E41_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E40_MASK         (0x00000100u)
-#define EDMA3_CCRL_EERH_E40_SHIFT        (0x00000008u)
-#define EDMA3_CCRL_EERH_E40_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E40_MASK         (0x00000100U)
+#define EDMA3_CCRL_EERH_E40_SHIFT        (0x00000008U)
+#define EDMA3_CCRL_EERH_E40_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E39_MASK         (0x00000080u)
-#define EDMA3_CCRL_EERH_E39_SHIFT        (0x00000007u)
-#define EDMA3_CCRL_EERH_E39_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E39_MASK         (0x00000080U)
+#define EDMA3_CCRL_EERH_E39_SHIFT        (0x00000007U)
+#define EDMA3_CCRL_EERH_E39_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E38_MASK         (0x00000040u)
-#define EDMA3_CCRL_EERH_E38_SHIFT        (0x00000006u)
-#define EDMA3_CCRL_EERH_E38_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E38_MASK         (0x00000040U)
+#define EDMA3_CCRL_EERH_E38_SHIFT        (0x00000006U)
+#define EDMA3_CCRL_EERH_E38_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E37_MASK         (0x00000020u)
-#define EDMA3_CCRL_EERH_E37_SHIFT        (0x00000005u)
-#define EDMA3_CCRL_EERH_E37_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E37_MASK         (0x00000020U)
+#define EDMA3_CCRL_EERH_E37_SHIFT        (0x00000005U)
+#define EDMA3_CCRL_EERH_E37_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E36_MASK         (0x00000010u)
-#define EDMA3_CCRL_EERH_E36_SHIFT        (0x00000004u)
-#define EDMA3_CCRL_EERH_E36_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E36_MASK         (0x00000010U)
+#define EDMA3_CCRL_EERH_E36_SHIFT        (0x00000004U)
+#define EDMA3_CCRL_EERH_E36_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E35_MASK         (0x00000008u)
-#define EDMA3_CCRL_EERH_E35_SHIFT        (0x00000003u)
-#define EDMA3_CCRL_EERH_E35_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E35_MASK         (0x00000008U)
+#define EDMA3_CCRL_EERH_E35_SHIFT        (0x00000003U)
+#define EDMA3_CCRL_EERH_E35_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E34_MASK         (0x00000004u)
-#define EDMA3_CCRL_EERH_E34_SHIFT        (0x00000002u)
-#define EDMA3_CCRL_EERH_E34_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E34_MASK         (0x00000004U)
+#define EDMA3_CCRL_EERH_E34_SHIFT        (0x00000002U)
+#define EDMA3_CCRL_EERH_E34_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E33_MASK         (0x00000002u)
-#define EDMA3_CCRL_EERH_E33_SHIFT        (0x00000001u)
-#define EDMA3_CCRL_EERH_E33_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E33_MASK         (0x00000002U)
+#define EDMA3_CCRL_EERH_E33_SHIFT        (0x00000001U)
+#define EDMA3_CCRL_EERH_E33_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_E32_MASK         (0x00000001u)
-#define EDMA3_CCRL_EERH_E32_SHIFT        (0x00000000u)
-#define EDMA3_CCRL_EERH_E32_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EERH_E32_MASK         (0x00000001U)
+#define EDMA3_CCRL_EERH_E32_SHIFT        (0x00000000U)
+#define EDMA3_CCRL_EERH_E32_RESETVAL     (0x00000000U)
 
-#define EDMA3_CCRL_EERH_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_EERH_RESETVAL         (0x00000000U)
 
 /* EECR */
 
-#define EDMA3_CCRL_EECR_E31_MASK         (0x80000000u)
-#define EDMA3_CCRL_EECR_E31_SHIFT        (0x0000001Fu)
-#define EDMA3_CCRL_EECR_E31_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E31_MASK         (0x80000000U)
+#define EDMA3_CCRL_EECR_E31_SHIFT        (0x0000001FU)
+#define EDMA3_CCRL_EECR_E31_RESETVAL     (0x00000000U)
 
 /*----E31 Tokens----*/
-#define EDMA3_CCRL_EECR_E31_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E31_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E30_MASK         (0x40000000u)
-#define EDMA3_CCRL_EECR_E30_SHIFT        (0x0000001Eu)
-#define EDMA3_CCRL_EECR_E30_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E30_MASK         (0x40000000U)
+#define EDMA3_CCRL_EECR_E30_SHIFT        (0x0000001EU)
+#define EDMA3_CCRL_EECR_E30_RESETVAL     (0x00000000U)
 
 /*----E30 Tokens----*/
-#define EDMA3_CCRL_EECR_E30_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E30_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E29_MASK         (0x20000000u)
-#define EDMA3_CCRL_EECR_E29_SHIFT        (0x0000001Du)
-#define EDMA3_CCRL_EECR_E29_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E29_MASK         (0x20000000U)
+#define EDMA3_CCRL_EECR_E29_SHIFT        (0x0000001DU)
+#define EDMA3_CCRL_EECR_E29_RESETVAL     (0x00000000U)
 
 /*----E29 Tokens----*/
-#define EDMA3_CCRL_EECR_E29_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E29_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E28_MASK         (0x10000000u)
-#define EDMA3_CCRL_EECR_E28_SHIFT        (0x0000001Cu)
-#define EDMA3_CCRL_EECR_E28_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E28_MASK         (0x10000000U)
+#define EDMA3_CCRL_EECR_E28_SHIFT        (0x0000001CU)
+#define EDMA3_CCRL_EECR_E28_RESETVAL     (0x00000000U)
 
 /*----E28 Tokens----*/
-#define EDMA3_CCRL_EECR_E28_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E28_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E27_MASK         (0x08000000u)
-#define EDMA3_CCRL_EECR_E27_SHIFT        (0x0000001Bu)
-#define EDMA3_CCRL_EECR_E27_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E27_MASK         (0x08000000U)
+#define EDMA3_CCRL_EECR_E27_SHIFT        (0x0000001BU)
+#define EDMA3_CCRL_EECR_E27_RESETVAL     (0x00000000U)
 
 /*----E27 Tokens----*/
-#define EDMA3_CCRL_EECR_E27_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E27_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E26_MASK         (0x04000000u)
-#define EDMA3_CCRL_EECR_E26_SHIFT        (0x0000001Au)
-#define EDMA3_CCRL_EECR_E26_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E26_MASK         (0x04000000U)
+#define EDMA3_CCRL_EECR_E26_SHIFT        (0x0000001AU)
+#define EDMA3_CCRL_EECR_E26_RESETVAL     (0x00000000U)
 
 /*----E26 Tokens----*/
-#define EDMA3_CCRL_EECR_E26_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E26_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E25_MASK         (0x02000000u)
-#define EDMA3_CCRL_EECR_E25_SHIFT        (0x00000019u)
-#define EDMA3_CCRL_EECR_E25_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E25_MASK         (0x02000000U)
+#define EDMA3_CCRL_EECR_E25_SHIFT        (0x00000019U)
+#define EDMA3_CCRL_EECR_E25_RESETVAL     (0x00000000U)
 
 /*----E25 Tokens----*/
-#define EDMA3_CCRL_EECR_E25_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E25_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E24_MASK         (0x01000000u)
-#define EDMA3_CCRL_EECR_E24_SHIFT        (0x00000018u)
-#define EDMA3_CCRL_EECR_E24_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E24_MASK         (0x01000000U)
+#define EDMA3_CCRL_EECR_E24_SHIFT        (0x00000018U)
+#define EDMA3_CCRL_EECR_E24_RESETVAL     (0x00000000U)
 
 /*----E24 Tokens----*/
-#define EDMA3_CCRL_EECR_E24_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E24_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E23_MASK         (0x00800000u)
-#define EDMA3_CCRL_EECR_E23_SHIFT        (0x00000017u)
-#define EDMA3_CCRL_EECR_E23_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E23_MASK         (0x00800000U)
+#define EDMA3_CCRL_EECR_E23_SHIFT        (0x00000017U)
+#define EDMA3_CCRL_EECR_E23_RESETVAL     (0x00000000U)
 
 /*----E23 Tokens----*/
-#define EDMA3_CCRL_EECR_E23_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E23_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E22_MASK         (0x00400000u)
-#define EDMA3_CCRL_EECR_E22_SHIFT        (0x00000016u)
-#define EDMA3_CCRL_EECR_E22_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E22_MASK         (0x00400000U)
+#define EDMA3_CCRL_EECR_E22_SHIFT        (0x00000016U)
+#define EDMA3_CCRL_EECR_E22_RESETVAL     (0x00000000U)
 
 /*----E22 Tokens----*/
-#define EDMA3_CCRL_EECR_E22_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E22_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E21_MASK         (0x00200000u)
-#define EDMA3_CCRL_EECR_E21_SHIFT        (0x00000015u)
-#define EDMA3_CCRL_EECR_E21_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E21_MASK         (0x00200000U)
+#define EDMA3_CCRL_EECR_E21_SHIFT        (0x00000015U)
+#define EDMA3_CCRL_EECR_E21_RESETVAL     (0x00000000U)
 
 /*----E21 Tokens----*/
-#define EDMA3_CCRL_EECR_E21_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E21_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E20_MASK         (0x00100000u)
-#define EDMA3_CCRL_EECR_E20_SHIFT        (0x00000014u)
-#define EDMA3_CCRL_EECR_E20_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E20_MASK         (0x00100000U)
+#define EDMA3_CCRL_EECR_E20_SHIFT        (0x00000014U)
+#define EDMA3_CCRL_EECR_E20_RESETVAL     (0x00000000U)
 
 /*----E20 Tokens----*/
-#define EDMA3_CCRL_EECR_E20_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E20_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E19_MASK         (0x00080000u)
-#define EDMA3_CCRL_EECR_E19_SHIFT        (0x00000013u)
-#define EDMA3_CCRL_EECR_E19_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E19_MASK         (0x00080000U)
+#define EDMA3_CCRL_EECR_E19_SHIFT        (0x00000013U)
+#define EDMA3_CCRL_EECR_E19_RESETVAL     (0x00000000U)
 
 /*----E19 Tokens----*/
-#define EDMA3_CCRL_EECR_E19_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E19_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E18_MASK         (0x00040000u)
-#define EDMA3_CCRL_EECR_E18_SHIFT        (0x00000012u)
-#define EDMA3_CCRL_EECR_E18_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E18_MASK         (0x00040000U)
+#define EDMA3_CCRL_EECR_E18_SHIFT        (0x00000012U)
+#define EDMA3_CCRL_EECR_E18_RESETVAL     (0x00000000U)
 
 /*----E18 Tokens----*/
-#define EDMA3_CCRL_EECR_E18_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E18_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E17_MASK         (0x00020000u)
-#define EDMA3_CCRL_EECR_E17_SHIFT        (0x00000011u)
-#define EDMA3_CCRL_EECR_E17_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E17_MASK         (0x00020000U)
+#define EDMA3_CCRL_EECR_E17_SHIFT        (0x00000011U)
+#define EDMA3_CCRL_EECR_E17_RESETVAL     (0x00000000U)
 
 /*----E17 Tokens----*/
-#define EDMA3_CCRL_EECR_E17_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E17_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E16_MASK         (0x00010000u)
-#define EDMA3_CCRL_EECR_E16_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_EECR_E16_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E16_MASK         (0x00010000U)
+#define EDMA3_CCRL_EECR_E16_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_EECR_E16_RESETVAL     (0x00000000U)
 
 /*----E16 Tokens----*/
-#define EDMA3_CCRL_EECR_E16_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E16_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E15_MASK         (0x00008000u)
-#define EDMA3_CCRL_EECR_E15_SHIFT        (0x0000000Fu)
-#define EDMA3_CCRL_EECR_E15_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E15_MASK         (0x00008000U)
+#define EDMA3_CCRL_EECR_E15_SHIFT        (0x0000000FU)
+#define EDMA3_CCRL_EECR_E15_RESETVAL     (0x00000000U)
 
 /*----E15 Tokens----*/
-#define EDMA3_CCRL_EECR_E15_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E15_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E14_MASK         (0x00004000u)
-#define EDMA3_CCRL_EECR_E14_SHIFT        (0x0000000Eu)
-#define EDMA3_CCRL_EECR_E14_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E14_MASK         (0x00004000U)
+#define EDMA3_CCRL_EECR_E14_SHIFT        (0x0000000EU)
+#define EDMA3_CCRL_EECR_E14_RESETVAL     (0x00000000U)
 
 /*----E14 Tokens----*/
-#define EDMA3_CCRL_EECR_E14_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E14_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E13_MASK         (0x00002000u)
-#define EDMA3_CCRL_EECR_E13_SHIFT        (0x0000000Du)
-#define EDMA3_CCRL_EECR_E13_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E13_MASK         (0x00002000U)
+#define EDMA3_CCRL_EECR_E13_SHIFT        (0x0000000DU)
+#define EDMA3_CCRL_EECR_E13_RESETVAL     (0x00000000U)
 
 /*----E13 Tokens----*/
-#define EDMA3_CCRL_EECR_E13_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E13_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E12_MASK         (0x00001000u)
-#define EDMA3_CCRL_EECR_E12_SHIFT        (0x0000000Cu)
-#define EDMA3_CCRL_EECR_E12_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E12_MASK         (0x00001000U)
+#define EDMA3_CCRL_EECR_E12_SHIFT        (0x0000000CU)
+#define EDMA3_CCRL_EECR_E12_RESETVAL     (0x00000000U)
 
 /*----E12 Tokens----*/
-#define EDMA3_CCRL_EECR_E12_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E12_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E11_MASK         (0x00000800u)
-#define EDMA3_CCRL_EECR_E11_SHIFT        (0x0000000Bu)
-#define EDMA3_CCRL_EECR_E11_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E11_MASK         (0x00000800U)
+#define EDMA3_CCRL_EECR_E11_SHIFT        (0x0000000BU)
+#define EDMA3_CCRL_EECR_E11_RESETVAL     (0x00000000U)
 
 /*----E11 Tokens----*/
-#define EDMA3_CCRL_EECR_E11_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E11_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E10_MASK         (0x00000400u)
-#define EDMA3_CCRL_EECR_E10_SHIFT        (0x0000000Au)
-#define EDMA3_CCRL_EECR_E10_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EECR_E10_MASK         (0x00000400U)
+#define EDMA3_CCRL_EECR_E10_SHIFT        (0x0000000AU)
+#define EDMA3_CCRL_EECR_E10_RESETVAL     (0x00000000U)
 
 /*----E10 Tokens----*/
-#define EDMA3_CCRL_EECR_E10_CLEAR        (0x00000001u)
+#define EDMA3_CCRL_EECR_E10_CLEAR        (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E9_MASK          (0x00000200u)
-#define EDMA3_CCRL_EECR_E9_SHIFT         (0x00000009u)
-#define EDMA3_CCRL_EECR_E9_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EECR_E9_MASK          (0x00000200U)
+#define EDMA3_CCRL_EECR_E9_SHIFT         (0x00000009U)
+#define EDMA3_CCRL_EECR_E9_RESETVAL      (0x00000000U)
 
 /*----E9 Tokens----*/
-#define EDMA3_CCRL_EECR_E9_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_EECR_E9_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E8_MASK          (0x00000100u)
-#define EDMA3_CCRL_EECR_E8_SHIFT         (0x00000008u)
-#define EDMA3_CCRL_EECR_E8_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EECR_E8_MASK          (0x00000100U)
+#define EDMA3_CCRL_EECR_E8_SHIFT         (0x00000008U)
+#define EDMA3_CCRL_EECR_E8_RESETVAL      (0x00000000U)
 
 /*----E8 Tokens----*/
-#define EDMA3_CCRL_EECR_E8_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_EECR_E8_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E7_MASK          (0x00000080u)
-#define EDMA3_CCRL_EECR_E7_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_EECR_E7_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EECR_E7_MASK          (0x00000080U)
+#define EDMA3_CCRL_EECR_E7_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_EECR_E7_RESETVAL      (0x00000000U)
 
 /*----E7 Tokens----*/
-#define EDMA3_CCRL_EECR_E7_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_EECR_E7_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E6_MASK          (0x00000040u)
-#define EDMA3_CCRL_EECR_E6_SHIFT         (0x00000006u)
-#define EDMA3_CCRL_EECR_E6_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EECR_E6_MASK          (0x00000040U)
+#define EDMA3_CCRL_EECR_E6_SHIFT         (0x00000006U)
+#define EDMA3_CCRL_EECR_E6_RESETVAL      (0x00000000U)
 
 /*----E6 Tokens----*/
-#define EDMA3_CCRL_EECR_E6_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_EECR_E6_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E5_MASK          (0x00000020u)
-#define EDMA3_CCRL_EECR_E5_SHIFT         (0x00000005u)
-#define EDMA3_CCRL_EECR_E5_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EECR_E5_MASK          (0x00000020U)
+#define EDMA3_CCRL_EECR_E5_SHIFT         (0x00000005U)
+#define EDMA3_CCRL_EECR_E5_RESETVAL      (0x00000000U)
 
 /*----E5 Tokens----*/
-#define EDMA3_CCRL_EECR_E5_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_EECR_E5_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E4_MASK          (0x00000010u)
-#define EDMA3_CCRL_EECR_E4_SHIFT         (0x00000004u)
-#define EDMA3_CCRL_EECR_E4_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EECR_E4_MASK          (0x00000010U)
+#define EDMA3_CCRL_EECR_E4_SHIFT         (0x00000004U)
+#define EDMA3_CCRL_EECR_E4_RESETVAL      (0x00000000U)
 
 /*----E4 Tokens----*/
-#define EDMA3_CCRL_EECR_E4_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_EECR_E4_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E3_MASK          (0x00000008u)
-#define EDMA3_CCRL_EECR_E3_SHIFT         (0x00000003u)
-#define EDMA3_CCRL_EECR_E3_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EECR_E3_MASK          (0x00000008U)
+#define EDMA3_CCRL_EECR_E3_SHIFT         (0x00000003U)
+#define EDMA3_CCRL_EECR_E3_RESETVAL      (0x00000000U)
 
 /*----E3 Tokens----*/
-#define EDMA3_CCRL_EECR_E3_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_EECR_E3_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E2_MASK          (0x00000004u)
-#define EDMA3_CCRL_EECR_E2_SHIFT         (0x00000002u)
-#define EDMA3_CCRL_EECR_E2_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EECR_E2_MASK          (0x00000004U)
+#define EDMA3_CCRL_EECR_E2_SHIFT         (0x00000002U)
+#define EDMA3_CCRL_EECR_E2_RESETVAL      (0x00000000U)
 
 /*----E2 Tokens----*/
-#define EDMA3_CCRL_EECR_E2_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_EECR_E2_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E1_MASK          (0x00000002u)
-#define EDMA3_CCRL_EECR_E1_SHIFT         (0x00000001u)
-#define EDMA3_CCRL_EECR_E1_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EECR_E1_MASK          (0x00000002U)
+#define EDMA3_CCRL_EECR_E1_SHIFT         (0x00000001U)
+#define EDMA3_CCRL_EECR_E1_RESETVAL      (0x00000000U)
 
 /*----E1 Tokens----*/
-#define EDMA3_CCRL_EECR_E1_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_EECR_E1_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_EECR_E0_MASK          (0x00000001u)
-#define EDMA3_CCRL_EECR_E0_SHIFT         (0x00000000u)
-#define EDMA3_CCRL_EECR_E0_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EECR_E0_MASK          (0x00000001U)
+#define EDMA3_CCRL_EECR_E0_SHIFT         (0x00000000U)
+#define EDMA3_CCRL_EECR_E0_RESETVAL      (0x00000000U)
 
 /*----E0 Tokens----*/
-#define EDMA3_CCRL_EECR_E0_CLEAR         (0x00000001u)
+#define EDMA3_CCRL_EECR_E0_CLEAR         (0x00000001U)
 
-#define EDMA3_CCRL_EECR_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_EECR_RESETVAL         (0x00000000U)
 
 /* EECRH */
 
-#define EDMA3_CCRL_EECRH_E63_MASK        (0x80000000u)
-#define EDMA3_CCRL_EECRH_E63_SHIFT       (0x0000001Fu)
-#define EDMA3_CCRL_EECRH_E63_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E63_MASK        (0x80000000U)
+#define EDMA3_CCRL_EECRH_E63_SHIFT       (0x0000001FU)
+#define EDMA3_CCRL_EECRH_E63_RESETVAL    (0x00000000U)
 
 /*----E63 Tokens----*/
-#define EDMA3_CCRL_EECRH_E63_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E63_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E62_MASK        (0x40000000u)
-#define EDMA3_CCRL_EECRH_E62_SHIFT       (0x0000001Eu)
-#define EDMA3_CCRL_EECRH_E62_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E62_MASK        (0x40000000U)
+#define EDMA3_CCRL_EECRH_E62_SHIFT       (0x0000001EU)
+#define EDMA3_CCRL_EECRH_E62_RESETVAL    (0x00000000U)
 
 /*----E62 Tokens----*/
-#define EDMA3_CCRL_EECRH_E62_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E62_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E61_MASK        (0x20000000u)
-#define EDMA3_CCRL_EECRH_E61_SHIFT       (0x0000001Du)
-#define EDMA3_CCRL_EECRH_E61_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E61_MASK        (0x20000000U)
+#define EDMA3_CCRL_EECRH_E61_SHIFT       (0x0000001DU)
+#define EDMA3_CCRL_EECRH_E61_RESETVAL    (0x00000000U)
 
 /*----E61 Tokens----*/
-#define EDMA3_CCRL_EECRH_E61_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E61_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E60_MASK        (0x10000000u)
-#define EDMA3_CCRL_EECRH_E60_SHIFT       (0x0000001Cu)
-#define EDMA3_CCRL_EECRH_E60_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E60_MASK        (0x10000000U)
+#define EDMA3_CCRL_EECRH_E60_SHIFT       (0x0000001CU)
+#define EDMA3_CCRL_EECRH_E60_RESETVAL    (0x00000000U)
 
 /*----E60 Tokens----*/
-#define EDMA3_CCRL_EECRH_E60_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E60_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E59_MASK        (0x08000000u)
-#define EDMA3_CCRL_EECRH_E59_SHIFT       (0x0000001Bu)
-#define EDMA3_CCRL_EECRH_E59_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E59_MASK        (0x08000000U)
+#define EDMA3_CCRL_EECRH_E59_SHIFT       (0x0000001BU)
+#define EDMA3_CCRL_EECRH_E59_RESETVAL    (0x00000000U)
 
 /*----E59 Tokens----*/
-#define EDMA3_CCRL_EECRH_E59_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E59_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E58_MASK        (0x04000000u)
-#define EDMA3_CCRL_EECRH_E58_SHIFT       (0x0000001Au)
-#define EDMA3_CCRL_EECRH_E58_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E58_MASK        (0x04000000U)
+#define EDMA3_CCRL_EECRH_E58_SHIFT       (0x0000001AU)
+#define EDMA3_CCRL_EECRH_E58_RESETVAL    (0x00000000U)
 
 /*----E58 Tokens----*/
-#define EDMA3_CCRL_EECRH_E58_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E58_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E57_MASK        (0x02000000u)
-#define EDMA3_CCRL_EECRH_E57_SHIFT       (0x00000019u)
-#define EDMA3_CCRL_EECRH_E57_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E57_MASK        (0x02000000U)
+#define EDMA3_CCRL_EECRH_E57_SHIFT       (0x00000019U)
+#define EDMA3_CCRL_EECRH_E57_RESETVAL    (0x00000000U)
 
 /*----E57 Tokens----*/
-#define EDMA3_CCRL_EECRH_E57_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E57_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E56_MASK        (0x01000000u)
-#define EDMA3_CCRL_EECRH_E56_SHIFT       (0x00000018u)
-#define EDMA3_CCRL_EECRH_E56_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E56_MASK        (0x01000000U)
+#define EDMA3_CCRL_EECRH_E56_SHIFT       (0x00000018U)
+#define EDMA3_CCRL_EECRH_E56_RESETVAL    (0x00000000U)
 
 /*----E56 Tokens----*/
-#define EDMA3_CCRL_EECRH_E56_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E56_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E55_MASK        (0x00800000u)
-#define EDMA3_CCRL_EECRH_E55_SHIFT       (0x00000017u)
-#define EDMA3_CCRL_EECRH_E55_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E55_MASK        (0x00800000U)
+#define EDMA3_CCRL_EECRH_E55_SHIFT       (0x00000017U)
+#define EDMA3_CCRL_EECRH_E55_RESETVAL    (0x00000000U)
 
 /*----E55 Tokens----*/
-#define EDMA3_CCRL_EECRH_E55_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E55_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E54_MASK        (0x00400000u)
-#define EDMA3_CCRL_EECRH_E54_SHIFT       (0x00000016u)
-#define EDMA3_CCRL_EECRH_E54_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E54_MASK        (0x00400000U)
+#define EDMA3_CCRL_EECRH_E54_SHIFT       (0x00000016U)
+#define EDMA3_CCRL_EECRH_E54_RESETVAL    (0x00000000U)
 
 /*----E54 Tokens----*/
-#define EDMA3_CCRL_EECRH_E54_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E54_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E53_MASK        (0x00200000u)
-#define EDMA3_CCRL_EECRH_E53_SHIFT       (0x00000015u)
-#define EDMA3_CCRL_EECRH_E53_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E53_MASK        (0x00200000U)
+#define EDMA3_CCRL_EECRH_E53_SHIFT       (0x00000015U)
+#define EDMA3_CCRL_EECRH_E53_RESETVAL    (0x00000000U)
 
 /*----E53 Tokens----*/
-#define EDMA3_CCRL_EECRH_E53_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E53_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E52_MASK        (0x00100000u)
-#define EDMA3_CCRL_EECRH_E52_SHIFT       (0x00000014u)
-#define EDMA3_CCRL_EECRH_E52_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E52_MASK        (0x00100000U)
+#define EDMA3_CCRL_EECRH_E52_SHIFT       (0x00000014U)
+#define EDMA3_CCRL_EECRH_E52_RESETVAL    (0x00000000U)
 
 /*----E52 Tokens----*/
-#define EDMA3_CCRL_EECRH_E52_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E52_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E51_MASK        (0x00080000u)
-#define EDMA3_CCRL_EECRH_E51_SHIFT       (0x00000013u)
-#define EDMA3_CCRL_EECRH_E51_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E51_MASK        (0x00080000U)
+#define EDMA3_CCRL_EECRH_E51_SHIFT       (0x00000013U)
+#define EDMA3_CCRL_EECRH_E51_RESETVAL    (0x00000000U)
 
 /*----E51 Tokens----*/
-#define EDMA3_CCRL_EECRH_E51_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E51_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E50_MASK        (0x00040000u)
-#define EDMA3_CCRL_EECRH_E50_SHIFT       (0x00000012u)
-#define EDMA3_CCRL_EECRH_E50_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E50_MASK        (0x00040000U)
+#define EDMA3_CCRL_EECRH_E50_SHIFT       (0x00000012U)
+#define EDMA3_CCRL_EECRH_E50_RESETVAL    (0x00000000U)
 
 /*----E50 Tokens----*/
-#define EDMA3_CCRL_EECRH_E50_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E50_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E49_MASK        (0x00020000u)
-#define EDMA3_CCRL_EECRH_E49_SHIFT       (0x00000011u)
-#define EDMA3_CCRL_EECRH_E49_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E49_MASK        (0x00020000U)
+#define EDMA3_CCRL_EECRH_E49_SHIFT       (0x00000011U)
+#define EDMA3_CCRL_EECRH_E49_RESETVAL    (0x00000000U)
 
 /*----E49 Tokens----*/
-#define EDMA3_CCRL_EECRH_E49_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E49_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E48_MASK        (0x00010000u)
-#define EDMA3_CCRL_EECRH_E48_SHIFT       (0x00000010u)
-#define EDMA3_CCRL_EECRH_E48_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E48_MASK        (0x00010000U)
+#define EDMA3_CCRL_EECRH_E48_SHIFT       (0x00000010U)
+#define EDMA3_CCRL_EECRH_E48_RESETVAL    (0x00000000U)
 
 /*----E48 Tokens----*/
-#define EDMA3_CCRL_EECRH_E48_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E48_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E47_MASK        (0x00008000u)
-#define EDMA3_CCRL_EECRH_E47_SHIFT       (0x0000000Fu)
-#define EDMA3_CCRL_EECRH_E47_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E47_MASK        (0x00008000U)
+#define EDMA3_CCRL_EECRH_E47_SHIFT       (0x0000000FU)
+#define EDMA3_CCRL_EECRH_E47_RESETVAL    (0x00000000U)
 
 /*----E47 Tokens----*/
-#define EDMA3_CCRL_EECRH_E47_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E47_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E46_MASK        (0x00004000u)
-#define EDMA3_CCRL_EECRH_E46_SHIFT       (0x0000000Eu)
-#define EDMA3_CCRL_EECRH_E46_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E46_MASK        (0x00004000U)
+#define EDMA3_CCRL_EECRH_E46_SHIFT       (0x0000000EU)
+#define EDMA3_CCRL_EECRH_E46_RESETVAL    (0x00000000U)
 
 /*----E46 Tokens----*/
-#define EDMA3_CCRL_EECRH_E46_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E46_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E45_MASK        (0x00002000u)
-#define EDMA3_CCRL_EECRH_E45_SHIFT       (0x0000000Du)
-#define EDMA3_CCRL_EECRH_E45_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E45_MASK        (0x00002000U)
+#define EDMA3_CCRL_EECRH_E45_SHIFT       (0x0000000DU)
+#define EDMA3_CCRL_EECRH_E45_RESETVAL    (0x00000000U)
 
 /*----E45 Tokens----*/
-#define EDMA3_CCRL_EECRH_E45_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E45_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E44_MASK        (0x00001000u)
-#define EDMA3_CCRL_EECRH_E44_SHIFT       (0x0000000Cu)
-#define EDMA3_CCRL_EECRH_E44_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E44_MASK        (0x00001000U)
+#define EDMA3_CCRL_EECRH_E44_SHIFT       (0x0000000CU)
+#define EDMA3_CCRL_EECRH_E44_RESETVAL    (0x00000000U)
 
 /*----E44 Tokens----*/
-#define EDMA3_CCRL_EECRH_E44_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E44_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E43_MASK        (0x00000800u)
-#define EDMA3_CCRL_EECRH_E43_SHIFT       (0x0000000Bu)
-#define EDMA3_CCRL_EECRH_E43_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E43_MASK        (0x00000800U)
+#define EDMA3_CCRL_EECRH_E43_SHIFT       (0x0000000BU)
+#define EDMA3_CCRL_EECRH_E43_RESETVAL    (0x00000000U)
 
 /*----E43 Tokens----*/
-#define EDMA3_CCRL_EECRH_E43_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E43_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E42_MASK        (0x00000400u)
-#define EDMA3_CCRL_EECRH_E42_SHIFT       (0x0000000Au)
-#define EDMA3_CCRL_EECRH_E42_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E42_MASK        (0x00000400U)
+#define EDMA3_CCRL_EECRH_E42_SHIFT       (0x0000000AU)
+#define EDMA3_CCRL_EECRH_E42_RESETVAL    (0x00000000U)
 
 /*----E42 Tokens----*/
-#define EDMA3_CCRL_EECRH_E42_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E42_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E41_MASK        (0x00000200u)
-#define EDMA3_CCRL_EECRH_E41_SHIFT       (0x00000009u)
-#define EDMA3_CCRL_EECRH_E41_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E41_MASK        (0x00000200U)
+#define EDMA3_CCRL_EECRH_E41_SHIFT       (0x00000009U)
+#define EDMA3_CCRL_EECRH_E41_RESETVAL    (0x00000000U)
 
 /*----E41 Tokens----*/
-#define EDMA3_CCRL_EECRH_E41_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E41_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E40_MASK        (0x00000100u)
-#define EDMA3_CCRL_EECRH_E40_SHIFT       (0x00000008u)
-#define EDMA3_CCRL_EECRH_E40_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E40_MASK        (0x00000100U)
+#define EDMA3_CCRL_EECRH_E40_SHIFT       (0x00000008U)
+#define EDMA3_CCRL_EECRH_E40_RESETVAL    (0x00000000U)
 
 /*----E40 Tokens----*/
-#define EDMA3_CCRL_EECRH_E40_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E40_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E39_MASK        (0x00000080u)
-#define EDMA3_CCRL_EECRH_E39_SHIFT       (0x00000007u)
-#define EDMA3_CCRL_EECRH_E39_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E39_MASK        (0x00000080U)
+#define EDMA3_CCRL_EECRH_E39_SHIFT       (0x00000007U)
+#define EDMA3_CCRL_EECRH_E39_RESETVAL    (0x00000000U)
 
 /*----E39 Tokens----*/
-#define EDMA3_CCRL_EECRH_E39_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E39_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E38_MASK        (0x00000040u)
-#define EDMA3_CCRL_EECRH_E38_SHIFT       (0x00000006u)
-#define EDMA3_CCRL_EECRH_E38_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E38_MASK        (0x00000040U)
+#define EDMA3_CCRL_EECRH_E38_SHIFT       (0x00000006U)
+#define EDMA3_CCRL_EECRH_E38_RESETVAL    (0x00000000U)
 
 /*----E38 Tokens----*/
-#define EDMA3_CCRL_EECRH_E38_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E38_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E37_MASK        (0x00000020u)
-#define EDMA3_CCRL_EECRH_E37_SHIFT       (0x00000005u)
-#define EDMA3_CCRL_EECRH_E37_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E37_MASK        (0x00000020U)
+#define EDMA3_CCRL_EECRH_E37_SHIFT       (0x00000005U)
+#define EDMA3_CCRL_EECRH_E37_RESETVAL    (0x00000000U)
 
 /*----E37 Tokens----*/
-#define EDMA3_CCRL_EECRH_E37_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E37_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E36_MASK        (0x00000010u)
-#define EDMA3_CCRL_EECRH_E36_SHIFT       (0x00000004u)
-#define EDMA3_CCRL_EECRH_E36_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E36_MASK        (0x00000010U)
+#define EDMA3_CCRL_EECRH_E36_SHIFT       (0x00000004U)
+#define EDMA3_CCRL_EECRH_E36_RESETVAL    (0x00000000U)
 
 /*----E36 Tokens----*/
-#define EDMA3_CCRL_EECRH_E36_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E36_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E35_MASK        (0x00000008u)
-#define EDMA3_CCRL_EECRH_E35_SHIFT       (0x00000003u)
-#define EDMA3_CCRL_EECRH_E35_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E35_MASK        (0x00000008U)
+#define EDMA3_CCRL_EECRH_E35_SHIFT       (0x00000003U)
+#define EDMA3_CCRL_EECRH_E35_RESETVAL    (0x00000000U)
 
 /*----E35 Tokens----*/
-#define EDMA3_CCRL_EECRH_E35_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E35_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E34_MASK        (0x00000004u)
-#define EDMA3_CCRL_EECRH_E34_SHIFT       (0x00000002u)
-#define EDMA3_CCRL_EECRH_E34_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E34_MASK        (0x00000004U)
+#define EDMA3_CCRL_EECRH_E34_SHIFT       (0x00000002U)
+#define EDMA3_CCRL_EECRH_E34_RESETVAL    (0x00000000U)
 
 /*----E34 Tokens----*/
-#define EDMA3_CCRL_EECRH_E34_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E34_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E33_MASK        (0x00000002u)
-#define EDMA3_CCRL_EECRH_E33_SHIFT       (0x00000001u)
-#define EDMA3_CCRL_EECRH_E33_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E33_MASK        (0x00000002U)
+#define EDMA3_CCRL_EECRH_E33_SHIFT       (0x00000001U)
+#define EDMA3_CCRL_EECRH_E33_RESETVAL    (0x00000000U)
 
 /*----E33 Tokens----*/
-#define EDMA3_CCRL_EECRH_E33_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E33_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_E32_MASK        (0x00000001u)
-#define EDMA3_CCRL_EECRH_E32_SHIFT       (0x00000000u)
-#define EDMA3_CCRL_EECRH_E32_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EECRH_E32_MASK        (0x00000001U)
+#define EDMA3_CCRL_EECRH_E32_SHIFT       (0x00000000U)
+#define EDMA3_CCRL_EECRH_E32_RESETVAL    (0x00000000U)
 
 /*----E32 Tokens----*/
-#define EDMA3_CCRL_EECRH_E32_CLEAR       (0x00000001u)
+#define EDMA3_CCRL_EECRH_E32_CLEAR       (0x00000001U)
 
-#define EDMA3_CCRL_EECRH_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_EECRH_RESETVAL        (0x00000000U)
 
 /* EESR */
 
-#define EDMA3_CCRL_EESR_E31_MASK         (0x80000000u)
-#define EDMA3_CCRL_EESR_E31_SHIFT        (0x0000001Fu)
-#define EDMA3_CCRL_EESR_E31_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E31_MASK         (0x80000000U)
+#define EDMA3_CCRL_EESR_E31_SHIFT        (0x0000001FU)
+#define EDMA3_CCRL_EESR_E31_RESETVAL     (0x00000000U)
 
 /*----E31 Tokens----*/
-#define EDMA3_CCRL_EESR_E31_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E31_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E30_MASK         (0x40000000u)
-#define EDMA3_CCRL_EESR_E30_SHIFT        (0x0000001Eu)
-#define EDMA3_CCRL_EESR_E30_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E30_MASK         (0x40000000U)
+#define EDMA3_CCRL_EESR_E30_SHIFT        (0x0000001EU)
+#define EDMA3_CCRL_EESR_E30_RESETVAL     (0x00000000U)
 
 /*----E30 Tokens----*/
-#define EDMA3_CCRL_EESR_E30_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E30_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E29_MASK         (0x20000000u)
-#define EDMA3_CCRL_EESR_E29_SHIFT        (0x0000001Du)
-#define EDMA3_CCRL_EESR_E29_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E29_MASK         (0x20000000U)
+#define EDMA3_CCRL_EESR_E29_SHIFT        (0x0000001DU)
+#define EDMA3_CCRL_EESR_E29_RESETVAL     (0x00000000U)
 
 /*----E29 Tokens----*/
-#define EDMA3_CCRL_EESR_E29_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E29_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E28_MASK         (0x10000000u)
-#define EDMA3_CCRL_EESR_E28_SHIFT        (0x0000001Cu)
-#define EDMA3_CCRL_EESR_E28_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E28_MASK         (0x10000000U)
+#define EDMA3_CCRL_EESR_E28_SHIFT        (0x0000001CU)
+#define EDMA3_CCRL_EESR_E28_RESETVAL     (0x00000000U)
 
 /*----E28 Tokens----*/
-#define EDMA3_CCRL_EESR_E28_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E28_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E27_MASK         (0x08000000u)
-#define EDMA3_CCRL_EESR_E27_SHIFT        (0x0000001Bu)
-#define EDMA3_CCRL_EESR_E27_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E27_MASK         (0x08000000U)
+#define EDMA3_CCRL_EESR_E27_SHIFT        (0x0000001BU)
+#define EDMA3_CCRL_EESR_E27_RESETVAL     (0x00000000U)
 
 /*----E27 Tokens----*/
-#define EDMA3_CCRL_EESR_E27_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E27_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E26_MASK         (0x04000000u)
-#define EDMA3_CCRL_EESR_E26_SHIFT        (0x0000001Au)
-#define EDMA3_CCRL_EESR_E26_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E26_MASK         (0x04000000U)
+#define EDMA3_CCRL_EESR_E26_SHIFT        (0x0000001AU)
+#define EDMA3_CCRL_EESR_E26_RESETVAL     (0x00000000U)
 
 /*----E26 Tokens----*/
-#define EDMA3_CCRL_EESR_E26_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E26_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E25_MASK         (0x02000000u)
-#define EDMA3_CCRL_EESR_E25_SHIFT        (0x00000019u)
-#define EDMA3_CCRL_EESR_E25_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E25_MASK         (0x02000000U)
+#define EDMA3_CCRL_EESR_E25_SHIFT        (0x00000019U)
+#define EDMA3_CCRL_EESR_E25_RESETVAL     (0x00000000U)
 
 /*----E25 Tokens----*/
-#define EDMA3_CCRL_EESR_E25_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E25_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E24_MASK         (0x01000000u)
-#define EDMA3_CCRL_EESR_E24_SHIFT        (0x00000018u)
-#define EDMA3_CCRL_EESR_E24_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E24_MASK         (0x01000000U)
+#define EDMA3_CCRL_EESR_E24_SHIFT        (0x00000018U)
+#define EDMA3_CCRL_EESR_E24_RESETVAL     (0x00000000U)
 
 /*----E24 Tokens----*/
-#define EDMA3_CCRL_EESR_E24_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E24_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E23_MASK         (0x00800000u)
-#define EDMA3_CCRL_EESR_E23_SHIFT        (0x00000017u)
-#define EDMA3_CCRL_EESR_E23_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E23_MASK         (0x00800000U)
+#define EDMA3_CCRL_EESR_E23_SHIFT        (0x00000017U)
+#define EDMA3_CCRL_EESR_E23_RESETVAL     (0x00000000U)
 
 /*----E23 Tokens----*/
-#define EDMA3_CCRL_EESR_E23_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E23_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E22_MASK         (0x00400000u)
-#define EDMA3_CCRL_EESR_E22_SHIFT        (0x00000016u)
-#define EDMA3_CCRL_EESR_E22_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E22_MASK         (0x00400000U)
+#define EDMA3_CCRL_EESR_E22_SHIFT        (0x00000016U)
+#define EDMA3_CCRL_EESR_E22_RESETVAL     (0x00000000U)
 
 /*----E22 Tokens----*/
-#define EDMA3_CCRL_EESR_E22_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E22_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E21_MASK         (0x00200000u)
-#define EDMA3_CCRL_EESR_E21_SHIFT        (0x00000015u)
-#define EDMA3_CCRL_EESR_E21_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E21_MASK         (0x00200000U)
+#define EDMA3_CCRL_EESR_E21_SHIFT        (0x00000015U)
+#define EDMA3_CCRL_EESR_E21_RESETVAL     (0x00000000U)
 
 /*----E21 Tokens----*/
-#define EDMA3_CCRL_EESR_E21_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E21_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E20_MASK         (0x00100000u)
-#define EDMA3_CCRL_EESR_E20_SHIFT        (0x00000014u)
-#define EDMA3_CCRL_EESR_E20_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E20_MASK         (0x00100000U)
+#define EDMA3_CCRL_EESR_E20_SHIFT        (0x00000014U)
+#define EDMA3_CCRL_EESR_E20_RESETVAL     (0x00000000U)
 
 /*----E20 Tokens----*/
-#define EDMA3_CCRL_EESR_E20_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E20_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E19_MASK         (0x00080000u)
-#define EDMA3_CCRL_EESR_E19_SHIFT        (0x00000013u)
-#define EDMA3_CCRL_EESR_E19_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E19_MASK         (0x00080000U)
+#define EDMA3_CCRL_EESR_E19_SHIFT        (0x00000013U)
+#define EDMA3_CCRL_EESR_E19_RESETVAL     (0x00000000U)
 
 /*----E19 Tokens----*/
-#define EDMA3_CCRL_EESR_E19_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E19_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E18_MASK         (0x00040000u)
-#define EDMA3_CCRL_EESR_E18_SHIFT        (0x00000012u)
-#define EDMA3_CCRL_EESR_E18_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E18_MASK         (0x00040000U)
+#define EDMA3_CCRL_EESR_E18_SHIFT        (0x00000012U)
+#define EDMA3_CCRL_EESR_E18_RESETVAL     (0x00000000U)
 
 /*----E18 Tokens----*/
-#define EDMA3_CCRL_EESR_E18_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E18_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E17_MASK         (0x00020000u)
-#define EDMA3_CCRL_EESR_E17_SHIFT        (0x00000011u)
-#define EDMA3_CCRL_EESR_E17_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E17_MASK         (0x00020000U)
+#define EDMA3_CCRL_EESR_E17_SHIFT        (0x00000011U)
+#define EDMA3_CCRL_EESR_E17_RESETVAL     (0x00000000U)
 
 /*----E17 Tokens----*/
-#define EDMA3_CCRL_EESR_E17_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E17_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E16_MASK         (0x00010000u)
-#define EDMA3_CCRL_EESR_E16_SHIFT        (0x00000010u)
-#define EDMA3_CCRL_EESR_E16_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E16_MASK         (0x00010000U)
+#define EDMA3_CCRL_EESR_E16_SHIFT        (0x00000010U)
+#define EDMA3_CCRL_EESR_E16_RESETVAL     (0x00000000U)
 
 /*----E16 Tokens----*/
-#define EDMA3_CCRL_EESR_E16_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E16_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E15_MASK         (0x00008000u)
-#define EDMA3_CCRL_EESR_E15_SHIFT        (0x0000000Fu)
-#define EDMA3_CCRL_EESR_E15_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E15_MASK         (0x00008000U)
+#define EDMA3_CCRL_EESR_E15_SHIFT        (0x0000000FU)
+#define EDMA3_CCRL_EESR_E15_RESETVAL     (0x00000000U)
 
 /*----E15 Tokens----*/
-#define EDMA3_CCRL_EESR_E15_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E15_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E14_MASK         (0x00004000u)
-#define EDMA3_CCRL_EESR_E14_SHIFT        (0x0000000Eu)
-#define EDMA3_CCRL_EESR_E14_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E14_MASK         (0x00004000U)
+#define EDMA3_CCRL_EESR_E14_SHIFT        (0x0000000EU)
+#define EDMA3_CCRL_EESR_E14_RESETVAL     (0x00000000U)
 
 /*----E14 Tokens----*/
-#define EDMA3_CCRL_EESR_E14_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E14_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E13_MASK         (0x00002000u)
-#define EDMA3_CCRL_EESR_E13_SHIFT        (0x0000000Du)
-#define EDMA3_CCRL_EESR_E13_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E13_MASK         (0x00002000U)
+#define EDMA3_CCRL_EESR_E13_SHIFT        (0x0000000DU)
+#define EDMA3_CCRL_EESR_E13_RESETVAL     (0x00000000U)
 
 /*----E13 Tokens----*/
-#define EDMA3_CCRL_EESR_E13_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E13_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E12_MASK         (0x00001000u)
-#define EDMA3_CCRL_EESR_E12_SHIFT        (0x0000000Cu)
-#define EDMA3_CCRL_EESR_E12_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E12_MASK         (0x00001000U)
+#define EDMA3_CCRL_EESR_E12_SHIFT        (0x0000000CU)
+#define EDMA3_CCRL_EESR_E12_RESETVAL     (0x00000000U)
 
 /*----E12 Tokens----*/
-#define EDMA3_CCRL_EESR_E12_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E12_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E11_MASK         (0x00000800u)
-#define EDMA3_CCRL_EESR_E11_SHIFT        (0x0000000Bu)
-#define EDMA3_CCRL_EESR_E11_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E11_MASK         (0x00000800U)
+#define EDMA3_CCRL_EESR_E11_SHIFT        (0x0000000BU)
+#define EDMA3_CCRL_EESR_E11_RESETVAL     (0x00000000U)
 
 /*----E11 Tokens----*/
-#define EDMA3_CCRL_EESR_E11_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E11_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E10_MASK         (0x00000400u)
-#define EDMA3_CCRL_EESR_E10_SHIFT        (0x0000000Au)
-#define EDMA3_CCRL_EESR_E10_RESETVAL     (0x00000000u)
+#define EDMA3_CCRL_EESR_E10_MASK         (0x00000400U)
+#define EDMA3_CCRL_EESR_E10_SHIFT        (0x0000000AU)
+#define EDMA3_CCRL_EESR_E10_RESETVAL     (0x00000000U)
 
 /*----E10 Tokens----*/
-#define EDMA3_CCRL_EESR_E10_SET          (0x00000001u)
+#define EDMA3_CCRL_EESR_E10_SET          (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E9_MASK          (0x00000200u)
-#define EDMA3_CCRL_EESR_E9_SHIFT         (0x00000009u)
-#define EDMA3_CCRL_EESR_E9_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EESR_E9_MASK          (0x00000200U)
+#define EDMA3_CCRL_EESR_E9_SHIFT         (0x00000009U)
+#define EDMA3_CCRL_EESR_E9_RESETVAL      (0x00000000U)
 
 /*----E9 Tokens----*/
-#define EDMA3_CCRL_EESR_E9_SET           (0x00000001u)
+#define EDMA3_CCRL_EESR_E9_SET           (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E8_MASK          (0x00000100u)
-#define EDMA3_CCRL_EESR_E8_SHIFT         (0x00000008u)
-#define EDMA3_CCRL_EESR_E8_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EESR_E8_MASK          (0x00000100U)
+#define EDMA3_CCRL_EESR_E8_SHIFT         (0x00000008U)
+#define EDMA3_CCRL_EESR_E8_RESETVAL      (0x00000000U)
 
 /*----E8 Tokens----*/
-#define EDMA3_CCRL_EESR_E8_SET           (0x00000001u)
+#define EDMA3_CCRL_EESR_E8_SET           (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E7_MASK          (0x00000080u)
-#define EDMA3_CCRL_EESR_E7_SHIFT         (0x00000007u)
-#define EDMA3_CCRL_EESR_E7_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EESR_E7_MASK          (0x00000080U)
+#define EDMA3_CCRL_EESR_E7_SHIFT         (0x00000007U)
+#define EDMA3_CCRL_EESR_E7_RESETVAL      (0x00000000U)
 
 /*----E7 Tokens----*/
-#define EDMA3_CCRL_EESR_E7_SET           (0x00000001u)
+#define EDMA3_CCRL_EESR_E7_SET           (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E6_MASK          (0x00000040u)
-#define EDMA3_CCRL_EESR_E6_SHIFT         (0x00000006u)
-#define EDMA3_CCRL_EESR_E6_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EESR_E6_MASK          (0x00000040U)
+#define EDMA3_CCRL_EESR_E6_SHIFT         (0x00000006U)
+#define EDMA3_CCRL_EESR_E6_RESETVAL      (0x00000000U)
 
 /*----E6 Tokens----*/
-#define EDMA3_CCRL_EESR_E6_SET           (0x00000001u)
+#define EDMA3_CCRL_EESR_E6_SET           (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E5_MASK          (0x00000020u)
-#define EDMA3_CCRL_EESR_E5_SHIFT         (0x00000005u)
-#define EDMA3_CCRL_EESR_E5_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EESR_E5_MASK          (0x00000020U)
+#define EDMA3_CCRL_EESR_E5_SHIFT         (0x00000005U)
+#define EDMA3_CCRL_EESR_E5_RESETVAL      (0x00000000U)
 
 /*----E5 Tokens----*/
-#define EDMA3_CCRL_EESR_E5_SET           (0x00000001u)
+#define EDMA3_CCRL_EESR_E5_SET           (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E4_MASK          (0x00000010u)
-#define EDMA3_CCRL_EESR_E4_SHIFT         (0x00000004u)
-#define EDMA3_CCRL_EESR_E4_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EESR_E4_MASK          (0x00000010U)
+#define EDMA3_CCRL_EESR_E4_SHIFT         (0x00000004U)
+#define EDMA3_CCRL_EESR_E4_RESETVAL      (0x00000000U)
 
 /*----E4 Tokens----*/
-#define EDMA3_CCRL_EESR_E4_SET           (0x00000001u)
+#define EDMA3_CCRL_EESR_E4_SET           (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E3_MASK          (0x00000008u)
-#define EDMA3_CCRL_EESR_E3_SHIFT         (0x00000003u)
-#define EDMA3_CCRL_EESR_E3_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EESR_E3_MASK          (0x00000008U)
+#define EDMA3_CCRL_EESR_E3_SHIFT         (0x00000003U)
+#define EDMA3_CCRL_EESR_E3_RESETVAL      (0x00000000U)
 
 /*----E3 Tokens----*/
-#define EDMA3_CCRL_EESR_E3_SET           (0x00000001u)
+#define EDMA3_CCRL_EESR_E3_SET           (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E2_MASK          (0x00000004u)
-#define EDMA3_CCRL_EESR_E2_SHIFT         (0x00000002u)
-#define EDMA3_CCRL_EESR_E2_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EESR_E2_MASK          (0x00000004U)
+#define EDMA3_CCRL_EESR_E2_SHIFT         (0x00000002U)
+#define EDMA3_CCRL_EESR_E2_RESETVAL      (0x00000000U)
 
 /*----E2 Tokens----*/
-#define EDMA3_CCRL_EESR_E2_SET           (0x00000001u)
+#define EDMA3_CCRL_EESR_E2_SET           (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E1_MASK          (0x00000002u)
-#define EDMA3_CCRL_EESR_E1_SHIFT         (0x00000001u)
-#define EDMA3_CCRL_EESR_E1_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EESR_E1_MASK          (0x00000002U)
+#define EDMA3_CCRL_EESR_E1_SHIFT         (0x00000001U)
+#define EDMA3_CCRL_EESR_E1_RESETVAL      (0x00000000U)
 
 /*----E1 Tokens----*/
-#define EDMA3_CCRL_EESR_E1_SET           (0x00000001u)
+#define EDMA3_CCRL_EESR_E1_SET           (0x00000001U)
 
-#define EDMA3_CCRL_EESR_E0_MASK          (0x00000001u)
-#define EDMA3_CCRL_EESR_E0_SHIFT         (0x00000000u)
-#define EDMA3_CCRL_EESR_E0_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_EESR_E0_MASK          (0x00000001U)
+#define EDMA3_CCRL_EESR_E0_SHIFT         (0x00000000U)
+#define EDMA3_CCRL_EESR_E0_RESETVAL      (0x00000000U)
 
 /*----E0 Tokens----*/
-#define EDMA3_CCRL_EESR_E0_SET           (0x00000001u)
+#define EDMA3_CCRL_EESR_E0_SET           (0x00000001U)
 
-#define EDMA3_CCRL_EESR_RESETVAL         (0x00000000u)
+#define EDMA3_CCRL_EESR_RESETVAL         (0x00000000U)
 
 /* EESRH */
 
-#define EDMA3_CCRL_EESRH_E63_MASK        (0x80000000u)
-#define EDMA3_CCRL_EESRH_E63_SHIFT       (0x0000001Fu)
-#define EDMA3_CCRL_EESRH_E63_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E63_MASK        (0x80000000U)
+#define EDMA3_CCRL_EESRH_E63_SHIFT       (0x0000001FU)
+#define EDMA3_CCRL_EESRH_E63_RESETVAL    (0x00000000U)
 
 /*----E63 Tokens----*/
-#define EDMA3_CCRL_EESRH_E63_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E63_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E62_MASK        (0x40000000u)
-#define EDMA3_CCRL_EESRH_E62_SHIFT       (0x0000001Eu)
-#define EDMA3_CCRL_EESRH_E62_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E62_MASK        (0x40000000U)
+#define EDMA3_CCRL_EESRH_E62_SHIFT       (0x0000001EU)
+#define EDMA3_CCRL_EESRH_E62_RESETVAL    (0x00000000U)
 
 /*----E62 Tokens----*/
-#define EDMA3_CCRL_EESRH_E62_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E62_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E61_MASK        (0x20000000u)
-#define EDMA3_CCRL_EESRH_E61_SHIFT       (0x0000001Du)
-#define EDMA3_CCRL_EESRH_E61_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E61_MASK        (0x20000000U)
+#define EDMA3_CCRL_EESRH_E61_SHIFT       (0x0000001DU)
+#define EDMA3_CCRL_EESRH_E61_RESETVAL    (0x00000000U)
 
 /*----E61 Tokens----*/
-#define EDMA3_CCRL_EESRH_E61_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E61_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E60_MASK        (0x10000000u)
-#define EDMA3_CCRL_EESRH_E60_SHIFT       (0x0000001Cu)
-#define EDMA3_CCRL_EESRH_E60_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E60_MASK        (0x10000000U)
+#define EDMA3_CCRL_EESRH_E60_SHIFT       (0x0000001CU)
+#define EDMA3_CCRL_EESRH_E60_RESETVAL    (0x00000000U)
 
 /*----E60 Tokens----*/
-#define EDMA3_CCRL_EESRH_E60_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E60_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E59_MASK        (0x08000000u)
-#define EDMA3_CCRL_EESRH_E59_SHIFT       (0x0000001Bu)
-#define EDMA3_CCRL_EESRH_E59_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E59_MASK        (0x08000000U)
+#define EDMA3_CCRL_EESRH_E59_SHIFT       (0x0000001BU)
+#define EDMA3_CCRL_EESRH_E59_RESETVAL    (0x00000000U)
 
 /*----E59 Tokens----*/
-#define EDMA3_CCRL_EESRH_E59_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E59_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E58_MASK        (0x04000000u)
-#define EDMA3_CCRL_EESRH_E58_SHIFT       (0x0000001Au)
-#define EDMA3_CCRL_EESRH_E58_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E58_MASK        (0x04000000U)
+#define EDMA3_CCRL_EESRH_E58_SHIFT       (0x0000001AU)
+#define EDMA3_CCRL_EESRH_E58_RESETVAL    (0x00000000U)
 
 /*----E58 Tokens----*/
-#define EDMA3_CCRL_EESRH_E58_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E58_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E57_MASK        (0x02000000u)
-#define EDMA3_CCRL_EESRH_E57_SHIFT       (0x00000019u)
-#define EDMA3_CCRL_EESRH_E57_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E57_MASK        (0x02000000U)
+#define EDMA3_CCRL_EESRH_E57_SHIFT       (0x00000019U)
+#define EDMA3_CCRL_EESRH_E57_RESETVAL    (0x00000000U)
 
 /*----E57 Tokens----*/
-#define EDMA3_CCRL_EESRH_E57_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E57_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E56_MASK        (0x01000000u)
-#define EDMA3_CCRL_EESRH_E56_SHIFT       (0x00000018u)
-#define EDMA3_CCRL_EESRH_E56_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E56_MASK        (0x01000000U)
+#define EDMA3_CCRL_EESRH_E56_SHIFT       (0x00000018U)
+#define EDMA3_CCRL_EESRH_E56_RESETVAL    (0x00000000U)
 
 /*----E56 Tokens----*/
-#define EDMA3_CCRL_EESRH_E56_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E56_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E55_MASK        (0x00800000u)
-#define EDMA3_CCRL_EESRH_E55_SHIFT       (0x00000017u)
-#define EDMA3_CCRL_EESRH_E55_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E55_MASK        (0x00800000U)
+#define EDMA3_CCRL_EESRH_E55_SHIFT       (0x00000017U)
+#define EDMA3_CCRL_EESRH_E55_RESETVAL    (0x00000000U)
 
 /*----E55 Tokens----*/
-#define EDMA3_CCRL_EESRH_E55_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E55_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E54_MASK        (0x00400000u)
-#define EDMA3_CCRL_EESRH_E54_SHIFT       (0x00000016u)
-#define EDMA3_CCRL_EESRH_E54_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E54_MASK        (0x00400000U)
+#define EDMA3_CCRL_EESRH_E54_SHIFT       (0x00000016U)
+#define EDMA3_CCRL_EESRH_E54_RESETVAL    (0x00000000U)
 
 /*----E54 Tokens----*/
-#define EDMA3_CCRL_EESRH_E54_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E54_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E53_MASK        (0x00200000u)
-#define EDMA3_CCRL_EESRH_E53_SHIFT       (0x00000015u)
-#define EDMA3_CCRL_EESRH_E53_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E53_MASK        (0x00200000U)
+#define EDMA3_CCRL_EESRH_E53_SHIFT       (0x00000015U)
+#define EDMA3_CCRL_EESRH_E53_RESETVAL    (0x00000000U)
 
 /*----E53 Tokens----*/
-#define EDMA3_CCRL_EESRH_E53_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E53_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E52_MASK        (0x00100000u)
-#define EDMA3_CCRL_EESRH_E52_SHIFT       (0x00000014u)
-#define EDMA3_CCRL_EESRH_E52_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E52_MASK        (0x00100000U)
+#define EDMA3_CCRL_EESRH_E52_SHIFT       (0x00000014U)
+#define EDMA3_CCRL_EESRH_E52_RESETVAL    (0x00000000U)
 
 /*----E52 Tokens----*/
-#define EDMA3_CCRL_EESRH_E52_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E52_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E51_MASK        (0x00080000u)
-#define EDMA3_CCRL_EESRH_E51_SHIFT       (0x00000013u)
-#define EDMA3_CCRL_EESRH_E51_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E51_MASK        (0x00080000U)
+#define EDMA3_CCRL_EESRH_E51_SHIFT       (0x00000013U)
+#define EDMA3_CCRL_EESRH_E51_RESETVAL    (0x00000000U)
 
 /*----E51 Tokens----*/
-#define EDMA3_CCRL_EESRH_E51_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E51_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E50_MASK        (0x00040000u)
-#define EDMA3_CCRL_EESRH_E50_SHIFT       (0x00000012u)
-#define EDMA3_CCRL_EESRH_E50_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E50_MASK        (0x00040000U)
+#define EDMA3_CCRL_EESRH_E50_SHIFT       (0x00000012U)
+#define EDMA3_CCRL_EESRH_E50_RESETVAL    (0x00000000U)
 
 /*----E50 Tokens----*/
-#define EDMA3_CCRL_EESRH_E50_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E50_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E49_MASK        (0x00020000u)
-#define EDMA3_CCRL_EESRH_E49_SHIFT       (0x00000011u)
-#define EDMA3_CCRL_EESRH_E49_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E49_MASK        (0x00020000U)
+#define EDMA3_CCRL_EESRH_E49_SHIFT       (0x00000011U)
+#define EDMA3_CCRL_EESRH_E49_RESETVAL    (0x00000000U)
 
 /*----E49 Tokens----*/
-#define EDMA3_CCRL_EESRH_E49_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E49_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E48_MASK        (0x00010000u)
-#define EDMA3_CCRL_EESRH_E48_SHIFT       (0x00000010u)
-#define EDMA3_CCRL_EESRH_E48_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E48_MASK        (0x00010000U)
+#define EDMA3_CCRL_EESRH_E48_SHIFT       (0x00000010U)
+#define EDMA3_CCRL_EESRH_E48_RESETVAL    (0x00000000U)
 
 /*----E48 Tokens----*/
-#define EDMA3_CCRL_EESRH_E48_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E48_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E47_MASK        (0x00008000u)
-#define EDMA3_CCRL_EESRH_E47_SHIFT       (0x0000000Fu)
-#define EDMA3_CCRL_EESRH_E47_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E47_MASK        (0x00008000U)
+#define EDMA3_CCRL_EESRH_E47_SHIFT       (0x0000000FU)
+#define EDMA3_CCRL_EESRH_E47_RESETVAL    (0x00000000U)
 
 /*----E47 Tokens----*/
-#define EDMA3_CCRL_EESRH_E47_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E47_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E46_MASK        (0x00004000u)
-#define EDMA3_CCRL_EESRH_E46_SHIFT       (0x0000000Eu)
-#define EDMA3_CCRL_EESRH_E46_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E46_MASK        (0x00004000U)
+#define EDMA3_CCRL_EESRH_E46_SHIFT       (0x0000000EU)
+#define EDMA3_CCRL_EESRH_E46_RESETVAL    (0x00000000U)
 
 /*----E46 Tokens----*/
-#define EDMA3_CCRL_EESRH_E46_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E46_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E45_MASK        (0x00002000u)
-#define EDMA3_CCRL_EESRH_E45_SHIFT       (0x0000000Du)
-#define EDMA3_CCRL_EESRH_E45_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E45_MASK        (0x00002000U)
+#define EDMA3_CCRL_EESRH_E45_SHIFT       (0x0000000DU)
+#define EDMA3_CCRL_EESRH_E45_RESETVAL    (0x00000000U)
 
 /*----E45 Tokens----*/
-#define EDMA3_CCRL_EESRH_E45_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E45_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E44_MASK        (0x00001000u)
-#define EDMA3_CCRL_EESRH_E44_SHIFT       (0x0000000Cu)
-#define EDMA3_CCRL_EESRH_E44_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E44_MASK        (0x00001000U)
+#define EDMA3_CCRL_EESRH_E44_SHIFT       (0x0000000CU)
+#define EDMA3_CCRL_EESRH_E44_RESETVAL    (0x00000000U)
 
 /*----E44 Tokens----*/
-#define EDMA3_CCRL_EESRH_E44_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E44_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E43_MASK        (0x00000800u)
-#define EDMA3_CCRL_EESRH_E43_SHIFT       (0x0000000Bu)
-#define EDMA3_CCRL_EESRH_E43_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E43_MASK        (0x00000800U)
+#define EDMA3_CCRL_EESRH_E43_SHIFT       (0x0000000BU)
+#define EDMA3_CCRL_EESRH_E43_RESETVAL    (0x00000000U)
 
 /*----E43 Tokens----*/
-#define EDMA3_CCRL_EESRH_E43_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E43_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E42_MASK        (0x00000400u)
-#define EDMA3_CCRL_EESRH_E42_SHIFT       (0x0000000Au)
-#define EDMA3_CCRL_EESRH_E42_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E42_MASK        (0x00000400U)
+#define EDMA3_CCRL_EESRH_E42_SHIFT       (0x0000000AU)
+#define EDMA3_CCRL_EESRH_E42_RESETVAL    (0x00000000U)
 
 /*----E42 Tokens----*/
-#define EDMA3_CCRL_EESRH_E42_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E42_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E41_MASK        (0x00000200u)
-#define EDMA3_CCRL_EESRH_E41_SHIFT       (0x00000009u)
-#define EDMA3_CCRL_EESRH_E41_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E41_MASK        (0x00000200U)
+#define EDMA3_CCRL_EESRH_E41_SHIFT       (0x00000009U)
+#define EDMA3_CCRL_EESRH_E41_RESETVAL    (0x00000000U)
 
 /*----E41 Tokens----*/
-#define EDMA3_CCRL_EESRH_E41_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E41_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E40_MASK        (0x00000100u)
-#define EDMA3_CCRL_EESRH_E40_SHIFT       (0x00000008u)
-#define EDMA3_CCRL_EESRH_E40_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E40_MASK        (0x00000100U)
+#define EDMA3_CCRL_EESRH_E40_SHIFT       (0x00000008U)
+#define EDMA3_CCRL_EESRH_E40_RESETVAL    (0x00000000U)
 
 /*----E40 Tokens----*/
-#define EDMA3_CCRL_EESRH_E40_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E40_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E39_MASK        (0x00000080u)
-#define EDMA3_CCRL_EESRH_E39_SHIFT       (0x00000007u)
-#define EDMA3_CCRL_EESRH_E39_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E39_MASK        (0x00000080U)
+#define EDMA3_CCRL_EESRH_E39_SHIFT       (0x00000007U)
+#define EDMA3_CCRL_EESRH_E39_RESETVAL    (0x00000000U)
 
 /*----E39 Tokens----*/
-#define EDMA3_CCRL_EESRH_E39_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E39_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E38_MASK        (0x00000040u)
-#define EDMA3_CCRL_EESRH_E38_SHIFT       (0x00000006u)
-#define EDMA3_CCRL_EESRH_E38_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E38_MASK        (0x00000040U)
+#define EDMA3_CCRL_EESRH_E38_SHIFT       (0x00000006U)
+#define EDMA3_CCRL_EESRH_E38_RESETVAL    (0x00000000U)
 
 /*----E38 Tokens----*/
-#define EDMA3_CCRL_EESRH_E38_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E38_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E37_MASK        (0x00000020u)
-#define EDMA3_CCRL_EESRH_E37_SHIFT       (0x00000005u)
-#define EDMA3_CCRL_EESRH_E37_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E37_MASK        (0x00000020U)
+#define EDMA3_CCRL_EESRH_E37_SHIFT       (0x00000005U)
+#define EDMA3_CCRL_EESRH_E37_RESETVAL    (0x00000000U)
 
 /*----E37 Tokens----*/
-#define EDMA3_CCRL_EESRH_E37_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E37_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E36_MASK        (0x00000010u)
-#define EDMA3_CCRL_EESRH_E36_SHIFT       (0x00000004u)
-#define EDMA3_CCRL_EESRH_E36_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E36_MASK        (0x00000010U)
+#define EDMA3_CCRL_EESRH_E36_SHIFT       (0x00000004U)
+#define EDMA3_CCRL_EESRH_E36_RESETVAL    (0x00000000U)
 
 /*----E36 Tokens----*/
-#define EDMA3_CCRL_EESRH_E36_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E36_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E35_MASK        (0x00000008u)
-#define EDMA3_CCRL_EESRH_E35_SHIFT       (0x00000003u)
-#define EDMA3_CCRL_EESRH_E35_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E35_MASK        (0x00000008U)
+#define EDMA3_CCRL_EESRH_E35_SHIFT       (0x00000003U)
+#define EDMA3_CCRL_EESRH_E35_RESETVAL    (0x00000000U)
 
 /*----E35 Tokens----*/
-#define EDMA3_CCRL_EESRH_E35_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E35_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E34_MASK        (0x00000004u)
-#define EDMA3_CCRL_EESRH_E34_SHIFT       (0x00000002u)
-#define EDMA3_CCRL_EESRH_E34_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E34_MASK        (0x00000004U)
+#define EDMA3_CCRL_EESRH_E34_SHIFT       (0x00000002U)
+#define EDMA3_CCRL_EESRH_E34_RESETVAL    (0x00000000U)
 
 /*----E34 Tokens----*/
-#define EDMA3_CCRL_EESRH_E34_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E34_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E33_MASK        (0x00000002u)
-#define EDMA3_CCRL_EESRH_E33_SHIFT       (0x00000001u)
-#define EDMA3_CCRL_EESRH_E33_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E33_MASK        (0x00000002U)
+#define EDMA3_CCRL_EESRH_E33_SHIFT       (0x00000001U)
+#define EDMA3_CCRL_EESRH_E33_RESETVAL    (0x00000000U)
 
 /*----E33 Tokens----*/
-#define EDMA3_CCRL_EESRH_E33_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E33_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_E32_MASK        (0x00000001u)
-#define EDMA3_CCRL_EESRH_E32_SHIFT       (0x00000000u)
-#define EDMA3_CCRL_EESRH_E32_RESETVAL    (0x00000000u)
+#define EDMA3_CCRL_EESRH_E32_MASK        (0x00000001U)
+#define EDMA3_CCRL_EESRH_E32_SHIFT       (0x00000000U)
+#define EDMA3_CCRL_EESRH_E32_RESETVAL    (0x00000000U)
 
 /*----E32 Tokens----*/
-#define EDMA3_CCRL_EESRH_E32_SET         (0x00000001u)
+#define EDMA3_CCRL_EESRH_E32_SET         (0x00000001U)
 
-#define EDMA3_CCRL_EESRH_RESETVAL        (0x00000000u)
+#define EDMA3_CCRL_EESRH_RESETVAL        (0x00000000U)
 
 /* SER */
 
-#define EDMA3_CCRL_SER_E31_MASK          (0x80000000u)
-#define EDMA3_CCRL_SER_E31_SHIFT         (0x0000001Fu)
-#define EDMA3_CCRL_SER_E31_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_SER_E31_MASK          (0x80000000U)
+#define EDMA3_CCRL_SER_E31_SHIFT         (0x0000001FU)
+#define EDMA3_CCRL_SER_E31_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_SER_E30_MASK          (0x40000000u)
-#define EDMA3_CCRL_SER_E30_SHIFT         (0x0000001Eu)
-#define EDMA3_CCRL_SER_E30_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_SER_E30_MASK          (0x40000000U)
+#define EDMA3_CCRL_SER_E30_SHIFT         (0x0000001EU)
+#define EDMA3_CCRL_SER_E30_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_SER_E29_MASK          (0x20000000u)
-#define EDMA3_CCRL_SER_E29_SHIFT         (0x0000001Du)
-#define EDMA3_CCRL_SER_E29_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_SER_E29_MASK          (0x20000000U)
+#define EDMA3_CCRL_SER_E29_SHIFT         (0x0000001DU)
+#define EDMA3_CCRL_SER_E29_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_SER_E28_MASK          (0x10000000u)
-#define EDMA3_CCRL_SER_E28_SHIFT         (0x0000001Cu)
-#define EDMA3_CCRL_SER_E28_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_SER_E28_MASK          (0x10000000U)
+#define EDMA3_CCRL_SER_E28_SHIFT         (0x0000001CU)
+#define EDMA3_CCRL_SER_E28_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_SER_E27_MASK          (0x08000000u)
-#define EDMA3_CCRL_SER_E27_SHIFT         (0x0000001Bu)
-#define EDMA3_CCRL_SER_E27_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_SER_E27_MASK          (0x08000000U)
+#define EDMA3_CCRL_SER_E27_SHIFT         (0x0000001BU)
+#define EDMA3_CCRL_SER_E27_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_SER_E26_MASK          (0x04000000u)
-#define EDMA3_CCRL_SER_E26_SHIFT         (0x0000001Au)
-#define EDMA3_CCRL_SER_E26_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_SER_E26_MASK          (0x04000000U)
+#define EDMA3_CCRL_SER_E26_SHIFT         (0x0000001AU)
+#define EDMA3_CCRL_SER_E26_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_SER_E25_MASK          (0x02000000u)
-#define EDMA3_CCRL_SER_E25_SHIFT         (0x00000019u)
-#define EDMA3_CCRL_SER_E25_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_SER_E25_MASK          (0x02000000U)
+#define EDMA3_CCRL_SER_E25_SHIFT         (0x00000019U)
+#define EDMA3_CCRL_SER_E25_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_SER_E24_MASK          (0x01000000u)
-#define EDMA3_CCRL_SER_E24_SHIFT         (0x00000018u)
-#define EDMA3_CCRL_SER_E24_RESETVAL      (0x00000000u)
+#define EDMA3_CCRL_SER_E24_MASK          (0x01000000U)
+#define EDMA3_CCRL_SER_E24_SHIFT         (0x00000018U)
+#define EDMA3_CCRL_SER_E24_RESETVAL      (0x00000000U)
 
-#define EDMA3_CCRL_SER_E23_MASK