summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 81f5e92)
raw | patch | inline | side by side (parent: 81f5e92)
| author | Sundaram Raju <sundaram@ti.com> | |
| Mon, 14 Feb 2011 13:08:15 +0000 (18:38 +0530) | ||
| committer | Sundaram Raju <sundaram@ti.com> | |
| Mon, 14 Feb 2011 13:08:15 +0000 (18:38 +0530) |
Signed-off-by: Sundaram Raju <sundaram@ti.com>
60 files changed:
diff --git a/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver.chm b/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver.chm
index d8eb0f58c0ed32166eff3e2dc8fe19e0b6a0c876..43e8f4c0b302a34a1cb14887192a8f092b4a6f64 100755 (executable)
Binary files a/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver.chm and b/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver.chm differ
Binary files a/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver.chm and b/packages/ti/sdo/edma3/drv/docs/EDMA3_Driver.chm differ
diff --git a/packages/ti/sdo/edma3/drv/docs/html/annotated.html b/packages/ti/sdo/edma3/drv/docs/html/annotated.html
index 740c0cb5492e90c47eea57b7aa0e6253f48d2f0e..9a7dde928ca725144461f54e4832e5c9013ecf50 100755 (executable)
<tr><td class="indexkey"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a></td><td class="indexvalue">EDMA3 Parameter RAM Set in User Configurable format </td></tr>
</table>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/classes.html b/packages/ti/sdo/edma3/drv/docs/html/classes.html
index 25b06a99f1eeba6b423c806e50607840794b6907..38c015775981c1e830afb1966e3e9db67bce5f9f 100755 (executable)
<tr><td><a name="letter_E"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah"> E </div></td></tr></table>
</td><td><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a> </td><td><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html">EDMA3_DRV_Instance</a> </td><td><a class="el" href="struct_e_d_m_a3___d_r_v___object.html">EDMA3_DRV_Object</a> </td></tr><tr><td><a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a> </td><td><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> </td><td><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html">EDMA3_DRV_InstanceInitConfig</a> </td><td><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html">EDMA3_DRV_ParamentryRegs</a> </td></tr><tr><td><a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html">EDMA3_DRV_ChBoundResources</a> </td><td><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html">EDMA3_DRV_InitConfig</a> </td><td><a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html">EDMA3_DRV_MiscParam</a> </td><td><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> </td></tr><tr><td><a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a> </td></tr></table><div class="qindex"><a class="qindex" href="#letter_E">E</a></div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/functions.html b/packages/ti/sdo/edma3/drv/docs/html/functions.html
index adbabb2f4218c92b082ddc45f45f41550d608fdd..1810243ceeeb57ce89e1f83add31a10651142667 100755 (executable)
@@ -55,33 +55,33 @@ Here is a list of all documented struct and union fields with links to the struc
<h3><a class="anchor" id="index_a">- a -</a></h3><ul>
<li>A_B_CNT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a07ebc5f75c693a5b50383c0804d1d9e7">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aea70b184b092488704e5182e088d4968">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>aCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aa8b1127bdb0fa8d104a2bdab4c629620">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#af77830b02d859677689f1d0780fea145">EDMA3_DRV_PaRAMRegs</a>
</li>
</ul>
<h3><a class="anchor" id="index_b">- b -</a></h3><ul>
<li>bCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0311c99486c3c8c3ae20751289256ac0">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a8da5f5386a5236c92016c13a4d7fa46c">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>bCntReload
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a877333b51a48685e71608f3d65856049">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aed0fd5b798844697018fe3e18844c36c">EDMA3_DRV_PaRAMRegs</a>
</li>
</ul>
<h3><a class="anchor" id="index_c">- c -</a></h3><ul>
<li>ccError
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a5f7297703c68fdb4d6e9b2a5d4750040">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a682330bc86c34485de0cd00bafd9f493">EDMA3_DRV_GblConfigParams</a>
</li>
<li>CCNT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#ab533890c55e9dd3a71be6b02021823b3">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#adfead71f5566801a10ff1f4749a1e827">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>cCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a675509d3b2db629f66cf296ef0498c7d">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a1b5490a1cdd8ee7fe5ec20f1df8bb5d2">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>configScrMapXbarToEvt
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ab697a86b3efb21d2ddbbafa2519d21b1">EDMA3_DRV_Instance</a>
@@ -91,28 +91,28 @@ Here is a list of all documented struct and union fields with links to the struc
<h3><a class="anchor" id="index_d">- d -</a></h3><ul>
<li>destAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a6e8b9889c9d5d9c60961dd1e40330b40">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aa5b16d579c2fe6c8a7874a24cb6e4043">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>destBIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a20c505ef21d1c7f1f3c4a7309488ed9c">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#af3a2c005386af4d0fa9e5c32eb46fee2">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>destCIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0a4d37d7b9a0025f7285d3d788635761">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a592299a486cafc80e554b69ccc2580bf">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>dmaChannelHwEvtMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ac205feb9fd0a3575627dbec2f95d176c">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aabc00a71e6a8b9bf895306f680d273ff">EDMA3_DRV_GblConfigParams</a>
</li>
<li>dmaChannelPaRAMMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aef6b47382a74f4aabfa050f6213512d4">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#af1e11302ce81f398d950a7629d6de4a9">EDMA3_DRV_GblConfigParams</a>
</li>
<li>dmaChannelTccMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a09dc86e6c4cbda84547c3033532e1b98">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9ef536e4867fc871dd9971801e0dfc28">EDMA3_DRV_GblConfigParams</a>
</li>
<li>dmaChPaRAMMapExists
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a38ffcc4df844701e587fddc6625255b8">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#acb8118d26c3680cdf2d06179264abb5d">EDMA3_DRV_GblConfigParams</a>
</li>
<li>dmaMapXbarToChan
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#a81951f5e7e005e5916aed68b4996181c">EDMA3_DRV_GblXbarToChanConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#a64c7060f3d51a5a690c01de14723fa0c">EDMA3_DRV_GblXbarToChanConfigParams</a>
</li>
<li>drvInstInitConfig
: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a0311bf1e9522f4b7c3543bd8b76f6a88">EDMA3_DRV_InitConfig</a>
@@ -126,18 +126,18 @@ Here is a list of all documented struct and union fields with links to the struc
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a012dd7bf9aa72726cbe3e5553f778124">EDMA3_DRV_Instance</a>
</li>
<li>DST
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aeed3278cea3d526c83477a4cc0eaee40">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#ad5271044278ba0a0b2c4d24c85055ad7">EDMA3_DRV_ParamentryRegs</a>
</li>
</ul>
<h3><a class="anchor" id="index_e">- e -</a></h3><ul>
<li>evtQPri
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a8970e4cce82366cef852a60cc5dc1a5a">EDMA3_DRV_GblConfigParams</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#a858e5c4051b793b974e6d268c328f2cf">EDMA3_DRV_EvtQuePriority</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a698cb3fedc00b1ce9cac888ee877a45c">EDMA3_DRV_GblConfigParams</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#a495ef97540d6c0984a2cfd2f4ba1cc7c">EDMA3_DRV_EvtQuePriority</a>
</li>
<li>evtQueueWaterMarkLvl
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a60f00b339733c6126951a688072b53b3">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a169774e25daf2f2380126c71ef6f10d8">EDMA3_DRV_GblConfigParams</a>
</li>
</ul>
@@ -163,11 +163,11 @@ Here is a list of all documented struct and union fields with links to the struc
<h3><a class="anchor" id="index_i">- i -</a></h3><ul>
<li>isMaster
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#aa03b188471e9dc09af09a3b9096f7712">EDMA3_DRV_InitConfig</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a5e27d856f44f731c3182c1a854a7acb6">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a91d915bcb63bcf6a9352298c4431cb5b">EDMA3_DRV_InitConfig</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a910f6482cc3e7dbcc72f1e6bd069b65a">EDMA3_DRV_Instance</a>
</li>
<li>isSlave
-: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a812d8f331ad701c3927e28ce4c86d8c0">EDMA3_DRV_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#af8f6c01edfaad57574c8ec1601d44ab6">EDMA3_DRV_MiscParam</a>
</li>
<li>itcchEn
: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#adcd7e3719abfabb3dd1778835002c7c8">EDMA3_DRV_ChainOptions</a>
@@ -180,10 +180,10 @@ Here is a list of all documented struct and union fields with links to the struc
<h3><a class="anchor" id="index_l">- l -</a></h3><ul>
<li>LINK_BCNTRLD
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#acda2db23599012f467bf51f22a01af9e">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#af47568d738013888e93d2f7a9d166b73">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>linkAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a9a90c589c5d20e363b8cd9a64732009e">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0cd745b505f157c103635a09387e1f65">EDMA3_DRV_PaRAMRegs</a>
</li>
</ul>
@@ -193,73 +193,73 @@ Here is a list of all documented struct and union fields with links to the struc
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afac1f63dcd293985df3777abab3b2f9a">EDMA3_DRV_Instance</a>
</li>
<li>memProtectionExists
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#afd883a70d5f8bb868e65a69aa44d0f8e">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a464a49700f3add6848dff2d382f2fac5">EDMA3_DRV_GblConfigParams</a>
</li>
</ul>
<h3><a class="anchor" id="index_n">- n -</a></h3><ul>
<li>numDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1d71e6ded1e1b3d3b14b20a11f896ce3">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a22c319a4bfbcec951d60f3d3e4485846">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numEvtQueue
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ad27e2c83868656fa72ee70a64ac3a534">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9d5c0de0a3fba5504610072367ca8cc9">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numOpens
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#aa02b8fca5781ab737d267b0b46598b80">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#ab3107c1484a016f0766eb11c55e70a16">EDMA3_DRV_Object</a>
</li>
<li>numPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9bf9fc29152fe9ddb63bc86683149fc9">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1add8cd6a0f8db4d829d8726a1d5af8e">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a629d5fc8d59adc8644f5f7a2691b8230">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1f18873723ea015ccd6da3729b013275">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numRegions
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a30316db491c3d5f08182dc5bdde92463">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aa74fc54114ba0d92a25470526b226d4d">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a14c6249081e4225ea140904758377c53">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a2e50b4619dc11a6daf59e63e5d76918c">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numTcs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a8285aab9b38d6369896777f08cb8febd">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a10e128f74fc3b16f0996009f521790f8">EDMA3_DRV_GblConfigParams</a>
</li>
</ul>
<h3><a class="anchor" id="index_o">- o -</a></h3><ul>
<li>OPT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a96fe729021c036ee4a39d58a3c6400e8">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a8fdca7ee065347ea5a50f42cd0914857">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>opt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a32d762dd945673da57fc34f633d078a0">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aea6724d515b3182ec9edb3c19f99d8a5">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>ownDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#aa718b355bf902648c421aef695836fa4">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a1dc3d39936118d391b4a1b95ea0f65e1">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>ownPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ab14f2d879a9d96a3eb41756e134706c8">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a7fdf14b23595c3e97e41500749642b75">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>ownQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a38f397851f049cdebe32340cd2c651c0">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a795ef36bf2e328e6634199a5dbb9c89e">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>ownTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad90d5a8af55128a3157afb45a4f68d56">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#aa8d98245fd41512a85889e477fba5f14">EDMA3_DRV_InstanceInitConfig</a>
</li>
</ul>
<h3><a class="anchor" id="index_p">- p -</a></h3><ul>
<li>param
-: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a9359f6ade97d2f3d910097fafd73da0a">EDMA3_DRV_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#afb7253b18e2a32e513f47c3566c11567">EDMA3_DRV_MiscParam</a>
</li>
<li>paRAMId
-: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#a7e7e0d656a59da04f54465a45e078a03">EDMA3_DRV_ChBoundResources</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ab5ff9e35236c7dc75a8f19bf6aaf25d8">EDMA3_DRV_ChBoundResources</a>
</li>
<li>pDrvObjectHandle
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#acc5b518c2a22a43289ca39438133a30b">EDMA3_DRV_Instance</a>
</li>
<li>phyCtrllerInstId
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#ae0923a080e0da9d1b23cd9cf655775aa">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#a278048cc0afab60a90690750986a60b1">EDMA3_DRV_Object</a>
</li>
</ul>
@@ -270,22 +270,22 @@ Here is a list of all documented struct and union fields with links to the struc
, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a1eb007f153b58999588f5649ecd2143f">EDMA3_DRV_Instance</a>
</li>
<li>reserved
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a6285ab933f20d29b5d6892b895582e24">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#ae4d8210fa6048328ff6e6f9bcb4495dc">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>resMgrInstance
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afc40e1cb787bbdae7afee7c6ea14109e">EDMA3_DRV_Instance</a>
</li>
<li>resvdDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a30630e869042596c4ed487a09bea35c3">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a6166eb480efe999107365112e91791b7">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>resvdPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a81d8b8d85f09f042658db196e208794b">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a8f9bf5f5fabc18ad810ac1da35340944">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>resvdQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad6707e2582dc13b7ea4d3a854834406e">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a743c6c78af10dfab4fc004ed3eebabb2">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>resvdTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a175d4b970b6bf34c05700f4105bae5a6">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a3b23079b2265a753f410a1ca4c01b3aa">EDMA3_DRV_InstanceInitConfig</a>
</li>
</ul>
@@ -295,22 +295,22 @@ Here is a list of all documented struct and union fields with links to the struc
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ad92603735455f8173b6e65467b78694a">EDMA3_DRV_Instance</a>
</li>
<li>SRC
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a6db0f14547c0586bffb62194ffffaf75">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a8579f79e402ee9897bf39293be301f5c">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>SRC_DST_BIDX
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aba20f4c8db04e562e01c6791cfebf258">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a19270fbbb293b073c48d2ce5f1dae870">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>SRC_DST_CIDX
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a65b8a533cf4f336b920341d35b9a10ad">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#afd0ff3d1edca294c7a434bf480221537">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>srcAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a8ac1ab47f33fd6834ed4b378a33faf13">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a3294f54a691bc767513c8b99b21eecaa">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>srcBIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a47d95d95fa2d572116180de42eae6d33">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a3faf892035063076228bc8cd2dfa584e">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>srcCIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#acceb3dbc415f63ee4974c9f3a11a11c6">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a23690d90719731ffb82e84e9a3aa55ef">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>state
: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#adfc26946970b87cc67579ec54c73a221">EDMA3_DRV_Object</a>
@@ -320,16 +320,16 @@ Here is a list of all documented struct and union fields with links to the struc
<h3><a class="anchor" id="index_t">- t -</a></h3><ul>
<li>tcc
-: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ae9afabd97444eada59c7a74a62a5e20d">EDMA3_DRV_ChBoundResources</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ad4e5c0b7026a9ca02984b4a5d0ea552d">EDMA3_DRV_ChBoundResources</a>
</li>
<li>tcchEn
: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#aceecc5cf449e9e5ec46f0ed1854af6e7">EDMA3_DRV_ChainOptions</a>
</li>
<li>tcDefaultBurstSize
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aa217c4ed918c9d5d695ee19ced91ef00">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a0557294e22cf97d82975a8b23e41f040">EDMA3_DRV_GblConfigParams</a>
</li>
<li>tcError
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a3fdbb69b709ecd01dc903ec47e59f5a8">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ae28ee7379bd413340012e9f19665c8c4">EDMA3_DRV_GblConfigParams</a>
</li>
<li>tcintEn
: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#a6d0d65081b0538bed2734adc7c904d61">EDMA3_DRV_ChainOptions</a>
@@ -345,11 +345,11 @@ Here is a list of all documented struct and union fields with links to the struc
<h3><a class="anchor" id="index_x">- x -</a></h3><ul>
<li>xferCompleteInt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a08b4ad4be6b0cd9c6dd046dfe4f68c1e">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a746b0e3fc21383aabf89f6d9dd428969">EDMA3_DRV_GblConfigParams</a>
</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/functions_vars.html b/packages/ti/sdo/edma3/drv/docs/html/functions_vars.html
index 46a7a0e1f49a19d73064f9922c48b4ef3e827634..4ee2b1831959472bbfba9119be5927a67380dbdf 100755 (executable)
<h3><a class="anchor" id="index_a">- a -</a></h3><ul>
<li>A_B_CNT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a07ebc5f75c693a5b50383c0804d1d9e7">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aea70b184b092488704e5182e088d4968">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>aCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aa8b1127bdb0fa8d104a2bdab4c629620">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#af77830b02d859677689f1d0780fea145">EDMA3_DRV_PaRAMRegs</a>
</li>
</ul>
<h3><a class="anchor" id="index_b">- b -</a></h3><ul>
<li>bCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0311c99486c3c8c3ae20751289256ac0">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a8da5f5386a5236c92016c13a4d7fa46c">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>bCntReload
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a877333b51a48685e71608f3d65856049">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aed0fd5b798844697018fe3e18844c36c">EDMA3_DRV_PaRAMRegs</a>
</li>
</ul>
<h3><a class="anchor" id="index_c">- c -</a></h3><ul>
<li>ccError
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a5f7297703c68fdb4d6e9b2a5d4750040">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a682330bc86c34485de0cd00bafd9f493">EDMA3_DRV_GblConfigParams</a>
</li>
<li>CCNT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#ab533890c55e9dd3a71be6b02021823b3">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#adfead71f5566801a10ff1f4749a1e827">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>cCnt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a675509d3b2db629f66cf296ef0498c7d">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a1b5490a1cdd8ee7fe5ec20f1df8bb5d2">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>configScrMapXbarToEvt
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ab697a86b3efb21d2ddbbafa2519d21b1">EDMA3_DRV_Instance</a>
<h3><a class="anchor" id="index_d">- d -</a></h3><ul>
<li>destAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a6e8b9889c9d5d9c60961dd1e40330b40">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aa5b16d579c2fe6c8a7874a24cb6e4043">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>destBIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a20c505ef21d1c7f1f3c4a7309488ed9c">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#af3a2c005386af4d0fa9e5c32eb46fee2">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>destCIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0a4d37d7b9a0025f7285d3d788635761">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a592299a486cafc80e554b69ccc2580bf">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>dmaChannelHwEvtMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ac205feb9fd0a3575627dbec2f95d176c">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aabc00a71e6a8b9bf895306f680d273ff">EDMA3_DRV_GblConfigParams</a>
</li>
<li>dmaChannelPaRAMMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aef6b47382a74f4aabfa050f6213512d4">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#af1e11302ce81f398d950a7629d6de4a9">EDMA3_DRV_GblConfigParams</a>
</li>
<li>dmaChannelTccMap
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a09dc86e6c4cbda84547c3033532e1b98">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9ef536e4867fc871dd9971801e0dfc28">EDMA3_DRV_GblConfigParams</a>
</li>
<li>dmaChPaRAMMapExists
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a38ffcc4df844701e587fddc6625255b8">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#acb8118d26c3680cdf2d06179264abb5d">EDMA3_DRV_GblConfigParams</a>
</li>
<li>dmaMapXbarToChan
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#a81951f5e7e005e5916aed68b4996181c">EDMA3_DRV_GblXbarToChanConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#a64c7060f3d51a5a690c01de14723fa0c">EDMA3_DRV_GblXbarToChanConfigParams</a>
</li>
<li>drvInstInitConfig
: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a0311bf1e9522f4b7c3543bd8b76f6a88">EDMA3_DRV_InitConfig</a>
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a012dd7bf9aa72726cbe3e5553f778124">EDMA3_DRV_Instance</a>
</li>
<li>DST
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aeed3278cea3d526c83477a4cc0eaee40">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#ad5271044278ba0a0b2c4d24c85055ad7">EDMA3_DRV_ParamentryRegs</a>
</li>
</ul>
<h3><a class="anchor" id="index_e">- e -</a></h3><ul>
<li>evtQPri
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a8970e4cce82366cef852a60cc5dc1a5a">EDMA3_DRV_GblConfigParams</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#a858e5c4051b793b974e6d268c328f2cf">EDMA3_DRV_EvtQuePriority</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a698cb3fedc00b1ce9cac888ee877a45c">EDMA3_DRV_GblConfigParams</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#a495ef97540d6c0984a2cfd2f4ba1cc7c">EDMA3_DRV_EvtQuePriority</a>
</li>
<li>evtQueueWaterMarkLvl
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a60f00b339733c6126951a688072b53b3">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a169774e25daf2f2380126c71ef6f10d8">EDMA3_DRV_GblConfigParams</a>
</li>
</ul>
<h3><a class="anchor" id="index_i">- i -</a></h3><ul>
<li>isMaster
-: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#aa03b188471e9dc09af09a3b9096f7712">EDMA3_DRV_InitConfig</a>
-, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a5e27d856f44f731c3182c1a854a7acb6">EDMA3_DRV_Instance</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a91d915bcb63bcf6a9352298c4431cb5b">EDMA3_DRV_InitConfig</a>
+, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a910f6482cc3e7dbcc72f1e6bd069b65a">EDMA3_DRV_Instance</a>
</li>
<li>isSlave
-: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a812d8f331ad701c3927e28ce4c86d8c0">EDMA3_DRV_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#af8f6c01edfaad57574c8ec1601d44ab6">EDMA3_DRV_MiscParam</a>
</li>
<li>itcchEn
: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#adcd7e3719abfabb3dd1778835002c7c8">EDMA3_DRV_ChainOptions</a>
<h3><a class="anchor" id="index_l">- l -</a></h3><ul>
<li>LINK_BCNTRLD
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#acda2db23599012f467bf51f22a01af9e">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#af47568d738013888e93d2f7a9d166b73">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>linkAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a9a90c589c5d20e363b8cd9a64732009e">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0cd745b505f157c103635a09387e1f65">EDMA3_DRV_PaRAMRegs</a>
</li>
</ul>
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afac1f63dcd293985df3777abab3b2f9a">EDMA3_DRV_Instance</a>
</li>
<li>memProtectionExists
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#afd883a70d5f8bb868e65a69aa44d0f8e">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a464a49700f3add6848dff2d382f2fac5">EDMA3_DRV_GblConfigParams</a>
</li>
</ul>
<h3><a class="anchor" id="index_n">- n -</a></h3><ul>
<li>numDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1d71e6ded1e1b3d3b14b20a11f896ce3">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a22c319a4bfbcec951d60f3d3e4485846">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numEvtQueue
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ad27e2c83868656fa72ee70a64ac3a534">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9d5c0de0a3fba5504610072367ca8cc9">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numOpens
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#aa02b8fca5781ab737d267b0b46598b80">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#ab3107c1484a016f0766eb11c55e70a16">EDMA3_DRV_Object</a>
</li>
<li>numPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9bf9fc29152fe9ddb63bc86683149fc9">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1add8cd6a0f8db4d829d8726a1d5af8e">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a629d5fc8d59adc8644f5f7a2691b8230">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1f18873723ea015ccd6da3729b013275">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numRegions
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a30316db491c3d5f08182dc5bdde92463">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aa74fc54114ba0d92a25470526b226d4d">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a14c6249081e4225ea140904758377c53">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a2e50b4619dc11a6daf59e63e5d76918c">EDMA3_DRV_GblConfigParams</a>
</li>
<li>numTcs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a8285aab9b38d6369896777f08cb8febd">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a10e128f74fc3b16f0996009f521790f8">EDMA3_DRV_GblConfigParams</a>
</li>
</ul>
<h3><a class="anchor" id="index_o">- o -</a></h3><ul>
<li>OPT
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a96fe729021c036ee4a39d58a3c6400e8">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a8fdca7ee065347ea5a50f42cd0914857">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>opt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a32d762dd945673da57fc34f633d078a0">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aea6724d515b3182ec9edb3c19f99d8a5">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>ownDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#aa718b355bf902648c421aef695836fa4">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a1dc3d39936118d391b4a1b95ea0f65e1">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>ownPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ab14f2d879a9d96a3eb41756e134706c8">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a7fdf14b23595c3e97e41500749642b75">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>ownQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a38f397851f049cdebe32340cd2c651c0">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a795ef36bf2e328e6634199a5dbb9c89e">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>ownTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad90d5a8af55128a3157afb45a4f68d56">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#aa8d98245fd41512a85889e477fba5f14">EDMA3_DRV_InstanceInitConfig</a>
</li>
</ul>
<h3><a class="anchor" id="index_p">- p -</a></h3><ul>
<li>param
-: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a9359f6ade97d2f3d910097fafd73da0a">EDMA3_DRV_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#afb7253b18e2a32e513f47c3566c11567">EDMA3_DRV_MiscParam</a>
</li>
<li>paRAMId
-: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#a7e7e0d656a59da04f54465a45e078a03">EDMA3_DRV_ChBoundResources</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ab5ff9e35236c7dc75a8f19bf6aaf25d8">EDMA3_DRV_ChBoundResources</a>
</li>
<li>pDrvObjectHandle
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#acc5b518c2a22a43289ca39438133a30b">EDMA3_DRV_Instance</a>
</li>
<li>phyCtrllerInstId
-: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#ae0923a080e0da9d1b23cd9cf655775aa">EDMA3_DRV_Object</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#a278048cc0afab60a90690750986a60b1">EDMA3_DRV_Object</a>
</li>
</ul>
, <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a1eb007f153b58999588f5649ecd2143f">EDMA3_DRV_Instance</a>
</li>
<li>reserved
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a6285ab933f20d29b5d6892b895582e24">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#ae4d8210fa6048328ff6e6f9bcb4495dc">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>resMgrInstance
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afc40e1cb787bbdae7afee7c6ea14109e">EDMA3_DRV_Instance</a>
</li>
<li>resvdDmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a30630e869042596c4ed487a09bea35c3">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a6166eb480efe999107365112e91791b7">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>resvdPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a81d8b8d85f09f042658db196e208794b">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a8f9bf5f5fabc18ad810ac1da35340944">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>resvdQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad6707e2582dc13b7ea4d3a854834406e">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a743c6c78af10dfab4fc004ed3eebabb2">EDMA3_DRV_InstanceInitConfig</a>
</li>
<li>resvdTccs
-: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a175d4b970b6bf34c05700f4105bae5a6">EDMA3_DRV_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a3b23079b2265a753f410a1ca4c01b3aa">EDMA3_DRV_InstanceInitConfig</a>
</li>
</ul>
: <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ad92603735455f8173b6e65467b78694a">EDMA3_DRV_Instance</a>
</li>
<li>SRC
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a6db0f14547c0586bffb62194ffffaf75">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a8579f79e402ee9897bf39293be301f5c">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>SRC_DST_BIDX
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aba20f4c8db04e562e01c6791cfebf258">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a19270fbbb293b073c48d2ce5f1dae870">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>SRC_DST_CIDX
-: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a65b8a533cf4f336b920341d35b9a10ad">EDMA3_DRV_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#afd0ff3d1edca294c7a434bf480221537">EDMA3_DRV_ParamentryRegs</a>
</li>
<li>srcAddr
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a8ac1ab47f33fd6834ed4b378a33faf13">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a3294f54a691bc767513c8b99b21eecaa">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>srcBIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a47d95d95fa2d572116180de42eae6d33">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a3faf892035063076228bc8cd2dfa584e">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>srcCIdx
-: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#acceb3dbc415f63ee4974c9f3a11a11c6">EDMA3_DRV_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a23690d90719731ffb82e84e9a3aa55ef">EDMA3_DRV_PaRAMRegs</a>
</li>
<li>state
: <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#adfc26946970b87cc67579ec54c73a221">EDMA3_DRV_Object</a>
<h3><a class="anchor" id="index_t">- t -</a></h3><ul>
<li>tcc
-: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ae9afabd97444eada59c7a74a62a5e20d">EDMA3_DRV_ChBoundResources</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ad4e5c0b7026a9ca02984b4a5d0ea552d">EDMA3_DRV_ChBoundResources</a>
</li>
<li>tcchEn
: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#aceecc5cf449e9e5ec46f0ed1854af6e7">EDMA3_DRV_ChainOptions</a>
</li>
<li>tcDefaultBurstSize
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aa217c4ed918c9d5d695ee19ced91ef00">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a0557294e22cf97d82975a8b23e41f040">EDMA3_DRV_GblConfigParams</a>
</li>
<li>tcError
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a3fdbb69b709ecd01dc903ec47e59f5a8">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ae28ee7379bd413340012e9f19665c8c4">EDMA3_DRV_GblConfigParams</a>
</li>
<li>tcintEn
: <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html#a6d0d65081b0538bed2734adc7c904d61">EDMA3_DRV_ChainOptions</a>
<h3><a class="anchor" id="index_x">- x -</a></h3><ul>
<li>xferCompleteInt
-: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a08b4ad4be6b0cd9c6dd046dfe4f68c1e">EDMA3_DRV_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a746b0e3fc21383aabf89f6d9dd428969">EDMA3_DRV_GblConfigParams</a>
</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___a_p_i.html b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___a_p_i.html
index b720044cdafdf62740ab738197a3b9174637e46a..191a4e8cd02a1e482448f0a6d8865a3bf362394d 100755 (executable)
Overview</a></h3>
<p>EDMA3 Driver is a functional library providing APIs for programming, scheduling and synchronizing with EDMA transfers and many more. </p>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:00 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___d_a_t_a_s_t_r_u_c_t.html b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___d_a_t_a_s_t_r_u_c_t.html
index b7b2f656adaf668777fe5c13124dcb130037c788..0a89b4158de94ae618ac72039249bc9ca516a6f0 100755 (executable)
--- a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___d_a_t_a_s_t_r_u_c_t.html
+++ b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___d_a_t_a_s_t_r_u_c_t.html
<tr><td class="mdescLeft"> </td><td class="mdescRight">Event queue priorities setup. <a href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#_details">More...</a><br/></td></tr>
</table>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:00 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html
index b628cf6e4386130002e9651828635b28a5eba8a4..a8ca63af74c77d4c06d54c66d28ba40dcf96c03d 100755 (executable)
<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html">EDMA3 Driver Advanced APIs</a></td></tr>
</table>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:00 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html
index 27db22109ade8a14d4ce52601c73524367fa1c7d..2cc75c48fc18fad726f5e4bff5bda42594110e53 100755 (executable)
<tr><td class="memItemLeft" align="right" valign="top">struct </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. <a href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#_details">More...</a><br/></td></tr>
<tr><td colspan="2"><h2>Typedefs</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_DRV_Result(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a> )(unsigned int eventNum, unsigned int *chanNum, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Associates cross bar mapped event to channel. <a href="#gae7867a62f61919df85b323ce981163e4"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_DRV_Result(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a> )(unsigned int eventNum, unsigned int chanNum)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Writes to the cross bar mapped event to channel to system configuration register. <a href="#ga02168cc5612b65b34812ce52df7154a3"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_DRV_Result(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaba09a1e3f0dbc70cff309a0030776168">EDMA3_DRV_mapXbarEvtToChan</a> )(uint32_t eventNum, uint32_t *chanNum, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Associates cross bar mapped event to channel. <a href="#gaba09a1e3f0dbc70cff309a0030776168"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_DRV_Result(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga44bf9e6ccf89645f0fcd1c345d8b5fde">EDMA3_DRV_xbarConfigScr</a> )(uint32_t eventNum, uint32_t chanNum)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Writes to the cross bar mapped event to channel to system configuration register. <a href="#ga44bf9e6ccf89645f0fcd1c345d8b5fde"></a><br/></td></tr>
<tr><td colspan="2"><h2>Functions</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa8561ee446bd1b9d0c5c4b106c9f40a9">EDMA3_DRV_linkChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Link two logical channels. <a href="#gaa8561ee446bd1b9d0c5c4b106c9f40a9"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaca6ef38f26d8e043352fa8963b7f090a">EDMA3_DRV_unlinkChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Unlink the channel from the earlier linked logical channel. <a href="#gaca6ef38f26d8e043352fa8963b7f090a"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gab8e524124e4aaa158fcaf494798def5e">EDMA3_DRV_chainChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a> *chainOptions)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Chain the two specified channels. <a href="#gab8e524124e4aaa158fcaf494798def5e"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gad6424fda12e9b6cccae47ccb22207bcf">EDMA3_DRV_unchainChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Unchain the two channels. <a href="#gad6424fda12e9b6cccae47ccb22207bcf"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga669ea0f2097604af17b9213a28985191">EDMA3_DRV_setQdmaTrigWord</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Assign a Trigger Word to the specified QDMA channel. <a href="#ga669ea0f2097604af17b9213a28985191"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga77841fc83e3876a3014963404cfc08ba">EDMA3_DRV_setPaRAM</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, const <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> *newPaRAM)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). <a href="#ga77841fc83e3876a3014963404cfc08ba"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga437d851ec0eb6c05bb118886ee5c17f2">EDMA3_DRV_getPaRAM</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> *currPaRAM)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). <a href="#ga437d851ec0eb6c05bb118886ee5c17f2"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga83bcb5bc4e319fd6e78466ab5df5c0ac">EDMA3_DRV_setPaRAMEntry</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> paRAMEntry, unsigned int newPaRAMEntryVal)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Set a particular PaRAM set entry of the specified PaRAM set. <a href="#ga83bcb5bc4e319fd6e78466ab5df5c0ac"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga443b63758caa5383ef0f9f66b29fb5e8">EDMA3_DRV_getPaRAMEntry</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> paRAMEntry, unsigned int *paRAMEntryVal)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get a particular PaRAM set entry of the specified PaRAM set. <a href="#ga443b63758caa5383ef0f9f66b29fb5e8"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga41151895e480b66bf320ec662506f078">EDMA3_DRV_setPaRAMField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> paRAMField, unsigned int newPaRAMFieldVal)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Set a particular PaRAM set field of the specified PaRAM set. <a href="#ga41151895e480b66bf320ec662506f078"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1254ca24861fd4b580010f118f093b51">EDMA3_DRV_getPaRAMField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> paRAMField, unsigned int *currPaRAMFieldVal)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get a particular PaRAM set field of the specified PaRAM set. <a href="#ga1254ca24861fd4b580010f118f093b51"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga5d0ac2830ede7245fc7a7b02666c4651">EDMA3_DRV_linkChannel</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh1, uint32_t lCh2)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Link two logical channels. <a href="#ga5d0ac2830ede7245fc7a7b02666c4651"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gab385b2ade87dab8377a3116d5957b4b3">EDMA3_DRV_unlinkChannel</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Unlink the channel from the earlier linked logical channel. <a href="#gab385b2ade87dab8377a3116d5957b4b3"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga523dba0bb68b6a6762ee72d92bd4a003">EDMA3_DRV_chainChannel</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh1, uint32_t lCh2, const <a class="el" href="struct_e_d_m_a3___d_r_v___chain_options.html">EDMA3_DRV_ChainOptions</a> *chainOptions)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Chain the two specified channels. <a href="#ga523dba0bb68b6a6762ee72d92bd4a003"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaea1980b0debbfca7099beddc82613f30">EDMA3_DRV_unchainChannel</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Unchain the two channels. <a href="#gaea1980b0debbfca7099beddc82613f30"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga216c695659e783937361893e2954be67">EDMA3_DRV_setQdmaTrigWord</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_RM_QdmaTrigWord trigWord)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Assign a Trigger Word to the specified QDMA channel. <a href="#ga216c695659e783937361893e2954be67"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae701899e3ecaffde66019991cc075e06">EDMA3_DRV_setPaRAM</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, const <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> *newPaRAM)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). <a href="#gae701899e3ecaffde66019991cc075e06"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gab7a95585219b3140771a6c7e07dea1ee">EDMA3_DRV_getPaRAM</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html">EDMA3_DRV_PaRAMRegs</a> *currPaRAM)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). <a href="#gab7a95585219b3140771a6c7e07dea1ee"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga801246bc529343f0324d125c65537fe8">EDMA3_DRV_setPaRAMEntry</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> paRAMEntry, uint32_t newPaRAMEntryVal)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Set a particular PaRAM set entry of the specified PaRAM set. <a href="#ga801246bc529343f0324d125c65537fe8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gad131a9d84d316d8c2c73c37ad8f6b520">EDMA3_DRV_getPaRAMEntry</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga82b01ec2292a13ad48a5bfcc724dfac6">EDMA3_DRV_PaRAMEntry</a> paRAMEntry, uint32_t *paRAMEntryVal)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get a particular PaRAM set entry of the specified PaRAM set. <a href="#gad131a9d84d316d8c2c73c37ad8f6b520"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga6b57b385ba8fca2757da48f714550f99">EDMA3_DRV_setPaRAMField</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> paRAMField, uint32_t newPaRAMFieldVal)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Set a particular PaRAM set field of the specified PaRAM set. <a href="#ga6b57b385ba8fca2757da48f714550f99"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga58d0eb4347d9aad2035d60054e70a6bb">EDMA3_DRV_getPaRAMField</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga3e31ba1b02dcbace3044c11c83ef5466">EDMA3_DRV_PaRAMField</a> paRAMField, uint32_t *currPaRAMFieldVal)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get a particular PaRAM set field of the specified PaRAM set. <a href="#ga58d0eb4347d9aad2035d60054e70a6bb"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga6a6c40cddb7bb7bc74635e104757e225">EDMA3_DRV_setEvtQPriority</a> (EDMA3_DRV_Handle hEdma, const <a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html">EDMA3_DRV_EvtQuePriority</a> *evtQPriObj)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Sets EDMA TC priority. <a href="#ga6a6c40cddb7bb7bc74635e104757e225"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga4419ae8ba6468ec35090e2717a28f958">EDMA3_DRV_mapChToEvtQ</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Associate Channel to Event Queue. <a href="#ga4419ae8ba6468ec35090e2717a28f958"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gab2058b44b471c44d001035e1a38fd06d">EDMA3_DRV_getMapChToEvtQ</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the Event Queue mapped to the specified DMA/QDMA channel. <a href="#gab2058b44b471c44d001035e1a38fd06d"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga2574c3da30322981b763e54dd1ea7fb2">EDMA3_DRV_setCCRegister</a> (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Set the Channel Controller (CC) Register value. <a href="#ga2574c3da30322981b763e54dd1ea7fb2"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga297f964f8fa3df44683e1bdedd56d928">EDMA3_DRV_getCCRegister</a> (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the Channel Controller (CC) Register value. <a href="#ga297f964f8fa3df44683e1bdedd56d928"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa73fe4d0c29760be55306a8fc1f35161">EDMA3_DRV_waitAndClearTcc</a> (EDMA3_DRV_Handle hEdma, unsigned int tccNo)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait for a transfer completion interrupt to occur and clear it. <a href="#gaa73fe4d0c29760be55306a8fc1f35161"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga3c098a85435e55a8eff2561cbcd79a77">EDMA3_DRV_checkAndClearTcc</a> (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Returns the status of a previously initiated transfer. <a href="#ga3c098a85435e55a8eff2561cbcd79a77"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gafeb7b2a17615b14bdac9b11af69e5142">EDMA3_DRV_getPaRAMPhyAddr</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the PaRAM Set Physical Address associated with a logical channel. <a href="#gafeb7b2a17615b14bdac9b11af69e5142"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga858eae593371bd2e8e88ea31ca89dee2">EDMA3_DRV_mapChToEvtQ</a> (EDMA3_DRV_Handle hEdma, uint32_t channelId, EDMA3_RM_EventQueue eventQ)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Associate Channel to Event Queue. <a href="#ga858eae593371bd2e8e88ea31ca89dee2"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga113009d6273cb3079376c41780bea56f">EDMA3_DRV_getMapChToEvtQ</a> (EDMA3_DRV_Handle hEdma, uint32_t channelId, uint32_t *mappedEvtQ)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the Event Queue mapped to the specified DMA/QDMA channel. <a href="#ga113009d6273cb3079376c41780bea56f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga4e63b90bcd4fdc809fa28f73eac708b0">EDMA3_DRV_setCCRegister</a> (EDMA3_DRV_Handle hEdma, uint32_t regOffset, uint32_t newRegValue)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Set the Channel Controller (CC) Register value. <a href="#ga4e63b90bcd4fdc809fa28f73eac708b0"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae76237491d2e0fb58094b8a22b551943">EDMA3_DRV_getCCRegister</a> (EDMA3_DRV_Handle hEdma, uint32_t regOffset, uint32_t *regValue)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the Channel Controller (CC) Register value. <a href="#gae76237491d2e0fb58094b8a22b551943"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gacbb02cd93e37f680e9ce6c4a710c6769">EDMA3_DRV_waitAndClearTcc</a> (EDMA3_DRV_Handle hEdma, uint32_t tccNo)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait for a transfer completion interrupt to occur and clear it. <a href="#gacbb02cd93e37f680e9ce6c4a710c6769"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae954e4efc65de14d1f863b83b6bf85a9">EDMA3_DRV_checkAndClearTcc</a> (EDMA3_DRV_Handle hEdma, uint32_t tccNo, uint16_t *tccStatus)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Returns the status of a previously initiated transfer. <a href="#gae954e4efc65de14d1f863b83b6bf85a9"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga8f3c8ae97270c310f740d5eb95ae014a">EDMA3_DRV_getPaRAMPhyAddr</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, uint32_t *paramPhyAddr)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the PaRAM Set Physical Address associated with a logical channel. <a href="#ga8f3c8ae97270c310f740d5eb95ae014a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga379162d6a5076160d4ed2e01ca8dcac6">EDMA3_DRV_Ioctl</a> (EDMA3_DRV_Handle hEdma, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8577940463f7ca5a8977b2fb65fae19a">EDMA3_DRV_IoctlCmd</a> cmd, void *cmdArg, void *param)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 Driver IOCTL. <a href="#ga379162d6a5076160d4ed2e01ca8dcac6"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Handle </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga866c17eaf78a3e0ddc83a397b91fe850">EDMA3_DRV_getInstHandle</a> (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Return the previously opened EDMA3 Driver Instance handle. <a href="#ga866c17eaf78a3e0ddc83a397b91fe850"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga43031c6c66af92677c388c156b50480b">EDMA3_DRV_registerTccCb</a> (EDMA3_DRV_Handle hEdma, const unsigned int channelId, EDMA3_RM_TccCallback tccCb, void *cbData)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Registers a transfer completion handler for a specific DMA/QDMA channel. <a href="#ga43031c6c66af92677c388c156b50480b"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa4ab2ce058e4e40a812b8a20970d4088">EDMA3_DRV_unregisterTccCb</a> (EDMA3_DRV_Handle hEdma, const unsigned int channelId)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Un-register the previously registered callback function against a DMA/QDMA channel. <a href="#gaa4ab2ce058e4e40a812b8a20970d4088"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga276f4ecd7f1e59f09ad065b633643ae4">EDMA3_DRV_setTcErrorInt</a> (unsigned int phyCtrllerInstId, unsigned int tcId, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga2b3b55b1d7c987a7873d8b0b085173b2">EDMA3_DRV_Tc_Err</a> tcErr)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable specific EDMA3 Transfer Controller Interrupts. <a href="#ga276f4ecd7f1e59f09ad065b633643ae4"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga85bad51ec992ce36ed7f28842b7d8219">EDMA3_DRV_getChannelStatus</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *lchStatus)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the current status of the DMA/QDMA channel. <a href="#ga85bad51ec992ce36ed7f28842b7d8219"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaba9535a00375255494df382382b834de">EDMA3_DRV_mapTccLinkCh</a> (EDMA3_DRV_Handle hEdma, unsigned int linkCh, unsigned int tcc)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Associates a link channel and a TCC. <a href="#gaba9535a00375255494df382382b834de"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1ff9d2ede0fb29c7194f15ba58ad8e0f">EDMA3_DRV_initXbarEventMap</a> (EDMA3_DRV_Handle hEdma, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a> mapXbarEvtFunc, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a> configXbarScr)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Handle </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga5b2b47b7f30d5232fae53bbf5e38ad17">EDMA3_DRV_getInstHandle</a> (uint32_t phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Return the previously opened EDMA3 Driver Instance handle. <a href="#ga5b2b47b7f30d5232fae53bbf5e38ad17"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga88d42967b207c6cf6f15862e1c7d562c">EDMA3_DRV_registerTccCb</a> (EDMA3_DRV_Handle hEdma, const uint32_t channelId, EDMA3_RM_TccCallback tccCb, void *cbData)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Registers a transfer completion handler for a specific DMA/QDMA channel. <a href="#ga88d42967b207c6cf6f15862e1c7d562c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga472684db77a1980ea38a2eb9acaea649">EDMA3_DRV_unregisterTccCb</a> (EDMA3_DRV_Handle hEdma, const uint32_t channelId)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Un-register the previously registered callback function against a DMA/QDMA channel. <a href="#ga472684db77a1980ea38a2eb9acaea649"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaad724400dcbc9418ab1122a0c047efd2">EDMA3_DRV_setTcErrorInt</a> (uint32_t phyCtrllerInstId, uint32_t tcId, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga2b3b55b1d7c987a7873d8b0b085173b2">EDMA3_DRV_Tc_Err</a> tcErr)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable specific EDMA3 Transfer Controller Interrupts. <a href="#gaad724400dcbc9418ab1122a0c047efd2"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga0241fe8f5788e4b4b217d650a383cf39">EDMA3_DRV_getChannelStatus</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, uint32_t *lchStatus)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the current status of the DMA/QDMA channel. <a href="#ga0241fe8f5788e4b4b217d650a383cf39"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaeff038764ab896e127e803557d543f7f">EDMA3_DRV_mapTccLinkCh</a> (EDMA3_DRV_Handle hEdma, uint32_t linkCh, uint32_t tcc)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Associates a link channel and a TCC. <a href="#gaeff038764ab896e127e803557d543f7f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1ff9d2ede0fb29c7194f15ba58ad8e0f">EDMA3_DRV_initXbarEventMap</a> (EDMA3_DRV_Handle hEdma, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaba09a1e3f0dbc70cff309a0030776168">EDMA3_DRV_mapXbarEvtToChan</a> mapXbarEvtFunc, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga44bf9e6ccf89645f0fcd1c345d8b5fde">EDMA3_DRV_xbarConfigScr</a> configXbarScr)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Initialize the cross bar mapped event to channel function. <a href="#ga1ff9d2ede0fb29c7194f15ba58ad8e0f"></a><br/></td></tr>
</table>
<hr/><h2>Typedef Documentation</h2>
-<a class="anchor" id="gae7867a62f61919df85b323ce981163e4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapXbarEvtToChan" ref="gae7867a62f61919df85b323ce981163e4" args=")(unsigned int eventNum, unsigned int *chanNum, const EDMA3_DRV_GblXbarToChanConfigParams *edmaGblXbarConfig)" -->
+<a class="anchor" id="gaba09a1e3f0dbc70cff309a0030776168"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapXbarEvtToChan" ref="gaba09a1e3f0dbc70cff309a0030776168" args=")(uint32_t eventNum, uint32_t *chanNum, const EDMA3_DRV_GblXbarToChanConfigParams *edmaGblXbarConfig)" -->
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- <td class="memname">typedef EDMA3_DRV_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a>)(unsigned int eventNum, unsigned int *chanNum, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td>
+ <td class="memname">typedef EDMA3_DRV_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaba09a1e3f0dbc70cff309a0030776168">EDMA3_DRV_mapXbarEvtToChan</a>)(uint32_t eventNum, uint32_t *chanNum, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="ga02168cc5612b65b34812ce52df7154a3"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_xbarConfigScr" ref="ga02168cc5612b65b34812ce52df7154a3" args=")(unsigned int eventNum, unsigned int chanNum)" -->
+<a class="anchor" id="ga44bf9e6ccf89645f0fcd1c345d8b5fde"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_xbarConfigScr" ref="ga44bf9e6ccf89645f0fcd1c345d8b5fde" args=")(uint32_t eventNum, uint32_t chanNum)" -->
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<div class="memproto">
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- <td class="memname">typedef EDMA3_DRV_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a>)(unsigned int eventNum, unsigned int chanNum)</td>
+ <td class="memname">typedef EDMA3_DRV_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga44bf9e6ccf89645f0fcd1c345d8b5fde">EDMA3_DRV_xbarConfigScr</a>)(uint32_t eventNum, uint32_t chanNum)</td>
</tr>
</table>
</div>
</div>
</div>
<hr/><h2>Function Documentation</h2>
-<a class="anchor" id="gaa8561ee446bd1b9d0c5c4b106c9f40a9"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_linkChannel" ref="gaa8561ee446bd1b9d0c5c4b106c9f40a9" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)" -->
+<a class="anchor" id="ga5d0ac2830ede7245fc7a7b02666c4651"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_linkChannel" ref="ga5d0ac2830ede7245fc7a7b02666c4651" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh1, uint32_t lCh2)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh2</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gaca6ef38f26d8e043352fa8963b7f090a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unlinkChannel" ref="gaca6ef38f26d8e043352fa8963b7f090a" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh)" -->
+<a class="anchor" id="gab385b2ade87dab8377a3116d5957b4b3"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unlinkChannel" ref="gab385b2ade87dab8377a3116d5957b4b3" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh)" -->
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<div class="memproto">
<table class="memname">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gab8e524124e4aaa158fcaf494798def5e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_chainChannel" ref="gab8e524124e4aaa158fcaf494798def5e" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const EDMA3_DRV_ChainOptions *chainOptions)" -->
+<a class="anchor" id="ga523dba0bb68b6a6762ee72d92bd4a003"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_chainChannel" ref="ga523dba0bb68b6a6762ee72d92bd4a003" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh1, uint32_t lCh2, const EDMA3_DRV_ChainOptions *chainOptions)" -->
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<div class="memproto">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh1</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh2</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gad6424fda12e9b6cccae47ccb22207bcf"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unchainChannel" ref="gad6424fda12e9b6cccae47ccb22207bcf" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh)" -->
+<a class="anchor" id="gaea1980b0debbfca7099beddc82613f30"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unchainChannel" ref="gaea1980b0debbfca7099beddc82613f30" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga669ea0f2097604af17b9213a28985191"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setQdmaTrigWord" ref="ga669ea0f2097604af17b9213a28985191" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)" -->
+<a class="anchor" id="ga216c695659e783937361893e2954be67"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setQdmaTrigWord" ref="ga216c695659e783937361893e2954be67" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_RM_QdmaTrigWord trigWord)" -->
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<div class="memproto">
<table class="memname">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga77841fc83e3876a3014963404cfc08ba"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAM" ref="ga77841fc83e3876a3014963404cfc08ba" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)" -->
+<a class="anchor" id="gae701899e3ecaffde66019991cc075e06"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAM" ref="gae701899e3ecaffde66019991cc075e06" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)" -->
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<div class="memproto">
<table class="memname">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga437d851ec0eb6c05bb118886ee5c17f2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAM" ref="ga437d851ec0eb6c05bb118886ee5c17f2" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)" -->
+<a class="anchor" id="gab7a95585219b3140771a6c7e07dea1ee"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAM" ref="gab7a95585219b3140771a6c7e07dea1ee" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga83bcb5bc4e319fd6e78466ab5df5c0ac"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAMEntry" ref="ga83bcb5bc4e319fd6e78466ab5df5c0ac" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int newPaRAMEntryVal)" -->
+<a class="anchor" id="ga801246bc529343f0324d125c65537fe8"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAMEntry" ref="ga801246bc529343f0324d125c65537fe8" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, uint32_t newPaRAMEntryVal)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>newPaRAMEntryVal</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga443b63758caa5383ef0f9f66b29fb5e8"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMEntry" ref="ga443b63758caa5383ef0f9f66b29fb5e8" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int *paRAMEntryVal)" -->
+<a class="anchor" id="gad131a9d84d316d8c2c73c37ad8f6b520"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMEntry" ref="gad131a9d84d316d8c2c73c37ad8f6b520" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, uint32_t *paRAMEntryVal)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>paRAMEntryVal</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga41151895e480b66bf320ec662506f078"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAMField" ref="ga41151895e480b66bf320ec662506f078" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int newPaRAMFieldVal)" -->
+<a class="anchor" id="ga6b57b385ba8fca2757da48f714550f99"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setPaRAMField" ref="ga6b57b385ba8fca2757da48f714550f99" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_DRV_PaRAMField paRAMField, uint32_t newPaRAMFieldVal)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>newPaRAMFieldVal</em></td><td> </td>
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<tr>
</div>
</div>
-<a class="anchor" id="ga1254ca24861fd4b580010f118f093b51"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMField" ref="ga1254ca24861fd4b580010f118f093b51" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int *currPaRAMFieldVal)" -->
+<a class="anchor" id="ga58d0eb4347d9aad2035d60054e70a6bb"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMField" ref="ga58d0eb4347d9aad2035d60054e70a6bb" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_DRV_PaRAMField paRAMField, uint32_t *currPaRAMFieldVal)" -->
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<div class="memproto">
<table class="memname">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>currPaRAMFieldVal</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga4419ae8ba6468ec35090e2717a28f958"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapChToEvtQ" ref="ga4419ae8ba6468ec35090e2717a28f958" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)" -->
+<a class="anchor" id="ga858eae593371bd2e8e88ea31ca89dee2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapChToEvtQ" ref="ga858eae593371bd2e8e88ea31ca89dee2" args="(EDMA3_DRV_Handle hEdma, uint32_t channelId, EDMA3_RM_EventQueue eventQ)" -->
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<div class="memproto">
<table class="memname">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>channelId</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gab2058b44b471c44d001035e1a38fd06d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getMapChToEvtQ" ref="gab2058b44b471c44d001035e1a38fd06d" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)" -->
+<a class="anchor" id="ga113009d6273cb3079376c41780bea56f"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getMapChToEvtQ" ref="ga113009d6273cb3079376c41780bea56f" args="(EDMA3_DRV_Handle hEdma, uint32_t channelId, uint32_t *mappedEvtQ)" -->
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- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>channelId</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>mappedEvtQ</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga2574c3da30322981b763e54dd1ea7fb2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setCCRegister" ref="ga2574c3da30322981b763e54dd1ea7fb2" args="(EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)" -->
+<a class="anchor" id="ga4e63b90bcd4fdc809fa28f73eac708b0"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setCCRegister" ref="ga4e63b90bcd4fdc809fa28f73eac708b0" args="(EDMA3_DRV_Handle hEdma, uint32_t regOffset, uint32_t newRegValue)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>regOffset</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>newRegValue</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga297f964f8fa3df44683e1bdedd56d928"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getCCRegister" ref="ga297f964f8fa3df44683e1bdedd56d928" args="(EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)" -->
+<a class="anchor" id="gae76237491d2e0fb58094b8a22b551943"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getCCRegister" ref="gae76237491d2e0fb58094b8a22b551943" args="(EDMA3_DRV_Handle hEdma, uint32_t regOffset, uint32_t *regValue)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>regOffset</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>regValue</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gaa73fe4d0c29760be55306a8fc1f35161"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_waitAndClearTcc" ref="gaa73fe4d0c29760be55306a8fc1f35161" args="(EDMA3_DRV_Handle hEdma, unsigned int tccNo)" -->
+<a class="anchor" id="gacbb02cd93e37f680e9ce6c4a710c6769"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_waitAndClearTcc" ref="gacbb02cd93e37f680e9ce6c4a710c6769" args="(EDMA3_DRV_Handle hEdma, uint32_t tccNo)" -->
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<table class="memname">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>tccNo</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga3c098a85435e55a8eff2561cbcd79a77"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_checkAndClearTcc" ref="ga3c098a85435e55a8eff2561cbcd79a77" args="(EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)" -->
+<a class="anchor" id="gae954e4efc65de14d1f863b83b6bf85a9"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_checkAndClearTcc" ref="gae954e4efc65de14d1f863b83b6bf85a9" args="(EDMA3_DRV_Handle hEdma, uint32_t tccNo, uint16_t *tccStatus)" -->
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<table class="memname">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>tccNo</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned short * </td>
+ <td class="paramtype">uint16_t * </td>
<td class="paramname"> <em>tccStatus</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gafeb7b2a17615b14bdac9b11af69e5142"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMPhyAddr" ref="gafeb7b2a17615b14bdac9b11af69e5142" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)" -->
+<a class="anchor" id="ga8f3c8ae97270c310f740d5eb95ae014a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getPaRAMPhyAddr" ref="ga8f3c8ae97270c310f740d5eb95ae014a" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, uint32_t *paramPhyAddr)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>paramPhyAddr</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga866c17eaf78a3e0ddc83a397b91fe850"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getInstHandle" ref="ga866c17eaf78a3e0ddc83a397b91fe850" args="(unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)" -->
+<a class="anchor" id="ga5b2b47b7f30d5232fae53bbf5e38ad17"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getInstHandle" ref="ga5b2b47b7f30d5232fae53bbf5e38ad17" args="(uint32_t phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">EDMA3_DRV_Handle EDMA3_DRV_getInstHandle </td>
<td>(</td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>phyCtrllerInstId</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga43031c6c66af92677c388c156b50480b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_registerTccCb" ref="ga43031c6c66af92677c388c156b50480b" args="(EDMA3_DRV_Handle hEdma, const unsigned int channelId, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
+<a class="anchor" id="ga88d42967b207c6cf6f15862e1c7d562c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_registerTccCb" ref="ga88d42967b207c6cf6f15862e1c7d562c" args="(EDMA3_DRV_Handle hEdma, const uint32_t channelId, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">const unsigned int </td>
+ <td class="paramtype">const uint32_t </td>
<td class="paramname"> <em>channelId</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gaa4ab2ce058e4e40a812b8a20970d4088"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unregisterTccCb" ref="gaa4ab2ce058e4e40a812b8a20970d4088" args="(EDMA3_DRV_Handle hEdma, const unsigned int channelId)" -->
+<a class="anchor" id="ga472684db77a1980ea38a2eb9acaea649"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_unregisterTccCb" ref="ga472684db77a1980ea38a2eb9acaea649" args="(EDMA3_DRV_Handle hEdma, const uint32_t channelId)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">const unsigned int </td>
+ <td class="paramtype">const uint32_t </td>
<td class="paramname"> <em>channelId</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga276f4ecd7f1e59f09ad065b633643ae4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setTcErrorInt" ref="ga276f4ecd7f1e59f09ad065b633643ae4" args="(unsigned int phyCtrllerInstId, unsigned int tcId, EDMA3_DRV_Tc_Err tcErr)" -->
+<a class="anchor" id="gaad724400dcbc9418ab1122a0c047efd2"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setTcErrorInt" ref="gaad724400dcbc9418ab1122a0c047efd2" args="(uint32_t phyCtrllerInstId, uint32_t tcId, EDMA3_DRV_Tc_Err tcErr)" -->
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<div class="memproto">
<table class="memname">
<tr>
<td class="memname">EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt </td>
<td>(</td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>phyCtrllerInstId</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>tcId</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga85bad51ec992ce36ed7f28842b7d8219"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getChannelStatus" ref="ga85bad51ec992ce36ed7f28842b7d8219" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *lchStatus)" -->
+<a class="anchor" id="ga0241fe8f5788e4b4b217d650a383cf39"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getChannelStatus" ref="ga0241fe8f5788e4b4b217d650a383cf39" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, uint32_t *lchStatus)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>lchStatus</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gaba9535a00375255494df382382b834de"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapTccLinkCh" ref="gaba9535a00375255494df382382b834de" args="(EDMA3_DRV_Handle hEdma, unsigned int linkCh, unsigned int tcc)" -->
+<a class="anchor" id="gaeff038764ab896e127e803557d543f7f"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_mapTccLinkCh" ref="gaeff038764ab896e127e803557d543f7f" args="(EDMA3_DRV_Handle hEdma, uint32_t linkCh, uint32_t tcc)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>linkCh</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>tcc</em></td><td> </td>
</tr>
<tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a> </td>
+ <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaba09a1e3f0dbc70cff309a0030776168">EDMA3_DRV_mapXbarEvtToChan</a> </td>
<td class="paramname"> <em>mapXbarEvtFunc</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a> </td>
+ <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga44bf9e6ccf89645f0fcd1c345d8b5fde">EDMA3_DRV_xbarConfigScr</a> </td>
<td class="paramname"> <em>configXbarScr</em></td><td> </td>
</tr>
<tr>
</div>
</div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html
index 4530c0e2c4cd76e82ab9cd7794a63f00b9f46d74..a9f8ab4913e54f5190689b3048d2e5ce731101e3 100755 (executable)
[<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html">EDMA3 Driver APIs</a>]</small>
</h1><table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Functions</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e">EDMA3_DRV_requestChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Request a DMA/QDMA/Link channel. <a href="#ga301122cb5f7cca50ae824611bd816f8e"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga0589ed9b15b42ecefc4a6ccd8e1758fc">EDMA3_DRV_freeChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. <a href="#ga0589ed9b15b42ecefc4a6ccd8e1758fc"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga35daa16c899b38d5af19d7d2d22777a5">EDMA3_DRV_clearErrorBits</a> (EDMA3_DRV_Handle hEdma, unsigned int channelId)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Disables the DMA Channel by clearing the Event Enable Register and clears Error Register & Secondary Event Register for a specific DMA channel. <a href="#ga35daa16c899b38d5af19d7d2d22777a5"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga095f1fea5377f30e65e6135414ad6e77">EDMA3_DRV_setOptField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> optField, unsigned int newOptFieldVal)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. <a href="#ga095f1fea5377f30e65e6135414ad6e77"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gad6bc4ec80662493860491f6374af7695">EDMA3_DRV_getOptField</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> optField, unsigned int *optFieldVal)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. <a href="#gad6bc4ec80662493860491f6374af7695"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga95f7e74ccb30f273b42b0cc08664ba55">EDMA3_DRV_setSrcParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> addrMode, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> fifoWidth)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">DMA source parameters setup. <a href="#ga95f7e74ccb30f273b42b0cc08664ba55"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gab4be03dc87dc50975c5ea870944dcee4">EDMA3_DRV_setDestParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> addrMode, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> fifoWidth)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">DMA Destination parameters setup. <a href="#gab4be03dc87dc50975c5ea870944dcee4"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga212d4abb6f644084b3a29b856c0ef0ac">EDMA3_DRV_setSrcIndex</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">DMA source index setup. <a href="#ga212d4abb6f644084b3a29b856c0ef0ac"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga4e7ec3c58f498bdbac7a507e0cba6221">EDMA3_DRV_setDestIndex</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">DMA destination index setup. <a href="#ga4e7ec3c58f498bdbac7a507e0cba6221"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga8e54f2e2e016bc557ed3374eb46d62ee">EDMA3_DRV_setTransferParams</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga1cc0705e142298a424a312034bd3b2c2">EDMA3_DRV_SyncType</a> syncType)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">DMA transfer parameters setup. <a href="#ga8e54f2e2e016bc557ed3374eb46d62ee"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga5c80afa7645f1e492951c0419c21dbe6">EDMA3_DRV_enableTransfer</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Start EDMA transfer on the specified channel. <a href="#ga5c80afa7645f1e492951c0419c21dbe6"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gadb56f2a6d896c03a77f14c8fdf57a397">EDMA3_DRV_disableTransfer</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Disable DMA transfer on the specified channel. <a href="#gadb56f2a6d896c03a77f14c8fdf57a397"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga11070a2e9fb80e16fe96e8ad210e0b59">EDMA3_DRV_disableLogicalChannel</a> (EDMA3_DRV_Handle hEdma, unsigned int lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Disable the event driven DMA channel or QDMA channel. <a href="#ga11070a2e9fb80e16fe96e8ad210e0b59"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06">EDMA3_DRV_requestChannel</a> (EDMA3_DRV_Handle hEdma, uint32_t *pLCh, uint32_t *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Request a DMA/QDMA/Link channel. <a href="#gaf972552f53ce9efe4db7bfe6db275c06"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga9b9c0be3ecedbaef8a136a3a515b0a7a">EDMA3_DRV_freeChannel</a> (EDMA3_DRV_Handle hEdma, uint32_t channelId)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings. <a href="#ga9b9c0be3ecedbaef8a136a3a515b0a7a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga3a43d634119deb804bf214c54d6be3d8">EDMA3_DRV_clearErrorBits</a> (EDMA3_DRV_Handle hEdma, uint32_t channelId)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Disables the DMA Channel by clearing the Event Enable Register and clears Error Register & Secondary Event Register for a specific DMA channel. <a href="#ga3a43d634119deb804bf214c54d6be3d8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga057f492e45940e2b7ba12b8d48d49e15">EDMA3_DRV_setOptField</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> optField, uint32_t newOptFieldVal)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. <a href="#ga057f492e45940e2b7ba12b8d48d49e15"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga05d77b37318ef8e81868a28678a7b2ac">EDMA3_DRV_getOptField</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#gaa0c576e8e46ac8db85c05bf73c01a5f9">EDMA3_DRV_OptField</a> optField, uint32_t *optFieldVal)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'. <a href="#ga05d77b37318ef8e81868a28678a7b2ac"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga89c3174bf68727a9bc653d38989449ad">EDMA3_DRV_setSrcParams</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, uint32_t srcAddr, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> addrMode, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> fifoWidth)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">DMA source parameters setup. <a href="#ga89c3174bf68727a9bc653d38989449ad"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga2a1ae983cef808737455677b7c2c0fb5">EDMA3_DRV_setDestParams</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, uint32_t destAddr, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga5896f43e878f4e9c47b449fccdec3af9">EDMA3_DRV_AddrMode</a> addrMode, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga8c37673293432ed46f9e26f04f5681dc">EDMA3_DRV_FifoWidth</a> fifoWidth)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">DMA Destination parameters setup. <a href="#ga2a1ae983cef808737455677b7c2c0fb5"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaa4f81e82c3c44391074ff86444080fa4">EDMA3_DRV_setSrcIndex</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, int32_t srcBIdx, int32_t srcCIdx)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">DMA source index setup. <a href="#gaa4f81e82c3c44391074ff86444080fa4"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga743d009b49ca70a22c6f1fbec0683f82">EDMA3_DRV_setDestIndex</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, int32_t destBIdx, int32_t destCIdx)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">DMA destination index setup. <a href="#ga743d009b49ca70a22c6f1fbec0683f82"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga44ba1ae06ac1a6aba94bd3f86f8e4f2e">EDMA3_DRV_setTransferParams</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, uint32_t aCnt, uint32_t bCnt, uint32_t cCnt, uint32_t bCntReload, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga1cc0705e142298a424a312034bd3b2c2">EDMA3_DRV_SyncType</a> syncType)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">DMA transfer parameters setup. <a href="#ga44ba1ae06ac1a6aba94bd3f86f8e4f2e"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga421bbec32ba1335296de937e35acc215">EDMA3_DRV_getVersion</a> (void)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Version information. <a href="#ga421bbec32ba1335296de937e35acc215"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">const char * </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga43f6e71816afb2d823a73ee9f90b073b">EDMA3_DRV_getVersionStr</a> (void)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Version string querry. <a href="#ga43f6e71816afb2d823a73ee9f90b073b"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga058da475e4b2e6db3f745611bd26fb27">EDMA3_DRV_enableTransfer</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Start EDMA transfer on the specified channel. <a href="#ga058da475e4b2e6db3f745611bd26fb27"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga999444d7f079889ea8e1c825b8bdd05a">EDMA3_DRV_disableTransfer</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Disable DMA transfer on the specified channel. <a href="#ga999444d7f079889ea8e1c825b8bdd05a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaeb4d5d16d283e5dda906cdac67a44d18">EDMA3_DRV_disableLogicalChannel</a> (EDMA3_DRV_Handle hEdma, uint32_t lCh, <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> trigMode)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Disable the event driven DMA channel or QDMA channel. <a href="#gaeb4d5d16d283e5dda906cdac67a44d18"></a><br/></td></tr>
</table>
<hr/><h2>Function Documentation</h2>
-<a class="anchor" id="ga301122cb5f7cca50ae824611bd816f8e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_requestChannel" ref="ga301122cb5f7cca50ae824611bd816f8e" args="(EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
+<a class="anchor" id="gaf972552f53ce9efe4db7bfe6db275c06"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_requestChannel" ref="gaf972552f53ce9efe4db7bfe6db275c06" args="(EDMA3_DRV_Handle hEdma, uint32_t *pLCh, uint32_t *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
<div class="memitem">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>pLCh</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>pTcc</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga0589ed9b15b42ecefc4a6ccd8e1758fc"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_freeChannel" ref="ga0589ed9b15b42ecefc4a6ccd8e1758fc" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId)" -->
+<a class="anchor" id="ga9b9c0be3ecedbaef8a136a3a515b0a7a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_freeChannel" ref="ga9b9c0be3ecedbaef8a136a3a515b0a7a" args="(EDMA3_DRV_Handle hEdma, uint32_t channelId)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>channelId</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga35daa16c899b38d5af19d7d2d22777a5"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_clearErrorBits" ref="ga35daa16c899b38d5af19d7d2d22777a5" args="(EDMA3_DRV_Handle hEdma, unsigned int channelId)" -->
+<a class="anchor" id="ga3a43d634119deb804bf214c54d6be3d8"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_clearErrorBits" ref="ga3a43d634119deb804bf214c54d6be3d8" args="(EDMA3_DRV_Handle hEdma, uint32_t channelId)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>channelId</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga095f1fea5377f30e65e6135414ad6e77"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setOptField" ref="ga095f1fea5377f30e65e6135414ad6e77" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int newOptFieldVal)" -->
+<a class="anchor" id="ga057f492e45940e2b7ba12b8d48d49e15"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setOptField" ref="ga057f492e45940e2b7ba12b8d48d49e15" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_DRV_OptField optField, uint32_t newOptFieldVal)" -->
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<table class="memname">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>newOptFieldVal</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gad6bc4ec80662493860491f6374af7695"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getOptField" ref="gad6bc4ec80662493860491f6374af7695" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int *optFieldVal)" -->
+<a class="anchor" id="ga05d77b37318ef8e81868a28678a7b2ac"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getOptField" ref="ga05d77b37318ef8e81868a28678a7b2ac" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_DRV_OptField optField, uint32_t *optFieldVal)" -->
<div class="memitem">
<div class="memproto">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>optFieldVal</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga95f7e74ccb30f273b42b0cc08664ba55"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setSrcParams" ref="ga95f7e74ccb30f273b42b0cc08664ba55" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)" -->
+<a class="anchor" id="ga89c3174bf68727a9bc653d38989449ad"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setSrcParams" ref="ga89c3174bf68727a9bc653d38989449ad" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, uint32_t srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)" -->
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- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>srcAddr</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gab4be03dc87dc50975c5ea870944dcee4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setDestParams" ref="gab4be03dc87dc50975c5ea870944dcee4" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)" -->
+<a class="anchor" id="ga2a1ae983cef808737455677b7c2c0fb5"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setDestParams" ref="ga2a1ae983cef808737455677b7c2c0fb5" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, uint32_t destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)" -->
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>destAddr</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga212d4abb6f644084b3a29b856c0ef0ac"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setSrcIndex" ref="ga212d4abb6f644084b3a29b856c0ef0ac" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)" -->
+<a class="anchor" id="gaa4f81e82c3c44391074ff86444080fa4"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setSrcIndex" ref="gaa4f81e82c3c44391074ff86444080fa4" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, int32_t srcBIdx, int32_t srcCIdx)" -->
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<td class="paramkey"></td>
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- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">int </td>
+ <td class="paramtype">int32_t </td>
<td class="paramname"> <em>srcBIdx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">int </td>
+ <td class="paramtype">int32_t </td>
<td class="paramname"> <em>srcCIdx</em></td><td> </td>
</tr>
<tr>
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</div>
-<a class="anchor" id="ga4e7ec3c58f498bdbac7a507e0cba6221"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setDestIndex" ref="ga4e7ec3c58f498bdbac7a507e0cba6221" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)" -->
+<a class="anchor" id="ga743d009b49ca70a22c6f1fbec0683f82"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setDestIndex" ref="ga743d009b49ca70a22c6f1fbec0683f82" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, int32_t destBIdx, int32_t destCIdx)" -->
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- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">int </td>
+ <td class="paramtype">int32_t </td>
<td class="paramname"> <em>destBIdx</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">int </td>
+ <td class="paramtype">int32_t </td>
<td class="paramname"> <em>destCIdx</em></td><td> </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga8e54f2e2e016bc557ed3374eb46d62ee"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setTransferParams" ref="ga8e54f2e2e016bc557ed3374eb46d62ee" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, EDMA3_DRV_SyncType syncType)" -->
+<a class="anchor" id="ga44ba1ae06ac1a6aba94bd3f86f8e4f2e"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_setTransferParams" ref="ga44ba1ae06ac1a6aba94bd3f86f8e4f2e" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, uint32_t aCnt, uint32_t bCnt, uint32_t cCnt, uint32_t bCntReload, EDMA3_DRV_SyncType syncType)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>aCnt</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>bCnt</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>cCnt</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>bCntReload</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga5c80afa7645f1e492951c0419c21dbe6"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_enableTransfer" ref="ga5c80afa7645f1e492951c0419c21dbe6" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
+<a class="anchor" id="ga421bbec32ba1335296de937e35acc215"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getVersion" ref="ga421bbec32ba1335296de937e35acc215" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t EDMA3_DRV_getVersion </td>
+ <td>(</td>
+ <td class="paramtype">void </td>
+ <td class="paramname"></td>
+ <td> ) </td>
+ <td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Version information. </p>
+<p>The function is used to get the version information of the EDMA LLD.</p>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Version Information. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga43f6e71816afb2d823a73ee9f90b073b"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_getVersionStr" ref="ga43f6e71816afb2d823a73ee9f90b073b" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">const char* EDMA3_DRV_getVersionStr </td>
+ <td>(</td>
+ <td class="paramtype">void </td>
+ <td class="paramname"></td>
+ <td> ) </td>
+ <td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Version string querry. </p>
+<p>The function is used to get the version string for the EDMA LLD.</p>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Version Information. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga058da475e4b2e6db3f745611bd26fb27"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_enableTransfer" ref="ga058da475e4b2e6db3f745611bd26fb27" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_DRV_TrigMode trigMode)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gadb56f2a6d896c03a77f14c8fdf57a397"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_disableTransfer" ref="gadb56f2a6d896c03a77f14c8fdf57a397" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
+<a class="anchor" id="ga999444d7f079889ea8e1c825b8bdd05a"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_disableTransfer" ref="ga999444d7f079889ea8e1c825b8bdd05a" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_DRV_TrigMode trigMode)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga11070a2e9fb80e16fe96e8ad210e0b59"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_disableLogicalChannel" ref="ga11070a2e9fb80e16fe96e8ad210e0b59" args="(EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)" -->
+<a class="anchor" id="gaeb4d5d16d283e5dda906cdac67a44d18"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_disableLogicalChannel" ref="gaeb4d5d16d283e5dda906cdac67a44d18" args="(EDMA3_DRV_Handle hEdma, uint32_t lCh, EDMA3_DRV_TrigMode trigMode)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>lCh</em>, </td>
</tr>
<tr>
</div>
</div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:00 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html
index 1b9b73105ca7ee749766b408bb15b399883303ac..ba40bbc5d48af030774817d09f5645ac4d182f39 100755 (executable)
[<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n.html">EDMA3 Driver APIs</a>]</small>
</h1><table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Functions</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#gafc4627bdc96b1720a9d69c694688b20c">EDMA3_DRV_create</a> (unsigned int phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a> *gblCfgParams, const void *miscParam)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Create EDMA3 Driver Object. <a href="#gafc4627bdc96b1720a9d69c694688b20c"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#ga1eccca6dee0e5a05fa845c51df24e97d">EDMA3_DRV_delete</a> (unsigned int phyCtrllerInstId, const void *param)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Delete EDMA3 Driver Object. <a href="#ga1eccca6dee0e5a05fa845c51df24e97d"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Handle </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#gafd80c545b7e21f770743c5cb87fd6351">EDMA3_DRV_open</a> (unsigned int phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html">EDMA3_DRV_InitConfig</a> *initCfg, EDMA3_DRV_Result *errorCode)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Open EDMA3 Driver Instance. <a href="#gafd80c545b7e21f770743c5cb87fd6351"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#ga12f3a9c4fcbb34e65b83da89a0d7430f">EDMA3_DRV_create</a> (uint32_t phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a> *gblCfgParams, const void *miscParam)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Create EDMA3 Driver Object. <a href="#ga12f3a9c4fcbb34e65b83da89a0d7430f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#ga5fc8e8b7f228f6692eb69156b6d77b45">EDMA3_DRV_delete</a> (uint32_t phyCtrllerInstId, const void *param)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Delete EDMA3 Driver Object. <a href="#ga5fc8e8b7f228f6692eb69156b6d77b45"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Handle </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#ga9b623dfb3ab6733a7472a893155072cc">EDMA3_DRV_open</a> (uint32_t phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html">EDMA3_DRV_InitConfig</a> *initCfg, EDMA3_DRV_Result *errorCode)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Open EDMA3 Driver Instance. <a href="#ga9b623dfb3ab6733a7472a893155072cc"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#ga2e0ec2776dcf873bd49e7af3b9c85f0d">EDMA3_DRV_close</a> (EDMA3_DRV_Handle hEdma, const void *param)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Close the EDMA3 Driver Instance. <a href="#ga2e0ec2776dcf873bd49e7af3b9c85f0d"></a><br/></td></tr>
</table>
<hr/><h2>Function Documentation</h2>
-<a class="anchor" id="gafc4627bdc96b1720a9d69c694688b20c"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_create" ref="gafc4627bdc96b1720a9d69c694688b20c" args="(unsigned int phyCtrllerInstId, const EDMA3_DRV_GblConfigParams *gblCfgParams, const void *miscParam)" -->
+<a class="anchor" id="ga12f3a9c4fcbb34e65b83da89a0d7430f"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_create" ref="ga12f3a9c4fcbb34e65b83da89a0d7430f" args="(uint32_t phyCtrllerInstId, const EDMA3_DRV_GblConfigParams *gblCfgParams, const void *miscParam)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">EDMA3_DRV_Result EDMA3_DRV_create </td>
<td>(</td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>phyCtrllerInstId</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga1eccca6dee0e5a05fa845c51df24e97d"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_delete" ref="ga1eccca6dee0e5a05fa845c51df24e97d" args="(unsigned int phyCtrllerInstId, const void *param)" -->
+<a class="anchor" id="ga5fc8e8b7f228f6692eb69156b6d77b45"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_delete" ref="ga5fc8e8b7f228f6692eb69156b6d77b45" args="(uint32_t phyCtrllerInstId, const void *param)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">EDMA3_DRV_Result EDMA3_DRV_delete </td>
<td>(</td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>phyCtrllerInstId</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="gafd80c545b7e21f770743c5cb87fd6351"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_open" ref="gafd80c545b7e21f770743c5cb87fd6351" args="(unsigned int phyCtrllerInstId, const EDMA3_DRV_InitConfig *initCfg, EDMA3_DRV_Result *errorCode)" -->
+<a class="anchor" id="ga9b623dfb3ab6733a7472a893155072cc"></a><!-- doxytag: member="edma3_drv.h::EDMA3_DRV_open" ref="ga9b623dfb3ab6733a7472a893155072cc" args="(uint32_t phyCtrllerInstId, const EDMA3_DRV_InitConfig *initCfg, EDMA3_DRV_Result *errorCode)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">EDMA3_DRV_Handle EDMA3_DRV_open </td>
<td>(</td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>phyCtrllerInstId</em>, </td>
</tr>
<tr>
</div>
</div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:00 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l.html b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l.html
index 6d67c0074483693aabe907c23ef8c80deb54ada9..cc7878b46d38ce696684e224404b541cde15ff65 100755 (executable)
<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html">EDMA3 Driver Enums</a></td></tr>
</table>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:00 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html
index ebf948ceb9d99b3614d8915474b0ab722f81d43f..34ce44942919124fd2463cfc41e92547ec767e7b 100755 (executable)
[<a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l.html">EDMA3 Driver Symbols</a>]</small>
</h1><table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5931139feb03ef40cfeb2a45764913dc"></a><!-- doxytag: member="EDMA3_LLD_DRV_SYMBOL_DEFINE::EDMA3_LLD_DRV_VERSION_ID" ref="ga5931139feb03ef40cfeb2a45764913dc" args="" -->
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga5931139feb03ef40cfeb2a45764913dc">EDMA3_LLD_DRV_VERSION_ID</a> (0x020B0002)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">This is the EDMA3 LLD Version. Versions numbers are encoded in the following format: 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD). <br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabe61e2f36bdaa29751022b88df96af7c"></a><!-- doxytag: member="EDMA3_LLD_DRV_SYMBOL_DEFINE::EDMA3_LLD_DRV_VERSION_STR" ref="gabe61e2f36bdaa29751022b88df96af7c" args="" -->
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gabe61e2f36bdaa29751022b88df96af7c">EDMA3_LLD_DRV_VERSION_STR</a> "EDMA3 LLD Revision: 02.11.00.02"</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">This is the version string which describes the EDMA3 LLD along with the date and build information. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1c61cf487147fe68e224d1c123a8b9a0"></a><!-- doxytag: member="EDMA3_LLD_DRV_SYMBOL_DEFINE::EDMA3_DRV_E_BASE" ref="ga1c61cf487147fe68e224d1c123a8b9a0" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga1c61cf487147fe68e224d1c123a8b9a0">EDMA3_DRV_E_BASE</a> (-128)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 Driver Error Codes Base define. <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gac52b4731852ac8dac2f824fe0bdd153c">EDMA3_DRV_QDMA_CHANNEL_6</a> (EDMA3_DRV_QDMA_CHANNEL_0+6u)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gafc951e66232fc729344802c3abf6218b">EDMA3_DRV_QDMA_CHANNEL_7</a> (EDMA3_DRV_QDMA_CHANNEL_0+7u)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga2ca0c95ae69ae4cc71cc8137287a8fd1">EDMA3_DRV_CHANNEL_CLEAN</a> 0x0000u</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga85bad51ec992ce36ed7f28842b7d8219" title="Get the current status of the DMA/QDMA channel.">EDMA3_DRV_getChannelStatus()</a>. <a href="#ga2ca0c95ae69ae4cc71cc8137287a8fd1"></a><br/></td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga0241fe8f5788e4b4b217d650a383cf39" title="Get the current status of the DMA/QDMA channel.">EDMA3_DRV_getChannelStatus()</a>. <a href="#ga2ca0c95ae69ae4cc71cc8137287a8fd1"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga4b4982df7c3844ea394c9bb743fdf558">EDMA3_DRV_CHANNEL_EVENT_PENDING</a> 0x0001u</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#ga80c785afc213172fda74b14c59946480">EDMA3_DRV_CHANNEL_XFER_COMPLETE</a> 0x0002u</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___d_e_f_i_n_e.html#gab4cc61240f1e9a3f69c602c0ede9553b">EDMA3_DRV_CHANNEL_ERR</a> 0x0004u</td></tr>
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-<p>Used to specify any available DMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned. </p>
+<p>Used to specify any available DMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned. </p>
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-<p>Used to specify any available QDMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned. </p>
+<p>Used to specify any available QDMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned. </p>
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-<p>Used to specify any available TCC while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned. </p>
+<p>Used to specify any available TCC while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned. </p>
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-<p>Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. </p>
+<p>Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. </p>
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-<p>Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for Link channels. TCC code should also be specified and it will be used to populate the LINK field of the PaRAM Set. Without TCC code, the call will fail. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. </p>
+<p>Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>, for Link channels. TCC code should also be specified and it will be used to populate the LINK field of the PaRAM Set. Without TCC code, the call will fail. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. </p>
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<p>QDMA Channel defines. </p>
-<p>They should be used while requesting a specific QDMA channel in API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a> as the argument (*pLch). Please note that these defines should ONLY be used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a> and not in any other API to perform further operations. They are only provided to allow user allocate specific QDMA channels. QDMA Channel 0 </p>
+<p>They should be used while requesting a specific QDMA channel in API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a> as the argument (*pLch). Please note that these defines should ONLY be used in the API <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a> and not in any other API to perform further operations. They are only provided to allow user allocate specific QDMA channels. QDMA Channel 0 </p>
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-<p>Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga85bad51ec992ce36ed7f28842b7d8219" title="Get the current status of the DMA/QDMA channel.">EDMA3_DRV_getChannelStatus()</a>. </p>
+<p>Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga0241fe8f5788e4b4b217d650a383cf39" title="Get the current status of the DMA/QDMA channel.">EDMA3_DRV_getChannelStatus()</a>. </p>
<p>Channel is clean; no pending event, completion interrupt and event miss interrupt </p>
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-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:00 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html
index 07d7659ff4790c3d9d7181f93fa6e1e95efea478..cd232167b0c54abe305244e7961f115082f89acc 100755 (executable)
--- a/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html
+++ b/packages/ti/sdo/edma3/drv/docs/html/group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html
<div class="memdoc">
<p>PaRAM Set Entry type. </p>
-<p>Use this enum to set or get any of the 8 DWords(unsigned int) within a Parameter RAM set </p>
+<p>Use this enum to set or get any of the 8 DWords(uint32_t) within a Parameter RAM set </p>
<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"><em><a class="anchor" id="gga82b01ec2292a13ad48a5bfcc724dfac6a5cb3c2eda075435c8f48ef685a28971b"></a><!-- doxytag: member="EDMA3_DRV_PARAM_ENTRY_OPT" ref="gga82b01ec2292a13ad48a5bfcc724dfac6a5cb3c2eda075435c8f48ef685a28971b" args="" -->EDMA3_DRV_PARAM_ENTRY_OPT</em> </td><td>
<p>The OPT field (Offset Address 0x0 Bytes) </p>
<p>By default, PaRAM Sets will be cleared during allocation. Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources. </p>
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<tr><td valign="top"><em><a class="anchor" id="gga8577940463f7ca5a8977b2fb65fae19aa9ef62634a561e221c136e62de9694f48"></a><!-- doxytag: member="EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION" ref="gga8577940463f7ca5a8977b2fb65fae19aa9ef62634a561e221c136e62de9694f48" args="" -->EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION</em> </td><td>
-<p>To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation. For e.g., unsigned short isParamClearingDone; cmdArg = </p>
+<p>To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation. For e.g., uint16_t isParamClearingDone; cmdArg = </p>
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</dd>
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</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:00 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/index.hhk b/packages/ti/sdo/edma3/drv/docs/html/index.hhk
index 85f21eb69fefa53904fde48d1f1726146e48850f..7a9cd419333c48b1e55f11485b3e6e79d91b9640 100755 (executable)
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-<h1>EDMA3 Driver Documentation</h1><h3>02.11.00 </h3></div>
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+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___ch_bound_resources.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___ch_bound_resources.html
index 781d1f64205d0d6557c8285ee99c115e5a09a014..5b8de6d5b2ac7264ef021474036574b368e6c99a 100755 (executable)
<p><code>#include <edma3.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#a7e7e0d656a59da04f54465a45e078a03">paRAMId</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ae9afabd97444eada59c7a74a62a5e20d">tcc</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ab5ff9e35236c7dc75a8f19bf6aaf25d8">paRAMId</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ad4e5c0b7026a9ca02984b4a5d0ea552d">tcc</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___s_y_m_b_o_l___e_n_u_m.html#ga9a3d4fdcf4d2d089d4defebe3ef3880e">EDMA3_DRV_TrigMode</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#a37ce2e0c452db7c087997ed2d4003c8b">trigMode</a></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>EDMA3 Channel-Bound resources. </p>
-<p>Used to maintain information of the EDMA3 resources (specifically Parameter RAM set and TCC) and the mode of triggering transfer (Manual, HW event driven etc) bound to the particular channel within <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga301122cb5f7cca50ae824611bd816f8e" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. </p>
+<p>Used to maintain information of the EDMA3 resources (specifically Parameter RAM set and TCC) and the mode of triggering transfer (Manual, HW event driven etc) bound to the particular channel within <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaf972552f53ce9efe4db7bfe6db275c06" title="Request a DMA/QDMA/Link channel.">EDMA3_DRV_requestChannel()</a>. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a7e7e0d656a59da04f54465a45e078a03"></a><!-- doxytag: member="EDMA3_DRV_ChBoundResources::paRAMId" ref="a7e7e0d656a59da04f54465a45e078a03" args="" -->
+<a class="anchor" id="ab5ff9e35236c7dc75a8f19bf6aaf25d8"></a><!-- doxytag: member="EDMA3_DRV_ChBoundResources::paRAMId" ref="ab5ff9e35236c7dc75a8f19bf6aaf25d8" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">int <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#a7e7e0d656a59da04f54465a45e078a03">EDMA3_DRV_ChBoundResources::paRAMId</a></td>
+ <td class="memname">int32_t <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ab5ff9e35236c7dc75a8f19bf6aaf25d8">EDMA3_DRV_ChBoundResources::paRAMId</a></td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="ae9afabd97444eada59c7a74a62a5e20d"></a><!-- doxytag: member="EDMA3_DRV_ChBoundResources::tcc" ref="ae9afabd97444eada59c7a74a62a5e20d" args="" -->
+<a class="anchor" id="ad4e5c0b7026a9ca02984b4a5d0ea552d"></a><!-- doxytag: member="EDMA3_DRV_ChBoundResources::tcc" ref="ad4e5c0b7026a9ca02984b4a5d0ea552d" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ae9afabd97444eada59c7a74a62a5e20d">EDMA3_DRV_ChBoundResources::tcc</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___ch_bound_resources.html#ad4e5c0b7026a9ca02984b4a5d0ea552d">EDMA3_DRV_ChBoundResources::tcc</a></td>
</tr>
</table>
</div>
<li>edma3.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___chain_options.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___chain_options.html
index 8f53d16a89a90017e9d7c356bb18263f70b8f2b1..802f3b79c84fc4070379acfdd8ce6885cfc39c97 100755 (executable)
<li>edma3_drv.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___evt_que_priority.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___evt_que_priority.html
index 6a211702848a1119f0ed109e8902a46fd307f5f0..eb917c47718fdda938b0d2fcd03f92ab963f9523 100755 (executable)
<p><code>#include <edma3_drv.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a858e5c4051b793b974e6d268c328f2cf"></a><!-- doxytag: member="EDMA3_DRV_EvtQuePriority::evtQPri" ref="a858e5c4051b793b974e6d268c328f2cf" args="[EDMA3_MAX_EVT_QUE]" -->
-unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#a858e5c4051b793b974e6d268c328f2cf">evtQPri</a> [EDMA3_MAX_EVT_QUE]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a495ef97540d6c0984a2cfd2f4ba1cc7c"></a><!-- doxytag: member="EDMA3_DRV_EvtQuePriority::evtQPri" ref="a495ef97540d6c0984a2cfd2f4ba1cc7c" args="[EDMA3_MAX_EVT_QUE]" -->
+uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___evt_que_priority.html#a495ef97540d6c0984a2cfd2f4ba1cc7c">evtQPri</a> [EDMA3_MAX_EVT_QUE]</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Event Queue Priorities. <br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<li>edma3_drv.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___gbl_config_params.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___gbl_config_params.html
index 6124f99f6c8b29016cfc55f59e0b64b68847c6d4..5e172459665af822f739575735e52cafda43db3f 100755 (executable)
<p><code>#include <edma3_drv.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1d71e6ded1e1b3d3b14b20a11f896ce3">numDmaChannels</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a629d5fc8d59adc8644f5f7a2691b8230">numQdmaChannels</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a14c6249081e4225ea140904758377c53">numTccs</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9bf9fc29152fe9ddb63bc86683149fc9">numPaRAMSets</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ad27e2c83868656fa72ee70a64ac3a534">numEvtQueue</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a8285aab9b38d6369896777f08cb8febd">numTcs</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a30316db491c3d5f08182dc5bdde92463">numRegions</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a38ffcc4df844701e587fddc6625255b8">dmaChPaRAMMapExists</a></td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Channel mapping existence. <a href="#a38ffcc4df844701e587fddc6625255b8"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#afd883a70d5f8bb868e65a69aa44d0f8e">memProtectionExists</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a22c319a4bfbcec951d60f3d3e4485846">numDmaChannels</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1f18873723ea015ccd6da3729b013275">numQdmaChannels</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a2e50b4619dc11a6daf59e63e5d76918c">numTccs</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1add8cd6a0f8db4d829d8726a1d5af8e">numPaRAMSets</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9d5c0de0a3fba5504610072367ca8cc9">numEvtQueue</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a10e128f74fc3b16f0996009f521790f8">numTcs</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aa74fc54114ba0d92a25470526b226d4d">numRegions</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#acb8118d26c3680cdf2d06179264abb5d">dmaChPaRAMMapExists</a></td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Channel mapping existence. <a href="#acb8118d26c3680cdf2d06179264abb5d"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a464a49700f3add6848dff2d382f2fac5">memProtectionExists</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a5efff8708e94a49f71b055578549c97a">globalRegs</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a31847b941f3a290ef68992ea3683228f">tcRegs</a> [EDMA3_MAX_TC]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a08b4ad4be6b0cd9c6dd046dfe4f68c1e">xferCompleteInt</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a5f7297703c68fdb4d6e9b2a5d4750040">ccError</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a3fdbb69b709ecd01dc903ec47e59f5a8">tcError</a> [EDMA3_MAX_TC]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a8970e4cce82366cef852a60cc5dc1a5a">evtQPri</a> [EDMA3_MAX_EVT_QUE]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 TC priority setting. <a href="#a8970e4cce82366cef852a60cc5dc1a5a"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a60f00b339733c6126951a688072b53b3">evtQueueWaterMarkLvl</a> [EDMA3_MAX_EVT_QUE]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Event Queues Watermark Levels. <a href="#a60f00b339733c6126951a688072b53b3"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aa217c4ed918c9d5d695ee19ced91ef00">tcDefaultBurstSize</a> [EDMA3_MAX_TC]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Default Burst Size (DBS) of TCs. <a href="#aa217c4ed918c9d5d695ee19ced91ef00"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aef6b47382a74f4aabfa050f6213512d4">dmaChannelPaRAMMap</a> [EDMA3_MAX_DMA_CH]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to PaRAM Sets. <a href="#aef6b47382a74f4aabfa050f6213512d4"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a09dc86e6c4cbda84547c3033532e1b98">dmaChannelTccMap</a> [EDMA3_MAX_DMA_CH]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to TCCs. <a href="#a09dc86e6c4cbda84547c3033532e1b98"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ac205feb9fd0a3575627dbec2f95d176c">dmaChannelHwEvtMap</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to Hardware Events. <a href="#ac205feb9fd0a3575627dbec2f95d176c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a746b0e3fc21383aabf89f6d9dd428969">xferCompleteInt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a682330bc86c34485de0cd00bafd9f493">ccError</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ae28ee7379bd413340012e9f19665c8c4">tcError</a> [EDMA3_MAX_TC]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a698cb3fedc00b1ce9cac888ee877a45c">evtQPri</a> [EDMA3_MAX_EVT_QUE]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 TC priority setting. <a href="#a698cb3fedc00b1ce9cac888ee877a45c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a169774e25daf2f2380126c71ef6f10d8">evtQueueWaterMarkLvl</a> [EDMA3_MAX_EVT_QUE]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Event Queues Watermark Levels. <a href="#a169774e25daf2f2380126c71ef6f10d8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a0557294e22cf97d82975a8b23e41f040">tcDefaultBurstSize</a> [EDMA3_MAX_TC]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Default Burst Size (DBS) of TCs. <a href="#a0557294e22cf97d82975a8b23e41f040"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#af1e11302ce81f398d950a7629d6de4a9">dmaChannelPaRAMMap</a> [EDMA3_MAX_DMA_CH]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to PaRAM Sets. <a href="#af1e11302ce81f398d950a7629d6de4a9"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9ef536e4867fc871dd9971801e0dfc28">dmaChannelTccMap</a> [EDMA3_MAX_DMA_CH]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to TCCs. <a href="#a9ef536e4867fc871dd9971801e0dfc28"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aabc00a71e6a8b9bf895306f680d273ff">dmaChannelHwEvtMap</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to Hardware Events. <a href="#aabc00a71e6a8b9bf895306f680d273ff"></a><br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. </p>
<p>This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresses of CC global registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 Driver Object, using API EDMA3_DRV_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a1d71e6ded1e1b3d3b14b20a11f896ce3"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numDmaChannels" ref="a1d71e6ded1e1b3d3b14b20a11f896ce3" args="" -->
+<a class="anchor" id="a22c319a4bfbcec951d60f3d3e4485846"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numDmaChannels" ref="a22c319a4bfbcec951d60f3d3e4485846" args="" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1d71e6ded1e1b3d3b14b20a11f896ce3">EDMA3_DRV_GblConfigParams::numDmaChannels</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a22c319a4bfbcec951d60f3d3e4485846">EDMA3_DRV_GblConfigParams::numDmaChannels</a></td>
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+<a class="anchor" id="a1f18873723ea015ccd6da3729b013275"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numQdmaChannels" ref="a1f18873723ea015ccd6da3729b013275" args="" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a629d5fc8d59adc8644f5f7a2691b8230">EDMA3_DRV_GblConfigParams::numQdmaChannels</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1f18873723ea015ccd6da3729b013275">EDMA3_DRV_GblConfigParams::numQdmaChannels</a></td>
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-<a class="anchor" id="a14c6249081e4225ea140904758377c53"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numTccs" ref="a14c6249081e4225ea140904758377c53" args="" -->
+<a class="anchor" id="a2e50b4619dc11a6daf59e63e5d76918c"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numTccs" ref="a2e50b4619dc11a6daf59e63e5d76918c" args="" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a14c6249081e4225ea140904758377c53">EDMA3_DRV_GblConfigParams::numTccs</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a2e50b4619dc11a6daf59e63e5d76918c">EDMA3_DRV_GblConfigParams::numTccs</a></td>
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-<a class="anchor" id="a9bf9fc29152fe9ddb63bc86683149fc9"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::numPaRAMSets" ref="a9bf9fc29152fe9ddb63bc86683149fc9" args="" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9bf9fc29152fe9ddb63bc86683149fc9">EDMA3_DRV_GblConfigParams::numPaRAMSets</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a1add8cd6a0f8db4d829d8726a1d5af8e">EDMA3_DRV_GblConfigParams::numPaRAMSets</a></td>
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ad27e2c83868656fa72ee70a64ac3a534">EDMA3_DRV_GblConfigParams::numEvtQueue</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a9d5c0de0a3fba5504610072367ca8cc9">EDMA3_DRV_GblConfigParams::numEvtQueue</a></td>
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</div>
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+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a10e128f74fc3b16f0996009f521790f8">EDMA3_DRV_GblConfigParams::numTcs</a></td>
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+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aa74fc54114ba0d92a25470526b226d4d">EDMA3_DRV_GblConfigParams::numRegions</a></td>
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+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#acb8118d26c3680cdf2d06179264abb5d">EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists</a></td>
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+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a464a49700f3add6848dff2d382f2fac5">EDMA3_DRV_GblConfigParams::memProtectionExists</a></td>
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+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a746b0e3fc21383aabf89f6d9dd428969">EDMA3_DRV_GblConfigParams::xferCompleteInt</a></td>
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a5f7297703c68fdb4d6e9b2a5d4750040">EDMA3_DRV_GblConfigParams::ccError</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#a682330bc86c34485de0cd00bafd9f493">EDMA3_DRV_GblConfigParams::ccError</a></td>
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</div>
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</div>
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</div>
-<a class="anchor" id="ac205feb9fd0a3575627dbec2f95d176c"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap" ref="ac205feb9fd0a3575627dbec2f95d176c" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
+<a class="anchor" id="aabc00a71e6a8b9bf895306f680d273ff"></a><!-- doxytag: member="EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap" ref="aabc00a71e6a8b9bf895306f680d273ff" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#ac205feb9fd0a3575627dbec2f95d176c">EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html#aabc00a71e6a8b9bf895306f680d273ff">EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
</tr>
</table>
</div>
<li>edma3_drv.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html
index 4d3ab1cde8df015f2e45f9ab6675d8979cbf3437..c403f054e300f2347c97d139f322e86439bf5f4c 100755 (executable)
--- a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html
+++ b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html
<p><code>#include <edma3_drv.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#a81951f5e7e005e5916aed68b4996181c">dmaMapXbarToChan</a> [EDMA3_DRV_MAX_XBAR_EVENTS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to Hardware Events. <a href="#a81951f5e7e005e5916aed68b4996181c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#a64c7060f3d51a5a690c01de14723fa0c">dmaMapXbarToChan</a> [EDMA3_DRV_MAX_XBAR_EVENTS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to Hardware Events. <a href="#a64c7060f3d51a5a690c01de14723fa0c"></a><br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. </p>
<p>This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. This configuraion structure provides the details of the mapping of cross bar events to available channels. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 Driver Object, using API EDMA3_DRV_initXbarEventMap. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, incase it is available. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a81951f5e7e005e5916aed68b4996181c"></a><!-- doxytag: member="EDMA3_DRV_GblXbarToChanConfigParams::dmaMapXbarToChan" ref="a81951f5e7e005e5916aed68b4996181c" args="[EDMA3_DRV_MAX_XBAR_EVENTS]" -->
+<a class="anchor" id="a64c7060f3d51a5a690c01de14723fa0c"></a><!-- doxytag: member="EDMA3_DRV_GblXbarToChanConfigParams::dmaMapXbarToChan" ref="a64c7060f3d51a5a690c01de14723fa0c" args="[EDMA3_DRV_MAX_XBAR_EVENTS]" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">int <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#a81951f5e7e005e5916aed68b4996181c">EDMA3_DRV_GblXbarToChanConfigParams::dmaMapXbarToChan</a>[EDMA3_DRV_MAX_XBAR_EVENTS]</td>
+ <td class="memname">int32_t <a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html#a64c7060f3d51a5a690c01de14723fa0c">EDMA3_DRV_GblXbarToChanConfigParams::dmaMapXbarToChan</a>[EDMA3_DRV_MAX_XBAR_EVENTS]</td>
</tr>
</table>
</div>
<li>edma3_drv.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___init_config.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___init_config.html
index 2c647ad2fcb0621a9a984490462712bab8591726..4e3d71b7eeddaf097e6c1f5717c24c3fc3f87db5 100755 (executable)
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_RegionId </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a203b65f7e1176d9c5a7736411ba97df8">regionId</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#aa03b188471e9dc09af09a3b9096f7712">isMaster</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a91d915bcb63bcf6a9352298c4431cb5b">isMaster</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html">EDMA3_DRV_InstanceInitConfig</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a0311bf1e9522f4b7c3543bd8b76f6a88">drvInstInitConfig</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a50b80ecf78fdb0b172719f92cce22d02">drvSemHandle</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_GblErrCallback </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a416b12b38ea85487ca86df5d83754cc2">gblerrCb</a></td></tr>
</div>
</div>
-<a class="anchor" id="aa03b188471e9dc09af09a3b9096f7712"></a><!-- doxytag: member="EDMA3_DRV_InitConfig::isMaster" ref="aa03b188471e9dc09af09a3b9096f7712" args="" -->
+<a class="anchor" id="a91d915bcb63bcf6a9352298c4431cb5b"></a><!-- doxytag: member="EDMA3_DRV_InitConfig::isMaster" ref="a91d915bcb63bcf6a9352298c4431cb5b" args="" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#aa03b188471e9dc09af09a3b9096f7712">EDMA3_DRV_InitConfig::isMaster</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___init_config.html#a91d915bcb63bcf6a9352298c4431cb5b">EDMA3_DRV_InitConfig::isMaster</a></td>
</tr>
</table>
</div>
<li>edma3_drv.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___instance.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___instance.html
index 26e39e8d407e8f768ef9e5234e1b3348a391b61e..bac0cae8100bd1c36f7e71c17f9327487df1d178 100755 (executable)
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_RegionId </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a1eb007f153b58999588f5649ecd2143f">regionId</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a5e27d856f44f731c3182c1a854a7acb6">isMaster</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a910f6482cc3e7dbcc72f1e6bd069b65a">isMaster</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html">EDMA3_DRV_InstanceInitConfig</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ad499f6a143851371949c908713c9e640">drvInstInitConfig</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a50d92b6f9d98acc19589f3585d17023f">drvSemHandle</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_GblErrCallbackParams </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a8db1897e81a58f66102840e992056e16">gblerrCbParams</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_CCRL_ShadowRegs * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ad92603735455f8173b6e65467b78694a">shadowRegs</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_e_d_m_a3___d_r_v___object.html">EDMA3_DRV_Object</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#acc5b518c2a22a43289ca39438133a30b">pDrvObjectHandle</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Handle </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afc40e1cb787bbdae7afee7c6ea14109e">resMgrInstance</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afac1f63dcd293985df3777abab3b2f9a">mapXbarToChan</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ab697a86b3efb21d2ddbbafa2519d21b1">configScrMapXbarToEvt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaba09a1e3f0dbc70cff309a0030776168">EDMA3_DRV_mapXbarEvtToChan</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afac1f63dcd293985df3777abab3b2f9a">mapXbarToChan</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga44bf9e6ccf89645f0fcd1c345d8b5fde">EDMA3_DRV_xbarConfigScr</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ab697a86b3efb21d2ddbbafa2519d21b1">configScrMapXbarToEvt</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_xbar_to_chan_config_params.html">EDMA3_DRV_GblXbarToChanConfigParams</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a012dd7bf9aa72726cbe3e5553f778124">drvXbarToEvtMapConfig</a></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
</div>
</div>
-<a class="anchor" id="a5e27d856f44f731c3182c1a854a7acb6"></a><!-- doxytag: member="EDMA3_DRV_Instance::isMaster" ref="a5e27d856f44f731c3182c1a854a7acb6" args="" -->
+<a class="anchor" id="a910f6482cc3e7dbcc72f1e6bd069b65a"></a><!-- doxytag: member="EDMA3_DRV_Instance::isMaster" ref="a910f6482cc3e7dbcc72f1e6bd069b65a" args="" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a5e27d856f44f731c3182c1a854a7acb6">EDMA3_DRV_Instance::isMaster</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#a910f6482cc3e7dbcc72f1e6bd069b65a">EDMA3_DRV_Instance::isMaster</a></td>
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</table>
</div>
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae7867a62f61919df85b323ce981163e4">EDMA3_DRV_mapXbarEvtToChan</a> <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afac1f63dcd293985df3777abab3b2f9a">EDMA3_DRV_Instance::mapXbarToChan</a></td>
+ <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaba09a1e3f0dbc70cff309a0030776168">EDMA3_DRV_mapXbarEvtToChan</a> <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#afac1f63dcd293985df3777abab3b2f9a">EDMA3_DRV_Instance::mapXbarToChan</a></td>
</tr>
</table>
</div>
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga02168cc5612b65b34812ce52df7154a3">EDMA3_DRV_xbarConfigScr</a> <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ab697a86b3efb21d2ddbbafa2519d21b1">EDMA3_DRV_Instance::configScrMapXbarToEvt</a></td>
+ <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga44bf9e6ccf89645f0fcd1c345d8b5fde">EDMA3_DRV_xbarConfigScr</a> <a class="el" href="struct_e_d_m_a3___d_r_v___instance.html#ab697a86b3efb21d2ddbbafa2519d21b1">EDMA3_DRV_Instance::configScrMapXbarToEvt</a></td>
</tr>
</table>
</div>
<li>edma3.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___instance_init_config.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___instance_init_config.html
index 8025544854a02f6a6d74b18c6068a7640c66c0e0..f008fe1770c30fb3e830f214640e27e7a51442d7 100755 (executable)
<p><code>#include <edma3_drv.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ab14f2d879a9d96a3eb41756e134706c8">ownPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#aa718b355bf902648c421aef695836fa4">ownDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a38f397851f049cdebe32340cd2c651c0">ownQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad90d5a8af55128a3157afb45a4f68d56">ownTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a81d8b8d85f09f042658db196e208794b">resvdPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved PaRAM Sets. <a href="#a81d8b8d85f09f042658db196e208794b"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a30630e869042596c4ed487a09bea35c3">resvdDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved DMA channels. <a href="#a30630e869042596c4ed487a09bea35c3"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad6707e2582dc13b7ea4d3a854834406e">resvdQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved QDMA channels. <a href="#ad6707e2582dc13b7ea4d3a854834406e"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a175d4b970b6bf34c05700f4105bae5a6">resvdTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved TCCs. <a href="#a175d4b970b6bf34c05700f4105bae5a6"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a7fdf14b23595c3e97e41500749642b75">ownPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a1dc3d39936118d391b4a1b95ea0f65e1">ownDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a795ef36bf2e328e6634199a5dbb9c89e">ownQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#aa8d98245fd41512a85889e477fba5f14">ownTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a8f9bf5f5fabc18ad810ac1da35340944">resvdPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved PaRAM Sets. <a href="#a8f9bf5f5fabc18ad810ac1da35340944"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a6166eb480efe999107365112e91791b7">resvdDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved DMA channels. <a href="#a6166eb480efe999107365112e91791b7"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a743c6c78af10dfab4fc004ed3eebabb2">resvdQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved QDMA channels. <a href="#a743c6c78af10dfab4fc004ed3eebabb2"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a3b23079b2265a753f410a1ca4c01b3aa">resvdTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved TCCs. <a href="#a3b23079b2265a753f410a1ca4c01b3aa"></a><br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. </p>
<p>Same logic applies for QDMA channels and TCCs.</p>
<p>For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 Driver automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="ab14f2d879a9d96a3eb41756e134706c8"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::ownPaRAMSets" ref="ab14f2d879a9d96a3eb41756e134706c8" args="[EDMA3_MAX_PARAM_DWRDS]" -->
+<a class="anchor" id="a7fdf14b23595c3e97e41500749642b75"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::ownPaRAMSets" ref="a7fdf14b23595c3e97e41500749642b75" args="[EDMA3_MAX_PARAM_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ab14f2d879a9d96a3eb41756e134706c8">EDMA3_DRV_InstanceInitConfig::ownPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a7fdf14b23595c3e97e41500749642b75">EDMA3_DRV_InstanceInitConfig::ownPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="aa718b355bf902648c421aef695836fa4"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::ownDmaChannels" ref="aa718b355bf902648c421aef695836fa4" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
+<a class="anchor" id="a1dc3d39936118d391b4a1b95ea0f65e1"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::ownDmaChannels" ref="a1dc3d39936118d391b4a1b95ea0f65e1" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#aa718b355bf902648c421aef695836fa4">EDMA3_DRV_InstanceInitConfig::ownDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a1dc3d39936118d391b4a1b95ea0f65e1">EDMA3_DRV_InstanceInitConfig::ownDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="a38f397851f049cdebe32340cd2c651c0"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::ownQdmaChannels" ref="a38f397851f049cdebe32340cd2c651c0" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
+<a class="anchor" id="a795ef36bf2e328e6634199a5dbb9c89e"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::ownQdmaChannels" ref="a795ef36bf2e328e6634199a5dbb9c89e" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a38f397851f049cdebe32340cd2c651c0">EDMA3_DRV_InstanceInitConfig::ownQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a795ef36bf2e328e6634199a5dbb9c89e">EDMA3_DRV_InstanceInitConfig::ownQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="ad90d5a8af55128a3157afb45a4f68d56"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::ownTccs" ref="ad90d5a8af55128a3157afb45a4f68d56" args="[EDMA3_MAX_TCC_DWRDS]" -->
+<a class="anchor" id="aa8d98245fd41512a85889e477fba5f14"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::ownTccs" ref="aa8d98245fd41512a85889e477fba5f14" args="[EDMA3_MAX_TCC_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad90d5a8af55128a3157afb45a4f68d56">EDMA3_DRV_InstanceInitConfig::ownTccs</a>[EDMA3_MAX_TCC_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#aa8d98245fd41512a85889e477fba5f14">EDMA3_DRV_InstanceInitConfig::ownTccs</a>[EDMA3_MAX_TCC_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="a81d8b8d85f09f042658db196e208794b"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::resvdPaRAMSets" ref="a81d8b8d85f09f042658db196e208794b" args="[EDMA3_MAX_PARAM_DWRDS]" -->
+<a class="anchor" id="a8f9bf5f5fabc18ad810ac1da35340944"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::resvdPaRAMSets" ref="a8f9bf5f5fabc18ad810ac1da35340944" args="[EDMA3_MAX_PARAM_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a81d8b8d85f09f042658db196e208794b">EDMA3_DRV_InstanceInitConfig::resvdPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a8f9bf5f5fabc18ad810ac1da35340944">EDMA3_DRV_InstanceInitConfig::resvdPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="a30630e869042596c4ed487a09bea35c3"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::resvdDmaChannels" ref="a30630e869042596c4ed487a09bea35c3" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
+<a class="anchor" id="a6166eb480efe999107365112e91791b7"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::resvdDmaChannels" ref="a6166eb480efe999107365112e91791b7" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a30630e869042596c4ed487a09bea35c3">EDMA3_DRV_InstanceInitConfig::resvdDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a6166eb480efe999107365112e91791b7">EDMA3_DRV_InstanceInitConfig::resvdDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="ad6707e2582dc13b7ea4d3a854834406e"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::resvdQdmaChannels" ref="ad6707e2582dc13b7ea4d3a854834406e" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
+<a class="anchor" id="a743c6c78af10dfab4fc004ed3eebabb2"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::resvdQdmaChannels" ref="a743c6c78af10dfab4fc004ed3eebabb2" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#ad6707e2582dc13b7ea4d3a854834406e">EDMA3_DRV_InstanceInitConfig::resvdQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a743c6c78af10dfab4fc004ed3eebabb2">EDMA3_DRV_InstanceInitConfig::resvdQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="a175d4b970b6bf34c05700f4105bae5a6"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::resvdTccs" ref="a175d4b970b6bf34c05700f4105bae5a6" args="[EDMA3_MAX_TCC_DWRDS]" -->
+<a class="anchor" id="a3b23079b2265a753f410a1ca4c01b3aa"></a><!-- doxytag: member="EDMA3_DRV_InstanceInitConfig::resvdTccs" ref="a3b23079b2265a753f410a1ca4c01b3aa" args="[EDMA3_MAX_TCC_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a175d4b970b6bf34c05700f4105bae5a6">EDMA3_DRV_InstanceInitConfig::resvdTccs</a>[EDMA3_MAX_TCC_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___instance_init_config.html#a3b23079b2265a753f410a1ca4c01b3aa">EDMA3_DRV_InstanceInitConfig::resvdTccs</a>[EDMA3_MAX_TCC_DWRDS]</td>
</tr>
</table>
</div>
<li>edma3_drv.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___misc_param.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___misc_param.html
index e9455e3ad6db46f7474b93b0973ebbbfbafaabfe..a504b0103e542171465dfb207f689ddba17de2cb 100755 (executable)
<p><code>#include <edma3_drv.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a812d8f331ad701c3927e28ce4c86d8c0">isSlave</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a9359f6ade97d2f3d910097fafd73da0a">param</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#af8f6c01edfaad57574c8ec1601d44ab6">isSlave</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#afb7253b18e2a32e513f47c3566c11567">param</a></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Used to specify the miscellaneous options during EDMA3 Driver Initialization. </p>
<p>This configuration structure is used to specify some misc options while creating the Driver object. New options may also be added into this structure in future. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a812d8f331ad701c3927e28ce4c86d8c0"></a><!-- doxytag: member="EDMA3_DRV_MiscParam::isSlave" ref="a812d8f331ad701c3927e28ce4c86d8c0" args="" -->
+<a class="anchor" id="af8f6c01edfaad57574c8ec1601d44ab6"></a><!-- doxytag: member="EDMA3_DRV_MiscParam::isSlave" ref="af8f6c01edfaad57574c8ec1601d44ab6" args="" -->
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- <td class="memname">unsigned short <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a812d8f331ad701c3927e28ce4c86d8c0">EDMA3_DRV_MiscParam::isSlave</a></td>
+ <td class="memname">uint16_t <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#af8f6c01edfaad57574c8ec1601d44ab6">EDMA3_DRV_MiscParam::isSlave</a></td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="a9359f6ade97d2f3d910097fafd73da0a"></a><!-- doxytag: member="EDMA3_DRV_MiscParam::param" ref="a9359f6ade97d2f3d910097fafd73da0a" args="" -->
+<a class="anchor" id="afb7253b18e2a32e513f47c3566c11567"></a><!-- doxytag: member="EDMA3_DRV_MiscParam::param" ref="afb7253b18e2a32e513f47c3566c11567" args="" -->
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- <td class="memname">unsigned short <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#a9359f6ade97d2f3d910097fafd73da0a">EDMA3_DRV_MiscParam::param</a></td>
+ <td class="memname">uint16_t <a class="el" href="struct_e_d_m_a3___d_r_v___misc_param.html#afb7253b18e2a32e513f47c3566c11567">EDMA3_DRV_MiscParam::param</a></td>
</tr>
</table>
</div>
<li>edma3_drv.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:01 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___object.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___object.html
index c0be330ca7853b5c834d7f8bf1739ce8a6e1c2b6..c5f825513cf855e3c60f5e3fa882ed906e0b4ca7 100755 (executable)
<p><code>#include <edma3.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___object.html#ae0923a080e0da9d1b23cd9cf655775aa">phyCtrllerInstId</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___object.html#a278048cc0afab60a90690750986a60b1">phyCtrllerInstId</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_DRV_ObjState </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___object.html#adfc26946970b87cc67579ec54c73a221">state</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___object.html#aa02b8fca5781ab737d267b0b46598b80">numOpens</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___object.html#ab3107c1484a016f0766eb11c55e70a16">numOpens</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_e_d_m_a3___d_r_v___gbl_config_params.html">EDMA3_DRV_GblConfigParams</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___object.html#a42669ba83291891a8e233c49aff390c3">gblCfgParams</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. <a href="#a42669ba83291891a8e233c49aff390c3"></a><br/></td></tr>
</table>
<p>EDMA3 Driver Object (HW Specific) Maintenance structure. </p>
<p>Used to maintain information of the EDMA3 HW configuration thoughout the lifetime of the EDMA3 Driver Object, one for each EDMA3 hardware instance. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="ae0923a080e0da9d1b23cd9cf655775aa"></a><!-- doxytag: member="EDMA3_DRV_Object::phyCtrllerInstId" ref="ae0923a080e0da9d1b23cd9cf655775aa" args="" -->
+<a class="anchor" id="a278048cc0afab60a90690750986a60b1"></a><!-- doxytag: member="EDMA3_DRV_Object::phyCtrllerInstId" ref="a278048cc0afab60a90690750986a60b1" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#ae0923a080e0da9d1b23cd9cf655775aa">EDMA3_DRV_Object::phyCtrllerInstId</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#a278048cc0afab60a90690750986a60b1">EDMA3_DRV_Object::phyCtrllerInstId</a></td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="aa02b8fca5781ab737d267b0b46598b80"></a><!-- doxytag: member="EDMA3_DRV_Object::numOpens" ref="aa02b8fca5781ab737d267b0b46598b80" args="" -->
+<a class="anchor" id="ab3107c1484a016f0766eb11c55e70a16"></a><!-- doxytag: member="EDMA3_DRV_Object::numOpens" ref="ab3107c1484a016f0766eb11c55e70a16" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#aa02b8fca5781ab737d267b0b46598b80">EDMA3_DRV_Object::numOpens</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___object.html#ab3107c1484a016f0766eb11c55e70a16">EDMA3_DRV_Object::numOpens</a></td>
</tr>
</table>
</div>
<div class="memdoc">
<p>Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. </p>
-<p>This configuration info can be provided by the user at run-time, while calling <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#gafc4627bdc96b1720a9d69c694688b20c" title="Create EDMA3 Driver Object.">EDMA3_DRV_create()</a>. If not provided at run-time, this info will be taken from the config file edma3Cfg.c. </p>
+<p>This configuration info can be provided by the user at run-time, while calling <a class="el" href="group___e_d_m_a3___l_l_d___d_r_v___f_u_n_c_t_i_o_n___i_n_i_t.html#ga12f3a9c4fcbb34e65b83da89a0d7430f" title="Create EDMA3 Driver Object.">EDMA3_DRV_create()</a>. If not provided at run-time, this info will be taken from the config file edma3Cfg.c. </p>
</div>
</div>
<li>edma3.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:02 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html
index 01b698801f4534d86f72806fb06f66584ac901a6..74949289f389ff138d2a8cc0039b67efae91d35f 100755 (executable)
<p><code>#include <edma3_drv.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a32d762dd945673da57fc34f633d078a0">opt</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8ac1ab47f33fd6834ed4b378a33faf13"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::srcAddr" ref="a8ac1ab47f33fd6834ed4b378a33faf13" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a8ac1ab47f33fd6834ed4b378a33faf13">srcAddr</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aea6724d515b3182ec9edb3c19f99d8a5">opt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3294f54a691bc767513c8b99b21eecaa"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::srcAddr" ref="a3294f54a691bc767513c8b99b21eecaa" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a3294f54a691bc767513c8b99b21eecaa">srcAddr</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa8b1127bdb0fa8d104a2bdab4c629620"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::aCnt" ref="aa8b1127bdb0fa8d104a2bdab4c629620" args="" -->
-volatile unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aa8b1127bdb0fa8d104a2bdab4c629620">aCnt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af77830b02d859677689f1d0780fea145"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::aCnt" ref="af77830b02d859677689f1d0780fea145" args="" -->
+volatile uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#af77830b02d859677689f1d0780fea145">aCnt</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Number of bytes in each Array (ACNT). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0311c99486c3c8c3ae20751289256ac0"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::bCnt" ref="a0311c99486c3c8c3ae20751289256ac0" args="" -->
-volatile unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0311c99486c3c8c3ae20751289256ac0">bCnt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8da5f5386a5236c92016c13a4d7fa46c"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::bCnt" ref="a8da5f5386a5236c92016c13a4d7fa46c" args="" -->
+volatile uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a8da5f5386a5236c92016c13a4d7fa46c">bCnt</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Number of Arrays in each Frame (BCNT). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6e8b9889c9d5d9c60961dd1e40330b40"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::destAddr" ref="a6e8b9889c9d5d9c60961dd1e40330b40" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a6e8b9889c9d5d9c60961dd1e40330b40">destAddr</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa5b16d579c2fe6c8a7874a24cb6e4043"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::destAddr" ref="aa5b16d579c2fe6c8a7874a24cb6e4043" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aa5b16d579c2fe6c8a7874a24cb6e4043">destAddr</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a47d95d95fa2d572116180de42eae6d33"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::srcBIdx" ref="a47d95d95fa2d572116180de42eae6d33" args="" -->
-volatile short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a47d95d95fa2d572116180de42eae6d33">srcBIdx</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3faf892035063076228bc8cd2dfa584e"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::srcBIdx" ref="a3faf892035063076228bc8cd2dfa584e" args="" -->
+volatile int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a3faf892035063076228bc8cd2dfa584e">srcBIdx</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a20c505ef21d1c7f1f3c4a7309488ed9c"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::destBIdx" ref="a20c505ef21d1c7f1f3c4a7309488ed9c" args="" -->
-volatile short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a20c505ef21d1c7f1f3c4a7309488ed9c">destBIdx</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af3a2c005386af4d0fa9e5c32eb46fee2"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::destBIdx" ref="af3a2c005386af4d0fa9e5c32eb46fee2" args="" -->
+volatile int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#af3a2c005386af4d0fa9e5c32eb46fee2">destBIdx</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9a90c589c5d20e363b8cd9a64732009e"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::linkAddr" ref="a9a90c589c5d20e363b8cd9a64732009e" args="" -->
-volatile unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a9a90c589c5d20e363b8cd9a64732009e">linkAddr</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0cd745b505f157c103635a09387e1f65"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::linkAddr" ref="a0cd745b505f157c103635a09387e1f65" args="" -->
+volatile uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0cd745b505f157c103635a09387e1f65">linkAddr</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a877333b51a48685e71608f3d65856049"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::bCntReload" ref="a877333b51a48685e71608f3d65856049" args="" -->
-volatile unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a877333b51a48685e71608f3d65856049">bCntReload</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aed0fd5b798844697018fe3e18844c36c"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::bCntReload" ref="aed0fd5b798844697018fe3e18844c36c" args="" -->
+volatile uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aed0fd5b798844697018fe3e18844c36c">bCntReload</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acceb3dbc415f63ee4974c9f3a11a11c6"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::srcCIdx" ref="acceb3dbc415f63ee4974c9f3a11a11c6" args="" -->
-volatile short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#acceb3dbc415f63ee4974c9f3a11a11c6">srcCIdx</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a23690d90719731ffb82e84e9a3aa55ef"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::srcCIdx" ref="a23690d90719731ffb82e84e9a3aa55ef" args="" -->
+volatile int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a23690d90719731ffb82e84e9a3aa55ef">srcCIdx</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Index between consecutive frames of a Source Block (SRCCIDX). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0a4d37d7b9a0025f7285d3d788635761"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::destCIdx" ref="a0a4d37d7b9a0025f7285d3d788635761" args="" -->
-volatile short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a0a4d37d7b9a0025f7285d3d788635761">destCIdx</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a592299a486cafc80e554b69ccc2580bf"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::destCIdx" ref="a592299a486cafc80e554b69ccc2580bf" args="" -->
+volatile int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a592299a486cafc80e554b69ccc2580bf">destCIdx</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Index between consecutive frames of a Dest Block (DSTCIDX). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a675509d3b2db629f66cf296ef0498c7d"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::cCnt" ref="a675509d3b2db629f66cf296ef0498c7d" args="" -->
-volatile unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a675509d3b2db629f66cf296ef0498c7d">cCnt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1b5490a1cdd8ee7fe5ec20f1df8bb5d2"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::cCnt" ref="a1b5490a1cdd8ee7fe5ec20f1df8bb5d2" args="" -->
+volatile uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a1b5490a1cdd8ee7fe5ec20f1df8bb5d2">cCnt</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Number of Frames in a block (CCNT). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6285ab933f20d29b5d6892b895582e24"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::reserved" ref="a6285ab933f20d29b5d6892b895582e24" args="" -->
-volatile short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a6285ab933f20d29b5d6892b895582e24">reserved</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae4d8210fa6048328ff6e6f9bcb4495dc"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::reserved" ref="ae4d8210fa6048328ff6e6f9bcb4495dc" args="" -->
+volatile int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#ae4d8210fa6048328ff6e6f9bcb4495dc">reserved</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>EDMA3 Parameter RAM Set in User Configurable format. </p>
<p>This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual fields </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a32d762dd945673da57fc34f633d078a0"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::opt" ref="a32d762dd945673da57fc34f633d078a0" args="" -->
+<a class="anchor" id="aea6724d515b3182ec9edb3c19f99d8a5"></a><!-- doxytag: member="EDMA3_DRV_PaRAMRegs::opt" ref="aea6724d515b3182ec9edb3c19f99d8a5" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">volatile unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#a32d762dd945673da57fc34f633d078a0">EDMA3_DRV_PaRAMRegs::opt</a></td>
+ <td class="memname">volatile uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___pa_r_a_m_regs.html#aea6724d515b3182ec9edb3c19f99d8a5">EDMA3_DRV_PaRAMRegs::opt</a></td>
</tr>
</table>
</div>
<li>edma3_drv.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:02 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___paramentry_regs.html b/packages/ti/sdo/edma3/drv/docs/html/struct_e_d_m_a3___d_r_v___paramentry_regs.html
index 855ab674e82c62bd6cd298a9fff3e13292c789dd..63f4017ab22f7314818029335d51d6160fac5587 100755 (executable)
<p><code>#include <edma3_drv.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a96fe729021c036ee4a39d58a3c6400e8">OPT</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6db0f14547c0586bffb62194ffffaf75"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::SRC" ref="a6db0f14547c0586bffb62194ffffaf75" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a6db0f14547c0586bffb62194ffffaf75">SRC</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a8fdca7ee065347ea5a50f42cd0914857">OPT</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8579f79e402ee9897bf39293be301f5c"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::SRC" ref="a8579f79e402ee9897bf39293be301f5c" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a8579f79e402ee9897bf39293be301f5c">SRC</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a07ebc5f75c693a5b50383c0804d1d9e7">A_B_CNT</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aeed3278cea3d526c83477a4cc0eaee40"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::DST" ref="aeed3278cea3d526c83477a4cc0eaee40" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aeed3278cea3d526c83477a4cc0eaee40">DST</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aea70b184b092488704e5182e088d4968">A_B_CNT</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad5271044278ba0a0b2c4d24c85055ad7"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::DST" ref="ad5271044278ba0a0b2c4d24c85055ad7" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#ad5271044278ba0a0b2c4d24c85055ad7">DST</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aba20f4c8db04e562e01c6791cfebf258">SRC_DST_BIDX</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#acda2db23599012f467bf51f22a01af9e">LINK_BCNTRLD</a></td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits). <a href="#acda2db23599012f467bf51f22a01af9e"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a65b8a533cf4f336b920341d35b9a10ad"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::SRC_DST_CIDX" ref="a65b8a533cf4f336b920341d35b9a10ad" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a65b8a533cf4f336b920341d35b9a10ad">SRC_DST_CIDX</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a19270fbbb293b073c48d2ce5f1dae870">SRC_DST_BIDX</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#af47568d738013888e93d2f7a9d166b73">LINK_BCNTRLD</a></td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits). <a href="#af47568d738013888e93d2f7a9d166b73"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afd0ff3d1edca294c7a434bf480221537"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::SRC_DST_CIDX" ref="afd0ff3d1edca294c7a434bf480221537" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#afd0ff3d1edca294c7a434bf480221537">SRC_DST_CIDX</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Index between consecutive frames of a Source Block (SRCCIDX) (16 bits) and Index between consecutive frames of a Dest Block (DSTCIDX) (16 bits). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab533890c55e9dd3a71be6b02021823b3"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::CCNT" ref="ab533890c55e9dd3a71be6b02021823b3" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#ab533890c55e9dd3a71be6b02021823b3">CCNT</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adfead71f5566801a10ff1f4749a1e827"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::CCNT" ref="adfead71f5566801a10ff1f4749a1e827" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#adfead71f5566801a10ff1f4749a1e827">CCNT</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Number of Frames in a block (CCNT) (16 bits). <br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>EDMA3 PaRAM Set. </p>
<p>This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual PaRAM words. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a96fe729021c036ee4a39d58a3c6400e8"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::OPT" ref="a96fe729021c036ee4a39d58a3c6400e8" args="" -->
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+ <td class="memname">volatile uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a8fdca7ee065347ea5a50f42cd0914857">EDMA3_DRV_ParamentryRegs::OPT</a></td>
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</div>
@@ -71,12 +71,12 @@ volatile unsigned int </td><td class="memItemRight" valign="bottom"><a clas
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+<a class="anchor" id="aea70b184b092488704e5182e088d4968"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::A_B_CNT" ref="aea70b184b092488704e5182e088d4968" args="" -->
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+ <td class="memname">volatile uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aea70b184b092488704e5182e088d4968">EDMA3_DRV_ParamentryRegs::A_B_CNT</a></td>
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</table>
</div>
@@ -85,12 +85,12 @@ volatile unsigned int </td><td class="memItemRight" valign="bottom"><a clas
</div>
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-<a class="anchor" id="aba20f4c8db04e562e01c6791cfebf258"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::SRC_DST_BIDX" ref="aba20f4c8db04e562e01c6791cfebf258" args="" -->
+<a class="anchor" id="a19270fbbb293b073c48d2ce5f1dae870"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::SRC_DST_BIDX" ref="a19270fbbb293b073c48d2ce5f1dae870" args="" -->
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- <td class="memname">volatile unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#aba20f4c8db04e562e01c6791cfebf258">EDMA3_DRV_ParamentryRegs::SRC_DST_BIDX</a></td>
+ <td class="memname">volatile uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#a19270fbbb293b073c48d2ce5f1dae870">EDMA3_DRV_ParamentryRegs::SRC_DST_BIDX</a></td>
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</div>
@@ -101,12 +101,12 @@ volatile unsigned int </td><td class="memItemRight" valign="bottom"><a clas
</div>
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-<a class="anchor" id="acda2db23599012f467bf51f22a01af9e"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::LINK_BCNTRLD" ref="acda2db23599012f467bf51f22a01af9e" args="" -->
+<a class="anchor" id="af47568d738013888e93d2f7a9d166b73"></a><!-- doxytag: member="EDMA3_DRV_ParamentryRegs::LINK_BCNTRLD" ref="af47568d738013888e93d2f7a9d166b73" args="" -->
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- <td class="memname">volatile unsigned int <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#acda2db23599012f467bf51f22a01af9e">EDMA3_DRV_ParamentryRegs::LINK_BCNTRLD</a></td>
+ <td class="memname">volatile uint32_t <a class="el" href="struct_e_d_m_a3___d_r_v___paramentry_regs.html#af47568d738013888e93d2f7a9d166b73">EDMA3_DRV_ParamentryRegs::LINK_BCNTRLD</a></td>
</tr>
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</div>
@@ -122,7 +122,7 @@ volatile unsigned int </td><td class="memItemRight" valign="bottom"><a clas
<li>edma3_drv.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:34:02 2011 for EDMA3 Driver by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/EDMA3_Resource_Manager.chm b/packages/ti/sdo/edma3/rm/docs/EDMA3_Resource_Manager.chm
index ce065559ab3fdf7286b6849b3ac00fcb8808df6a..3a591c604de8b6ca5b014c75ce3f8e17176aa28d 100755 (executable)
Binary files a/packages/ti/sdo/edma3/rm/docs/EDMA3_Resource_Manager.chm and b/packages/ti/sdo/edma3/rm/docs/EDMA3_Resource_Manager.chm differ
Binary files a/packages/ti/sdo/edma3/rm/docs/EDMA3_Resource_Manager.chm and b/packages/ti/sdo/edma3/rm/docs/EDMA3_Resource_Manager.chm differ
diff --git a/packages/ti/sdo/edma3/rm/docs/html/annotated.html b/packages/ti/sdo/edma3/rm/docs/html/annotated.html
index c33732d4b999ffe11bd09a7fc4ba18c00fdd4d6e..d36a9ac9c8771e7ccf52e2c7f90cff1b8c3bcac1 100755 (executable)
<tr><td class="indexkey"><a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html">EDMA3_RM_TccCallbackParams</a></td><td class="indexvalue">TCC Callback - Caters to channel specific status reporting </td></tr>
</table>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:50 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/classes.html b/packages/ti/sdo/edma3/rm/docs/html/classes.html
index ca585c4a8495655311766f62d957a7e2b6e236ec..7bfee7327e10a7e33ea7173ec34fc1166cc12928 100755 (executable)
<tr><td><a name="letter_E"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah"> E </div></td></tr></table>
</td><td><a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html">EDMA3_RM_GblXbarToChanConfigParams</a> </td><td><a class="el" href="struct_e_d_m_a3___r_m___obj.html">EDMA3_RM_Obj</a> </td><td><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html">EDMA3_RM_PaRAMRegs</a> </td></tr><tr><td><a class="el" href="struct_e_d_m_a3___r_m___ch_bound_resources.html">EDMA3_RM_ChBoundResources</a> </td><td><a class="el" href="struct_e_d_m_a3___r_m___instance.html">EDMA3_RM_Instance</a> </td><td><a class="el" href="struct_e_d_m_a3___r_m___param.html">EDMA3_RM_Param</a> </td><td><a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> </td></tr><tr><td><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html">EDMA3_RM_GblConfigParams</a> </td><td><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html">EDMA3_RM_InstanceInitConfig</a> </td><td><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html">EDMA3_RM_ParamentryRegs</a> </td><td><a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html">EDMA3_RM_TccCallbackParams</a> </td></tr><tr><td><a class="el" href="struct_e_d_m_a3___r_m___gbl_err_callback_params.html">EDMA3_RM_GblErrCallbackParams</a> </td><td><a class="el" href="struct_e_d_m_a3___r_m___misc_param.html">EDMA3_RM_MiscParam</a> </td></tr></table><div class="qindex"><a class="qindex" href="#letter_E">E</a></div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:50 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/functions.html b/packages/ti/sdo/edma3/rm/docs/html/functions.html
index 56ae833846dd171e5f642dc2e0be65ad604403cc..c89c8904e04f1115420db3ac71ed14857320d42d 100755 (executable)
@@ -55,10 +55,10 @@ Here is a list of all documented struct and union fields with links to the struc
<h3><a class="anchor" id="index_a">- a -</a></h3><ul>
<li>A_B_CNT
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a86ce51bcde596db8686df5151d1e36f4">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#acc6b08ed32da038adf39628a11314042">EDMA3_RM_ParamentryRegs</a>
</li>
<li>aCnt
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a6b793fb789c2e62244588c1de455d5c3">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ade3675d257bad105135f87cacecb6071">EDMA3_RM_PaRAMRegs</a>
</li>
<li>avlblDmaChannels
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#ac79c170f0c84f077084772c06334e72c">EDMA3_RM_Instance</a>
@@ -77,10 +77,10 @@ Here is a list of all documented struct and union fields with links to the struc
<h3><a class="anchor" id="index_b">- b -</a></h3><ul>
<li>bCnt
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ac7a839fc4ec88ef71de0298ae9d0f5c0">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a7fcb8088ada92e2a8e85b8ddf799497e">EDMA3_RM_PaRAMRegs</a>
</li>
<li>bCntReload
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ae7a0840fb53ccfd2ae35e943390bf9f2">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a89420524d0a519582e3b8a991272c04a">EDMA3_RM_PaRAMRegs</a>
</li>
</ul>
@@ -90,13 +90,13 @@ Here is a list of all documented struct and union fields with links to the struc
: <a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html#a9834742e3ec7ea2b7ec1064055417cab">EDMA3_RM_TccCallbackParams</a>
</li>
<li>ccError
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a9154b7f04bfe4b3f3d1071da8ad8b483">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a4f06097909c77f1ed1cbec564ba4d8bb">EDMA3_RM_GblConfigParams</a>
</li>
<li>cCnt
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a88d49983095c65ad1787cc02d56daf27">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ad3fd07485720ce2655f7cbda7c9ab067">EDMA3_RM_PaRAMRegs</a>
</li>
<li>CCNT
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#aa3ef14c588c533a40427f219242e7f2a">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#aa45df17e9b9fad3ce516d3d7053dcdd8">EDMA3_RM_ParamentryRegs</a>
</li>
<li>configScrMapXbarToEvt
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#aa68814a024cee0e4239d9b58acdfa6aa">EDMA3_RM_Instance</a>
@@ -106,41 +106,41 @@ Here is a list of all documented struct and union fields with links to the struc
<h3><a class="anchor" id="index_d">- d -</a></h3><ul>
<li>destAddr
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a476c3a53fd360b0c823c4432ef3da665">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#abc6bf0cba0c58295198a0a361ff832f6">EDMA3_RM_PaRAMRegs</a>
</li>
<li>destBIdx
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a20e706a171712ea04b3f73cfaaa9b388">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ae884a5534b218804f5ede866d8ee8814">EDMA3_RM_PaRAMRegs</a>
</li>
<li>destCIdx
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a14e3f593a8db50dd39fc5379a7fa2b7a">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ae21ea5a25f7aadbee9ae6aa0d9c194fa">EDMA3_RM_PaRAMRegs</a>
</li>
<li>dmaChannelHwEvtMap
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ac75808b1b49e327e540620ff08eb23d7">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afcb2fcb340f13f2e450fac817b255747">EDMA3_RM_GblConfigParams</a>
</li>
<li>dmaChannelPaRAMMap
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afa7ba95cc73b21f640888aab87a66533">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a6366c59f0006724b2966135e0ea81fef">EDMA3_RM_GblConfigParams</a>
</li>
<li>dmaChannelTccMap
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ab06c1d88f0efb9c82c963daf8d7ea684">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af409720cb469a021a3624ff4d3e6ded6">EDMA3_RM_GblConfigParams</a>
</li>
<li>dmaChPaRAMMapExists
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#adc4e7bfa2cfca03fa38c8baa10b508be">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#aa3fd8314930b636baf770de745c1cacc">EDMA3_RM_GblConfigParams</a>
</li>
<li>dmaMapXbarToChan
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html#a170275163e292e728ed7c0039e84811a">EDMA3_RM_GblXbarToChanConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html#ad1a73637621a502d4a5bc896a2bcd6ca">EDMA3_RM_GblXbarToChanConfigParams</a>
</li>
<li>DST
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a962a4fded1f7b63f8cc9150c924b97f5">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#af0dfaf6acd333ce4f4ebadcfbe983609">EDMA3_RM_ParamentryRegs</a>
</li>
</ul>
<h3><a class="anchor" id="index_e">- e -</a></h3><ul>
<li>evtQPri
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ad4e9caa9307edbc6832ebe662de1b6f6">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ace6903ed2d8d30d97a4b1a2d51426021">EDMA3_RM_GblConfigParams</a>
</li>
<li>evtQueueWaterMarkLvl
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ae633ff54dda219dafc5d3b609a28a202">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af8f66e50d0fd61272e332fa69c437612">EDMA3_RM_GblConfigParams</a>
</li>
</ul>
@@ -169,20 +169,20 @@ Here is a list of all documented struct and union fields with links to the struc
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#a9ea516313f4cbf1203ed945b75120770">EDMA3_RM_Instance</a>
</li>
<li>isMaster
-: <a class="el" href="struct_e_d_m_a3___r_m___param.html#ad984d3a198db18f7287c67e3b7b74da9">EDMA3_RM_Param</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___param.html#a784ad88bc2b19240b1ecd83fe91c247a">EDMA3_RM_Param</a>
</li>
<li>isSlave
-: <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a56ea473581e1d76b7497796d1e46d850">EDMA3_RM_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a70ded9151608e23053f391816898f17d">EDMA3_RM_MiscParam</a>
</li>
</ul>
<h3><a class="anchor" id="index_l">- l -</a></h3><ul>
<li>LINK_BCNTRLD
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a4262be65b0dcae242b5e2dccd5b5b23f">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a94895249b81f76b9aee370af7dcc53c8">EDMA3_RM_ParamentryRegs</a>
</li>
<li>linkAddr
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a895743ea8620f21b5ddc2149d2a05c3b">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a137bdee75d4f4850cc914123637b4c33">EDMA3_RM_PaRAMRegs</a>
</li>
</ul>
@@ -192,64 +192,64 @@ Here is a list of all documented struct and union fields with links to the struc
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#a35df179f3c52d5099e37a3ffcc06d5ae">EDMA3_RM_Instance</a>
</li>
<li>memProtectionExists
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ac2e3f4494b538c862581895558b37e6f">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a14d7d6cb9ccba0f454616b21cd6a7229">EDMA3_RM_GblConfigParams</a>
</li>
</ul>
<h3><a class="anchor" id="index_n">- n -</a></h3><ul>
<li>numDmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a146c49c83ca4e65a3145d9b15d73571d">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a90181831a767d1f5e6d796a5eb9a2ed1">EDMA3_RM_GblConfigParams</a>
</li>
<li>numEvtQueue
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a152b2623285f14f6013b130fbfdf2ee1">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a054dff0f68d9260dd20478042683e400">EDMA3_RM_GblConfigParams</a>
</li>
<li>numOpens
: <a class="el" href="struct_e_d_m_a3___r_m___obj.html#a13b4308a8ad6baf647b5c7adbe54702c">EDMA3_RM_Obj</a>
</li>
<li>numPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a9f66e1878cc69101518f94c5f95ec393">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af5b2f463d96971ecebc269cc2b3e1e76">EDMA3_RM_GblConfigParams</a>
</li>
<li>numQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a49bb3d33efc585d75c8c18cf26dbf169">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afa03f7cd037ca5983017c8c403f82419">EDMA3_RM_GblConfigParams</a>
</li>
<li>numRegions
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af96ad7a22abe4152c2dbec6ddd793ffb">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a6b973fc32b6d8f47cb8dd46bb1ba88fd">EDMA3_RM_GblConfigParams</a>
</li>
<li>numTccs
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ade09c3f169c87739ab5b5d00101a59ed">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a8a0680e508ad29d759a0370084cbb6c0">EDMA3_RM_GblConfigParams</a>
</li>
<li>numTcs
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a2469da2ae6f4c3895c1edf6333590b1e">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afbce74bc0f62d807cb436656f418338a">EDMA3_RM_GblConfigParams</a>
</li>
</ul>
<h3><a class="anchor" id="index_o">- o -</a></h3><ul>
<li>OPT
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a0cf7a755d7bae28725d5473f55e4b285">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a110b9d0964b16086bcce89f7a6a46cbe">EDMA3_RM_ParamentryRegs</a>
</li>
<li>opt
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ab3fbc10843edca5369164bb54f8f1311">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a7b017530e64c24d5e51a1b557820da7c">EDMA3_RM_PaRAMRegs</a>
</li>
<li>ownDmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#afea6ae753bce07d64d92f6521bb489e5">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a3160a96263a4aa8049a22f27fd620af0">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>ownPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a195712f03e6c92f0a386dd036422f956">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a1825ba86c6fb95f870475beeb6de5864">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>ownQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a836f8f25e8a2e01d6649034b7cc92d50">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a4d53baba7f90efe887ef6607e02a465e">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>ownTccs
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a38b3b42404f41e978c3b682ccf63fa8f">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#af3c6a8276f80b2e4314984a6eb03790b">EDMA3_RM_InstanceInitConfig</a>
</li>
</ul>
<h3><a class="anchor" id="index_p">- p -</a></h3><ul>
<li>param
-: <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#ab66a1abe88183a9f57c85373010e5c75">EDMA3_RM_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a73a5b20cd432208e692cd0be0faef50e">EDMA3_RM_MiscParam</a>
</li>
<li>paRAMId
: <a class="el" href="struct_e_d_m_a3___r_m___ch_bound_resources.html#abe7b47232db77c8ed3ce9487ca8f658f">EDMA3_RM_ChBoundResources</a>
@@ -271,28 +271,28 @@ Here is a list of all documented struct and union fields with links to the struc
: <a class="el" href="struct_e_d_m_a3___r_m___param.html#a5722cd299dd4712cdb9f7cf7aec869b6">EDMA3_RM_Param</a>
</li>
<li>regionInitEnable
-: <a class="el" href="struct_e_d_m_a3___r_m___param.html#ad0a96e32f45702667e091717595150f8">EDMA3_RM_Param</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___param.html#a2d609f44e5cc8e6c08fb217bd0ba7d18">EDMA3_RM_Param</a>
</li>
<li>regModificationRequired
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#a9994deccfdf8a63db677311aced1db79">EDMA3_RM_Instance</a>
</li>
<li>reserved
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a4c42631d5ab80acf9332ba666abf9a9b">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a71075ffdf5d932cf329fb18ccb2a8412">EDMA3_RM_PaRAMRegs</a>
</li>
<li>resId
-: <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a8fffc8bd17e838ce866a225ffe14ce02">EDMA3_RM_ResDesc</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a7a3b79d5f21a9a6d4af2e47edc905b69">EDMA3_RM_ResDesc</a>
</li>
<li>resvdDmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a6df76275220d03b4b42c9161b4d670ff">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a32f9138da21f943608572ee5598162b8">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>resvdPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ab97d5476ee84765b1cb26216af673cfc">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#aeedea606ea2994be97bf4f1095eff9b1">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>resvdQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ae7909518f9ba93b32c496193e797bf3b">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ab9330897d8493510ec820604832320a8">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>resvdTccs
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a7996562a8045cf6b7f33e40aa9b49313">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#aecf1dd1cffbf644e3275b41ab6f94d9b">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>rmInstInitConfig
: <a class="el" href="struct_e_d_m_a3___r_m___param.html#ab4b422aad358309280f16027423df238">EDMA3_RM_Param</a>
@@ -311,22 +311,22 @@ Here is a list of all documented struct and union fields with links to the struc
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#ab3bc4cc87520c8156b0569600b9678e5">EDMA3_RM_Instance</a>
</li>
<li>SRC
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a5cdf48fe9dfa1bf57634707cb0844272">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a6fcb86ab0e29c57c86c81de6509023c8">EDMA3_RM_ParamentryRegs</a>
</li>
<li>SRC_DST_BIDX
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#afb5a2b7960d93156dbf7d5f1966b5b47">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a8a8201bdc65cca0618ab84cba098a6d9">EDMA3_RM_ParamentryRegs</a>
</li>
<li>SRC_DST_CIDX
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#ac2f5d7cc117f6078c9857ebb630cad17">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a84deb8a812c77152972d24126fbac35a">EDMA3_RM_ParamentryRegs</a>
</li>
<li>srcAddr
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a88f22ecb531e50776a8d39efb07e1f03">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#afd0564c51a029cfd93d571792a2de9df">EDMA3_RM_PaRAMRegs</a>
</li>
<li>srcBIdx
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a379c5a7e527a0df8f1a0f3f570370a4a">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ad2580901284de100faad83df848dd448">EDMA3_RM_PaRAMRegs</a>
</li>
<li>srcCIdx
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a948163aaedd3fff182f8ba9de03b4091">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#aeb5320c3c544792f3e9c3703586d6192">EDMA3_RM_PaRAMRegs</a>
</li>
<li>state
: <a class="el" href="struct_e_d_m_a3___r_m___obj.html#aa262df0776f0a9b6163e8f64d91a0265">EDMA3_RM_Obj</a>
@@ -342,10 +342,10 @@ Here is a list of all documented struct and union fields with links to the struc
: <a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html#ab46111c7ca4b209d38383103bfd9a1e5">EDMA3_RM_TccCallbackParams</a>
</li>
<li>tcDefaultBurstSize
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#add171129e6252b02ba54d5e79cb7ecea">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#aefb3e813e7cad1cf08f7f4af24f13015">EDMA3_RM_GblConfigParams</a>
</li>
<li>tcError
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a72c01f8e87453fc8495371cd44b2dcc4">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a7bcfe31be2064b8133bbb37044079816">EDMA3_RM_GblConfigParams</a>
</li>
<li>tcRegs
: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a167e1ab12a947d4446ba56f8129ed91d">EDMA3_RM_GblConfigParams</a>
@@ -358,11 +358,11 @@ Here is a list of all documented struct and union fields with links to the struc
<h3><a class="anchor" id="index_x">- x -</a></h3><ul>
<li>xferCompleteInt
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af902e3c9d3d6d54fdc472bf79297c947">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a04d28c89d332f101383e0db8452154e4">EDMA3_RM_GblConfigParams</a>
</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:50 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/functions_vars.html b/packages/ti/sdo/edma3/rm/docs/html/functions_vars.html
index 4755debb84c9144056557a3bb64b6b67f8835f27..c8e1e356934aec276a60a3c40c0c6af428c84352 100755 (executable)
<h3><a class="anchor" id="index_a">- a -</a></h3><ul>
<li>A_B_CNT
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a86ce51bcde596db8686df5151d1e36f4">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#acc6b08ed32da038adf39628a11314042">EDMA3_RM_ParamentryRegs</a>
</li>
<li>aCnt
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a6b793fb789c2e62244588c1de455d5c3">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ade3675d257bad105135f87cacecb6071">EDMA3_RM_PaRAMRegs</a>
</li>
<li>avlblDmaChannels
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#ac79c170f0c84f077084772c06334e72c">EDMA3_RM_Instance</a>
<h3><a class="anchor" id="index_b">- b -</a></h3><ul>
<li>bCnt
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ac7a839fc4ec88ef71de0298ae9d0f5c0">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a7fcb8088ada92e2a8e85b8ddf799497e">EDMA3_RM_PaRAMRegs</a>
</li>
<li>bCntReload
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ae7a0840fb53ccfd2ae35e943390bf9f2">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a89420524d0a519582e3b8a991272c04a">EDMA3_RM_PaRAMRegs</a>
</li>
</ul>
: <a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html#a9834742e3ec7ea2b7ec1064055417cab">EDMA3_RM_TccCallbackParams</a>
</li>
<li>ccError
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a9154b7f04bfe4b3f3d1071da8ad8b483">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a4f06097909c77f1ed1cbec564ba4d8bb">EDMA3_RM_GblConfigParams</a>
</li>
<li>cCnt
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a88d49983095c65ad1787cc02d56daf27">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ad3fd07485720ce2655f7cbda7c9ab067">EDMA3_RM_PaRAMRegs</a>
</li>
<li>CCNT
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#aa3ef14c588c533a40427f219242e7f2a">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#aa45df17e9b9fad3ce516d3d7053dcdd8">EDMA3_RM_ParamentryRegs</a>
</li>
<li>configScrMapXbarToEvt
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#aa68814a024cee0e4239d9b58acdfa6aa">EDMA3_RM_Instance</a>
<h3><a class="anchor" id="index_d">- d -</a></h3><ul>
<li>destAddr
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a476c3a53fd360b0c823c4432ef3da665">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#abc6bf0cba0c58295198a0a361ff832f6">EDMA3_RM_PaRAMRegs</a>
</li>
<li>destBIdx
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a20e706a171712ea04b3f73cfaaa9b388">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ae884a5534b218804f5ede866d8ee8814">EDMA3_RM_PaRAMRegs</a>
</li>
<li>destCIdx
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a14e3f593a8db50dd39fc5379a7fa2b7a">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ae21ea5a25f7aadbee9ae6aa0d9c194fa">EDMA3_RM_PaRAMRegs</a>
</li>
<li>dmaChannelHwEvtMap
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ac75808b1b49e327e540620ff08eb23d7">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afcb2fcb340f13f2e450fac817b255747">EDMA3_RM_GblConfigParams</a>
</li>
<li>dmaChannelPaRAMMap
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afa7ba95cc73b21f640888aab87a66533">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a6366c59f0006724b2966135e0ea81fef">EDMA3_RM_GblConfigParams</a>
</li>
<li>dmaChannelTccMap
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ab06c1d88f0efb9c82c963daf8d7ea684">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af409720cb469a021a3624ff4d3e6ded6">EDMA3_RM_GblConfigParams</a>
</li>
<li>dmaChPaRAMMapExists
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#adc4e7bfa2cfca03fa38c8baa10b508be">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#aa3fd8314930b636baf770de745c1cacc">EDMA3_RM_GblConfigParams</a>
</li>
<li>dmaMapXbarToChan
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html#a170275163e292e728ed7c0039e84811a">EDMA3_RM_GblXbarToChanConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html#ad1a73637621a502d4a5bc896a2bcd6ca">EDMA3_RM_GblXbarToChanConfigParams</a>
</li>
<li>DST
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a962a4fded1f7b63f8cc9150c924b97f5">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#af0dfaf6acd333ce4f4ebadcfbe983609">EDMA3_RM_ParamentryRegs</a>
</li>
</ul>
<h3><a class="anchor" id="index_e">- e -</a></h3><ul>
<li>evtQPri
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ad4e9caa9307edbc6832ebe662de1b6f6">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ace6903ed2d8d30d97a4b1a2d51426021">EDMA3_RM_GblConfigParams</a>
</li>
<li>evtQueueWaterMarkLvl
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ae633ff54dda219dafc5d3b609a28a202">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af8f66e50d0fd61272e332fa69c437612">EDMA3_RM_GblConfigParams</a>
</li>
</ul>
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#a9ea516313f4cbf1203ed945b75120770">EDMA3_RM_Instance</a>
</li>
<li>isMaster
-: <a class="el" href="struct_e_d_m_a3___r_m___param.html#ad984d3a198db18f7287c67e3b7b74da9">EDMA3_RM_Param</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___param.html#a784ad88bc2b19240b1ecd83fe91c247a">EDMA3_RM_Param</a>
</li>
<li>isSlave
-: <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a56ea473581e1d76b7497796d1e46d850">EDMA3_RM_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a70ded9151608e23053f391816898f17d">EDMA3_RM_MiscParam</a>
</li>
</ul>
<h3><a class="anchor" id="index_l">- l -</a></h3><ul>
<li>LINK_BCNTRLD
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a4262be65b0dcae242b5e2dccd5b5b23f">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a94895249b81f76b9aee370af7dcc53c8">EDMA3_RM_ParamentryRegs</a>
</li>
<li>linkAddr
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a895743ea8620f21b5ddc2149d2a05c3b">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a137bdee75d4f4850cc914123637b4c33">EDMA3_RM_PaRAMRegs</a>
</li>
</ul>
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#a35df179f3c52d5099e37a3ffcc06d5ae">EDMA3_RM_Instance</a>
</li>
<li>memProtectionExists
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ac2e3f4494b538c862581895558b37e6f">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a14d7d6cb9ccba0f454616b21cd6a7229">EDMA3_RM_GblConfigParams</a>
</li>
</ul>
<h3><a class="anchor" id="index_n">- n -</a></h3><ul>
<li>numDmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a146c49c83ca4e65a3145d9b15d73571d">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a90181831a767d1f5e6d796a5eb9a2ed1">EDMA3_RM_GblConfigParams</a>
</li>
<li>numEvtQueue
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a152b2623285f14f6013b130fbfdf2ee1">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a054dff0f68d9260dd20478042683e400">EDMA3_RM_GblConfigParams</a>
</li>
<li>numOpens
: <a class="el" href="struct_e_d_m_a3___r_m___obj.html#a13b4308a8ad6baf647b5c7adbe54702c">EDMA3_RM_Obj</a>
</li>
<li>numPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a9f66e1878cc69101518f94c5f95ec393">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af5b2f463d96971ecebc269cc2b3e1e76">EDMA3_RM_GblConfigParams</a>
</li>
<li>numQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a49bb3d33efc585d75c8c18cf26dbf169">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afa03f7cd037ca5983017c8c403f82419">EDMA3_RM_GblConfigParams</a>
</li>
<li>numRegions
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af96ad7a22abe4152c2dbec6ddd793ffb">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a6b973fc32b6d8f47cb8dd46bb1ba88fd">EDMA3_RM_GblConfigParams</a>
</li>
<li>numTccs
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ade09c3f169c87739ab5b5d00101a59ed">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a8a0680e508ad29d759a0370084cbb6c0">EDMA3_RM_GblConfigParams</a>
</li>
<li>numTcs
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a2469da2ae6f4c3895c1edf6333590b1e">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afbce74bc0f62d807cb436656f418338a">EDMA3_RM_GblConfigParams</a>
</li>
</ul>
<h3><a class="anchor" id="index_o">- o -</a></h3><ul>
<li>OPT
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a0cf7a755d7bae28725d5473f55e4b285">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a110b9d0964b16086bcce89f7a6a46cbe">EDMA3_RM_ParamentryRegs</a>
</li>
<li>opt
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ab3fbc10843edca5369164bb54f8f1311">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a7b017530e64c24d5e51a1b557820da7c">EDMA3_RM_PaRAMRegs</a>
</li>
<li>ownDmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#afea6ae753bce07d64d92f6521bb489e5">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a3160a96263a4aa8049a22f27fd620af0">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>ownPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a195712f03e6c92f0a386dd036422f956">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a1825ba86c6fb95f870475beeb6de5864">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>ownQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a836f8f25e8a2e01d6649034b7cc92d50">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a4d53baba7f90efe887ef6607e02a465e">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>ownTccs
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a38b3b42404f41e978c3b682ccf63fa8f">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#af3c6a8276f80b2e4314984a6eb03790b">EDMA3_RM_InstanceInitConfig</a>
</li>
</ul>
<h3><a class="anchor" id="index_p">- p -</a></h3><ul>
<li>param
-: <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#ab66a1abe88183a9f57c85373010e5c75">EDMA3_RM_MiscParam</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a73a5b20cd432208e692cd0be0faef50e">EDMA3_RM_MiscParam</a>
</li>
<li>paRAMId
: <a class="el" href="struct_e_d_m_a3___r_m___ch_bound_resources.html#abe7b47232db77c8ed3ce9487ca8f658f">EDMA3_RM_ChBoundResources</a>
: <a class="el" href="struct_e_d_m_a3___r_m___param.html#a5722cd299dd4712cdb9f7cf7aec869b6">EDMA3_RM_Param</a>
</li>
<li>regionInitEnable
-: <a class="el" href="struct_e_d_m_a3___r_m___param.html#ad0a96e32f45702667e091717595150f8">EDMA3_RM_Param</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___param.html#a2d609f44e5cc8e6c08fb217bd0ba7d18">EDMA3_RM_Param</a>
</li>
<li>regModificationRequired
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#a9994deccfdf8a63db677311aced1db79">EDMA3_RM_Instance</a>
</li>
<li>reserved
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a4c42631d5ab80acf9332ba666abf9a9b">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a71075ffdf5d932cf329fb18ccb2a8412">EDMA3_RM_PaRAMRegs</a>
</li>
<li>resId
-: <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a8fffc8bd17e838ce866a225ffe14ce02">EDMA3_RM_ResDesc</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a7a3b79d5f21a9a6d4af2e47edc905b69">EDMA3_RM_ResDesc</a>
</li>
<li>resvdDmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a6df76275220d03b4b42c9161b4d670ff">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a32f9138da21f943608572ee5598162b8">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>resvdPaRAMSets
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ab97d5476ee84765b1cb26216af673cfc">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#aeedea606ea2994be97bf4f1095eff9b1">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>resvdQdmaChannels
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ae7909518f9ba93b32c496193e797bf3b">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ab9330897d8493510ec820604832320a8">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>resvdTccs
-: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a7996562a8045cf6b7f33e40aa9b49313">EDMA3_RM_InstanceInitConfig</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#aecf1dd1cffbf644e3275b41ab6f94d9b">EDMA3_RM_InstanceInitConfig</a>
</li>
<li>rmInstInitConfig
: <a class="el" href="struct_e_d_m_a3___r_m___param.html#ab4b422aad358309280f16027423df238">EDMA3_RM_Param</a>
: <a class="el" href="struct_e_d_m_a3___r_m___instance.html#ab3bc4cc87520c8156b0569600b9678e5">EDMA3_RM_Instance</a>
</li>
<li>SRC
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a5cdf48fe9dfa1bf57634707cb0844272">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a6fcb86ab0e29c57c86c81de6509023c8">EDMA3_RM_ParamentryRegs</a>
</li>
<li>SRC_DST_BIDX
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#afb5a2b7960d93156dbf7d5f1966b5b47">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a8a8201bdc65cca0618ab84cba098a6d9">EDMA3_RM_ParamentryRegs</a>
</li>
<li>SRC_DST_CIDX
-: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#ac2f5d7cc117f6078c9857ebb630cad17">EDMA3_RM_ParamentryRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a84deb8a812c77152972d24126fbac35a">EDMA3_RM_ParamentryRegs</a>
</li>
<li>srcAddr
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a88f22ecb531e50776a8d39efb07e1f03">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#afd0564c51a029cfd93d571792a2de9df">EDMA3_RM_PaRAMRegs</a>
</li>
<li>srcBIdx
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a379c5a7e527a0df8f1a0f3f570370a4a">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ad2580901284de100faad83df848dd448">EDMA3_RM_PaRAMRegs</a>
</li>
<li>srcCIdx
-: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a948163aaedd3fff182f8ba9de03b4091">EDMA3_RM_PaRAMRegs</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#aeb5320c3c544792f3e9c3703586d6192">EDMA3_RM_PaRAMRegs</a>
</li>
<li>state
: <a class="el" href="struct_e_d_m_a3___r_m___obj.html#aa262df0776f0a9b6163e8f64d91a0265">EDMA3_RM_Obj</a>
: <a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html#ab46111c7ca4b209d38383103bfd9a1e5">EDMA3_RM_TccCallbackParams</a>
</li>
<li>tcDefaultBurstSize
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#add171129e6252b02ba54d5e79cb7ecea">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#aefb3e813e7cad1cf08f7f4af24f13015">EDMA3_RM_GblConfigParams</a>
</li>
<li>tcError
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a72c01f8e87453fc8495371cd44b2dcc4">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a7bcfe31be2064b8133bbb37044079816">EDMA3_RM_GblConfigParams</a>
</li>
<li>tcRegs
: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a167e1ab12a947d4446ba56f8129ed91d">EDMA3_RM_GblConfigParams</a>
<h3><a class="anchor" id="index_x">- x -</a></h3><ul>
<li>xferCompleteInt
-: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af902e3c9d3d6d54fdc472bf79297c947">EDMA3_RM_GblConfigParams</a>
+: <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a04d28c89d332f101383e0db8452154e4">EDMA3_RM_GblConfigParams</a>
</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:50 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___a_p_i.html b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___a_p_i.html
index 54fd074f0a1b3080b30a17a85af9899d342a841a..0cb00b8cb61bb531147ebaaf8ed5870fee5d2770 100755 (executable)
Overview</a></h3>
<p>EDMA3 Resource Manager is a TI mandated library for all EDMA3 peripheral users to acquire and configure EDMA3 hardware resources (DMA/QDMA channels, PaRAM Sets, TCCs etc.) and DMA Interrupt Service Routines. </p>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:49 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___d_a_t_a_s_t_r_u_c_t.html b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___d_a_t_a_s_t_r_u_c_t.html
index 53529fdde60a1a09c6257c6ceb07476623ab46c6..b798e7751b3d0ef1fe287f0c53118ba320b5dec2 100755 (executable)
<tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 PaRAM Set in User Configurable format. <a href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#_details">More...</a><br/></td></tr>
</table>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:49 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n.html b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n.html
index 80a56e23a2db50a685e64a181fedce479458930d..8abd0614404836ff11272933f42c1c6ee9afa077 100755 (executable)
<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html">EDMA3 Resource Manager Advanced APIs</a></td></tr>
</table>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:49 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html
index 0faacc9222fe8c80543c6d0cf342900935e196d5..45ec7457d601d6f6a557100b6b8c8246366fb882 100755 (executable)
<tr><td class="memItemLeft" align="right" valign="top">struct </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html">EDMA3_RM_GblXbarToChanConfigParams</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. <a href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html#_details">More...</a><br/></td></tr>
<tr><td colspan="2"><h2>Typedefs</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_RM_Result(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga373c55dba0c349454ce9be1a625ad17f">EDMA3_RM_mapXbarEvtToChan</a> )(unsigned int eventNum, unsigned int *chanNum, const <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html">EDMA3_RM_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Associates cross bar mapped event to channel. <a href="#ga373c55dba0c349454ce9be1a625ad17f"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_RM_Result(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga07f4c95a3095e6f0b25d34931312b315">EDMA3_RM_xbarConfigScr</a> )(unsigned int eventNum, unsigned int chanNum)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Writes to the cross bar mapped event to channel to system configuration register. <a href="#ga07f4c95a3095e6f0b25d34931312b315"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_RM_Result(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa3446e78614a94f6a90723f79888fd33">EDMA3_RM_mapXbarEvtToChan</a> )(uint32_t eventNum, uint32_t *chanNum, const <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html">EDMA3_RM_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Associates cross bar mapped event to channel. <a href="#gaa3446e78614a94f6a90723f79888fd33"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef EDMA3_RM_Result(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1e994f8dbd5632fa1ed4930dad03593f">EDMA3_RM_xbarConfigScr</a> )(uint32_t eventNum, uint32_t chanNum)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Writes to the cross bar mapped event to channel to system configuration register. <a href="#ga1e994f8dbd5632fa1ed4930dad03593f"></a><br/></td></tr>
<tr><td colspan="2"><h2>Functions</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga4ac58bd9d22200f51216887576f77d32">EDMA3_RM_allocLogicalChannel</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *lChObj, unsigned int *pParam, unsigned int *pTcc)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Request a DMA/QDMA/Link channel. <a href="#ga4ac58bd9d22200f51216887576f77d32"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga349e5d31b0ff155b6d1a4052396f8dd5">EDMA3_RM_allocLogicalChannel</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *lChObj, uint32_t *pParam, uint32_t *pTcc)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Request a DMA/QDMA/Link channel. <a href="#ga349e5d31b0ff155b6d1a4052396f8dd5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga5edfca892da0ae3320f9bf9df4bfd52f">EDMA3_RM_freeLogicalChannel</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *lChObj)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc). <a href="#ga5edfca892da0ae3320f9bf9df4bfd52f"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gac921ebbbe2c23fb5b55d6822d8731b90">EDMA3_RM_mapEdmaChannel</a> (EDMA3_RM_Handle hEdmaResMgr, unsigned int channelId, unsigned int paRAMId)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. <a href="#gac921ebbbe2c23fb5b55d6822d8731b90"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga9ed44bdab3967bbad7d4edddadde819f">EDMA3_RM_mapQdmaChannel</a> (EDMA3_RM_Handle hEdmaResMgr, unsigned int channelId, unsigned int paRAMId, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#gacabe6aeb4a0ce496671777e783cdb2c4">EDMA3_RM_QdmaTrigWord</a> trigWord)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. <a href="#ga9ed44bdab3967bbad7d4edddadde819f"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1c222a9feda9024cf4e28ba897b5c285">EDMA3_RM_setCCRegister</a> (EDMA3_RM_Handle hEdmaResMgr, unsigned int regOffset, unsigned int newRegValue)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Set the Channel Controller (CC) Register value. <a href="#ga1c222a9feda9024cf4e28ba897b5c285"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaea15b18d6ef5224fe0e4a1beadc6d1ee">EDMA3_RM_getCCRegister</a> (EDMA3_RM_Handle hEdmaResMgr, unsigned int regOffset, unsigned int *regValue)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the Channel Controller (CC) Register value. <a href="#gaea15b18d6ef5224fe0e4a1beadc6d1ee"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gac9a6d0bd72ba4476c30b2898e407888e">EDMA3_RM_waitAndClearTcc</a> (EDMA3_RM_Handle hEdmaResMgr, unsigned int tccNo)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait for a transfer completion interrupt to occur and clear it. <a href="#gac9a6d0bd72ba4476c30b2898e407888e"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga0ebe052bd9f612942908236bc96c54b4">EDMA3_RM_checkAndClearTcc</a> (EDMA3_RM_Handle hEdmaResMgr, unsigned int tccNo, unsigned short *tccStatus)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Returns the status of a previously initiated transfer. <a href="#ga0ebe052bd9f612942908236bc96c54b4"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gad0690a3a5317d4d928b1d968e61ac796">EDMA3_RM_mapEdmaChannel</a> (EDMA3_RM_Handle hEdmaResMgr, uint32_t channelId, uint32_t paRAMId)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. <a href="#gad0690a3a5317d4d928b1d968e61ac796"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga0b893408e1d61aff5662f76ea9aac6b9">EDMA3_RM_mapQdmaChannel</a> (EDMA3_RM_Handle hEdmaResMgr, uint32_t channelId, uint32_t paRAMId, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#gacabe6aeb4a0ce496671777e783cdb2c4">EDMA3_RM_QdmaTrigWord</a> trigWord)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error. <a href="#ga0b893408e1d61aff5662f76ea9aac6b9"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga3c1f70a6659baae70acd0bd5e05ce42c">EDMA3_RM_setCCRegister</a> (EDMA3_RM_Handle hEdmaResMgr, uint32_t regOffset, uint32_t newRegValue)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Set the Channel Controller (CC) Register value. <a href="#ga3c1f70a6659baae70acd0bd5e05ce42c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga508e7ab10ea4d68b7d52777128523123">EDMA3_RM_getCCRegister</a> (EDMA3_RM_Handle hEdmaResMgr, uint32_t regOffset, uint32_t *regValue)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the Channel Controller (CC) Register value. <a href="#ga508e7ab10ea4d68b7d52777128523123"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga03eb291d9e4f05e66f304e0e1c09e795">EDMA3_RM_waitAndClearTcc</a> (EDMA3_RM_Handle hEdmaResMgr, uint32_t tccNo)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Wait for a transfer completion interrupt to occur and clear it. <a href="#ga03eb291d9e4f05e66f304e0e1c09e795"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaf275e3dedd2a7592eec305d18b19bbbd">EDMA3_RM_checkAndClearTcc</a> (EDMA3_RM_Handle hEdmaResMgr, uint32_t tccNo, uint16_t *tccStatus)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Returns the status of a previously initiated transfer. <a href="#gaf275e3dedd2a7592eec305d18b19bbbd"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gae904366a2d8518b01bf36c4fe5e1596b">EDMA3_RM_setPaRAM</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *lChObj, const <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html">EDMA3_RM_PaRAMRegs</a> *newPaRAM)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link). <a href="#gae904366a2d8518b01bf36c4fe5e1596b"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga3ba432ad2e794dcce6f892e839a1c4fd">EDMA3_RM_getPaRAM</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *lChObj, <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html">EDMA3_RM_PaRAMRegs</a> *currPaRAM)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link). <a href="#ga3ba432ad2e794dcce6f892e839a1c4fd"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gac1155de8f396305d8e23da2bb81cc731">EDMA3_RM_getPaRAMPhyAddr</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *lChObj, unsigned int *paramPhyAddr)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the PaRAM Set Physical Address associated with a logical channel. <a href="#gac1155de8f396305d8e23da2bb81cc731"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gafeb4ec75d54a14cd76f4ef9bbfc7c182">EDMA3_RM_getBaseAddress</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga73a8a7c45f838fa372757dca388c8a4f">EDMA3_RM_Cntrlr_PhyAddr</a> controllerId, unsigned int *phyAddress)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the Channel Controller or Transfer Controller (n) Physical Address. <a href="#gafeb4ec75d54a14cd76f4ef9bbfc7c182"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gabe844cd7d2e2c907ff3ffd0dabd4efaa">EDMA3_RM_getGblConfigParams</a> (unsigned int phyCtrllerInstId, <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html">EDMA3_RM_GblConfigParams</a> *gblCfgParams)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the SoC specific configuration structure for the EDMA3 Hardware. <a href="#gabe844cd7d2e2c907ff3ffd0dabd4efaa"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga633e97bd8ee118260938f8e1de0af112">EDMA3_RM_getPaRAMPhyAddr</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *lChObj, uint32_t *paramPhyAddr)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the PaRAM Set Physical Address associated with a logical channel. <a href="#ga633e97bd8ee118260938f8e1de0af112"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga57819bbb04ee04fbc836919dc46934fa">EDMA3_RM_getBaseAddress</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga73a8a7c45f838fa372757dca388c8a4f">EDMA3_RM_Cntrlr_PhyAddr</a> controllerId, uint32_t *phyAddress)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the Channel Controller or Transfer Controller (n) Physical Address. <a href="#ga57819bbb04ee04fbc836919dc46934fa"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga3425ab19139bc4cc0f0383b4a881e3a8">EDMA3_RM_getGblConfigParams</a> (uint32_t phyCtrllerInstId, <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html">EDMA3_RM_GblConfigParams</a> *gblCfgParams)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the SoC specific configuration structure for the EDMA3 Hardware. <a href="#ga3425ab19139bc4cc0f0383b4a881e3a8"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gac3035b42aa8cbb53603cbcdc6e6ca5b8">EDMA3_RM_getInstanceInitCfg</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html">EDMA3_RM_InstanceInitConfig</a> *instanceInitConfig)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc). <a href="#gac3035b42aa8cbb53603cbcdc6e6ca5b8"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaf0e5b30b8e1d058499bcf088847484c5">EDMA3_RM_Ioctl</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga009c5aa71d396e2d6b84426709a8da7e">EDMA3_RM_IoctlCmd</a> cmd, void *cmdArg, void *param)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 Resource Manager IOCTL. <a href="#gaf0e5b30b8e1d058499bcf088847484c5"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gabc273aa6aa42d3ffcaedc0856e921c92">EDMA3_RM_initXbarEventMap</a> (EDMA3_RM_Handle hEdma, const <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html">EDMA3_RM_GblXbarToChanConfigParams</a> *edmaGblXbarConfig, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga373c55dba0c349454ce9be1a625ad17f">EDMA3_RM_mapXbarEvtToChan</a> mapXbarEvtFunc, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga07f4c95a3095e6f0b25d34931312b315">EDMA3_RM_xbarConfigScr</a> configXbarScr)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gabc273aa6aa42d3ffcaedc0856e921c92">EDMA3_RM_initXbarEventMap</a> (EDMA3_RM_Handle hEdma, const <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html">EDMA3_RM_GblXbarToChanConfigParams</a> *edmaGblXbarConfig, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa3446e78614a94f6a90723f79888fd33">EDMA3_RM_mapXbarEvtToChan</a> mapXbarEvtFunc, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1e994f8dbd5632fa1ed4930dad03593f">EDMA3_RM_xbarConfigScr</a> configXbarScr)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Initialize the cross bar mapped event to channel function. <a href="#gabc273aa6aa42d3ffcaedc0856e921c92"></a><br/></td></tr>
</table>
<hr/><h2>Typedef Documentation</h2>
-<a class="anchor" id="ga373c55dba0c349454ce9be1a625ad17f"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_mapXbarEvtToChan" ref="ga373c55dba0c349454ce9be1a625ad17f" args=")(unsigned int eventNum, unsigned int *chanNum, const EDMA3_RM_GblXbarToChanConfigParams *edmaGblXbarConfig)" -->
+<a class="anchor" id="gaa3446e78614a94f6a90723f79888fd33"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_mapXbarEvtToChan" ref="gaa3446e78614a94f6a90723f79888fd33" args=")(uint32_t eventNum, uint32_t *chanNum, const EDMA3_RM_GblXbarToChanConfigParams *edmaGblXbarConfig)" -->
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- <td class="memname">typedef EDMA3_RM_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga373c55dba0c349454ce9be1a625ad17f">EDMA3_RM_mapXbarEvtToChan</a>)(unsigned int eventNum, unsigned int *chanNum, const <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html">EDMA3_RM_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td>
+ <td class="memname">typedef EDMA3_RM_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa3446e78614a94f6a90723f79888fd33">EDMA3_RM_mapXbarEvtToChan</a>)(uint32_t eventNum, uint32_t *chanNum, const <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html">EDMA3_RM_GblXbarToChanConfigParams</a> *edmaGblXbarConfig)</td>
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-<a class="anchor" id="ga07f4c95a3095e6f0b25d34931312b315"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_xbarConfigScr" ref="ga07f4c95a3095e6f0b25d34931312b315" args=")(unsigned int eventNum, unsigned int chanNum)" -->
+<a class="anchor" id="ga1e994f8dbd5632fa1ed4930dad03593f"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_xbarConfigScr" ref="ga1e994f8dbd5632fa1ed4930dad03593f" args=")(uint32_t eventNum, uint32_t chanNum)" -->
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- <td class="memname">typedef EDMA3_RM_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga07f4c95a3095e6f0b25d34931312b315">EDMA3_RM_xbarConfigScr</a>)(unsigned int eventNum, unsigned int chanNum)</td>
+ <td class="memname">typedef EDMA3_RM_Result(* <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1e994f8dbd5632fa1ed4930dad03593f">EDMA3_RM_xbarConfigScr</a>)(uint32_t eventNum, uint32_t chanNum)</td>
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</div>
<hr/><h2>Function Documentation</h2>
-<a class="anchor" id="ga4ac58bd9d22200f51216887576f77d32"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_allocLogicalChannel" ref="ga4ac58bd9d22200f51216887576f77d32" args="(EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, unsigned int *pParam, unsigned int *pTcc)" -->
+<a class="anchor" id="ga349e5d31b0ff155b6d1a4052396f8dd5"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_allocLogicalChannel" ref="ga349e5d31b0ff155b6d1a4052396f8dd5" args="(EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, uint32_t *pParam, uint32_t *pTcc)" -->
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- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>pParam</em>, </td>
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>pTcc</em></td><td> </td>
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-<a class="anchor" id="gac921ebbbe2c23fb5b55d6822d8731b90"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_mapEdmaChannel" ref="gac921ebbbe2c23fb5b55d6822d8731b90" args="(EDMA3_RM_Handle hEdmaResMgr, unsigned int channelId, unsigned int paRAMId)" -->
+<a class="anchor" id="gad0690a3a5317d4d928b1d968e61ac796"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_mapEdmaChannel" ref="gad0690a3a5317d4d928b1d968e61ac796" args="(EDMA3_RM_Handle hEdmaResMgr, uint32_t channelId, uint32_t paRAMId)" -->
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- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>channelId</em>, </td>
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>paRAMId</em></td><td> </td>
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-<a class="anchor" id="ga9ed44bdab3967bbad7d4edddadde819f"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_mapQdmaChannel" ref="ga9ed44bdab3967bbad7d4edddadde819f" args="(EDMA3_RM_Handle hEdmaResMgr, unsigned int channelId, unsigned int paRAMId, EDMA3_RM_QdmaTrigWord trigWord)" -->
+<a class="anchor" id="ga0b893408e1d61aff5662f76ea9aac6b9"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_mapQdmaChannel" ref="ga0b893408e1d61aff5662f76ea9aac6b9" args="(EDMA3_RM_Handle hEdmaResMgr, uint32_t channelId, uint32_t paRAMId, EDMA3_RM_QdmaTrigWord trigWord)" -->
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<td class="paramkey"></td>
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- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>channelId</em>, </td>
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>paRAMId</em>, </td>
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-<a class="anchor" id="ga1c222a9feda9024cf4e28ba897b5c285"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_setCCRegister" ref="ga1c222a9feda9024cf4e28ba897b5c285" args="(EDMA3_RM_Handle hEdmaResMgr, unsigned int regOffset, unsigned int newRegValue)" -->
+<a class="anchor" id="ga3c1f70a6659baae70acd0bd5e05ce42c"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_setCCRegister" ref="ga3c1f70a6659baae70acd0bd5e05ce42c" args="(EDMA3_RM_Handle hEdmaResMgr, uint32_t regOffset, uint32_t newRegValue)" -->
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- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>regOffset</em>, </td>
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>newRegValue</em></td><td> </td>
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-<a class="anchor" id="gaea15b18d6ef5224fe0e4a1beadc6d1ee"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_getCCRegister" ref="gaea15b18d6ef5224fe0e4a1beadc6d1ee" args="(EDMA3_RM_Handle hEdmaResMgr, unsigned int regOffset, unsigned int *regValue)" -->
+<a class="anchor" id="ga508e7ab10ea4d68b7d52777128523123"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_getCCRegister" ref="ga508e7ab10ea4d68b7d52777128523123" args="(EDMA3_RM_Handle hEdmaResMgr, uint32_t regOffset, uint32_t *regValue)" -->
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+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>regOffset</em>, </td>
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>regValue</em></td><td> </td>
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-<a class="anchor" id="gac9a6d0bd72ba4476c30b2898e407888e"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_waitAndClearTcc" ref="gac9a6d0bd72ba4476c30b2898e407888e" args="(EDMA3_RM_Handle hEdmaResMgr, unsigned int tccNo)" -->
+<a class="anchor" id="ga03eb291d9e4f05e66f304e0e1c09e795"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_waitAndClearTcc" ref="ga03eb291d9e4f05e66f304e0e1c09e795" args="(EDMA3_RM_Handle hEdmaResMgr, uint32_t tccNo)" -->
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- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>tccNo</em></td><td> </td>
</tr>
<tr>
</div>
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-<a class="anchor" id="ga0ebe052bd9f612942908236bc96c54b4"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_checkAndClearTcc" ref="ga0ebe052bd9f612942908236bc96c54b4" args="(EDMA3_RM_Handle hEdmaResMgr, unsigned int tccNo, unsigned short *tccStatus)" -->
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- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>tccNo</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned short * </td>
+ <td class="paramtype">uint16_t * </td>
<td class="paramname"> <em>tccStatus</em></td><td> </td>
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<tr>
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-<a class="anchor" id="gac1155de8f396305d8e23da2bb81cc731"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_getPaRAMPhyAddr" ref="gac1155de8f396305d8e23da2bb81cc731" args="(EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, unsigned int *paramPhyAddr)" -->
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- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>paramPhyAddr</em></td><td> </td>
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-<a class="anchor" id="gafeb4ec75d54a14cd76f4ef9bbfc7c182"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_getBaseAddress" ref="gafeb4ec75d54a14cd76f4ef9bbfc7c182" args="(EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_Cntrlr_PhyAddr controllerId, unsigned int *phyAddress)" -->
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- <td class="paramtype">unsigned int * </td>
+ <td class="paramtype">uint32_t * </td>
<td class="paramname"> <em>phyAddress</em></td><td> </td>
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-<a class="anchor" id="gabe844cd7d2e2c907ff3ffd0dabd4efaa"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_getGblConfigParams" ref="gabe844cd7d2e2c907ff3ffd0dabd4efaa" args="(unsigned int phyCtrllerInstId, EDMA3_RM_GblConfigParams *gblCfgParams)" -->
+<a class="anchor" id="ga3425ab19139bc4cc0f0383b4a881e3a8"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_getGblConfigParams" ref="ga3425ab19139bc4cc0f0383b4a881e3a8" args="(uint32_t phyCtrllerInstId, EDMA3_RM_GblConfigParams *gblCfgParams)" -->
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<td class="memname">EDMA3_RM_Result EDMA3_RM_getGblConfigParams </td>
<td>(</td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>phyCtrllerInstId</em>, </td>
</tr>
<tr>
<div class="memdoc">
<p>Get the SoC specific configuration structure for the EDMA3 Hardware. </p>
-<p>This API is used to fetch the global SoC specific configuration structure for the EDMA3 Hardware. It is useful for the user who has not passed this information during <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#gadc4459024208af43ca53740f5f0e24f2" title="Create EDMA3 Resource Manager Object.">EDMA3_RM_create()</a> and taken the default configuration coming along with the package.</p>
+<p>This API is used to fetch the global SoC specific configuration structure for the EDMA3 Hardware. It is useful for the user who has not passed this information during <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#ga4ed822e8a60e9cc0d6c894f98ff2ae86" title="Create EDMA3 Resource Manager Object.">EDMA3_RM_create()</a> and taken the default configuration coming along with the package.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>phyCtrllerInstId</em> </td><td>[IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0). </td></tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga373c55dba0c349454ce9be1a625ad17f">EDMA3_RM_mapXbarEvtToChan</a> </td>
+ <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa3446e78614a94f6a90723f79888fd33">EDMA3_RM_mapXbarEvtToChan</a> </td>
<td class="paramname"> <em>mapXbarEvtFunc</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga07f4c95a3095e6f0b25d34931312b315">EDMA3_RM_xbarConfigScr</a> </td>
+ <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1e994f8dbd5632fa1ed4930dad03593f">EDMA3_RM_xbarConfigScr</a> </td>
<td class="paramname"> <em>configXbarScr</em></td><td> </td>
</tr>
<tr>
</div>
</div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:50 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html
index 75dbcb5224b45ebf7ad52fc883ed872a8bd4b04a..76e594ae83f1745f07aef90d41335e359ad93be1 100755 (executable)
--- a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html
+++ b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html
[<a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n.html">EDMA3 Resource Manager APIs</a>]</small>
</h1><table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Functions</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gad57281a3cabf45b1520007a1a78f6a53">EDMA3_RM_registerTccCb</a> (EDMA3_RM_Handle hEdmaResMgr, const <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *channelObj, unsigned int tcc, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#gaadca81927be74261ef874009bf8e37d3">EDMA3_RM_TccCallback</a> tccCb, void *cbData)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Registers a transfer completion handler for a specific DMA/QDMA channel. <a href="#gad57281a3cabf45b1520007a1a78f6a53"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaee10da91383b091d07e2fb193e830d3c">EDMA3_RM_registerTccCb</a> (EDMA3_RM_Handle hEdmaResMgr, const <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *channelObj, uint32_t tcc, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga3d1093c590b221a5d7b24dbb9bba58d1">EDMA3_RM_TccCallback</a> tccCb, void *cbData)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Registers a transfer completion handler for a specific DMA/QDMA channel. <a href="#gaee10da91383b091d07e2fb193e830d3c"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga34a841202d01ea2e2a35747aa873a984">EDMA3_RM_unregisterTccCb</a> (EDMA3_RM_Handle hEdmaResMgr, const <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *channelObj)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Unregister the previously registered callback function against a DMA/QDMA channel. <a href="#ga34a841202d01ea2e2a35747aa873a984"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaa8d149c517bb15b5539f22f497327775">EDMA3_RM_allocResource</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *resObj)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. <a href="#gaa8d149c517bb15b5539f22f497327775"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga2ba87def618a4bdd08b01f8e89ef1e9d">EDMA3_RM_freeResource</a> (EDMA3_RM_Handle hEdmaResMgr, const <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *resObj)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC. <a href="#ga2ba87def618a4bdd08b01f8e89ef1e9d"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga91a8cc9b909db61a200572ace81a22f3">EDMA3_RM_allocContiguousResource</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *firstResIdObj, unsigned int numResources)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC. <a href="#ga91a8cc9b909db61a200572ace81a22f3"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga787f3fe9f08e7c0105e56ad1171cabca">EDMA3_RM_freeContiguousResource</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *firstResIdObj, unsigned int numResources)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated. <a href="#ga787f3fe9f08e7c0105e56ad1171cabca"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga758a8843e88d474dc8d84fc3a3c69afc">EDMA3_RM_allocContiguousResource</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *firstResIdObj, uint32_t numResources)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC. <a href="#ga758a8843e88d474dc8d84fc3a3c69afc"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#ga310958afd9925c16e72004dafdbc3ad4">EDMA3_RM_freeContiguousResource</a> (EDMA3_RM_Handle hEdmaResMgr, <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html">EDMA3_RM_ResDesc</a> *firstResIdObj, uint32_t numResources)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated. <a href="#ga310958afd9925c16e72004dafdbc3ad4"></a><br/></td></tr>
</table>
<hr/><h2>Function Documentation</h2>
-<a class="anchor" id="gad57281a3cabf45b1520007a1a78f6a53"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_registerTccCb" ref="gad57281a3cabf45b1520007a1a78f6a53" args="(EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj, unsigned int tcc, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
+<a class="anchor" id="gaee10da91383b091d07e2fb193e830d3c"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_registerTccCb" ref="gaee10da91383b091d07e2fb193e830d3c" args="(EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj, uint32_t tcc, EDMA3_RM_TccCallback tccCb, void *cbData)" -->
<div class="memitem">
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<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>tcc</em>, </td>
</tr>
<tr>
<td class="paramkey"></td>
<td></td>
- <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#gaadca81927be74261ef874009bf8e37d3">EDMA3_RM_TccCallback</a> </td>
+ <td class="paramtype"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga3d1093c590b221a5d7b24dbb9bba58d1">EDMA3_RM_TccCallback</a> </td>
<td class="paramname"> <em>tccCb</em>, </td>
</tr>
<tr>
<p>ANY types of resources are those resources when user doesn't care about the actual resource allocated; user just wants a resource of the type specified. One use-case is to perform memory-to-memory data transfer operation. This operation can be performed using any available DMA or QDMA channel. User doesn't need any specific channel for the same.</p>
<p>To allocate a specific resource, first this API checks whether that resource is OWNED by the Resource Manager instance. Then it checks the current availability of that resource.</p>
<p>To allocate ANY available resource, this API tries to allocate a resource from the pool of (owned && non_reserved && available_right_now) resources.</p>
-<p>After allocating a DMA/QDMA channel, the same resource is enabled in the shadow region specific register (DRAE/DRAEH/QRAE). DRAE/DRAEH register for a TCC is updated only when user registers a callback function against that TCC using <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gad57281a3cabf45b1520007a1a78f6a53" title="Registers a transfer completion handler for a specific DMA/QDMA channel.">EDMA3_RM_registerTccCb()</a>.</p>
+<p>After allocating a DMA/QDMA channel, the same resource is enabled in the shadow region specific register (DRAE/DRAEH/QRAE). DRAE/DRAEH register for a TCC is updated only when user registers a callback function against that TCC using <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaee10da91383b091d07e2fb193e830d3c" title="Registers a transfer completion handler for a specific DMA/QDMA channel.">EDMA3_RM_registerTccCb()</a>.</p>
<p>Allocated PaRAM Set is initialized to NULL before this API returns if user has requested for one.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
</div>
</div>
-<a class="anchor" id="ga91a8cc9b909db61a200572ace81a22f3"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_allocContiguousResource" ref="ga91a8cc9b909db61a200572ace81a22f3" args="(EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, unsigned int numResources)" -->
+<a class="anchor" id="ga758a8843e88d474dc8d84fc3a3c69afc"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_allocContiguousResource" ref="ga758a8843e88d474dc8d84fc3a3c69afc" args="(EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, uint32_t numResources)" -->
<div class="memitem">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>numResources</em></td><td> </td>
</tr>
<tr>
<p>ANY types of resources are those resources when user doesn't care about the actual resource allocated; user just wants a resource of the type specified. One use-case is to perform memory-to-memory data transfer operation. This operation can be performed using any available DMA or QDMA channel. User doesn't need any specific channel for the same.</p>
<p>To allocate specific contiguous resources, first this API checks whether those requested resources are OWNED by the Resource Manager instance. Then it checks the current availability of those resources.</p>
<p>To allocate ANY available contiguous resources, this API tries to allocate resources from the pool of (owned && non_reserved && available_right_now) resources.</p>
-<p>After allocating DMA/QDMA channels, the same resources are enabled in the shadow region specific register (DRAE/DRAEH/QRAE). DRAE/DRAEH register for a TCC is updated only when user registers a callback function against that TCC using <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gad57281a3cabf45b1520007a1a78f6a53" title="Registers a transfer completion handler for a specific DMA/QDMA channel.">EDMA3_RM_registerTccCb()</a>. Allocated PaRAM Sets are initialized to NULL before this API returns.</p>
+<p>After allocating DMA/QDMA channels, the same resources are enabled in the shadow region specific register (DRAE/DRAEH/QRAE). DRAE/DRAEH register for a TCC is updated only when user registers a callback function against that TCC using <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___b_a_s_i_c.html#gaee10da91383b091d07e2fb193e830d3c" title="Registers a transfer completion handler for a specific DMA/QDMA channel.">EDMA3_RM_registerTccCb()</a>. Allocated PaRAM Sets are initialized to NULL before this API returns.</p>
<dl><dt><b>Parameters:</b></dt><dd>
<table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"></td><td valign="top"><em>hEdmaResMgr</em> </td><td>[IN] Handle to the previously opened Resource Manager Instance. </td></tr>
</div>
</div>
-<a class="anchor" id="ga787f3fe9f08e7c0105e56ad1171cabca"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_freeContiguousResource" ref="ga787f3fe9f08e7c0105e56ad1171cabca" args="(EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, unsigned int numResources)" -->
+<a class="anchor" id="ga310958afd9925c16e72004dafdbc3ad4"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_freeContiguousResource" ref="ga310958afd9925c16e72004dafdbc3ad4" args="(EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, uint32_t numResources)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
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<td class="paramkey"></td>
<td></td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>numResources</em></td><td> </td>
</tr>
<tr>
</div>
</div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:50 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html
index ff7c9506611779ed552f1ab53e022ba97ee288bf..0fb61818b7021e3957d6f64d2308225603fd47d0 100755 (executable)
--- a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html
+++ b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html
[<a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n.html">EDMA3 Resource Manager APIs</a>]</small>
</h1><table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Functions</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#gadc4459024208af43ca53740f5f0e24f2">EDMA3_RM_create</a> (unsigned int phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html">EDMA3_RM_GblConfigParams</a> *gblCfgParams, const void *miscParam)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Create EDMA3 Resource Manager Object. <a href="#gadc4459024208af43ca53740f5f0e24f2"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#ga91cc5101fd09c700b6d2a2e72baf88fe">EDMA3_RM_delete</a> (unsigned int phyCtrllerInstId, const void *param)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Delete EDMA3 Resource Manager Object. <a href="#ga91cc5101fd09c700b6d2a2e72baf88fe"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Handle </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#ga06b18003d700ce3c227f70e422dd9897">EDMA3_RM_open</a> (unsigned int phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___r_m___param.html">EDMA3_RM_Param</a> *initParam, EDMA3_RM_Result *errorCode)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Open EDMA3 Resource Manager Instance. <a href="#ga06b18003d700ce3c227f70e422dd9897"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#ga4ed822e8a60e9cc0d6c894f98ff2ae86">EDMA3_RM_create</a> (uint32_t phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html">EDMA3_RM_GblConfigParams</a> *gblCfgParams, const void *miscParam)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Create EDMA3 Resource Manager Object. <a href="#ga4ed822e8a60e9cc0d6c894f98ff2ae86"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#gac752b26df1a9ee0ceccdb600cfe06ac2">EDMA3_RM_delete</a> (uint32_t phyCtrllerInstId, const void *param)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Delete EDMA3 Resource Manager Object. <a href="#gac752b26df1a9ee0ceccdb600cfe06ac2"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Handle </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#ga5b4cf0dbda9250f6e3e63e80733e31c0">EDMA3_RM_open</a> (uint32_t phyCtrllerInstId, const <a class="el" href="struct_e_d_m_a3___r_m___param.html">EDMA3_RM_Param</a> *initParam, EDMA3_RM_Result *errorCode)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Open EDMA3 Resource Manager Instance. <a href="#ga5b4cf0dbda9250f6e3e63e80733e31c0"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">EDMA3_RM_Result </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#ga92776ae6a8795fe8ffce672e8a04e409">EDMA3_RM_close</a> (EDMA3_RM_Handle hEdmaResMgr, const void *param)</td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Close EDMA3 Resource Manager Instance. <a href="#ga92776ae6a8795fe8ffce672e8a04e409"></a><br/></td></tr>
</table>
<hr/><h2>Function Documentation</h2>
-<a class="anchor" id="gadc4459024208af43ca53740f5f0e24f2"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_create" ref="gadc4459024208af43ca53740f5f0e24f2" args="(unsigned int phyCtrllerInstId, const EDMA3_RM_GblConfigParams *gblCfgParams, const void *miscParam)" -->
+<a class="anchor" id="ga4ed822e8a60e9cc0d6c894f98ff2ae86"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_create" ref="ga4ed822e8a60e9cc0d6c894f98ff2ae86" args="(uint32_t phyCtrllerInstId, const EDMA3_RM_GblConfigParams *gblCfgParams, const void *miscParam)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">EDMA3_RM_Result EDMA3_RM_create </td>
<td>(</td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>phyCtrllerInstId</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga91cc5101fd09c700b6d2a2e72baf88fe"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_delete" ref="ga91cc5101fd09c700b6d2a2e72baf88fe" args="(unsigned int phyCtrllerInstId, const void *param)" -->
+<a class="anchor" id="gac752b26df1a9ee0ceccdb600cfe06ac2"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_delete" ref="gac752b26df1a9ee0ceccdb600cfe06ac2" args="(uint32_t phyCtrllerInstId, const void *param)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">EDMA3_RM_Result EDMA3_RM_delete </td>
<td>(</td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>phyCtrllerInstId</em>, </td>
</tr>
<tr>
</div>
</div>
-<a class="anchor" id="ga06b18003d700ce3c227f70e422dd9897"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_open" ref="ga06b18003d700ce3c227f70e422dd9897" args="(unsigned int phyCtrllerInstId, const EDMA3_RM_Param *initParam, EDMA3_RM_Result *errorCode)" -->
+<a class="anchor" id="ga5b4cf0dbda9250f6e3e63e80733e31c0"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_open" ref="ga5b4cf0dbda9250f6e3e63e80733e31c0" args="(uint32_t phyCtrllerInstId, const EDMA3_RM_Param *initParam, EDMA3_RM_Result *errorCode)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
<td class="memname">EDMA3_RM_Handle EDMA3_RM_open </td>
<td>(</td>
- <td class="paramtype">unsigned int </td>
+ <td class="paramtype">uint32_t </td>
<td class="paramname"> <em>phyCtrllerInstId</em>, </td>
</tr>
<tr>
</div>
</div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:50 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l.html b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l.html
index 787cf078652ddd884ee8737cd546b0152ae232b1..cfd0efab7cf64886fdb28dbcbada1298ddd833f4 100755 (executable)
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Include common header file </p>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:49 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___d_e_f_i_n_e.html b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___d_e_f_i_n_e.html
index 48c0054b92a5892853ce36d73653748bd220a61c..16120039ea1eddef5357447f2983f238bef8824a 100755 (executable)
--- a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___d_e_f_i_n_e.html
+++ b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___d_e_f_i_n_e.html
<tr><td colspan="2"><h2>Defines</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2bc56ec70e329a97072891f90ed78bf9"></a><!-- doxytag: member="EDMA3_LLD_RM_SYMBOL_DEFINE::EDMA3_RM_RES_ANY" ref="ga2bc56ec70e329a97072891f90ed78bf9" args="" -->
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___d_e_f_i_n_e.html#ga2bc56ec70e329a97072891f90ed78bf9">EDMA3_RM_RES_ANY</a> (1010u)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Used to specify any available Resource Id (<a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a8fffc8bd17e838ce866a225ffe14ce02">EDMA3_RM_ResDesc.resId</a>). <br/></td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Used to specify any available Resource Id (<a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a7a3b79d5f21a9a6d4af2e47edc905b69">EDMA3_RM_ResDesc.resId</a>). <br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___d_e_f_i_n_e.html#gab014f5a62cb4f050873d3836cc189ca7">EDMA3_RM_E_BASE</a> (-155)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___d_e_f_i_n_e.html#ga9b69fe3203335237b365833e70d49ff8">EDMA3_RM_E_OBJ_NOT_DELETED</a> (EDMA3_RM_E_BASE)</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___d_e_f_i_n_e.html#gaaf4a8d35e9b2acedc8962b56e02a776f">EDMA3_RM_E_OBJ_NOT_CLOSED</a> (EDMA3_RM_E_BASE-1)</td></tr>
</table>
</div>
<div class="memdoc">
-<p>Used to specify any available QDMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga4ac58bd9d22200f51216887576f77d32" title="Request a DMA/QDMA/Link channel.">EDMA3_RM_allocLogicalChannel()</a>. QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned. </p>
+<p>Used to specify any available QDMA Channel while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga349e5d31b0ff155b6d1a4052396f8dd5" title="Request a DMA/QDMA/Link channel.">EDMA3_RM_allocLogicalChannel()</a>. QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned. </p>
</div>
</div>
</table>
</div>
<div class="memdoc">
-<p>Used to specify any available TCC while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga4ac58bd9d22200f51216887576f77d32" title="Request a DMA/QDMA/Link channel.">EDMA3_RM_allocLogicalChannel()</a>, for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned. </p>
+<p>Used to specify any available TCC while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga349e5d31b0ff155b6d1a4052396f8dd5" title="Request a DMA/QDMA/Link channel.">EDMA3_RM_allocLogicalChannel()</a>, for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned. </p>
</div>
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</table>
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<div class="memdoc">
-<p>Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga4ac58bd9d22200f51216887576f77d32" title="Request a DMA/QDMA/Link channel.">EDMA3_RM_allocLogicalChannel()</a>, for both DMA/QDMA and Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. </p>
+<p>Used to specify any available PaRAM Set while requesting one. Used in the API <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga349e5d31b0ff155b6d1a4052396f8dd5" title="Request a DMA/QDMA/Link channel.">EDMA3_RM_allocLogicalChannel()</a>, for both DMA/QDMA and Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned. </p>
</div>
</div>
</div>
</div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:49 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html
index a9d6dbfe25947a78a0a347f9ad40425b9995e552..1082b59bb30c6c30d95e963389dd78379b260845 100755 (executable)
--- a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html
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<p>This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer. </p>
<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"><em><a class="anchor" id="gga16a012f757d48bd975b8ea0c971be3aba67c32e3e11c96cc049c518a59f032a70"></a><!-- doxytag: member="EDMA3_RM_E_CC_QUE_THRES_EXCEED" ref="gga16a012f757d48bd975b8ea0c971be3aba67c32e3e11c96cc049c518a59f032a70" args="" -->EDMA3_RM_E_CC_QUE_THRES_EXCEED</em> </td><td>
-<p>Threshold exceed:- for all event queues. These get latched in EDMA3CC error register (CCERR). This error has a direct relation with the setting of <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ae633ff54dda219dafc5d3b609a28a202" title="Event Queues Watermark Levels.">EDMA3_RM_GblConfigParams.evtQueueWaterMarkLvl</a> </p>
+<p>Threshold exceed:- for all event queues. These get latched in EDMA3CC error register (CCERR). This error has a direct relation with the setting of <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af8f66e50d0fd61272e332fa69c437612" title="Event Queues Watermark Levels.">EDMA3_RM_GblConfigParams.evtQueueWaterMarkLvl</a> </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="gga16a012f757d48bd975b8ea0c971be3aba15eeafe3ddc875b7571a98e9c884222d"></a><!-- doxytag: member="EDMA3_RM_E_CC_TCC" ref="gga16a012f757d48bd975b8ea0c971be3aba15eeafe3ddc875b7571a98e9c884222d" args="" -->EDMA3_RM_E_CC_TCC</em> </td><td>
<p>TCC error:- for outstanding transfer requests expected to return completion code (TCCHEN or TCINTEN bit in OPT is set to 1) exceeding the maximum limit of 63. This also gets latched in the CCERR. </p>
<div class="memdoc">
<p>QDMA Trigger Word. </p>
-<p>Use this enum to set the QDMA trigger word to any of the 8 DWords(unsigned int) within a Parameter RAM set </p>
+<p>Use this enum to set the QDMA trigger word to any of the 8 DWords(uint32_t) within a Parameter RAM set </p>
<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"><em><a class="anchor" id="ggacabe6aeb4a0ce496671777e783cdb2c4a04d3b9e93a0257fe8273ab578b661a5c"></a><!-- doxytag: member="EDMA3_RM_QDMA_TRIG_OPT" ref="ggacabe6aeb4a0ce496671777e783cdb2c4a04d3b9e93a0257fe8273ab578b661a5c" args="" -->EDMA3_RM_QDMA_TRIG_OPT</em> </td><td>
<p>Set the OPT field (Offset Address 0h Bytes) as the QDMA trigger word </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="gga009c5aa71d396e2d6b84426709a8da7eae030b74d933852aeec16cce9fa6f2a93"></a><!-- doxytag: member="EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION" ref="gga009c5aa71d396e2d6b84426709a8da7eae030b74d933852aeec16cce9fa6f2a93" args="" -->EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION</em> </td><td>
<p>To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation.</p>
-<p>For e.g., unsigned int *isParamClearingDone = (unsigned int *)cmdArg; (*isParamClearingDone) = paramClearingRequired; </p>
+<p>For e.g., uint32_t *isParamClearingDone = (uint32_t *)cmdArg; (*isParamClearingDone) = paramClearingRequired; </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="gga009c5aa71d396e2d6b84426709a8da7ea746e145f594c91c85f7e85baf68c8adb"></a><!-- doxytag: member="EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION" ref="gga009c5aa71d396e2d6b84426709a8da7ea746e145f594c91c85f7e85baf68c8adb" args="" -->EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION</em> </td><td>
<p>Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be modified OR will not be modified during EDMA3_RM_allocLogicalChannel (), depending upon this option.</p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="gga009c5aa71d396e2d6b84426709a8da7ea499e21c8201b7cde74b51ae9d05bac46"></a><!-- doxytag: member="EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION" ref="gga009c5aa71d396e2d6b84426709a8da7ea499e21c8201b7cde74b51ae9d05bac46" args="" -->EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION</em> </td><td>
<p>To check whether Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed or not during allocation (EDMA3_RM_allocLogicalChannel ()). If the value read is '1', it means that the registers/PaRAMs are getting programmed during allocation. If the value read is '0', it means that the registers/PaRAMs are NOT getting programmed during allocation.</p>
-<p>For e.g., unsigned int *isParamClearingDone = (unsigned int *)cmdArg; (*isParamClearingDone) = paramClearingRequired; </p>
+<p>For e.g., uint32_t *isParamClearingDone = (uint32_t *)cmdArg; (*isParamClearingDone) = paramClearingRequired; </p>
</td></tr>
</table>
</dd>
</div>
</div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:49 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html
index e3e074eb44a98d27be56b4768f1aa4c4dd2a8ace..166d2b02df6e354fc8453f28a2cced94787ed425 100755 (executable)
--- a/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html
+++ b/packages/ti/sdo/edma3/rm/docs/html/group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html
[<a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l.html">EDMA3 Resource Manager Symbols</a>]</small>
</h1><table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Typedefs</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga6768147ae320fd3951df6762133d2ede">EDMA3_RM_GblErrCallback</a> )(<a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga16a012f757d48bd975b8ea0c971be3ab">EDMA3_RM_GlobalError</a> deviceStatus, unsigned int instanceId, void *gblerrData)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Global Error callback - caters to module events like bus error etc which are not channel specific. Runs in ISR context. <a href="#ga6768147ae320fd3951df6762133d2ede"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#gaadca81927be74261ef874009bf8e37d3">EDMA3_RM_TccCallback</a> )(unsigned int tcc, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga6552b0f8faaf17b884686da3bdcb955f">EDMA3_RM_TccStatus</a> status, void *appData)</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">TCC callback - caters to channel-specific events like "Event Miss Error" or "Transfer Complete". Runs in ISR context. <a href="#gaadca81927be74261ef874009bf8e37d3"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">typedef unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga95ce8c6a9989cc4bbd29e0234e6ee5e4">EDMA3_RM_RegionId</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#gaa0dbaf46ef2ab3f68257e8ed26c643fd">EDMA3_RM_GblErrCallback</a> )(<a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga16a012f757d48bd975b8ea0c971be3ab">EDMA3_RM_GlobalError</a> deviceStatus, uint32_t instanceId, void *gblerrData)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Global Error callback - caters to module events like bus error etc which are not channel specific. Runs in ISR context. <a href="#gaa0dbaf46ef2ab3f68257e8ed26c643fd"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga3d1093c590b221a5d7b24dbb9bba58d1">EDMA3_RM_TccCallback</a> )(uint32_t tcc, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga6552b0f8faaf17b884686da3bdcb955f">EDMA3_RM_TccStatus</a> status, void *appData)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">TCC callback - caters to channel-specific events like "Event Miss Error" or "Transfer Complete". Runs in ISR context. <a href="#ga3d1093c590b221a5d7b24dbb9bba58d1"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga95ce8c6a9989cc4bbd29e0234e6ee5e4">EDMA3_RM_RegionId</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 Region Id. <a href="#ga95ce8c6a9989cc4bbd29e0234e6ee5e4"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">typedef unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga73da34ea04a5d4c536919febc341ff2a">EDMA3_RM_EventQueue</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga73da34ea04a5d4c536919febc341ff2a">EDMA3_RM_EventQueue</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 Event Queue assignment. <a href="#ga73da34ea04a5d4c536919febc341ff2a"></a><br/></td></tr>
</table>
<hr/><h2>Typedef Documentation</h2>
-<a class="anchor" id="ga6768147ae320fd3951df6762133d2ede"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_GblErrCallback" ref="ga6768147ae320fd3951df6762133d2ede" args=")(EDMA3_RM_GlobalError deviceStatus, unsigned int instanceId, void *gblerrData)" -->
+<a class="anchor" id="gaa0dbaf46ef2ab3f68257e8ed26c643fd"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_GblErrCallback" ref="gaa0dbaf46ef2ab3f68257e8ed26c643fd" args=")(EDMA3_RM_GlobalError deviceStatus, uint32_t instanceId, void *gblerrData)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">typedef void(* <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga6768147ae320fd3951df6762133d2ede">EDMA3_RM_GblErrCallback</a>)(<a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga16a012f757d48bd975b8ea0c971be3ab">EDMA3_RM_GlobalError</a> deviceStatus, unsigned int instanceId, void *gblerrData)</td>
+ <td class="memname">typedef void(* <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#gaa0dbaf46ef2ab3f68257e8ed26c643fd">EDMA3_RM_GblErrCallback</a>)(<a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga16a012f757d48bd975b8ea0c971be3ab">EDMA3_RM_GlobalError</a> deviceStatus, uint32_t instanceId, void *gblerrData)</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="gaadca81927be74261ef874009bf8e37d3"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_TccCallback" ref="gaadca81927be74261ef874009bf8e37d3" args=")(unsigned int tcc, EDMA3_RM_TccStatus status, void *appData)" -->
+<a class="anchor" id="ga3d1093c590b221a5d7b24dbb9bba58d1"></a><!-- doxytag: member="edma3_rm.h::EDMA3_RM_TccCallback" ref="ga3d1093c590b221a5d7b24dbb9bba58d1" args=")(uint32_t tcc, EDMA3_RM_TccStatus status, void *appData)" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">typedef void(* <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#gaadca81927be74261ef874009bf8e37d3">EDMA3_RM_TccCallback</a>)(unsigned int tcc, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga6552b0f8faaf17b884686da3bdcb955f">EDMA3_RM_TccStatus</a> status, void *appData)</td>
+ <td class="memname">typedef void(* <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga3d1093c590b221a5d7b24dbb9bba58d1">EDMA3_RM_TccCallback</a>)(uint32_t tcc, <a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga6552b0f8faaf17b884686da3bdcb955f">EDMA3_RM_TccStatus</a> status, void *appData)</td>
</tr>
</table>
</div>
</div>
</div>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:49 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/index.hhk b/packages/ti/sdo/edma3/rm/docs/html/index.hhk
index 167ca20a1ebac48558a4d201337b3d5550dcccf0..c67c1873bd27fd48589f31a52b7a5cf070704025 100755 (executable)
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-<h1>EDMA3 Resource Manager Documentation</h1><h3>02.11.00 </h3></div>
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<p><code>#include <edma3_rm.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a146c49c83ca4e65a3145d9b15d73571d">numDmaChannels</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a49bb3d33efc585d75c8c18cf26dbf169">numQdmaChannels</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ade09c3f169c87739ab5b5d00101a59ed">numTccs</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a9f66e1878cc69101518f94c5f95ec393">numPaRAMSets</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a152b2623285f14f6013b130fbfdf2ee1">numEvtQueue</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a2469da2ae6f4c3895c1edf6333590b1e">numTcs</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af96ad7a22abe4152c2dbec6ddd793ffb">numRegions</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#adc4e7bfa2cfca03fa38c8baa10b508be">dmaChPaRAMMapExists</a></td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Channel mapping existence. <a href="#adc4e7bfa2cfca03fa38c8baa10b508be"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ac2e3f4494b538c862581895558b37e6f">memProtectionExists</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a90181831a767d1f5e6d796a5eb9a2ed1">numDmaChannels</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afa03f7cd037ca5983017c8c403f82419">numQdmaChannels</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a8a0680e508ad29d759a0370084cbb6c0">numTccs</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af5b2f463d96971ecebc269cc2b3e1e76">numPaRAMSets</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a054dff0f68d9260dd20478042683e400">numEvtQueue</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afbce74bc0f62d807cb436656f418338a">numTcs</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a6b973fc32b6d8f47cb8dd46bb1ba88fd">numRegions</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#aa3fd8314930b636baf770de745c1cacc">dmaChPaRAMMapExists</a></td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Channel mapping existence. <a href="#aa3fd8314930b636baf770de745c1cacc"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a14d7d6cb9ccba0f454616b21cd6a7229">memProtectionExists</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ac37e1efa702856b32e621560d4ddde2d">globalRegs</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a167e1ab12a947d4446ba56f8129ed91d">tcRegs</a> [EDMA3_MAX_TC]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af902e3c9d3d6d54fdc472bf79297c947">xferCompleteInt</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a9154b7f04bfe4b3f3d1071da8ad8b483">ccError</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a72c01f8e87453fc8495371cd44b2dcc4">tcError</a> [EDMA3_MAX_TC]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ad4e9caa9307edbc6832ebe662de1b6f6">evtQPri</a> [EDMA3_MAX_EVT_QUE]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 TC priority setting. <a href="#ad4e9caa9307edbc6832ebe662de1b6f6"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ae633ff54dda219dafc5d3b609a28a202">evtQueueWaterMarkLvl</a> [EDMA3_MAX_EVT_QUE]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Event Queues Watermark Levels. <a href="#ae633ff54dda219dafc5d3b609a28a202"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#add171129e6252b02ba54d5e79cb7ecea">tcDefaultBurstSize</a> [EDMA3_MAX_TC]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Default Burst Size (DBS) of TCs. <a href="#add171129e6252b02ba54d5e79cb7ecea"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afa7ba95cc73b21f640888aab87a66533">dmaChannelPaRAMMap</a> [EDMA3_MAX_DMA_CH]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to PaRAM Sets. <a href="#afa7ba95cc73b21f640888aab87a66533"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ab06c1d88f0efb9c82c963daf8d7ea684">dmaChannelTccMap</a> [EDMA3_MAX_DMA_CH]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to TCCs. <a href="#ab06c1d88f0efb9c82c963daf8d7ea684"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ac75808b1b49e327e540620ff08eb23d7">dmaChannelHwEvtMap</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to Hardware Events. <a href="#ac75808b1b49e327e540620ff08eb23d7"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a04d28c89d332f101383e0db8452154e4">xferCompleteInt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a4f06097909c77f1ed1cbec564ba4d8bb">ccError</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a7bcfe31be2064b8133bbb37044079816">tcError</a> [EDMA3_MAX_TC]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ace6903ed2d8d30d97a4b1a2d51426021">evtQPri</a> [EDMA3_MAX_EVT_QUE]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">EDMA3 TC priority setting. <a href="#ace6903ed2d8d30d97a4b1a2d51426021"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af8f66e50d0fd61272e332fa69c437612">evtQueueWaterMarkLvl</a> [EDMA3_MAX_EVT_QUE]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Event Queues Watermark Levels. <a href="#af8f66e50d0fd61272e332fa69c437612"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#aefb3e813e7cad1cf08f7f4af24f13015">tcDefaultBurstSize</a> [EDMA3_MAX_TC]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Default Burst Size (DBS) of TCs. <a href="#aefb3e813e7cad1cf08f7f4af24f13015"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a6366c59f0006724b2966135e0ea81fef">dmaChannelPaRAMMap</a> [EDMA3_MAX_DMA_CH]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to PaRAM Sets. <a href="#a6366c59f0006724b2966135e0ea81fef"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af409720cb469a021a3624ff4d3e6ded6">dmaChannelTccMap</a> [EDMA3_MAX_DMA_CH]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to TCCs. <a href="#af409720cb469a021a3624ff4d3e6ded6"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afcb2fcb340f13f2e450fac817b255747">dmaChannelHwEvtMap</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to Hardware Events. <a href="#afcb2fcb340f13f2e450fac817b255747"></a><br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. </p>
<p>This configuration structure is used to specify the EDMA3 Resource Manager global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresses of CC global registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 RM Object, using API EDMA3_RM_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a146c49c83ca4e65a3145d9b15d73571d"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::numDmaChannels" ref="a146c49c83ca4e65a3145d9b15d73571d" args="" -->
+<a class="anchor" id="a90181831a767d1f5e6d796a5eb9a2ed1"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::numDmaChannels" ref="a90181831a767d1f5e6d796a5eb9a2ed1" args="" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a146c49c83ca4e65a3145d9b15d73571d">EDMA3_RM_GblConfigParams::numDmaChannels</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a90181831a767d1f5e6d796a5eb9a2ed1">EDMA3_RM_GblConfigParams::numDmaChannels</a></td>
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+<a class="anchor" id="afa03f7cd037ca5983017c8c403f82419"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::numQdmaChannels" ref="afa03f7cd037ca5983017c8c403f82419" args="" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a49bb3d33efc585d75c8c18cf26dbf169">EDMA3_RM_GblConfigParams::numQdmaChannels</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afa03f7cd037ca5983017c8c403f82419">EDMA3_RM_GblConfigParams::numQdmaChannels</a></td>
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+<a class="anchor" id="a8a0680e508ad29d759a0370084cbb6c0"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::numTccs" ref="a8a0680e508ad29d759a0370084cbb6c0" args="" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ade09c3f169c87739ab5b5d00101a59ed">EDMA3_RM_GblConfigParams::numTccs</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a8a0680e508ad29d759a0370084cbb6c0">EDMA3_RM_GblConfigParams::numTccs</a></td>
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+<a class="anchor" id="af5b2f463d96971ecebc269cc2b3e1e76"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::numPaRAMSets" ref="af5b2f463d96971ecebc269cc2b3e1e76" args="" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a9f66e1878cc69101518f94c5f95ec393">EDMA3_RM_GblConfigParams::numPaRAMSets</a></td>
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a152b2623285f14f6013b130fbfdf2ee1">EDMA3_RM_GblConfigParams::numEvtQueue</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a054dff0f68d9260dd20478042683e400">EDMA3_RM_GblConfigParams::numEvtQueue</a></td>
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+<a class="anchor" id="afbce74bc0f62d807cb436656f418338a"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::numTcs" ref="afbce74bc0f62d807cb436656f418338a" args="" -->
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+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a6b973fc32b6d8f47cb8dd46bb1ba88fd">EDMA3_RM_GblConfigParams::numRegions</a></td>
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+<a class="anchor" id="aa3fd8314930b636baf770de745c1cacc"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists" ref="aa3fd8314930b636baf770de745c1cacc" args="" -->
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+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#aa3fd8314930b636baf770de745c1cacc">EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists</a></td>
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+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a14d7d6cb9ccba0f454616b21cd6a7229">EDMA3_RM_GblConfigParams::memProtectionExists</a></td>
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+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a04d28c89d332f101383e0db8452154e4">EDMA3_RM_GblConfigParams::xferCompleteInt</a></td>
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-<a class="anchor" id="ae633ff54dda219dafc5d3b609a28a202"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::evtQueueWaterMarkLvl" ref="ae633ff54dda219dafc5d3b609a28a202" args="[EDMA3_MAX_EVT_QUE]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afa7ba95cc73b21f640888aab87a66533">EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap</a>[EDMA3_MAX_DMA_CH]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#a6366c59f0006724b2966135e0ea81fef">EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap</a>[EDMA3_MAX_DMA_CH]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="ab06c1d88f0efb9c82c963daf8d7ea684"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::dmaChannelTccMap" ref="ab06c1d88f0efb9c82c963daf8d7ea684" args="[EDMA3_MAX_DMA_CH]" -->
+<a class="anchor" id="af409720cb469a021a3624ff4d3e6ded6"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::dmaChannelTccMap" ref="af409720cb469a021a3624ff4d3e6ded6" args="[EDMA3_MAX_DMA_CH]" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ab06c1d88f0efb9c82c963daf8d7ea684">EDMA3_RM_GblConfigParams::dmaChannelTccMap</a>[EDMA3_MAX_DMA_CH]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#af409720cb469a021a3624ff4d3e6ded6">EDMA3_RM_GblConfigParams::dmaChannelTccMap</a>[EDMA3_MAX_DMA_CH]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="ac75808b1b49e327e540620ff08eb23d7"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::dmaChannelHwEvtMap" ref="ac75808b1b49e327e540620ff08eb23d7" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
+<a class="anchor" id="afcb2fcb340f13f2e450fac817b255747"></a><!-- doxytag: member="EDMA3_RM_GblConfigParams::dmaChannelHwEvtMap" ref="afcb2fcb340f13f2e450fac817b255747" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#ac75808b1b49e327e540620ff08eb23d7">EDMA3_RM_GblConfigParams::dmaChannelHwEvtMap</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_config_params.html#afcb2fcb340f13f2e450fac817b255747">EDMA3_RM_GblConfigParams::dmaChannelHwEvtMap</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
</tr>
</table>
</div>
<li>edma3_rm.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:50 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___gbl_err_callback_params.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___gbl_err_callback_params.html
index bdfc86c874007fd4b09040c1d1a514621bb405b9..5c9c2f26f3dada84413d0ef81f6728f8f55b4bd1 100755 (executable)
<p><code>#include <edma3_rm.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga6768147ae320fd3951df6762133d2ede">EDMA3_RM_GblErrCallback</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_err_callback_params.html#a7e71d5910d29c6a69576c3f860f6b272">gblerrCb</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#gaa0dbaf46ef2ab3f68257e8ed26c643fd">EDMA3_RM_GblErrCallback</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_err_callback_params.html#a7e71d5910d29c6a69576c3f860f6b272">gblerrCb</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_err_callback_params.html#af2a780928d2b6918ec49426a8ea60144">gblerrData</a></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga6768147ae320fd3951df6762133d2ede">EDMA3_RM_GblErrCallback</a> <a class="el" href="struct_e_d_m_a3___r_m___gbl_err_callback_params.html#a7e71d5910d29c6a69576c3f860f6b272">EDMA3_RM_GblErrCallbackParams::gblerrCb</a></td>
+ <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#gaa0dbaf46ef2ab3f68257e8ed26c643fd">EDMA3_RM_GblErrCallback</a> <a class="el" href="struct_e_d_m_a3___r_m___gbl_err_callback_params.html#a7e71d5910d29c6a69576c3f860f6b272">EDMA3_RM_GblErrCallbackParams::gblerrCb</a></td>
</tr>
</table>
</div>
<li>edma3_rm.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:50 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html
index a4d4a70827a9132c877e8d353074bd8499f98fa7..96f0e3acd1811079165d9905a225bb808c3c019f 100755 (executable)
--- a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html
+++ b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html
<p><code>#include <edma3_rm.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html#a170275163e292e728ed7c0039e84811a">dmaMapXbarToChan</a> [EDMA3_RM_MAX_XBAR_EVENTS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to Hardware Events. <a href="#a170275163e292e728ed7c0039e84811a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html#ad1a73637621a502d4a5bc896a2bcd6ca">dmaMapXbarToChan</a> [EDMA3_RM_MAX_XBAR_EVENTS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Mapping from DMA channels to Hardware Events. <a href="#ad1a73637621a502d4a5bc896a2bcd6ca"></a><br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. </p>
<p>This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. This configuraion structure provides the details of the mapping of cross bar events to available channels. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 Driver Object, using API EDMA3_RM_initXbarEventMap. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, incase it is available. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a170275163e292e728ed7c0039e84811a"></a><!-- doxytag: member="EDMA3_RM_GblXbarToChanConfigParams::dmaMapXbarToChan" ref="a170275163e292e728ed7c0039e84811a" args="[EDMA3_RM_MAX_XBAR_EVENTS]" -->
+<a class="anchor" id="ad1a73637621a502d4a5bc896a2bcd6ca"></a><!-- doxytag: member="EDMA3_RM_GblXbarToChanConfigParams::dmaMapXbarToChan" ref="ad1a73637621a502d4a5bc896a2bcd6ca" args="[EDMA3_RM_MAX_XBAR_EVENTS]" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">int <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html#a170275163e292e728ed7c0039e84811a">EDMA3_RM_GblXbarToChanConfigParams::dmaMapXbarToChan</a>[EDMA3_RM_MAX_XBAR_EVENTS]</td>
+ <td class="memname">int32_t <a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html#ad1a73637621a502d4a5bc896a2bcd6ca">EDMA3_RM_GblXbarToChanConfigParams::dmaMapXbarToChan</a>[EDMA3_RM_MAX_XBAR_EVENTS]</td>
</tr>
</table>
</div>
<li>edma3_rm.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:50 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___instance.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___instance.html
index 43d3376cb36399f1c1f922cb75f96f0248a56e19..87b71b9f959e2054cf95f8fbd52647b0fddf8d4e 100755 (executable)
<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance.html#aa25e136d2bae2f3a8c159bf6aa38e84e">avlblTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance.html#a750feffdd410001a563b312cd6d1442c">paramInitRequired</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance.html#a9994deccfdf8a63db677311aced1db79">regModificationRequired</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga373c55dba0c349454ce9be1a625ad17f">EDMA3_RM_mapXbarEvtToChan</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance.html#a35df179f3c52d5099e37a3ffcc06d5ae">mapXbarToChan</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga07f4c95a3095e6f0b25d34931312b315">EDMA3_RM_xbarConfigScr</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance.html#aa68814a024cee0e4239d9b58acdfa6aa">configScrMapXbarToEvt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa3446e78614a94f6a90723f79888fd33">EDMA3_RM_mapXbarEvtToChan</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance.html#a35df179f3c52d5099e37a3ffcc06d5ae">mapXbarToChan</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1e994f8dbd5632fa1ed4930dad03593f">EDMA3_RM_xbarConfigScr</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance.html#aa68814a024cee0e4239d9b58acdfa6aa">configScrMapXbarToEvt</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_e_d_m_a3___r_m___gbl_xbar_to_chan_config_params.html">EDMA3_RM_GblXbarToChanConfigParams</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance.html#a4f873f9f719e7e6643938e81a930509c">rmXbarToEvtMapConfig</a></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga373c55dba0c349454ce9be1a625ad17f">EDMA3_RM_mapXbarEvtToChan</a> <a class="el" href="struct_e_d_m_a3___r_m___instance.html#a35df179f3c52d5099e37a3ffcc06d5ae">EDMA3_RM_Instance::mapXbarToChan</a></td>
+ <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#gaa3446e78614a94f6a90723f79888fd33">EDMA3_RM_mapXbarEvtToChan</a> <a class="el" href="struct_e_d_m_a3___r_m___instance.html#a35df179f3c52d5099e37a3ffcc06d5ae">EDMA3_RM_Instance::mapXbarToChan</a></td>
</tr>
</table>
</div>
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga07f4c95a3095e6f0b25d34931312b315">EDMA3_RM_xbarConfigScr</a> <a class="el" href="struct_e_d_m_a3___r_m___instance.html#aa68814a024cee0e4239d9b58acdfa6aa">EDMA3_RM_Instance::configScrMapXbarToEvt</a></td>
+ <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___a_d_v_a_n_c_e_d.html#ga1e994f8dbd5632fa1ed4930dad03593f">EDMA3_RM_xbarConfigScr</a> <a class="el" href="struct_e_d_m_a3___r_m___instance.html#aa68814a024cee0e4239d9b58acdfa6aa">EDMA3_RM_Instance::configScrMapXbarToEvt</a></td>
</tr>
</table>
</div>
<li>edma3resmgr.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:51 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___instance_init_config.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___instance_init_config.html
index 79627466197d0f164723def519c6c5776ff7c187..a152418c54698614a1e01a6dc726ab78376c709c 100755 (executable)
<p><code>#include <edma3_rm.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a195712f03e6c92f0a386dd036422f956">ownPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#afea6ae753bce07d64d92f6521bb489e5">ownDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a836f8f25e8a2e01d6649034b7cc92d50">ownQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a38b3b42404f41e978c3b682ccf63fa8f">ownTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ab97d5476ee84765b1cb26216af673cfc">resvdPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved PaRAM Sets. <a href="#ab97d5476ee84765b1cb26216af673cfc"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a6df76275220d03b4b42c9161b4d670ff">resvdDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved DMA channels. <a href="#a6df76275220d03b4b42c9161b4d670ff"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ae7909518f9ba93b32c496193e797bf3b">resvdQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved QDMA channels. <a href="#ae7909518f9ba93b32c496193e797bf3b"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a7996562a8045cf6b7f33e40aa9b49313">resvdTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved TCCs. <a href="#a7996562a8045cf6b7f33e40aa9b49313"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a1825ba86c6fb95f870475beeb6de5864">ownPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a3160a96263a4aa8049a22f27fd620af0">ownDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a4d53baba7f90efe887ef6607e02a465e">ownQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#af3c6a8276f80b2e4314984a6eb03790b">ownTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#aeedea606ea2994be97bf4f1095eff9b1">resvdPaRAMSets</a> [EDMA3_MAX_PARAM_DWRDS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved PaRAM Sets. <a href="#aeedea606ea2994be97bf4f1095eff9b1"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a32f9138da21f943608572ee5598162b8">resvdDmaChannels</a> [EDMA3_MAX_DMA_CHAN_DWRDS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved DMA channels. <a href="#a32f9138da21f943608572ee5598162b8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ab9330897d8493510ec820604832320a8">resvdQdmaChannels</a> [EDMA3_MAX_QDMA_CHAN_DWRDS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved QDMA channels. <a href="#ab9330897d8493510ec820604832320a8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#aecf1dd1cffbf644e3275b41ab6f94d9b">resvdTccs</a> [EDMA3_MAX_TCC_DWRDS]</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved TCCs. <a href="#aecf1dd1cffbf644e3275b41ab6f94d9b"></a><br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. </p>
<p>Same logic applies for QDMA channels and TCCs.</p>
<p>For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 RM automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a195712f03e6c92f0a386dd036422f956"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownPaRAMSets" ref="a195712f03e6c92f0a386dd036422f956" args="[EDMA3_MAX_PARAM_DWRDS]" -->
+<a class="anchor" id="a1825ba86c6fb95f870475beeb6de5864"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownPaRAMSets" ref="a1825ba86c6fb95f870475beeb6de5864" args="[EDMA3_MAX_PARAM_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a195712f03e6c92f0a386dd036422f956">EDMA3_RM_InstanceInitConfig::ownPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a1825ba86c6fb95f870475beeb6de5864">EDMA3_RM_InstanceInitConfig::ownPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="afea6ae753bce07d64d92f6521bb489e5"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownDmaChannels" ref="afea6ae753bce07d64d92f6521bb489e5" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
+<a class="anchor" id="a3160a96263a4aa8049a22f27fd620af0"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownDmaChannels" ref="a3160a96263a4aa8049a22f27fd620af0" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
<div class="memitem">
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<tr>
- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#afea6ae753bce07d64d92f6521bb489e5">EDMA3_RM_InstanceInitConfig::ownDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a3160a96263a4aa8049a22f27fd620af0">EDMA3_RM_InstanceInitConfig::ownDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="a836f8f25e8a2e01d6649034b7cc92d50"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownQdmaChannels" ref="a836f8f25e8a2e01d6649034b7cc92d50" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
+<a class="anchor" id="a4d53baba7f90efe887ef6607e02a465e"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownQdmaChannels" ref="a4d53baba7f90efe887ef6607e02a465e" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a836f8f25e8a2e01d6649034b7cc92d50">EDMA3_RM_InstanceInitConfig::ownQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a4d53baba7f90efe887ef6607e02a465e">EDMA3_RM_InstanceInitConfig::ownQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="a38b3b42404f41e978c3b682ccf63fa8f"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownTccs" ref="a38b3b42404f41e978c3b682ccf63fa8f" args="[EDMA3_MAX_TCC_DWRDS]" -->
+<a class="anchor" id="af3c6a8276f80b2e4314984a6eb03790b"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::ownTccs" ref="af3c6a8276f80b2e4314984a6eb03790b" args="[EDMA3_MAX_TCC_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a38b3b42404f41e978c3b682ccf63fa8f">EDMA3_RM_InstanceInitConfig::ownTccs</a>[EDMA3_MAX_TCC_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#af3c6a8276f80b2e4314984a6eb03790b">EDMA3_RM_InstanceInitConfig::ownTccs</a>[EDMA3_MAX_TCC_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="ab97d5476ee84765b1cb26216af673cfc"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdPaRAMSets" ref="ab97d5476ee84765b1cb26216af673cfc" args="[EDMA3_MAX_PARAM_DWRDS]" -->
+<a class="anchor" id="aeedea606ea2994be97bf4f1095eff9b1"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdPaRAMSets" ref="aeedea606ea2994be97bf4f1095eff9b1" args="[EDMA3_MAX_PARAM_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ab97d5476ee84765b1cb26216af673cfc">EDMA3_RM_InstanceInitConfig::resvdPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#aeedea606ea2994be97bf4f1095eff9b1">EDMA3_RM_InstanceInitConfig::resvdPaRAMSets</a>[EDMA3_MAX_PARAM_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="a6df76275220d03b4b42c9161b4d670ff"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdDmaChannels" ref="a6df76275220d03b4b42c9161b4d670ff" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
+<a class="anchor" id="a32f9138da21f943608572ee5598162b8"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdDmaChannels" ref="a32f9138da21f943608572ee5598162b8" args="[EDMA3_MAX_DMA_CHAN_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a6df76275220d03b4b42c9161b4d670ff">EDMA3_RM_InstanceInitConfig::resvdDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a32f9138da21f943608572ee5598162b8">EDMA3_RM_InstanceInitConfig::resvdDmaChannels</a>[EDMA3_MAX_DMA_CHAN_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="ae7909518f9ba93b32c496193e797bf3b"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdQdmaChannels" ref="ae7909518f9ba93b32c496193e797bf3b" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
+<a class="anchor" id="ab9330897d8493510ec820604832320a8"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdQdmaChannels" ref="ab9330897d8493510ec820604832320a8" args="[EDMA3_MAX_QDMA_CHAN_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ae7909518f9ba93b32c496193e797bf3b">EDMA3_RM_InstanceInitConfig::resvdQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#ab9330897d8493510ec820604832320a8">EDMA3_RM_InstanceInitConfig::resvdQdmaChannels</a>[EDMA3_MAX_QDMA_CHAN_DWRDS]</td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="a7996562a8045cf6b7f33e40aa9b49313"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdTccs" ref="a7996562a8045cf6b7f33e40aa9b49313" args="[EDMA3_MAX_TCC_DWRDS]" -->
+<a class="anchor" id="aecf1dd1cffbf644e3275b41ab6f94d9b"></a><!-- doxytag: member="EDMA3_RM_InstanceInitConfig::resvdTccs" ref="aecf1dd1cffbf644e3275b41ab6f94d9b" args="[EDMA3_MAX_TCC_DWRDS]" -->
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#a7996562a8045cf6b7f33e40aa9b49313">EDMA3_RM_InstanceInitConfig::resvdTccs</a>[EDMA3_MAX_TCC_DWRDS]</td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html#aecf1dd1cffbf644e3275b41ab6f94d9b">EDMA3_RM_InstanceInitConfig::resvdTccs</a>[EDMA3_MAX_TCC_DWRDS]</td>
</tr>
</table>
</div>
<li>edma3_rm.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:51 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___misc_param.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___misc_param.html
index 381e5a8bf82cff4b47643ce1cd0d4e7b69f0382c..18f3514688365efed3f3811daa9f45ec35d2f050 100755 (executable)
<p><code>#include <edma3_rm.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a56ea473581e1d76b7497796d1e46d850">isSlave</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#ab66a1abe88183a9f57c85373010e5c75">param</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a70ded9151608e23053f391816898f17d">isSlave</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a73a5b20cd432208e692cd0be0faef50e">param</a></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Used to specify the miscellaneous options during Resource Manager Initialization. </p>
<p>This configuration structure is used to specify some misc options while creating the RM Object. New options may also be added into this structure in future. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a56ea473581e1d76b7497796d1e46d850"></a><!-- doxytag: member="EDMA3_RM_MiscParam::isSlave" ref="a56ea473581e1d76b7497796d1e46d850" args="" -->
+<a class="anchor" id="a70ded9151608e23053f391816898f17d"></a><!-- doxytag: member="EDMA3_RM_MiscParam::isSlave" ref="a70ded9151608e23053f391816898f17d" args="" -->
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- <td class="memname">unsigned short <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a56ea473581e1d76b7497796d1e46d850">EDMA3_RM_MiscParam::isSlave</a></td>
+ <td class="memname">uint16_t <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a70ded9151608e23053f391816898f17d">EDMA3_RM_MiscParam::isSlave</a></td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="ab66a1abe88183a9f57c85373010e5c75"></a><!-- doxytag: member="EDMA3_RM_MiscParam::param" ref="ab66a1abe88183a9f57c85373010e5c75" args="" -->
+<a class="anchor" id="a73a5b20cd432208e692cd0be0faef50e"></a><!-- doxytag: member="EDMA3_RM_MiscParam::param" ref="a73a5b20cd432208e692cd0be0faef50e" args="" -->
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- <td class="memname">unsigned short <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#ab66a1abe88183a9f57c85373010e5c75">EDMA3_RM_MiscParam::param</a></td>
+ <td class="memname">uint16_t <a class="el" href="struct_e_d_m_a3___r_m___misc_param.html#a73a5b20cd432208e692cd0be0faef50e">EDMA3_RM_MiscParam::param</a></td>
</tr>
</table>
</div>
<li>edma3_rm.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:51 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___obj.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___obj.html
index 62e95a4205466dea134d78be9ab6f86d7ea02160..cf71e679937b70ea9153b41d46698bfe236208ae 100755 (executable)
<div class="memdoc">
<p>Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. </p>
-<p>This configuration will can be provided by the user at run-time, while calling <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#gadc4459024208af43ca53740f5f0e24f2" title="Create EDMA3 Resource Manager Object.">EDMA3_RM_create()</a>. </p>
+<p>This configuration will can be provided by the user at run-time, while calling <a class="el" href="group___e_d_m_a3___l_l_d___r_m___f_u_n_c_t_i_o_n___i_n_i_t.html#ga4ed822e8a60e9cc0d6c894f98ff2ae86" title="Create EDMA3 Resource Manager Object.">EDMA3_RM_create()</a>. </p>
</div>
</div>
<li>edma3resmgr.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:51 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___pa_r_a_m_regs.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___pa_r_a_m_regs.html
index a5f6b8e8393c5eb038799014cbbf6fafb10321e0..2e3987aec04c1315df23e6407884f9de8bc6da1f 100755 (executable)
<p><code>#include <edma3_rm.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ab3fbc10843edca5369164bb54f8f1311">opt</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a88f22ecb531e50776a8d39efb07e1f03"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::srcAddr" ref="a88f22ecb531e50776a8d39efb07e1f03" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a88f22ecb531e50776a8d39efb07e1f03">srcAddr</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a7b017530e64c24d5e51a1b557820da7c">opt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afd0564c51a029cfd93d571792a2de9df"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::srcAddr" ref="afd0564c51a029cfd93d571792a2de9df" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#afd0564c51a029cfd93d571792a2de9df">srcAddr</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6b793fb789c2e62244588c1de455d5c3"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::aCnt" ref="a6b793fb789c2e62244588c1de455d5c3" args="" -->
-volatile unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a6b793fb789c2e62244588c1de455d5c3">aCnt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ade3675d257bad105135f87cacecb6071"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::aCnt" ref="ade3675d257bad105135f87cacecb6071" args="" -->
+volatile uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ade3675d257bad105135f87cacecb6071">aCnt</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Number of bytes in each Array (ACNT). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac7a839fc4ec88ef71de0298ae9d0f5c0"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::bCnt" ref="ac7a839fc4ec88ef71de0298ae9d0f5c0" args="" -->
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+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7fcb8088ada92e2a8e85b8ddf799497e"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::bCnt" ref="a7fcb8088ada92e2a8e85b8ddf799497e" args="" -->
+volatile uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a7fcb8088ada92e2a8e85b8ddf799497e">bCnt</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Number of Arrays in each Frame (BCNT). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a476c3a53fd360b0c823c4432ef3da665"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::destAddr" ref="a476c3a53fd360b0c823c4432ef3da665" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a476c3a53fd360b0c823c4432ef3da665">destAddr</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abc6bf0cba0c58295198a0a361ff832f6"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::destAddr" ref="abc6bf0cba0c58295198a0a361ff832f6" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#abc6bf0cba0c58295198a0a361ff832f6">destAddr</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a379c5a7e527a0df8f1a0f3f570370a4a"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::srcBIdx" ref="a379c5a7e527a0df8f1a0f3f570370a4a" args="" -->
-volatile short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a379c5a7e527a0df8f1a0f3f570370a4a">srcBIdx</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad2580901284de100faad83df848dd448"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::srcBIdx" ref="ad2580901284de100faad83df848dd448" args="" -->
+volatile int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ad2580901284de100faad83df848dd448">srcBIdx</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a20e706a171712ea04b3f73cfaaa9b388"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::destBIdx" ref="a20e706a171712ea04b3f73cfaaa9b388" args="" -->
-volatile short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a20e706a171712ea04b3f73cfaaa9b388">destBIdx</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae884a5534b218804f5ede866d8ee8814"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::destBIdx" ref="ae884a5534b218804f5ede866d8ee8814" args="" -->
+volatile int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ae884a5534b218804f5ede866d8ee8814">destBIdx</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a895743ea8620f21b5ddc2149d2a05c3b"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::linkAddr" ref="a895743ea8620f21b5ddc2149d2a05c3b" args="" -->
-volatile unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a895743ea8620f21b5ddc2149d2a05c3b">linkAddr</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a137bdee75d4f4850cc914123637b4c33"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::linkAddr" ref="a137bdee75d4f4850cc914123637b4c33" args="" -->
+volatile uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a137bdee75d4f4850cc914123637b4c33">linkAddr</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae7a0840fb53ccfd2ae35e943390bf9f2"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::bCntReload" ref="ae7a0840fb53ccfd2ae35e943390bf9f2" args="" -->
-volatile unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ae7a0840fb53ccfd2ae35e943390bf9f2">bCntReload</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a89420524d0a519582e3b8a991272c04a"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::bCntReload" ref="a89420524d0a519582e3b8a991272c04a" args="" -->
+volatile uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a89420524d0a519582e3b8a991272c04a">bCntReload</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a948163aaedd3fff182f8ba9de03b4091"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::srcCIdx" ref="a948163aaedd3fff182f8ba9de03b4091" args="" -->
-volatile short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a948163aaedd3fff182f8ba9de03b4091">srcCIdx</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aeb5320c3c544792f3e9c3703586d6192"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::srcCIdx" ref="aeb5320c3c544792f3e9c3703586d6192" args="" -->
+volatile int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#aeb5320c3c544792f3e9c3703586d6192">srcCIdx</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Index between consecutive frames of a Source Block (SRCCIDX). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a14e3f593a8db50dd39fc5379a7fa2b7a"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::destCIdx" ref="a14e3f593a8db50dd39fc5379a7fa2b7a" args="" -->
-volatile short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a14e3f593a8db50dd39fc5379a7fa2b7a">destCIdx</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae21ea5a25f7aadbee9ae6aa0d9c194fa"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::destCIdx" ref="ae21ea5a25f7aadbee9ae6aa0d9c194fa" args="" -->
+volatile int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ae21ea5a25f7aadbee9ae6aa0d9c194fa">destCIdx</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Index between consecutive frames of a Dest Block (DSTCIDX). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a88d49983095c65ad1787cc02d56daf27"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::cCnt" ref="a88d49983095c65ad1787cc02d56daf27" args="" -->
-volatile unsigned short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a88d49983095c65ad1787cc02d56daf27">cCnt</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad3fd07485720ce2655f7cbda7c9ab067"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::cCnt" ref="ad3fd07485720ce2655f7cbda7c9ab067" args="" -->
+volatile uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ad3fd07485720ce2655f7cbda7c9ab067">cCnt</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Number of Frames in a block (CCNT). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4c42631d5ab80acf9332ba666abf9a9b"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::reserved" ref="a4c42631d5ab80acf9332ba666abf9a9b" args="" -->
-volatile short </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a4c42631d5ab80acf9332ba666abf9a9b">reserved</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a71075ffdf5d932cf329fb18ccb2a8412"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::reserved" ref="a71075ffdf5d932cf329fb18ccb2a8412" args="" -->
+volatile int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a71075ffdf5d932cf329fb18ccb2a8412">reserved</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>EDMA3 PaRAM Set in User Configurable format. </p>
<p>This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual fields. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="ab3fbc10843edca5369164bb54f8f1311"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::opt" ref="ab3fbc10843edca5369164bb54f8f1311" args="" -->
+<a class="anchor" id="a7b017530e64c24d5e51a1b557820da7c"></a><!-- doxytag: member="EDMA3_RM_PaRAMRegs::opt" ref="a7b017530e64c24d5e51a1b557820da7c" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">volatile unsigned int <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#ab3fbc10843edca5369164bb54f8f1311">EDMA3_RM_PaRAMRegs::opt</a></td>
+ <td class="memname">volatile uint32_t <a class="el" href="struct_e_d_m_a3___r_m___pa_r_a_m_regs.html#a7b017530e64c24d5e51a1b557820da7c">EDMA3_RM_PaRAMRegs::opt</a></td>
</tr>
</table>
</div>
<li>edma3_rm.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:51 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___param.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___param.html
index 69615dbe8e7c2abf80b7c13ac8dca719c4b68d39..85307612c6f539b2f5a4681d2195196b1914a6e1 100755 (executable)
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga95ce8c6a9989cc4bbd29e0234e6ee5e4">EDMA3_RM_RegionId</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___param.html#a5722cd299dd4712cdb9f7cf7aec869b6">regionId</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___param.html#ad984d3a198db18f7287c67e3b7b74da9">isMaster</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___param.html#a784ad88bc2b19240b1ecd83fe91c247a">isMaster</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_e_d_m_a3___r_m___instance_init_config.html">EDMA3_RM_InstanceInitConfig</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___param.html#ab4b422aad358309280f16027423df238">rmInstInitConfig</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___param.html#a5f6478d1cacf5b62e3039f37c82a4e78">rmSemHandle</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___param.html#ad0a96e32f45702667e091717595150f8">regionInitEnable</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___param.html#a2d609f44e5cc8e6c08fb217bd0ba7d18">regionInitEnable</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_e_d_m_a3___r_m___gbl_err_callback_params.html">EDMA3_RM_GblErrCallbackParams</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___param.html#abafa6f546c9a5a893885f161d96ebe61">gblerrCbParams</a></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
</div>
</div>
-<a class="anchor" id="ad984d3a198db18f7287c67e3b7b74da9"></a><!-- doxytag: member="EDMA3_RM_Param::isMaster" ref="ad984d3a198db18f7287c67e3b7b74da9" args="" -->
+<a class="anchor" id="a784ad88bc2b19240b1ecd83fe91c247a"></a><!-- doxytag: member="EDMA3_RM_Param::isMaster" ref="a784ad88bc2b19240b1ecd83fe91c247a" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___param.html#ad984d3a198db18f7287c67e3b7b74da9">EDMA3_RM_Param::isMaster</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___param.html#a784ad88bc2b19240b1ecd83fe91c247a">EDMA3_RM_Param::isMaster</a></td>
</tr>
</table>
</div>
</div>
</div>
-<a class="anchor" id="ad0a96e32f45702667e091717595150f8"></a><!-- doxytag: member="EDMA3_RM_Param::regionInitEnable" ref="ad0a96e32f45702667e091717595150f8" args="" -->
+<a class="anchor" id="a2d609f44e5cc8e6c08fb217bd0ba7d18"></a><!-- doxytag: member="EDMA3_RM_Param::regionInitEnable" ref="a2d609f44e5cc8e6c08fb217bd0ba7d18" args="" -->
<div class="memitem">
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___param.html#ad0a96e32f45702667e091717595150f8">EDMA3_RM_Param::regionInitEnable</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___param.html#a2d609f44e5cc8e6c08fb217bd0ba7d18">EDMA3_RM_Param::regionInitEnable</a></td>
</tr>
</table>
</div>
<li>edma3_rm.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:51 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___paramentry_regs.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___paramentry_regs.html
index d377278be30fdcd169c1b1ec2c82cbf55f28fd0e..4a70628a60fcb3015c007ba1dcf7213cc1b6b517 100755 (executable)
<p><code>#include <edma3_rm.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a0cf7a755d7bae28725d5473f55e4b285">OPT</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5cdf48fe9dfa1bf57634707cb0844272"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::SRC" ref="a5cdf48fe9dfa1bf57634707cb0844272" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a5cdf48fe9dfa1bf57634707cb0844272">SRC</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a110b9d0964b16086bcce89f7a6a46cbe">OPT</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6fcb86ab0e29c57c86c81de6509023c8"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::SRC" ref="a6fcb86ab0e29c57c86c81de6509023c8" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a6fcb86ab0e29c57c86c81de6509023c8">SRC</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a86ce51bcde596db8686df5151d1e36f4">A_B_CNT</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a962a4fded1f7b63f8cc9150c924b97f5"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::DST" ref="a962a4fded1f7b63f8cc9150c924b97f5" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a962a4fded1f7b63f8cc9150c924b97f5">DST</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#acc6b08ed32da038adf39628a11314042">A_B_CNT</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af0dfaf6acd333ce4f4ebadcfbe983609"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::DST" ref="af0dfaf6acd333ce4f4ebadcfbe983609" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#af0dfaf6acd333ce4f4ebadcfbe983609">DST</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0. <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#afb5a2b7960d93156dbf7d5f1966b5b47">SRC_DST_BIDX</a></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a4262be65b0dcae242b5e2dccd5b5b23f">LINK_BCNTRLD</a></td></tr>
-<tr><td class="mdescLeft"> </td><td class="mdescRight">Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits). <a href="#a4262be65b0dcae242b5e2dccd5b5b23f"></a><br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac2f5d7cc117f6078c9857ebb630cad17"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::SRC_DST_CIDX" ref="ac2f5d7cc117f6078c9857ebb630cad17" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#ac2f5d7cc117f6078c9857ebb630cad17">SRC_DST_CIDX</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a8a8201bdc65cca0618ab84cba098a6d9">SRC_DST_BIDX</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a94895249b81f76b9aee370af7dcc53c8">LINK_BCNTRLD</a></td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits). <a href="#a94895249b81f76b9aee370af7dcc53c8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a84deb8a812c77152972d24126fbac35a"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::SRC_DST_CIDX" ref="a84deb8a812c77152972d24126fbac35a" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a84deb8a812c77152972d24126fbac35a">SRC_DST_CIDX</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Index between consecutive frames of a Source Block (SRCCIDX) (16 bits) and Index between consecutive frames of a Dest Block (DSTCIDX) (16 bits). <br/></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa3ef14c588c533a40427f219242e7f2a"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::CCNT" ref="aa3ef14c588c533a40427f219242e7f2a" args="" -->
-volatile unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#aa3ef14c588c533a40427f219242e7f2a">CCNT</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa45df17e9b9fad3ce516d3d7053dcdd8"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::CCNT" ref="aa45df17e9b9fad3ce516d3d7053dcdd8" args="" -->
+volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#aa45df17e9b9fad3ce516d3d7053dcdd8">CCNT</a></td></tr>
<tr><td class="mdescLeft"> </td><td class="mdescRight">Number of Frames in a block (CCNT) (16 bits). <br/></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
@@ -58,12 +58,12 @@ volatile unsigned int </td><td class="memItemRight" valign="bottom"><a clas
<p>This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual PaRAM words.</p>
<p>It could be used by the advanced users to program the PaRAM Set directly, without using any API. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a0cf7a755d7bae28725d5473f55e4b285"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::OPT" ref="a0cf7a755d7bae28725d5473f55e4b285" args="" -->
+<a class="anchor" id="a110b9d0964b16086bcce89f7a6a46cbe"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::OPT" ref="a110b9d0964b16086bcce89f7a6a46cbe" args="" -->
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- <td class="memname">volatile unsigned int <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a0cf7a755d7bae28725d5473f55e4b285">EDMA3_RM_ParamentryRegs::OPT</a></td>
+ <td class="memname">volatile uint32_t <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a110b9d0964b16086bcce89f7a6a46cbe">EDMA3_RM_ParamentryRegs::OPT</a></td>
</tr>
</table>
</div>
@@ -72,12 +72,12 @@ volatile unsigned int </td><td class="memItemRight" valign="bottom"><a clas
</div>
</div>
-<a class="anchor" id="a86ce51bcde596db8686df5151d1e36f4"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::A_B_CNT" ref="a86ce51bcde596db8686df5151d1e36f4" args="" -->
+<a class="anchor" id="acc6b08ed32da038adf39628a11314042"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::A_B_CNT" ref="acc6b08ed32da038adf39628a11314042" args="" -->
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- <td class="memname">volatile unsigned int <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a86ce51bcde596db8686df5151d1e36f4">EDMA3_RM_ParamentryRegs::A_B_CNT</a></td>
+ <td class="memname">volatile uint32_t <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#acc6b08ed32da038adf39628a11314042">EDMA3_RM_ParamentryRegs::A_B_CNT</a></td>
</tr>
</table>
</div>
@@ -86,12 +86,12 @@ volatile unsigned int </td><td class="memItemRight" valign="bottom"><a clas
</div>
</div>
-<a class="anchor" id="afb5a2b7960d93156dbf7d5f1966b5b47"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::SRC_DST_BIDX" ref="afb5a2b7960d93156dbf7d5f1966b5b47" args="" -->
+<a class="anchor" id="a8a8201bdc65cca0618ab84cba098a6d9"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::SRC_DST_BIDX" ref="a8a8201bdc65cca0618ab84cba098a6d9" args="" -->
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- <td class="memname">volatile unsigned int <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#afb5a2b7960d93156dbf7d5f1966b5b47">EDMA3_RM_ParamentryRegs::SRC_DST_BIDX</a></td>
+ <td class="memname">volatile uint32_t <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a8a8201bdc65cca0618ab84cba098a6d9">EDMA3_RM_ParamentryRegs::SRC_DST_BIDX</a></td>
</tr>
</table>
</div>
@@ -102,12 +102,12 @@ volatile unsigned int </td><td class="memItemRight" valign="bottom"><a clas
</div>
</div>
-<a class="anchor" id="a4262be65b0dcae242b5e2dccd5b5b23f"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::LINK_BCNTRLD" ref="a4262be65b0dcae242b5e2dccd5b5b23f" args="" -->
+<a class="anchor" id="a94895249b81f76b9aee370af7dcc53c8"></a><!-- doxytag: member="EDMA3_RM_ParamentryRegs::LINK_BCNTRLD" ref="a94895249b81f76b9aee370af7dcc53c8" args="" -->
<div class="memitem">
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- <td class="memname">volatile unsigned int <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a4262be65b0dcae242b5e2dccd5b5b23f">EDMA3_RM_ParamentryRegs::LINK_BCNTRLD</a></td>
+ <td class="memname">volatile uint32_t <a class="el" href="struct_e_d_m_a3___r_m___paramentry_regs.html#a94895249b81f76b9aee370af7dcc53c8">EDMA3_RM_ParamentryRegs::LINK_BCNTRLD</a></td>
</tr>
</table>
</div>
@@ -123,7 +123,7 @@ volatile unsigned int </td><td class="memItemRight" valign="bottom"><a clas
<li>edma3_rm.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:51 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___res_desc.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___res_desc.html
index 77807b99bc58f2510ed79d9b269a2a7a59315cf1..dac1acaafd20e65d7a93c48809394d05648ec6f5 100755 (executable)
<p><code>#include <edma3_rm.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top">unsigned int </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a8fffc8bd17e838ce866a225ffe14ce02">resId</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a7a3b79d5f21a9a6d4af2e47edc905b69">resId</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___e_n_u_m.html#ga05b92650ee862481552b709fe0f4f904">EDMA3_RM_ResType</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a3d13077eac87394e8c0721e6346c3716">type</a></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Handle to a Resource. </p>
<hr/><h2>Field Documentation</h2>
-<a class="anchor" id="a8fffc8bd17e838ce866a225ffe14ce02"></a><!-- doxytag: member="EDMA3_RM_ResDesc::resId" ref="a8fffc8bd17e838ce866a225ffe14ce02" args="" -->
+<a class="anchor" id="a7a3b79d5f21a9a6d4af2e47edc905b69"></a><!-- doxytag: member="EDMA3_RM_ResDesc::resId" ref="a7a3b79d5f21a9a6d4af2e47edc905b69" args="" -->
<div class="memitem">
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- <td class="memname">unsigned int <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a8fffc8bd17e838ce866a225ffe14ce02">EDMA3_RM_ResDesc::resId</a></td>
+ <td class="memname">uint32_t <a class="el" href="struct_e_d_m_a3___r_m___res_desc.html#a7a3b79d5f21a9a6d4af2e47edc905b69">EDMA3_RM_ResDesc::resId</a></td>
</tr>
</table>
</div>
<li>edma3_rm.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:51 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>
diff --git a/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___tcc_callback_params.html b/packages/ti/sdo/edma3/rm/docs/html/struct_e_d_m_a3___r_m___tcc_callback_params.html
index 923a364422d62b4ae4329b4c7a985504f0b23ac3..3e25963219ad51f3c490e7177bc345756e7ec1e4 100755 (executable)
<p><code>#include <edma3resmgr.h></code></p>
<table border="0" cellpadding="0" cellspacing="0">
<tr><td colspan="2"><h2>Data Fields</h2></td></tr>
-<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#gaadca81927be74261ef874009bf8e37d3">EDMA3_RM_TccCallback</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html#ab46111c7ca4b209d38383103bfd9a1e5">tccCb</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga3d1093c590b221a5d7b24dbb9bba58d1">EDMA3_RM_TccCallback</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html#ab46111c7ca4b209d38383103bfd9a1e5">tccCb</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html#a9834742e3ec7ea2b7ec1064055417cab">cbData</a></td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<div class="memproto">
<table class="memname">
<tr>
- <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#gaadca81927be74261ef874009bf8e37d3">EDMA3_RM_TccCallback</a> <a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html#ab46111c7ca4b209d38383103bfd9a1e5">EDMA3_RM_TccCallbackParams::tccCb</a></td>
+ <td class="memname"><a class="el" href="group___e_d_m_a3___l_l_d___r_m___s_y_m_b_o_l___t_y_p_e_d_e_f.html#ga3d1093c590b221a5d7b24dbb9bba58d1">EDMA3_RM_TccCallback</a> <a class="el" href="struct_e_d_m_a3___r_m___tcc_callback_params.html#ab46111c7ca4b209d38383103bfd9a1e5">EDMA3_RM_TccCallbackParams::tccCb</a></td>
</tr>
</table>
</div>
<li>edma3resmgr.h</li>
</ul>
</div>
-<hr size="1"/><address style="text-align: right;"><small>Generated on Fri Jan 28 16:33:51 2011 for EDMA3 Resource Manager by
+<hr size="1"/><address style="text-align: right;"><small>Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.6.1 </small></address>
</body>