OMAPL137 Integration: Config files for OMAPL137EVM

Add default config files for OMAPL137 EVM board

Signed-off-by: Pratap Reddy <x0257344@ti.com>

diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_arm_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_arm_cfg.c
new file mode 100644 (file)
index 0000000..8fb63d2
--- /dev/null
+++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_arm_cfg.c
@@ -0,0 +1,788 @@
+/*
+ * sample_omapl137_cfg.c
+ *
+ * SoC specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                    1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+{
+    return 0;
+}
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+{
+    (void) dspNum;
+    return 0;
+}
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET                              (128u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC                                   (32u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_0_NUM_EVTQUE                              (2u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_0_NUM_TC                                  (2u)
+
+
+/** Interrupt no. for Transfer Completion                                     */
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (11u)
+
+/** Interrupt no. for CC Error                                                */
+#define EDMA3_0_CC_ERROR_INT                            (12u)
+
+/** Interrupt no. for TCs Error                                               */
+#define EDMA3_0_TC0_ERROR_INT                           (13u)
+#define EDMA3_0_TC1_ERROR_INT                           (32u)
+#define EDMA3_0_TC2_ERROR_INT                           (0u)
+#define EDMA3_0_TC3_ERROR_INT                           (0u)
+#define EDMA3_0_TC4_ERROR_INT                           (0u)
+#define EDMA3_0_TC5_ERROR_INT                           (0u)
+#define EDMA3_0_TC6_ERROR_INT                           (0u)
+#define EDMA3_0_TC7_ERROR_INT                           (0u)
+
+
+/**
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+ * ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file.
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+ * to transfer completion interrupt.
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+ * to CC error interrupts.
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+ * to TC error interrupts.
+ */
+/* EDMA 0 */
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_0_HWI_INT_CC_ERR                              (7u)
+#define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                      /* 31     0 */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFF3FF3FFu)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in omapl138. */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x0u)
+
+/* Variable which will be used internally for referring number of Event Queues*/
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+                                                        EDMA3_0_NUM_EVTQUE
+                                                    };
+
+/* Variable which will be used internally for referring number of TCs.        */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+                                                    EDMA3_0_NUM_TC
+                                                };
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                {
+                    EDMA3_0_CC_XFER_COMPLETION_INT, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+                },
+            };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_CC_ERROR_INT
+                                               };
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
+                               {
+                                   EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
+                                   EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
+                                   EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
+                                   EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
+                               }
+                            };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_HWI_INT_XFER_COMP
+                                                  };
+
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+                                                   EDMA3_0_HWI_INT_CC_ERR
+                                               };
+
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+                                                     {
+                                                        EDMA3_0_HWI_INT_TC0_ERR,
+                                                        EDMA3_0_HWI_INT_TC1_ERR,
+                                                     }
+                                               };
+
+/* Driver Object Initialization Configuration */
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+{
+    {
+        /* EDMA3 INSTANCE# 0 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        32u,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        8u,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        32u,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        128u,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        2u,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        2u,
+        /** Number of Regions on this EDMA3 controller                        */
+        4u,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        0u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        (void *)0x01C00000u,
+        /** Transfer Controller (TC) Registers */
+        {
+            (void *)0x01C08000u,
+            (void *)0x01C08400u,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_0_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_0_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            EDMA3_0_TC0_ERROR_INT,
+            EDMA3_0_TC1_ERROR_INT,
+            EDMA3_0_TC2_ERROR_INT,
+            EDMA3_0_TC3_ERROR_INT,
+            EDMA3_0_TC4_ERROR_INT,
+            EDMA3_0_TC5_ERROR_INT,
+            EDMA3_0_TC6_ERROR_INT,
+            EDMA3_0_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+            },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            }
+        },
+};
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Resources owned/reserved by region 0 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31       0 */
+            {0xFF3FF3FFu,
+            /* 63..32 */
+            0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+        },
+        /* Resources owned/reserved by region 1 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31       0 */
+            {0xFF3FF3FFu,
+            /* 63..32 */
+            0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+        },
+        /* Resources owned/reserved by region 2 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 3 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 4 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 5 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 6 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 7 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+    }
+};
+
+/* End of File */
+

diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_arm_int_reg.c
new file mode 100644 (file)
index 0000000..5cd0575
--- /dev/null
+++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_arm_int_reg.c
@@ -0,0 +1,168 @@
+/*
+ * sample_omapl137_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/hal/Hwi.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+/* This variable has to be used as an extern */
+unsigned int gpp_num = 0;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+    Hwi_Params hwiParams; 
+        
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntXferComp[edma3Id];
+    
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num],
+                                       (&lisrEdma3ComplHandler0),
+                                       (const Hwi_Params *) (&hwiParams),
+                                       NULL);
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntCcErr[edma3Id];
+       
+       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+                (&lisrEdma3CCErrHandler0),
+                (const Hwi_Params *) (&hwiParams),
+                NULL);
+
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        /* Initialize the HWI parameters with user specified values */
+        Hwi_Params_init(&hwiParams);
+        /* argument for the ISR */
+        hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+        hwiParams.priority = hwIntTcErr[edma3Id];
+        
+        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+                    (ptrEdma3TcIsrHandler[numTc]),
+                    (const Hwi_Params *) (&hwiParams),
+                    NULL);
+        numTc++;
+       }
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
+    Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
+    Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    Hwi_delete(&hwiCCXferCompInt);
+    Hwi_delete(&hwiCCErrInt);
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_delete(&hwiTCErrInt[numTc]);
+        numTc++;
+       }
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+

diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_cfg.c
new file mode 100644 (file)
index 0000000..80d09a2
--- /dev/null
+++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_cfg.c
@@ -0,0 +1,785 @@
+/*
+ * sample_omapl137_cfg.c
+ *
+ * SoC specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                    1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+{
+    return 1;
+}
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+unsigned short isGblConfigRequired(unsigned int dspNum)
+{
+    (void) dspNum;
+
+    return 1;
+}
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET                              (128u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC                                   (32u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_0_NUM_EVTQUE                              (2u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_0_NUM_TC                                  (2u)
+
+#ifdef __TMS470__  /* values for ARM */
+
+#else /* values for DSP */
+/** Interrupt no. for Transfer Completion                                     */
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (8u)
+
+/** Interrupt no. for CC Error                                                */
+#define EDMA3_0_CC_ERROR_INT                            (56u)
+
+/** Interrupt no. for TCs Error                                               */
+#define EDMA3_0_TC0_ERROR_INT                           (57u)
+#define EDMA3_0_TC1_ERROR_INT                           (58u)
+#define EDMA3_0_TC2_ERROR_INT                           (0u)
+#define EDMA3_0_TC3_ERROR_INT                           (0u)
+#define EDMA3_0_TC4_ERROR_INT                           (0u)
+#define EDMA3_0_TC5_ERROR_INT                           (0u)
+#define EDMA3_0_TC6_ERROR_INT                           (0u)
+#define EDMA3_0_TC7_ERROR_INT                           (0u)
+
+/**
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+ * ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file.
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+ * to transfer completion interrupt.
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+ * to CC error interrupts.
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+ * to TC error interrupts.
+ */
+/* EDMA 0 */
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_0_HWI_INT_CC_ERR                              (8u)
+#define EDMA3_0_HWI_INT_TC0_ERR                             (8u)
+#define EDMA3_0_HWI_INT_TC1_ERR                             (8u)
+
+#endif  /* __TMS470__ */
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                      /* 31     0 */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFF3FF3FFu)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in omapl138. */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x0u)
+
+/* Variable which will be used internally for referring number of Event Queues*/
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+                                                        EDMA3_0_NUM_EVTQUE
+                                                    };
+
+/* Variable which will be used internally for referring number of TCs.        */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+                                                    EDMA3_0_NUM_TC
+                                                };
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                {
+                    0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+                },
+            };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_CC_ERROR_INT
+                                               };
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
+                               {
+                                   EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
+                                   EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
+                                   EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
+                                   EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
+                               }
+                            };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_HWI_INT_XFER_COMP
+                                                  };
+
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+                                                   EDMA3_0_HWI_INT_CC_ERR
+                                               };
+
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+                                                     {
+                                                        EDMA3_0_HWI_INT_TC0_ERR,
+                                                        EDMA3_0_HWI_INT_TC1_ERR,
+                                                     }
+                                               };
+
+/* Driver Object Initialization Configuration */
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+{
+    {
+        /* EDMA3 INSTANCE# 0 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        32u,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        8u,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        32u,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        128u,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        2u,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        2u,
+        /** Number of Regions on this EDMA3 controller                        */
+        4u,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        0u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        (void *)0x01C00000u,
+        /** Transfer Controller (TC) Registers */
+        {
+            (void *)0x01C08000u,
+            (void *)0x01C08400u,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_0_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_0_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            EDMA3_0_TC0_ERROR_INT,
+            EDMA3_0_TC1_ERROR_INT,
+            EDMA3_0_TC2_ERROR_INT,
+            EDMA3_0_TC3_ERROR_INT,
+            EDMA3_0_TC4_ERROR_INT,
+            EDMA3_0_TC5_ERROR_INT,
+            EDMA3_0_TC6_ERROR_INT,
+            EDMA3_0_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+            },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            }
+        }
+};
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Resources owned/reserved by region 0 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+        /* Resources owned/reserved by region 1 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31       0 */
+            {0xFF3FF3FFu,
+            /* 63..32 */
+            0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+        },
+        /* Resources owned/reserved by region 2 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 3 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 4 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 5 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 6 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 7 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+       }
+};
+
+/* End of File */
+

diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_int_reg.c
new file mode 100644 (file)
index 0000000..4598042
--- /dev/null
+++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_omapl137_int_reg.c
@@ -0,0 +1,152 @@
+/*
+ * sample_omapl137_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+extern unsigned int dsp_num;
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Enable the Xfer Completion Event Interrupt */
+    EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
+                               edma3Id, 1);
+    EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Enable the CC Error Event Interrupt */
+    EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
+                                               edma3Id, 1);
+    EventCombiner_enableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
+                            (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
+                            edma3Id, 1);
+        EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
+    Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
+    Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Disable the Xfer Completion Event Interrupt */
+       EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Disable the CC Error Event Interrupt */
+       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+       {
+        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+

diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_arm_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_arm_cfg.c
new file mode 100644 (file)
index 0000000..62df58e
--- /dev/null
+++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_arm_cfg.c
@@ -0,0 +1,786 @@
+/*
+ * sample_omapl137_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                    1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+{
+    return 0;
+}
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+{
+    (void) dspNum;
+    return 0;
+}
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle SemHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET                              (128u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC                                   (32u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_0_NUM_EVTQUE                              (2u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_0_NUM_TC                                  (2u)
+
+/** Interrupt no. for Transfer Completion                                     */
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (11u)
+
+/** Interrupt no. for CC Error                                                */
+#define EDMA3_0_CC_ERROR_INT                            (12u)
+
+/** Interrupt no. for TCs Error                                               */
+#define EDMA3_0_TC0_ERROR_INT                           (13u)
+#define EDMA3_0_TC1_ERROR_INT                           (32u)
+#define EDMA3_0_TC2_ERROR_INT                           (0u)
+#define EDMA3_0_TC3_ERROR_INT                           (0u)
+#define EDMA3_0_TC4_ERROR_INT                           (0u)
+#define EDMA3_0_TC5_ERROR_INT                           (0u)
+#define EDMA3_0_TC6_ERROR_INT                           (0u)
+#define EDMA3_0_TC7_ERROR_INT                           (0u)
+
+
+/**
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+ * ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file.
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+ * to transfer completion interrupt.
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+ * to CC error interrupts.
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+ * to TC error interrupts.
+ */
+/* EDMA 0 */
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_0_HWI_INT_CC_ERR                              (7u)
+#define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                      /* 31     0 */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFF3FF3FFu)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in omapl138. */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x0u)
+
+/* Variable which will be used internally for referring number of Event Queues*/
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+                                                        EDMA3_0_NUM_EVTQUE
+                                                    };
+
+/* Variable which will be used internally for referring number of TCs.        */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+                                                    EDMA3_0_NUM_TC
+                                                };
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                {
+                    EDMA3_0_CC_XFER_COMPLETION_INT, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+                },
+            };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_CC_ERROR_INT
+                                               };
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
+                               {
+                                   EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
+                                   EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
+                                   EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
+                                   EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
+                               }
+                            };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_HWI_INT_XFER_COMP
+                                                  };
+
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+                                                   EDMA3_0_HWI_INT_CC_ERR
+                                               };
+
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+                                                     {
+                                                        EDMA3_0_HWI_INT_TC0_ERR,
+                                                        EDMA3_0_HWI_INT_TC1_ERR,
+                                                     }
+                                               };
+
+/* Driver Object Initialization Configuration                                 */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+{
+    {
+        /* EDMA3 INSTANCE# 0 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        32u,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        8u,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        32u,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        128u,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        2u,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        2u,
+        /** Number of Regions on this EDMA3 controller                        */
+        4u,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        0u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        (void *)0x01C00000u,
+        /** Transfer Controller (TC) Registers */
+        {
+            (void *)0x01C08000u,
+            (void *)0x01C08400u,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_0_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_0_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            EDMA3_0_TC0_ERROR_INT,
+            EDMA3_0_TC1_ERROR_INT,
+            EDMA3_0_TC2_ERROR_INT,
+            EDMA3_0_TC3_ERROR_INT,
+            EDMA3_0_TC4_ERROR_INT,
+            EDMA3_0_TC5_ERROR_INT,
+            EDMA3_0_TC6_ERROR_INT,
+            EDMA3_0_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+            },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            }
+        },
+};
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Resources owned/reserved by region 0 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+        },
+        /* Resources owned/reserved by region 1 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+        },
+        /* Resources owned/reserved by region 2 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 3 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 4 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 5 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 6 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 7 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+    }
+};
+
+/* End of File */
+

diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_arm_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_arm_int_reg.c
new file mode 100644 (file)
index 0000000..a2c33f1
--- /dev/null
+++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_arm_int_reg.c
@@ -0,0 +1,154 @@
+/*
+ * sample_omapl137_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 - 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/hal/Hwi.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+extern unsigned int dsp_num;
+/* This variable has to be used as an extern */
+unsigned int gpp_num = 0;
+
+Hwi_Handle hwiCCXferCompInt;
+Hwi_Handle hwiCCErrInt;
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+    Hwi_Params hwiParams; 
+        
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntXferComp[edma3Id];
+    
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num],
+                                       (&lisrEdma3ComplHandler0),
+                                       (const Hwi_Params *) (&hwiParams),
+                                       NULL);
+    /* Initialize the HWI parameters with user specified values */
+    Hwi_Params_init(&hwiParams);
+    /* argument for the ISR */
+    hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+       hwiParams.priority = hwIntCcErr[edma3Id];
+       
+       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
+                (&lisrEdma3CCErrHandler0),
+                (const Hwi_Params *) (&hwiParams),
+                NULL);
+
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        /* Initialize the HWI parameters with user specified values */
+        Hwi_Params_init(&hwiParams);
+        /* argument for the ISR */
+        hwiParams.arg = edma3Id;
+       /* set the priority ID     */
+        hwiParams.priority = hwIntTcErr[edma3Id];
+        
+        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
+                    (ptrEdma3TcIsrHandler[numTc]),
+                    (const Hwi_Params *) (&hwiParams),
+                    NULL);
+        numTc++;
+       }
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    Hwi_delete(&hwiCCXferCompInt);
+    Hwi_delete(&hwiCCErrInt);
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        Hwi_delete(&hwiTCErrInt[numTc]);
+        numTc++;
+       }
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+

diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_cfg.c
new file mode 100644 (file)
index 0000000..252ff5f
--- /dev/null
+++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_cfg.c
@@ -0,0 +1,785 @@
+/*
+ * sample_omapl137_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2009 - 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                    1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+{
+    return 1;
+}
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+unsigned short isGblConfigRequired(unsigned int dspNum)
+{
+    (void) dspNum;
+
+    return 1;
+}
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle SemHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET                              (128u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC                                   (32u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_0_NUM_EVTQUE                              (2u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_0_NUM_TC                                  (2u)
+
+#ifdef __TMS470__  /* values for ARM */
+
+#else /* values for DSP */
+/** Interrupt no. for Transfer Completion                                     */
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (8u)
+
+/** Interrupt no. for CC Error                                                */
+#define EDMA3_0_CC_ERROR_INT                            (56u)
+
+/** Interrupt no. for TCs Error                                               */
+#define EDMA3_0_TC0_ERROR_INT                           (57u)
+#define EDMA3_0_TC1_ERROR_INT                           (58u)
+#define EDMA3_0_TC2_ERROR_INT                           (0u)
+#define EDMA3_0_TC3_ERROR_INT                           (0u)
+#define EDMA3_0_TC4_ERROR_INT                           (0u)
+#define EDMA3_0_TC5_ERROR_INT                           (0u)
+#define EDMA3_0_TC6_ERROR_INT                           (0u)
+#define EDMA3_0_TC7_ERROR_INT                           (0u)
+
+/**
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+ * ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file.
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+ * to transfer completion interrupt.
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+ * to CC error interrupts.
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+ * to TC error interrupts.
+ */
+/* EDMA 0 */
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_0_HWI_INT_CC_ERR                              (8u)
+#define EDMA3_0_HWI_INT_TC0_ERR                             (8u)
+#define EDMA3_0_HWI_INT_TC1_ERR                             (8u)
+
+#endif  /* __TMS470__ */
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                      /* 31     0 */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFF3FF3FFu)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in omapl138. */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x0u)
+
+/* Variable which will be used internally for referring number of Event Queues*/
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+                                                        EDMA3_0_NUM_EVTQUE
+                                                    };
+
+/* Variable which will be used internally for referring number of TCs.        */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+                                                    EDMA3_0_NUM_TC
+                                                };
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                {
+                    0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+                },
+            };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_CC_ERROR_INT
+                                               };
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
+                               {
+                                   EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
+                                   EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
+                                   EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
+                                   EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
+                               }
+                            };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_HWI_INT_XFER_COMP
+                                                  };
+
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+                                                   EDMA3_0_HWI_INT_CC_ERR
+                                               };
+
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+                                                     {
+                                                        EDMA3_0_HWI_INT_TC0_ERR,
+                                                        EDMA3_0_HWI_INT_TC1_ERR,
+                                                     }
+                                               };
+
+/* Driver Object Initialization Configuration                                 */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+{
+    {
+        /* EDMA3 INSTANCE# 0 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        32u,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        8u,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        32u,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        128u,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        2u,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        2u,
+        /** Number of Regions on this EDMA3 controller                        */
+        4u,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        0u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        (void *)0x01C00000u,
+        /** Transfer Controller (TC) Registers */
+        {
+            (void *)0x01C08000u,
+            (void *)0x01C08400u,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_0_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_0_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            EDMA3_0_TC0_ERROR_INT,
+            EDMA3_0_TC1_ERROR_INT,
+            EDMA3_0_TC2_ERROR_INT,
+            EDMA3_0_TC3_ERROR_INT,
+            EDMA3_0_TC4_ERROR_INT,
+            EDMA3_0_TC5_ERROR_INT,
+            EDMA3_0_TC6_ERROR_INT,
+            EDMA3_0_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+            },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            }
+    },
+};
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Resources owned/reserved by region 0 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+        /* Resources owned/reserved by region 1 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+        },
+        /* Resources owned/reserved by region 2 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 3 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 4 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 5 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 6 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 7 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+    }
+};
+
+/* End of File */
+

diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_int_reg.c
new file mode 100644 (file)
index 0000000..320959d
--- /dev/null
+++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_omapl137_int_reg.c
@@ -0,0 +1,152 @@
+/*
+ * sample_omapl137_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 - 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+extern unsigned int dsp_num;
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Enable the Xfer Completion Event Interrupt */
+    EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
+                               edma3Id, 1);
+    EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Enable the CC Error Event Interrupt */
+    EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
+                                               edma3Id, 1);
+    EventCombiner_enableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
+                            (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
+                            edma3Id, 1);
+        EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
+    Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
+    Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Disable the Xfer Completion Event Interrupt */
+       EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Disable the CC Error Event Interrupt */
+       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+       {
+        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+

diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_omapl137_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_omapl137_cfg.c
new file mode 100644 (file)
index 0000000..6280e27
--- /dev/null
+++ b/packages/ti/sdo/edma3/rm/src/configs/edma3_omapl137_cfg.c
@@ -0,0 +1,465 @@
+/*
+ * edma3_omapl137_cfg.c
+ *
+ * EDMA3 Driver Adaptation Configuration File (Soc Specific) for OMAPL138.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+#define NUM_SHADOW_REGIONS                      (4u)
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* EDMA3 0 */
+                                                /* 31     0 */
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0        (0xFF3FF3FFu)
+/**
+ * EDMA channels 22 and 23, which correspond to GPIO
+ * bank interrupts will be used for memory-to-memory data transfers.
+ */
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+/* EDMA3 0 */
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1        (0x0u)
+
+EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+    /** Total number of DMA Channels supported by the EDMA3 Controller */
+    32u,
+    /** Total number of QDMA Channels supported by the EDMA3 Controller */
+    8u,
+    /** Total number of TCCs supported by the EDMA3 Controller */
+    32u,
+    /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+    128u,
+    /** Total number of Event Queues in the EDMA3 Controller */
+    2u,
+    /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+    2u,
+    /** Number of Regions on this EDMA3 controller */
+    4u,
+
+    /**
+     * \brief Channel mapping existence
+     * A value of 0 (No channel mapping) implies that there is fixed association
+     * for a channel number to a parameter entry number or, in other words,
+     * PaRAM entry n corresponds to channel n.
+     */
+    0u,
+
+    /** Existence of memory protection feature */
+    0u,
+
+    /** Global Register Region of CC Registers */
+    (void *)(0x01C00000u),
+    /** Transfer Controller (TC) Registers */
+        {
+        (void *)(0x01C08000u),
+        (void *)(0x01C08400u),
+        (void *)NULL,
+        (void *)NULL,
+        (void *)NULL,
+        (void *)NULL,
+        (void *)NULL,
+        (void *)NULL,
+        },
+    /** Interrupt no. for Transfer Completion */
+    8u,
+    /** Interrupt no. for CC Error */
+    56u,
+    /** Interrupt no. for TCs Error */
+        {
+        57u,
+        58u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        },
+
+   /**
+     * \brief EDMA3 TC priority setting
+     *
+     * User can program the priority of the Event Queues
+     * at a system-wide level.  This means that the user can set the
+     * priority of an IO initiated by either of the TCs (Transfer Controllers)
+     * relative to IO initiated by the other bus masters on the
+     * device (ARM, DSP, USB, etc)
+     */
+        {
+        0u,
+        1u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+    /**
+     * \brief To Configure the Threshold level of number of events
+     * that can be queued up in the Event queues. EDMA3CC error register
+     * (CCERR) will indicate whether or not at any instant of time the
+     * number of events queued up in any of the event queues exceeds
+     * or equals the threshold/watermark value that is set
+     * in the queue watermark threshold register (QWMTHRA).
+     */
+        {
+        16u,
+        16u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+
+    /**
+     * \brief To Configure the Default Burst Size (DBS) of TCs.
+     * An optimally-sized command is defined by the transfer controller
+     * default burst size (DBS). Different TCs can have different
+     * DBS values. It is defined in Bytes.
+     */
+        {
+        16u,
+        16u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+
+    /**
+     * \brief Mapping from each DMA channel to a Parameter RAM set,
+     * if it exists, otherwise of no use.
+     */
+        {
+        0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+        16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+        /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+        },
+
+     /**
+      * \brief Mapping from each DMA channel to a TCC. This specific
+      * TCC code will be returned when the transfer is completed
+      * on the mapped channel.
+      */
+        {
+        0u, 1u, 2u, 3u,
+        4u, 5u, 6u, 7u,
+        8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        12u, 13u, 14u, 15u,
+        16u, 17u, 18u, 19u,
+        20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        24u, 25u, 26u, 27u,
+        28u, 29u, 30u, 31u,
+        /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+        },
+
+    /**
+     * \brief Mapping of DMA channels to Hardware Events from
+     * various peripherals, which use EDMA for data transfer.
+     * All channels need not be mapped, some can be free also.
+     */
+        {
+        DMA_CHANNEL_TO_EVENT_MAPPING_0_0,
+        DMA_CHANNEL_TO_EVENT_MAPPING_0_1
+        }
+    },
+};
+
+
+/* Default RM Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SHADOW_REGIONS] =
+{
+        /* EDMA3 INSTANCE# 0 */
+        {
+          {
+            /* Resources owned by Region 0 */
+             /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* Resources reserved by Region 0 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+          },
+
+          {
+            /* Resources owned by Region 1 */
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31      0  63..32 */
+            {DMA_CHANNEL_TO_EVENT_MAPPING_0_0, DMA_CHANNEL_TO_EVENT_MAPPING_0_1},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31      0  63..32 */
+            {DMA_CHANNEL_TO_EVENT_MAPPING_0_0, DMA_CHANNEL_TO_EVENT_MAPPING_0_1},
+          },
+
+          {
+            /* Resources owned by Region 2 */
+             /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* Resources reserved by Region 2 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+          },
+
+          {
+            /* Resources owned by Region 3 */
+             /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* Resources reserved by Region 3 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+          },
+        },
+};
+
+/* End of File */
+
+
+