Bug Fix: IR No SDOCM00112223
authorSunil MS <x0190988@ti.com>
Thu, 9 Oct 2014 10:03:48 +0000 (15:33 +0530)
committerSunil MS <x0190988@ti.com>
Mon, 20 Oct 2014 14:13:59 +0000 (19:43 +0530)
Bug Description:Include all EDMA instances in the RM configuration structure
for dra72x and tda2xx

Solution:RM configuartion for all edma instances has been defined with
respect to DRV.
Signed-off-by: Sunil MS <x0190988@ti.com>
Change-Id: Icf63858080403039e894d3484a16a6e6693d791c
Signed-off-by: Sunil MS <x0190988@ti.com>
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_dra72x_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c
packages/ti/sdo/edma3/rm/edma3_rm.h
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_dra72x_cfg.c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda2xx_cfg.c
packages/ti/sdo/edma3/rm/src/configs/edma3_dra72x_cfg.c
packages/ti/sdo/edma3/rm/src/configs/edma3_tda2xx_cfg.c

index 87229c0b6e16cb0b3754785e53900ec50f943c5e..c9a6d79871f3673396ab79b9fcbeb6abca417b2d 100644 (file)
@@ -275,7 +275,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                       /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA       (0x3FC0C06Eu)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06Eu)  /* TBD */
 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFu)  /* TBD */
 
 /**
@@ -292,7 +292,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  *
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA       (0xF3FFFFFCu) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCu) /* TBD */
 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000u) /* TBD */
 
 
@@ -425,10 +425,10 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
     },
     /* EDMA3 INSTANCE# 1 */
     {
+        DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,
         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
-        DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,
     }
 };
 unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
@@ -706,8 +706,8 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * All channels need not be mapped, some can be free also.
          */
             {
-            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA,
-            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA
             }
         },
     {
@@ -938,7 +938,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -948,7 +948,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -985,7 +985,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -995,7 +995,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -1032,7 +1032,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -1042,7 +1042,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -1126,7 +1126,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -1136,7 +1136,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -1173,7 +1173,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -1183,7 +1183,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -1220,7 +1220,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -1230,7 +1230,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -1267,7 +1267,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -1277,7 +1277,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -1410,7 +1410,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -1672,6 +1672,97 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     /* EDMA3 INSTANCE# 0 */
+    {
+        /* Event to channel map for region 0 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 1 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 2 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 3 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 4 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 5 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 6 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+        /* Event to channel map for region 7 */
+        {
+            {-1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
+        },
+    },
+    /* EDMA3 INSTANCE# 1 */
     {
         /* Event to channel map for region 0 */
         {
index 7c29be080f49dc3921a5f9422b9abaf3e2cd8820..49494182bb21875bd6d4368b7d0bb45a3d4fd682 100644 (file)
@@ -333,7 +333,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
  */\r
                                                       /* 31     0 */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA       (0x3FC0C06EU)  /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06EU)  /* TBD */\r
 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFU)  /* TBD */\r
 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA        (0x00000000U)  /* TBD */\r
 \r
@@ -351,7 +351,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  *\r
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
  */\r
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA       (0xF3FFFFFCU) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCU) /* TBD */\r
 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000U) /* TBD */\r
 #define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA        (0x00000000U) /* TBD */\r
 \r
@@ -535,10 +535,10 @@ uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
     },\r
     /* EDMA3 INSTANCE# 1 */\r
     {\r
+        DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
         EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
         EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
         EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
-        DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
     },\r
     /* EDMA3 INSTANCE# 2 */\r
     {\r
@@ -861,8 +861,8 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * All channels need not be mapped, some can be free also.\r
          */\r
             {\r
-            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA,\r
-            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA\r
             }\r
         },\r
     {\r
@@ -1289,7 +1289,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -1344,7 +1344,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -1391,7 +1391,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -1438,7 +1438,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -1485,7 +1485,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -1532,7 +1532,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -1579,7 +1579,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -1626,7 +1626,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
index 02fd6dc014f0dc98bc5162b4d6a0e92668ec61dc..a6cd3c5701da41638c6b0de99b335ce2f304c4ee 100755 (executable)
@@ -2172,7 +2172,7 @@ EDMA3_RM_Result EDMA3_RM_Ioctl(
                       void                  *param
                      );
 
-#define EDMA3_RM_MAX_XBAR_EVENTS (31U)
+#define EDMA3_RM_MAX_XBAR_EVENTS (63U)
 
 /**\struct  EDMA3_RM_GblXbarToChanConfigParams
  * \brief   Init-time Configuration structure for EDMA3
index d919b14e5b69c087d4e6ff4715f96fd41fa2868d..8f17253e52c8effaaf28b5f42e6df96316e82769 100644 (file)
 */
 
 #include <ti/sdo/edma3/rm/edma3_rm.h>
+#ifdef BUILD_DRA72X_IPU
+#include <ti/sysbios/family/arm/ducati/Core.h>
 
+#endif
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         1u
+#define NUM_EDMA3_INSTANCES         2u
 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 /* Number of DSPs present in the system */
@@ -123,28 +126,114 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_NUM_QDMA_CHANNELS                         (8u)
 
 /** Number of Event Queues available                                          */
-#define EDMA3_0_NUM_EVTQUE                              (4u)
+#define EDMA3_NUM_EVTQUE                              (4u)
 
 /** Number of Transfer Controllers available                                  */
-#define EDMA3_0_NUM_TC                                  (4u)
+#define EDMA3_NUM_TC                                  (4u)
 
 /** Number of Regions                                                         */
-#define EDMA3_0_NUM_REGIONS                             (2u)
-
-
-/** Interrupt no. for Transfer Completion                                     */
-#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34u)
-/** Interrupt no. for CC Error                                                */
-#define EDMA3_0_CC_ERROR_INT                            (35u)
-/** Interrupt no. for TCs Error                                               */
-#define EDMA3_0_TC0_ERROR_INT                           (36u)
-#define EDMA3_0_TC1_ERROR_INT                           (37u)
-#define EDMA3_0_TC2_ERROR_INT                           (0u)
-#define EDMA3_0_TC3_ERROR_INT                           (0u)
-#define EDMA3_0_TC4_ERROR_INT                           (0u)
-#define EDMA3_0_TC5_ERROR_INT                           (0u)
-#define EDMA3_0_TC6_ERROR_INT                           (0u)
-#define EDMA3_0_TC7_ERROR_INT                           (0u)
+#define EDMA3_NUM_REGIONS                             (2u)
+
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38u)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34u)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33u)
+
+/** Based on the interrupt number to be mapped define the XBAR instance number */
+#define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)
+#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7u)
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12u)
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11u)
+
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT_A15                          (67u)
+#define EDMA3_CC_ERROR_INT_DSP                          (39u)
+#define EDMA3_CC_ERROR_INT_IPU                          (35u)
+
+/** Based on the interrupt number to be mapped define the XBAR instance number */
+#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)
+#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8u)
+#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13u)
+
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT_A15                         (68u)
+#define EDMA3_TC0_ERROR_INT_DSP                         (40u)
+#define EDMA3_TC0_ERROR_INT_IPU                         (36u)
+#define EDMA3_TC1_ERROR_INT_A15                         (69u)
+#define EDMA3_TC1_ERROR_INT_DSP                         (41u)
+#define EDMA3_TC1_ERROR_INT_IPU                         (37u)
+
+/** Based on the interrupt number to be mapped define the XBAR instance number */
+#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9u)
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14u)
+#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10u)
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15u)
+
+#ifdef BUILD_DRA72X_MPU
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A15
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_A15_XBAR_INST_NO
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A15
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_A15
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+
+#elif defined BUILD_DRA72X_DSP
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_DSP_XBAR_INST_NO
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_DSP
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_DSP
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_DSP_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_DSP_XBAR_INST_NO
+
+#elif defined BUILD_DRA72X_IPU
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU_C0
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU_XBAR_INST_NO
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO
+
+#else
+#define EDMA3_CC_XFER_COMPLETION_INT                    (0u)
+#define EDMA3_CC_ERROR_INT                              (0u)
+#define CC_ERROR_INT_XBAR_INST_NO                       (0u)
+#define EDMA3_TC0_ERROR_INT                             (0u)
+#define EDMA3_TC1_ERROR_INT                             (0u)
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+#endif
+
+#define EDMA3_TC2_ERROR_INT                             (0u)
+#define EDMA3_TC3_ERROR_INT                             (0u)
+#define EDMA3_TC4_ERROR_INT                             (0u)
+#define EDMA3_TC5_ERROR_INT                             (0u)
+#define EDMA3_TC6_ERROR_INT                             (0u)
+#define EDMA3_TC7_ERROR_INT                             (0u)
+
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19u)
+#define DSP1_EDMA3_CC_ERROR_INT                         (27u)
+#define DSP1_EDMA3_TC0_ERROR_INT                        (28u)
+#define DSP1_EDMA3_TC1_ERROR_INT                        (29u)
+
+/** XBAR interrupt source index numbers for EDMA interrupts */
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)
+
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)
 
 /**
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
@@ -162,12 +251,12 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  */
 /* EDMA 0 */
 
-#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
-#define EDMA3_0_HWI_INT_CC_ERR                              (7u)
-#define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
-#define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
-#define EDMA3_0_HWI_INT_TC2_ERR                             (7u)
-#define EDMA3_0_HWI_INT_TC3_ERR                             (7u)
+#define EDMA3_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_HWI_INT_CC_ERR                              (7u)
+#define EDMA3_HWI_INT_TC0_ERR                             (10u)
+#define EDMA3_HWI_INT_TC1_ERR                             (10u)
+#define EDMA3_HWI_INT_TC2_ERR                             (10u)
+#define EDMA3_HWI_INT_TC3_ERR                             (10u)
 
 
 /**
@@ -175,25 +264,29 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * various peripherals, which use EDMA for data transfer.
  * All channels need not be mapped, some can be free also.
  * 1: Mapped
- * 0: Not mapped
+ * 0: Not mapped (channel available)
  *
  * This mapping will be used to allocate DMA channels when user passes
  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
  * copy). The same mapping is used to allocate the TCC when user passes
  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
  *
+ * For Vayu Since the xbar can be used to map event to any EDMA channel,
+ * If the application is assigning events to other channel this variable
+ * should be modified
+ *
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                       /* 31     0 */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x3FC0C06Eu)  /* TBD */
-
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06Eu)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFu)  /* TBD */
 
 /**
  * \brief Mapping of DMA channels 32-63 to Hardware Events from
  * various peripherals, which use EDMA for data transfer.
  * All channels need not be mapped, some can be free also.
  * 1: Mapped
- * 0: Not mapped
+ * 0: Not mapped (channel available)
  *
  * This mapping will be used to allocate DMA channels when user passes
  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
@@ -202,17 +295,19 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  *
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xF3FFFFFCu) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCu) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000u) /* TBD */
 
 
 /* Variable which will be used internally for referring number of Event Queues*/
 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
-                                                        EDMA3_0_NUM_EVTQUE,
+                                                        EDMA3_NUM_EVTQUE,
                                                     };
 
 /* Variable which will be used internally for referring number of TCs.        */
 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
-                                                    EDMA3_0_NUM_TC,
+                                                    EDMA3_NUM_TC,
+                                                    EDMA3_NUM_TC
                                                 };
 
 /**
@@ -221,57 +316,118 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
  */
 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
+    /* EDMA3 INSTANCE# 0 */
     {
-        0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+        EDMA3_CC_XFER_COMPLETION_INT_A15,
+        EDMA3_CC_XFER_COMPLETION_INT_A15,
+               EDMA3_CC_XFER_COMPLETION_INT_DSP,
+        0u,
+               EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
+        EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,
+        EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,
+        EDMA3_CC_XFER_COMPLETION_INT_IPU_C1
     },
+    /* EDMA3 INSTANCE# 1 */
+    {
+        0u,
+        0u,
+        DSP1_EDMA3_CC_XFER_COMPLETION_INT,
+        0u,
+        0u,
+        0u,
+        0u,
+        0u
+    }
 };
 
 /**
  * Variable which will be used internally for referring channel controller's
  * error interrupt.
  */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
-                                                    EDMA3_0_CC_ERROR_INT,
-                                               };
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] =
+{
+    EDMA3_CC_ERROR_INT,
+    DSP1_EDMA3_CC_ERROR_INT
+};
 
 /**
  * Variable which will be used internally for referring transfer controllers'
  * error interrupts.
  */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
-   {
-       EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
-       EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
-       EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
-       EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
-   }
+    /* EDMA3 INSTANCE# 0 */
+    {
+        EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+        EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
+    },
+    /* EDMA3 INSTANCE# 1 */
+    {
+        DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,
+        EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+    }
 };
 
 /**
  * Variables which will be used internally for referring the hardware interrupt
  * for various EDMA3 interrupts.
  */
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
-                                                    EDMA3_0_HWI_INT_XFER_COMP
-                                                  };
-
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
-                                                   EDMA3_0_HWI_INT_CC_ERR
-                                               };
-
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
-                                                     {
-                                                        EDMA3_0_HWI_INT_TC0_ERR,
-                                                        EDMA3_0_HWI_INT_TC1_ERR,
-                                                        EDMA3_0_HWI_INT_TC2_ERR,
-                                                        EDMA3_0_HWI_INT_TC3_ERR
-                                                     }
-                                               };
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] =
+{
+    EDMA3_HWI_INT_XFER_COMP,
+    EDMA3_HWI_INT_XFER_COMP
+};
+
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] =
+{
+    EDMA3_HWI_INT_CC_ERR,
+    EDMA3_HWI_INT_CC_ERR
+};
+
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        EDMA3_HWI_INT_TC0_ERR,
+        EDMA3_HWI_INT_TC1_ERR,
+        EDMA3_HWI_INT_TC2_ERR,
+        EDMA3_HWI_INT_TC3_ERR
+    },
+    /* EDMA3 INSTANCE# 1 */
+    {
+        EDMA3_HWI_INT_TC0_ERR,
+        EDMA3_HWI_INT_TC1_ERR,
+        EDMA3_HWI_INT_TC2_ERR,
+        EDMA3_HWI_INT_TC3_ERR
+    }
+};
 
+/**
+ * \brief Base address as seen from the different cores may be different
+ * And is defined based on the core
+ */
+#if ((defined BUILD_DRA72X_MPU) || (defined BUILD_DRA72X_DSP))
 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))
 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))
 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))
+#elif (defined BUILD_DRA72X_IPU)
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x63300000))
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x63400000))
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x63500000))
+#else
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x0))
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x0))
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x0))
+#endif
+
+#define DSP1_EDMA3_CC_BASE_ADDR                     ((void *)(0x01D10000))
+#define DSP1_EDMA3_TC0_BASE_ADDR                    ((void *)(0x01D05000))
+#define DSP1_EDMA3_TC1_BASE_ADDR                    ((void *)(0x01D06000))
+
 /* Driver Object Initialization Configuration                                 */
 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
 {
@@ -286,11 +442,11 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
         EDMA3_NUM_PARAMSET,
         /** Total number of Event Queues in the EDMA3 Controller              */
-        EDMA3_0_NUM_EVTQUE,
+        EDMA3_NUM_EVTQUE,
         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
-        EDMA3_0_NUM_TC,
+        EDMA3_NUM_TC,
         /** Number of Regions on this EDMA3 controller                        */
-        EDMA3_0_NUM_REGIONS,
+        EDMA3_NUM_REGIONS,
 
         /**
          * \brief Channel mapping existence
@@ -317,19 +473,19 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
             (void *)NULL
         },
         /** Interrupt no. for Transfer Completion */
-        EDMA3_0_CC_XFER_COMPLETION_INT,
+        EDMA3_CC_XFER_COMPLETION_INT,
         /** Interrupt no. for CC Error */
-        EDMA3_0_CC_ERROR_INT,
+        EDMA3_CC_ERROR_INT,
         /** Interrupt no. for TCs Error */
         {
-            EDMA3_0_TC0_ERROR_INT,
-            EDMA3_0_TC1_ERROR_INT,
-            EDMA3_0_TC2_ERROR_INT,
-            EDMA3_0_TC3_ERROR_INT,
-            EDMA3_0_TC4_ERROR_INT,
-            EDMA3_0_TC5_ERROR_INT,
-            EDMA3_0_TC6_ERROR_INT,
-            EDMA3_0_TC7_ERROR_INT
+            EDMA3_TC0_ERROR_INT,
+            EDMA3_TC1_ERROR_INT,
+            EDMA3_TC2_ERROR_INT,
+            EDMA3_TC3_ERROR_INT,
+            EDMA3_TC4_ERROR_INT,
+            EDMA3_TC5_ERROR_INT,
+            EDMA3_TC6_ERROR_INT,
+            EDMA3_TC7_ERROR_INT
         },
 
         /**
@@ -344,8 +500,8 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
         {
             0u,
             1u,
-            2u,
-            3u,
+            0u,
+            0u,
             0u,
             0u,
             0u,
@@ -362,11 +518,196 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
         {
             16u,
             16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+                       },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA
+            }
+        },
+    {
+        /* EDMA3 INSTANCE# 1 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        EDMA3_NUM_DMA_CHANNELS,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        EDMA3_NUM_QDMA_CHANNELS,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        EDMA3_NUM_TCC,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        EDMA3_NUM_PARAMSET,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        EDMA3_NUM_EVTQUE,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        EDMA3_NUM_TC,
+        /** Number of Regions on this EDMA3 controller                        */
+        EDMA3_NUM_REGIONS,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        1u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        DSP1_EDMA3_CC_BASE_ADDR,
+        /** Transfer Controller (TC) Registers */
+        {
+               DSP1_EDMA3_TC0_BASE_ADDR,
+               DSP1_EDMA3_TC1_BASE_ADDR,
+               (void *)NULL,
+               (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        DSP1_EDMA3_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        DSP1_EDMA3_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            DSP1_EDMA3_TC0_ERROR_INT,
+            DSP1_EDMA3_TC1_ERROR_INT,
+            EDMA3_TC2_ERROR_INT,
+            EDMA3_TC3_ERROR_INT,
+            EDMA3_TC4_ERROR_INT,
+            EDMA3_TC5_ERROR_INT,
+            EDMA3_TC6_ERROR_INT,
+            EDMA3_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
             16u,
             16u,
             0u,
             0u,
             0u,
+            0u,
+            0u,
             0u
         },
 
@@ -392,14 +733,38 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * if it exists, otherwise of no use.
          */
             {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
             },
 
          /**
@@ -408,22 +773,22 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
           * on the mapped channel.
           */
             {
-            0u, 1u, 2u, 3u,
-            4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u,
-            12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u,
-            20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u,
-            28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
             },
 
         /**
@@ -432,13 +797,21 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * All channels need not be mapped, some can be free also.
          */
             {
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA
             }
-        },
-
+    }
 };
 
+/**
+ * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
+ * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
+ * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
+ * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
+ *
+ * Only Resources owned by a perticular core are allocated by Driver
+ * Reserved resources are not allocated if requested for any available resource
+ */
 
 /* Driver Instance Initialization Configuration */
 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
@@ -471,7 +844,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -481,7 +854,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -492,7 +865,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                {0x00u, 0x00u},
                        },
 
-                       /* Resources owned/reserved by region 1 (Associated to any DSP core) */
+                       /* Resources owned/reserved by region 1 (Associated to MPU core 1) */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
@@ -504,7 +877,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                /* 415  384     447  416     479  448     511  480 */
                                 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 
-                               /* ownDmaChannels */
+                 /* ownDmaChannels */
                                /* 31     0     63    32 */
                                {0xFFFFFFFFu, 0xFFFFFFFFu},
 
@@ -518,7 +891,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -528,7 +901,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -539,7 +912,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                {0x00u, 0x00u},
                        },
 
-               /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/
+                       /* Resources owned/reserved by region 2 (Associated to any DSP core) */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
@@ -565,7 +938,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -575,7 +948,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -586,33 +959,33 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                {0x00u, 0x00u},
                        },
 
-               /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/
+               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0x00000000u, 0x00000000u},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000FFu},
+                               {0x00000000u},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+                               {0x00000000u, 0x00000000u},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -622,40 +995,40 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00000000u, 0x00000000u},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00u},
+                               {0x00000000u},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00u, 0x00u},
+                               {0x00000000u, 0x00000000u},
                        },
 
-               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
+               /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x000000FFu},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
@@ -669,40 +1042,40 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00u},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00u, 0x00u},
                        },
 
-               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
+               /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x000000FFu},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
@@ -716,40 +1089,40 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00u},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00u, 0x00u},
                        },
 
-               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
+               /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x000000FFu},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
@@ -763,22 +1136,71 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {0x00u},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {0x00u, 0x00u},
                        },
 
-               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
+               /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+           },
+               /* EDMA3 INSTANCE# 1 DSP1 EDMA*/
+               {
+               /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -819,8 +1241,337 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                /* resvdTccs */
                                /* 31     0     63    32 */
                                {0x00000000u, 0x00000000u},
-        },
-    },
+                       },
+
+                       /* Resources owned/reserved by region 1 (Not Associated to any core supported) */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 2 (Associated to DSP core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x000000FFu},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00u, 0x00u},
+                       },
+
+               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+           }
 };
 
 /* Driver Instance Cross bar event to channel map Initialization Configuration */
@@ -833,6 +1584,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1}
         },
         /* Event to channel map for region 1 */
@@ -840,13 +1595,21 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, 26, 27, -1, -1, -1, -1}
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1}
         },
         /* Event to channel map for region 2 */
         {
             {-1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1}
         },
         /* Event to channel map for region 3 */
@@ -854,6 +1617,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1}
         },
         /* Event to channel map for region 4 */
@@ -861,6 +1628,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1}
         },
         /* Event to channel map for region 5 */
@@ -868,6 +1639,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1}
         },
         /* Event to channel map for region 6 */
@@ -875,6 +1650,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1}
         },
         /* Event to channel map for region 7 */
@@ -882,6 +1661,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1}
         },
     }
index 255d1e488d879d3fe9a901d62806db7e3d7c80d9..0a6c4dbb074be42b8894d69e3b19cb9f5599dae1 100644 (file)
 */\r
 \r
 #include <ti/sdo/edma3/rm/edma3_rm.h>\r
+#ifdef BUILD_TDA2XX_IPU\r
+#include <ti/sysbios/family/arm/ducati/Core.h> \r
 \r
+#endif\r
 /* Number of EDMA3 controllers present in the system */\r
-#define NUM_EDMA3_INSTANCES         1U\r
+#define NUM_EDMA3_INSTANCES         3U\r
 const uint32_t numEdma3Instances = NUM_EDMA3_INSTANCES;\r
 \r
 /* Number of DSPs present in the system */\r
@@ -160,28 +163,129 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_NUM_QDMA_CHANNELS                         (8U)\r
 \r
 /** Number of Event Queues available                                          */\r
-#define EDMA3_0_NUM_EVTQUE                              (4U)\r
+#define EDMA3_NUM_EVTQUE                                (4U)\r
 \r
 /** Number of Transfer Controllers available                                  */\r
-#define EDMA3_0_NUM_TC                                  (4U)\r
+#define EDMA3_NUM_TC                                    (2U)\r
 \r
 /** Number of Regions                                                         */\r
-#define EDMA3_0_NUM_REGIONS                             (2U)\r
-\r
-\r
-/** Interrupt no. for Transfer Completion                                     */\r
-#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34U)\r
-/** Interrupt no. for CC Error                                                */\r
-#define EDMA3_0_CC_ERROR_INT                            (35U)\r
-/** Interrupt no. for TCs Error                                               */\r
-#define EDMA3_0_TC0_ERROR_INT                           (36U)\r
-#define EDMA3_0_TC1_ERROR_INT                           (37U)\r
-#define EDMA3_0_TC2_ERROR_INT                           (0U)\r
-#define EDMA3_0_TC3_ERROR_INT                           (0U)\r
-#define EDMA3_0_TC4_ERROR_INT                           (0U)\r
-#define EDMA3_0_TC5_ERROR_INT                           (0U)\r
-#define EDMA3_0_TC6_ERROR_INT                           (0U)\r
-#define EDMA3_0_TC7_ERROR_INT                           (0U)\r
+#define EDMA3_NUM_REGIONS                               (8U)\r
+\r
+/** Interrupt no. for Transfer Completion */\r
+#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33U)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_EVE                (8U)\r
+\r
+/** Based on the interrupt number to be mapped define the XBAR instance number */\r
+#define COMPLETION_INT_A15_XBAR_INST_NO                 (29U)\r
+#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7U)\r
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12U)\r
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11U)\r
+\r
+/** Interrupt no. for CC Error */\r
+#define EDMA3_CC_ERROR_INT_A15                          (67U)\r
+#define EDMA3_CC_ERROR_INT_DSP                          (39U)\r
+#define EDMA3_CC_ERROR_INT_IPU                          (35U)\r
+#define EDMA3_CC_ERROR_INT_EVE                          (23U)\r
+\r
+/** Based on the interrupt number to be mapped define the XBAR instance number */\r
+#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30U)\r
+#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8U)\r
+#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13U)\r
+\r
+/** Interrupt no. for TCs Error */\r
+#define EDMA3_TC0_ERROR_INT_A15                         (68U)\r
+#define EDMA3_TC0_ERROR_INT_DSP                         (40U)\r
+#define EDMA3_TC0_ERROR_INT_IPU                         (36U)\r
+#define EDMA3_TC0_ERROR_INT_EVE                         (24U)\r
+#define EDMA3_TC1_ERROR_INT_A15                         (69U)\r
+#define EDMA3_TC1_ERROR_INT_DSP                         (41U)\r
+#define EDMA3_TC1_ERROR_INT_IPU                         (37U)\r
+#define EDMA3_TC1_ERROR_INT_EVE                         (25U)\r
+\r
+/** Based on the interrupt number to be mapped define the XBAR instance number */\r
+#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31U)\r
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9U) \r
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14U)\r
+#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32U)\r
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10U)\r
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15U)\r
+\r
+#ifdef BUILD_TDA2XX_MPU\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_A15)\r
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_A15)\r
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_A15_XBAR_INST_NO)\r
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_A15)\r
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_A15)\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
+\r
+#elif defined BUILD_TDA2XX_DSP\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_DSP)\r
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_DSP)\r
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_DSP_XBAR_INST_NO)\r
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_DSP)\r
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_DSP)\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_DSP_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_DSP_XBAR_INST_NO)\r
+\r
+#elif defined BUILD_TDA2XX_IPU\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_IPU_C0)\r
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_IPU)\r
+#define CC_ERROR_INT_XBAR_INST_NO                       (CC_ERROR_INT_IPU_XBAR_INST_NO)\r
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_IPU)\r
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_IPU)\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_IPU_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_IPU_XBAR_INST_NO)\r
+\r
+#elif defined BUILD_TDA2XX_EVE\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    (EDMA3_CC_XFER_COMPLETION_INT_EVE)\r
+#define EDMA3_CC_ERROR_INT                              (EDMA3_CC_ERROR_INT_EVE)\r
+#define EDMA3_TC0_ERROR_INT                             (EDMA3_TC0_ERROR_INT_EVE)\r
+#define EDMA3_TC1_ERROR_INT                             (EDMA3_TC1_ERROR_INT_EVE)\r
+/* For accessing EVE internal edma, there is no need to configure Xbar */\r
+#define CC_ERROR_INT_XBAR_INST_NO                       (0U)\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      (0U)\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      (0U)\r
+\r
+#else\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    (0U)\r
+#define EDMA3_CC_ERROR_INT                              (0U)\r
+#define CC_ERROR_INT_XBAR_INST_NO                       (0U)\r
+#define EDMA3_TC0_ERROR_INT                             (0U)\r
+#define EDMA3_TC1_ERROR_INT                             (0U)\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      (TC0_ERROR_INT_A15_XBAR_INST_NO)\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      (TC1_ERROR_INT_A15_XBAR_INST_NO)\r
+#endif\r
+\r
+#define EDMA3_TC2_ERROR_INT                             (0U)\r
+#define EDMA3_TC3_ERROR_INT                             (0U)\r
+#define EDMA3_TC4_ERROR_INT                             (0U)\r
+#define EDMA3_TC5_ERROR_INT                             (0U)\r
+#define EDMA3_TC6_ERROR_INT                             (0U)\r
+#define EDMA3_TC7_ERROR_INT                             (0U)\r
+\r
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19U)\r
+#define DSP2_EDMA3_CC_XFER_COMPLETION_INT               (20U)\r
+#define DSP1_EDMA3_CC_ERROR_INT                         (27U)\r
+#define DSP1_EDMA3_TC0_ERROR_INT                        (28U)\r
+#define DSP1_EDMA3_TC1_ERROR_INT                        (29U)\r
+\r
+/** XBAR interrupt source index numbers for EDMA interrupts */\r
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367U)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368U)\r
+\r
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359U)\r
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370U)\r
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371U)\r
 \r
 /**\r
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
@@ -199,38 +303,42 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  */\r
 /* EDMA 0 */\r
 \r
-#define EDMA3_0_HWI_INT_XFER_COMP                           (7U)\r
-#define EDMA3_0_HWI_INT_CC_ERR                              (7U)\r
-#define EDMA3_0_HWI_INT_TC0_ERR                             (7U)\r
-#define EDMA3_0_HWI_INT_TC1_ERR                             (7U)\r
-#define EDMA3_0_HWI_INT_TC2_ERR                             (7U)\r
-#define EDMA3_0_HWI_INT_TC3_ERR                             (7U)\r
-\r
+#define EDMA3_HWI_INT_XFER_COMP                           (7U)\r
+#define EDMA3_HWI_INT_CC_ERR                              (7U)\r
+#define EDMA3_HWI_INT_TC0_ERR                             (10U)\r
+#define EDMA3_HWI_INT_TC1_ERR                             (10U)\r
+#define EDMA3_HWI_INT_TC2_ERR                             (10U)\r
+#define EDMA3_HWI_INT_TC3_ERR                             (10U)\r
 \r
 /**\r
  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
  * various peripherals, which use EDMA for data transfer.\r
  * All channels need not be mapped, some can be free also.\r
  * 1: Mapped\r
- * 0: Not mapped\r
+ * 0: Not mapped (channel available)\r
  *\r
  * This mapping will be used to allocate DMA channels when user passes\r
  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
  * copy). The same mapping is used to allocate the TCC when user passes\r
  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
+ * \r
+ * For Vayu Since the xbar can be used to map event to any EDMA channel,\r
+ * If the application is assigning events to other channel this variable \r
+ * should be modified\r
  *\r
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
  */\r
                                                       /* 31     0 */\r
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x3FC0C06EU)  /* TBD */\r
-\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06EU)  /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFU)  /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA        (0x00000000U)  /* TBD */\r
 \r
 /**\r
  * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
  * various peripherals, which use EDMA for data transfer.\r
  * All channels need not be mapped, some can be free also.\r
  * 1: Mapped\r
- * 0: Not mapped\r
+ * 0: Not mapped (channel available)\r
  *\r
  * This mapping will be used to allocate DMA channels when user passes\r
  * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
@@ -239,17 +347,23 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  *\r
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
  */\r
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xF3FFFFFCU) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCU) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000U) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA        (0x00000000U) /* TBD */\r
 \r
 \r
 /* Variable which will be used internally for referring number of Event Queues*/\r
 uint32_t numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
-                                                        EDMA3_0_NUM_EVTQUE,\r
+                                                        EDMA3_NUM_EVTQUE,\r
+                                                        EDMA3_NUM_EVTQUE,\r
+                                                        EDMA3_NUM_EVTQUE\r
                                                     };\r
 \r
 /* Variable which will be used internally for referring number of TCs.        */\r
 uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
-                                                    EDMA3_0_NUM_TC,\r
+                                                    EDMA3_NUM_TC,\r
+                                                    EDMA3_NUM_TC,\r
+                                                    EDMA3_NUM_TC\r
                                                 };\r
 \r
 /**\r
@@ -258,61 +372,204 @@ uint32_t numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
  */\r
 uint32_t ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
 {\r
+    /* EDMA3 INSTANCE# 0 */\r
+    {\r
+        EDMA3_CC_XFER_COMPLETION_INT_A15,\r
+        EDMA3_CC_XFER_COMPLETION_INT_A15,\r
+               EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
+        EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
+               EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
+        EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
+        EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
+        EDMA3_CC_XFER_COMPLETION_INT_IPU_C1\r
+    },\r
+    /* EDMA3 INSTANCE# 1 */\r
+    {\r
+        0U,\r
+        0U,\r
+        DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
+        DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U\r
+    },\r
+    /* EDMA3 INSTANCE# 2 */\r
+    {\r
+        0U,\r
+        /* Region 1 (Associated to EVE core)*/\r
+        EDMA3_CC_XFER_COMPLETION_INT_EVE,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+    }\r
+};\r
+/** These are the Xbar instance numbers corresponding to interrupt numbers */\r
+uint32_t ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+    /* EDMA3 INSTANCE# 0 */\r
+    {\r
+        COMPLETION_INT_A15_XBAR_INST_NO,\r
+        COMPLETION_INT_A15_XBAR_INST_NO,\r
+               COMPLETION_INT_DSP_XBAR_INST_NO,\r
+        COMPLETION_INT_DSP_XBAR_INST_NO,\r
+               COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
+        COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
+        COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
+        COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
+    },\r
+    /* EDMA3 INSTANCE# 1 */\r
     {\r
-        0U, EDMA3_0_CC_XFER_COMPLETION_INT, 0U, 0U, 0U, 0U, 0U, 0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U\r
     },\r
+    /* EDMA3 INSTANCE# 2 */\r
+    {\r
+     /* \r
+      * For accessing EVE internal edma,\r
+      * there is no need to configure Xbar.\r
+      * So getting to zero.\r
+      */\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U,\r
+        0U\r
+    }\r
 };\r
 \r
 /**\r
  * Variable which will be used internally for referring channel controller's\r
  * error interrupt.\r
  */\r
-uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
-                                                    EDMA3_0_CC_ERROR_INT,\r
-                                               };\r
+uint32_t ccErrorInt[NUM_EDMA3_INSTANCES] = \r
+{\r
+    EDMA3_CC_ERROR_INT,\r
+    DSP1_EDMA3_CC_ERROR_INT,\r
+    EDMA3_CC_ERROR_INT\r
+};\r
 \r
 /**\r
  * Variable which will be used internally for referring transfer controllers'\r
  * error interrupts.\r
  */\r
-uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
+uint32_t tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
 {\r
-   {\r
-       EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,\r
-       EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,\r
-       EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,\r
-       EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,\r
-   }\r
+    /* EDMA3 INSTANCE# 0 */\r
+    {\r
+        EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
+        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+        EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
+    },\r
+    /* EDMA3 INSTANCE# 1 */\r
+    {\r
+        DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
+        EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
+        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+    },\r
+    /* EDMA3 INSTANCE# 2 */\r
+    {\r
+        EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
+        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+        EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
+    }\r
 };\r
 \r
 /**\r
  * Variables which will be used internally for referring the hardware interrupt\r
  * for various EDMA3 interrupts.\r
  */\r
-uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
-                                                    EDMA3_0_HWI_INT_XFER_COMP\r
-                                                  };\r
-\r
-uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
-                                                   EDMA3_0_HWI_INT_CC_ERR\r
-                                               };\r
-\r
-uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
-                                                     {\r
-                                                        EDMA3_0_HWI_INT_TC0_ERR,\r
-                                                        EDMA3_0_HWI_INT_TC1_ERR,\r
-                                                        EDMA3_0_HWI_INT_TC2_ERR,\r
-                                                        EDMA3_0_HWI_INT_TC3_ERR,\r
-                                                        0U,\r
-                                                        0U,\r
-                                                        0U,\r
-                                                        0U\r
-                                                     }\r
-                                               };\r
+uint32_t hwIntXferComp[NUM_EDMA3_INSTANCES] =\r
+{\r
+    EDMA3_HWI_INT_XFER_COMP,\r
+    EDMA3_HWI_INT_XFER_COMP,\r
+    EDMA3_CC_XFER_COMPLETION_INT\r
+};\r
+\r
+uint32_t hwIntCcErr[NUM_EDMA3_INSTANCES] =\r
+{\r
+    EDMA3_HWI_INT_CC_ERR,\r
+    EDMA3_HWI_INT_CC_ERR,\r
+    EDMA3_CC_ERROR_INT\r
+};\r
+\r
+uint32_t hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+    /* EDMA3 INSTANCE# 0 */\r
+    {\r
+         EDMA3_HWI_INT_TC0_ERR ,\r
+         EDMA3_HWI_INT_TC1_ERR ,\r
+         EDMA3_HWI_INT_TC2_ERR ,\r
+         EDMA3_HWI_INT_TC3_ERR ,\r
+         0U ,\r
+         0U ,\r
+         0U ,\r
+         0U \r
+    },\r
+    /* EDMA3 INSTANCE# 1 */\r
+    {\r
+         EDMA3_HWI_INT_TC0_ERR ,\r
+         EDMA3_HWI_INT_TC1_ERR ,\r
+         EDMA3_HWI_INT_TC2_ERR ,\r
+         EDMA3_HWI_INT_TC3_ERR ,\r
+         0U ,\r
+         0U ,\r
+         0U ,\r
+         0U \r
+    },\r
+    /* EDMA3 INSTANCE# 2 */\r
+    {\r
+         EDMA3_TC0_ERROR_INT ,\r
+         EDMA3_TC1_ERROR_INT ,\r
+         EDMA3_TC2_ERROR_INT ,\r
+         EDMA3_TC3_ERROR_INT ,\r
+         0U ,\r
+         0U ,\r
+         0U ,\r
+         0U \r
+    }\r
+};\r
 \r
+/**\r
+ * \brief Base address as seen from the different cores may be different\r
+ * And is defined based on the core\r
+ */\r
+#if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP))\r
 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
+#elif (defined BUILD_TDA2XX_IPU)\r
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x63300000))\r
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x63400000))\r
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x63500000))\r
+#elif (defined BUILD_TDA2XX_EVE)\r
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x400A0000))\r
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x40086000))\r
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x40087000))\r
+#else\r
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x0))\r
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x0))\r
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x0))\r
+#endif\r
+\r
+#define DSP1_EDMA3_CC_BASE_ADDR                     ((void *)(0x01D10000))\r
+#define DSP1_EDMA3_TC0_BASE_ADDR                    ((void *)(0x01D05000))\r
+#define DSP1_EDMA3_TC1_BASE_ADDR                    ((void *)(0x01D06000))\r
 /* Driver Object Initialization Configuration                                 */\r
 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
 {\r
@@ -327,11 +584,11 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
         EDMA3_NUM_PARAMSET,\r
         /** Total number of Event Queues in the EDMA3 Controller              */\r
-        EDMA3_0_NUM_EVTQUE,\r
+        EDMA3_NUM_EVTQUE,\r
         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
-        EDMA3_0_NUM_TC,\r
+        EDMA3_NUM_TC,\r
         /** Number of Regions on this EDMA3 controller                        */\r
-        EDMA3_0_NUM_REGIONS,\r
+        EDMA3_NUM_REGIONS,\r
 \r
         /**\r
          * \brief Channel mapping existence\r
@@ -358,19 +615,19 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
             (void *)NULL\r
         },\r
         /** Interrupt no. for Transfer Completion */\r
-        EDMA3_0_CC_XFER_COMPLETION_INT,\r
+        EDMA3_CC_XFER_COMPLETION_INT,\r
         /** Interrupt no. for CC Error */\r
-        EDMA3_0_CC_ERROR_INT,\r
+        EDMA3_CC_ERROR_INT,\r
         /** Interrupt no. for TCs Error */\r
         {\r
-            EDMA3_0_TC0_ERROR_INT,\r
-            EDMA3_0_TC1_ERROR_INT,\r
-            EDMA3_0_TC2_ERROR_INT,\r
-            EDMA3_0_TC3_ERROR_INT,\r
-            EDMA3_0_TC4_ERROR_INT,\r
-            EDMA3_0_TC5_ERROR_INT,\r
-            EDMA3_0_TC6_ERROR_INT,\r
-            EDMA3_0_TC7_ERROR_INT\r
+            EDMA3_TC0_ERROR_INT,\r
+            EDMA3_TC1_ERROR_INT,\r
+            EDMA3_TC2_ERROR_INT,\r
+            EDMA3_TC3_ERROR_INT,\r
+            EDMA3_TC4_ERROR_INT,\r
+            EDMA3_TC5_ERROR_INT,\r
+            EDMA3_TC6_ERROR_INT,\r
+            EDMA3_TC7_ERROR_INT\r
         },\r
 \r
         /**\r
@@ -385,8 +642,8 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
         {\r
             0U,\r
             1U,\r
-            2U,\r
-            3U,\r
+            0U,\r
+            0U,\r
             0U,\r
             0U,\r
             0U,\r
@@ -403,8 +660,8 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
         {\r
             16U,\r
             16U,\r
-            16U,\r
-            16U,\r
+            0U,\r
+            0U,\r
             0U,\r
             0U,\r
             0U,\r
@@ -433,15 +690,39 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * if it exists, otherwise of no use.\r
          */\r
             {\r
-            0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U,\r
-            8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U,\r
-            16U, 17U, 18U, 19U, 20U, 21U, 22U, 23U,\r
-            24U, 25U, 26U, 27U, 28U, 29U, 30U, 31U,\r
-            32U, 33U, 34U, 35U, 36U, 37U, 38U, 39U, \r
-            40U, 41U, 42U, 43U, 44U, 45U, 46U, 47U,\r
-            48U, 49U, 50U, 51U, 52U, 53U, 54U, 55U,\r
-            56U, 57U, 58U, 59U, 60U, 61U, 62U, 63U\r
-            },\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
+                       },\r
 \r
          /**\r
           * \brief Mapping from each DMA channel to a TCC. This specific\r
@@ -449,22 +730,22 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
           * on the mapped channel.\r
           */\r
             {\r
-            0U, 1U, 2U, 3U,\r
-            4U, 5U, 6U, 7U,\r
-            8U, 9U, 10U, 11U,\r
-            12U, 13U, 14U, 15U,\r
-            16U, 17U, 18U, 19U,\r
-            20U, 21U, 22U, 23U,\r
-            24U, 25U, 26U, 27U,\r
-            28U, 29U, 30U, 31U,\r
-            32U, 33U, 34U, 35U,\r
-            36U, 37U, 38U, 39U,\r
-            40U, 41U, 42U, 43U,\r
-            44U, 45U, 46U, 47U,\r
-            48U, 49U, 50U, 51U,\r
-            52U, 53U, 54U, 55U,\r
-            56U, 57U, 58U, 59U,\r
-            60U, 61U, 62U, 63U\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
             },\r
 \r
         /**\r
@@ -473,67 +754,501 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * All channels need not be mapped, some can be free also.\r
          */\r
             {\r
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,\r
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA\r
             }\r
         },\r
+    {\r
+        /* EDMA3 INSTANCE# 1 */\r
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
+        EDMA3_NUM_DMA_CHANNELS,\r
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
+        EDMA3_NUM_QDMA_CHANNELS,\r
+        /** Total number of TCCs supported by the EDMA3 Controller            */\r
+        EDMA3_NUM_TCC,\r
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
+        EDMA3_NUM_PARAMSET,\r
+        /** Total number of Event Queues in the EDMA3 Controller              */\r
+        EDMA3_NUM_EVTQUE,\r
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
+        EDMA3_NUM_TC,\r
+        /** Number of Regions on this EDMA3 controller                        */\r
+        EDMA3_NUM_REGIONS,\r
 \r
-};\r
+        /**\r
+         * \brief Channel mapping existence\r
+         * A value of 0 (No channel mapping) implies that there is fixed association\r
+         * for a channel number to a parameter entry number or, in other words,\r
+         * PaRAM entry n corresponds to channel n.\r
+         */\r
+        1U,\r
 \r
+        /** Existence of memory protection feature */\r
+        0U,\r
 \r
-/* Driver Instance Initialization Configuration */\r
-EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
-{\r
-    /* EDMA3 INSTANCE# 0 */\r
-               {\r
-                       /* Resources owned/reserved by region 0 (Associated to any MPU core)*/\r
-                       {\r
-                               /* ownPaRAMSets */\r
-                               /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
-                               /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
-                               /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
-                               /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+        /** Global Register Region of CC Registers */\r
+        DSP1_EDMA3_CC_BASE_ADDR,\r
+        /** Transfer Controller (TC) Registers */\r
+        {\r
+               DSP1_EDMA3_TC0_BASE_ADDR,\r
+               DSP1_EDMA3_TC1_BASE_ADDR,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL\r
+        },\r
+        /** Interrupt no. for Transfer Completion */\r
+        DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
+        /** Interrupt no. for CC Error */\r
+        DSP1_EDMA3_CC_ERROR_INT,\r
+        /** Interrupt no. for TCs Error */\r
+        {\r
+            DSP1_EDMA3_TC0_ERROR_INT,\r
+            DSP1_EDMA3_TC1_ERROR_INT,\r
+            EDMA3_TC2_ERROR_INT,\r
+            EDMA3_TC3_ERROR_INT,\r
+            EDMA3_TC4_ERROR_INT,\r
+            EDMA3_TC5_ERROR_INT,\r
+            EDMA3_TC6_ERROR_INT,\r
+            EDMA3_TC7_ERROR_INT\r
+        },\r
 \r
-                               /* ownDmaChannels */\r
-                               /* 31     0     63    32 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+        /**\r
+         * \brief EDMA3 TC priority setting\r
+         *\r
+         * User can program the priority of the Event Queues\r
+         * at a system-wide level.  This means that the user can set the\r
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+         * relative to IO initiated by the other bus masters on the\r
+         * device (ARM, DSP, USB, etc)\r
+         */\r
+        {\r
+            0U,\r
+            1U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
+        },\r
+        /**\r
+         * \brief To Configure the Threshold level of number of events\r
+         * that can be queued up in the Event queues. EDMA3CC error register\r
+         * (CCERR) will indicate whether or not at any instant of time the\r
+         * number of events queued up in any of the event queues exceeds\r
+         * or equals the threshold/watermark value that is set\r
+         * in the queue watermark threshold register (QWMTHRA).\r
+         */\r
+        {\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
+        },\r
 \r
-                               /* ownQdmaChannels */\r
-                               /* 31     0 */\r
-                               {0x000000FFU},\r
+        /**\r
+         * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+         * An optimally-sized command is defined by the transfer controller\r
+         * default burst size (DBS). Different TCs can have different\r
+         * DBS values. It is defined in Bytes.\r
+         */\r
+            {\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
+            },\r
 \r
-                               /* ownTccs */\r
-                               /* 31     0     63    32 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+        /**\r
+         * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+         * if it exists, otherwise of no use.\r
+         */\r
+            {\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
+            },\r
 \r
-                               /* resvdPaRAMSets */\r
-                               /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
-                               /* 159  128     191  160     223  192     255  224 */\r
-                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
-                               /* 287  256     319  288     351  320     383  352 */\r
-                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
-                               /* 415  384     447  416     479  448     511  480 */\r
-                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+         /**\r
+          * \brief Mapping from each DMA channel to a TCC. This specific\r
+          * TCC code will be returned when the transfer is completed\r
+          * on the mapped channel.\r
+          */\r
+            {\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+            },\r
 \r
-                               /* resvdDmaChannels */\r
-                               /* 31     0     63    32 */\r
-                               {0x00U, 0x00U},\r
+        /**\r
+         * \brief Mapping of DMA channels to Hardware Events from\r
+         * various peripherals, which use EDMA for data transfer.\r
+         * All channels need not be mapped, some can be free also.\r
+         */\r
+            {\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA,\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
+            }\r
+    },\r
+    {\r
+        /* EDMA3 INSTANCE# 2 */\r
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
+        EDMA3_NUM_DMA_CHANNELS,\r
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
+        EDMA3_NUM_QDMA_CHANNELS,\r
+        /** Total number of TCCs supported by the EDMA3 Controller            */\r
+        EDMA3_NUM_TCC,\r
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
+        EDMA3_NUM_PARAMSET,\r
+        /** Total number of Event Queues in the EDMA3 Controller              */\r
+        EDMA3_NUM_EVTQUE,\r
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
+        EDMA3_NUM_TC,\r
+        /** Number of Regions on this EDMA3 controller                        */\r
+        EDMA3_NUM_REGIONS,\r
 \r
-                               /* resvdQdmaChannels */\r
-                               /* 31     0 */\r
-                               {0x00U},\r
+        /**\r
+         * \brief Channel mapping existence\r
+         * A value of 0 (No channel mapping) implies that there is fixed association\r
+         * for a channel number to a parameter entry number or, in other words,\r
+         * PaRAM entry n corresponds to channel n.\r
+         */\r
+        1U,\r
 \r
-                               /* resvdTccs */\r
-                               /* 31     0     63    32 */\r
-                               {0x00U, 0x00U},\r
+        /** Existence of memory protection feature */\r
+        0U,\r
+\r
+        /** Global Register Region of CC Registers */\r
+        EDMA3_CC_BASE_ADDR,\r
+        /** Transfer Controller (TC) Registers */\r
+        {\r
+               EDMA3_TC0_BASE_ADDR,\r
+               EDMA3_TC1_BASE_ADDR,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL\r
+        },\r
+        /** Interrupt no. for Transfer Completion */\r
+        EDMA3_CC_XFER_COMPLETION_INT,\r
+        /** Interrupt no. for CC Error */\r
+        EDMA3_CC_ERROR_INT,\r
+        /** Interrupt no. for TCs Error */\r
+        {\r
+            EDMA3_TC0_ERROR_INT,\r
+            EDMA3_TC1_ERROR_INT,\r
+            EDMA3_TC2_ERROR_INT,\r
+            EDMA3_TC3_ERROR_INT,\r
+            EDMA3_TC4_ERROR_INT,\r
+            EDMA3_TC5_ERROR_INT,\r
+            EDMA3_TC6_ERROR_INT,\r
+            EDMA3_TC7_ERROR_INT\r
+        },\r
+\r
+        /**\r
+         * \brief EDMA3 TC priority setting\r
+         *\r
+         * User can program the priority of the Event Queues\r
+         * at a system-wide level.  This means that the user can set the\r
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+         * relative to IO initiated by the other bus masters on the\r
+         * device (ARM, DSP, USB, etc)\r
+         */\r
+        {\r
+            0U,\r
+            1U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
+        },\r
+        /**\r
+         * \brief To Configure the Threshold level of number of events\r
+         * that can be queued up in the Event queues. EDMA3CC error register\r
+         * (CCERR) will indicate whether or not at any instant of time the\r
+         * number of events queued up in any of the event queues exceeds\r
+         * or equals the threshold/watermark value that is set\r
+         * in the queue watermark threshold register (QWMTHRA).\r
+         */\r
+        {\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
+        },\r
+\r
+        /**\r
+         * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+         * An optimally-sized command is defined by the transfer controller\r
+         * default burst size (DBS). Different TCs can have different\r
+         * DBS values. It is defined in Bytes.\r
+         */\r
+            {\r
+            16U,\r
+            16U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U,\r
+            0U\r
+            },\r
+\r
+        /**\r
+         * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+         * if it exists, otherwise of no use.\r
+         */\r
+            {\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
+            },\r
+\r
+         /**\r
+          * \brief Mapping from each DMA channel to a TCC. This specific\r
+          * TCC code will be returned when the transfer is completed\r
+          * on the mapped channel.\r
+          */\r
+            {\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+            },\r
+\r
+        /**\r
+         * \brief Mapping of DMA channels to Hardware Events from\r
+         * various peripherals, which use EDMA for data transfer.\r
+         * All channels need not be mapped, some can be free also.\r
+         */\r
+            {\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA,\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA\r
+            }\r
+    },\r
+\r
+};\r
+\r
+/**\r
+ * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
+ * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
+ * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
+ * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
+ *\r
+ * Only Resources owned by a perticular core are allocated by Driver\r
+ * Reserved resources are not allocated if requested for any available resource\r
+ */\r
\r
+/* Driver Instance Initialization Configuration */\r
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+    /* EDMA3 INSTANCE# 0 */\r
+               {\r
+                       /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFU},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00U, 0x00U},\r
+                       },\r
+\r
+                       /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+/* \r
+ * This instance 0 and region 1 is only accessible to MPU core 1.\r
+ * So other cores should not be access.\r
+ */\r
+#ifdef BUILD_TDA2XX_MPU\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+#else\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+#endif\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFU},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00U, 0x00U},\r
                        },\r
 \r
-                       /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
+               /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
@@ -559,7 +1274,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -569,7 +1284,54 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
                                {0x00U, 0x00U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFU},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
@@ -580,33 +1342,695 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                {0x00U, 0x00U},\r
                        },\r
 \r
-               /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
+               /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
                                {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFU},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00U, 0x00U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFU},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00U, 0x00U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFU},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00U, 0x00U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFU},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00U, 0x00U},\r
+                       },\r
+           },\r
+               /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
+               {\r
+               /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+                       },\r
+\r
+                       /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFU},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00U, 0x00U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFU},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00U, 0x00U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+                       },\r
+           },\r
+               /* EDMA3 INSTANCE# 2 EVE EDMA*/\r
+               {\r
+               /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000U, 0x00000000U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 1 (Associated to any EVE core)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFU},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00U},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00U, 0x00U},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFU},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -616,44 +2040,44 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00U, 0x00U},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00U},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00U, 0x00U},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
-               /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
+               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
                        {\r
                                /* ownPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
-                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
-                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 415  384     447  416     479  448     511  480 */\r
-                                0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU},\r
+                                0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U},\r
 \r
                                /* ownDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* ownQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x000000FFU},\r
+                               {0x00000000U},\r
 \r
                                /* ownTccs */\r
                                /* 31     0     63    32 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdPaRAMSets */\r
                                /* 31     0     63    32     95    64     127   96 */\r
-                               {0xFFFFFFFFU, 0xFFFFFFFFU, 0x00000000U, 0x00000000U,\r
+                               {0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 159  128     191  160     223  192     255  224 */\r
                                 0x00000000U, 0x00000000U, 0x00000000U, 0x00000000U,\r
                                /* 287  256     319  288     351  320     383  352 */\r
@@ -663,15 +2087,15 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 \r
                                /* resvdDmaChannels */\r
                                /* 31     0     63    32 */\r
-                               {0x00U, 0x00U},\r
+                               {0x00000000U, 0x00000000U},\r
 \r
                                /* resvdQdmaChannels */\r
                                /* 31     0 */\r
-                               {0x00U},\r
+                               {0x00000000U},\r
 \r
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
-                               {0x00U, 0x00U},\r
+                               {0x00000000U, 0x00000000U},\r
                        },\r
 \r
                /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
@@ -860,8 +2284,8 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                /* resvdTccs */\r
                                /* 31     0     63    32 */\r
                                {0x00000000U, 0x00000000U},\r
-        },\r
-    },\r
+                       },\r
+           },\r
 };\r
 \r
 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
@@ -874,6 +2298,194 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 1 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 2 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 3 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 4 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 5 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 6 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 7 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+    },\r
+    \r
+    /* EDMA3 INSTANCE# 1 */\r
+    {\r
+        /* Event to channel map for region 0 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 1 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 2 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 3 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 4 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 5 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 6 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+        /* Event to channel map for region 7 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
+        },\r
+    },\r
+    \r
+    /* EDMA3 INSTANCE# 2 */\r
+    {\r
+        /* Event to channel map for region 0 */\r
+        {\r
+            {-1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1}\r
         },\r
         /* Event to channel map for region 1 */\r
@@ -881,13 +2493,21 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
-            -1, 26, 27, -1, -1, -1, -1}\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1}\r
         },\r
         /* Event to channel map for region 2 */\r
         {\r
             {-1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1}\r
         },\r
         /* Event to channel map for region 3 */\r
@@ -895,6 +2515,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1}\r
         },\r
         /* Event to channel map for region 4 */\r
@@ -902,6 +2526,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1}\r
         },\r
         /* Event to channel map for region 5 */\r
@@ -909,6 +2537,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1}\r
         },\r
         /* Event to channel map for region 6 */\r
@@ -916,6 +2548,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1}\r
         },\r
         /* Event to channel map for region 7 */\r
@@ -923,6 +2559,10 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES]
             {-1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
             -1, -1, -1, -1, -1, -1, -1}\r
         },\r
     }\r
index 568ce0de4302467152d9e4ac0dac77d13f5b4478..e27db93e13bb1b2a79640dd96d302889fc4fcd7c 100644 (file)
 */
 
 #include <ti/sdo/edma3/rm/edma3_rm.h>
+#ifdef BUILD_DRA72X_IPU
+#include <ti/sysbios/family/arm/ducati/Core.h>
+
+#endif
 
 #define NUM_SHADOW_REGIONS                      (8u)
 
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         1u
+#define NUM_EDMA3_INSTANCES         2u
 
 /** Number of PaRAM Sets available                                            */
 #define EDMA3_NUM_PARAMSET                              (512u)
 #define EDMA3_NUM_QDMA_CHANNELS                         (8u)
 
 /** Number of Event Queues available                                          */
-#define EDMA3_0_NUM_EVTQUE                              (4u)
+#define EDMA3_NUM_EVTQUE                                (4u)
 
 /** Number of Transfer Controllers available                                  */
-#define EDMA3_0_NUM_TC                                  (4u)
+#define EDMA3_NUM_TC                                    (2u)
 
 /** Number of Regions                                                         */
-#define EDMA3_0_NUM_REGIONS                             (2u)
-
-/** Interrupt no. for Transfer Completion                                     */
-#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34u)
-/** Interrupt no. for CC Error                                                */
-#define EDMA3_0_CC_ERROR_INT                            (35u)
-/** Interrupt no. for TCs Error                                               */
-#define EDMA3_0_TC0_ERROR_INT                           (36u)
-#define EDMA3_0_TC1_ERROR_INT                           (37u)
-#define EDMA3_0_TC2_ERROR_INT                           (0u)
-#define EDMA3_0_TC3_ERROR_INT                           (0u)
-#define EDMA3_0_TC4_ERROR_INT                           (0u)
-#define EDMA3_0_TC5_ERROR_INT                           (0u)
-#define EDMA3_0_TC6_ERROR_INT                           (0u)
-#define EDMA3_0_TC7_ERROR_INT                           (0u)
+#define EDMA3_NUM_REGIONS                               (8u)
+
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38u)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0             (34u)
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1             (33u)
+
+/** Based on the interrupt number to be mapped define the XBAR instance number */
+#define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)
+#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7u)
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO              (12u)
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO              (11u)
+
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT_A15                          (67u)
+#define EDMA3_CC_ERROR_INT_DSP                          (39u)
+#define EDMA3_CC_ERROR_INT_IPU                          (35u)
+
+/** Based on the interrupt number to be mapped define the XBAR instance number */
+#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)
+#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8u)
+#define CC_ERROR_INT_IPU_XBAR_INST_NO                   (13u)
+
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT_A15                         (68u)
+#define EDMA3_TC0_ERROR_INT_DSP                         (40u)
+#define EDMA3_TC0_ERROR_INT_IPU                         (36u)
+#define EDMA3_TC1_ERROR_INT_A15                         (69u)
+#define EDMA3_TC1_ERROR_INT_DSP                         (41u)
+#define EDMA3_TC1_ERROR_INT_IPU                         (37u)
+
+/** Based on the interrupt number to be mapped define the XBAR instance number */
+#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9u)
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO                  (14u)
+#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10u)
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO                  (15u)
+
+#ifdef BUILD_DRA72X_MPU
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A15
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_A15_XBAR_INST_NO
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A15
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_A15
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+
+#elif defined BUILD_DRA72X_DSP
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_DSP_XBAR_INST_NO
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_DSP
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_DSP
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_DSP_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_DSP_XBAR_INST_NO
+
+#elif defined BUILD_DRA72X_IPU
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU_C0
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU_XBAR_INST_NO
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU_XBAR_INST_NO
+
+#else
+#define EDMA3_CC_XFER_COMPLETION_INT                    (0u)
+#define EDMA3_CC_ERROR_INT                              (0u)
+#define CC_ERROR_INT_XBAR_INST_NO                       (0u)
+#define EDMA3_TC0_ERROR_INT                             (0u)
+#define EDMA3_TC1_ERROR_INT                             (0u)
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO
+#endif
+
+#define EDMA3_TC2_ERROR_INT                             (0u)
+#define EDMA3_TC3_ERROR_INT                             (0u)
+#define EDMA3_TC4_ERROR_INT                             (0u)
+#define EDMA3_TC5_ERROR_INT                             (0u)
+#define EDMA3_TC6_ERROR_INT                             (0u)
+#define EDMA3_TC7_ERROR_INT                             (0u)
+
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (19u)
+#define DSP1_EDMA3_CC_ERROR_INT                         (27u)
+#define DSP1_EDMA3_TC0_ERROR_INT                        (28u)
+#define DSP1_EDMA3_TC1_ERROR_INT                        (29u)
 
 /** XBAR interrupt source index numbers for EDMA interrupts */
 #define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)
 #define XBAR_EDMA_TC0_IRQ_ERR                           (370u)
 #define XBAR_EDMA_TC1_IRQ_ERR                           (371u)
 
+/**
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+ * ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file.
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+ * to transfer completion interrupt.
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+ * to CC error interrupts.
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+ * to TC error interrupts.
+ */
+/* EDMA 0 */
+
+#define EDMA3_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_HWI_INT_CC_ERR                              (7u)
+#define EDMA3_HWI_INT_TC0_ERR                             (10u)
+#define EDMA3_HWI_INT_TC1_ERR                             (10u)
+#define EDMA3_HWI_INT_TC2_ERR                             (10u)
+#define EDMA3_HWI_INT_TC3_ERR                             (10u)
+
 /**
  * \brief Mapping of DMA channels 0-31 to Hardware Events from
  * various peripherals, which use EDMA for data transfer.
  * copy). The same mapping is used to allocate the TCC when user passes
  * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
  *
+ * For Vayu Since the xbar can be used to map event to any EDMA channel,
+ * If the application is assigning events to other channel this variable
+ * should be modified
+ *
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
-                                                /* 31     0 */
-#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0        (0x00000000u)
+                                                      /* 31     0 */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA       (0x3FC0C06Eu)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA        (0x000FFFFFu)  /* TBD */
 
 
 /**
  *
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
-#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1        (0x00000000u)
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA       (0xF3FFFFFCu) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA        (0x00000000u) /* TBD */
 
 
 
  * \brief Base address as seen from the different cores may be different
  * And is defined based on the core
  */
+#if ((defined BUILD_DRA72X_MPU) || (defined BUILD_DRA72X_DSP))
 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))
 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))
 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))
-EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
+#elif (defined BUILD_DRA72X_IPU)
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x63300000))
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x63400000))
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x63500000))
+#else
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x0))
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x0))
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x0))
+#endif
+
+#define DSP1_EDMA3_CC_BASE_ADDR                     ((void *)(0x01D10000))
+#define DSP1_EDMA3_TC0_BASE_ADDR                    ((void *)(0x01D05000))
+#define DSP1_EDMA3_TC1_BASE_ADDR                    ((void *)(0x01D06000))
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
 {
-    /* EDMA3 INSTANCE# 0 */
     {
-    /** Total number of DMA Channels supported by the EDMA3 Controller */
-    EDMA3_NUM_DMA_CHANNELS,
-    /** Total number of QDMA Channels supported by the EDMA3 Controller */
-    EDMA3_NUM_QDMA_CHANNELS,
-    /** Total number of TCCs supported by the EDMA3 Controller */
-    EDMA3_NUM_TCC,
-    /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-    EDMA3_NUM_PARAMSET,
-    /** Total number of Event Queues in the EDMA3 Controller */
-    EDMA3_0_NUM_EVTQUE,
-    /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-    EDMA3_0_NUM_TC,
-    /** Number of Regions on this EDMA3 controller */
-    EDMA3_0_NUM_REGIONS,
-
-    /**
-     * \brief Channel mapping existence
-     * A value of 0 (No channel mapping) implies that there is fixed association
-     * for a channel number to a parameter entry number or, in other words,
-     * PaRAM entry n corresponds to channel n.
-     */
-    0u,
-
-    /** Existence of memory protection feature */
-    0u,
+        /* EDMA3 INSTANCE# 0 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        EDMA3_NUM_DMA_CHANNELS,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        EDMA3_NUM_QDMA_CHANNELS,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        EDMA3_NUM_TCC,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        EDMA3_NUM_PARAMSET,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        EDMA3_NUM_EVTQUE,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        EDMA3_NUM_TC,
+        /** Number of Regions on this EDMA3 controller                        */
+        EDMA3_NUM_REGIONS,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        1u,
+
+        /** Existence of memory protection feature */
+        0u,
 
         /** Global Register Region of CC Registers */
         EDMA3_CC_BASE_ADDR,
@@ -179,131 +301,349 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
             (void *)NULL,
             (void *)NULL
         },
-    /** Interrupt no. for Transfer Completion */
-    EDMA3_0_CC_XFER_COMPLETION_INT,
-    /** Interrupt no. for CC Error */
-    EDMA3_0_CC_ERROR_INT,
-    /** Interrupt no. for TCs Error */
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
         {
-        EDMA3_0_TC0_ERROR_INT,
-        EDMA3_0_TC1_ERROR_INT,
-        EDMA3_0_TC2_ERROR_INT,
-        EDMA3_0_TC3_ERROR_INT,
-        EDMA3_0_TC4_ERROR_INT,
-        EDMA3_0_TC5_ERROR_INT,
-        EDMA3_0_TC6_ERROR_INT,
-        EDMA3_0_TC7_ERROR_INT
+            EDMA3_TC0_ERROR_INT,
+            EDMA3_TC1_ERROR_INT,
+            EDMA3_TC2_ERROR_INT,
+            EDMA3_TC3_ERROR_INT,
+            EDMA3_TC4_ERROR_INT,
+            EDMA3_TC5_ERROR_INT,
+            EDMA3_TC6_ERROR_INT,
+            EDMA3_TC7_ERROR_INT
         },
 
-   /**
-     * \brief EDMA3 TC priority setting
-     *
-     * User can program the priority of the Event Queues
-     * at a system-wide level.  This means that the user can set the
-     * priority of an IO initiated by either of the TCs (Transfer Controllers)
-     * relative to IO initiated by the other bus masters on the
-     * device (ARM, DSP, USB, etc)
-     */
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
         {
-        0u,
-        1u,
-        2u,
-        3u,
-        0u,
-        0u,
-        0u,
-        0u
+            0u,
+            1u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
         },
-    /**
-     * \brief To Configure the Threshold level of number of events
-     * that can be queued up in the Event queues. EDMA3CC error register
-     * (CCERR) will indicate whether or not at any instant of time the
-     * number of events queued up in any of the event queues exceeds
-     * or equals the threshold/watermark value that is set
-     * in the queue watermark threshold register (QWMTHRA).
-     */
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
         {
-        16u,
-        16u,
-        16u,
-        16u,
-        0u,
-        0u,
-        0u,
-        0u
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
         },
 
-    /**
-     * \brief To Configure the Default Burst Size (DBS) of TCs.
-     * An optimally-sized command is defined by the transfer controller
-     * default burst size (DBS). Different TCs can have different
-     * DBS values. It is defined in Bytes.
-     */
-        {
-        16u,
-        16u,
-        16u,
-        16u,
-        0u,
-        0u,
-        0u,
-        0u
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+                       EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+                       },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+                       EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_SYSTEDMA,
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_SYSTEDMA
+            }
         },
+    {
+        /* EDMA3 INSTANCE# 1 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        EDMA3_NUM_DMA_CHANNELS,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        EDMA3_NUM_QDMA_CHANNELS,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        EDMA3_NUM_TCC,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        EDMA3_NUM_PARAMSET,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        EDMA3_NUM_EVTQUE,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        EDMA3_NUM_TC,
+        /** Number of Regions on this EDMA3 controller                        */
+        EDMA3_NUM_REGIONS,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        1u,
+
+        /** Existence of memory protection feature */
+        0u,
 
-    /**
-     * \brief Mapping from each DMA channel to a Parameter RAM set,
-     * if it exists, otherwise of no use.
-     */
+        /** Global Register Region of CC Registers */
+        DSP1_EDMA3_CC_BASE_ADDR,
+        /** Transfer Controller (TC) Registers */
+        {
+               DSP1_EDMA3_TC0_BASE_ADDR,
+               DSP1_EDMA3_TC1_BASE_ADDR,
+               (void *)NULL,
+               (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        DSP1_EDMA3_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        DSP1_EDMA3_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
         {
-        0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            DSP1_EDMA3_TC0_ERROR_INT,
+            DSP1_EDMA3_TC1_ERROR_INT,
+            EDMA3_TC2_ERROR_INT,
+            EDMA3_TC3_ERROR_INT,
+            EDMA3_TC4_ERROR_INT,
+            EDMA3_TC5_ERROR_INT,
+            EDMA3_TC6_ERROR_INT,
+            EDMA3_TC7_ERROR_INT
         },
 
-     /**
-      * \brief Mapping from each DMA channel to a TCC. This specific
-      * TCC code will be returned when the transfer is completed
-      * on the mapped channel.
-      */
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
         {
-        0u, 1u, 2u, 3u,
-        4u, 5u, 6u, 7u,
-        8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u,
-        20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        24u, 25u, 26u, 27u,
-        28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
+            0u,
+            1u,
+            0u,
+            0u,
+