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raw | patch | inline | side by side (parent: d080f5f)
author | Sunil MS <x0190988@ti.com> | |
Mon, 13 Oct 2014 09:23:25 +0000 (14:53 +0530) | ||
committer | Sunil MS <x0190988@ti.com> | |
Tue, 14 Oct 2014 09:22:34 +0000 (14:52 +0530) |
MISRA.ASM.ENCAPS
MISRA.BITS.NOT_UNSIGNED
MISRA.CVALUE.IMPL.CAST
MISRA.DECL.ARRAY_SIZE
MISRA.DEFINE.BADEXP
MISRA.EXPR.PARENS
MISRA.FUNC.NOPROT.DEF
MISRA.FUNC.UNNAMED.PARAMS
MISRA.IF.NO_COMPOUND
MISRA.IF.NO_ELSE
MISRA.INIT.BRACES
MISRA.LITERAL.UNSIGNED.SUFFIX
MISRA.VAR.UNIQUE.STATIC
Signed-off-by: Sunil MS <x0190988@ti.com>
Change-Id: I2fc2bcfe2f56374dbe4b003a98a28f618167785c
MISRA.BITS.NOT_UNSIGNED
MISRA.CVALUE.IMPL.CAST
MISRA.DECL.ARRAY_SIZE
MISRA.DEFINE.BADEXP
MISRA.EXPR.PARENS
MISRA.FUNC.NOPROT.DEF
MISRA.FUNC.UNNAMED.PARAMS
MISRA.IF.NO_COMPOUND
MISRA.IF.NO_ELSE
MISRA.INIT.BRACES
MISRA.LITERAL.UNSIGNED.SUFFIX
MISRA.VAR.UNIQUE.STATIC
Signed-off-by: Sunil MS <x0190988@ti.com>
Change-Id: I2fc2bcfe2f56374dbe4b003a98a28f618167785c
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_arm_int_reg.c | patch | blob | history | |
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_cfg.c | patch | blob | history |
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_arm_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_arm_int_reg.c
index 62a3dc3aebc344dc9ce81e47066f4a94833d41cc..c02f2dfb81264e9a4765c88606f55bd03cb4119a 100644 (file)
*/
void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
{
- (void (*)(uint32_t))&lisrEdma3TC0ErrHandler0,
- (void (*)(uint32_t))&lisrEdma3TC1ErrHandler0,
- (void (*)(uint32_t))&lisrEdma3TC2ErrHandler0,
- (void (*)(uint32_t))&lisrEdma3TC3ErrHandler0,
- (void (*)(uint32_t))&lisrEdma3TC4ErrHandler0,
- (void (*)(uint32_t))&lisrEdma3TC5ErrHandler0,
- (void (*)(uint32_t))&lisrEdma3TC6ErrHandler0,
- (void (*)(uint32_t))&lisrEdma3TC7ErrHandler0,
+ &lisrEdma3TC0ErrHandler0,
+ &lisrEdma3TC1ErrHandler0,
+ &lisrEdma3TC2ErrHandler0,
+ &lisrEdma3TC3ErrHandler0,
+ &lisrEdma3TC4ErrHandler0,
+ &lisrEdma3TC5ErrHandler0,
+ &lisrEdma3TC6ErrHandler0,
+ &lisrEdma3TC7ErrHandler0,
};
-extern uint32_t ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern uint32_t ccErrorInt[];
-extern uint32_t tcErrorInt[][EDMA3_MAX_TC];
-extern uint32_t numEdma3Tc[];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
+extern uint32_t numEdma3Tc[EDMA3_MAX_EDMA3_INSTANCES];
/**
* Variables which will be used internally for referring the hardware interrupt
* for various EDMA3 interrupts.
*/
-extern uint32_t hwIntXferComp[];
-extern uint32_t hwIntCcErr[];
-extern uint32_t hwIntTcErr[];
+extern uint32_t hwIntXferComp[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntCcErr[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t hwIntTcErr[EDMA3_MAX_EDMA3_INSTANCES];
extern uint32_t dsp_num;
/* This variable has to be used as an extern */
/* External Instance Specific Configuration Structure */
extern EDMA3_DRV_GblXbarToChanConfigParams
- sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+ sampleXbarChanInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
typedef struct {
volatile Uint32 TPCC_EVTMUX[32];
void Edma3MemProtectionHandler(uint32_t edma3InstanceId);
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma,
+ uint32_t edma3Id);
+
+/** To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (uint32_t edma3Id);
+
+/** To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (uint32_t edma3Id);
+
/** To Register the ISRs with the underlying OS, if required. */
void registerEdma3Interrupts (uint32_t edma3Id)
{
((Hwi_FuncPtr)&lisrEdma3ComplHandler0),
(const Hwi_Params *) (&hwiParams),
&eb);
- if (TRUE == Error_check(&eb))
+ if ((bool)TRUE == Error_check(&eb))
{
System_printf("HWI Create Failed\n",Error_getCode(&eb));
}
(const Hwi_Params *) (&hwiParams),
&eb);
- if (TRUE == Error_check(&eb))
+ if ((bool)TRUE == Error_check(&eb))
{
System_printf("HWI Create Failed\n",Error_getCode(&eb));
}
(ptrEdma3TcIsrHandler[numTc]),
(const Hwi_Params *) (&hwiParams),
&eb);
- if (TRUE == Error_check(&eb))
+ if ((bool)TRUE == Error_check(&eb))
{
System_printf("HWI Create Failed\n",Error_getCode(&eb));
}
/** To Unregister the ISRs with the underlying OS, if previously registered. */
void unregisterEdma3Interrupts (uint32_t edma3Id)
{
- static UInt32 cookie = 0;
+ static UInt32 cookiee = 0;
uint32_t numTc = 0;
/* Disabling the global interrupts */
- cookie = Hwi_disable();
+ cookiee = Hwi_disable();
Hwi_delete(&hwiCCXferCompInt);
Hwi_delete(&hwiCCErrInt);
numTc++;
}
/* Restore interrupts */
- Hwi_restore(cookie);
+ Hwi_restore(cookiee);
}
/**
if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TDA3XX) &&
(chanNum < EDMA3_NUM_TCC))
{
- scrRegOffset = chanNum / 2;
- scrChanOffset = chanNum - (scrRegOffset * 2);
- xBarEvtNum = eventNum + 1;
+ scrRegOffset = chanNum / 2U;
+ scrChanOffset = chanNum - (scrRegOffset * 2U);
+ xBarEvtNum = eventNum + 1U;
switch(scrChanOffset)
{
scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
(xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
break;
- case 1:
+ case 1U:
scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
void Edma3MemProtectionHandler(uint32_t edma3InstanceId)
{
+#ifdef EDMA3_RM_DEBUG
+ /* Added to fix Misra C error */
printf("memory Protection error");
+#endif
}
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda3xx_cfg.c
index 2b5129d0a1af78af15734532119da598bdc0ca24..1066f967999668d1eb24039aa5360c6ea4134400 100644 (file)
#define NUM_DSPS 1U
const uint32_t numDsps = NUM_DSPS;
+#ifdef BUILD_TDA2XX_MPU
+void __inline readProcFeatureReg(void);
+void __inline readProcFeatureReg(void)
+{
+ asm (" push {r0-r2} \n\t"
+ " MRC p15, 0, r0, c0, c0, 5\n\t"
+ " LDR r1, =myCoreNum\n\t"
+ " STR r0, [r1]\n\t"
+ " pop {r0-r2}\n\t");
+}
+#endif
+
/* Determine the processor id by reading DNUM register. */
/* Statically allocate the region numbers with cores. */
int32_t myCoreNum;
#define PID0_ADDRESS 0xE00FFFE0U
#define CORE_ID_C0 0x0
#define CORE_ID_C1 0x1
-uint16_t determineProcId()
+
+int8_t* getGlobalAddr(int8_t* addr);
+
+uint16_t isGblConfigRequired(uint32_t dspNum);
+
+uint16_t determineProcId(void);
+
+uint16_t determineProcId(void)
{
-uint16_t regionNo = numEdma3Instances;
+uint16_t regionNo = (uint16_t)numEdma3Instances;
#ifdef BUILD_TDA2XX_DSP
extern __cregister volatile uint32_t DNUM;
#endif
-myCoreNum = numDsps;
+myCoreNum = (int32_t)numDsps;
#ifdef BUILD_TDA2XX_MPU
- asm (" push {r0-r2} \n\t"
- " MRC p15, 0, r0, c0, c0, 5\n\t"
- " LDR r1, =myCoreNum\n\t"
- " STR r0, [r1]\n\t"
- " pop {r0-r2}\n\t");
+ readProcFeatureReg();
if((myCoreNum & 0x03) == 1)
- regionNo = 1;
+ {
+ regionNo = 1U;
+ }
else
- regionNo = 0;
+ {
+ regionNo = 0U;
+ }
#elif defined(BUILD_TDA2XX_IPU)
myCoreNum = (*(uint32_t *)(PID0_ADDRESS));
if(Core_getIpuId() == 1){
if(myCoreNum == CORE_ID_C0)
- regionNo = 4;
+ {
+ regionNo = 4U;
+ }
else if (myCoreNum == CORE_ID_C1)
- regionNo = 5;
+ {
+ regionNo = 5U;
+ }
+ else
+ {
+ /* Nothing to be done here */
+ }
}
if(Core_getIpuId() == 2){
if(myCoreNum == CORE_ID_C0)
- regionNo = 6;
+ {
+ regionNo = 6U;
+ }
else if (myCoreNum == CORE_ID_C1)
- regionNo = 7;
+ {
+ regionNo = 7U;
+ }
+ else
+ {
+ /* Nothing to be done here */
+ }
}
#elif defined BUILD_TDA2XX_DSP
- myCoreNum = DNUM;
+ myCoreNum = (int32_t)DNUM;
if(myCoreNum == 0)
- regionNo = 2;
+ {
+ regionNo = 2U;
+ }
else
- regionNo = 3;
+ {
+ regionNo = 3U;
+ }
#endif
return regionNo;
}
{
(void) dspNum;
- return 1;
+ return 1U;
}
/* Semaphore handles */
EDMA3_0_HWI_INT_TC0_ERR,
EDMA3_0_HWI_INT_TC1_ERR,
EDMA3_0_HWI_INT_TC2_ERR,
- EDMA3_0_HWI_INT_TC3_ERR
+ EDMA3_0_HWI_INT_TC3_ERR,
+ 0,
+ 0,
+ 0,
+ 0
}
};