Added Vayu support in edma3lld
authorPrasad Konnur <prasadkonnur@ti.com>
Thu, 18 Apr 2013 09:44:08 +0000 (15:14 +0530)
committerPrasad Konnur <prasadkonnur@ti.com>
Thu, 18 Apr 2013 09:44:08 +0000 (15:14 +0530)
Tested on A15, IPU and DSP cores on Zebu
System edma and DSP edma both added

Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
22 files changed:
examples/edma3_driver/evmtda2xx/makefile [new file with mode: 0644]
examples/edma3_driver/evmtda2xx/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmtda2xx/sample_app/linker.cmd [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_A15/rtsc_config/edma3_drv_bios6_tda2xx_a15_st_sample.cfg
examples/edma3_driver/evmtda2xx_M4/makefile
examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_st_sample.cfg
examples/edma3_driver/evmtda2xx_M4/sample_app/linker.cmd
examples/edma3_driver/src/common.c
examples/edma3_driver/src/main.c
makerules/common.mk
makerules/platform.mk
packages/component.mk
packages/makefile
packages/ti/sdo/edma3/drv/package.xs
packages/ti/sdo/edma3/drv/sample/makefile
packages/ti/sdo/edma3/drv/sample/package.xs
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/sample_arm_cs.c
packages/ti/sdo/edma3/rm/package.xs
packages/ti/sdo/edma3/rm/sample/package.xs

diff --git a/examples/edma3_driver/evmtda2xx/makefile b/examples/edma3_driver/evmtda2xx/makefile
new file mode 100644 (file)
index 0000000..24f681d
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_tda2xx_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files 
+#  need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
+              qdma_link_test.c
+CFLAGS_LOCAL_COMMON = -DBUILD_TDA2XX_DSP
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example: 
+#   SRCS_<core/SoC/platform-name> = 
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk 
+#     and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evmtda2xx/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg b/examples/edma3_driver/evmtda2xx/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
new file mode 100644 (file)
index 0000000..228064b
--- /dev/null
@@ -0,0 +1,22 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
+var ECM       = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi   = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Startup   = xdc.useModule ("xdc.runtime.Startup");
+var System    = xdc.useModule ("xdc.runtime.System");
+var Log       = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+Timer.timerSettings[0].intNum = 14;
diff --git a/examples/edma3_driver/evmtda2xx/sample_app/linker.cmd b/examples/edma3_driver/evmtda2xx/sample_app/linker.cmd
new file mode 100644 (file)
index 0000000..1280f81
--- /dev/null
@@ -0,0 +1,7 @@
+SECTIONS
+{
+       .my_sect_iram  > EXT_RAM
+       .my_sect_ddr  > EXT_RAM
+}
+
+
index c24c9d90b6939377c0801d3be4b13a7fff361af3..f5eb28c951ed0f2f18c8d85385a461c8ce3383c7 100644 (file)
@@ -7,9 +7,10 @@ var Log       = xdc.useModule ("xdc.runtime.Log");
 var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');\r
 var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');\r
 var Program     = xdc.useModule("xdc.cfg.Program");\r
-//var Cache = xdc.useModule('ti.sysbios.hal.Cache');\r
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');\r
 var Error = xdc.useModule('xdc.runtime.Error');\r
 \r
+//BIOS.libType = BIOS.LibType_Custom;\r
 /* Heap used when creating semaphore's, TSK's or malloc() ... */\r
 Program.heap            = 0x1000;\r
 \r
@@ -24,13 +25,13 @@ Program.sectMap[".cio"].loadSegment = "EXT_RAM";
 \r
 /* MMU/Cache related configurations                                           */\r
 \r
-var Cache  = xdc.useModule('ti.sysbios.family.arm.a15.Cache');\r
+var Cache1  = xdc.useModule('ti.sysbios.family.arm.a15.Cache');\r
 var Mmu    = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');\r
 var InitXbar = xdc.useModule('ti.sysbios.hal.vayu.IntXbar');\r
 \r
 \r
 /* Enable the cache                                                           */\r
-Cache.enableCache = false;\r
+Cache1.enableCache = false;\r
 \r
 /* Enable the MMU (Required for L1 data caching)                              */\r
 Mmu.enableMMU = true;\r
index 9fda959d058f917f3f2d60a383095a36cccf8935..b0fa6dc92ec696c7a4e89e95985d0be8585e4996 100644 (file)
@@ -19,7 +19,7 @@ XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_st_sample.cfg
 SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \\r
               dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \\r
               qdma_link_test.c\r
-CFLAGS_LOCAL_COMMON = \r
+CFLAGS_LOCAL_COMMON = -DBUILD_TDA2XX_IPU\r
 \r
 # Core/SoC/platform specific source files and CFLAGS\r
 # Example: \r
index 3a7679e568901a458c71ed171e59d39f75f1f7ef..e2229eadabc33b0e22767a46af8928e1066ce4e2 100644 (file)
@@ -12,13 +12,17 @@ var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
 var Program     = xdc.useModule("xdc.cfg.Program");\r
 var InitXbar    = xdc.useModule("ti.sysbios.hal.vayu.IntXbar");\r
 \r
-\r
 /* ISR/SWI stack        */\r
 Program.stack           = 0x4000;\r
 \r
 /* Heap used when creating semaphore's, TSK's or malloc() ... */\r
 Program.heap            = 0x15000;\r
 \r
+Program.sectMap[".ducatiBoot"]          = "L2_RAM";\r
+Program.sectMap[".bootVecs"]            = "L2_RAM";\r
+Program.sectMap[".ducatiGates"]         = "L2_RAM"; \r
+\r
+\r
 /* enable print of exception handing info */\r
 HwiM3.enableException = true;\r
 \r
@@ -26,6 +30,10 @@ HwiM3.enableException = true;
 var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');\r
 Core.id = 0;\r
 \r
+var M3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');\r
+M3Hwi.resetVectorAddress = (Core.id + 1) * 0 + 0x20000400;\r
+M3Hwi.vectorTableAddress = M3Hwi.resetVectorAddress; \r
+\r
 /* USE EDMA3 Sample App */\r
 //xdc.loadPackage('ti.sdo.edma3.drv.sample');\r
 \r
@@ -35,17 +43,10 @@ var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
 \r
 /* Enable the cache                                                           */\r
 Cache1.enableCache = true;\r
-/*\r
-AMMU.smallPages[2].pageEnabled = AMMU.Enable_YES;\r
-AMMU.smallPages[2].logicalAddress = 0x43300000;\r
-AMMU.smallPages[2].translatedAddress = 0xA0000000;\r
-AMMU.smallPages[2].translationEnabled = AMMU.Enable_YES;\r
-AMMU.smallPages[2].size = AMMU.Small_16K;\r
-AMMU.smallPages[2].volatileQualifier = AMMU.Volatile_FOLLOW; \r
-*/\r
+\r
 AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;\r
-AMMU.mediumPages[1].logicalAddress = 0x43300000;\r
-AMMU.mediumPages[1].translatedAddress = 0xA0000000;\r
+AMMU.mediumPages[1].logicalAddress = 0x60000000;\r
+AMMU.mediumPages[1].translatedAddress = 0x43300000;\r
 AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;\r
 AMMU.mediumPages[1].size = AMMU.Medium_256K;\r
 AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;\r
index 20e29835080cbe061d938821063c777025be44b8..f93cddfad89d2e318734e429c8844adf9b744d6b 100644 (file)
@@ -1,5 +1,11 @@
+MEMORY\r
+{\r
+    OCMC_RAM : org = 0x40300000, len = 0x10000\r
+}\r
+\r
 SECTIONS\r
 {\r
     .my_sect_iram > EXT_RAM\r
     .my_sect_ddr  > EXT_RAM\r
+    .resetVecs  > L2_RAM       \r
 }\r
index 680ab560e53e141ffac13ebedb29209138398860..370c409a17929702d63c8bfe01b518b811f67eb0 100644 (file)
@@ -46,6 +46,7 @@ volatile short irqRaised2 = 0;
 
 
 /* Cache line aligned source buffer 1. */
+#ifndef BUILD_TDA2XX_MPU
 #ifdef EDMA3_ENABLE_DCACHE
 /**
  * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
@@ -58,9 +59,16 @@ volatile short irqRaised2 = 0;
 #endif  /* #ifdef EDMA3_ENABLE_DCACHE */
 #pragma DATA_SECTION(_srcBuff1, ".my_sect_ddr");
 signed char   _srcBuff1[MAX_BUFFER_SIZE];
-
+#else
+#ifdef EDMA3_ENABLE_DCACHE
+signed char   _srcBuff1[MAX_BUFFER_SIZE] __attribute__ ((aligned (EDMA3_CACHE_LINE_SIZE_IN_BYTES)));
+#else
+signed char   _srcBuff1[MAX_BUFFER_SIZE];
+#endif
+#endif
 
 /* Cache line aligned destination buffer 1. */
+#ifndef BUILD_TDA2XX_MPU
 #ifdef EDMA3_ENABLE_DCACHE
 /**
  * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
@@ -73,6 +81,13 @@ signed char   _srcBuff1[MAX_BUFFER_SIZE];
 #endif  /* #ifdef EDMA3_ENABLE_DCACHE */
 #pragma DATA_SECTION(_dstBuff1, ".my_sect_ddr");
 signed char   _dstBuff1[MAX_BUFFER_SIZE];
+#else
+#ifdef EDMA3_ENABLE_DCACHE
+signed char   _dstBuff1[MAX_BUFFER_SIZE] __attribute__ ((aligned (EDMA3_CACHE_LINE_SIZE_IN_BYTES)));
+#else
+signed char   _dstBuff1[MAX_BUFFER_SIZE];
+#endif
+#endif
 
 signed char *srcBuff1;
 signed char *dstBuff1;
@@ -80,6 +95,7 @@ signed char *dstBuff1;
 
 
 /* Cache line aligned source buffer 2. */
+#ifndef BUILD_TDA2XX_MPU
 #ifdef EDMA3_ENABLE_DCACHE
 /**
  * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
@@ -92,8 +108,15 @@ signed char *dstBuff1;
 #endif  /* #ifdef EDMA3_ENABLE_DCACHE */
 #pragma DATA_SECTION(_srcBuff2, ".my_sect_ddr");
 signed char   _srcBuff2[MAX_BUFFER_SIZE];
+#else
+#ifdef EDMA3_ENABLE_DCACHE
+signed char   _srcBuff2[MAX_BUFFER_SIZE] __attribute__ ((aligned (EDMA3_CACHE_LINE_SIZE_IN_BYTES)));
+#else
+signed char   _srcBuff2[MAX_BUFFER_SIZE];
+#endif
+#endif
 
-
+#ifndef BUILD_TDA2XX_MPU
 #ifdef EDMA3_ENABLE_DCACHE
 /* Cache line aligned destination buffer 2. */
 /**
@@ -107,6 +130,13 @@ signed char   _srcBuff2[MAX_BUFFER_SIZE];
 #endif  /* #ifdef EDMA3_ENABLE_DCACHE */
 #pragma DATA_SECTION(_dstBuff2, ".my_sect_ddr");
 signed char   _dstBuff2[MAX_BUFFER_SIZE];
+#else
+#ifdef EDMA3_ENABLE_DCACHE
+signed char   _dstBuff2[MAX_BUFFER_SIZE] __attribute__ ((aligned (EDMA3_CACHE_LINE_SIZE_IN_BYTES)));
+#else
+signed char   _dstBuff2[MAX_BUFFER_SIZE];
+#endif
+#endif
 
 signed char *srcBuff2;
 signed char *dstBuff2;
index e3db65674305919a5a9c901f3a8177d8004d4543..1be466a6b4316c6cda44aceabbc998e53a495c5e 100644 (file)
@@ -307,7 +307,8 @@ EDMA3_DRV_Result edma3MemToMemCpytest (EDMA3_DRV_Handle hEdma)
 
     if (hEdma == NULL)
         {
-        result = EDMA3_DRV_E_INVALID_PARAM;
+        //result = EDMA3_DRV_E_INVALID_PARAM;
+               return result;
         }
 
     /* Edma test without linking, async, incr mode */
index 73fdaaa7443c141a6663bd1943654877b90365f6..c6a7cd5f8ad18f42ab97f869df5cebcc62f24717 100755 (executable)
@@ -172,6 +172,9 @@ ifneq ($(XDC_CFG_FILE_$(CORE)),)
   XDC_CFG_BASE_FILE_NAME = $(basename $(notdir $(XDC_CFG_FILE_$(CORE))))
 #  OBJ_PATHS += $(CFG_COBJ_XDC)
   LNKCMD_FILE = $(CONFIGURO_DIR)/linker_mod.cmd
+ifeq ($(ISA),a15)
+  LNKCMD_FILE = $(CONFIGURO_DIR)/linker.cmd
+endif
   SPACE := 
   SPACE += 
   XDC_GREP_STRING = $(CONFIGURO_DIRNAME)
index 8b9363cad5564d9c153c35dc803cd18fa1f629cc..8a6c60dbe5adab341afb50be8a401f79283d21eb 100755 (executable)
@@ -181,6 +181,9 @@ ifeq ($(CORE),c6xdsp)
  ifeq ($(SOC),ti816x)
   ISA = 674
  endif
+ ifeq ($(SOC),tda2xx)
+  ISA = 66
+ endif
  ifeq ($(SOC),ti814x)
   ISA = 674
  endif
index 8c304a2107abd6762108766c8ca01fd9b66e991c..0fe2a9b69df4070bf5a3174af021492ab18842db 100755 (executable)
@@ -232,4 +232,7 @@ edma3_drv_tda2xx-evm_m4_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_td
 edma3_drv_tda2xx-evm_a15_example_EXAMPLES_RELPATH = examples/edma3_driver/evmtda2xx_A15
 edma3_drv_tda2xx-evm_a15_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda2xx-evm_a15_example_EXAMPLES_RELPATH)
 
+edma3_drv_tda2xx-evm_66_example_EXAMPLES_RELPATH = examples/edma3_driver/evmtda2xx
+edma3_drv_tda2xx-evm_66_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda2xx-evm_66_example_EXAMPLES_RELPATH)
+
 # Nothing beyond this point
index 3a753d6b5d5f4a09aee630bc65b703070e946925..447a7ec49b3a64b33fe7ffee3ad542cbc43a384b 100755 (executable)
@@ -57,6 +57,61 @@ cleanexamples: $(CLEANALL_EXAMPLES)
 #=======================================================================================================================================
 
 
+#=======================================================================================================================================
+#To Build libs For Platform tda2xx-evm Target 66
+edma3_lld_tda2xx-evm_66_libs: edma3_lld_tda2xx-evm_66_libs_drv edma3_lld_tda2xx-evm_66_libs_rm edma3_lld_tda2xx-evm_66_libs_drvsample edma3_lld_tda2xx-evm_66_libs_rmsample
+edma3_lld_tda2xx-evm_66_libs_drv:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making 66:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Making 66:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm PROFILE_c6xdsp=release
+endif
+edma3_lld_tda2xx-evm_66_libs_rm:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm PROFILE_c6xdsp=release
+endif
+edma3_lld_tda2xx-evm_66_libs_drvsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm PROFILE_c6xdsp=release
+endif
+edma3_lld_tda2xx-evm_66_libs_rmsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm PROFILE_c6xdsp=release
+endif
+
+#To Clean libs For Platform tda2xx-evm Target 66
+edma3_lld_tda2xx-evm_66_libs_clean: edma3_lld_tda2xx-evm_66_libs_drv_clean edma3_lld_tda2xx-evm_66_libs_rm_clean edma3_lld_tda2xx-evm_66_libs_drvsample_clean edma3_lld_tda2xx-evm_66_libs_rmsample_clean
+edma3_lld_tda2xx-evm_66_libs_drv_clean:
+       $(ECHO) \# Cleaning 66:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning 66:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm PROFILE_c6xdsp=release
+edma3_lld_tda2xx-evm_66_libs_rm_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm PROFILE_c6xdsp=release
+edma3_lld_tda2xx-evm_66_libs_drvsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm PROFILE_c6xdsp=release
+edma3_lld_tda2xx-evm_66_libs_rmsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm PROFILE_c6xdsp=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm PROFILE_c6xdsp=release
+
 #=======================================================================================================================================
 #To Build libs For Platform tda2xx-evm Target m4
 edma3_lld_tda2xx-evm_m4_libs: edma3_lld_tda2xx-evm_m4_libs_drv edma3_lld_tda2xx-evm_m4_libs_rm edma3_lld_tda2xx-evm_m4_libs_drvsample edma3_lld_tda2xx-evm_m4_libs_rmsample
@@ -2474,6 +2529,16 @@ ifeq ($(FORMAT),ELF)
        $(ECHO) \# Making example $@:release
        $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6a811x-evm CORE=m3vpss PROFILE_m3vpss=release
 endif
+edma3_drv_tda2xx-evm_66_example:
+       $(ECHO) \# Configuring XDC packages for $@:m4:debug 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=debug     
+
+       $(ECHO) \# Configuring XDC packages for $@:m4:release 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
+       $(ECHO) \# Making example $@:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=c6xdsp PROFILE_c6xdsp=release
 
 edma3_drv_tda2xx-evm_m4_example:
 ifeq ($(FORMAT),ELF)
index 895cc944769a91c8e5f167e742c533ffba8a4596..f82d397cb47e5998e05b9d902ac6f3ff1f9b8b63 100755 (executable)
@@ -77,6 +77,7 @@ function getLibs(prog)
                         'TMS320DM8148',
                         'TMS320TI814X',
                         'TMS320TI816X',
+                        'Vayu',
                     ];
 
     for (var i = 0; i < devices.length; i++)
@@ -95,6 +96,10 @@ function getLibs(prog)
                        target = "a8/";
                 if (java.lang.String(Program.build.target.suffix).contains('m3'))
                        target = "m3/";
+                if (java.lang.String(Program.build.target.suffix).contains('a15'))
+                       target = "a15/";
+                if (java.lang.String(Program.build.target.suffix).contains('a8'))
+                       target = "a8/";
                 if (java.lang.String(Program.build.target.suffix).contains('9'))
                        target = "arm9/";
                 lib = lib + target;
index cad6f5cf65b060b5069bd5ee3fb385b6424f8e84..d6322de0c71feba09fb9e50fb8099646359afbb5 100755 (executable)
@@ -44,6 +44,8 @@ CFLAGS_LOCAL_ti814x-evm = -DBUILD_CENTAURUS_DSP
 SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_int_reg.c
 CFLAGS_LOCAL_c6a811x-evm = -DBUILD_C6A811X_DSP
 SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_int_reg.c
+SRCS_tda2xx-evm = sample_tda2xx_cfg.c sample_tda2xx_int_reg.c
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_DSP
 else
 SRCS_omapl138-evm = sample_omapl138_arm_cfg.c sample_omapl138_arm_int_reg.c
 SRCS_tda2xx-evm = sample_tda2xx_cfg.c sample_tda2xx_arm_int_reg.c
index 46fcebaabe5aa9a39a9bb16b114016d816ccc6ae..481754b6e4f20cf4bb9ef6710f68ae4480c693bb 100755 (executable)
@@ -77,6 +77,7 @@ function getLibs(prog)
                         'TMS320DM8148',
                         'TMS320TI814X',
                         'TMS320TI816X',
+                        'Vayu',
                     ];
 
     /* Directories for each platform */
@@ -100,6 +101,7 @@ function getLibs(prog)
                 'ti814x-evm/',
                 'ti814x-evm/',
                 'ti816x-evm/',
+                'tda2xx-evm/',
               ];
 
     for (var i = 0; i < devices.length; i++)
@@ -121,6 +123,10 @@ function getLibs(prog)
                        target = "m3/";
                 if (java.lang.String(Program.build.target.suffix).contains('9'))
                        target = "arm9/";
+                if (java.lang.String(Program.build.target.suffix).contains('m4'))
+                       target = "m4/";
+                if (java.lang.String(Program.build.target.suffix).contains('a15'))
+                       target = "a15/";
                 lib = lib + target;
                 bool = 1;
                 break;
index 84dd33f6e2c1646125fcc8f1ec9d90ee908ab760..cae613892d2f7e9e8f2cbbec36af92d6d1c65f6e 100644 (file)
@@ -94,39 +94,22 @@ extern EDMA3_DRV_GblXbarToChanConfigParams
                                                                sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];\r
 \r
 typedef struct  {\r
-    volatile Uint32 DSP_INTMUX[21];\r
-    volatile Uint32 DUCATI_INTMUX[15];\r
-    volatile Uint32 TPCC_EVTMUX[16];\r
-    volatile Uint32 TIMER_EVTCAPT;\r
-    volatile Uint32 GPIO_MUX;\r
+    volatile Uint32 TPCC_EVTMUX[32];\r
 } CSL_IntmuxRegs;\r
 \r
 typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;\r
 \r
-\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)\r
-\r
-\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)\r
-\r
-\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)\r
 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
 \r
-\r
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)\r
 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
 #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
 \r
 \r
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)\r
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)\r
 #define EDMA3_NUM_TCC                     (64u)\r
-\r
 /*\r
  * Forward decleration\r
  */\r
@@ -149,8 +132,6 @@ void registerEdma3Interrupts (unsigned int edma3Id)
        IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);\r
        IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);\r
        \r
-//     *((volatile UInt32 *) 0x4A002544U) = (UInt32) 0xF757FDC0;\r
-\r
     Hwi_Params hwiParams; \r
     Error_Block      eb;\r
 \r
@@ -176,7 +157,7 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     {\r
         System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
     }\r
-#if 0\r
+\r
     /* Initialize the HWI parameters with user specified values */\r
     Hwi_Params_init(&hwiParams);\r
     /* argument for the ISR */\r
@@ -213,7 +194,7 @@ void registerEdma3Interrupts (unsigned int edma3Id)
         }\r
         numTc++;\r
        }\r
-#endif\r
+\r
    /**\r
     * Enabling the HWI_ID.\r
     * EDMA3 interrupts (transfer completion, CC error etc.)\r
@@ -226,7 +207,6 @@ void registerEdma3Interrupts (unsigned int edma3Id)
     * API C64_enableIER(), in which the YYY bit is SET.\r
     */\r
     Hwi_enableInterrupt(ccErrorInt[edma3Id]);\r
-#if 0\r
     Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);\r
     numTc = 0;\r
     while (numTc < numEdma3Tc[edma3Id])\r
@@ -234,7 +214,6 @@ void registerEdma3Interrupts (unsigned int edma3Id)
         Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);\r
         numTc++;\r
        }\r
-#endif\r
     /* Restore interrupts */\r
     Hwi_restore(cookie);\r
     }\r
@@ -306,14 +285,14 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
     unsigned int scrChanOffset = 0;\r
     unsigned int scrRegOffset  = 0;\r
     unsigned int xBarEvtNum    = 0;\r
-    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);\r
+    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x4a002c78);\r
 \r
 \r
        if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
                (chanNum < EDMA3_NUM_TCC))\r
                {\r
-               scrRegOffset = chanNum / 4;\r
-               scrChanOffset = chanNum - (scrRegOffset * 4);\r
+               scrRegOffset = chanNum / 2;\r
+               scrChanOffset = chanNum - (scrRegOffset * 2);\r
                xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;\r
                \r
                switch(scrChanOffset)\r
@@ -327,16 +306,6 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
                                        ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
                                        (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
                                break;\r
-                       case 2:\r
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & \r
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));\r
-                               break;\r
-                       case 3:\r
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & \r
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));\r
-                               break;\r
                        default:\r
                                edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
                                break;\r
index 54aba28192cde5bec6b2a0ff97e27564cb40ec74..0f3efdc49b0efb214f1d9d43a9ea94f17133466f 100644 (file)
@@ -41,7 +41,7 @@
 #include <ti/sdo/edma3/drv/edma3_drv.h>\r
 \r
 /* Number of EDMA3 controllers present in the system */\r
-#define NUM_EDMA3_INSTANCES         1u\r
+#define NUM_EDMA3_INSTANCES         2u\r
 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
 \r
 /* Number of DSPs present in the system */\r
@@ -100,46 +100,44 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_NUM_REGIONS                               (8u)\r
 \r
 /** Interrupt no. for Transfer Completion */\r
-//#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_A15                (34u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (34u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (38u)\r
 #define EDMA3_CC_XFER_COMPLETION_INT_IPU0               (34u)\r
 #define EDMA3_CC_XFER_COMPLETION_INT_IPU1               (34u)\r
 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
 #define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)\r
-#define COMPLETION_INT_DSP_XBAR_INST_NO                 (3u)\r
+#define COMPLETION_INT_DSP_XBAR_INST_NO                 (7u)\r
 #define COMPLETION_INT_IPU0_XBAR_INST_NO                (12u)\r
 #define COMPLETION_INT_IPU1_XBAR_INST_NO                (12u)\r
 \r
 /** Interrupt no. for CC Error */\r
-//#define EDMA3_CC_ERROR_INT_A15                          (67u)\r
-#define EDMA3_CC_ERROR_INT_A15                          (35u)\r
-#define EDMA3_CC_ERROR_INT_DSP                          (35u)\r
+#define EDMA3_CC_ERROR_INT_A15                          (67u)\r
+#define EDMA3_CC_ERROR_INT_DSP                          (39u)\r
 #define EDMA3_CC_ERROR_INT_IPU0                         (35u)\r
 #define EDMA3_CC_ERROR_INT_IPU1                         (35u)\r
 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
 #define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)\r
-#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (4u)\r
+#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (8u)\r
 #define CC_ERROR_INT_IPU0_XBAR_INST_NO                  (13u)\r
 #define CC_ERROR_INT_IPU1_XBAR_INST_NO                  (13u)\r
 \r
 \r
 /** Interrupt no. for TCs Error */\r
-#define EDMA3_TC0_ERROR_INT_A15                         (36u)\r
-#define EDMA3_TC0_ERROR_INT_DSP                         (36u)\r
+#define EDMA3_TC0_ERROR_INT_A15                         (68u)\r
+#define EDMA3_TC0_ERROR_INT_DSP                         (40u)\r
 #define EDMA3_TC0_ERROR_INT_IPU0                        (36u)\r
 #define EDMA3_TC0_ERROR_INT_IPU1                        (36u)\r
-#define EDMA3_TC1_ERROR_INT_A15                         (37u)\r
-#define EDMA3_TC1_ERROR_INT_DSP                         (37u)\r
+#define EDMA3_TC1_ERROR_INT_A15                         (69u)\r
+#define EDMA3_TC1_ERROR_INT_DSP                         (41u)\r
 #define EDMA3_TC1_ERROR_INT_IPU0                        (37u)\r
 #define EDMA3_TC1_ERROR_INT_IPU1                        (37u)\r
 /** Based on the interrupt number to be mapped define the XBAR instance number */\r
 #define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)\r
-#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (5u)\r
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (9u)\r
 #define TC0_ERROR_INT_IPU0_XBAR_INST_NO                 (14u)\r
 #define TC0_ERROR_INT_IPU1_XBAR_INST_NO                 (14u)\r
 #define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)\r
-#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (6u)\r
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (10u)\r
 #define TC1_ERROR_INT_IPU0_XBAR_INST_NO                 (15u)\r
 #define TC1_ERROR_INT_IPU1_XBAR_INST_NO                 (15u)\r
 \r
@@ -196,6 +194,11 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_TC6_ERROR_INT                             (0u)\r
 #define EDMA3_TC7_ERROR_INT                             (0u)\r
 \r
+#define DSP1_EDMA3_CC_XFER_COMPLETION_INT               (18u)\r
+#define DSP1_EDMA3_CC_ERROR_INT                         {27u}\r
+#define DSP1_EDMA3_TC0_ERROR_INT                        (28u)\r
+#define DSP1_EDMA3_TC1_ERROR_INT                        (29u)\r
+\r
 /** XBAR interrupt source index numbers for EDMA interrupts */\r
 #define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)\r
 #define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)\r
@@ -210,6 +213,29 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define XBAR_EDMA_TC0_IRQ_ERR                           (370u)\r
 #define XBAR_EDMA_TC1_IRQ_ERR                           (371u)\r
 \r
+/**\r
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
+ * ECM events (SoC specific). These ECM events come\r
+ * under ECM block XXX (handling those specific ECM events). Normally, block\r
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
+ * is mapped to a specific HWI_INT YYY in the tcf file.\r
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
+ * to transfer completion interrupt.\r
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
+ * to CC error interrupts.\r
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
+ * to TC error interrupts.\r
+ */\r
+/* EDMA 0 */\r
+\r
+#define EDMA3_HWI_INT_XFER_COMP                           (7u)\r
+#define EDMA3_HWI_INT_CC_ERR                              (7u)\r
+#define EDMA3_HWI_INT_TC0_ERR                             (10u)\r
+#define EDMA3_HWI_INT_TC1_ERR                             (10u)\r
+#define EDMA3_HWI_INT_TC2_ERR                             (10u)\r
+#define EDMA3_HWI_INT_TC3_ERR                             (10u)\r
+\r
 /**\r
  * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
  * various peripherals, which use EDMA for data transfer.\r
@@ -266,6 +292,10 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
                EDMA3_CC_XFER_COMPLETION_INT_IPU0, EDMA3_CC_XFER_COMPLETION_INT_IPU1,\r
         0u, 0u, 0u, 0u,\r
     },\r
+    {\r
+        0u, DSP1_EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u,\r
+        0u, 0u, 0u, 0u,\r
+    },\r
 };\r
 /** These are the Xbar instance numbers corresponding to interrupt numbers */\r
 unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
@@ -291,7 +321,7 @@ unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
  * error interrupt.\r
  */\r
 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
-                                                    EDMA3_CC_ERROR_INT,\r
+                                                    EDMA3_CC_ERROR_INT,DSP1_EDMA3_CC_ERROR_INT,\r
                                                };\r
 unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] = {\r
                                                     CC_ERROR_INT_XBAR_INST_NO,\r
@@ -312,6 +342,12 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
        EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
        EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
        EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
+   },\r
+   {\r
+       DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
+       EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+       EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+       EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
    }\r
 };\r
 unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][8] =\r
@@ -327,26 +363,32 @@ unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][8] =
 unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][8] =\r
 {\r
    {\r
-       XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC0_IRQ_ERR,\r
+       XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
           0u, 0u,\r
        0u, 0u, 0u, 0u,\r
    }\r
 };\r
 \r
-#if 0\r
+\r
 /**\r
  * Variables which will be used internally for referring the hardware interrupt\r
  * for various EDMA3 interrupts.\r
  */\r
 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
-                                                    EDMA3_HWI_INT_XFER_COMP\r
+                                                    EDMA3_HWI_INT_XFER_COMP, EDMA3_HWI_INT_XFER_COMP,\r
                                                   };\r
 \r
 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
-                                                   EDMA3_HWI_INT_CC_ERR\r
+                                                   EDMA3_HWI_INT_CC_ERR, EDMA3_HWI_INT_CC_ERR,\r
                                                };\r
 \r
 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
+                                                     {\r
+                                                        EDMA3_HWI_INT_TC0_ERR,\r
+                                                        EDMA3_HWI_INT_TC1_ERR,\r
+                                                        EDMA3_HWI_INT_TC2_ERR,\r
+                                                        EDMA3_HWI_INT_TC3_ERR\r
+                                                     },\r
                                                      {\r
                                                         EDMA3_HWI_INT_TC0_ERR,\r
                                                         EDMA3_HWI_INT_TC1_ERR,\r
@@ -354,24 +396,28 @@ unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
                                                         EDMA3_HWI_INT_TC3_ERR\r
                                                      }\r
                                                };\r
-#endif\r
+\r
 /**\r
  * \brief Base address as seen from the different cores may be different\r
  * And is defined based on the core\r
  */\r
-#ifdef BUILD_TDA2XX_MPU\r
+#if ((defined BUILD_TDA2XX_MPU) || (defined BUILD_TDA2XX_DSP))\r
 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
 #elif ((defined BUILD_TDA2XX_IPU0) || (defined BUILD_TDA2XX_IPU1))\r
-#define EDMA3_CC_BASE_ADDR                          ((void *)(0xA0000000))\r
-#define EDMA3_TC0_BASE_ADDR                         ((void *)(0xA0100000))\r
-#define EDMA3_TC1_BASE_ADDR                         ((void *)(0xA0200000))\r
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x60000000))\r
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x60100000))\r
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x60200000))\r
 #else\r
 #define EDMA3_CC_BASE_ADDR                          ((void *)(0x0))\r
 #define EDMA3_TC0_BASE_ADDR                         ((void *)(0x0))\r
 #define EDMA3_TC1_BASE_ADDR                         ((void *)(0x0))\r
 #endif\r
+\r
+#define DSP1_EDMA3_CC_BASE_ADDR                     ((void *)(0x01D10000))\r
+#define DSP1_EDMA3_TC0_BASE_ADDR                    ((void *)(0x01D05000))\r
+#define DSP1_EDMA3_TC1_BASE_ADDR                    ((void *)(0x01D06000))\r
 /* Driver Object Initialization Configuration */\r
 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
 {\r
@@ -536,6 +582,167 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
             EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1\r
             }\r
         },\r
+    {\r
+        /* EDMA3 INSTANCE# 1 */\r
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
+        EDMA3_NUM_DMA_CHANNELS,\r
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
+        EDMA3_NUM_QDMA_CHANNELS,\r
+        /** Total number of TCCs supported by the EDMA3 Controller            */\r
+        EDMA3_NUM_TCC,\r
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
+        EDMA3_NUM_PARAMSET,\r
+        /** Total number of Event Queues in the EDMA3 Controller              */\r
+        EDMA3_NUM_EVTQUE,\r
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
+        EDMA3_NUM_TC,\r
+        /** Number of Regions on this EDMA3 controller                        */\r
+        EDMA3_NUM_REGIONS,\r
+\r
+        /**\r
+         * \brief Channel mapping existence\r
+         * A value of 0 (No channel mapping) implies that there is fixed association\r
+         * for a channel number to a parameter entry number or, in other words,\r
+         * PaRAM entry n corresponds to channel n.\r
+         */\r
+        1u,\r
+\r
+        /** Existence of memory protection feature */\r
+        0u,\r
+\r
+        /** Global Register Region of CC Registers */\r
+        DSP1_EDMA3_CC_BASE_ADDR,\r
+        /** Transfer Controller (TC) Registers */\r
+        {\r
+               DSP1_EDMA3_TC0_BASE_ADDR,\r
+               DSP1_EDMA3_TC1_BASE_ADDR,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL\r
+        },\r
+        /** Interrupt no. for Transfer Completion */\r
+        DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
+        /** Interrupt no. for CC Error */\r
+        DSP1_EDMA3_CC_ERROR_INT,\r
+        /** Interrupt no. for TCs Error */\r
+        {\r
+            DSP1_EDMA3_TC0_ERROR_INT,\r
+            DSP1_EDMA3_TC1_ERROR_INT,\r
+            EDMA3_TC2_ERROR_INT,\r
+            EDMA3_TC3_ERROR_INT,\r
+            EDMA3_TC4_ERROR_INT,\r
+            EDMA3_TC5_ERROR_INT,\r
+            EDMA3_TC6_ERROR_INT,\r
+            EDMA3_TC7_ERROR_INT\r
+        },\r
+\r
+        /**\r
+         * \brief EDMA3 TC priority setting\r
+         *\r
+         * User can program the priority of the Event Queues\r
+         * at a system-wide level.  This means that the user can set the\r
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+         * relative to IO initiated by the other bus masters on the\r
+         * device (ARM, DSP, USB, etc)\r
+         */\r
+        {\r
+            0u,\r
+            1u,\r
+            2u,\r
+            3u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u\r
+        },\r
+        /**\r
+         * \brief To Configure the Threshold level of number of events\r
+         * that can be queued up in the Event queues. EDMA3CC error register\r
+         * (CCERR) will indicate whether or not at any instant of time the\r
+         * number of events queued up in any of the event queues exceeds\r
+         * or equals the threshold/watermark value that is set\r
+         * in the queue watermark threshold register (QWMTHRA).\r
+         */\r
+        {\r
+            16u,\r
+            16u,\r
+            16u,\r
+            16u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u\r
+        },\r
+\r
+        /**\r
+         * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+         * An optimally-sized command is defined by the transfer controller\r
+         * default burst size (DBS). Different TCs can have different\r
+         * DBS values. It is defined in Bytes.\r
+         */\r
+            {\r
+            16u,\r
+            16u,\r
+            16u,\r
+            16u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u\r
+            },\r
+\r
+        /**\r
+         * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+         * if it exists, otherwise of no use.\r
+         */\r
+            {\r
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, \r
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
+            },\r
+\r
+         /**\r
+          * \brief Mapping from each DMA channel to a TCC. This specific\r
+          * TCC code will be returned when the transfer is completed\r
+          * on the mapped channel.\r
+          */\r
+            {\r
+            0u, 1u, 2u, 3u,\r
+            4u, 5u, 6u, 7u,\r
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+            12u, 13u, 14u, 15u,\r
+            16u, 17u, 18u, 19u,\r
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+            24u, 25u, 26u, 27u,\r
+            28u, 29u, 30u, 31u,\r
+            32u, 33u, 34u, 35u,\r
+            36u, 37u, 38u, 39u,\r
+            40u, 41u, 42u, 43u,\r
+            44u, 45u, 46u, 47u,\r
+            48u, 49u, 50u, 51u,\r
+            52u, 53u, 54u, 55u,\r
+            56u, 57u, 58u, 59u,\r
+            60u, 61u, 62u, 63u\r
+            },\r
+\r
+        /**\r
+         * \brief Mapping of DMA channels to Hardware Events from\r
+         * various peripherals, which use EDMA for data transfer.\r
+         * All channels need not be mapped, some can be free also.\r
+         */\r
+            {\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1\r
+            }\r
+    },\r
 };\r
 \r
 /**\r
@@ -929,7 +1136,385 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                                {0x00000000u, 0x00000000u},\r
                        },\r
            },\r
-    };\r
+               /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
+               {\r
+               /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+                       /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+           },\r
+       };\r
 \r
 /* Driver Instance Cross bar event to channel map Initialization Configuration */\r
 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_int_reg.c
new file mode 100644 (file)
index 0000000..68b3723
--- /dev/null
@@ -0,0 +1,299 @@
+/*
+ * sample_tda2xx_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+#include <ti/sysbios/hal/vayu/IntXbar.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];
+extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorIntXbarInstNo[];
+extern unsigned int ccErrEdmaXbarIndex[];
+extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];
+extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+extern unsigned int dsp_num;
+
+/* External Instance Specific Configuration Structure */
+extern EDMA3_DRV_GblXbarToChanConfigParams 
+                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+
+typedef struct  {
+    volatile Uint32 TPCC_EVTMUX[32];
+} CSL_IntmuxRegs;
+
+typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFu)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+
+
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (127u)
+#define EDMA3_NUM_TCC                     (64u)
+
+/*
+ * Forward decleration
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum);
+
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+    /* Do the xbar configuration only for edma inst 0 */
+       /* EDMA inst 1 is for DSP1 EDMA which has direct interrupt mapping */
+       if(edma3Id == 0)
+       {
+           IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);
+           IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);
+           IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);
+           IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);
+       }
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Enable the Xfer Completion Event Interrupt */
+    EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
+                               edma3Id, 1);
+    EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Enable the CC Error Event Interrupt */
+    EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
+                                               edma3Id, 1);
+    EventCombiner_enableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
+                            (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
+                            edma3Id, 1);
+        EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+       if(edma3Id == 0)
+       {
+    Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
+    Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
+    Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Disable the Xfer Completion Event Interrupt */
+       EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Disable the CC Error Event Interrupt */
+       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+       {
+        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**
+ * \brief   sampleMapXbarEvtToChan
+ *
+ * This function reads from the sample configuration structure which specifies 
+ * cross bar events mapped to DMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+    unsigned int xbarEvtNum = 0;
+    int          edmaChanNum = 0;
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum != NULL) &&
+               (edmaGblXbarConfig != NULL))
+               {
+               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
+               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
+               if (edmaChanNum != -1)
+                       {
+                       *chanNum = edmaChanNum;
+                       edma3Result = EDMA3_DRV_SOK;
+                       }
+               }
+       return (edma3Result);
+       }
+
+
+/**
+ * \brief   sampleConfigScr
+ *
+ * This function configures control config registers for the cross bar events 
+ * mapped to the EDMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
+    unsigned int scrChanOffset = 0;
+    unsigned int scrRegOffset  = 0;
+    unsigned int xBarEvtNum    = 0;
+    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x4a002c78);
+
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum < EDMA3_NUM_TCC))
+               {
+               scrRegOffset = chanNum / 2;
+               scrChanOffset = chanNum - (scrRegOffset * 2);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+               
+               switch(scrChanOffset)
+                       {
+                       case 0:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
+                               break;
+                       case 1:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
+                               break;
+                       default:
+                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+                               break;
+                       }
+               }
+       else
+               {
+               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+               }
+       return edma3Result;
+       }
+
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
+                                   unsigned int edma3Id)
+    {
+    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
+    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
+                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
+    if (hEdma != NULL)
+        {
+        retVal = EDMA3_DRV_initXbarEventMap(hEdma, 
+                                                                       sampleXbarToChanConfig, 
+                                                                       &sampleMapXbarEvtToChan, 
+                                                                       &sampleConfigScr);
+        }
+    
+    return retVal;
+    }
index 73ddd4f0227a1dbea26bd8746da40432d7b1c07d..1e0e97b94632c72032cc8b453977299eb5cca150 100644 (file)
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
 */
-
+#ifdef BUILD_TDA2XX_MPU
+#include <ti/sysbios/family/arm/a15/Cache.h>
+#else
 #include <ti/sysbios/hal/Cache.h>
+#endif
 #include <ti/sysbios/hal/Hwi.h>
 #include <ti/sysbios/knl/Task.h>
 #include <ti/sysbios/knl/Semaphore.h>
index b0b0462bc1dc47424ad6aabec30eece13453dd9a..db0e47b6d73e98e7e7404efea5e558ca9f510cf1 100755 (executable)
@@ -77,6 +77,7 @@ function getLibs(prog)
                         'TMS320DM8148',
                         'TMS320TI814X',
                         'TMS320TI816X',
+                        'Vayu',
                     ];
 
     /* Directories for each platform */
@@ -100,6 +101,7 @@ function getLibs(prog)
                 'ti814x-evm/',
                 'ti814x-evm/',
                 'ti816x-evm/',
+                'tda2xx-evm/',
               ];
 
     for (var i = 0; i < devices.length; i++)
@@ -121,6 +123,10 @@ function getLibs(prog)
                        target = "m3/";
                 if (java.lang.String(Program.build.target.suffix).contains('9'))
                        target = "arm9/";
+                if (java.lang.String(Program.build.target.suffix).contains('m4'))
+                       target = "m4/";
+                if (java.lang.String(Program.build.target.suffix).contains('a15'))
+                       target = "a15/";
                 lib = lib + target;
                 bool = 1;
                 break;
index 9542f9df4e58c2c4ac09c26bcd3117d66d17d715..b894e53509a787319361b03a275f8c7f90ce8e13 100755 (executable)
@@ -77,6 +77,7 @@ function getLibs(prog)
                         'TMS320DM8148',
                         'TMS320TI814X',
                         'TMS320TI816X',
+                        'Vayu',
                     ];
 
     /* Directories for each platform */
@@ -100,6 +101,7 @@ function getLibs(prog)
                 'ti814x-evm/',
                 'ti814x-evm/',
                 'ti816x-evm/',
+                'tda2xx-evm/',
               ];
 
 
@@ -122,6 +124,10 @@ function getLibs(prog)
                        target = "m3/";
                 if (java.lang.String(Program.build.target.suffix).contains('9'))
                        target = "arm9/";
+                if (java.lang.String(Program.build.target.suffix).contains('m4'))
+                       target = "m4/";
+                if (java.lang.String(Program.build.target.suffix).contains('a15'))
+                       target = "a15/";
                 lib = lib + target;
                 bool = 1;
                 break;