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raw | patch | inline | side by side (parent: 5eb2e0a)
raw | patch | inline | side by side (parent: 5eb2e0a)
| author | Arvind <x0193495@ti.com> | |
| Tue, 7 Jan 2014 09:39:02 +0000 (15:09 +0530) | ||
| committer | Arvind <x0193495@ti.com> | |
| Tue, 7 Jan 2014 09:39:02 +0000 (15:09 +0530) |
1. Teardown sequence in standalone example was not proper ie edma3deinit()
was called after heartbeats (huge delay) so de-initialization was
not happening.
2. Code clean up - Indentation and tab removal changes for only standalone
example files.
was called after heartbeats (huge delay) so de-initialization was
not happening.
2. Code clean up - Indentation and tab removal changes for only standalone
example files.
index fd0f941ff4afcba5e8238e3b3c74369f5ea4167f..31c67a9695a19eeebfa4fd7f2c223980a8a43535 100644 (file)
/*
- * common.c
- *
- * Demo sample application for the EDMA3 Driver for BIOS 6.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* common.c
+*
+* Demo sample application for the EDMA3 Driver for BIOS 6.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#include "sample.h"
#ifndef GCC_BUILD
#ifdef EDMA3_ENABLE_DCACHE
/**
- * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
- * alignment boundary is the maximum of the symbol\92s default alignment value
- * or the value of the constant in bytes. The constant must be a power of 2.
- * The syntax of the pragma in C is:
- * #pragma DATA_ALIGN (symbol, constant);
- */
+* The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
+* alignment boundary is the maximum of the symbol\92s default alignment value
+* or the value of the constant in bytes. The constant must be a power of 2.
+* The syntax of the pragma in C is:
+* #pragma DATA_ALIGN (symbol, constant);
+*/
#pragma DATA_ALIGN(_srcBuff1, EDMA3_CACHE_LINE_SIZE_IN_BYTES);
#endif /* #ifdef EDMA3_ENABLE_DCACHE */
#pragma DATA_SECTION(_srcBuff1, ".my_sect_ddr");
#ifndef GCC_BUILD
#ifdef EDMA3_ENABLE_DCACHE
/**
- * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
- * alignment boundary is the maximum of the symbol\92s default alignment value
- * or the value of the constant in bytes. The constant must be a power of 2.
- * The syntax of the pragma in C is:
- * #pragma DATA_ALIGN (symbol, constant);
- */
+* The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
+* alignment boundary is the maximum of the symbol\92s default alignment value
+* or the value of the constant in bytes. The constant must be a power of 2.
+* The syntax of the pragma in C is:
+* #pragma DATA_ALIGN (symbol, constant);
+*/
#pragma DATA_ALIGN(_dstBuff1, EDMA3_CACHE_LINE_SIZE_IN_BYTES);
#endif /* #ifdef EDMA3_ENABLE_DCACHE */
#pragma DATA_SECTION(_dstBuff1, ".my_sect_ddr");
#ifndef GCC_BUILD
#ifdef EDMA3_ENABLE_DCACHE
/**
- * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
- * alignment boundary is the maximum of the symbol\92s default alignment value
- * or the value of the constant in bytes. The constant must be a power of 2.
- * The syntax of the pragma in C is:
- * #pragma DATA_ALIGN (symbol, constant);
- */
+* The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
+* alignment boundary is the maximum of the symbol\92s default alignment value
+* or the value of the constant in bytes. The constant must be a power of 2.
+* The syntax of the pragma in C is:
+* #pragma DATA_ALIGN (symbol, constant);
+*/
#pragma DATA_ALIGN(_srcBuff2, EDMA3_CACHE_LINE_SIZE_IN_BYTES);
#endif /* #ifdef EDMA3_ENABLE_DCACHE */
#pragma DATA_SECTION(_srcBuff2, ".my_sect_ddr");
@@ -125,12 +125,12 @@ signed char __attribute__((section(".my_sect_ddr"))) _srcBuff2[MAX_BUFFER_SIZE
#ifdef EDMA3_ENABLE_DCACHE
/* Cache line aligned destination buffer 2. */
/**
- * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
- * alignment boundary is the maximum of the symbol\92s default alignment value
- * or the value of the constant in bytes. The constant must be a power of 2.
- * The syntax of the pragma in C is:
- * #pragma DATA_ALIGN (symbol, constant);
- */
+* The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
+* alignment boundary is the maximum of the symbol\92s default alignment value
+* or the value of the constant in bytes. The constant must be a power of 2.
+* The syntax of the pragma in C is:
+* #pragma DATA_ALIGN (symbol, constant);
+*/
#pragma DATA_ALIGN(_dstBuff2, EDMA3_CACHE_LINE_SIZE_IN_BYTES);
#endif /* #ifdef EDMA3_ENABLE_DCACHE */
#pragma DATA_SECTION(_dstBuff2, ".my_sect_ddr");
/* Callback function 1 */
void callback1 (uint32_t tcc, EDMA3_RM_TccStatus status,
- void *appData)
- {
+ void *appData)
+{
(void)tcc;
(void)appData;
switch (status)
- {
- case EDMA3_RM_XFER_COMPLETE:
- /* Transfer completed successfully */
- irqRaised1 = 1;
- break;
- case EDMA3_RM_E_CC_DMA_EVT_MISS:
- /* Transfer resulted in DMA event miss error. */
- irqRaised1 = -1;
- break;
- case EDMA3_RM_E_CC_QDMA_EVT_MISS:
- /* Transfer resulted in QDMA event miss error. */
- irqRaised1 = -2;
- break;
- default:
- break;
- }
- edma3OsSemGive(AppSemHandle1);
+ {
+ case EDMA3_RM_XFER_COMPLETE:
+ /* Transfer completed successfully */
+ irqRaised1 = 1;
+ break;
+ case EDMA3_RM_E_CC_DMA_EVT_MISS:
+ /* Transfer resulted in DMA event miss error. */
+ irqRaised1 = -1;
+ break;
+ case EDMA3_RM_E_CC_QDMA_EVT_MISS:
+ /* Transfer resulted in QDMA event miss error. */
+ irqRaised1 = -2;
+ break;
+ default:
+ break;
}
+ edma3OsSemGive(AppSemHandle1);
+}
/* Callback function 2 */
void callback2 (uint32_t tcc, EDMA3_RM_TccStatus status,
- void *appData)
- {
+ void *appData)
+{
(void)tcc;
(void)appData;
switch (status)
- {
- case EDMA3_RM_XFER_COMPLETE:
- /* Transfer completed successfully */
- irqRaised2 = 1;
- break;
- case EDMA3_RM_E_CC_DMA_EVT_MISS:
- /* Transfer resulted in DMA event miss error. */
- irqRaised2 = -1;
- break;
- case EDMA3_RM_E_CC_QDMA_EVT_MISS:
- /* Transfer resulted in QDMA event miss error. */
- irqRaised2 = -2;
- break;
- default:
- break;
- }
- edma3OsSemGive(AppSemHandle2);
+ {
+ case EDMA3_RM_XFER_COMPLETE:
+ /* Transfer completed successfully */
+ irqRaised2 = 1;
+ break;
+ case EDMA3_RM_E_CC_DMA_EVT_MISS:
+ /* Transfer resulted in DMA event miss error. */
+ irqRaised2 = -1;
+ break;
+ case EDMA3_RM_E_CC_QDMA_EVT_MISS:
+ /* Transfer resulted in QDMA event miss error. */
+ irqRaised2 = -2;
+ break;
+ default:
+ break;
}
-
-
+ edma3OsSemGive(AppSemHandle2);
+}
diff --git a/examples/edma3_driver/src/dma_chain_test.c b/examples/edma3_driver/src/dma_chain_test.c
index f8e53a65a140262f2e7f738139d3ba1f894aa949..8227148ceba39fb66dc99aa3dc7714d662ee0af0 100755 (executable)
/*
- * dma_chain_test.c
- *
- * Test case demonstrating the usgae of DMA channels for transferring data
- * between two memory locations. The two DMA channels are chained to each other.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* dma_chain_test.c
+*
+* Test case demonstrating the usgae of DMA channels for transferring data
+* between two memory locations. The two DMA channels are chained to each other.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#include "sample.h"
extern void *AppSemHandle2;
/**
- * \brief EDMA3 mem-to-mem data copy test case, using two DMA channels,
- * chained to each other.
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
+* \brief EDMA3 mem-to-mem data copy test case, using two DMA channels,
+* chained to each other.
+*
+* \param acnt [IN] Number of bytes in an array
+* \param bcnt [IN] Number of arrays in a frame
+* \param ccnt [IN] Number of frames in a block
+* \param syncType [IN] Synchronization type (A/AB Sync)
+*
+* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
EDMA3_DRV_Result edma3_test_with_chaining(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType)
- {
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType)
+{
EDMA3_DRV_ChainOptions chain = {EDMA3_DRV_TCCHEN_DIS,
- EDMA3_DRV_ITCCHEN_DIS,
- EDMA3_DRV_TCINTEN_DIS,
- EDMA3_DRV_ITCINTEN_DIS};
+ EDMA3_DRV_ITCCHEN_DIS,
+ EDMA3_DRV_TCINTEN_DIS,
+ EDMA3_DRV_ITCINTEN_DIS};
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
uint32_t BRCnt = 0;
int srcbidx = 0, desbidx = 0;
/* Initalize source and destination buffers */
for (count = 0u; count < (acnt*bcnt*ccnt); count++)
- {
+ {
srcBuff1[count] = (int)count+4;
srcBuff2[count] = (int)count+4;
/**
- * No need to initialize the destination buffer as it is being invalidated.
+ * No need to initialize the destination buffer as it is being invalidated.
dstBuff1[count] = initval;
dstBuff2[count] = initval;
*/
- }
+ }
#ifdef EDMA3_ENABLE_DCACHE
*/
/* Flush the Source Buffers */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheFlush((uint32_t)srcBuff2, (acnt*bcnt*ccnt));
- }
+ }
/* Invalidate the Destination Buffers */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstBuff2, (acnt*bcnt*ccnt));
- }
+ }
#endif /* EDMA3_ENABLE_DCACHE */
desbidx = (int)acnt;
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
/* A Sync Transfer Mode */
srccidx = (int)acnt;
descidx = (int)acnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
srccidx = ((int)acnt * (int)bcnt);
descidx = ((int)acnt * (int)bcnt);
- }
+ }
/* Transfer complete chaining enable. */
ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1,
- (EDMA3_RM_EventQueue)0,
- &callback1, NULL);
- }
+ (EDMA3_RM_EventQueue)0,
+ &callback1, NULL);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setSrcParams (hEdma, ch1Id,
- (uint32_t)(srcBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ (uint32_t)(srcBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setDestParams (hEdma, ch1Id,
- (uint32_t)(dstBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ (uint32_t)(dstBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
- ccnt,BRCnt,
- EDMA3_DRV_SYNC_A);
- }
+ ccnt,BRCnt,
+ EDMA3_DRV_SYNC_A);
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
- ccnt, BRCnt,
- EDMA3_DRV_SYNC_AB);
- }
+ ccnt, BRCnt,
+ EDMA3_DRV_SYNC_AB);
}
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Setup for Channel 2 */
tcc2 = EDMA3_DRV_TCC_ANY;
ch2Id = EDMA3_DRV_DMA_CHANNEL_ANY;
result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2,
- (EDMA3_RM_EventQueue)0,
- &callback2, NULL);
- }
+ (EDMA3_RM_EventQueue)0,
+ &callback2, NULL);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (uint32_t)(srcBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setDestParams (hEdma, ch2Id,
- (uint32_t)(dstBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ (uint32_t)(dstBuff2),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
- ccnt, BRCnt,
- EDMA3_DRV_SYNC_A);
- }
+ ccnt, BRCnt,
+ EDMA3_DRV_SYNC_A);
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
- ccnt, BRCnt,
- EDMA3_DRV_SYNC_AB);
- }
+ ccnt, BRCnt,
+ EDMA3_DRV_SYNC_AB);
}
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/**
- * Enable the Transfer Completion Interrupt on the Chained Channel
- * (Ch 2).
- */
+ * Enable the Transfer Completion Interrupt on the Chained Channel
+ * (Ch 2).
+ */
result = EDMA3_DRV_setOptField (hEdma, ch2Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/**
- * Enable the Intermediate Transfer Completion Interrupt on the
- * Chained Channel (Ch 2).
- */
+ * Enable the Intermediate Transfer Completion Interrupt on the
+ * Chained Channel (Ch 2).
+ */
result = EDMA3_DRV_setOptField (hEdma, ch2Id,
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Now chain the two channels together. */
result = EDMA3_DRV_chainChannel(hEdma, ch1Id, ch2Id,
- (EDMA3_DRV_ChainOptions *)&chain);
- }
+ (EDMA3_DRV_ChainOptions *)&chain);
+ }
/*Need to activate next param*/
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
numenabled = bcnt * ccnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
numenabled = ccnt;
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
for (i = 0; i < numenabled; i++)
- {
+ {
irqRaised2 = 0;
/*
- * Now enable the transfer for Master channel as many times
- * as calculated above.
- */
+ * Now enable the transfer for Master channel as many times
+ * as calculated above.
+ */
result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
- EDMA3_DRV_TRIG_MODE_MANUAL);
+ EDMA3_DRV_TRIG_MODE_MANUAL);
if (result != EDMA3_DRV_SOK)
- {
- #ifdef EDMA3_DRV_DEBUG
+ {
+#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("error from edma3_test_with_chaining\n\r\n");
- #endif /* EDMA3_DRV_DEBUG */
+#endif /* EDMA3_DRV_DEBUG */
break;
- }
+ }
/**
- * Transfer on the master channel (ch1Id) will finish after some
- * time.
- * Now, because of the enabling of intermediate chaining on channel
- * 1, after the transfer gets over, a sync event will be sent
- * to channel 2, which will trigger the transfer on it.
- * Also, Final and Intermediate Transfer Complete
- * Interrupts are enabled on channel 2, so we should wait for the
- * completion ISR on channel 2 first, before proceeding
- * ahead.
- */
- edma3OsSemTake(AppSemHandle2, EDMA3_OSSEM_NO_TIMEOUT);
+ * Transfer on the master channel (ch1Id) will finish after some
+ * time.
+ * Now, because of the enabling of intermediate chaining on channel
+ * 1, after the transfer gets over, a sync event will be sent
+ * to channel 2, which will trigger the transfer on it.
+ * Also, Final and Intermediate Transfer Complete
+ * Interrupts are enabled on channel 2, so we should wait for the
+ * completion ISR on channel 2 first, before proceeding
+ * ahead.
+ */
+ edma3OsSemTake(AppSemHandle2, EDMA3_OSSEM_NO_TIMEOUT);
while (irqRaised2 == 0)
- {
+ {
/* Wait for the Completion ISR on channel 2. */
- printf ("waiting for interrupt...\n");
- }
+ printf ("waiting for interrupt...\n");
+ }
/* Check the status of the completed transfer */
if (irqRaised2 < 0)
- {
+ {
/* Some error occured, break from the FOR loop. */
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("\r\nedma3_test_with_chaining: Event Miss Occured!!!\r\n");
result = EDMA3_DRV_clearErrorBits (hEdma, ch1Id);
break;
- }
}
}
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Match the Source and Destination Buffers. */
if (result == EDMA3_DRV_SOK)
- {
+ {
for (i = 0; i < (acnt*bcnt*ccnt); i++)
- {
+ {
if (srcBuff1[i] != dstBuff1[i])
- {
+ {
Istestpassed1 = 0;
- #ifdef EDMA3_DRV_DEBUG
+#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_chaining: Data write-read " \
- "matching FAILED at i = %d " \
- "(srcBuff1 -> dstBuff1)\r\n", i);
- #endif /* EDMA3_DRV_DEBUG */
+ "matching FAILED at i = %d " \
+ "(srcBuff1 -> dstBuff1)\r\n", i);
+#endif /* EDMA3_DRV_DEBUG */
break;
- }
}
+ }
if (i == (acnt*bcnt*ccnt))
- {
+ {
Istestpassed1 = 1u;
- }
+ }
for (i = 0; i < (acnt*bcnt*ccnt); i++)
- {
+ {
if (srcBuff2[i] != dstBuff2[i])
- {
+ {
Istestpassed2 = 0;
- #ifdef EDMA3_DRV_DEBUG
+#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_chaining: Data write-read " \
- "matching FAILED at i = %d " \
- "(srcBuff2 -> dstBuff2)\r\n", i);
- #endif /* EDMA3_DRV_DEBUG */
+ "matching FAILED at i = %d " \
+ "(srcBuff2 -> dstBuff2)\r\n", i);
+#endif /* EDMA3_DRV_DEBUG */
break;
- }
}
+ }
if (i == (acnt*bcnt*ccnt))
- {
+ {
Istestpassed2 = 1u;
- }
}
+ }
- if (result == EDMA3_DRV_SOK)
+ if (result == EDMA3_DRV_SOK)
{
- /* Free the previously allocated channels. */
- result = EDMA3_DRV_freeChannel (hEdma, ch1Id);
- if (result != EDMA3_DRV_SOK)
+ /* Free the previously allocated channels. */
+ result = EDMA3_DRV_freeChannel (hEdma, ch1Id);
+ if (result != EDMA3_DRV_SOK)
{
#ifdef EDMA3_DRV_DEBUG
- EDMA3_DRV_PRINTF("edma3_test_with_chaining: EDMA3_DRV_freeChannel() for ch 1 FAILED, error code: %d\r\n", result);
+ EDMA3_DRV_PRINTF("edma3_test_with_chaining: EDMA3_DRV_freeChannel() for ch 1 FAILED, error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
}
- else
+ else
{
- result = EDMA3_DRV_freeChannel (hEdma, ch2Id);
- if (result != EDMA3_DRV_SOK)
+ result = EDMA3_DRV_freeChannel (hEdma, ch2Id);
+ if (result != EDMA3_DRV_SOK)
{
#ifdef EDMA3_DRV_DEBUG
- EDMA3_DRV_PRINTF("edma3_test_with_chaining: EDMA3_DRV_freeChannel() for ch 2 FAILED, error code: %d\r\n", result);
+ EDMA3_DRV_PRINTF("edma3_test_with_chaining: EDMA3_DRV_freeChannel() for ch 2 FAILED, error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
}
}
if((Istestpassed1 == 1u) && (Istestpassed2 == 1u))
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_chaining PASSED\r\n");
#endif /* EDMA3_DRV_DEBUG */
- }
+ }
else
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_chaining FAILED\r\n");
#endif /* EDMA3_DRV_DEBUG */
result = ((EDMA3_DRV_SOK == result) ?
- EDMA3_DATA_MISMATCH_ERROR : result);
- }
-
-
- return result;
+ EDMA3_DATA_MISMATCH_ERROR : result);
}
-
+ return result;
+}
index 46c322dfeab7c062e13d9203b8f0f68f726532ad..a06dd97c6b83938b75d9c763567b853af4c4d5d1 100755 (executable)
/*
- * dma_link_test.c
- *
- * EDMA3 mem-to-mem data copy test case, using two DMA channels, linked to each
- * other.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* dma_link_test.c
+*
+* EDMA3 mem-to-mem data copy test case, using two DMA channels, linked to each
+* other.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#include "sample.h"
extern void *AppSemHandle1;
/**
- * \brief EDMA3 mem-to-mem data copy test case, using two DMA
- * channels, linked to each other.
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
+* \brief EDMA3 mem-to-mem data copy test case, using two DMA
+* channels, linked to each other.
+*
+* \param acnt [IN] Number of bytes in an array
+* \param bcnt [IN] Number of arrays in a frame
+* \param ccnt [IN] Number of frames in a block
+* \param syncType [IN] Synchronization type (A/AB Sync)
+*
+* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
EDMA3_DRV_Result edma3_test_with_link(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType)
- {
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType)
+{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};
uint32_t ch1Id = 0;
/* Initalize source and destination buffers */
for (count = 0u; count < (acnt*bcnt*ccnt); count++)
- {
+ {
srcBuff1[count] = (int)count+1;
srcBuff2[count] = (int)count+1;
/**
- * No need to initialize the destination buffer as it is being invalidated.
+ * No need to initialize the destination buffer as it is being invalidated.
dstBuff1[count] = initval;
dstBuff2[count] = initval;
*/
- }
+ }
#ifdef EDMA3_ENABLE_DCACHE
*/
/* Flush the Source Buffers */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheFlush((uint32_t)srcBuff2, (acnt*bcnt*ccnt));
- }
+ }
/* Invalidate the Destination Buffers */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstBuff2, (acnt*bcnt*ccnt));
- }
+ }
#endif /* EDMA3_ENABLE_DCACHE */
srcbidx = (int)acnt;
desbidx = (int)acnt;
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
/* A Sync Transfer Mode */
srccidx = (int)acnt;
descidx = (int)acnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
srccidx = ((int)acnt * (int)bcnt);
descidx = ((int)acnt * (int)bcnt);
- }
+ }
/* Setup for Channel 1*/
/* Request any DMA channel and any TCC */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1,
- (EDMA3_RM_EventQueue)0,
- &callback1, NULL);
- }
+ (EDMA3_RM_EventQueue)0,
+ &callback1, NULL);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Fill the PaRAM Set with transfer specific information */
paramSet.srcAddr = (uint32_t)(srcBuff1);
paramSet.destAddr = (uint32_t)(dstBuff1);
/**
- * Be Careful !!!
- * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767
- * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767
- */
+ * Be Careful !!!
+ * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767
+ * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767
+ */
paramSet.srcBIdx = srcbidx;
paramSet.destBIdx = desbidx;
paramSet.srcCIdx = srccidx;
paramSet.destCIdx = descidx;
/**
- * Be Careful !!!
- * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
- * ACNT/BCNT/CCNT must be greater than or equal to 1.
- * Maximum number of bytes in an array (ACNT) is 65535 bytes
- * Maximum number of arrays in a frame (BCNT) is 65535
- * Maximum number of frames in a block (CCNT) is 65535
- */
+ * Be Careful !!!
+ * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
+ * ACNT/BCNT/CCNT must be greater than or equal to 1.
+ * Maximum number of bytes in an array (ACNT) is 65535 bytes
+ * Maximum number of arrays in a frame (BCNT) is 65535
+ * Maximum number of frames in a block (CCNT) is 65535
+ */
paramSet.aCnt = acnt;
paramSet.bCnt = bcnt;
paramSet.cCnt = ccnt;
paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
paramSet.opt &= 0xFFFFFFFBu;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
- }
+ }
/* Now, write the PaRAM Set. */
result = EDMA3_DRV_setPaRAM (hEdma, ch1Id, ¶mSet);
- }
+ }
/*
- * There is another way to program the PaRAM Set using specific APIs
- * for different PaRAM set entries. It gives user more control and easier
- * to use interface. User can use any of the methods.
- * Below is the alternative way to program the PaRAM Set.
- */
+ * There is another way to program the PaRAM Set using specific APIs
+ * for different PaRAM set entries. It gives user more control and easier
+ * to use interface. User can use any of the methods.
+ * Below is the alternative way to program the PaRAM Set.
+ */
/*
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (uint32_t)(srcBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ {
+ result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (uint32_t)(srcBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setDestParams (hEdma, ch1Id,
- (uint32_t)(dstBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ {
+ result = EDMA3_DRV_setDestParams (hEdma, ch1Id,
+ (uint32_t)(dstBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);
- }
+ {
+ result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);
- }
+ {
+ result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);
+ }
if (result == EDMA3_DRV_SOK)
- {
- if (syncType == EDMA3_DRV_SYNC_A)
- {
- result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
- ccnt, BRCnt,
- EDMA3_DRV_SYNC_A);
- }
- else
- {
- result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
- ccnt, BRCnt,
- EDMA3_DRV_SYNC_AB);
- }
- }
+ {
+ if (syncType == EDMA3_DRV_SYNC_A)
+ {
+ result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
+ ccnt, BRCnt,
+ EDMA3_DRV_SYNC_A);
+ }
+ else
+ {
+ result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
+ ccnt, BRCnt,
+ EDMA3_DRV_SYNC_AB);
+ }
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setOptField (hEdma, ch1Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
- }
+ {
+ result = EDMA3_DRV_setOptField (hEdma, ch1Id,
+ EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setOptField (hEdma, ch1Id,
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
- }
+ {
+ result = EDMA3_DRV_setOptField (hEdma, ch1Id,
+ EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+ }
*/
/* Request any LINK channel and any TCC */
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Setup for Channel 2 */
ch2Id = EDMA3_DRV_LINK_CHANNEL;
tcc2 = EDMA3_DRV_TCC_ANY;
result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2,
- (EDMA3_RM_EventQueue)0,
- &callback1, NULL);
- }
+ (EDMA3_RM_EventQueue)0,
+ &callback1, NULL);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/*
- * Fill the PaRAM Set for the LINK channel
- * with transfer specific information.
- */
+ * Fill the PaRAM Set for the LINK channel
+ * with transfer specific information.
+ */
paramSet.srcAddr = (uint32_t)(srcBuff2);
paramSet.destAddr = (uint32_t)(dstBuff2);
/**
- * Be Careful !!!
- * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767
- * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767
- */
+ * Be Careful !!!
+ * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767
+ * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767
+ */
paramSet.srcBIdx = srcbidx;
paramSet.destBIdx = desbidx;
paramSet.srcCIdx = srccidx;
paramSet.destCIdx = descidx;
/**
- * Be Careful !!!
- * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
- * ACNT/BCNT/CCNT must be greater than or equal to 1.
- * Maximum number of bytes in an array (ACNT) is 65535 bytes
- * Maximum number of arrays in a frame (BCNT) is 65535
- * Maximum number of frames in a block (CCNT) is 65535
- */
+ * Be Careful !!!
+ * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
+ * ACNT/BCNT/CCNT must be greater than or equal to 1.
+ * Maximum number of bytes in an array (ACNT) is 65535 bytes
+ * Maximum number of arrays in a frame (BCNT) is 65535
+ * Maximum number of frames in a block (CCNT) is 65535
+ */
paramSet.aCnt = acnt;
paramSet.bCnt = bcnt;
paramSet.cCnt = ccnt;
paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
paramSet.opt &= 0xFFFFFFFBu;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
- }
+ }
/* Now, write the PaRAM Set. */
result = EDMA3_DRV_setPaRAM(hEdma, ch2Id, ¶mSet);
- }
+ }
/*
- * There is another way to program the PaRAM Set using specific APIs
- * for different PaRAM set entries. It gives user more control and easier
- * to use interface. User can use any of the methods.
- * Below is the alternative way to program the PaRAM Set.
- */
+ * There is another way to program the PaRAM Set using specific APIs
+ * for different PaRAM set entries. It gives user more control and easier
+ * to use interface. User can use any of the methods.
+ * Below is the alternative way to program the PaRAM Set.
+ */
/*
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (uint32_t)(srcBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ {
+ result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (uint32_t)(srcBuff2),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setDestParams (hEdma, ch2Id,
- (uint32_t)(dstBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ {
+ result = EDMA3_DRV_setDestParams (hEdma, ch2Id,
+ (uint32_t)(dstBuff2),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
- }
+ {
+ result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);
- }
+ {
+ result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);
+ }
if (result == EDMA3_DRV_SOK)
- {
- if (syncType == EDMA3_DRV_SYNC_A)
- {
- result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
- ccnt,
- BRCnt,EDMA3_DRV_SYNC_A);
- }
- else
- {
- result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
- ccnt,
- BRCnt,EDMA3_DRV_SYNC_AB);
- }
- }
+ {
+ if (syncType == EDMA3_DRV_SYNC_A)
+ {
+ result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
+ ccnt,
+ BRCnt,EDMA3_DRV_SYNC_A);
+ }
+ else
+ {
+ result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
+ ccnt,
+ BRCnt,EDMA3_DRV_SYNC_AB);
+ }
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setOptField (hEdma, ch2Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
- }
+ {
+ result = EDMA3_DRV_setOptField (hEdma, ch2Id,
+ EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setOptField (hEdma, ch2Id,
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
- }
+ {
+ result = EDMA3_DRV_setOptField (hEdma, ch2Id,
+ EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+ }
*/
/* Link both the channels. */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);
- }
+ }
/*
- * Since the transfer is going to happen in Manual mode of EDMA3
- * operation, we have to 'Enable the Transfer' multiple times.
- * Number of times depends upon the Mode (A/AB Sync)
- * and the different counts.
- */
+ * Since the transfer is going to happen in Manual mode of EDMA3
+ * operation, we have to 'Enable the Transfer' multiple times.
+ * Number of times depends upon the Mode (A/AB Sync)
+ * and the different counts.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
/*Need to activate next param*/
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
numenabled = bcnt * ccnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
numenabled = ccnt;
- }
+ }
for (i = 0; i < numenabled; i++)
- {
+ {
irqRaised1 = 0;
/*
- * Now enable the transfer for Master channel as many times
- * as calculated above.
- */
+ * Now enable the transfer for Master channel as many times
+ * as calculated above.
+ */
result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
- EDMA3_DRV_TRIG_MODE_MANUAL);
+ EDMA3_DRV_TRIG_MODE_MANUAL);
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n");
#endif /* EDMA3_DRV_DEBUG */
break;
- }
+ }
- edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
+ edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
while (irqRaised1 == 0)
- {
+ {
/* Wait for the Completion ISR on Master Channel. */
- printf ("waiting for interrupt...\n");
- }
+ printf ("waiting for interrupt...\n");
+ }
/* Check the status of the completed transfer */
if (irqRaised1 < 0)
- {
+ {
/* Some error occured, break from the FOR loop. */
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n");
result = EDMA3_DRV_clearErrorBits (hEdma, ch1Id);
break;
- }
}
}
+ }
/**
- * Now the transfer on Master channel is finished.
- * Trigger next (LINK) param.
- */
+ * Now the transfer on Master channel is finished.
+ * Trigger next (LINK) param.
+ */
if (EDMA3_DRV_SOK == result)
- {
+ {
for (i = 0; i < numenabled; i++)
- {
+ {
irqRaised1 = 0;
/*
- * Enable the transfer for LINK channel as many times
- * as calculated above.
- */
+ * Enable the transfer for LINK channel as many times
+ * as calculated above.
+ */
result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
- EDMA3_DRV_TRIG_MODE_MANUAL);
+ EDMA3_DRV_TRIG_MODE_MANUAL);
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("error from edma3_test_with_link\n\r\n");
#endif /* EDMA3_DRV_DEBUG */
break;
- }
+ }
- edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
+ edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
while (irqRaised1 == 0)
- {
+ {
/* Wait for the Completion ISR on the Link Channel. */
printf ("waiting for interrupt...\n");
- }
+ }
/* Check the status of the completed transfer */
if (irqRaised1 < 0)
- {
+ {
/* Some error occured, break from the FOR loop. */
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("\r\nedma3_test_with_link: Event Miss Occured!!!\r\n");
result = EDMA3_DRV_clearErrorBits (hEdma, ch2Id);
break;
- }
}
}
+ }
/* Match the Source and Destination Buffers. */
if (EDMA3_DRV_SOK == result)
- {
+ {
for (i = 0; i < (acnt*bcnt*ccnt); i++)
- {
+ {
if (srcBuff1[i] != dstBuff1[i])
- {
+ {
Istestpassed1 = 0u;
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \
- "matching FAILED at i = %d " \
- "(srcBuff1 -> dstBuff1)\r\n", i);
+ "matching FAILED at i = %d " \
+ "(srcBuff1 -> dstBuff1)\r\n", i);
#endif /* EDMA3_DRV_DEBUG */
break;
- }
}
+ }
if (i == (acnt*bcnt*ccnt))
- {
+ {
Istestpassed1 = 1u;
- }
+ }
for (i = 0; i < (acnt*bcnt*ccnt); i++)
- {
+ {
if (srcBuff2[i] != dstBuff2[i])
- {
+ {
Istestpassed2 = 0;
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link: Data write-read " \
- "matching FAILED at i = %d " \
- "(srcBuff2 -> dstBuff2)\r\n", i);
+ "matching FAILED at i = %d " \
+ "(srcBuff2 -> dstBuff2)\r\n", i);
#endif /* EDMA3_DRV_DEBUG */
break;
- }
}
+ }
if (i == (acnt*bcnt*ccnt))
- {
+ {
Istestpassed2 = 1u;
- }
+ }
/* Free the previously allocated channels. */
result = EDMA3_DRV_freeChannel (hEdma, ch1Id);
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link: EDMA3_DRV_freeChannel() " \
- "for ch1 FAILED, error code: %d\r\n", result);
+ "for ch1 FAILED, error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
- }
+ }
else
- {
+ {
result = EDMA3_DRV_freeChannel (hEdma, ch2Id);
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link: " \
- "EDMA3_DRV_freeChannel() for ch 2 FAILED, " \
- "error code: %d\r\n", result);
+ "EDMA3_DRV_freeChannel() for ch 2 FAILED, " \
+ "error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
- }
}
}
+ }
if((Istestpassed1 == 1u) && (Istestpassed2 == 1u))
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link PASSED\r\n");
#endif /* EDMA3_DRV_DEBUG */
- }
+ }
else
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_with_link FAILED\r\n");
#endif /* EDMA3_DRV_DEBUG */
result = ((EDMA3_DRV_SOK == result) ?
- EDMA3_DATA_MISMATCH_ERROR : result);
- }
-
-
+ EDMA3_DATA_MISMATCH_ERROR : result);
+ }
return result;
}
-
-
index 372bf35c65b1ca7261e3d4d73f9e12519928f9d3..e956e0bdacd619446cf9ee6aab0c4d55d4b457ee 100644 (file)
/*
- * dma_misc_test.c
- *
- * Miscellaneous EDMA3 test cases.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* dma_misc_test.c
+*
+* Miscellaneous EDMA3 test cases.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#include "sample.h"
/**
- * \brief EDMA3 misc test cases.
- * This test case will read/write to some CC registers.
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
+* \brief EDMA3 misc test cases.
+* This test case will read/write to some CC registers.
+*
+* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
EDMA3_DRV_Result edma3_misc_test(EDMA3_DRV_Handle hEdma)
- {
+{
EDMA3_DRV_Result drvResult = EDMA3_DRV_SOK;
uint32_t ccRegOffset = 0u;
uint32_t ccRegVal = 0u;
/**
- *1. Try fetching some CC registers value.
- * It should PASS.
- */
+ *1. Try fetching some CC registers value.
+ * It should PASS.
+ */
/* PID Register */
ccRegOffset = 0x0u;
ccRegVal = 0;
drvResult = EDMA3_DRV_getCCRegister(hEdma, ccRegOffset, &ccRegVal);
if (drvResult != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Failed, test FAILED\r\n", ccRegOffset);
#endif
- }
+ }
else
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Passed, test PASSED\r\n", ccRegOffset);
#endif
#ifdef EDMA3_DEBUG_PRINT
EDMA3_DEBUG_PRINTF ("Fetched CC Register at Offset 0X%x, Value = 0X%x\r\n", ccRegOffset, ccRegVal);
#endif /* EDMA3_DEBUG_PRINT */
- }
+ }
if (drvResult == EDMA3_DRV_SOK)
- {
+ {
/* Fetch DRAE1 Register */
ccRegOffset = 0x0348u;
ccRegVal = 0;
drvResult = EDMA3_DRV_getCCRegister(hEdma, ccRegOffset, &ccRegVal);
if (drvResult != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Failed, test FAILED\r\n", ccRegOffset);
#endif
- }
+ }
else
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Passed, test PASSED\r\n", ccRegOffset);
#endif
#ifdef EDMA3_DEBUG_PRINT
EDMA3_DEBUG_PRINTF ("Fetched CC Register at Offset 0X%x, Value = 0X%x\r\n", ccRegOffset, ccRegVal);
#endif /* EDMA3_DEBUG_PRINT */
- }
}
+ }
if (drvResult == EDMA3_DRV_SOK)
- {
+ {
/* Fetch QWMTHRA Register */
ccRegOffset = 0x0620u;
ccRegVal = 0;
drvResult = EDMA3_DRV_getCCRegister(hEdma, ccRegOffset, &ccRegVal);
if (drvResult != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Failed, test FAILED\r\n", ccRegOffset);
#endif
return drvResult;
- }
+ }
else
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Passed, test PASSED\r\n", ccRegOffset);
#endif
#ifdef EDMA3_DEBUG_PRINT
EDMA3_DEBUG_PRINTF ("Fetched CC Register at Offset 0X%x, Value = 0X%x\r\n", ccRegOffset, ccRegVal);
#endif /* EDMA3_DEBUG_PRINT */
- }
}
+ }
/**
- * 2. Try fetching some CC registers value, whose offset is not 4-bytes
- * aligned. It should FAIL.
- */
+ * 2. Try fetching some CC registers value, whose offset is not 4-bytes
+ * aligned. It should FAIL.
+ */
if (drvResult == EDMA3_DRV_SOK)
- {
+ {
ccRegOffset = 0x1002u;
ccRegVal = 0x0u;
drvResult = EDMA3_DRV_getCCRegister(hEdma, ccRegOffset, &ccRegVal);
if (drvResult == EDMA3_DRV_E_INVALID_PARAM)
- {
+ {
#ifdef EDMA3_DEBUG_PRINT
EDMA3_DEBUG_PRINTF ("Fetching Invalid CC Register (offset 0X%x) Failed, test PASSED\r\n", ccRegOffset);
#endif /* EDMA3_DEBUG_PRINT */
drvResult = EDMA3_DRV_SOK;
- }
+ }
else
- {
+ {
#ifdef EDMA3_DEBUG_PRINT
EDMA3_DEBUG_PRINTF ("Fetching Invalid CC Register (offset 0X%x) Passed, test FAILED\r\n", ccRegOffset);
#endif /* EDMA3_DEBUG_PRINT */
- }
}
+ }
/**
- * 3. Read CC Register QWMTHRA. Store the current value. Write a different
- * value on it. Read it back. Write the original value again. Read it back to
- * cross-check. It should PASS.
- */
+ * 3. Read CC Register QWMTHRA. Store the current value. Write a different
+ * value on it. Read it back. Write the original value again. Read it back to
+ * cross-check. It should PASS.
+ */
if (drvResult == EDMA3_DRV_SOK)
- {
+ {
ccRegOffset = 0x0620u;
origRegVal = 0x0u;
drvResult = EDMA3_DRV_getCCRegister(hEdma, ccRegOffset, &origRegVal);
if (drvResult != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Failed, test FAILED\r\n", ccRegOffset);
#endif
- }
+ }
else
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("Fetching CC Register (offset 0X%x) Passed, test PASSED\r\n", ccRegOffset);
#endif
/* Find the new value to be written, it depends on the no of event queues */
switch (origRegVal)
- {
+ {
/* Write a new value on the same register */
- case 0x10:
- /* 1 TC */
- newRegVal = 0x0Fu;
- break;
-
- case 0x1010:
- /* 2 TC */
- newRegVal = 0x0F0Fu;
- break;
-
- case 0x101010:
- /* 3 TC */
- newRegVal = 0x0F0F0Fu;
- break;
-
- case 0x10101010:
- /* 4 TC */
- newRegVal = 0x0F0F0F0Fu;
- break;
-
- default:
- newRegVal = origRegVal;
- break;
- }
+ case 0x10:
+ /* 1 TC */
+ newRegVal = 0x0Fu;
+ break;
+
+ case 0x1010:
+ /* 2 TC */
+ newRegVal = 0x0F0Fu;
+ break;
+
+ case 0x101010:
+ /* 3 TC */
+ newRegVal = 0x0F0F0Fu;
+ break;
+
+ case 0x10101010:
+ /* 4 TC */
+ newRegVal = 0x0F0F0F0Fu;
+ break;
+
+ default:
+ newRegVal = origRegVal;
+ break;
+ }
drvResult = EDMA3_DRV_setCCRegister (hEdma, ccRegOffset, newRegVal);
if (drvResult == EDMA3_DRV_SOK)
- {
+ {
/* If write is successful, read it back to check */
ccRegVal = 0x0u;
drvResult = EDMA3_DRV_getCCRegister (hEdma, ccRegOffset, &ccRegVal);
if (drvResult == EDMA3_DRV_SOK)
- {
+ {
/* Check with the value which we have written */
if (newRegVal == ccRegVal)
- {
+ {
#ifdef EDMA3_DEBUG_PRINT
EDMA3_DEBUG_PRINTF ("Value written successfully \r\n");
#endif /* EDMA3_DEBUG_PRINT */
- }
+ }
else
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("QWMTHRA write FAILED \r\n");
#endif
drvResult = EDMA3_DRV_E_INVALID_PARAM;
- }
}
+ }
/* Restore the original value */
if (drvResult == EDMA3_DRV_SOK)
- {
+ {
drvResult = EDMA3_DRV_setCCRegister (hEdma, ccRegOffset, origRegVal);
if (drvResult != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DEBUG_PRINT
EDMA3_DEBUG_PRINTF ("QWMTHRA Restore FAILED\r\n");
#endif /* EDMA3_DEBUG_PRINT */
- }
+ }
else
- {
+ {
#ifdef EDMA3_DEBUG_PRINT
EDMA3_DEBUG_PRINTF ("QWMTHRA Restore Successful\r\n");
#endif /* EDMA3_DEBUG_PRINT */
- }
}
}
}
}
-
-
- return drvResult;
}
-
+ return drvResult;
+}
diff --git a/examples/edma3_driver/src/dma_ping_pong_test.c b/examples/edma3_driver/src/dma_ping_pong_test.c
index eb863289c3d10d23c29838e0ca916f8e795e9997..69cf835730659c560f39608ccca19fe1ea8a846f 100755 (executable)
/*
- * dma_ping_pong_test.c
- *
- * EDMA3 ping-pong buffers based data copy test case, using a DMA and a link
- * channel.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* dma_ping_pong_test.c
+*
+* EDMA3 ping-pong buffers based data copy test case, using a DMA and a link
+* channel.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#include "sample.h"
/** Test Case Description **/
/**
- * There are two big buffers of size (PING_PONG_NUM_COLUMNS * PING_PONG_NUM_ROWS).
- * Both are present in DDR and are known as pingpongSrcBuf and pingpongDestBuf.
- * There are two small buffers of size (PING_PONG_L1D_BUFFER_SIZE). They are known as
- * ping buffer and pong buffer.
- * The pingpongSrcBuf is divided into chunks, each having size of
- * PING_PONG_L1D_BUFFER_SIZE. Data is being transferred from pingpongSrcBuf
- * to either ping or pong buffers, using EDMA3. Logic behind using two ping pong
- * buffers is that one can be processed by DSP while the other is used by EDMA3
- * for data movement. So ping and pong are alternately used by EDMA3 and DSP.
- * Also, to simulate the real world scenario, as a part of DSP processing,
- * I am copying data from ping/pong buffers to pingpongDestBuf.
- * In the end, I compare pingpongSrcBuf and pingpongDestBuf to check whether
- * the algorithm has worked fine.
- */
+* There are two big buffers of size (PING_PONG_NUM_COLUMNS * PING_PONG_NUM_ROWS).
+* Both are present in DDR and are known as pingpongSrcBuf and pingpongDestBuf.
+* There are two small buffers of size (PING_PONG_L1D_BUFFER_SIZE). They are known as
+* ping buffer and pong buffer.
+* The pingpongSrcBuf is divided into chunks, each having size of
+* PING_PONG_L1D_BUFFER_SIZE. Data is being transferred from pingpongSrcBuf
+* to either ping or pong buffers, using EDMA3. Logic behind using two ping pong
+* buffers is that one can be processed by DSP while the other is used by EDMA3
+* for data movement. So ping and pong are alternately used by EDMA3 and DSP.
+* Also, to simulate the real world scenario, as a part of DSP processing,
+* I am copying data from ping/pong buffers to pingpongDestBuf.
+* In the end, I compare pingpongSrcBuf and pingpongDestBuf to check whether
+* the algorithm has worked fine.
+*/
/**
- * Number of columns in the bigger source buffer.
- */
+* Number of columns in the bigger source buffer.
+*/
#define PING_PONG_NUM_COLUMNS (72u)
/**
- * Number of columns in the bigger source buffer.
- */
+* Number of columns in the bigger source buffer.
+*/
#define PING_PONG_NUM_ROWS (48u)
/* ACNT is equal to number of columns. */
#ifdef EDMA3_ENABLE_DCACHE
/* Cache line aligned big source buffer. */
/**
- * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
- * alignment boundary is the maximum of the symbol\92s default alignment value
- * or the value of the constant in bytes. The constant must be a power of 2.
- * The syntax of the pragma in C is:
- * #pragma DATA_ALIGN (symbol, constant);
- */
+* The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
+* alignment boundary is the maximum of the symbol\92s default alignment value
+* or the value of the constant in bytes. The constant must be a power of 2.
+* The syntax of the pragma in C is:
+* #pragma DATA_ALIGN (symbol, constant);
+*/
#pragma DATA_ALIGN(_pingpongSrcBuf, EDMA3_CACHE_LINE_SIZE_IN_BYTES);
#endif /* #ifdef EDMA3_ENABLE_DCACHE */
#pragma DATA_SECTION(_pingpongSrcBuf, ".my_sect_ddr");
@@ -105,20 +105,20 @@ signed char __attribute__((section(".my_sect_ddr"))) _pingpongSrcBuf[PING_PONG_D
#endif
/**
- * Ping pong destination buffer.
- * It will be used to copy data from L1D ping/pong buffers to check the
- * validity.
- */
+* Ping pong destination buffer.
+* It will be used to copy data from L1D ping/pong buffers to check the
+* validity.
+*/
#ifndef GCC_BUILD
#ifdef EDMA3_ENABLE_DCACHE
/* Cache line aligned big destination buffer. */
/**
- * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
- * alignment boundary is the maximum of the symbol\92s default alignment value
- * or the value of the constant in bytes. The constant must be a power of 2.
- * The syntax of the pragma in C is:
- * #pragma DATA_ALIGN (symbol, constant);
- */
+* The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
+* alignment boundary is the maximum of the symbol\92s default alignment value
+* or the value of the constant in bytes. The constant must be a power of 2.
+* The syntax of the pragma in C is:
+* #pragma DATA_ALIGN (symbol, constant);
+*/
#pragma DATA_ALIGN(_pingpongDestBuf, EDMA3_CACHE_LINE_SIZE_IN_BYTES);
#endif /* #ifdef EDMA3_ENABLE_DCACHE */
#pragma DATA_SECTION(_pingpongDestBuf, ".my_sect_ddr");
@@ -137,18 +137,18 @@ signed char __attribute__((section(".my_sect_ddr"))) _pingpongDestBuf[PING_PONG_
#ifdef EDMA3_ENABLE_DCACHE
/* Cache line aligned destination buffer 1 i.e. Ping buffer. */
/**
- * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
- * alignment boundary is the maximum of the symbol\92s default alignment value
- * or the value of the constant in bytes. The constant must be a power of 2.
- * The syntax of the pragma in C is:
- * #pragma DATA_ALIGN (symbol, constant);
- */
+* The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
+* alignment boundary is the maximum of the symbol\92s default alignment value
+* or the value of the constant in bytes. The constant must be a power of 2.
+* The syntax of the pragma in C is:
+* #pragma DATA_ALIGN (symbol, constant);
+*/
#pragma DATA_ALIGN(_dstL1DBuff1, EDMA3_CACHE_LINE_SIZE_IN_BYTES);
#endif /* #ifdef EDMA3_ENABLE_DCACHE */
#ifdef __TMS470__
- #pragma DATA_SECTION(_dstL1DBuff1, ".my_sect_ddr");
+#pragma DATA_SECTION(_dstL1DBuff1, ".my_sect_ddr");
#else
- #pragma DATA_SECTION(_dstL1DBuff1, ".my_sect_iram");
+#pragma DATA_SECTION(_dstL1DBuff1, ".my_sect_iram");
#endif
signed char _dstL1DBuff1[PING_PONG_L1D_BUFFER_SIZE];
#else
@@ -171,18 +171,18 @@ signed char __attribute__((section(".my_sect_iram"))) _dstL1DBuff1[PING_PONG_L1D
#ifdef EDMA3_ENABLE_DCACHE
/* Cache line aligned destination buffer 2 i.e. Pong buffer. */
/**
- * The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
- * alignment boundary is the maximum of the symbol\92s default alignment value
- * or the value of the constant in bytes. The constant must be a power of 2.
- * The syntax of the pragma in C is:
- * #pragma DATA_ALIGN (symbol, constant);
- */
+* The DATA_ALIGN pragma aligns the symbol to an alignment boundary. The
+* alignment boundary is the maximum of the symbol\92s default alignment value
+* or the value of the constant in bytes. The constant must be a power of 2.
+* The syntax of the pragma in C is:
+* #pragma DATA_ALIGN (symbol, constant);
+*/
#pragma DATA_ALIGN(_dstL1DBuff2, EDMA3_CACHE_LINE_SIZE_IN_BYTES);
#endif /* #ifdef EDMA3_ENABLE_DCACHE */
#ifdef __TMS470__
- #pragma DATA_SECTION(_dstL1DBuff2, ".my_sect_ddr");
+#pragma DATA_SECTION(_dstL1DBuff2, ".my_sect_ddr");
#else
- #pragma DATA_SECTION(_dstL1DBuff2, ".my_sect_iram");
+#pragma DATA_SECTION(_dstL1DBuff2, ".my_sect_iram");
#endif
signed char _dstL1DBuff2[PING_PONG_L1D_BUFFER_SIZE];
#else
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
/**
- * Copy the L1D ping-pong buffers from L1D to DDR using CPU.
- * This is kind of dummy processing routine.
- */
+ * Copy the L1D ping-pong buffers from L1D to DDR using CPU.
+ * This is kind of dummy processing routine.
+ */
if (buff_id == 1u)
- {
+ {
/* Copy pong buffer */
/* Invalidate first if cache is enabled, otherwise CPU will take from cache. */
/**
- * Since the ping/pong buffers are in IRAM, there is no need of invalidating
- * them. If they are in DDR, invalidate them.
- */
+ * Since the ping/pong buffers are in IRAM, there is no need of invalidating
+ * them. If they are in DDR, invalidate them.
+ */
#ifdef EDMA3_ENABLE_DCACHE
-
+
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstL1DBuff2,
- PING_PONG_L1D_BUFFER_SIZE);
- }
-
+ PING_PONG_L1D_BUFFER_SIZE);
+ }
+
#endif /* EDMA3_ENABLE_DCACHE */
if (result == EDMA3_DRV_SOK)
- {
+ {
edma3MemCpy((void *)(pingpongDestBufCopy),
- (const void *)(dstL1DBuff2),
- PING_PONG_L1D_BUFFER_SIZE);
- }
+ (const void *)(dstL1DBuff2),
+ PING_PONG_L1D_BUFFER_SIZE);
}
+ }
else
- {
+ {
/* Copy ping buffer */
/* Invalidate first if cache is enabled, otherwise CPU will take from cache. */
#ifdef EDMA3_ENABLE_DCACHE
-
+
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstL1DBuff1,
- PING_PONG_L1D_BUFFER_SIZE);
- }
-
+ PING_PONG_L1D_BUFFER_SIZE);
+ }
+
#endif /* EDMA3_ENABLE_DCACHE */
if (result == EDMA3_DRV_SOK)
- {
+ {
edma3MemCpy((void *)(pingpongDestBufCopy),
- (const void *)(dstL1DBuff1),
- PING_PONG_L1D_BUFFER_SIZE);
- }
+ (const void *)(dstL1DBuff1),
+ PING_PONG_L1D_BUFFER_SIZE);
}
+ }
/* Adjust the pointer. */
pingpongDestBufCopy += PING_PONG_L1D_BUFFER_SIZE;
/**
- * \brief EDMA3 ping-pong based data copy test case, using a DMA and
- * a link channel.
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
+* \brief EDMA3 ping-pong based data copy test case, using a DMA and
+* a link channel.
+*
+* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
EDMA3_DRV_Result edma3_test_ping_pong_mode(EDMA3_DRV_Handle hEdma)
- {
+{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};
/* One master channel */
/* Initalize source buffer for PING_PONG_DDR_BUFFER_SIZE bytes of data */
for (count = 0u; count < PING_PONG_DDR_BUFFER_SIZE; count++)
- {
+ {
pingpongSrcBuf[count] = (count % 0xFF);
- }
+ }
#ifdef EDMA3_ENABLE_DCACHE
*/
/* Flush the Source Buffer */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheFlush((uint32_t)pingpongSrcBuf, PING_PONG_DDR_BUFFER_SIZE);
- }
+ }
/* Invalidate the Destination Buffers */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)pingpongDestBuf, PING_PONG_DDR_BUFFER_SIZE);
- }
+ }
/**
- * Since the ping/pong buffers are in IRAM, there is no need of invalidating
- * them. If they are in DDR, invalidate them.
- */
+ * Since the ping/pong buffers are in IRAM, there is no need of invalidating
+ * them. If they are in DDR, invalidate them.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstL1DBuff1, PING_PONG_L1D_BUFFER_SIZE);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstL1DBuff2, PING_PONG_L1D_BUFFER_SIZE);
- }
+ }
#endif /* EDMA3_ENABLE_DCACHE */
/* Request any DMA channel and any TCC */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
- (EDMA3_RM_EventQueue)0,
- &callback1, NULL);
- }
+ (EDMA3_RM_EventQueue)0,
+ &callback1, NULL);
+ }
/* If successful, allocate the two link channels. */
if (result == EDMA3_DRV_SOK)
- {
+ {
lChId1 = EDMA3_DRV_LINK_CHANNEL;
lChId2 = EDMA3_DRV_LINK_CHANNEL;
result = (
- (EDMA3_DRV_requestChannel (hEdma, &lChId1, NULL,
- (EDMA3_RM_EventQueue)0,
- &callback1, NULL))
- ||
- (EDMA3_DRV_requestChannel (hEdma, &lChId2, NULL,
- (EDMA3_RM_EventQueue)0,
- &callback1, NULL))
- );
- }
+ (EDMA3_DRV_requestChannel (hEdma, &lChId1, NULL,
+ (EDMA3_RM_EventQueue)0,
+ &callback1, NULL))
+ ||
+ (EDMA3_DRV_requestChannel (hEdma, &lChId2, NULL,
+ (EDMA3_RM_EventQueue)0,
+ &callback1, NULL))
+ );
+ }
/**
- * Fill the PaRAM Sets associated with all these channels with transfer
- * specific information.
- */
+ * Fill the PaRAM Sets associated with all these channels with transfer
+ * specific information.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
paramSet.srcBIdx = srcbidx;
paramSet.destBIdx = desbidx;
paramSet.srcCIdx = srccidx;
/* Write to the master DMA channel first. */
result = EDMA3_DRV_setPaRAM(hEdma, chId, ¶mSet);
- }
+ }
/* If write is successful, write the same thing to first link channel. */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setPaRAM(hEdma, lChId1, ¶mSet);
- }
+ }
/**
- * Now modify the dest addresses and write the param set to the
- * second link channel.
- */
+ * Now modify the dest addresses and write the param set to the
+ * second link channel.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
paramSet.destAddr = (uint32_t)(dstL1DBuff2);
result = EDMA3_DRV_setPaRAM(hEdma, lChId2, ¶mSet);
- }
+ }
/**
- * Do the linking now.
- * Master DMA channel is linked to IInd Link channel.
- * IInd Link channel is linked to Ist Link channel.
- * Ist Link channel is again linked to IInd Link channel.
- */
+ * Do the linking now.
+ * Master DMA channel is linked to IInd Link channel.
+ * IInd Link channel is linked to Ist Link channel.
+ * Ist Link channel is again linked to IInd Link channel.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = (
- (EDMA3_DRV_linkChannel (hEdma, chId, lChId2))
- ||
- (EDMA3_DRV_linkChannel (hEdma, lChId2, lChId1))
- ||
- (EDMA3_DRV_linkChannel (hEdma, lChId1, lChId2))
- );
- }
+ (EDMA3_DRV_linkChannel (hEdma, chId, lChId2))
+ ||
+ (EDMA3_DRV_linkChannel (hEdma, lChId2, lChId1))
+ ||
+ (EDMA3_DRV_linkChannel (hEdma, lChId1, lChId2))
+ );
+ }
/**
- * Save the handle to the master dma channel param set.
- * It will be used later to modify the source address quickly.
- */
+ * Save the handle to the master dma channel param set.
+ * It will be used later to modify the source address quickly.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_getPaRAMPhyAddr(hEdma, chId, &phyaddress);
- }
+ }
/*
- Algorithm used in the ping pong copy:
7. Application starts processing pong buffer.
8. Repeat from step 3, until image exhausted.
- EDMA re-programming should be minimized to reduce overhead (PaRAM
- accesses via slow config bus), i.e. use 2 reload PaRAM entries, and
- only change src address fields.
+ accesses via slow config bus), i.e. use 2 reload PaRAM entries, and
+ only change src address fields.
*/
if (result == EDMA3_DRV_SOK)
- {
+ {
irqRaised1 = 0;
/* Param address successfully fetched. */
param_handle = (EDMA3_DRV_ParamentryRegs *)phyaddress;
/* Step 1 */
result = EDMA3_DRV_enableTransfer (hEdma, chId,
- EDMA3_DRV_TRIG_MODE_MANUAL);
+ EDMA3_DRV_TRIG_MODE_MANUAL);
/**
- * Every time a transfer is triggered, numenabled is decremented.
- */
+ * Every time a transfer is triggered, numenabled is decremented.
+ */
numenabled--;
/**
- * Every time a transfer is triggered, pingpongSrcBufCopy is
- * incremented to point it to correct source address.
- */
+ * Every time a transfer is triggered, pingpongSrcBufCopy is
+ * incremented to point it to correct source address.
+ */
pingpongSrcBufCopy += PING_PONG_L1D_BUFFER_SIZE;
/* Step 2 */
/* Wait for the Completion ISR. */
- edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
+ edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
while (irqRaised1 == 0u)
- {
+ {
/* Wait for the Completion ISR. */
printf ("waiting for interrupt...\n");
- }
}
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Need to activate next param till numenabled is exhausted. */
for (i = 0; numenabled; i++)
- {
+ {
irqRaised1 = 0;
/*
- * Now modify the source buffer in the param set
- * loaded to the master dma channel and trigger
- * the transfer again..
- */
+ * Now modify the source buffer in the param set
+ * loaded to the master dma channel and trigger
+ * the transfer again..
+ */
param_handle->SRC = (uint32_t)pingpongSrcBufCopy;
/* Step 3 */
result = EDMA3_DRV_enableTransfer (hEdma, chId,
- EDMA3_DRV_TRIG_MODE_MANUAL);
+ EDMA3_DRV_TRIG_MODE_MANUAL);
/**
- * Every time a transfer is triggered, numenabled is decremented.
- */
+ * Every time a transfer is triggered, numenabled is decremented.
+ */
numenabled--;
/**
- * Every time a transfer is triggered, pingpongSrcBufCopy is
- * incremented to point it to correct source address.
- */
+ * Every time a transfer is triggered, pingpongSrcBufCopy is
+ * incremented to point it to correct source address.
+ */
pingpongSrcBufCopy += PING_PONG_L1D_BUFFER_SIZE;
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("edma3_test_ping_pong_mode: EDMA3_DRV_enableTransfer " \
- "Failed, error code: %d\r\n", result);
+ "Failed, error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
break;
- }
+ }
/**
- * Step 4, copy the ping buffer to the dest buffer in
- * DDR (using CPU), as a part of processing.
- */
+ * Step 4, copy the ping buffer to the dest buffer in
+ * DDR (using CPU), as a part of processing.
+ */
result = process_ping_pong_buffer(0u);
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("edma3_test_ping_pong_mode: process_ping_pong_buffer " \
- "Failed, error code: %d\r\n", result);
+ "Failed, error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
break;
- }
+ }
/* Step 5 */
/* Wait for the Completion ISR. */
- edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
+ edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
while (irqRaised1 == 0u)
- {
+ {
/* Wait for the Completion ISR. */
printf ("waiting for interrupt...\n");
- }
+ }
/* Check the status of the completed transfer */
if (irqRaised1 < 0)
- {
+ {
/* Some error occured, break from the FOR loop. */
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("\r\nedma3_test: Event Miss Occured!!!\r\n");
/* Clear the error bits first */
result = EDMA3_DRV_clearErrorBits (hEdma, chId);
break;
- }
+ }
/**
- * Last row will be transferred by the Pong buffer.
- * So this step should be jumped over.
- * Check for that...
- */
+ * Last row will be transferred by the Pong buffer.
+ * So this step should be jumped over.
+ * Check for that...
+ */
if (numenabled)
- {
+ {
irqRaised1 = 0;
/* Step 6 */
/*
- * Now modify the source buffer in the param set
- * again and trigger the transfer...
- */
+ * Now modify the source buffer in the param set
+ * again and trigger the transfer...
+ */
param_handle->SRC = (uint32_t)pingpongSrcBufCopy;
result = EDMA3_DRV_enableTransfer (hEdma, chId,
- EDMA3_DRV_TRIG_MODE_MANUAL);
+ EDMA3_DRV_TRIG_MODE_MANUAL);
/**
- * Every time a transfer is triggered, numenabled is decremented.
- */
+ * Every time a transfer is triggered, numenabled is decremented.
+ */
numenabled--;
/**
- * Every time a transfer is triggered, pingpongSrcBufCopy is
- * incremented to point it to correct source address.
- */
+ * Every time a transfer is triggered, pingpongSrcBufCopy is
+ * incremented to point it to correct source address.
+ */
pingpongSrcBufCopy += PING_PONG_L1D_BUFFER_SIZE;
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("edma3_test_ping_pong_mode: EDMA3_DRV_enableTransfer " \
- "Failed, error code: %d\r\n", result);
+ "Failed, error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
break;
- }
}
+ }
/**
- * Step 7, copy the pong buffer to the dest buffer in
- * DDR (using CPU), as a part of processing.
- */
+ * Step 7, copy the pong buffer to the dest buffer in
+ * DDR (using CPU), as a part of processing.
+ */
result = process_ping_pong_buffer(1u);
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("edma3_test_ping_pong_mode: process_ping_pong_buffer " \
- "Failed, error code: %d\r\n", result);
+ "Failed, error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
break;
- }
+ }
if (numenabled)
{
- /* Wait for the Completion ISR. */
- edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
- while (irqRaised1 == 0u)
+ /* Wait for the Completion ISR. */
+ edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
+ while (irqRaised1 == 0u)
{
- /* Wait for the Completion ISR. */
- printf ("waiting for interrupt...\n");
+ /* Wait for the Completion ISR. */
+ printf ("waiting for interrupt...\n");
}
}
/* Check the status of the completed transfer */
if (irqRaised1 < 0)
- {
+ {
/* Some error occured, break from the FOR loop. */
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("\r\nedma3_test: Event Miss Occured!!!\r\n");
/* Clear the error bits first */
result = EDMA3_DRV_clearErrorBits (hEdma, chId);
break;
- }
}
}
+ }
if (EDMA3_DRV_SOK == result)
- {
+ {
/* Match the Source and Destination Buffers. */
for (i = 0; i < PING_PONG_DDR_BUFFER_SIZE; i++)
- {
+ {
if (pingpongSrcBuf[i] != pingpongDestBuf[i])
- {
+ {
Istestpassed = 0u;
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_ping_pong_mode: Data write-read matching" \
- "FAILED at i = %d\r\n", i);
+ "FAILED at i = %d\r\n", i);
#endif /* EDMA3_DRV_DEBUG */
break;
- }
}
+ }
if (i == PING_PONG_DDR_BUFFER_SIZE)
- {
+ {
Istestpassed = 1u;
- }
+ }
/* Free the previously allocated channels. */
result = (
- (EDMA3_DRV_freeChannel (hEdma, chId))
- ||
- (EDMA3_DRV_freeChannel (hEdma, lChId1))
- ||
- (EDMA3_DRV_freeChannel (hEdma, lChId2))
- );
+ (EDMA3_DRV_freeChannel (hEdma, chId))
+ ||
+ (EDMA3_DRV_freeChannel (hEdma, lChId1))
+ ||
+ (EDMA3_DRV_freeChannel (hEdma, lChId2))
+ );
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_ping_pong_mode: EDMA3_DRV_freeChannel() FAILED, " \
- "error code: %d\r\n", result);
+ "error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
- }
}
+ }
if(Istestpassed == 1u)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_ping_pong_mode PASSED\r\n");
#endif /* EDMA3_DRV_DEBUG */
- }
+ }
else
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_ping_pong_mode FAILED\r\n");
#endif /* EDMA3_DRV_DEBUG */
result = ((EDMA3_DRV_SOK == result) ?
- EDMA3_DATA_MISMATCH_ERROR : result);
- }
-
-
- return result;
+ EDMA3_DATA_MISMATCH_ERROR : result);
}
+ return result;
+}
index 8a7737e9c03336771629843c7f37e2483435abf4..948dc1acf453385d965f1b59430ae51c79106b44 100644 (file)
/*
- * dma_poll_test.c
- *
- * Test case demonstrating the poll mode scenario. User has requested a data
- * transfer without giving any callback function. After programming and
- * enabling the channel, he uses different APIs (meant to be used in poll mode)
- * to check the status of ongoing transfer. Interrupt will NOT occur in this
- * case.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* dma_poll_test.c
+*
+* Test case demonstrating the poll mode scenario. User has requested a data
+* transfer without giving any callback function. After programming and
+* enabling the channel, he uses different APIs (meant to be used in poll mode)
+* to check the status of ongoing transfer. Interrupt will NOT occur in this
+* case.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#include "sample.h"
extern signed char *dstBuff1;
/**
- * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
- * This test case doesnot rely on the callback mechanism.
- * Instead, it Polls the IPR register to check the transfer
- * completion status.
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
+* \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
+* This test case doesnot rely on the callback mechanism.
+* Instead, it Polls the IPR register to check the transfer
+* completion status.
+*
+* \param acnt [IN] Number of bytes in an array
+* \param bcnt [IN] Number of arrays in a frame
+* \param ccnt [IN] Number of frames in a block
+* \param syncType [IN] Synchronization type (A/AB Sync)
+*
+* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
EDMA3_DRV_Result edma3_test_poll_mode(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType)
- {
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType)
+{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
uint32_t chId = 0;
uint32_t tcc = 0;
/* Initalize source and destination buffers */
for (count = 0u; count < (acnt*bcnt*ccnt); count++)
- {
+ {
srcBuff1[count] = (int)count+5;
/**
- * No need to initialize the destination buffer as it is being invalidated.
+ * No need to initialize the destination buffer as it is being invalidated.
dstBuff1[count] = initval;
*/
- }
+ }
#ifdef EDMA3_ENABLE_DCACHE
*/
/* Flush the Source Buffer */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
- }
+ }
/* Invalidate the Destination Buffer */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
- }
+ }
#endif /* EDMA3_ENABLE_DCACHE */
desbidx = (int)acnt;
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
/* A Sync Transfer Mode */
srccidx = (int)acnt;
descidx = (int)acnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
srccidx = ((int)acnt * (int)bcnt);
descidx = ((int)acnt * (int)bcnt);
- }
+ }
/* Setup for Channel 1*/
/* Request any DMA channel and any TCC */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
- (EDMA3_RM_EventQueue)0,
- NULL, NULL);
- }
+ (EDMA3_RM_EventQueue)0,
+ NULL, NULL);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setSrcParams (hEdma, chId, (uint32_t)(srcBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setDestParams (hEdma, chId, (uint32_t)(dstBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
- BRCnt, EDMA3_DRV_SYNC_A);
- }
+ BRCnt, EDMA3_DRV_SYNC_A);
+ }
else
- {
+ {
result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
- BRCnt, EDMA3_DRV_SYNC_AB);
- }
+ BRCnt, EDMA3_DRV_SYNC_AB);
}
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setOptField (hEdma, chId,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setOptField (hEdma, chId,
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+ }
/*
- * Since the transfer is going to happen in Manual mode of EDMA3
- * operation, we have to 'Enable the Transfer' multiple times.
- * Number of times depends upon the Mode (A/AB Sync)
- * and the different counts.
- */
+ * Since the transfer is going to happen in Manual mode of EDMA3
+ * operation, we have to 'Enable the Transfer' multiple times.
+ * Number of times depends upon the Mode (A/AB Sync)
+ * and the different counts.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
/*Need to activate next param*/
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
numenabled = bcnt * ccnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
numenabled = ccnt;
- }
+ }
for (i = 0; i < numenabled; i++)
- {
+ {
/*
- * Now enable the transfer as many times as calculated above.
- */
+ * Now enable the transfer as many times as calculated above.
+ */
result = EDMA3_DRV_enableTransfer (hEdma, chId,
- EDMA3_DRV_TRIG_MODE_MANUAL);
+ EDMA3_DRV_TRIG_MODE_MANUAL);
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_enableTransfer " \
- "Failed, error code: %d\r\n", result);
+ "Failed, error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
break;
- }
+ }
/* Wait for the Completion Bit to be SET in the IPR/IPRH register. */
result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc);
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF ("edma3_test_poll_mode: EDMA3_DRV_waitAndClearTcc " \
- "Failed, error code: %d\r\n", result);
+ "Failed, error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
break;
- }
}
}
+ }
/* Match the Source and Destination Buffers. */
if (EDMA3_DRV_SOK == result)
- {
+ {
for (i = 0; i < (acnt*bcnt*ccnt); i++)
- {
+ {
if (srcBuff1[i] != dstBuff1[i])
- {
+ {
Istestpassed = 0u;
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_poll_mode: Data write-read matching" \
- "FAILED at i = %d\r\n", i);
+ "FAILED at i = %d\r\n", i);
#endif /* EDMA3_DRV_DEBUG */
break;
- }
}
+ }
if (i == (acnt*bcnt*ccnt))
- {
+ {
Istestpassed = 1u;
- }
+ }
/* Free the previously allocated channel. */
result = EDMA3_DRV_freeChannel (hEdma, chId);
if (result != EDMA3_DRV_SOK)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_poll_mode: EDMA3_DRV_freeChannel() FAILED, " \
- "error code: %d\r\n", result);
+ "error code: %d\r\n", result);
#endif /* EDMA3_DRV_DEBUG */
- }
}
+ }
if(Istestpassed == 1u)
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_poll_mode PASSED\r\n");
#endif /* EDMA3_DRV_DEBUG */
- }
+ }
else
- {
+ {
#ifdef EDMA3_DRV_DEBUG
EDMA3_DRV_PRINTF("edma3_test_poll_mode FAILED\r\n");
#endif /* EDMA3_DRV_DEBUG */
result = ((EDMA3_DRV_SOK == result) ?
- EDMA3_DATA_MISMATCH_ERROR : result);
- }
-
-
+ EDMA3_DATA_MISMATCH_ERROR : result);
+ }
return result;
}
index d68ce31f249a6c13c3b0b98a73346b4052a3e9ba..c46c45d12a089cd3f5be5d3fd42374b5a3475c69 100755 (executable)
/*
- * dma_test.c
- *
- * EDMA3 mem-to-mem data copy test case, using a DMA channel.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* dma_test.c
+*
+* EDMA3 mem-to-mem data copy test case, using a DMA channel.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#include "sample.h"
/**
- * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
- *
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
+* \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
+*
+*
+* \param acnt [IN] Number of bytes in an array
+* \param bcnt [IN] Number of arrays in a frame
+* \param ccnt [IN] Number of frames in a block
+* \param syncType [IN] Synchronization type (A/AB Sync)
+*
+* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
EDMA3_DRV_Result edma3_test(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType)
- {
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType)
+{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};
uint32_t chId = 0;
/* Initalize source and destination buffers */
for (count = 0u; count < (acnt*bcnt*ccnt); count++)
- {
+ {
srcBuff1[count] = (int)count;
/**
- * No need to initialize the destination buffer as it is being invalidated.
+ * No need to initialize the destination buffer as it is being invalidated.
dstBuff1[count] = initval;
*/
- }
+ }
#ifdef EDMA3_ENABLE_DCACHE
*/
/* Flush the Source Buffer */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
- }
+ }
/* Invalidate the Destination Buffer */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
- }
+ }
#endif /* EDMA3_ENABLE_DCACHE */
srcbidx = (int)acnt;
desbidx = (int)acnt;
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
/* A Sync Transfer Mode */
srccidx = (int)acnt;
descidx = (int)acnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
srccidx = ((int)acnt * (int)bcnt);
descidx = ((int)acnt * (int)bcnt);
- }
+ }
/* Setup for Channel 1*/
/* Request any DMA channel and any TCC */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,
- (EDMA3_RM_EventQueue)0,
- &callback1, NULL);
- }
+ (EDMA3_RM_EventQueue)0,
+ &callback1, NULL);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Fill the PaRAM Set with transfer specific information */
paramSet.srcAddr = (uint32_t)(srcBuff1);
paramSet.destAddr = (uint32_t)(dstBuff1);
/**
- * Be Careful !!!
- * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767
- * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767
- */
+ * Be Careful !!!
+ * Valid values for SRCBIDX/DSTBIDX are between \9632768 and 32767
+ * Valid values for SRCCIDX/DSTCIDX are between \9632768 and 32767
+ */
paramSet.srcBIdx = srcbidx;
paramSet.destBIdx = desbidx;
paramSet.srcCIdx = srccidx;
paramSet.destCIdx = descidx;
/**
- * Be Careful !!!
- * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
- * ACNT/BCNT/CCNT must be greater than or equal to 1.
- * Maximum number of bytes in an array (ACNT) is 65535 bytes
- * Maximum number of arrays in a frame (BCNT) is 65535
- * Maximum number of frames in a block (CCNT) is 65535
- */
+ * Be Careful !!!
+ * Valid values for ACNT/BCNT/CCNT are between 0 and 65535.
+ * ACNT/BCNT/CCNT must be greater than or equal to 1.
+ * Maximum number of bytes in an array (ACNT) is 65535 bytes
+ * Maximum number of arrays in a frame (BCNT) is 65535
+ * Maximum number of frames in a block (CCNT) is 65535
+ */
paramSet.aCnt = acnt;
paramSet.bCnt = bcnt;
paramSet.cCnt = ccnt;
paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
paramSet.opt &= 0xFFFFFFFBu;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);
- }
+ }
/* Now, write the PaRAM Set. */
result = EDMA3_DRV_setPaRAM(hEdma, chId, ¶mSet);
- }
+ }
/*
- * There is another way to program the PaRAM Set using specific APIs
- * for different PaRAM set entries. It gives user more control and easier
- * to use interface. User can use any of the methods.
- * Below is the alternative way to program the PaRAM Set.
- */
+ * There is another way to program the PaRAM Set using specific APIs
+ * for different PaRAM set entries. It gives user more control and easier
+ * to use interface. User can use any of the methods.
+ * Below is the alternative way to program the PaRAM Set.
+ */
/*
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setSrcParams (hEdma, chId, (uint32_t)(srcBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ {
+ result = EDMA3_DRV_setSrcParams (hEdma, chId, (uint32_t)(srcBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setDestParams (hEdma, chId, (uint32_t)(dstBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ {
+ result = EDMA3_DRV_setDestParams (hEdma, chId, (uint32_t)(dstBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
- }
+ {
+ result = EDMA3_DRV_setSrcIndex (hEdma, chId, srcbidx, srccidx);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
- }
+ {
+ result = EDMA3_DRV_setDestIndex (hEdma, chId, desbidx, descidx);
+ }
if (result == EDMA3_DRV_SOK)
- {
- if (syncType == EDMA3_DRV_SYNC_A)
- {
- result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
- BRCnt, EDMA3_DRV_SYNC_A);
- }
- else
- {
- result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
- BRCnt, EDMA3_DRV_SYNC_AB);
- }
- }
+ {
+ if (syncType == EDMA3_DRV_SYNC_A)
+ {
+ result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
+ BRCnt, EDMA3_DRV_SYNC_A);
+ }
+ else
+ {
+ result = EDMA3_DRV_setTransferParams (hEdma, chId, acnt, bcnt, ccnt,
+ BRCnt, EDMA3_DRV_SYNC_AB);
+ }
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setOptField (hEdma, chId,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
- }
+ {
+ result = EDMA3_DRV_setOptField (hEdma, chId,
+ EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
- result = EDMA3_DRV_setOptField (hEdma, chId,
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
- }
+ {
+ result = EDMA3_DRV_setOptField (hEdma, chId,
+ EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+ }
*/
/*
- * Since the transfer is going to happen in Manual mode of EDMA3
- * operation, we have to 'Enable the Transfer' multiple times.
- * Number of times depends upon the Mode (A/AB Sync)
- * and the different counts.
- */
+ * Since the transfer is going to happen in Manual mode of EDMA3
+ * operation, we have to 'Enable the Transfer' multiple times.
+ * Number of times depends upon the Mode (A/AB Sync)
+ * and the different counts.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
/*Need to activate next param*/
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
numenabled = bcnt * ccnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
numenabled = ccnt;
- }
+ }
for (i = 0; i < numenabled; i++)
- {
+ {
irqRaised1 = 0;
/*
- * Now enable the transfer as many times as calculated above.
- */
+ * Now enable the transfer as many times as calculated above.
+ */
result = EDMA3_DRV_enableTransfer (hEdma, chId,
- EDMA3_DRV_TRIG_MODE_MANUAL);
+ EDMA3_DRV_TRIG_MODE_MANUAL);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf ("edma3_test: EDMA3_DRV_enableTransfer " \
- "Failed, error code: %d\r\n", (int)result);
+ "Failed, error code: %d\r\n", (int)result);
break;
- }
- edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
+ }
+ edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
/* Wait for the Completion ISR. */
while (irqRaised1 == 0u)
- {
+ {
/* Wait for the Completion ISR. */
- printf ("waiting for interrupt...\n");
- }
+ printf ("waiting for interrupt...\n");
+ }
/* Check the status of the completed transfer */
if (irqRaised1 < 0)
- {
+ {
/* Some error occured, break from the FOR loop. */
printf ("\r\nedma3_test: Event Miss Occured!!!\r\n");
/* Clear the error bits first */
result = EDMA3_DRV_clearErrorBits (hEdma, chId);
break;
- }
}
}
+ }
/* Match the Source and Destination Buffers. */
if (EDMA3_DRV_SOK == result)
- {
+ {
for (i = 0; i < (acnt*bcnt*ccnt); i++)
- {
+ {
if (srcBuff1[i] != dstBuff1[i])
- {
+ {
Istestpassed = 0u;
printf("edma3_test: Data write-read matching" \
- "FAILED at i = %d\r\n", i);
+ "FAILED at i = %d\r\n", i);
break;
- }
}
+ }
if (i == (acnt*bcnt*ccnt))
- {
+ {
Istestpassed = 1u;
- }
+ }
/* Free the previously allocated channel. */
result = EDMA3_DRV_freeChannel (hEdma, chId);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf("edma3_test: EDMA3_DRV_freeChannel() FAILED, " \
- "error code: %d\r\n", (int)result);
- }
+ "error code: %d\r\n", (int)result);
}
+ }
if(Istestpassed == 1u)
- {
+ {
printf("edma3_test PASSED\r\n");
- }
+ }
else
- {
+ {
printf("edma3_test FAILED\r\n");
result = ((EDMA3_DRV_SOK == result) ?
- EDMA3_DATA_MISMATCH_ERROR : result);
- }
-
-
+ EDMA3_DATA_MISMATCH_ERROR : result);
+ }
return result;
}
-
-
index 0f508b8b04819c7f37f395471983690be8276b0f..e658fd3b741e369805a85a4f928ed8020a58bd0b 100644 (file)
/*
- * main.c
- *
- * This file contains the test / demo code to demonstrate the EDMA3 driver
- * functionality on DSP/BIOS 6.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* main.c
+*
+* This file contains the test / demo code to demonstrate the EDMA3 driver
+* functionality on DSP/BIOS 6.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#include <xdc/std.h>
extern const uint32_t numEdma3Instances;
/**
- * DSP instance number on which the executable is running. Its value is
- * determined by reading the processor specific register DNUM.
- */
+* DSP instance number on which the executable is running. Its value is
+* determined by reading the processor specific register DNUM.
+*/
uint32_t dsp_num_tmp;
/* To find out the DSP# */
extern unsigned short determineProcId();
extern void *AppSemHandle2;
/*
- * Local References
- */
+* Local References
+*/
static void tskHeartBit(void);
void echo(void);
Task_create((Task_FuncPtr)echo, NULL, NULL);
BIOS_start();
-
- return 0;
+
+ return 0;
}
static void printWelcomeBanner(void)
- {
+{
/* Welcome Message */
printf("***************************************************************\n\r");
printf("* *\n\r");
printf("* *\n\r");
printf("***************************************************************\n\r");
printf("\r\n\r\n");
- }
+}
/**
- * \brief This function determines if testing on a EDMA3 instance will be bypassed.
- * When there are no EDMA channels allocated for the core from the given EDMA3
- * instance, testing shall be bypassed.
- *
- * \return TRUE if bypass; FALSE if testing will done.
- */
+* \brief This function determines if testing on a EDMA3 instance will be bypassed.
+* When there are no EDMA channels allocated for the core from the given EDMA3
+* instance, testing shall be bypassed.
+*
+* \return TRUE if bypass; FALSE if testing will done.
+*/
uint32_t bypassCore(uint32_t edmaInstNum)
{
- uint32_t i, bypassFlag = 1;
+ uint32_t i, bypassFlag = 1;
#ifndef EDMA3_DRV_USE_DEF_RM_CFG
EDMA3_DRV_InstanceInitConfig *instanceConfig = NULL;
dsp_num_tmp = determineProcId();
#ifndef EDMA3_DRV_USE_DEF_RM_CFG
- /* configuration structure for the Driver */
- instanceConfig = &sampleInstInitConfig[edmaInstNum][dsp_num_tmp];
- for (i = 0; i < EDMA3_MAX_DMA_CHAN_DWRDS; i++)
- {
- if(instanceConfig->ownDmaChannels[i])
- bypassFlag = 0;
- }
+ /* configuration structure for the Driver */
+ instanceConfig = &sampleInstInitConfig[edmaInstNum][dsp_num_tmp];
+ for (i = 0; i < EDMA3_MAX_DMA_CHAN_DWRDS; i++)
+ {
+ if(instanceConfig->ownDmaChannels[i])
+ bypassFlag = 0;
+ }
#else
/* configuration structure for the Driver */
- rmInstInitCfg = &defInstInitConfig[edmaInstNum][dsp_num_tmp];
- for (i = 0; i < EDMA3_MAX_DMA_CHAN_DWRDS; i++)
- {
- if(rmInstInitCfg->ownDmaChannels[i])
- bypassFlag = 0;
- }
+ rmInstInitCfg = &defInstInitConfig[edmaInstNum][dsp_num_tmp];
+ for (i = 0; i < EDMA3_MAX_DMA_CHAN_DWRDS; i++)
+ {
+ if(rmInstInitCfg->ownDmaChannels[i])
+ bypassFlag = 0;
+ }
#endif
- return (bypassFlag);
+ return (bypassFlag);
}
void echo()
- {
+{
EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;
- uint32_t i, bypass;
- uint32_t count=0;
- EDMA3_DRV_Handle hEdma[MAX_NUM_EDMA_INSTANCES];
- Semaphore_Params semParams;
+ uint32_t i, bypass;
+ uint32_t count=0;
+ EDMA3_DRV_Handle hEdma[MAX_NUM_EDMA_INSTANCES];
+ Semaphore_Params semParams;
memset(hEdma,0,sizeof(hEdma));
/* Print the Welcome Message */
printWelcomeBanner();
-
- Semaphore_Params_init(&semParams);
- edmaResult = edma3OsSemCreate(0, &semParams, &AppSemHandle1);
- if((edmaResult != EDMA3_DRV_SOK) || (AppSemHandle1 == NULL))
- {
- printf("Error initializing the Application Semaphore handle\n");
- return;
- }
- edmaResult = edma3OsSemCreate(0, &semParams, &AppSemHandle2);
- if((edmaResult != EDMA3_DRV_SOK) || (AppSemHandle2 == NULL))
- {
- printf("Error initializing the Application Semaphore handle\n");
- return;
- }
+
+ Semaphore_Params_init(&semParams);
+ edmaResult = edma3OsSemCreate(0, &semParams, &AppSemHandle1);
+ if((edmaResult != EDMA3_DRV_SOK) || (AppSemHandle1 == NULL))
+ {
+ printf("Error initializing the Application Semaphore handle\n");
+ return;
+ }
+ edmaResult = edma3OsSemCreate(0, &semParams, &AppSemHandle2);
+ if((edmaResult != EDMA3_DRV_SOK) || (AppSemHandle2 == NULL))
+ {
+ printf("Error initializing the Application Semaphore handle\n");
+ return;
+ }
if(numEdma3Instances > MAX_NUM_EDMA_INSTANCES)
{
printf("Error numEdma3Instances:%d > MAX_NUM_EDMA_INSTANCES: %d\n", (int)numEdma3Instances, MAX_NUM_EDMA_INSTANCES);
return;
}
-
+
for (i = 0; i < numEdma3Instances; i++)
{
- bypass = bypassCore(i);
+ bypass = bypassCore(i);
if(sampleEdma3GblCfgParams[i].numRegions > 1)
{
/* For multi core test init and de-init only once per test
- * for a core.
- */
+ * for a core.
+ */
if(bypass)
- {
- printf("Bypassing init for Core %d on EDMA3 instance %d\n", (int)dsp_num_tmp, (int)i);
+ {
+ printf("Bypassing init for Core %d on EDMA3 instance %d\n", (int)dsp_num_tmp, (int)i);
continue;
- }
+ }
hEdma[i] = edma3init(i, &edmaResult);
- if (hEdma[i])
- {
- printf("edma3init() Passed\n");
- }
- else
- {
- printf("edma3init() Failed, error code: %d\n", (int)edmaResult);
- }
+ if (hEdma[i])
+ {
+ printf("edma3init() Passed\n");
+ }
+ else
+ {
+ printf("edma3init() Failed, error code: %d\n", (int)edmaResult);
+ }
}
}
-
- for (count=0; count<10; count++)
- {
- printf ("\nCount = %d\n",(int)count);
- for (i = 0; i < numEdma3Instances; i++)
- {
+ for (count=0; count<10; count++)
+ {
+ printf ("\nCount = %d\n",(int)count);
+ for (i = 0; i < numEdma3Instances; i++)
+ {
bypass = bypassCore(i);
- if(bypass)
- {
- printf("Bypass Core %d on EDMA3 instance %d\n", (int)dsp_num_tmp, (int)i);
- }
- else
- {
+ if(bypass)
+ {
+ printf("Bypass Core %d on EDMA3 instance %d\n", (int)dsp_num_tmp, (int)i);
+ }
+ else
+ {
if(sampleEdma3GblCfgParams[i].numRegions == 1)
{
/* Single Region Config Do Init and Deinit test for each iteration */
hEdma[i] = edma3init(i, &edmaResult);
- if (hEdma[i])
- {
- printf("edma3init() Passed\n");
- }
- else
- {
- printf("edma3init() Failed, error code: %d\n", (int)edmaResult);
- }
+ if (hEdma[i])
+ {
+ printf("edma3init() Passed\n");
+ }
+ else
+ {
+ printf("edma3init() Failed, error code: %d\n", (int)edmaResult);
+ }
}
- if (edmaResult == EDMA3_DRV_SOK)
- {
- printf("\nStart -> EDMA3 Test memory to memory copy on Instance %d\n",(int)i);
+ if (edmaResult == EDMA3_DRV_SOK)
+ {
+ printf("\nStart -> EDMA3 Test memory to memory copy on Instance %d\n",(int)i);
- edmaResult = edma3MemToMemCpytest(hEdma[i]);
+ edmaResult = edma3MemToMemCpytest(hEdma[i]);
- if (EDMA3_DRV_SOK != edmaResult)
- {
- /* Report EDMA Error */
- printf("edma3MemToMemCpytest() FAILED!!!!!!!!!!!!!!!!\n");
- return;
- }
- else
- {
- printf("edma3MemToMemCpytest() Passed\n");
- }
+ if (EDMA3_DRV_SOK != edmaResult)
+ {
+ /* Report EDMA Error */
+ printf("edma3MemToMemCpytest() FAILED!!!!!!!!!!!!!!!!\n");
+ return;
+ }
+ else
+ {
+ printf("edma3MemToMemCpytest() Passed\n");
+ }
- printf("\nEnd -> EDMA3 Test memory to memory copy\n\n");
- }
+ printf("\nEnd -> EDMA3 Test memory to memory copy\n\n");
+ }
if(sampleEdma3GblCfgParams[i].numRegions == 1)
{
/* Single Region Config Do deinit */
/* De-init EDMA3 */
- if (hEdma[i])
- {
- edmaResult = edma3deinit(i, hEdma[i]);
- if (edmaResult != EDMA3_DRV_SOK)
- {
- printf("edma3deinit() Failed, error code: %d\n", (int)edmaResult);
- }
- else
- {
- printf("edma3deinit() Passed\n");
- }
+ if (hEdma[i])
+ {
+ edmaResult = edma3deinit(i, hEdma[i]);
+ if (edmaResult != EDMA3_DRV_SOK)
+ {
+ printf("edma3deinit() Failed, error code: %d\n", (int)edmaResult);
+ }
+ else
+ {
+ printf("edma3deinit() Passed\n");
+ }
}
}
- }
-
- }
- }
-
- /* Start the Heart Beat Print */
- tskHeartBit();
+ }
+ }
+ }
for (i = 0; i < numEdma3Instances; i++)
- {
+ {
if(sampleEdma3GblCfgParams[i].numRegions > 1)
{
- if(bypass)
- {
- printf("Bypassing de-init for Core %d on EDMA3 instance %d\n", (int)dsp_num_tmp, (int)i);
- continue;
- }
-
/* Multi core Do deinit */
/* De-init EDMA3 */
- if (hEdma[i])
- {
- edmaResult = edma3deinit(i, hEdma[i]);
- if (edmaResult != EDMA3_DRV_SOK)
- {
- printf("edma3deinit() Failed, error code: %d\n", (int)edmaResult);
- }
- else
- {
- printf("edma3deinit() Passed\n");
- }
+ if (hEdma[i])
+ {
+ edmaResult = edma3deinit(i, hEdma[i]);
+ if (edmaResult != EDMA3_DRV_SOK)
+ {
+ printf("edma3deinit() Failed, error code: %d\n", (int)edmaResult);
+ }
+ else
+ {
+ printf("edma3deinit() Passed\n");
+ }
}
}
}
+ /* Start the Heart Beat Print */
+ tskHeartBit();
+
return;
- }
+}
/**
- * \brief Main sample test case which will call other EDMA3 test cases.
- * If one wants to call Edma3 test cases, include this main
- * test case only.
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
+* \brief Main sample test case which will call other EDMA3 test cases.
+* If one wants to call Edma3 test cases, include this main
+* test case only.
+*
+* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
EDMA3_DRV_Result edma3MemToMemCpytest (EDMA3_DRV_Handle hEdma)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
if (hEdma == NULL)
- {
+ {
//result = EDMA3_DRV_E_INVALID_PARAM;
- return result;
- }
+ return result;
+ }
/* Edma test without linking, async, incr mode */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = edma3_test(hEdma, MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
- if (result == EDMA3_DRV_SOK)
- {
- printf ("edma3_test (without linking) Passed\r\n");
- }
- else
- {
- printf ("edma3_test (without linking) Failed\r\n");
- }
- }
-
- /* Edma test with linking, async, incr mode */
- if (result == EDMA3_DRV_SOK)
+ if (result == EDMA3_DRV_SOK)
{
- result = edma3_test_with_link(hEdma, MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
+ printf ("edma3_test (without linking) Passed\r\n");
+ }
+ else
+ {
+ printf ("edma3_test (without linking) Failed\r\n");
+ }
+ }
- if (result == EDMA3_DRV_SOK)
- {
- printf ("edma3_test_with_link Passed\r\n");
- }
- else
- {
- printf ("edma3_test_with_link Failed\r\n");
- }
- }
-
- /* Qdma test, async, incr mode */
+ /* Edma test with linking, async, incr mode */
if (result == EDMA3_DRV_SOK)
+ {
+ result = edma3_test_with_link(hEdma, MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
+
+ if (result == EDMA3_DRV_SOK)
{
- result = qdma_test(hEdma, MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
+ printf ("edma3_test_with_link Passed\r\n");
+ }
+ else
+ {
+ printf ("edma3_test_with_link Failed\r\n");
+ }
+ }
- if (result == EDMA3_DRV_SOK)
- {
- printf ("qdma_test Passed\r\n");
- }
- else
- {
- printf ("qdma_test Failed\r\n");
- }
- }
-
- /* Qdma test with linking, async, incr mode */
+ /* Qdma test, async, incr mode */
if (result == EDMA3_DRV_SOK)
+ {
+ result = qdma_test(hEdma, MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
+
+ if (result == EDMA3_DRV_SOK)
{
- result = qdma_test_with_link (hEdma, MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
+ printf ("qdma_test Passed\r\n");
+ }
+ else
+ {
+ printf ("qdma_test Failed\r\n");
+ }
+ }
- if (result == EDMA3_DRV_SOK)
- {
- printf ("qdma_test_with_link Passed\r\n");
- }
- else
- {
- printf ("qdma_test_with_link Failed\r\n");
- }
- }
-
- /* DMA channels with chaining test. */
+ /* Qdma test with linking, async, incr mode */
if (result == EDMA3_DRV_SOK)
+ {
+ result = qdma_test_with_link (hEdma, MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
+
+ if (result == EDMA3_DRV_SOK)
+ {
+ printf ("qdma_test_with_link Passed\r\n");
+ }
+ else
{
+ printf ("qdma_test_with_link Failed\r\n");
+ }
+ }
+
+ /* DMA channels with chaining test. */
+ if (result == EDMA3_DRV_SOK)
+ {
result = edma3_test_with_chaining(hEdma, MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
if (result == EDMA3_DRV_SOK)
- {
+ {
printf ("edma3_test_with_chaining Passed\r\n");
- }
+ }
else
- {
+ {
printf ("edma3_test_with_chaining Failed\r\n");
- }
}
+ }
- /* DMA channels using Polling mode test. */
+ /* DMA channels using Polling mode test. */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = edma3_test_poll_mode(hEdma, MAX_ACOUNT, MAX_BCOUNT, MAX_CCOUNT, EDMA3_DRV_SYNC_A);
if (result == EDMA3_DRV_SOK)
- {
+ {
printf ("edma3_test_poll_mode Passed\r\n");
- }
+ }
else
- {
+ {
printf ("edma3_test_poll_mode Failed\r\n");
- }
}
+ }
- /* DMA channels in using ping-pong buffers test. */
+ /* DMA channels in using ping-pong buffers test. */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = edma3_test_ping_pong_mode(hEdma);
if (result == EDMA3_DRV_SOK)
- {
+ {
printf ("edma3_test_ping_pong_mode Passed\r\n");
- }
+ }
else
- {
+ {
printf ("edma3_test_ping_pong_mode Failed\r\n");
- }
}
+ }
- /* Misc tests. */
+ /* Misc tests. */
if (result == EDMA3_DRV_SOK)
- {
- result = edma3_misc_test(hEdma);
+ {
+ result = edma3_misc_test(hEdma);
if (result == EDMA3_DRV_SOK)
- {
+ {
printf ("edma3_misc_test Passed\r\n");
- }
+ }
else
- {
+ {
printf ("edma3_misc_test Failed\r\n");
- }
}
+ }
return result;
}
void tskHeartBit()
- {
+{
static uint32_t counter = 0u;
while (counter < 0x1000000u)
- {
+ {
printf("\r\n\r\n!!! EDMA3 LLD HrtBt %x", (unsigned int)counter);
counter++;
- }
}
+}
diff --git a/examples/edma3_driver/src/qdma_link_test.c b/examples/edma3_driver/src/qdma_link_test.c
index 0ca5753157c5c0ab4db41ea22d6909f6925e2ea6..5f6c062810ab86fbb549bce7c51c7bd2fd3eb19a 100755 (executable)
/*
- * qdma_link_test.c
- *
- * Test case demonstrating the usgae of QDMA channel for transferring data
- * between two memory locations. QDMA channel is linked to a LINK channel.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* qdma_link_test.c
+*
+* Test case demonstrating the usgae of QDMA channel for transferring data
+* between two memory locations. QDMA channel is linked to a LINK channel.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#include "sample.h"
extern signed char *dstBuff2;
extern void *AppSemHandle1;
/**
- * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel,
- * linked to another LINK channel.
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
+* \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel,
+* linked to another LINK channel.
+*
+* \param acnt [IN] Number of bytes in an array
+* \param bcnt [IN] Number of arrays in a frame
+* \param ccnt [IN] Number of frames in a block
+* \param syncType [IN] Synchronization type (A/AB Sync)
+*
+* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
EDMA3_DRV_Result qdma_test_with_link(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType)
- {
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType)
+{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
uint32_t i;
uint32_t count;
/* Initalize source and destination buffers */
for (count= 0u; count < (acnt*bcnt*ccnt); count++)
- {
+ {
srcBuff1[count] = (int)count+3;
srcBuff2[count] = (int)count+3;
/**
- * No need to initialize the destination buffer as it is being invalidated.
+ * No need to initialize the destination buffer as it is being invalidated.
dstBuff1[count] = initval;
dstBuff2[count] = initval;
*/
- }
+ }
#ifdef EDMA3_ENABLE_DCACHE
*/
/* Flush the Source Buffers */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheFlush((uint32_t)srcBuff2, (acnt*bcnt*ccnt));
- }
+ }
/* Invalidate the Destination Buffers */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstBuff2, (acnt*bcnt*ccnt));
- }
+ }
#endif /* EDMA3_ENABLE_DCACHE */
desbidx = (int)acnt;
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
/* A Sync Transfer Mode */
srccidx = (int)acnt;
descidx = (int)acnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
srccidx = ((int)acnt * (int)bcnt);
descidx = ((int)acnt * (int)bcnt);
- }
+ }
/* Setup for any QDMA Channel */
qTcc1 = EDMA3_DRV_TCC_ANY;
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
- (EDMA3_RM_EventQueue)0,
- &callback1, NULL);
- }
+ (EDMA3_RM_EventQueue)0,
+ &callback1, NULL);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Setup for Channel 2 (Link Channel) */
qCh2Id = EDMA3_DRV_LINK_CHANNEL;
qTcc2 = EDMA3_DRV_TCC_ANY;
result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2,
- (EDMA3_RM_EventQueue)0,
- &callback1, NULL);
- }
+ (EDMA3_RM_EventQueue)0,
+ &callback1, NULL);
+ }
/* Configure the Link Channel first */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id,
- (uint32_t)(srcBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ (uint32_t)(srcBuff2),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setDestParams (hEdma, qCh2Id,
- (uint32_t)(dstBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
- }
+ (uint32_t)(dstBuff2),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt,
- ccnt, BRCnt,
- EDMA3_DRV_SYNC_A);
- }
+ ccnt, BRCnt,
+ EDMA3_DRV_SYNC_A);
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt,
- ccnt, BRCnt,
- EDMA3_DRV_SYNC_AB);
- }
+ ccnt, BRCnt,
+ EDMA3_DRV_SYNC_AB);
}
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Enable the Transfer Completion Interrupt on Link Channel */
result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/**
- * Enable the Intermediate Transfer Completion Interrupt on Link
- * Channel.
- */
+ * Enable the Intermediate Transfer Completion Interrupt on Link
+ * Channel.
+ */
result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Link both the channels. */
result = EDMA3_DRV_linkChannel (hEdma, qCh1Id, qCh2Id);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/**
- * Now configure the QDMA channel. Here lies the trick. Since QDMA
- * channel is linked to another DMA channel, as soon as transfer on
- * QDMA channel is finished, static field being NOT SET, the associated
- * PaRAM Set will be reloaded with the Linked PaRAM Set. Now, as the
- * reload occurs, the QDMA channel will be triggered due to the write
- * on a specific Trigger Word. We want the trigger to happen immediately
- * after the write, so the trigger word should be chosen in such a way
- * that it should trigger after the COMPLETE PaRAM Set will get copied
- * onto the QDMA Channel PaRAM Set. In that case, only ONE option is
- * there to choose the CCNT as the trigger word. All other trigger
- * words will cause the trigger happen in-between the PaRAM Set is
- * loading. So Set the trigger word as CCNT.
- */
+ * Now configure the QDMA channel. Here lies the trick. Since QDMA
+ * channel is linked to another DMA channel, as soon as transfer on
+ * QDMA channel is finished, static field being NOT SET, the associated
+ * PaRAM Set will be reloaded with the Linked PaRAM Set. Now, as the
+ * reload occurs, the QDMA channel will be triggered due to the write
+ * on a specific Trigger Word. We want the trigger to happen immediately
+ * after the write, so the trigger word should be chosen in such a way
+ * that it should trigger after the COMPLETE PaRAM Set will get copied
+ * onto the QDMA Channel PaRAM Set. In that case, only ONE option is
+ * there to choose the CCNT as the trigger word. All other trigger
+ * words will cause the trigger happen in-between the PaRAM Set is
+ * loading. So Set the trigger word as CCNT.
+ */
result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
- EDMA3_RM_QDMA_TRIG_CCNT);
- }
+ EDMA3_RM_QDMA_TRIG_CCNT);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
- }
+ }
abCNT = acnt | ((bcnt & 0xFFFFu) << 16u);
/* Write ACNT and BCNT */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id,
- EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT,
- abCNT);
- }
+ EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT,
+ abCNT);
+ }
/* Set the SYNC Mode (A/AB Sync) */
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_SYNCDIM, 0u);
- }
+ EDMA3_DRV_OPT_FIELD_SYNCDIM, 0u);
+ }
else
- {
+ {
result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_SYNCDIM, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_SYNCDIM, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Enable Transfer Completion Interrupt */
result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Enable Intermediate Transfer Completion Interrupt */
result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Set Source Transfer Mode as Increment Mode. */
result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM,
- EDMA3_DRV_ADDR_MODE_INCR);
- }
+ EDMA3_DRV_ADDR_MODE_INCR);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Set Destination Transfer Mode as Increment Mode. */
result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM,
- EDMA3_DRV_ADDR_MODE_INCR);
- }
+ EDMA3_DRV_ADDR_MODE_INCR);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Get Link Address. */
result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id,
- EDMA3_DRV_PARAM_FIELD_LINKADDR,
- &bcntReloadLinkField);
- }
+ EDMA3_DRV_PARAM_FIELD_LINKADDR,
+ &bcntReloadLinkField);
+ }
bcntReloadLinkField = (bcntReloadLinkField | (BRCnt << 16));
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Set B Count Reload & Link Address. */
result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id,
- EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD,
- bcntReloadLinkField);
- }
+ EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD,
+ bcntReloadLinkField);
+ }
/*Need to activate next param*/
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
numenabled = bcnt * ccnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
numenabled = ccnt;
- }
+ }
if (numenabled == 1u)
- {
+ {
/**
- * If only one Sync event is required, make the PaRAM Set associated
- * with the LINK channel as Static.
- */
+ * If only one Sync event is required, make the PaRAM Set associated
+ * with the LINK channel as Static.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
- EDMA3_DRV_OPT_FIELD_STATIC, 1u);
- }
-
- /**
- * Be Careful!!!
- * PaRAM Set associated with the Master Channel should NOT be
- * set as Static, otherwise the reload will not occur.
- */
+ EDMA3_DRV_OPT_FIELD_STATIC, 1u);
}
+ /**
+ * Be Careful!!!
+ * PaRAM Set associated with the Master Channel should NOT be
+ * set as Static, otherwise the reload will not occur.
+ */
+ }
+
/*
- * Since the transfer is going to happen in QDMA mode of EDMA3
- * operation, we have to "Trigger" the transfer multiple times.
- * Number of times depends upon the Mode (A/AB Sync)
- * and the different counts.
- */
+ * Since the transfer is going to happen in QDMA mode of EDMA3
+ * operation, we have to "Trigger" the transfer multiple times.
+ * Number of times depends upon the Mode (A/AB Sync)
+ * and the different counts.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
for (i = 0u; i < numenabled; i++)
- {
+ {
irqRaised1 = 0u;
/* Write to the Source Address */
result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
- (uint32_t)(srcBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
+ (uint32_t)(srcBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf ("error from qdma_test_with_link\r\n\r\n");
return result;
- }
+ }
/* Write to the Destination Address */
result = EDMA3_DRV_setDestParams(hEdma, qCh1Id,
- (uint32_t)(dstBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
+ (uint32_t)(dstBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf ("error from qdma_test_with_link\r\n\r\n");
return result;
- }
+ }
/* Now write to the Trigger Word i.e. CCNT. */
result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_CCNT, ccnt);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf ("error from qdma_test_with_link\r\n\r\n");
return result;
- }
+ }
/* After this, transfer will start. */
/**
- * Now, update the source and destination addresses for next
- * "Trigger".
- */
+ * Now, update the source and destination addresses for next
+ * "Trigger".
+ */
srcBuff1 += srccidx;
dstBuff1 += descidx;
/**
- * Read the current C Count from the PaRAM Set and write it back.
- * In this way, we would write the correct CCNT every time and
- * trigger the transfer also. Since CC will decrement the CCNT
- * after every (ACNT * BCNT) bytes of data transfer, we can use
- * that decremented value to trigger the next transfer.
- * Another option is to take count of CCNT manually (in your code)
- * and write that value.
- * First option seems less error prone.
- */
+ * Read the current C Count from the PaRAM Set and write it back.
+ * In this way, we would write the correct CCNT every time and
+ * trigger the transfer also. Since CC will decrement the CCNT
+ * after every (ACNT * BCNT) bytes of data transfer, we can use
+ * that decremented value to trigger the next transfer.
+ * Another option is to take count of CCNT manually (in your code)
+ * and write that value.
+ * First option seems less error prone.
+ */
result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id, EDMA3_DRV_PARAM_FIELD_CCNT, &ccnt);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf ("error from qdma_test_with_link\r\n\r\n");
return result;
- }
}
}
+ }
/**
- * Transfer on the QDMA channel has finished and Link
- * PaRAM Set is loaded on the QDMA channel PaRAM Set.
- * Now for the transfers on the LINK channel,
- * if only one "TRIGGER" is required,
- * that has already been provided by the PaRAM Set
- * upload.
- * For other triggers, we will take care.
- */
+ * Transfer on the QDMA channel has finished and Link
+ * PaRAM Set is loaded on the QDMA channel PaRAM Set.
+ * Now for the transfers on the LINK channel,
+ * if only one "TRIGGER" is required,
+ * that has already been provided by the PaRAM Set
+ * upload.
+ * For other triggers, we will take care.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
/**
- * One trigger has been provided already, so first wait for
- * that transfer to complete.
- */
- edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
+ * One trigger has been provided already, so first wait for
+ * that transfer to complete.
+ */
+ edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
while (irqRaised1 == 0)
- {
+ {
/* Wait for the Completion ISR for the Master QDMA Channel. */
- printf ("waiting for interrupt...\n");
- }
+ printf ("waiting for interrupt...\n");
+ }
/* Check the status of the completed transfer */
if (irqRaised1 < 0)
- {
+ {
/* Some error occured, clear the error bits. */
printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n");
/* Clear the error bits first */
result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);
- }
+ }
if (numenabled == 1u)
- {
+ {
/**
- * Only 1 trigger was required which has been provided
- * already. No need to do anything.
- */
- }
+ * Only 1 trigger was required which has been provided
+ * already. No need to do anything.
+ */
+ }
else
- {
+ {
/**
- * One trigger has been provided already, so take that into account.
- */
+ * One trigger has been provided already, so take that into account.
+ */
numenabled -= 1u;
for (i = 0u; i < numenabled; i++)
- {
+ {
irqRaised1 = 0u;
if (i == (numenabled - 1u))
- {
+ {
/**
- * Before providing the last trigger,
- * make the PaRAM Set static.
- */
+ * Before providing the last trigger,
+ * make the PaRAM Set static.
+ */
result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_STATIC, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_STATIC, 1u);
+ }
/**
- * Now, update the source and destination addresses for next
- * "Trigger".
- */
+ * Now, update the source and destination addresses for next
+ * "Trigger".
+ */
srcBuff2 += srccidx;
dstBuff2 += descidx;
/**
- * Read the current C Count from the PaRAM Set and write it back.
- * In this way, we would write the correct CCNT every time and
- * trigger the transfer also.
- */
+ * Read the current C Count from the PaRAM Set and write it back.
+ * In this way, we would write the correct CCNT every time and
+ * trigger the transfer also.
+ */
result = EDMA3_DRV_getPaRAMField(hEdma, qCh1Id, EDMA3_DRV_PARAM_FIELD_CCNT, &ccnt);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf ("error from qdma_test_with_link\r\n\r\n");
return result;
- }
+ }
/* Write to the Source Address */
result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
- (uint32_t)(srcBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
+ (uint32_t)(srcBuff2),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf ("error from qdma_test_with_link\r\n\r\n");
return result;
- }
+ }
/* Write to the Destination Address */
result = EDMA3_DRV_setDestParams(hEdma, qCh1Id,
- (uint32_t)(dstBuff2),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
+ (uint32_t)(dstBuff2),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf ("error from qdma_test_with_link\r\n\r\n");
return result;
- }
+ }
/* Now write to the Trigger Word i.e. CCNT. */
result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_CCNT, ccnt);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf ("error from qdma_test_with_link\r\n\r\n");
return result;
- }
+ }
/* After this, transfer will start. */
- edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
+ edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
while (irqRaised1 == 0)
- {
+ {
/* Wait for the Completion ISR for the Link Channel. */
- printf ("waiting for interrupt...\n");
- }
+ printf ("waiting for interrupt...\n");
+ }
/* Check the status of the completed transfer */
if (irqRaised1 < 0)
- {
+ {
/* Some error occured, break from the FOR loop. */
printf ("\r\nqdma_test_with_link: Event Miss Occured!!!\r\n");
result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);
break;
- }
}
}
}
+ }
/* Restore the src and dest buffers */
/* Match the Source and Destination Buffers. */
if (EDMA3_DRV_SOK == result)
- {
+ {
for (i = 0; i < (acnt*bcnt*ccnt); i++)
- {
+ {
if (srcBuff1[i] != dstBuff1[i])
- {
+ {
Istestpassed1 = 0;
printf("qdma_test_with_link: Data write-read " \
- "matching FAILED at i = %d " \
- "(srcBuff1 -> dstBuff1)\r\r\n", (int)i);
+ "matching FAILED at i = %d " \
+ "(srcBuff1 -> dstBuff1)\r\r\n", (int)i);
break;
- }
}
+ }
if (i == (acnt*bcnt*ccnt))
- {
+ {
Istestpassed1 = 1u;
- }
+ }
for (i = 0; i < (acnt*bcnt*ccnt); i++)
- {
+ {
if (srcBuff2[i] != dstBuff2[i])
- {
+ {
Istestpassed2 = 0;
printf("qdma_test_with_link: Data write-read " \
- "matching FAILED at i = %d " \
- "(srcBuff2 -> dstBuff2)\r\n", (int)i);
+ "matching FAILED at i = %d " \
+ "(srcBuff2 -> dstBuff2)\r\n", (int)i);
break;
- }
}
+ }
if (i == (acnt*bcnt*ccnt))
- {
+ {
Istestpassed2 = 1u;
- }
}
+ }
if (EDMA3_DRV_SOK == result)
- {
+ {
/* Free the previously allocated channels. */
result = EDMA3_DRV_freeChannel (hEdma, qCh1Id);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf("qdma_test_with_link: EDMA3_DRV_freeChannel() for qCh1Id FAILED, error code: %d\r\n", (int)result);
- }
+ }
else
- {
+ {
result = EDMA3_DRV_freeChannel (hEdma, qCh2Id);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf("qdma_test_with_link: EDMA3_DRV_freeChannel() for qCh2Id FAILED, error code: %d\r\n", (int)result);
- }
}
}
+ }
if((Istestpassed1 == 1u) && (Istestpassed2 == 1u))
- {
+ {
printf("qdma_test_with_link PASSED\r\n");
- }
+ }
else
- {
+ {
printf("qdma_test_with_link FAILED\r\n");
result = ((EDMA3_DRV_SOK == result) ?
- EDMA3_DATA_MISMATCH_ERROR : result);
- }
-
-
- return result;
+ EDMA3_DATA_MISMATCH_ERROR : result);
}
-
+ return result;
+}
index b81cc3637f60622f5b75b3e1cb7b1b6e2bb502a8..9e891647e6f3044657e8f5c1522a1454175f102d 100755 (executable)
/*
- * qdma_test.c
- *
- * EDMA3 mem-to-mem data copy test case, using a QDMA channel.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* qdma_test.c
+*
+* EDMA3 mem-to-mem data copy test case, using a QDMA channel.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#include "sample.h"
extern void *AppSemHandle1;
/**
- * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel.
- *
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
+* \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel.
+*
+*
+* \param acnt [IN] Number of bytes in an array
+* \param bcnt [IN] Number of arrays in a frame
+* \param ccnt [IN] Number of frames in a block
+* \param syncType [IN] Synchronization type (A/AB Sync)
+*
+* \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+*/
EDMA3_DRV_Result qdma_test(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType)
- {
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType)
+{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
uint32_t i;
uint32_t count;
/* Initalize source and destination buffers */
for (count = 0u; count < (acnt*bcnt*ccnt); count++)
- {
+ {
srcBuff1[count] = (int)count+2;
/**
- * No need to initialize the destination buffer as it is being invalidated.
+ * No need to initialize the destination buffer as it is being invalidated.
dstBuff1[count] = initval;
*/
- }
+ }
#ifdef EDMA3_ENABLE_DCACHE
/*
*/
/* Flush the Source Buffer */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheFlush((uint32_t)srcBuff1, (acnt*bcnt*ccnt));
- }
+ }
/* Invalidate the Destination Buffer */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = Edma3_CacheInvalidate((uint32_t)dstBuff1, (acnt*bcnt*ccnt));
- }
+ }
#endif /* EDMA3_ENABLE_DCACHE */
desbidx = (int)acnt;
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
srccidx = (int)acnt;
descidx = (int)acnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
srccidx = ((int)acnt * (int)bcnt);
descidx = ((int)acnt * (int)bcnt);
- }
+ }
/* Setup for any QDMA Channel */
qTcc1 = EDMA3_DRV_TCC_ANY;
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
- (EDMA3_RM_EventQueue)0, &callback1,
- NULL);
- }
+ (EDMA3_RM_EventQueue)0, &callback1,
+ NULL);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Set QDMA Trigger Word as Destination Address */
result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
- EDMA3_RM_QDMA_TRIG_DST);
- }
+ EDMA3_RM_QDMA_TRIG_DST);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
- }
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
- ccnt, BRCnt, EDMA3_DRV_SYNC_A);
- }
+ ccnt, BRCnt, EDMA3_DRV_SYNC_A);
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
- ccnt, BRCnt, EDMA3_DRV_SYNC_AB);
- }
+ ccnt, BRCnt, EDMA3_DRV_SYNC_AB);
}
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Enable Transfer Completion Interrupt */
result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Enable Intermediate Transfer Completion Interrupt */
result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Set Source Transfer Mode as Increment Mode. */
result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM,
- EDMA3_DRV_ADDR_MODE_INCR);
- }
+ EDMA3_DRV_ADDR_MODE_INCR);
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Set Destination Transfer Mode as Increment Mode. */
result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM,
- EDMA3_DRV_ADDR_MODE_INCR);
- }
+ EDMA3_DRV_ADDR_MODE_INCR);
+ }
/*
- * Since the transfer is going to happen in QDMA mode of EDMA3
- * operation, we have to "Trigger" the transfer multiple times.
- * Number of times depends upon the Mode (A/AB Sync)
- * and the different counts.
- */
+ * Since the transfer is going to happen in QDMA mode of EDMA3
+ * operation, we have to "Trigger" the transfer multiple times.
+ * Number of times depends upon the Mode (A/AB Sync)
+ * and the different counts.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
/*Need to activate next param*/
if (syncType == EDMA3_DRV_SYNC_A)
- {
+ {
numenabled = bcnt * ccnt;
- }
+ }
else
- {
+ {
/* AB Sync Transfer Mode */
numenabled = ccnt;
- }
+ }
for (i = 0u; i < numenabled; i++)
- {
+ {
irqRaised1 = 0u;
if (i == (numenabled-1u))
- {
+ {
/**
- * Since OPT.STATIC field should be SET for isolated QDMA
- * transfers or for the final transfer in a linked list of QDMA
- * transfers, do the needful for the last request.
- */
+ * Since OPT.STATIC field should be SET for isolated QDMA
+ * transfers or for the final transfer in a linked list of QDMA
+ * transfers, do the needful for the last request.
+ */
result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
- EDMA3_DRV_OPT_FIELD_STATIC, 1u);
- }
+ EDMA3_DRV_OPT_FIELD_STATIC, 1u);
+ }
/* Write to the Source Address */
result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
- (uint32_t)(srcBuff1),
- EDMA3_DRV_ADDR_MODE_INCR,
- EDMA3_DRV_W8BIT);
+ (uint32_t)(srcBuff1),
+ EDMA3_DRV_ADDR_MODE_INCR,
+ EDMA3_DRV_W8BIT);
/*
- * Now trigger the QDMA channel by writing to the Trigger
- * Word which is set as Destination Address.
- */
+ * Now trigger the QDMA channel by writing to the Trigger
+ * Word which is set as Destination Address.
+ */
if (result == EDMA3_DRV_SOK)
- {
+ {
result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,
- EDMA3_DRV_PARAM_ENTRY_DST,
- (uint32_t)(dstBuff1));
+ EDMA3_DRV_PARAM_ENTRY_DST,
+ (uint32_t)(dstBuff1));
if (result != EDMA3_DRV_SOK)
- {
+ {
printf ("error from qdma_test\n\r\n");
break;
- }
}
+ }
/* Wait for the Completion ISR. */
- edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
+ edma3OsSemTake(AppSemHandle1, EDMA3_OSSEM_NO_TIMEOUT);
while (irqRaised1 == 0)
- {
+ {
/* Wait for the Completion ISR. */
- printf ("waiting for interrupt...\n");
- }
+ printf ("waiting for interrupt...\n");
+ }
/* Check the status of the completed transfer */
if (irqRaised1 < 0)
- {
+ {
/* Some error occured, break from the FOR loop. */
printf ("\r\nqdma_test: Event Miss Occured!!!\r\n");
result = EDMA3_DRV_clearErrorBits (hEdma, qCh1Id);
break;
- }
+ }
/**
- * Now, update the source and destination addresses for next
- * "Trigger".
- */
+ * Now, update the source and destination addresses for next
+ * "Trigger".
+ */
srcBuff1 += srccidx;
dstBuff1 += descidx;
- }
}
+ }
if (result == EDMA3_DRV_SOK)
- {
+ {
/* Restore the src and dest buffers */
srcBuff1 = tmpSrcBuff1;
dstBuff1 = tmpDstBuff1;
/* Match the Source and Destination Buffers. */
for (i = 0u; i < (acnt*bcnt*ccnt); i++)
- {
+ {
if (srcBuff1[i] != dstBuff1[i])
- {
+ {
Istestpassed = 0u;
printf("qdma_test: Data write-read matching FAILED" \
- " at i = %d\r\n", (int)i);
+ " at i = %d\r\n", (int)i);
break;
- }
}
+ }
if (i == (acnt*bcnt*ccnt))
- {
+ {
Istestpassed = 1u;
- }
+ }
/* Free the previously allocated channel. */
result = EDMA3_DRV_freeChannel (hEdma, qCh1Id);
if (result != EDMA3_DRV_SOK)
- {
+ {
printf("qdma_test: EDMA3_DRV_freeChannel() FAILED, error code: %d\r\n", (int)result);
- }
}
+ }
if(Istestpassed == 1u)
- {
+ {
printf("qdma_test PASSED\r\n");
- }
+ }
else
- {
+ {
printf("qdma_test FAILED\r\n");
result = ((EDMA3_DRV_SOK == result) ?
- EDMA3_DATA_MISMATCH_ERROR : result);
- }
-
- return result;
+ EDMA3_DATA_MISMATCH_ERROR : result);
}
-
+ return result;
+}
index bea000f853352bbfb1d69835f720c9a31ce73765..63e708af81c4c74c785073068c15f4ddf1fce2ac 100644 (file)
/*
- * bios6_edma3_drv_sample.h
- *
- * Header file for the Demo application for the EDMA3 Driver.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+* bios6_edma3_drv_sample.h
+*
+* Header file for the Demo application for the EDMA3 Driver.
+*
+* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
*/
#ifndef _SAMPLE_H_
extern "C" {
#endif
-/* MAX ACOUNT */
-#define MAX_ACOUNT (64u)
-/* MAX BCOUNT */
-#define MAX_BCOUNT (1u)
-/* MAX CCOUNT */
-#define MAX_CCOUNT (1u)
-/**
- * Buffers (src and dest) are needed for mem-2-mem data transfers.
- * This define is for the MAXIMUM size and hence the maximum data
- * which could be transferred using the sample test cases below.
- */
-#define MAX_BUFFER_SIZE (MAX_ACOUNT * MAX_BCOUNT * MAX_CCOUNT)
+ /* MAX ACOUNT */
+#define MAX_ACOUNT (64u)
+ /* MAX BCOUNT */
+#define MAX_BCOUNT (1u)
+ /* MAX CCOUNT */
+#define MAX_CCOUNT (1u)
+ /**
+ * Buffers (src and dest) are needed for mem-2-mem data transfers.
+ * This define is for the MAXIMUM size and hence the maximum data
+ * which could be transferred using the sample test cases below.
+ */
+#define MAX_BUFFER_SIZE (MAX_ACOUNT * MAX_BCOUNT * MAX_CCOUNT)
#ifndef BUILD_TDA2XX_MPU
-/* To enable/disable the cache .*/
+ /* To enable/disable the cache .*/
#define EDMA3_ENABLE_DCACHE (1u)
#endif
-/* OPT Field specific defines */
+ /* OPT Field specific defines */
#define OPT_SYNCDIM_SHIFT (0x00000002u)
#define OPT_TCC_MASK (0x0003F000u)
#define OPT_TCC_SHIFT (0x0000000Cu)
#define OPT_ITCINTEN_SHIFT (0x00000015u)
#define OPT_TCINTEN_SHIFT (0x00000014u)
-/**
- * EDMA3 Driver Handle, which is used to call all the Driver APIs.
- * It gets initialized during EDMA3 Initialization.
- */
-extern EDMA3_DRV_Handle hEdma[];
+ /**
+ * EDMA3 Driver Handle, which is used to call all the Driver APIs.
+ * It gets initialized during EDMA3 Initialization.
+ */
+ extern EDMA3_DRV_Handle hEdma[];
-extern void callback1 (uint32_t tcc, EDMA3_RM_TccStatus status,
- void *appData);
+ extern void callback1 (uint32_t tcc, EDMA3_RM_TccStatus status,
+ void *appData);
-extern void callback2 (uint32_t tcc, EDMA3_RM_TccStatus status,
- void *appData);
+ extern void callback2 (uint32_t tcc, EDMA3_RM_TccStatus status,
+ void *appData);
-extern signed char* getGlobalAddr(signed char* addr);
-/* Flag variable to check transfer completion on channel 1 */
-extern volatile short irqRaised1;
-/* Flag variable to check transfer completion on channel 2 */
-extern volatile short irqRaised2;
+ extern signed char* getGlobalAddr(signed char* addr);
+ /* Flag variable to check transfer completion on channel 1 */
+ extern volatile short irqRaised1;
+ /* Flag variable to check transfer completion on channel 2 */
+ extern volatile short irqRaised2;
#define MAX_NUM_EDMA_INSTANCES 5
-/* Define to verify the default RM config.
- * Additional configuration required. Update the
- * gblCfgReqdArray[] to reflect the master/slave config.
- * In the case of multiple instances default configuration
- * may require more than one cores other than core 0 to be master.
- * #define EDMA3_DRV_USE_DEF_RM_CFG
- */
+ /* Define to verify the default RM config.
+ * Additional configuration required. Update the
+ * gblCfgReqdArray[] to reflect the master/slave config.
+ * In the case of multiple instances default configuration
+ * may require more than one cores other than core 0 to be master.
+ * #define EDMA3_DRV_USE_DEF_RM_CFG
+ */
#define GLOBAL_ADDR(addr) (getGlobalAddr(addr))
-/**
- * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
- *
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
-EDMA3_DRV_Result edma3_test(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType);
-
-
-
-/**
- * \brief EDMA3 mem-to-mem data copy test case, using two DMA
- * channels, linked to each other.
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
-EDMA3_DRV_Result edma3_test_with_link(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType);
-
-
-
-/**
- * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel.
- *
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
-EDMA3_DRV_Result qdma_test(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType);
-
-
-
-/**
- * \brief EDMA3 misc test cases.
- * This test case will read/write to some CC registers.
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
-EDMA3_DRV_Result edma3_misc_test(EDMA3_DRV_Handle hEdma);
-
-
-/**
- * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel,
- * linked to another LINK channel.
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
-EDMA3_DRV_Result qdma_test_with_link(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType);
-
-
-/**
- * \brief EDMA3 mem-to-mem data copy test case, using two DMA channels,
- * chained to each other.
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
-EDMA3_DRV_Result edma3_test_with_chaining(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType);
-
-
-/**
- * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
- * This test case doesnot rely on the callback mechanism.
- * Instead, it Polls the IPR register to check the transfer
- * completion status.
- *
- * \param acnt [IN] Number of bytes in an array
- * \param bcnt [IN] Number of arrays in a frame
- * \param ccnt [IN] Number of frames in a block
- * \param syncType [IN] Synchronization type (A/AB Sync)
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
-EDMA3_DRV_Result edma3_test_poll_mode(
- EDMA3_DRV_Handle hEdma,
- uint32_t acnt,
- uint32_t bcnt,
- uint32_t ccnt,
- EDMA3_DRV_SyncType syncType);
-
-
-/**
- * \brief EDMA3 ping-pong based data copy test case, using a DMA and
- * a link channel.
- *
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
- */
-EDMA3_DRV_Result edma3_test_ping_pong_mode(EDMA3_DRV_Handle hEdma);
+ /**
+ * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
+ *
+ *
+ * \param acnt [IN] Number of bytes in an array
+ * \param bcnt [IN] Number of arrays in a frame
+ * \param ccnt [IN] Number of frames in a block
+ * \param syncType [IN] Synchronization type (A/AB Sync)
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+ EDMA3_DRV_Result edma3_test(
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType);
+
+
+
+ /**
+ * \brief EDMA3 mem-to-mem data copy test case, using two DMA
+ * channels, linked to each other.
+ *
+ * \param acnt [IN] Number of bytes in an array
+ * \param bcnt [IN] Number of arrays in a frame
+ * \param ccnt [IN] Number of frames in a block
+ * \param syncType [IN] Synchronization type (A/AB Sync)
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+ EDMA3_DRV_Result edma3_test_with_link(
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType);
+
+
+
+ /**
+ * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel.
+ *
+ *
+ * \param acnt [IN] Number of bytes in an array
+ * \param bcnt [IN] Number of arrays in a frame
+ * \param ccnt [IN] Number of frames in a block
+ * \param syncType [IN] Synchronization type (A/AB Sync)
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+ EDMA3_DRV_Result qdma_test(
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType);
+
+
+
+ /**
+ * \brief EDMA3 misc test cases.
+ * This test case will read/write to some CC registers.
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+ EDMA3_DRV_Result edma3_misc_test(EDMA3_DRV_Handle hEdma);
+
+
+ /**
+ * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel,
+ * linked to another LINK channel.
+ *
+ * \param acnt [IN] Number of bytes in an array
+ * \param bcnt [IN] Number of arrays in a frame
+ * \param ccnt [IN] Number of frames in a block
+ * \param syncType [IN] Synchronization type (A/AB Sync)
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+ EDMA3_DRV_Result qdma_test_with_link(
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType);
+
+
+ /**
+ * \brief EDMA3 mem-to-mem data copy test case, using two DMA channels,
+ * chained to each other.
+ *
+ * \param acnt [IN] Number of bytes in an array
+ * \param bcnt [IN] Number of arrays in a frame
+ * \param ccnt [IN] Number of frames in a block
+ * \param syncType [IN] Synchronization type (A/AB Sync)
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+ EDMA3_DRV_Result edma3_test_with_chaining(
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType);
+
+
+ /**
+ * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.
+ * This test case doesnot rely on the callback mechanism.
+ * Instead, it Polls the IPR register to check the transfer
+ * completion status.
+ *
+ * \param acnt [IN] Number of bytes in an array
+ * \param bcnt [IN] Number of arrays in a frame
+ * \param ccnt [IN] Number of frames in a block
+ * \param syncType [IN] Synchronization type (A/AB Sync)
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+ EDMA3_DRV_Result edma3_test_poll_mode(
+ EDMA3_DRV_Handle hEdma,
+ uint32_t acnt,
+ uint32_t bcnt,
+ uint32_t ccnt,
+ EDMA3_DRV_SyncType syncType);
+
+
+ /**
+ * \brief EDMA3 ping-pong based data copy test case, using a DMA and
+ * a link channel.
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ */
+ EDMA3_DRV_Result edma3_test_ping_pong_mode(EDMA3_DRV_Handle hEdma);
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif /* _SAMPLE_H_ */
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