Updated AM335x and AM437x sample config file with correct available resources DEV_EDMA3_LLD_02_12_01_23
authorIvan Pang <i-pang@ti.com>
Tue, 1 Mar 2016 17:30:07 +0000 (11:30 -0600)
committerIvan Pang <i-pang@ti.com>
Tue, 1 Mar 2016 17:30:07 +0000 (11:30 -0600)
Signed-off-by: Ivan Pang <i-pang@ti.com>
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_am335x_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_am437x_cfg.c

index d1ef5967984e7b2f7a29b45f2c4e01f0ba9cafd8..8f6683c2ce80c9613937c0de4f478a847e1c9018 100644 (file)
@@ -403,22 +403,22 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
       * on the mapped channel.
       */
         {
-        0u, 1u, 2u, 3u,
         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
-        8u, 9u, 10u, 11u,
-        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, 14u, 15u,
-        16u, 17u, 18u, 19u,
-        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, 22u, 23u,
-        24u, 25u, 26u, 27u,
-        28u, 29u, 30u, 31u,
         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
-        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, 38u, 39u,
-        40u, 41u, 42u, 43u,
-        44u, 45u, 46u, 47u,
-        48u, 49u, 50u, 51u,
-        52u, 53u, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
-        56u, 57u, 58u, 59u,
-        60u, 61u, 62u, 63u
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP
         },
 
     /**
@@ -443,9 +443,9 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU
             /* Resources owned by Region 0 */
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
             /* 159  128     191  160     223  192     255  224 */
-             0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
             /* 287  256     319  288     351  320     383  352 */
              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
             /* 415  384     447  416     479  448     511  480 */
@@ -453,20 +453,20 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x00303000u, 0x00C0003Fu},
+            {0xFFFFFFFFu, 0xFFFFFFFFu},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x000000FFu},
+            {0x000000FFU},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x00303000u, 0x00C0003Fu},
+            {0xFFFFFFFFU, 0xFFFFFFFFU},
 
             /* Resources reserved by Region 0 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
             /* 159  128     191  160     223  192     255  224 */
              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
             /* 287  256     319  288     351  320     383  352 */
@@ -476,7 +476,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU
 
             /* resvdDmaChannels */
             /* 31                                         0  63                                                  32 */
-            {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
+            {0x00000000u, 0x00000000u},
 
             /* resvdQdmaChannels */
             /* 31     0 */
@@ -484,7 +484,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU
 
             /* resvdTccs */
             /* 31                                         0  63                                                  32 */
-            {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
+            {0x00000000u, 0x00000000u},
           },
 
           {
index 4746d98fba5f81dc7b44782997ce53c924cb5547..44fce33f1295f7ef3490b8a2177baf10c46691bd 100644 (file)
@@ -403,22 +403,22 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams [NUM_EDMA3_INSTANCES] =
       * on the mapped channel.
       */
         {
-        0u, 1u, 2u, 3u,
         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
-        8u, 9u, 10u, 11u,
-        12u, 13u, 14u, 15u,
-        16u, 17u, 18u, 19u,
-        20u, 21u, 22u, 23u,
-        24u, 25u, 26u, 27u,
-        28u, 29u, 30u, 31u,
         EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
-        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, 38u, 39u,
-        40u, 41u, 42u, 43u,
-        44u, 45u, 46u, 47u,
-        48u, 49u, 50u, 51u,
-        52u, 53u, 54u, 55u,
-        56u, 57u, 58u, 59u,
-        60u, 61u, 62u, 63u
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+        EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP
         },
 
     /**
@@ -442,9 +442,9 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU
             /* Resources owned by Region 0 */
             /* ownPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
             /* 159  128     191  160     223  192     255  224 */
-             0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU,
             /* 287  256     319  288     351  320     383  352 */
              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
             /* 415  384     447  416     479  448     511  480 */
@@ -452,20 +452,20 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU
 
             /* ownDmaChannels */
             /* 31     0     63    32 */
-            {0x000000F0u, 0x0000003Fu},
+            {0xFFFFFFFFu, 0xFFFFFFFFu},
 
             /* ownQdmaChannels */
             /* 31     0 */
-            {0x000000FFu},
+            {0x000000FFU},
 
             /* ownTccs */
             /* 31     0     63    32 */
-            {0x000000F0u, 0x0000003Fu},
+            {0xFFFFFFFFU, 0xFFFFFFFFU},
 
             /* Resources reserved by Region 0 */
             /* resvdPaRAMSets */
             /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
             /* 159  128     191  160     223  192     255  224 */
              0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
             /* 287  256     319  288     351  320     383  352 */
@@ -475,7 +475,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU
 
             /* resvdDmaChannels */
             /* 31                                         0  63                                                  32 */
-            {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
+            {0x00000000u, 0x00000000u},
 
             /* resvdQdmaChannels */
             /* 31     0 */
@@ -483,7 +483,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU
 
             /* resvdTccs */
             /* 31                                         0  63                                                  32 */
-            {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1},
+            {0x00000000u, 0x00000000u},
           },
 
           {