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raw | patch | inline | side by side (parent: 625e363)
raw | patch | inline | side by side (parent: 625e363)
| author | Arvind <x0193495@ti.com> | |
| Wed, 18 Dec 2013 12:05:40 +0000 (17:35 +0530) | ||
| committer | Arvind <x0193495@ti.com> | |
| Wed, 18 Dec 2013 12:05:40 +0000 (17:35 +0530) |
17 files changed:
diff --git a/examples/edma3_driver/evmtda2xx_EVE/eve_edma_mmu_setting.gel b/examples/edma3_driver/evmtda2xx_EVE/eve_edma_mmu_setting.gel
--- /dev/null
@@ -0,0 +1,192 @@
+#define WR_MEM_32(addr, data) *(unsigned int*)(addr) =(unsigned int)(data)\r
+#define RD_MEM_32(addr) *(unsigned int*)(addr)\r
+\r
+menuitem "EVE MMU Config"\r
+\r
+hotmenu EVE_MMU_Config()\r
+{\r
+ EVE1_MMU_Config();\r
+ EVE2_MMU_Config();\r
+ EVE3_MMU_Config();\r
+ EVE4_MMU_Config();\r
+}\r
+\r
+hotmenu EVE1_MMU_Config()\r
+{\r
+ //#define MMU_BASE 0x40081000 //EVE's view\r
+ #define MMU_BASE 0x42081000 // MPU's view\r
+ #define TESLASS_MMU__MMU_CNTL ( MMU_BASE + 0x44 )\r
+ #define TESLASS_MMU__MMU_CAM ( MMU_BASE + 0x58 )\r
+ #define TESLASS_MMU__MMU_RAM ( MMU_BASE + 0x5c )\r
+ #define TESLASS_MMU__MMU_LOCK ( MMU_BASE + 0x50 )\r
+ #define TESLASS_MMU__MMU_LD_TLB ( MMU_BASE + 0x54 )\r
+\r
+ #define PHY_ADDR1 0x81000000\r
+ #define VIRT_ADDR1 0x00000000\r
+ \r
+ #define PHY_ADDR2 0x81000000\r
+ #define VIRT_ADDR2 0x81000000\r
+ \r
+ /* Configure the MMU */\r
+ GEL_TextOut("\tConfiguring EVE1 MMU TLB entry 1 \n","Output",1,1,1);\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000c | (VIRT_ADDR1 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR1 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4 \r
+\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 1 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+\r
+ GEL_TextOut("\tConfiguring EVE1 MMU TLB entry 2 \n","Output",1,1,1);\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000f | (VIRT_ADDR2 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR2 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4 \r
+\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 2 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+\r
+ /*Enable MMU*/\r
+ WR_MEM_32(TESLASS_MMU__MMU_CNTL, ((RD_MEM_32(TESLASS_MMU__MMU_CNTL)) & 0xFFFFFFFD) | 0x2); \r
+\r
+ /********************/\r
+ GEL_TextOut("\tMMU configured for EVE1 \n","Output",1,1,1);\r
+}\r
+\r
+hotmenu EVE2_MMU_Config()\r
+{\r
+ //#define MMU_BASE 0x40081000 //EVE's view\r
+ #define MMU_BASE 0x42181000 // MPU's view\r
+ #define TESLASS_MMU__MMU_CNTL ( MMU_BASE + 0x44 )\r
+ #define TESLASS_MMU__MMU_CAM ( MMU_BASE + 0x58 )\r
+ #define TESLASS_MMU__MMU_RAM ( MMU_BASE + 0x5c )\r
+ #define TESLASS_MMU__MMU_LOCK ( MMU_BASE + 0x50 )\r
+ #define TESLASS_MMU__MMU_LD_TLB ( MMU_BASE + 0x54 )\r
+\r
+ #define PHY_ADDR1 0x81000000\r
+ #define VIRT_ADDR1 0x00000000\r
+\r
+ #define PHY_ADDR2 0x81000000\r
+ #define VIRT_ADDR2 0x81000000\r
+\r
+ /* Configure the MMU */\r
+ GEL_TextOut("\tConfiguring EVE2 MMU TLB entry 1 \n","Output",1,1,1);\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000c | (VIRT_ADDR1 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR1 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4 \r
+\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 1 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+\r
+ GEL_TextOut("\tConfiguring EVE2 MMU TLB entry 2 \n","Output",1,1,1);\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000f | (VIRT_ADDR2 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR2 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4 \r
+\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 2 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+\r
+ /*Enable MMU*/\r
+ WR_MEM_32(TESLASS_MMU__MMU_CNTL, ((RD_MEM_32(TESLASS_MMU__MMU_CNTL)) & 0xFFFFFFFD) | 0x2); \r
+\r
+ /********************/\r
+ GEL_TextOut("\tMMU configured for EVE2 \n","Output",1,1,1);\r
+}\r
+\r
+hotmenu EVE3_MMU_Config()\r
+{\r
+ //#define MMU_BASE 0x40081000 //EVE's view\r
+ #define MMU_BASE 0x42281000 // MPU's view\r
+ #define TESLASS_MMU__MMU_CNTL ( MMU_BASE + 0x44 )\r
+ #define TESLASS_MMU__MMU_CAM ( MMU_BASE + 0x58 )\r
+ #define TESLASS_MMU__MMU_RAM ( MMU_BASE + 0x5c )\r
+ #define TESLASS_MMU__MMU_LOCK ( MMU_BASE + 0x50 )\r
+ #define TESLASS_MMU__MMU_LD_TLB ( MMU_BASE + 0x54 )\r
+\r
+ #define PHY_ADDR1 0x81000000\r
+ #define VIRT_ADDR1 0x00000000\r
+\r
+ #define PHY_ADDR2 0x81000000\r
+ #define VIRT_ADDR2 0x81000000\r
+\r
+ /* Configure the MMU */\r
+ GEL_TextOut("\tConfiguring EVE2 MMU TLB entry 1 \n","Output",1,1,1);\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000c | (VIRT_ADDR1 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR1 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4 \r
+\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 1 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+\r
+ GEL_TextOut("\tConfiguring EVE2 MMU TLB entry 2 \n","Output",1,1,1);\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000f | (VIRT_ADDR2 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR2 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4 \r
+\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 2 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+\r
+ /*Enable MMU*/\r
+ WR_MEM_32(TESLASS_MMU__MMU_CNTL, ((RD_MEM_32(TESLASS_MMU__MMU_CNTL)) & 0xFFFFFFFD) | 0x2); \r
+\r
+ /********************/\r
+ GEL_TextOut("\tMMU configured for EVE2 \n","Output",1,1,1);\r
+}\r
+\r
+hotmenu EVE4_MMU_Config()\r
+{\r
+ //#define MMU_BASE 0x40081000 //EVE's view\r
+ #define MMU_BASE 0x42381000 // MPU's view\r
+ #define TESLASS_MMU__MMU_CNTL ( MMU_BASE + 0x44 )\r
+ #define TESLASS_MMU__MMU_CAM ( MMU_BASE + 0x58 )\r
+ #define TESLASS_MMU__MMU_RAM ( MMU_BASE + 0x5c )\r
+ #define TESLASS_MMU__MMU_LOCK ( MMU_BASE + 0x50 )\r
+ #define TESLASS_MMU__MMU_LD_TLB ( MMU_BASE + 0x54 )\r
+\r
+ #define PHY_ADDR1 0x81000000\r
+ #define VIRT_ADDR1 0x00000000\r
+\r
+ #define PHY_ADDR2 0x81000000\r
+ #define VIRT_ADDR2 0x81000000\r
+\r
+ /* Configure the MMU */\r
+ GEL_TextOut("\tConfiguring EVE2 MMU TLB entry 1 \n","Output",1,1,1);\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000c | (VIRT_ADDR1 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR1 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4 \r
+\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 1 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+\r
+ GEL_TextOut("\tConfiguring EVE2 MMU TLB entry 2 \n","Output",1,1,1);\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000f | (VIRT_ADDR2 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR2 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4 \r
+\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 2 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+\r
+ /*Enable MMU*/\r
+ WR_MEM_32(TESLASS_MMU__MMU_CNTL, ((RD_MEM_32(TESLASS_MMU__MMU_CNTL)) & 0xFFFFFFFD) | 0x2); \r
+\r
+ /********************/\r
+ GEL_TextOut("\tMMU configured for EVE2 \n","Output",1,1,1);\r
+}
\ No newline at end of file
diff --git a/examples/edma3_driver/evmtda2xx_EVE/eve_mmu.c b/examples/edma3_driver/evmtda2xx_EVE/eve_mmu.c
--- /dev/null
@@ -0,0 +1,103 @@
+/*\r
+ * eve_mmu.c\r
+ *\r
+ * This file contains the test / demo code to demonstrate the EDMA3 driver\r
+ * functionality on DSP/BIOS 6.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+/******************************************************************************\r
+* Macro Declarations *\r
+******************************************************************************/\r
+#define WR_MEM_32(addr, data) *(unsigned int*)(addr) =(unsigned int)(data)\r
+#define RD_MEM_32(addr) *(unsigned int*)(addr)\r
+\r
+#define MMU_BASE 0x40081000 /* EVE's view */\r
+/* #define MMU_BASE 0x42081000 */ /* MPU's view */\r
+#define TESLASS_MMU__MMU_CNTL ( MMU_BASE + 0x44 )\r
+#define TESLASS_MMU__MMU_CAM ( MMU_BASE + 0x58 )\r
+#define TESLASS_MMU__MMU_RAM ( MMU_BASE + 0x5c )\r
+#define TESLASS_MMU__MMU_LOCK ( MMU_BASE + 0x50 )\r
+#define TESLASS_MMU__MMU_LD_TLB ( MMU_BASE + 0x54 )\r
+\r
+#define PHY_ADDR1 0x4A000000\r
+#define VIRT_ADDR1 0x4A000000\r
+\r
+#define PHY_ADDR2 0xAA000000\r
+#define VIRT_ADDR2 0xAA000000\r
+\r
+#define PHY_ADDR3 0xAB000000\r
+#define VIRT_ADDR3 0xAB000000\r
+\r
+/*\r
+ * eve1MmuConfig() This function does EVE MMU settings. This function is\r
+ * called from Reset Module which is defined in configuration file. \r
+ */\r
+void eveMmuConfig(void)\r
+{\r
+ /* ------------------------------------------------------------------------------------------------------- */\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000f | (VIRT_ADDR1 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR1 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 3 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+ /* ------------------------------------------------------------------------------------------------------- */\r
+\r
+ /* ------------------------------------------------------------------------------------------------------- */\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000f | (VIRT_ADDR2 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR2 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 4 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+ /* ------------------------------------------------------------------------------------------------------- */\r
+\r
+\r
+ /* ------------------------------------------------------------------------------------------------------- */\r
+ WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000f | (VIRT_ADDR3 & 0xFFFFE000));\r
+ WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR3 & 0xFFFFE000));\r
+\r
+ /* tlbEntry is bits 8:4\r
+ #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM BITFIELD(8, 4) */\r
+ WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 5 << 4 ));\r
+ WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+ /* ------------------------------------------------------------------------------------------------------- */\r
+\r
+ /*Enable MMU*/\r
+ WR_MEM_32(TESLASS_MMU__MMU_CNTL, ((RD_MEM_32(TESLASS_MMU__MMU_CNTL)) & 0xFFFFFFFD) | 0x2);\r
+\r
+}\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/makefile b/examples/edma3_driver/evmtda2xx_EVE/makefile
--- /dev/null
@@ -0,0 +1,40 @@
+# Makefile for edma3 lld app\r
+\r
+APP_NAME = edma3_drv_tda2xx_sample\r
+\r
+SRCDIR = ../src .\r
+INCDIR = ../src\r
+\r
+# List all the external components/interfaces, whose interface header files \r
+# need to be included for this component\r
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld\r
+\r
+# List all the components required by the application\r
+COMP_LIST_eve = edma3_lld_drv edma3_lld_rm\r
+\r
+# XDC CFG File\r
+XDC_CFG_FILE_eve = rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg\r
+\r
+CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld\r
+\r
+PLATFORM_XDC_CUSTOM = ti.platforms.simVayu:EVE_1\r
+\r
+# Common source files and CFLAGS across all platforms and cores\r
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \\r
+ dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \\r
+ qdma_link_test.c eve_mmu.c\r
+\r
+CFLAGS_LOCAL_COMMON = -DBUILD_TDA2XX_EVE\r
+\r
+# Core/SoC/platform specific source files and CFLAGS\r
+# Example: \r
+# SRCS_<core/SoC/platform-name> = \r
+# CFLAGS_LOCAL_<core/SoC/platform-name> =\r
+\r
+# Include common make files\r
+include $(ROOTDIR)/makerules/common.mk\r
+\r
+# OBJs and libraries are built by using rule defined in rules_<target>.mk \r
+# and need not be explicitly specified here\r
+\r
+# Nothing beyond this point\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/app_mem_seg_placement.cfg b/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/app_mem_seg_placement.cfg
--- /dev/null
@@ -0,0 +1,49 @@
+/*******************************************************************************\r
+ * *\r
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/ *\r
+ * ALL RIGHTS RESERVED *\r
+ * *\r
+ ******************************************************************************/\r
+\r
+/*\r
+ * @file app_mem_seg_placement.cfg\r
+ *\r
+ * @brief \r
+ */\r
+\r
+function init()\r
+{\r
+ Program.sectMap[".inthandler"] = "CODE_CORE_EVE";\r
+ Program.sectMap[".text"] = "CODE_CORE_EVE";\r
+ Program.sectMap[".stack"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".bss:taskStackSection"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".bss"] = "PRIVATE_DATA_CORE_EVE";\r
+ //Program.sectMap[".bss"] = "DMEM";\r
+ Program.sectMap[".cinit"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".init_array"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".const"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".data"] = "PRIVATE_DATA_CORE_EVE";\r
+ //Program.sectMap[".data"] = "DMEM";\r
+ Program.sectMap[".switch"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".sysmem"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".far"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".args"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".cio"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".fardata"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".rodata"] = "PRIVATE_DATA_CORE_EVE";\r
+ //Program.sectMap[".rodata"] = "DMEM";\r
+ Program.sectMap[".sysmem"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".sysmem"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".my_sect_iram"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".my_sect_ddr"] = "PRIVATE_DATA_CORE_EVE";\r
+ Program.sectMap[".vecs"] = "EVE_1_VECS";\r
+ /* Program.sectMap[".imemha"] = "IBUFHA";\r
+ Program.sectMap[".imemhb"] = "IBUFHB";\r
+ Program.sectMap[".imemla"] = "IBUFLA";\r
+ Program.sectMap[".imemlb"] = "IBUFLB";\r
+ Program.sectMap[".wmem"] = "WBUF";\r
+ Program.sectMap[".vcop_parameter_block"] = "WBUF";\r
+ Program.sectMap["Cdata"] = "WBUF";\r
+ Program.sectMap["Udata"] = "WBUF";\r
+ */\r
+}\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/custom_config.bld b/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/custom_config.bld
--- /dev/null
@@ -0,0 +1,6 @@
+/*\r
+ * ======== config.bld ========\r
+ * Sample Build configuration script\r
+ */\r
+\r
+var platform_xs = xdc.loadCapsule("platform.xs");
\ No newline at end of file
diff --git a/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg b/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
--- /dev/null
@@ -0,0 +1,24 @@
+/*use modules*/\r
+var Task = xdc.useModule ("ti.sysbios.knl.Task");\r
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");\r
+var Startup = xdc.useModule ("xdc.runtime.Startup");\r
+var System = xdc.useModule ("xdc.runtime.System");\r
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');\r
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');\r
+var Cache = xdc.useModule('ti.sysbios.family.arp32.Cache');\r
+var InitXbar = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");\r
+var Cache = xdc.useModule('ti.sysbios.family.arp32.Cache');\r
+var halCache = xdc.useModule('ti.sysbios.hal.Cache');\r
+var Reset = xdc.useModule('xdc.runtime.Reset');\r
+\r
+Reset.fxns[Reset.fxns.length++] = "&eveMmuConfig";\r
+\r
+halCache.CacheProxy = Cache;\r
+\r
+//Program.heap = 0x5000;\r
+\r
+/* USE EDMA3 Sample App */\r
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');\r
+\r
+var segPlacement = xdc.loadCapsule("app_mem_seg_placement.cfg");\r
+segPlacement.init();\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/mem_segment_definition.xs
--- /dev/null
@@ -0,0 +1,341 @@
+/*******************************************************************************\r
+ * *\r
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/ *\r
+ * ALL RIGHTS RESERVED *\r
+ * *\r
+ ******************************************************************************/\r
+\r
+/*\r
+ * ======== mem_segment_definition.xs ========\r
+ */\r
+\r
+\r
+function getMemSegmentDefinitionIPU_1_0()\r
+{\r
+ var memory = new Array();\r
+\r
+ memory[0] = ["CODE_CORE_IPU1_0",\r
+ {\r
+ name: "CODE_CORE_IPU1_0",\r
+ base: 0x84000000,\r
+ len: 0x01000000,\r
+ space: "code",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",\r
+ {\r
+ name: "PRIVATE_DATA_CORE_IPU1_0",\r
+ base: 0x85000000,\r
+ len: 0x01800000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",\r
+ {\r
+ name: "HDVPSS_DESCRIPTOR_NON_CACHED",\r
+ base: 0xA1800000,\r
+ len: 0x00800000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[3] = ["SHARED_MEM",\r
+ {\r
+ name: "SHARED_MEM",\r
+ base: 0xA2000000,\r
+ len: 0x01000000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[4] = ["SHARED_FRAME_BUFFER",\r
+ {\r
+ name: "SHARED_FRAME_BUFFER",\r
+ base: 0x8A000000,\r
+ len: 0x04000000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[5] = ["SHARED_CTRL",\r
+ {\r
+ name: "SHARED_CTRL",\r
+ base: 0xA0000000,\r
+ len: 0x01000000,\r
+ space: "code/data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[6] = ["SHARED_LOG_MEM",\r
+ {\r
+ name: "SHARED_LOG_MEM",\r
+ base: 0xA1000000,\r
+ len: 0x00700000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+ \r
+ return (memory);\r
+}\r
+\r
+function getMemSegmentDefinitionIPU_1_1()\r
+{\r
+ var memory = new Array();\r
+\r
+ memory[0] = ["CODE_CORE_IPU1_1",\r
+ {\r
+ name: "CODE_CORE_IPU1_1",\r
+ base: 0x86800000,\r
+ len: 0x01000000,\r
+ space: "code",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",\r
+ {\r
+ name: "PRIVATE_DATA_CORE_IPU1_1",\r
+ base: 0x87800000,\r
+ len: 0x01800000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[2] = ["SHARED_MEM",\r
+ {\r
+ name: "SHARED_MEM",\r
+ base: 0xA2000000,\r
+ len: 0x01000000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[3] = ["SHARED_FRAME_BUFFER",\r
+ {\r
+ name: "SHARED_FRAME_BUFFER",\r
+ base: 0x8A000000,\r
+ len: 0x04000000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[4] = ["SHARED_CTRL",\r
+ {\r
+ name: "SHARED_CTRL",\r
+ base: 0xA0000000,\r
+ len: 0x01000000,\r
+ space: "code/data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[5] = ["SHARED_LOG_MEM",\r
+ {\r
+ name: "SHARED_LOG_MEM",\r
+ base: 0xA1000000,\r
+ len: 0x00700000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+ \r
+ return (memory);\r
+}\r
+\r
+function getMemSegmentDefinitionDSP_1()\r
+{\r
+ var memory = new Array();\r
+\r
+ memory[0] = ["CODE_CORE_DSP1",\r
+ {\r
+ name: "CODE_CORE_DSP1",\r
+ base: 0x83100000,\r
+ len: 0x00700000,\r
+ space: "code",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[1] = ["PRIVATE_DATA_CORE_DSP1",\r
+ {\r
+ name: "PRIVATE_DATA_CORE_DSP1",\r
+ base: 0x83800000,\r
+ len: 0x00800000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[2] = ["SHARED_MEM",\r
+ {\r
+ name: "SHARED_MEM",\r
+ base: 0xA2000000,\r
+ len: 0x01000000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[3] = ["SHARED_FRAME_BUFFER",\r
+ {\r
+ name: "SHARED_FRAME_BUFFER",\r
+ base: 0x8A000000,\r
+ len: 0x04000000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[4] = ["SHARED_CTRL",\r
+ {\r
+ name: "SHARED_CTRL",\r
+ base: 0xA0000000,\r
+ len: 0x01000000,\r
+ space: "code/data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[5] = ["SHARED_LOG_MEM",\r
+ {\r
+ name: "SHARED_LOG_MEM",\r
+ base: 0xA1000000,\r
+ len: 0x00700000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+ \r
+ return (memory);\r
+}\r
+\r
+function getMemSegmentDefinitionHOST()\r
+{\r
+ var memory = new Array();\r
+\r
+ memory[8] = ["CODE_CORE_HOST",\r
+ {\r
+ name: "CODE_CORE_HOST",\r
+ base: 0x89000000,\r
+ len: 0x00800000,\r
+ space: "code",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[9] = ["PRIVATE_DATA_CORE_HOST",\r
+ {\r
+ name: "PRIVATE_DATA_CORE_HOST",\r
+ base: 0x89800000,\r
+ len: 0x00800000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[10] = ["SHARED_MEM",\r
+ {\r
+ name: "SHARED_MEM",\r
+ base: 0xA2000000,\r
+ len: 0x01000000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[11] = ["SHARED_FRAME_BUFFER",\r
+ {\r
+ name: "SHARED_FRAME_BUFFER",\r
+ base: 0x8A000000,\r
+ len: 0x04000000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[12] = ["SHARED_CTRL",\r
+ {\r
+ name: "SHARED_CTRL",\r
+ base: 0xA0000000,\r
+ len: 0x01000000,\r
+ space: "code/data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[13] = ["SHARED_LOG_MEM",\r
+ {\r
+ name: "SHARED_LOG_MEM",\r
+ base: 0xA1000000,\r
+ len: 0x00700000,\r
+ space: "data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ return (memory);\r
+}\r
+\r
+function getMemSegmentDefinitionEVE()\r
+{\r
+ var memory = new Array();\r
+\r
+ memory[0] = ["EVE_1_VECS",\r
+ {\r
+ name: "EVE_1_VECS",\r
+ base: 0x81000000,\r
+ len: 0x00000100,\r
+ space: "code/data",\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[1] = ["CODE_CORE_EVE",\r
+ {\r
+ name: "CODE_CORE_EVE",\r
+ base: 0x81000100,\r
+ len: 0x0004FF00,\r
+ space: "code",\r
+ page: 1,\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[2] = ["PRIVATE_DATA_CORE_EVE",\r
+ {\r
+ name: "PRIVATE_DATA_CORE_EVE",\r
+ base: 0x81050000,\r
+ len: 0x00400000,\r
+ space: "data",\r
+ page: 1,\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[3] = ["SHARED_MEM",\r
+ {\r
+ name: "SHARED_MEM",\r
+ base: 0xA2000000,\r
+ len: 0x01000000,\r
+ space: "data",\r
+ page: 1,\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[4] = ["SHARED_FRAME_BUFFER",\r
+ {\r
+ name: "SHARED_FRAME_BUFFER",\r
+ base: 0x8A000000,\r
+ len: 0x04000000,\r
+ space: "data",\r
+ page: 1,\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[5] = ["SHARED_CTRL",\r
+ {\r
+ name: "SHARED_CTRL",\r
+ base: 0xA0000000,\r
+ len: 0x01000000,\r
+ space: "code/data",\r
+ page: 1,\r
+ access: "RWX"\r
+ }];\r
+\r
+ memory[6] = ["SHARED_LOG_MEM",\r
+ {\r
+ name: "SHARED_LOG_MEM",\r
+ base: 0xA1000000,\r
+ len: 0x00700000,\r
+ space: "data",\r
+ page: 1,\r
+ access: "RWX"\r
+ }];\r
+\r
+ return (memory);\r
+}\r
+\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/platform.xs b/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/platform.xs
--- /dev/null
@@ -0,0 +1,54 @@
+/*******************************************************************************\r
+ * *\r
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/ *\r
+ * ALL RIGHTS RESERVED *\r
+ * *\r
+ ******************************************************************************/\r
+\r
+/*\r
+ * ======== platform.xs ========\r
+ */\r
+\r
+var Build = xdc.useModule('xdc.bld.BuildEnvironment'); \r
+\r
+var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");\r
+\r
+Build.platformTable["ti.platforms.simVayu:IPU_1_0"] =\r
+{ \r
+ externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),\r
+ codeMemory:"CODE_CORE_IPU1_0",\r
+ dataMemory:"PRIVATE_DATA_CORE_IPU1_0",\r
+ stackMemory:"PRIVATE_DATA_CORE_IPU1_0"\r
+};\r
+\r
+Build.platformTable["ti.platforms.simVayu:IPU_1_1"] =\r
+{ \r
+ externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),\r
+ codeMemory:"CODE_CORE_IPU1_1",\r
+ dataMemory:"PRIVATE_DATA_CORE_IPU1_1",\r
+ stackMemory:"PRIVATE_DATA_CORE_IPU1_1"\r
+};\r
+\r
+Build.platformTable["ti.platforms.simVayu:DSP_1"] =\r
+{\r
+ externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),\r
+ codeMemory:"CODE_CORE_DSP1",\r
+ dataMemory:"PRIVATE_DATA_CORE_DSP1",\r
+ stackMemory:"PRIVATE_DATA_CORE_DSP1"\r
+};\r
+\r
+Build.platformTable["ti.platforms.simVayu:Cortex_A15"] =\r
+{\r
+ externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),\r
+ codeMemory:"CODE_CORE_HOST",\r
+ dataMemory:"PRIVATE_DATA_CORE_HOST",\r
+ stackMemory:"PRIVATE_DATA_CORE_HOST"\r
+};\r
+\r
+Build.platformTable["ti.platforms.simVayu:EVE_1"] =\r
+{\r
+ externalMemoryMap: MemSegDefine.getMemSegmentDefinitionEVE(),\r
+ codeMemory:"CODE_CORE_EVE",\r
+ dataMemory:"PRIVATE_DATA_CORE_EVE",\r
+ stackMemory:"PRIVATE_DATA_CORE_EVE"\r
+};\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/sample_app/linker.cmd b/examples/edma3_driver/evmtda2xx_EVE/sample_app/linker.cmd
--- /dev/null
@@ -0,0 +1,5 @@
+SECTIONS\r
+{\r
+// .my_sect_iram > EXT_RAM\r
+// .my_sect_ddr > EXT_RAM\r
+}\r
diff --git a/makerules/env.mk b/makerules/env.mk
index e6018032ce94449ea974822e29969eaccc1d1be9..dcc37587d383e56d4aa17b2a32390a67e0fc2dbb 100755 (executable)
--- a/makerules/env.mk
+++ b/makerules/env.mk
CODEGEN_PATH_DSP = $(EXTERNAL_SW_ROOT)/C6000C~2.1
CODEGEN_PATH_DSPELF = $(EXTERNAL_SW_ROOT)/C6000C~2.1
+# ARP32
+CODEGEN_PATH_ARP32 = $(EXTERNAL_SW_ROOT)/ARP32C~1.2
# Commands commonly used within the make files
diff --git a/makerules/platform.mk b/makerules/platform.mk
index 540c0d61133ccb3d348d2c386d0080bf383ce3e3..f06b9cbb8410caa8fa463e74fcf589ed19688daa 100755 (executable)
--- a/makerules/platform.mk
+++ b/makerules/platform.mk
endif
endif
+# EVE - arp32
+ifeq ($(CORE),eve)
+ ISA = arp32
+endif
+
# Platform and SOC is generic; use the core name same as ISA (eg: 674)
ifeq ($(SOC),generic)
ISA = $(CORE)
ASMEXT = s$(FORMAT_EXT)9$(ENDIAN_EXT)
endif
+ifeq ($(ISA),arp32)
+ ifeq ($(FORMAT),ELF)
+ TARGET_XDC = ti.targets.arp32.elf.ARP32_far
+ ENDIAN_EXT = f
+ FORMAT_EXT = e
+ else
+ TARGET_XDC = ti.targets.arp32.elf.ARP32
+ endif
+
+ # If ENDIAN is set to "big", set ENDIAN_EXT to "e", that would be used in
+ # in the filename extension of object/library/executable files
+ ifeq ($(ENDIAN),big)
+ ENDIAN_EXT = e
+ endif
+
+ # Define the file extensions
+ OBJEXT = o$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+ LIBEXT = a$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+ EXEEXT = x$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+ ASMEXT = s$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+endif
+
ifeq (sim,$(findstring sim,$(PLATFORM)))
OMX_PLATFORM = sim
endif
diff --git a/makerules/rules_arp32.mk b/makerules/rules_arp32.mk
--- /dev/null
+++ b/makerules/rules_arp32.mk
@@ -0,0 +1,231 @@
+#/*******************************************************************************\r
+# * *\r
+# * Copyright (c) 2013 Texas Instruments Incorporated - http://www.ti.com/ *\r
+# * ALL RIGHTS RESERVED *\r
+# * *\r
+# ******************************************************************************/\r
+\r
+# Filename: rules_arp32.mk\r
+#\r
+# Make rules for EVE - This file has all the common rules and defines required\r
+# for arp32 ISA\r
+#\r
+# This file needs to change when:\r
+# 1. Code generation tool chain changes (currently it uses arp32cgt_1.0.2)\r
+# 2. Internal switches (which are normally not touched) has to change\r
+# 3. XDC specific switches change\r
+# 4. a rule common for arp32 ISA has to be added or modified\r
+\r
+# Set compiler/archiver/linker commands and include paths\r
+CODEGEN_INCLUDE = $(CODEGEN_PATH_ARP32)/include\r
+\r
+CC = $(CODEGEN_PATH_ARP32)/bin/cl-arp32.exe\r
+AR = $(CODEGEN_PATH_ARP32)/bin/ar-arp32.exe\r
+LNK = $(CODEGEN_PATH_ARP32)/bin/lnk-arp32.exe\r
+\r
+# Derive a part of RTS Library name based on ENDIAN: little/big\r
+ifeq ($(ENDIAN),little)\r
+ RTSLIB_ENDIAN = \r
+else\r
+ RTSLIB_ENDIAN = e\r
+endif\r
+\r
+# Derive compiler switch and part of RTS Library name based on FORMAT: COFF/ELF\r
+ifeq ($(FORMAT),COFF)\r
+ CSWITCH_FORMAT = \r
+ RTSLIB_FORMAT = \r
+endif\r
+ifeq ($(FORMAT),ELF)\r
+ CSWITCH_FORMAT = eabi\r
+ RTSLIB_FORMAT = elf\r
+endif\r
+\r
+# Internal CFLAGS - normally doesn't change\r
+CFLAGS_INTERNAL = -v210 -c -qq -pdsw225 --abi=$(CSWITCH_FORMAT) -eo.$(OBJEXT) -ea.$(ASMEXT) --symdebug:dwarf\r
+CFLAGS_DIROPTS = -fr=$(OBJDIR) -fs=$(OBJDIR)\r
+\r
+# XDC Specific defines\r
+ifneq ($(XDC_CFG_FILE_$(CORE)),)\r
+ ifeq ($(PROFILE_$(CORE)),debug)\r
+ CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)\r
+ CFG_LNKFILENAMEPART_XDC=\r
+ endif\r
+ ifeq ($(PROFILE_$(CORE)),release)\r
+ CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)\r
+ CFG_LNKFILENAMEPART_XDC=\r
+ endif\r
+ ifeq ($(PROFILE_$(CORE)),whole_program_debug)\r
+ CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)\r
+ CFG_LNKFILENAMEPART_XDC=_x\r
+ endif\r
+ CFG_CFILE_XDC =$(patsubst %.cfg,%_$(CFG_CFILENAMEPART_XDC).c,$(notdir $(XDC_CFG_FILE_$(CORE))))\r
+ CFG_C_XDC = $(addprefix $(CONFIGURO_DIR)/package/cfg/,$(CFG_CFILE_XDC))\r
+ XDCLNKCMD_FILE =$(patsubst %.c, %$(CFG_LNKFILENAMEPART_XDC).xdl, $(CFG_C_XDC))\r
+ CFG_COBJ_XDC = $(patsubst %.c,%.$(OBJEXT),$(CFG_CFILE_XDC))\r
+# OBJ_PATHS += $(CFG_COBJ_XDC)\r
+ LNKCMD_FILE = $(CONFIGURO_DIR)/linker_mod.cmd\r
+ SPACE := \r
+ SPACE += \r
+ XDC_GREP_STRING = $(CONFIGURO_DIRNAME)\r
+# XDC_GREP_STRING = $(subst $(SPACE),\|,$(COMP_LIST_$(CORE)))\r
+# XDC_GREP_STRING += \|$(CONFIGURO_DIRNAME)\r
+endif\r
+\r
+# CFLAGS based on profile selected\r
+ifeq ($(PROFILE_$(CORE)), debug)\r
+ CFLAGS_XDCINTERNAL += -Dxdc_target_name__=ARP32_far -Dxdc_target_types__=ti/targets/arp32/elf/std.h -Dxdc_bld__profile_debug -Dxdc_bld__vers_1_0_4_6_1 -D_DEBUG_=1 \r
+ ifndef MODULE_NAME\r
+ CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_CFG_BASE_FILE_NAME)_pearp32.h' \r
+ endif\r
+ LNKFLAGS_INTERNAL_PROFILE = \r
+endif\r
+\r
+ifeq ($(PROFILE_$(CORE)), release)\r
+ CFLAGS_XDCINTERNAL += -Dxdc_target_name__=ARP32_far -Dxdc_target_types__=ti/targets/arp32/elf/std.h -Dxdc_bld__profile_release -Dxdc_bld__vers_1_0_4_6_1 -D_DEBUG_=0 -o2\r
+ ifndef MODULE_NAME\r
+ CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_CFG_BASE_FILE_NAME)_pearp32.h' \r
+ endif\r
+ LNKFLAGS_INTERNAL_PROFILE = -o2\r
+endif\r
+\r
+# For generic platform define GENERIC in CFLAGS\r
+ifeq ($(PLATFORM),generic)\r
+ CFLAGS_XDCINTERNAL += -DGENERIC\r
+endif\r
+\r
+# Following 'if...' block is for an application; to add a #define for each\r
+# component in the build. This is required to know - at compile time - which\r
+# components are on which core.\r
+ifndef MODULE_NAME\r
+ # Derive list of all packages from each of the components needed by the app\r
+ PKG_LIST_EVE_LOCAL = $(foreach COMP,$(COMP_LIST_$(CORE)),$($(COMP)_PKG_LIST))\r
+ \r
+ # Defines for the app and cfg source code to know which components/packages\r
+ # are included in the build for the local CORE...\r
+ CFLAGS_APP_DEFINES = $(foreach PKG,$(PKG_LIST_EVE_LOCAL),-D_LOCAL_$(PKG)_)\r
+ CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_EVE_LOCAL),-D_BUILD_$(PKG)_)\r
+ ifeq ($(CORE),eve)\r
+ PKG_LIST_EVE_REMOTE = $(foreach COMP,$(COMP_LIST_eve),$($(COMP)_PKG_LIST))\r
+ CFLAGS_APP_DEFINES += -D_LOCAL_CORE_EVE_\r
+ endif\r
+ \r
+ PKG_LIST_EVE_REMOTE = $(foreach COMP,$(COMP_LIST_eve),$($(COMP)_PKG_LIST))\r
+\r
+ # Defines for the app and cfg source code to know which components/packages\r
+ # are included in the build for the remote CORE...\r
+ CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_EVE_REMOTE),-D_REMOTE_$(PKG)_)\r
+ CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_EVE_REMOTE),-D_BUILD_$(PKG)_)\r
+endif\r
+\r
+# Assemble CFLAGS from all other CFLAGS definitions\r
+_CFLAGS = $(CFLAGS_INTERNAL) $(CFLAGS_GLOBAL_$(CORE)) $(CFLAGS_XDCINTERNAL) $(CFLAGS_LOCAL_COMMON) $(CFLAGS_LOCAL_$(CORE)) $(CFLAGS_LOCAL_$(PLATFORM)) $(CFLAGS_LOCAL_$(SOC)) $(CFLAGS_APP_DEFINES) $(CFLAGS_COMP_COMMON) $(CFLAGS_GLOBAL_$(PLATFORM))\r
+\r
+# Object file creation\r
+# The first $(CC) generates the dependency make files for each of the objects\r
+# The second $(CC) compiles the source to generate object\r
+$(OBJ_PATHS): $(OBJDIR)/%.$(OBJEXT): %.c\r
+ $(ECHO) \# Compiling $< to $@ ...\r
+ $(CC) -ppd=$(DEPFILE).P $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $<\r
+ $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $<\r
+\r
+# Archive flags - normally doesn't change\r
+ARFLAGS = rq\r
+\r
+# Archive/library file creation\r
+$(LIBDIR)/$(MODULE_NAME).$(LIBEXT) : $(OBJ_PATHS)\r
+ $(ECHO) \#\r
+ $(ECHO) \# Archiving $(OBJ_PATHS) into $@...\r
+ $(ECHO) \#\r
+ $(AR) $(ARFLAGS) $@ $(OBJ_PATHS)\r
+\r
+# Linker options and rules\r
+LNKFLAGS_INTERNAL_COMMON = -w -q -u _c_int00 --silicon_version=210 -c --rom_model\r
+\r
+# Assemble Linker flags from all other LNKFLAGS definitions\r
+_LNKFLAGS = $(LNKFLAGS_INTERNAL_COMMON) $(LNKFLAGS_INTERNAL_PROFILE) $(LNKFLAGS_GLOBAL_$(CORE)) $(LNKFLAGS_LOCAL_COMMON) $(LNKFLAGS_LOCAL_$(CORE)) \r
+\r
+# Path of the RTS library - normally doesn't change for a given tool-chain\r
+RTSLIB_PATH = $(CODEGEN_PATH_ARP32)/lib/rtsarp32_v200.lib\r
+LIB_PATHS += $(RTSLIB_PATH)\r
+\r
+LNK_LIBS = $(addprefix -l,$(LIB_PATHS))\r
+ifeq ($(DEST_ROOT),)\r
+ TMPOBJDIR = .\r
+else\r
+ TMPOBJDIR = $(OBJDIR)\r
+endif\r
+# Linker - to create executable file \r
+$(BINDIR)/$(APP_NAME)_$(CORE)_$(PROFILE_$(CORE)).$(EXEEXT) : $(OBJ_PATHS) $(LIB_PATHS) $(LNKCMD_FILE) $(OBJDIR)/$(CFG_COBJ_XDC)\r
+ $(ECHO) \# Linking into $@\r
+ $(ECHO) \#\r
+ cd $(TMPOBJDIR) && $(LNK) $(_LNKFLAGS) $(OBJ_PATHS) -l$(LNKCMD_FILE) sample_app/linker.cmd -o $@ -m $@.map $(LNK_LIBS)\r
+ $(ECHO) \#\r
+ $(ECHO) \# $@ created.\r
+ $(ECHO) \#\r
+\r
+ifeq ($(CONFIG_BLD_XDC_CUSTOM),)\r
+ CONFIG_BLD_FILE = $(CONFIG_BLD_XDC_$(ISA))\r
+else\r
+ CONFIG_BLD_FILE = $(CONFIG_BLD_XDC_CUSTOM)\r
+endif\r
+ifeq ($(PLATFORM_XDC_CUSTOM),)\r
+ PLATFORM_XDC_NAME = $(PLATFORM_XDC)\r
+else\r
+ PLATFORM_XDC_NAME = $(PLATFORM_XDC_CUSTOM)\r
+endif\r
+\r
+# XDC specific - assemble XDC-Configuro command\r
+#CONFIGURO_CMD = $(xdc_PATH)/xs xdc.tools.configuro --generationOnly -o $(CONFIGURO_DIR) -t $(TARGET_XDC) -p $(PLATFORM_XDC) \\r
+# $(CFGARGS_XDC) -r $(PROFILE_$(CORE)) -b $(CONFIG_BLD_XDC_$(ISA)) $(XDC_CFG_FILE_NAME)\r
+CONFIGURO_CMD = $(xdc_PATH)/xs xdc.tools.configuro --generationOnly -o $(CONFIGURO_DIR) -t $(TARGET_XDC) -p $(PLATFORM_XDC_NAME) \\r
+ -r $(PROFILE_$(CORE)) -c $(CODEGEN_PATH_ARP32) -b $(CONFIG_BLD_FILE) $(XDC_CFG_FILE_NAME) \r
+_XDC_GREP_STRING = \"$(XDC_GREP_STRING)\"\r
+EGREP_CMD = $(EGREP) -ivw $(XDC_GREP_STRING) $(XDCLNKCMD_FILE)\r
+\r
+ifneq ($(DEST_ROOT),)\r
+ DEST_ROOT += /\r
+endif\r
+# Invoke configuro for the rest of the components\r
+# NOTE: 1. String handling is having issues with various make versions when the \r
+# cammand is directly tried to be given below. Hence, as a work-around, \r
+# the command is re-directed to a file (shell or batch file) and then \r
+# executed\r
+# 2. The linker.cmd file generated, includes the libraries generated by\r
+# XDC. An egrep to search for these and omit in the .cmd file is added\r
+# after configuro is done\r
+#$(CFG_CFILE_XDC) : $(XDC_CFG_FILE)\r
+xdc_configuro : $(XDC_CFG_FILE) $(CONFIGURO_DIR)\r
+ $(ECHO) \# Invoking configuro...\r
+ $(ECHO) -e $(CONFIGURO_CMD) > $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+ifeq ($(OS),Windows_NT)\r
+ CACLS $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat /E /P Everyone:F\r
+ $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+else\r
+ $(CHMOD) a+x $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+ ./$(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+endif\r
+ $(CP) $(XDCLNKCMD_FILE) $(LNKCMD_FILE)\r
+# $(ECHO) @ $(EGREP_CMD) > maketemp_egrep_cmd.bat\r
+# ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)\r
+# $(EGREP_CMD) > $(LNKCMD_FILE)\r
+# $(EGREP) -iv "$(XDC_GREP_STRING)" $(XDCLNKCMD_FILE) > $(LNKCMD_FILE)\r
+ $(ECHO) \# Configuro done!\r
+\r
+$(LNKCMD_FILE) :\r
+# $(CP) $(XDCLNKCMD_FILE) $(LNKCMD_FILE)\r
+# $(ECHO) @ $(EGREP_CMD) > maketemp_egrep_cmd.bat\r
+# ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)\r
+# $(EGREP_CMD) > $(LNKCMD_FILE)\r
+ \r
+ifndef MODULE_NAME\r
+$(OBJDIR)/$(CFG_COBJ_XDC) : $(CFG_C_XDC)\r
+ $(ECHO) \# Compiling generated $< to $@ ...\r
+ $(CC) -ppd=$(DEPFILE).P $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $(CFG_C_XDC)\r
+ $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $(CFG_C_XDC)\r
+ $(CP) $(OBJDIR)/$(CFG_COBJ_XDC) $(CONFIGURO_DIR)/package/cfg/$(CFG_COBJ_XDC)\r
+endif\r
+\r
+# Include dependency make files that were generated by $(CC)\r
+-include $(SRCS:%.c=$(DEPDIR)/%.P)\r
+\r
+# Nothing beyond this point\r
diff --git a/packages/component.mk b/packages/component.mk
index 2e849b55925112f9dd66125ac21c7d020a88fdef..6adbf5f6dfd5c9ffcbaf7ed59cca798ef171b856 100755 (executable)
--- a/packages/component.mk
+++ b/packages/component.mk
endif
ifeq ($(TARGET),)
-TARGET = 674 m3 a8 64p 66 m4 a15
+TARGET = 674 m3 a8 64p 66 m4 a15 eve
edma3_lld_LIBS_ALL = edma3_lld_rm_generic
endif
@@ -242,4 +242,7 @@ edma3_drv_tda2xx-evm_a15_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_t
edma3_drv_tda2xx-evm_66_example_EXAMPLES_RELPATH = examples/edma3_driver/evmtda2xx
edma3_drv_tda2xx-evm_66_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda2xx-evm_66_example_EXAMPLES_RELPATH)
+edma3_drv_tda2xx-evm_eve_example_EXAMPLES_RELPATH = examples/edma3_driver/evmtda2xx_EVE
+edma3_drv_tda2xx-evm_eve_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda2xx-evm_eve_example_EXAMPLES_RELPATH)
+
# Nothing beyond this point
diff --git a/packages/makefile b/packages/makefile
index 30a738307ee28033054f15fa9ae73c2c325ee1c3..9e20dfd214425df7d386a549d8ee5f58ee23aa47 100755 (executable)
--- a/packages/makefile
+++ b/packages/makefile
$(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm_sample
$(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+#=======================================================================================================================================
+#To Build libs For Platform tda2xx-evm Target EVE
+edma3_lld_tda2xx-evm_eve_libs: edma3_lld_tda2xx-evm_eve_libs_drv edma3_lld_tda2xx-evm_eve_libs_rm edma3_lld_tda2xx-evm_eve_libs_drvsample edma3_lld_tda2xx-evm_eve_libs_rmsample
+edma3_lld_tda2xx-evm_eve_libs_drv:
+ifeq ($(FORMAT),ELF)
+ $(ECHO) \# Making eve:debug:edma3_lld_drv
+ $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+ $(ECHO) \# Making eve:release:edma3_lld_drv
+ $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+edma3_lld_tda2xx-evm_eve_libs_rm:
+ifeq ($(FORMAT),ELF)
+ $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm
+ $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+ $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm
+ $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+edma3_lld_tda2xx-evm_eve_libs_drvsample:
+ifeq ($(FORMAT),ELF)
+ $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_drv_sample
+ $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+ $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_drv_sample
+ $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+edma3_lld_tda2xx-evm_eve_libs_rmsample:
+ifeq ($(FORMAT),ELF)
+ $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm_sample
+ $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+ $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm_sample
+ $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+
+#To Clean libs For Platform tda2xx-evm Target eve
+edma3_lld_tda2xx-evm_eve_libs_clean: edma3_lld_tda2xx-evm_eve_libs_drv_clean edma3_lld_tda2xx-evm_eve_libs_rm_clean edma3_lld_tda2xx-evm_eve_libs_drvsample_clean edma3_lld_tda2xx-evm_eve_libs_rmsample_clean
+edma3_lld_tda2xx-evm_eve_libs_drv_clean:
+ $(ECHO) \# Cleaning eve:debug:edma3_lld_drv
+ $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+ $(ECHO) \# Cleaning eve:release:edma3_lld_drv
+ $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+edma3_lld_tda2xx-evm_eve_libs_rm_clean:
+ $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm
+ $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+ $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm
+ $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+edma3_lld_tda2xx-evm_eve_libs_drvsample_clean:
+ $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_drv_sample
+ $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+ $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_drv_sample
+ $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+edma3_lld_tda2xx-evm_eve_libs_rmsample_clean:
+ $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm_sample
+ $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+ $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm_sample
+ $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+
#=======================================================================================================================================
#To Build libs For Platform ti816x-evm Target 674
edma3_lld_ti816x-evm_674_libs: edma3_lld_ti816x-evm_674_libs_drv edma3_lld_ti816x-evm_674_libs_rm edma3_lld_ti816x-evm_674_libs_drvsample edma3_lld_ti816x-evm_674_libs_rmsample
$(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
endif
+edma3_drv_tda2xx-evm_eve_example:
+ifeq ($(FORMAT),ELF)
+ $(ECHO) \# Configuring XDC packages for $@:eve:debug $($@_EXAMPLES_PATH)
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+ $(ECHO) \# Making example $@:debug
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+
+ $(ECHO) \# Configuring XDC packages for $@:eve:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+ $(ECHO) \# Making example $@:release
+ $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+
+
#=======================================================================================================================================
#
# Rule to clean all examples
$(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
endif
+edma3_drv_tda2xx-evm_eve_example_clean:
+ifeq ($(FORMAT),ELF)
+ $(ECHO) \# Cleaning example $@:debug
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=debug
+ $(ECHO) \# Cleaning example $@:release
+ $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean PLATFORM=tda2xx-evm CORE=eve PROFILE_eve=release
+endif
+
edma3_drv_ti816x-evm_m3_example_clean:
ifeq ($(FORMAT),ELF)
$(ECHO) \# Cleaning example $@:debug
index cdfbef14bc5f4b25d7fab58be67bcc1cfde4072e..8a20dc67be96d5829f49338394bd9fdfc6f92c80 100755 (executable)
SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_arm_int_reg.c
SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_arm_int_reg.c
endif
+
ifeq ($(CORE),m3video)
CFLAGS_LOCAL_ti816x-evm = -DBUILD_NETRA_M3VIDEO
CFLAGS_LOCAL_ti814x-evm = -DBUILD_CENTAURUS_M3VIDEO
SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_arm_int_reg.c
SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_arm_int_reg.c
endif
+
ifeq ($(CORE),m3vpss)
CFLAGS_LOCAL_ti816x-evm = -DBUILD_NETRA_M3VPSS
CFLAGS_LOCAL_ti814x-evm = -DBUILD_CENTAURUS_M3VPSS
SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_arm_int_reg.c
SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_arm_int_reg.c
endif
+
ifeq ($(CORE),m4)
CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_IPU
endif
+
ifeq ($(CORE),a15host)
CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_MPU
endif
+
+ifeq ($(CORE),eve)
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_EVE
+endif
+
SRCS_c6748-evm = sample_c6748_cfg.c sample_c6748_int_reg.c
SRCS_da830-evm = sample_da830_cfg.c sample_da830_int_reg.c
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c
index 1fcf3c487874ee935462679ca2826c8df7dc92dc..b12b62948b869cae2331ce2bc5ebf096abaebc63 100644 (file)
{\r
static UInt32 cookie = 0;\r
unsigned int numTc = 0;\r
- \r
- IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);\r
- IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);\r
- IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);\r
- IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);\r
- \r
+\r
+ /*\r
+ * Skip these interrupt xbar configuration.\r
+ * if it is accessing EVE internal edma instance ie edma3id = 2 and dsp_num = 1.\r
+ */\r
+ if (edma3Id != 2 && dsp_num != 1)\r
+ {\r
+ IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);\r
+ IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);\r
+ IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);\r
+ IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);\r
+ }\r
+\r
Hwi_Params hwiParams; \r
Error_Block eb;\r
\r
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c
index eb4007698522a5a45ea10e319664cea8d423785d..24c35e29032ca43c7ebcdf93786ce3797a6b81a2 100644 (file)
#endif\r
\r
/* Number of EDMA3 controllers present in the system */\r
-#define NUM_EDMA3_INSTANCES 2u\r
+#define NUM_EDMA3_INSTANCES 3u\r
const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
\r
/* Number of DSPs present in the system */\r
\r
unsigned short determineProcId()\r
{\r
-unsigned short regionNo = numEdma3Instances;\r
+ unsigned short regionNo = numEdma3Instances;\r
#ifdef BUILD_TDA2XX_DSP\r
-extern __cregister volatile unsigned int DNUM;\r
+ extern __cregister volatile unsigned int DNUM;\r
#endif\r
-myCoreNum = numDsps;\r
-#ifdef BUILD_TDA2XX_MPU\r
\r
+ myCoreNum = numDsps;\r
+\r
+#ifdef BUILD_TDA2XX_MPU\r
asm (" push {r0-r2} \n\t"\r
" MRC p15, 0, r0, c0, c0, 5\n\t"\r
" LDR r1, =myCoreNum\n\t"\r
else\r
regionNo = 0;\r
#elif defined(BUILD_TDA2XX_IPU)\r
-myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
-if(Core_getIpuId() == 1){\r
- if(myCoreNum == CORE_ID_C0)\r
- regionNo = 4;\r
- else if (myCoreNum == CORE_ID_C1)\r
- regionNo = 5;\r
-}\r
-if(Core_getIpuId() == 2){\r
- if(myCoreNum == CORE_ID_C0)\r
- regionNo = 6;\r
- else if (myCoreNum == CORE_ID_C1)\r
- regionNo = 7;\r
-}\r
-#elif defined BUILD_TDA2XX_DSP\r
+ myCoreNum = (*(unsigned int *)(PID0_ADDRESS));\r
+ if(Core_getIpuId() == 1){\r
+ if(myCoreNum == CORE_ID_C0)\r
+ regionNo = 4;\r
+ else if (myCoreNum == CORE_ID_C1)\r
+ regionNo = 5;\r
+ }\r
+ if(Core_getIpuId() == 2){\r
+ if(myCoreNum == CORE_ID_C0)\r
+ regionNo = 6;\r
+ else if (myCoreNum == CORE_ID_C1)\r
+ regionNo = 7;\r
+ }\r
+#elif defined(BUILD_TDA2XX_DSP)\r
\r
myCoreNum = DNUM;\r
if(myCoreNum == 0)\r
regionNo = 2;\r
else\r
regionNo = 3;\r
+#elif defined(BUILD_TDA2XX_EVE)\r
+ regionNo = 1;\r
#endif\r
return regionNo;\r
}\r
/** Interrupt no. for Transfer Completion */\r
#define EDMA3_CC_XFER_COMPLETION_INT_A15 (66u)\r
#define EDMA3_CC_XFER_COMPLETION_INT_DSP (38u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34u)\r
-#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C0 (34u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU_C1 (33u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_EVE (8u)\r
+\r
/** Based on the interrupt number to be mapped define the XBAR instance number */\r
#define COMPLETION_INT_A15_XBAR_INST_NO (29u)\r
#define COMPLETION_INT_DSP_XBAR_INST_NO (7u)\r
-#define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12u)\r
-#define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11u)\r
+#define COMPLETION_INT_IPU_C0_XBAR_INST_NO (12u)\r
+#define COMPLETION_INT_IPU_C1_XBAR_INST_NO (11u)\r
\r
/** Interrupt no. for CC Error */\r
#define EDMA3_CC_ERROR_INT_A15 (67u)\r
#define EDMA3_CC_ERROR_INT_DSP (39u)\r
-#define EDMA3_CC_ERROR_INT_IPU (35u)\r
+#define EDMA3_CC_ERROR_INT_IPU (35u)\r
+#define EDMA3_CC_ERROR_INT_EVE (23u)\r
\r
/** Based on the interrupt number to be mapped define the XBAR instance number */\r
#define CC_ERROR_INT_A15_XBAR_INST_NO (30u)\r
#define CC_ERROR_INT_DSP_XBAR_INST_NO (8u)\r
-#define CC_ERROR_INT_IPU_XBAR_INST_NO (13u)\r
+#define CC_ERROR_INT_IPU_XBAR_INST_NO (13u)\r
\r
/** Interrupt no. for TCs Error */\r
#define EDMA3_TC0_ERROR_INT_A15 (68u)\r
#define EDMA3_TC0_ERROR_INT_DSP (40u)\r
-#define EDMA3_TC0_ERROR_INT_IPU (36u)\r
+#define EDMA3_TC0_ERROR_INT_IPU (36u)\r
+#define EDMA3_TC0_ERROR_INT_EVE (24u)\r
#define EDMA3_TC1_ERROR_INT_A15 (69u)\r
#define EDMA3_TC1_ERROR_INT_DSP (41u)\r
-#define EDMA3_TC1_ERROR_INT_IPU (37u)\r
+#define EDMA3_TC1_ERROR_INT_IPU (37u)\r
+#define EDMA3_TC1_ERROR_INT_EVE (25u)\r
+\r
/** Based on the interrupt number to be mapped define the XBAR instance number */\r
#define TC0_ERROR_INT_A15_XBAR_INST_NO (31u)\r
-#define TC0_ERROR_INT_DSP_XBAR_INST_NO (9u)\r
-#define TC0_ERROR_INT_IPU_XBAR_INST_NO (14u)\r
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO (9u) \r
+#define TC0_ERROR_INT_IPU_XBAR_INST_NO (14u)\r
#define TC1_ERROR_INT_A15_XBAR_INST_NO (32u)\r
#define TC1_ERROR_INT_DSP_XBAR_INST_NO (10u)\r
-#define TC1_ERROR_INT_IPU_XBAR_INST_NO (15u)\r
+#define TC1_ERROR_INT_IPU_XBAR_INST_NO (15u)\r
\r
#ifdef BUILD_TDA2XX_MPU\r
#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15\r
#define TC0_ERROR_INT_XBAR_INST_NO TC0_ERROR_INT_IPU_XBAR_INST_NO\r
#define TC1_ERROR_INT_XBAR_INST_NO TC1_ERROR_INT_IPU_XBAR_INST_NO\r
\r
+#elif defined BUILD_TDA2XX_EVE\r
+#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_EVE\r
+#define EDMA3_CC_ERROR_INT EDMA3_CC_ERROR_INT_EVE\r
+#define EDMA3_TC0_ERROR_INT EDMA3_TC0_ERROR_INT_EVE\r
+#define EDMA3_TC1_ERROR_INT EDMA3_TC1_ERROR_INT_EVE\r
+/* For accessing EVE internal edma, there is no need to configure Xbar */\r
+#define CC_ERROR_INT_XBAR_INST_NO 0u\r
+#define TC0_ERROR_INT_XBAR_INST_NO 0u\r
+#define TC1_ERROR_INT_XBAR_INST_NO 0u\r
+\r
#else\r
#define EDMA3_CC_XFER_COMPLETION_INT (0u)\r
#define EDMA3_CC_ERROR_INT (0u)\r
* various peripherals, which use EDMA for data transfer.\r
* All channels need not be mapped, some can be free also.\r
* 1: Mapped\r
- * 0: Not mapped\r
+ * 0: Not mapped (channel available)\r
*\r
* This mapping will be used to allocate DMA channels when user passes\r
* EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
/* 31 0 */\r
#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA (0x3FC0C06Eu) /* TBD */\r
#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA (0x000FFFFFu) /* TBD */\r
-\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA (0x00000000u) /* TBD */\r
\r
/**\r
* \brief Mapping of DMA channels 32-63 to Hardware Events from\r
* various peripherals, which use EDMA for data transfer.\r
* All channels need not be mapped, some can be free also.\r
* 1: Mapped\r
- * 0: Not mapped\r
+ * 0: Not mapped (channel available)\r
*\r
* This mapping will be used to allocate DMA channels when user passes\r
* EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
*/\r
#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA (0xF3FFFFFCu) /* TBD */\r
#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA (0x00000000u) /* TBD */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA (0x00000000u) /* TBD */\r
\r
\r
/* Variable which will be used internally for referring number of Event Queues*/\r
/* Variable which will be used internally for referring number of TCs. */\r
unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {\r
EDMA3_NUM_TC,\r
+ EDMA3_NUM_TC,\r
+ EDMA3_NUM_TC\r
};\r
\r
/**\r
*/\r
unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
+ /* EDMA3 INSTANCE# 0 */\r
{\r
- EDMA3_CC_XFER_COMPLETION_INT_A15, EDMA3_CC_XFER_COMPLETION_INT_A15,\r
- EDMA3_CC_XFER_COMPLETION_INT_DSP, EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
- EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
- EDMA3_CC_XFER_COMPLETION_INT_IPU_C0, EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
+ EDMA3_CC_XFER_COMPLETION_INT_A15,\r
+ EDMA3_CC_XFER_COMPLETION_INT_A15,\r
+ EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
+ EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
+ EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
+ EDMA3_CC_XFER_COMPLETION_INT_IPU_C1,\r
+ EDMA3_CC_XFER_COMPLETION_INT_IPU_C0,\r
+ EDMA3_CC_XFER_COMPLETION_INT_IPU_C1\r
},\r
+ /* EDMA3 INSTANCE# 1 */\r
{\r
- 0u, 0u, DSP1_EDMA3_CC_XFER_COMPLETION_INT, DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
- 0u, 0u, 0u, 0u,\r
+ 0u,\r
+ 0u,\r
+ DSP1_EDMA3_CC_XFER_COMPLETION_INT,\r
+ DSP2_EDMA3_CC_XFER_COMPLETION_INT,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u\r
},\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ 0u,\r
+ /* Region 1 (Associated to EVE core)*/\r
+ EDMA3_CC_XFER_COMPLETION_INT_EVE,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ }\r
};\r
/** These are the Xbar instance numbers corresponding to interrupt numbers */\r
unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ COMPLETION_INT_A15_XBAR_INST_NO,\r
+ COMPLETION_INT_A15_XBAR_INST_NO,\r
+ COMPLETION_INT_DSP_XBAR_INST_NO,\r
+ COMPLETION_INT_DSP_XBAR_INST_NO,\r
+ COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
+ COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
+ COMPLETION_INT_IPU_C0_XBAR_INST_NO,\r
+ COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
{\r
- COMPLETION_INT_A15_XBAR_INST_NO, COMPLETION_INT_A15_XBAR_INST_NO,\r
- COMPLETION_INT_DSP_XBAR_INST_NO, COMPLETION_INT_DSP_XBAR_INST_NO,\r
- COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
- COMPLETION_INT_IPU_C0_XBAR_INST_NO, COMPLETION_INT_IPU_C1_XBAR_INST_NO,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u\r
},\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ /* \r
+ * For accessing EVE internal edma,\r
+ * there is no need to configure Xbar.\r
+ * So getting to zero.\r
+ */\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u\r
+ }\r
};\r
\r
/** These are the Interrupt Crossbar Index For EDMA Completion for different regions */\r
unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
+ /* EDMA3 INSTANCE# 0 */\r
{\r
- XBAR_EDMA_TPCC_IRQ_REGION0, XBAR_EDMA_TPCC_IRQ_REGION1, XBAR_EDMA_TPCC_IRQ_REGION2, XBAR_EDMA_TPCC_IRQ_REGION3,\r
- XBAR_EDMA_TPCC_IRQ_REGION4, XBAR_EDMA_TPCC_IRQ_REGION5, XBAR_EDMA_TPCC_IRQ_REGION6, XBAR_EDMA_TPCC_IRQ_REGION7,\r
+ XBAR_EDMA_TPCC_IRQ_REGION0,\r
+ XBAR_EDMA_TPCC_IRQ_REGION1,\r
+ XBAR_EDMA_TPCC_IRQ_REGION2,\r
+ XBAR_EDMA_TPCC_IRQ_REGION3,\r
+ XBAR_EDMA_TPCC_IRQ_REGION4,\r
+ XBAR_EDMA_TPCC_IRQ_REGION5,\r
+ XBAR_EDMA_TPCC_IRQ_REGION6,\r
+ XBAR_EDMA_TPCC_IRQ_REGION7\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ XBAR_EDMA_TPCC_IRQ_REGION0,\r
+ XBAR_EDMA_TPCC_IRQ_REGION1,\r
+ XBAR_EDMA_TPCC_IRQ_REGION2,\r
+ XBAR_EDMA_TPCC_IRQ_REGION3,\r
+ XBAR_EDMA_TPCC_IRQ_REGION4,\r
+ XBAR_EDMA_TPCC_IRQ_REGION5,\r
+ XBAR_EDMA_TPCC_IRQ_REGION6,\r
+ XBAR_EDMA_TPCC_IRQ_REGION7\r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ /* \r
+ * For accessing EVE internal edma,\r
+ * there is no need to configure Xbar.\r
+ * So getting to zero.\r
+ */\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u\r
}\r
};\r
\r
* Variable which will be used internally for referring channel controller's\r
* error interrupt.\r
*/\r
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
- EDMA3_CC_ERROR_INT,DSP1_EDMA3_CC_ERROR_INT,\r
- };\r
-unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] = {\r
- CC_ERROR_INT_XBAR_INST_NO,\r
- };\r
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = \r
+{\r
+ EDMA3_CC_ERROR_INT,\r
+ DSP1_EDMA3_CC_ERROR_INT,\r
+ EDMA3_CC_ERROR_INT\r
+};\r
+unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] =\r
+{\r
+ CC_ERROR_INT_XBAR_INST_NO,\r
+ CC_ERROR_INT_XBAR_INST_NO,\r
+ CC_ERROR_INT_XBAR_INST_NO\r
+};\r
unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
{\r
XBAR_EDMA_TPCC_IRQ_ERR,\r
+ XBAR_EDMA_TPCC_IRQ_ERR,\r
+ XBAR_EDMA_TPCC_IRQ_ERR\r
};\r
\r
/**\r
* Variable which will be used internally for referring transfer controllers'\r
* error interrupts.\r
*/\r
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
- {\r
- EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
- EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
- EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
- EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
- },\r
- {\r
- EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
- EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
- EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
- DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
- }\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+ EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+ DSP1_EDMA3_TC0_ERROR_INT, DSP1_EDMA3_TC1_ERROR_INT,\r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
+ EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+ EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+ EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
+ }\r
};\r
-unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][8] =\r
+unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
- {\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
+ 0u, 0u,\r
+ 0u, 0u,\r
+ 0u, 0u,\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
+ 0u, 0u,\r
+ 0u, 0u,\r
+ 0u, 0u,\r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
0u, 0u,\r
0u, 0u,\r
0u, 0u,\r
- }\r
+ }\r
};\r
\r
-unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][8] =\r
+unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
- {\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
+ 0u, 0u,\r
+ 0u, 0u, 0u, 0u,\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
+ 0u, 0u,\r
+ 0u, 0u, 0u, 0u,\r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC1_IRQ_ERR,\r
- 0u, 0u,\r
+ 0u, 0u,\r
0u, 0u, 0u, 0u,\r
- }\r
+ }\r
};\r
\r
\r
* Variables which will be used internally for referring the hardware interrupt\r
* for various EDMA3 interrupts.\r
*/\r
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
- EDMA3_HWI_INT_XFER_COMP, EDMA3_HWI_INT_XFER_COMP,\r
- };\r
-\r
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
- EDMA3_HWI_INT_CC_ERR, EDMA3_HWI_INT_CC_ERR,\r
- };\r
-\r
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
- {\r
- EDMA3_HWI_INT_TC0_ERR,\r
- EDMA3_HWI_INT_TC1_ERR,\r
- EDMA3_HWI_INT_TC2_ERR,\r
- EDMA3_HWI_INT_TC3_ERR\r
- },\r
- {\r
- EDMA3_HWI_INT_TC0_ERR,\r
- EDMA3_HWI_INT_TC1_ERR,\r
- EDMA3_HWI_INT_TC2_ERR,\r
- EDMA3_HWI_INT_TC3_ERR\r
- }\r
- };\r
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] =\r
+{\r
+ EDMA3_HWI_INT_XFER_COMP,\r
+ EDMA3_HWI_INT_XFER_COMP,\r
+ EDMA3_CC_XFER_COMPLETION_INT\r
+};\r
+\r
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] =\r
+{\r
+ EDMA3_HWI_INT_CC_ERR,\r
+ EDMA3_HWI_INT_CC_ERR,\r
+ EDMA3_CC_ERROR_INT\r
+};\r
+\r
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ EDMA3_HWI_INT_TC0_ERR,\r
+ EDMA3_HWI_INT_TC1_ERR,\r
+ EDMA3_HWI_INT_TC2_ERR,\r
+ EDMA3_HWI_INT_TC3_ERR\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ {\r
+ EDMA3_HWI_INT_TC0_ERR,\r
+ EDMA3_HWI_INT_TC1_ERR,\r
+ EDMA3_HWI_INT_TC2_ERR,\r
+ EDMA3_HWI_INT_TC3_ERR\r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ {\r
+ EDMA3_TC0_ERROR_INT,\r
+ EDMA3_TC1_ERROR_INT,\r
+ EDMA3_TC2_ERROR_INT,\r
+ EDMA3_TC3_ERROR_INT\r
+ }\r
+};\r
\r
/**\r
* \brief Base address as seen from the different cores may be different\r
#define EDMA3_CC_BASE_ADDR ((void *)(0x63300000))\r
#define EDMA3_TC0_BASE_ADDR ((void *)(0x63400000))\r
#define EDMA3_TC1_BASE_ADDR ((void *)(0x63500000))\r
+#elif (defined BUILD_TDA2XX_EVE)\r
+#define EDMA3_CC_BASE_ADDR ((void *)(0x400A0000))\r
+#define EDMA3_TC0_BASE_ADDR ((void *)(0x40086000))\r
+#define EDMA3_TC1_BASE_ADDR ((void *)(0x40087000))\r
#else\r
#define EDMA3_CC_BASE_ADDR ((void *)(0x0))\r
#define EDMA3_TC0_BASE_ADDR ((void *)(0x0))\r
EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA\r
}\r
},\r
-};\r
-\r
-/**\r
- * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
- * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
- * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
- * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
- *\r
- * Only Resources owned by a perticular core are allocated by Driver\r
- * Reserved resources are not allocated if requested for any available resource\r
- */\r
- \r
-/* Driver Instance Initialization Configuration */\r
-EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
{\r
- /* EDMA3 INSTANCE# 0 */\r
- {\r
- /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
+ /* EDMA3 INSTANCE# 2 */\r
+ /** Total number of DMA Channels supported by the EDMA3 Controller */\r
+ EDMA3_NUM_DMA_CHANNELS,\r
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
+ EDMA3_NUM_QDMA_CHANNELS,\r
+ /** Total number of TCCs supported by the EDMA3 Controller */\r
+ EDMA3_NUM_TCC,\r
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
+ EDMA3_NUM_PARAMSET,\r
+ /** Total number of Event Queues in the EDMA3 Controller */\r
+ EDMA3_NUM_EVTQUE,\r
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
+ EDMA3_NUM_TC,\r
+ /** Number of Regions on this EDMA3 controller */\r
+ EDMA3_NUM_REGIONS,\r
+\r
+ /**\r
+ * \brief Channel mapping existence\r
+ * A value of 0 (No channel mapping) implies that there is fixed association\r
+ * for a channel number to a parameter entry number or, in other words,\r
+ * PaRAM entry n corresponds to channel n.\r
+ */\r
+ 1u,\r
+\r
+ /** Existence of memory protection feature */\r
+ 0u,\r
+\r
+ /** Global Register Region of CC Registers */\r
+ EDMA3_CC_BASE_ADDR,\r
+ /** Transfer Controller (TC) Registers */\r
+ {\r
+ EDMA3_TC0_BASE_ADDR,\r
+ EDMA3_TC1_BASE_ADDR,\r
+ (void *)NULL,\r
+ (void *)NULL,\r
+ (void *)NULL,\r
+ (void *)NULL,\r
+ (void *)NULL,\r
+ (void *)NULL\r
+ },\r
+ /** Interrupt no. for Transfer Completion */\r
+ EDMA3_CC_XFER_COMPLETION_INT,\r
+ /** Interrupt no. for CC Error */\r
+ EDMA3_CC_ERROR_INT,\r
+ /** Interrupt no. for TCs Error */\r
+ {\r
+ EDMA3_TC0_ERROR_INT,\r
+ EDMA3_TC1_ERROR_INT,\r
+ EDMA3_TC2_ERROR_INT,\r
+ EDMA3_TC3_ERROR_INT,\r
+ EDMA3_TC4_ERROR_INT,\r
+ EDMA3_TC5_ERROR_INT,\r
+ EDMA3_TC6_ERROR_INT,\r
+ EDMA3_TC7_ERROR_INT\r
+ },\r
+\r
+ /**\r
+ * \brief EDMA3 TC priority setting\r
+ *\r
+ * User can program the priority of the Event Queues\r
+ * at a system-wide level. This means that the user can set the\r
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+ * relative to IO initiated by the other bus masters on the\r
+ * device (ARM, DSP, USB, etc)\r
+ */\r
+ {\r
+ 0u,\r
+ 1u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u\r
+ },\r
+ /**\r
+ * \brief To Configure the Threshold level of number of events\r
+ * that can be queued up in the Event queues. EDMA3CC error register\r
+ * (CCERR) will indicate whether or not at any instant of time the\r
+ * number of events queued up in any of the event queues exceeds\r
+ * or equals the threshold/watermark value that is set\r
+ * in the queue watermark threshold register (QWMTHRA).\r
+ */\r
+ {\r
+ 16u,\r
+ 16u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u\r
+ },\r
+\r
+ /**\r
+ * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+ * An optimally-sized command is defined by the transfer controller\r
+ * default burst size (DBS). Different TCs can have different\r
+ * DBS values. It is defined in Bytes.\r
+ */\r
+ {\r
+ 16u,\r
+ 16u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u\r
+ },\r
+\r
+ /**\r
+ * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+ * if it exists, otherwise of no use.\r
+ */\r
+ {\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
+ },\r
+\r
+ /**\r
+ * \brief Mapping from each DMA channel to a TCC. This specific\r
+ * TCC code will be returned when the transfer is completed\r
+ * on the mapped channel.\r
+ */\r
+ {\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+ },\r
+\r
+ /**\r
+ * \brief Mapping of DMA channels to Hardware Events from\r
+ * various peripherals, which use EDMA for data transfer.\r
+ * All channels need not be mapped, some can be free also.\r
+ */\r
+ {\r
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA,\r
+ EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA\r
+ }\r
+ },\r
+\r
+};\r
+\r
+/**\r
+ * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
+ * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
+ * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
+ * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
+ *\r
+ * Only Resources owned by a perticular core are allocated by Driver\r
+ * Reserved resources are not allocated if requested for any available resource\r
+ */\r
+ \r
+/* Driver Instance Initialization Configuration */\r
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+ {\r
+ /* EDMA3 INSTANCE# 0 */\r
+ {\r
+ /* Resources owned/reserved by region 0 (Associated to MPU core 0)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFu},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00u},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00u, 0x00u},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+/* \r
+ * This instance 0 and region 1 is only accessible to MPU core 1.\r
+ * So other cores should not be access.\r
+ */\r
+#ifdef BUILD_TDA2XX_MPU\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+#else\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0x00000000u, 0x00000000u},\r
+#endif\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFu},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00u},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00u, 0x00u},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFu},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00u},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00u, 0x00u},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFu},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00u},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00u, 0x00u},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFu},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00u},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00u, 0x00u},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x000000FFu},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00u},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00u, 0x00u},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
@@ -887,7 +1540,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
{0x00u, 0x00u},\r
},\r
\r
- /* Resources owned/reserved by region 1 (Associated to MPU core 1) */\r
+ /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
@@ -933,34 +1586,36 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
/* 31 0 63 32 */\r
{0x00u, 0x00u},\r
},\r
-\r
- /* Resources owned/reserved by region 2 (Associated to any DSP1)*/\r
+ },\r
+ /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
+ {\r
+ /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000u},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 159 128 191 160 223 192 255 224 */\r
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
@@ -970,44 +1625,44 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000u},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000u, 0x00000000u},\r
},\r
\r
- /* Resources owned/reserved by region 3 (Associated to any DSP2)*/\r
+ /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000u},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 159 128 191 160 223 192 255 224 */\r
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
@@ -1017,18 +1672,18 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000u},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000u, 0x00000000u},\r
},\r
\r
- /* Resources owned/reserved by region 4 (Associated to any IPU1 core 0)*/\r
+ /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
@@ -1064,7 +1719,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
@@ -1075,7 +1730,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
{0x00u, 0x00u},\r
},\r
\r
- /* Resources owned/reserved by region 5 (Associated to any IPU1 core 1)*/\r
+ /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
@@ -1111,7 +1766,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
@@ -1122,33 +1777,33 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
{0x00u, 0x00u},\r
},\r
\r
- /* Resources owned/reserved by region 6 (Associated to any IPU2 core 0)*/\r
+ /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000u},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 159 128 191 160 223 192 255 224 */\r
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
@@ -1158,44 +1813,44 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000u},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000u, 0x00000000u},\r
},\r
\r
- /* Resources owned/reserved by region 7 (Associated to any IPU2 core 1)*/\r
+ /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000u},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 159 128 191 160 223 192 255 224 */\r
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
@@ -1205,20 +1860,18 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_STSTEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_STSTEDMA},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000u},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000u, 0x00000000u},\r
},\r
- },\r
- /* EDMA3 INSTANCE# 1 DSP1 EDMA*/\r
- {\r
- /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
+\r
+ /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
@@ -1265,7 +1918,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
{0x00000000u, 0x00000000u},\r
},\r
\r
- /* Resources owned/reserved by region 1 (Not Associated to any core supported) */\r
+ /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
@@ -1311,18 +1964,67 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
/* 31 0 63 32 */\r
{0x00000000u, 0x00000000u},\r
},\r
+ },\r
+ /* EDMA3 INSTANCE# 2 EVE EDMA*/\r
+ {\r
+ /* Resources owned/reserved by region 0 (Not Associated to any core supported)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
\r
- /* Resources owned/reserved by region 2 (Associated to any DSP core 0)*/\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0x00000000u, 0x00000000u},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00000000u},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00000000u, 0x00000000u},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0x00000000u, 0x00000000u},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00000000u},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00000000u, 0x00000000u},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 1 (Associated to any EVE core)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
{0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
@@ -1348,7 +2050,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
+ {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_EVEEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_EVEEDMA},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
@@ -1359,33 +2061,33 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
{0x00u, 0x00u},\r
},\r
\r
- /* Resources owned/reserved by region 3 (Associated to any DSP core 1)*/\r
+ /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/\r
{\r
/* ownPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 159 128 191 160 223 192 255 224 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 415 384 447 416 479 448 511 480 */\r
- 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
\r
/* ownDmaChannels */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* ownQdmaChannels */\r
/* 31 0 */\r
- {0x000000FFu},\r
+ {0x00000000u},\r
\r
/* ownTccs */\r
/* 31 0 63 32 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* resvdPaRAMSets */\r
/* 31 0 63 32 95 64 127 96 */\r
- {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 159 128 191 160 223 192 255 224 */\r
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
/* 287 256 319 288 351 320 383 352 */\r
@@ -1395,15 +2097,62 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
\r
/* resvdDmaChannels */\r
/* 31 0 63 32 */\r
- {EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0_DSPEDMA, EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1_DSPEDMA},\r
+ {0x00000000u, 0x00000000u},\r
\r
/* resvdQdmaChannels */\r
/* 31 0 */\r
- {0x00u},\r
+ {0x00000000u},\r
\r
/* resvdTccs */\r
/* 31 0 63 32 */\r
- {0x00u, 0x00u},\r
+ {0x00000000u, 0x00000000u},\r
+ },\r
+\r
+ /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/\r
+ {\r
+ /* ownPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+ /* ownDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0x00000000u, 0x00000000u},\r
+\r
+ /* ownQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00000000u},\r
+\r
+ /* ownTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00000000u, 0x00000000u},\r
+\r
+ /* resvdPaRAMSets */\r
+ /* 31 0 63 32 95 64 127 96 */\r
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 159 128 191 160 223 192 255 224 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 287 256 319 288 351 320 383 352 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+ /* 415 384 447 416 479 448 511 480 */\r
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+ /* resvdDmaChannels */\r
+ /* 31 0 63 32 */\r
+ {0x00000000u, 0x00000000u},\r
+\r
+ /* resvdQdmaChannels */\r
+ /* 31 0 */\r
+ {0x00000000u},\r
+\r
+ /* resvdTccs */\r
+ /* 31 0 63 32 */\r
+ {0x00000000u, 0x00000000u},\r
},\r
\r
/* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
@@ -1594,7 +2343,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
{0x00000000u, 0x00000000u},\r
},\r
},\r
- };\r
+};\r
\r
/* Driver Instance Cross bar event to channel map Initialization Configuration */\r
EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r