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raw | patch | inline | side by side (parent: 60ea15d)
| author | Vinay K Nooji <x0101786@ti.com> | |
| Tue, 7 Sep 2010 11:10:50 +0000 (16:40 +0530) | ||
| committer | Sundaram Raju <sundaram@ti.com> | |
| Tue, 7 Sep 2010 23:48:41 +0000 (05:18 +0530) |
- Modified the DRV and RM source files for adding support for cross bar mapped events.
Signed-off-by: Sundaram Raju <sundaram@ti.com>
Signed-off-by: Sundaram Raju <sundaram@ti.com>
index 3e595cb24f8d04a8b2f6254a30cd3db33584a78f..368f1a3fab8e6682fa8d9a164fc1dfe6a3d6ed1b 100755 (executable)
unsigned int linkCh,
unsigned int tcc);
+#define EDMA3_DRV_MAX_XBAR_EVENTS (31u)
+
+/**\struct EDMA3_DRV_GblXbarToChanConfigParams
+ * \brief Init-time Configuration structure for EDMA3
+ * controller, to provide Global SoC specific Information.
+ *
+ * This configuration structure is used to specify the EDMA3 Driver
+ * global settings, specific to the SoC.
+ * This configuraion structure provides the details of the mapping of cross bar
+ * events to available channels.
+ * This configuration information is SoC specific and could be provided by the
+ * user at run-time while creating the EDMA3 Driver Object, using API
+ * EDMA3_DRV_initXbarEventMap. In case user doesn't provide it,
+ * this information could be taken from the SoC specific configuration
+ * file edma3_<SOC_NAME>_cfg.c, incase it is available.
+ */
+typedef struct {
+ /**
+ * \brief Mapping from DMA channels to Hardware Events
+ *
+ * Each element in this array corresponds to one cross bar event and tells
+ * whether this event is mapped to any DMA channel. That is whether any
+ * free or unused DMA channel can be mapped to this event.
+ * -1 means the cross bar event is not mapped to any DMA channel;
+ * Any number from 0 to 63 means this event is mapped to specified channel.
+ * All channels need not be mapped, some can be free also.
+ * For the cross bar event mapped to DMA channel, appropriate Control Config
+ * register of TPCC event mux register should be configured.
+ */
+ int dmaMapXbarToChan [EDMA3_DRV_MAX_XBAR_EVENTS];
+ } EDMA3_DRV_GblXbarToChanConfigParams;
+
+
+/**
+ * \brief Associates cross bar mapped event to channel
+ *
+ * This function have to be defined in the configuration file.
+ * This function will be called only if the channel requested for is beyond the
+ * maximum number of channels.
+ * This function should read from the global cross bar mapped configuration
+ * data structure and return the mapped channel number to this event.
+ *
+ * \param eventNum [IN] Event number
+ * \param chanNum [IN/OUT]Return the channel number to which the
+ * request event is mapped to.
+ * \param edmaGblXbarConfig [IN] This is the configuration data structure
+ * for mapping the events to the channel
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note This function is re-entrant for unique event values. It is
+ * non-re-entrant for same event values.
+ */
+typedef EDMA3_DRV_Result (*EDMA3_DRV_mapXbarEvtToChan) (unsigned int eventNum,
+ unsigned int *chanNum,
+ const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
+
+/**
+ * \brief Writes to the cross bar mapped event to channel to system
+ * configuration register
+ *
+ * This function have to be defined in the configuration file.
+ * This function will be called only if the event number requested for is
+ * beyond the maximum number of channels and if any channel is allocated to this
+ * event.
+ * This function should read the cross bar mapped event number and write the
+ * allocated channel number in Control Config Event Mux registers.
+ *
+ * \param eventNum [IN] Event number
+ * \param chanNum [IN/OUT]Return the channel number to which the
+ * request event is mapped to.
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note This function is re-entrant for unique event values. It is
+ * non-re-entrant for same event values.
+ */
+typedef EDMA3_DRV_Result (*EDMA3_DRV_xbarConfigScr) (unsigned int eventNum,
+ unsigned int chanNum);
+
+/**
+ * \brief Initialize the cross bar mapped event to channel function
+ *
+ * This API provides interface to associate the cross bar mapped event to edma
+ * channel in the driver.
+ * This function will called by the application during initilization.
+ * User could pass the application specific configuration structure
+ * during init-time. In case user doesn't provide it, this information could
+ * be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c,
+ * in case it is available.
+ * \param hEdma [IN] Handle to the EDMA Driver Instance.
+ * \param edmaGblXbarConfig [IN] This is the configuration data structure
+ * for mapping the events to the channel
+ * \param mapXbarEvtFunc [IN] This is the user defined function for
+ * mapping the cross bar event to channel.
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note This function disables the global interrupts (by calling API
+ * edma3OsProtectEntry with protection level
+ * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data
+ * structures, to make it re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap (EDMA3_DRV_Handle hEdma,
+ const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig,
+ EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc,
+ EDMA3_DRV_xbarConfigScr configXbarScr);
+
+
+
/**
@}
*/
diff --git a/packages/ti/sdo/edma3/drv/sample/src/sample_init.c b/packages/ti/sdo/edma3/drv/sample/src/sample_init.c
index 9c7ee1d7b23a4f1aa718c121698ee77f3ba1d2d8..656ac77d961243d25c2a0e7f74ccd79d3ceda37b 100755 (executable)
hEdma = EDMA3_DRV_open (edma3Id, (void *) &initCfg, &edma3Result);
}
+#if defined (CHIP_TI814X)
+ {
+ if(hEdma && (edma3Result == EDMA3_DRV_SOK))
+ {
+ edma3Result = sampleInitXbarEvt(hEdma, edma3Id);
+ }
+ }
+#endif
if(hEdma && (edma3Result == EDMA3_DRV_SOK))
{
/**
index cff498e9ac06af38db652406992005a0c91d3ed0..accefbe9bb2014486feaed2f56fcdd10b8276e8d 100755 (executable)
/** Pointer to the Resource Manager Instance opened by the EDMA3 Driver */
EDMA3_RM_Handle resMgrInstance;
+ /**
+ * Pointer to the user defined function for mapping cross bar events to
+ * channel.
+ */
+ EDMA3_DRV_mapXbarEvtToChan mapXbarToChan;
+
+ /**
+ * Pointer to the user defined function for configuring the cross bar
+ * events to appropriate channel in the Control Config TPCC Event Config
+ * registers.
+ */
+ EDMA3_DRV_xbarConfigScr configScrMapXbarToEvt;
+
+ /**
+ * Pointer to the configuration data structure for
+ * mapping cross bar events to channel.
+ */
+ EDMA3_DRV_GblXbarToChanConfigParams drvXbarToEvtMapConfig;
}EDMA3_DRV_Instance;
diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c
index 2079deb558bebaad47ced34602fd2bb8efb3e4df..6aa81c7f56fbbbe0339053a3f805f94357b02b67 100755 (executable)
int mappedPaRAMId;
unsigned int edma3Id;
unsigned int freeDmaQdmaChannel = FALSE;
+ unsigned int mapXbarEvtToChanFlag = FALSE;
+ unsigned int xBarEvtBeforeMap = 0;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
}
+ if ( drvInst->mapXbarToChan != NULL)
+ {
+ xBarEvtBeforeMap = *pLCh;
+ edma3Id = drvObject->phyCtrllerInstId;
+ if ((xBarEvtBeforeMap > edma3_dma_ch_max_val [edma3Id]) &&
+ (xBarEvtBeforeMap < EDMA3_DRV_DMA_CHANNEL_ANY) &&
+ ((*pLCh) == (*pTcc)))
+ {
+ result = drvInst->mapXbarToChan(xBarEvtBeforeMap,
+ pLCh,
+ &drvInst->drvXbarToEvtMapConfig);
+ if (EDMA3_DRV_SOK == result)
+ {
+ *pTcc = *pLCh;
+ mapXbarEvtToChanFlag = TRUE;
+ }
+ }
+ }
+
if (EDMA3_DRV_SOK == result)
{
edma3Id = drvObject->phyCtrllerInstId;
globalRegs = (volatile EDMA3_CCRL_Regs *)(drvObject->gblCfgParams.globalRegs);
-
+
/* Identify the request type and validate the appropriate arguments.
* Starting in the order of PaRAM Set availability,
* check for a specific DMA channel request first.
result = EDMA3_DRV_E_TCC_UNAVAIL;
}
}
+ if ((drvInst->configScrMapXbarToEvt != NULL) &&
+ (mapXbarEvtToChanFlag == TRUE))
+ {
+ drvInst->configScrMapXbarToEvt(xBarEvtBeforeMap, *pLCh);
+ }
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_init.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_init.c
index 5884d7acdcb04332313ba25336aa0aff38cc07fe..c2c6d550fc2f16174aa1183e1118f86307f82d3a 100755 (executable)
return result;
}
+EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap (EDMA3_DRV_Handle hEdma,
+ const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig,
+ EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc,
+ EDMA3_DRV_xbarConfigScr configXbarScr)
+ {
+ EDMA3_DRV_Result result = EDMA3_DRV_SOK;
+ EDMA3_DRV_Instance *drvInst = NULL;
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdma == NULL)
+ {
+ result = EDMA3_DRV_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ drvInst = (EDMA3_DRV_Instance *)hEdma;
+
+ if (mapXbarEvtFunc != NULL)
+ {
+ drvInst->mapXbarToChan = mapXbarEvtFunc;
+ }
+ if (configXbarScr != NULL)
+ {
+ drvInst->configScrMapXbarToEvt = configXbarScr;
+ }
+ if (edmaGblXbarConfig != NULL)
+ {
+ edma3MemCpy((void *)(&drvInst->drvXbarToEvtMapConfig),
+ (const void *)(edmaGblXbarConfig),
+ sizeof (EDMA3_DRV_GblXbarToChanConfigParams));
+ }
+ result = EDMA3_RM_initXbarEventMap(drvInst->resMgrInstance,
+ (const EDMA3_RM_GblXbarToChanConfigParams *)&drvInst->drvXbarToEvtMapConfig,
+ (EDMA3_RM_mapXbarEvtToChan)drvInst->mapXbarToChan,
+ (EDMA3_RM_xbarConfigScr)drvInst->configScrMapXbarToEvt);
+ }
+
+ return (result);
+ }
/* Definitions of Local functions - End */
/* End of File */
index d2db4399fd911d14d3247ef625d7572278497a9e..0b68628d2ed66fee5be104294e2b36814ca61dec 100755 (executable)
void *param
);
+#define EDMA3_RM_MAX_XBAR_EVENTS (31u)
+
+/**\struct EDMA3_RM_GblXbarToChanConfigParams
+ * \brief Init-time Configuration structure for EDMA3
+ * controller, to provide Global SoC specific Information.
+ *
+ * This configuration structure is used to specify the EDMA3 Driver
+ * global settings, specific to the SoC.
+ * This configuraion structure provides the details of the mapping of cross bar
+ * events to available channels.
+ * This configuration information is SoC specific and could be provided by the
+ * user at run-time while creating the EDMA3 Driver Object, using API
+ * EDMA3_RM_initXbarEventMap. In case user doesn't provide it,
+ * this information could be taken from the SoC specific configuration
+ * file edma3_<SOC_NAME>_cfg.c, incase it is available.
+ */
+typedef struct {
+ /**
+ * \brief Mapping from DMA channels to Hardware Events
+ *
+ * Each element in this array corresponds to one cross bar event and tells
+ * whether this event is mapped to any DMA channel. That is whether any
+ * free or unused DMA channel can be mapped to this event.
+ * -1 means the cross bar event is not mapped to any DMA channel;
+ * Any number from 0 to 63 means this event is mapped to specified channel.
+ * All channels need not be mapped, some can be free also.
+ * For the cross bar event mapped to DMA channel, appropriate Control Config
+ * register of TPCC event mux register should be configured.
+ */
+ int dmaMapXbarToChan [EDMA3_RM_MAX_XBAR_EVENTS];
+ } EDMA3_RM_GblXbarToChanConfigParams;
+
+
+/**
+ * \brief Associates cross bar mapped event to channel
+ *
+ * This function have to be defined in the configuration file.
+ * This function will be called only if the channel requested for is beyond the
+ * maximum number of channels.
+ * This function should read from the global cross bar mapped configuration
+ * data structure and return the mapped channel number to this event.
+ *
+ * \param eventNum [IN] Event number
+ * \param chanNum [IN/OUT]Return the channel number to which the
+ * request event is mapped to.
+ * \param edmaGblXbarConfig [IN] This is the configuration data structure
+ * for mapping the events to the channel
+ *
+ * \return EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note This function is re-entrant for unique event values. It is
+ * non-re-entrant for same event values.
+ */
+typedef EDMA3_RM_Result (*EDMA3_RM_mapXbarEvtToChan) (unsigned int eventNum,
+ unsigned int *chanNum,
+ const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig);
+
+/**
+ * \brief Writes to the cross bar mapped event to channel to system
+ * configuration register
+ *
+ * This function have to be defined in the configuration file.
+ * This function will be called only if the event number requested for is
+ * beyond the maximum number of channels and if any channel is allocated to this
+ * event.
+ * This function should read the cross bar mapped event number and write the
+ * allocated channel number in Control Config Event Mux registers.
+ *
+ * \param eventNum [IN] Event number
+ * \param chanNum [IN/OUT]Return the channel number to which the
+ * request event is mapped to.
+ *
+ * \return EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note This function is re-entrant for unique event values. It is
+ * non-re-entrant for same event values.
+ */
+typedef EDMA3_RM_Result (*EDMA3_RM_xbarConfigScr) (unsigned int eventNum,
+ unsigned int chanNum);
+
+/**
+ * \brief Initialize the cross bar mapped event to channel function
+ *
+ * This API provides interface to associate the cross bar mapped event to edma
+ * channel in the driver.
+ * This function will called by the application during initilization.
+ * User could pass the application specific configuration structure
+ * during init-time. In case user doesn't provide it, this information could
+ * be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c,
+ * in case it is available.
+ * \param hEdma [IN] Handle to the EDMA Driver Instance.
+ * \param edmaGblXbarConfig [IN] This is the configuration data structure
+ * for mapping the events to the channel
+ * \param mapXbarEvtFunc [IN] This is the user defined function for
+ * mapping the cross bar event to channel.
+ *
+ * \return EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note This function disables the global interrupts (by calling API
+ * edma3OsProtectEntry with protection level
+ * EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data
+ * structures, to make it re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_initXbarEventMap (EDMA3_RM_Handle hEdma,
+ const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig,
+ EDMA3_RM_mapXbarEvtToChan mapXbarEvtFunc,
+ EDMA3_RM_xbarConfigScr configXbarScr);
+
+
+
/**
@}
*/
diff --git a/packages/ti/sdo/edma3/rm/sample/src/sample_init.c b/packages/ti/sdo/edma3/rm/sample/src/sample_init.c
index a8a7f0ec0cabb10c540488121be845d8fa0422bc..1aacce4f2a98bbed951764f03e0db6da18b90311 100755 (executable)
&edma3Result);\r
}\r
\r
+#if defined (CHIP_TI814X)\r
+ {\r
+ if(hEdmaResMgr && (edma3Result == EDMA3_RM_SOK))\r
+ {\r
+ edma3Result = sampleInitXbarEvt(hEdmaResMgr, edma3Id);\r
+ }\r
+ }\r
+#endif \r
if(hEdmaResMgr && (edma3Result == EDMA3_DRV_SOK))\r
{\r
/**\r
diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.c b/packages/ti/sdo/edma3/rm/src/edma3resmgr.c
index b42677b2ebf0f4eb35094f37e91ac6e72dcf0153..87872e847d466ed80f316ab1b9642315b318c23d 100755 (executable)
unsigned int resIdSet = 0x0;
unsigned int resId;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
+ unsigned int mapXbarEvtToChanFlag = FALSE;
+ unsigned int xBarEvtBeforeMap = 0;
unsigned int edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
resIdClr = (unsigned int)(~(1u << (resId%32u)));
resIdSet = (1u << (resId%32u));
- /**
- * Take the instance specific semaphore, to prevent simultaneous
- * access to the shared resources.
- */
- semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,
- EDMA3_OSSEM_NO_TIMEOUT);
- if (EDMA3_RM_SOK == semResult)
+ if ( rmInstance->mapXbarToChan != NULL)
{
- switch (resObj->type)
+ xBarEvtBeforeMap = resId;
+ if ((resId > rmObj->gblCfgParams.numDmaChannels) &&
+ (resId != EDMA3_RM_RES_ANY) &&
+ (resObj->type == EDMA3_RM_RES_DMA_CHANNEL))
{
- case EDMA3_RM_RES_DMA_CHANNEL :
- {
- if (resId == EDMA3_RM_RES_ANY)
- {
- for (avlblIdx=0u;
- avlblIdx <
- rmObj->gblCfgParams.numDmaChannels;
- ++avlblIdx)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[avlblIdx/32u])
- &
- (rmInstance->avlblDmaChannels[avlblIdx/32u])
- &
- ~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[avlblIdx/32u])
- &
- (1u << (avlblIdx%32u))) != FALSE)
- {
- /*
- * Match found.
- * A resource which is owned by this instance of the
- * Resource Manager and which is presently available
- * and which has not been reserved - is found.
- */
- resObj->resId = avlblIdx;
- /*
- * Mark the 'match found' resource as "Not Available"
- * for future requests
- */
- rmInstance->avlblDmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
-
- /**
- * Check if the register modification flag is
- * set or not.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- /**
- * Enable the DMA channel in the
- * DRAE/DRAEH registers also.
- */
- if (avlblIdx < 32u)
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << avlblIdx);
- }
- else
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (avlblIdx - 32u));
- }
- }
-
- result = EDMA3_RM_SOK;
- break;
- }
- }
- /*
- * If none of the owned resources of this type is available
- * then report "All Resources of this type not available" error
- */
- if (avlblIdx == rmObj->gblCfgParams.numDmaChannels)
- {
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- if (resId < rmObj->gblCfgParams.numDmaChannels)
- {
- /*
- * Check if specified resource is owned
- * by this instance of the resource manager
- */
- if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resId/32u])&(resIdSet))!=FALSE)
- {
- /* Now check if specified resource is available presently*/
- if (((rmInstance->avlblDmaChannels[resId/32u])&(resIdSet))!=FALSE)
- {
- /*
- * Mark the specified channel as "Not Available"
- * for future requests
- */
- rmInstance->avlblDmaChannels[resId/32u] &= resIdClr;
-
- /**
- * Check if the register modification flag is
- * set or not.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- if (resId < 32u)
- {
- rmInstance->shadowRegs->EECR = (1UL << resId);
-
- /**
- * Enable the DMA channel in the
- * DRAE registers also.
- */
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << resId);
- }
- else
- {
- rmInstance->shadowRegs->EECRH = (1UL << resId);
-
- /**
- * Enable the DMA channel in the
- * DRAEH registers also.
- */
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (resId - 32u));
- }
- }
-
- result = EDMA3_RM_SOK;
- }
- else
- {
- /* Specified resource is owned but is already booked */
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- /*
- * Specified resource is not owned by this instance
- * of the Resource Manager
- */
- result = EDMA3_RM_E_RES_NOT_OWNED;
- }
- }
- else
- {
- result = EDMA3_RM_E_INVALID_PARAM;
- }
- }
- }
- break;
-
- case EDMA3_RM_RES_QDMA_CHANNEL :
- {
- if (resId == EDMA3_RM_RES_ANY)
- {
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numQdmaChannels; ++avlblIdx)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[avlblIdx/32u])
- &
- (rmInstance->avlblQdmaChannels[avlblIdx/32u])
- &
- ~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[avlblIdx/32u])
- &
- (1u << (avlblIdx%32u))) != FALSE)
- {
- resObj->resId = avlblIdx;
- rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
-
- /**
- * Check if the register modification flag is
- * set or not.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- /**
- * Enable the QDMA channel in the
- * QRAE register also.
- */
- gblRegs->QRAE[rmInstance->initParam.regionId]
- |= (0x1u << avlblIdx);
- }
-
- result = EDMA3_RM_SOK;
- break;
- }
- }
- /*
- * If none of the owned resources of this type is available
- * then report "All Resources of this type not available" error
- */
- if (avlblIdx == rmObj->gblCfgParams.numQdmaChannels)
- {
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- if (resId < rmObj->gblCfgParams.numQdmaChannels)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32u])&(resIdSet))!=FALSE)
- {
- if (((rmInstance->avlblQdmaChannels [resId/32u])&(resIdSet))!=FALSE)
- {
- rmInstance->avlblQdmaChannels [resId/32u] &= resIdClr;
-
- /**
- * Check if the register modification flag is
- * set or not.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- /**
- * Enable the QDMA channel in the
- * QRAE register also.
- */
- gblRegs->QRAE[rmInstance->initParam.regionId]
- |= (0x1u << resId);
- }
-
- result = EDMA3_RM_SOK;
- }
- else
- {
- /* Specified resource is owned but is already booked */
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- /*
- * Specified resource is not owned by this instance
- * of the Resource Manager
- */
- result = EDMA3_RM_E_RES_NOT_OWNED;
- }
- }
- else
- {
- result = EDMA3_RM_E_INVALID_PARAM;
- }
- }
- }
- break;
-
- case EDMA3_RM_RES_TCC :
- {
- if (resId == EDMA3_RM_RES_ANY)
- {
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numTccs; ++avlblIdx)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [avlblIdx/32u])
- & (rmInstance->avlblTccs [avlblIdx/32u])
- & ~(rmInstance->initParam.rmInstInitConfig->resvdTccs [avlblIdx/32u])
- & (1u << (avlblIdx%32u)))!=FALSE)
- {
- resObj->resId = avlblIdx;
- rmInstance->avlblTccs [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
-
- /**
- * Check if the register modification flag is
- * set or not.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- /**
- * Enable the Interrupt channel in the
- * DRAE/DRAEH registers also.
- * Also, If the region id coming from this
- * RM instance is same as the Master RM
- * Instance's region id, only then we will be
- * getting the interrupts on the same side.
- * So save the TCC in the allocatedTCCs[] array.
- */
- if (avlblIdx < 32u)
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << avlblIdx);
-
- /**
- * Do not modify this global array if the register
- * modificatio flag is not set.
- * Reason being is based on this flag, the IPR/ICR
- * or error bit is cleared in the completion or
- * error handler ISR.
- */
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][0u] |= (0x1u << avlblIdx);
- }
- }
- else
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (avlblIdx - 32u));
-
- /**
- * Do not modify this global array if the register
- * modificatio flag is not set.
- * Reason being is based on this flag, the IPR/ICR
- * or error bit is cleared in the completion or
- * error handler ISR.
- */
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][1u] |= (0x1u << (avlblIdx - 32u));
- }
- }
- }
-
-
- result = EDMA3_RM_SOK;
- break;
- }
- }
- /*
- * If none of the owned resources of this type is available
- * then report "All Resources of this type not available" error
- */
- if ( avlblIdx == rmObj->gblCfgParams.numTccs)
- {
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- if (resId < rmObj->gblCfgParams.numTccs)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32u])&(resIdSet))!=FALSE)
- {
- if (((rmInstance->avlblTccs [resId/32u])&(resIdSet))!=FALSE)
- {
- rmInstance->avlblTccs [resId/32u] &= resIdClr;
-
- /**
- * Check if the register modification flag is
- * set or not.
- */
- if (TRUE == rmInstance->regModificationRequired)
- {
- /**
- * Enable the Interrupt channel in the
- * DRAE/DRAEH registers also.
- * Also, If the region id coming from this
- * RM instance is same as the Master RM
- * Instance's region id, only then we will be
- * getting the interrupts on the same side.
- * So save the TCC in the allocatedTCCs[] array.
- */
- if (resId < 32u)
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAE
- |= (0x1u << resId);
-
- /**
- * Do not modify this global array if the register
- * modificatio flag is not set.
- * Reason being is based on this flag, the IPR/ICR
- * or error bit is cleared in the completion or
- * error handler ISR.
- */
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][0u] |= (0x1u << resId);
- }
- }
- else
- {
- gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
- |= (0x1u << (resId - 32u));
-
- /**
- * Do not modify this global array if the register
- * modificatio flag is not set.
- * Reason being is based on this flag, the IPR/ICR
- * or error bit is cleared in the completion or
- * error handler ISR.
- */
- if (edma3RegionId == rmInstance->initParam.regionId)
- {
- allocatedTCCs[edma3Id][1u] |= (0x1u << (resId - 32u));
- }
- }
- }
-
- result = EDMA3_RM_SOK;
- }
- else
- {
- /* Specified resource is owned but is already booked */
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- /*
- * Specified resource is not owned by this instance
- * of the Resource Manager
- */
- result = EDMA3_RM_E_RES_NOT_OWNED;
- }
- }
- else
- {
- result = EDMA3_RM_E_INVALID_PARAM;
- }
- }
- }
- break;
-
- case EDMA3_RM_RES_PARAM_SET :
- {
- if (resId == EDMA3_RM_RES_ANY)
- {
- for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numPaRAMSets; ++avlblIdx)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [avlblIdx/32u])
- &
- (rmInstance->avlblPaRAMSets [avlblIdx/32u])
- &
- ~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets [avlblIdx/32u])
- &
- (1u << (avlblIdx%32u)))!=FALSE)
- {
- resObj->resId = avlblIdx;
- rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
-
- /**
- * Also, make the actual PARAM Set NULL, checking the flag
- * whether it is required or not.
- */
- if ((TRUE == rmInstance->regModificationRequired)
- && (TRUE == rmInstance->paramInitRequired))
- {
- edma3MemZero((void *)(&gblRegs->PARAMENTRY[avlblIdx]),
- sizeof(gblRegs->PARAMENTRY[avlblIdx]));
- }
-
- result = EDMA3_RM_SOK;
- break;
- }
- }
- /*
- * If none of the owned resources of this type is available
- * then report "All Resources of this type not available" error
- */
- if ( avlblIdx == rmObj->gblCfgParams.numPaRAMSets)
- {
- result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- if (resId < rmObj->gblCfgParams.numPaRAMSets)
- {
- if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32u])&(resIdSet))!=FALSE)
- {
- if (((rmInstance->avlblPaRAMSets [resId/32u])&(resIdSet)) !=FALSE)
- {
- rmInstance->avlblPaRAMSets [resId/32u] &= resIdClr;
-
- /**
- * Also, make the actual PARAM Set NULL, checking the flag
- * whether it is required or not.
- */
- if ((TRUE == rmInstance->regModificationRequired)
- && (TRUE == rmInstance->paramInitRequired))
- {
- edma3MemZero((void *)(&gblRegs->PARAMENTRY[resId]),
- sizeof(gblRegs->PARAMENTRY[resId]));
- }
-
- result = EDMA3_RM_SOK;
- }
- else
- {
- /* Specified resource is owned but is already booked */
- result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
- }
- }
- else
- {
- /*
- * Specified resource is not owned by this instance
- * of the Resource Manager
- */
- result = EDMA3_RM_E_RES_NOT_OWNED;
- }
- }
- else
- {
- result = EDMA3_RM_E_INVALID_PARAM;
- }
- }
- }
- break;
-
- default:
- result = EDMA3_RM_E_INVALID_PARAM;
- break;
+ result = rmInstance->mapXbarToChan(xBarEvtBeforeMap,
+ &resObj->resId,
+ &rmInstance->rmXbarToEvtMapConfig);
+ if (EDMA3_RM_SOK == result)
+ {
+ resId = resObj->resId;
+ mapXbarEvtToChanFlag = TRUE;
+ }
}
-
- /* Return the semaphore back */
- semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
}
- }
+
+ if (result == EDMA3_RM_SOK)
+ {
+ /**
+ * Take the instance specific semaphore, to prevent simultaneous
+ * access to the shared resources.
+ */
+ semResult = edma3OsSemTake(rmInstance->initParam.rmSemHandle,
+ EDMA3_OSSEM_NO_TIMEOUT);
+ if (EDMA3_RM_SOK == semResult)
+ {
+ switch (resObj->type)
+ {
+ case EDMA3_RM_RES_DMA_CHANNEL :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0u;
+ avlblIdx <
+ rmObj->gblCfgParams.numDmaChannels;
+ ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[avlblIdx/32u])
+ &
+ (rmInstance->avlblDmaChannels[avlblIdx/32u])
+ &
+ ~(rmInstance->initParam.rmInstInitConfig->resvdDmaChannels[avlblIdx/32u])
+ &
+ (1u << (avlblIdx%32u))) != FALSE)
+ {
+ /*
+ * Match found.
+ * A resource which is owned by this instance of the
+ * Resource Manager and which is presently available
+ * and which has not been reserved - is found.
+ */
+ resObj->resId = avlblIdx;
+ /*
+ * Mark the 'match found' resource as "Not Available"
+ * for future requests
+ */
+ rmInstance->avlblDmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the DMA channel in the
+ * DRAE/DRAEH registers also.
+ */
+ if (avlblIdx < 32u)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= (0x1u << avlblIdx);
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= (0x1u << (avlblIdx - 32u));
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if (avlblIdx == rmObj->gblCfgParams.numDmaChannels)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numDmaChannels)
+ {
+ /*
+ * Check if specified resource is owned
+ * by this instance of the resource manager
+ */
+ if (((rmInstance->initParam.rmInstInitConfig->ownDmaChannels[resId/32u])&(resIdSet))!=FALSE)
+ {
+ /* Now check if specified resource is available presently*/
+ if (((rmInstance->avlblDmaChannels[resId/32u])&(resIdSet))!=FALSE)
+ {
+ /*
+ * Mark the specified channel as "Not Available"
+ * for future requests
+ */
+ rmInstance->avlblDmaChannels[resId/32u] &= resIdClr;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ if (resId < 32u)
+ {
+ rmInstance->shadowRegs->EECR = (1UL << resId);
+
+ /**
+ * Enable the DMA channel in the
+ * DRAE registers also.
+ */
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= (0x1u << resId);
+ }
+ else
+ {
+ rmInstance->shadowRegs->EECRH = (1UL << resId);
+
+ /**
+ * Enable the DMA channel in the
+ * DRAEH registers also.
+ */
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= (0x1u << (resId - 32u));
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_QDMA_CHANNEL :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numQdmaChannels; ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels[avlblIdx/32u])
+ &
+ (rmInstance->avlblQdmaChannels[avlblIdx/32u])
+ &
+ ~(rmInstance->initParam.rmInstInitConfig->resvdQdmaChannels[avlblIdx/32u])
+ &
+ (1u << (avlblIdx%32u))) != FALSE)
+ {
+ resObj->resId = avlblIdx;
+ rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the QDMA channel in the
+ * QRAE register also.
+ */
+ gblRegs->QRAE[rmInstance->initParam.regionId]
+ |= (0x1u << avlblIdx);
+ }
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if (avlblIdx == rmObj->gblCfgParams.numQdmaChannels)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numQdmaChannels)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownQdmaChannels [resId/32u])&(resIdSet))!=FALSE)
+ {
+ if (((rmInstance->avlblQdmaChannels [resId/32u])&(resIdSet))!=FALSE)
+ {
+ rmInstance->avlblQdmaChannels [resId/32u] &= resIdClr;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the QDMA channel in the
+ * QRAE register also.
+ */
+ gblRegs->QRAE[rmInstance->initParam.regionId]
+ |= (0x1u << resId);
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_TCC :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numTccs; ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [avlblIdx/32u])
+ & (rmInstance->avlblTccs [avlblIdx/32u])
+ & ~(rmInstance->initParam.rmInstInitConfig->resvdTccs [avlblIdx/32u])
+ & (1u << (avlblIdx%32u)))!=FALSE)
+ {
+ resObj->resId = avlblIdx;
+ rmInstance->avlblTccs [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the Interrupt channel in the
+ * DRAE/DRAEH registers also.
+ * Also, If the region id coming from this
+ * RM instance is same as the Master RM
+ * Instance's region id, only then we will be
+ * getting the interrupts on the same side.
+ * So save the TCC in the allocatedTCCs[] array.
+ */
+ if (avlblIdx < 32u)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= (0x1u << avlblIdx);
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0u] |= (0x1u << avlblIdx);
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= (0x1u << (avlblIdx - 32u));
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1u] |= (0x1u << (avlblIdx - 32u));
+ }
+ }
+ }
+
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if ( avlblIdx == rmObj->gblCfgParams.numTccs)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numTccs)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownTccs [resId/32u])&(resIdSet))!=FALSE)
+ {
+ if (((rmInstance->avlblTccs [resId/32u])&(resIdSet))!=FALSE)
+ {
+ rmInstance->avlblTccs [resId/32u] &= resIdClr;
+
+ /**
+ * Check if the register modification flag is
+ * set or not.
+ */
+ if (TRUE == rmInstance->regModificationRequired)
+ {
+ /**
+ * Enable the Interrupt channel in the
+ * DRAE/DRAEH registers also.
+ * Also, If the region id coming from this
+ * RM instance is same as the Master RM
+ * Instance's region id, only then we will be
+ * getting the interrupts on the same side.
+ * So save the TCC in the allocatedTCCs[] array.
+ */
+ if (resId < 32u)
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAE
+ |= (0x1u << resId);
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][0u] |= (0x1u << resId);
+ }
+ }
+ else
+ {
+ gblRegs->DRA[rmInstance->initParam.regionId].DRAEH
+ |= (0x1u << (resId - 32u));
+
+ /**
+ * Do not modify this global array if the register
+ * modificatio flag is not set.
+ * Reason being is based on this flag, the IPR/ICR
+ * or error bit is cleared in the completion or
+ * error handler ISR.
+ */
+ if (edma3RegionId == rmInstance->initParam.regionId)
+ {
+ allocatedTCCs[edma3Id][1u] |= (0x1u << (resId - 32u));
+ }
+ }
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ case EDMA3_RM_RES_PARAM_SET :
+ {
+ if (resId == EDMA3_RM_RES_ANY)
+ {
+ for (avlblIdx=0u; avlblIdx<rmObj->gblCfgParams.numPaRAMSets; ++avlblIdx)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [avlblIdx/32u])
+ &
+ (rmInstance->avlblPaRAMSets [avlblIdx/32u])
+ &
+ ~(rmInstance->initParam.rmInstInitConfig->resvdPaRAMSets [avlblIdx/32u])
+ &
+ (1u << (avlblIdx%32u)))!=FALSE)
+ {
+ resObj->resId = avlblIdx;
+ rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+
+ /**
+ * Also, make the actual PARAM Set NULL, checking the flag
+ * whether it is required or not.
+ */
+ if ((TRUE == rmInstance->regModificationRequired)
+ && (TRUE == rmInstance->paramInitRequired))
+ {
+ edma3MemZero((void *)(&gblRegs->PARAMENTRY[avlblIdx]),
+ sizeof(gblRegs->PARAMENTRY[avlblIdx]));
+ }
+
+ result = EDMA3_RM_SOK;
+ break;
+ }
+ }
+ /*
+ * If none of the owned resources of this type is available
+ * then report "All Resources of this type not available" error
+ */
+ if ( avlblIdx == rmObj->gblCfgParams.numPaRAMSets)
+ {
+ result = EDMA3_RM_E_ALL_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ if (resId < rmObj->gblCfgParams.numPaRAMSets)
+ {
+ if (((rmInstance->initParam.rmInstInitConfig->ownPaRAMSets [resId/32u])&(resIdSet))!=FALSE)
+ {
+ if (((rmInstance->avlblPaRAMSets [resId/32u])&(resIdSet)) !=FALSE)
+ {
+ rmInstance->avlblPaRAMSets [resId/32u] &= resIdClr;
+
+ /**
+ * Also, make the actual PARAM Set NULL, checking the flag
+ * whether it is required or not.
+ */
+ if ((TRUE == rmInstance->regModificationRequired)
+ && (TRUE == rmInstance->paramInitRequired))
+ {
+ edma3MemZero((void *)(&gblRegs->PARAMENTRY[resId]),
+ sizeof(gblRegs->PARAMENTRY[resId]));
+ }
+
+ result = EDMA3_RM_SOK;
+ }
+ else
+ {
+ /* Specified resource is owned but is already booked */
+ result = EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE;
+ }
+ }
+ else
+ {
+ /*
+ * Specified resource is not owned by this instance
+ * of the Resource Manager
+ */
+ result = EDMA3_RM_E_RES_NOT_OWNED;
+ }
+ }
+ else
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+ }
+ }
+ break;
+
+ default:
+ result = EDMA3_RM_E_INVALID_PARAM;
+ break;
+ }
+
+ /* Return the semaphore back */
+ semResult = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
+ }
+ }
+ }
}
/**
* Else, return semResult.
*/
if (EDMA3_RM_SOK == result)
- {
- /**
- * Resource Allocation successful, return semResult for returning
- * semaphore.
- */
- result = semResult;
- }
+ {
+ /**
+ * Resource Allocation successful, return semResult for returning
+ * semaphore.
+ */
+ result = semResult;
+ if ((rmInstance->configScrMapXbarToEvt != NULL) &&
+ (mapXbarEvtToChanFlag == TRUE))
+ {
+ rmInstance->configScrMapXbarToEvt(xBarEvtBeforeMap, resObj->resId);
+ }
+ }
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
return result;
}
+
+EDMA3_RM_Result EDMA3_RM_initXbarEventMap (EDMA3_RM_Handle hEdmaResMgr,
+ const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig,
+ EDMA3_RM_mapXbarEvtToChan mapXbarEvtFunc,
+ EDMA3_RM_xbarConfigScr configXbarScr)
+ {
+ EDMA3_RM_Result result = EDMA3_DRV_SOK;
+ EDMA3_RM_Instance *rmInstance = NULL;
+
+ /* If parameter checking is enabled... */
+#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
+ if (hEdmaResMgr == NULL)
+ {
+ result = EDMA3_RM_E_INVALID_PARAM;
+ }
+#endif
+
+ /* Check if the parameters are OK. */
+ if (EDMA3_DRV_SOK == result)
+ {
+ rmInstance = (EDMA3_RM_Instance *)hEdmaResMgr;
+
+ if (mapXbarEvtFunc != NULL)
+ {
+ rmInstance->mapXbarToChan = mapXbarEvtFunc;
+ }
+ if (configXbarScr != NULL)
+ {
+ rmInstance->configScrMapXbarToEvt = configXbarScr;
+ }
+ if (edmaGblXbarConfig != NULL)
+ {
+ edma3MemCpy((void *)(&rmInstance->rmXbarToEvtMapConfig),
+ (const void *)(edmaGblXbarConfig),
+ sizeof (EDMA3_RM_GblXbarToChanConfigParams));
+ }
+ }
+
+ return (result);
+ }
+
/* Resource Manager Internal functions - End */
/* End of File */
diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.h b/packages/ti/sdo/edma3/rm/src/edma3resmgr.h
index f730a92bda6724cd6f280211daa42170f6bbdc7f..0714fcbf815d495b10f4a28e2764cb3017a54730 100755 (executable)
* This value can be modified using the IOCTL commands.
*/
unsigned int regModificationRequired;
+ /**
+ * Pointer to the user defined function for mapping cross bar events to
+ * channel.
+ */
+ EDMA3_RM_mapXbarEvtToChan mapXbarToChan;
+
+ /**
+ * Pointer to the user defined function for configuring the cross bar
+ * events to appropriate channel in the Control Config TPCC Event Config
+ * registers.
+ */
+ EDMA3_RM_xbarConfigScr configScrMapXbarToEvt;
+
+ /**
+ * Pointer to the configuration data structure for
+ * mapping cross bar events to channel.
+ */
+ EDMA3_RM_GblXbarToChanConfigParams rmXbarToEvtMapConfig;
}EDMA3_RM_Instance;
/**