summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: e5e95d5)
raw | patch | inline | side by side (parent: e5e95d5)
author | Sundaram Raju <sundaram@ti.com> | |
Mon, 28 Jun 2010 08:24:15 +0000 (13:54 +0530) | ||
committer | Sundaram Raju <sundaram@ti.com> | |
Thu, 15 Jul 2010 12:33:50 +0000 (18:03 +0530) |
- Refer to IR# SDOCM00071134 for more details
Signed-off-by: Sundaram Raju <sundaram@ti.com>
Signed-off-by: Sundaram Raju <sundaram@ti.com>
packages/ti/sdo/edma3/rm/src/edma3resmgr.c | patch | blob | history |
diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.c b/packages/ti/sdo/edma3/rm/src/edma3resmgr.c
index ea0f53386440483e303746c94de90daa0c426661..dad4a44dd1470bc09a2ccd63182a00e4e75def93 100755 (executable)
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
volatile unsigned int pendingIrqs;
+ volatile unsigned int isIPR = 0;
+
unsigned int indexl;
unsigned int indexh;
unsigned int edma3Id;
+ unsigned int numTCCs;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
assert (NULL != rmObj);
edma3Id = rmObj->phyCtrllerInstId;
+ numTCCs = rmObj->gblCfgParams.numTccs;
ptrEdmaccRegs =
(volatile EDMA3_CCRL_Regs *)rmObj->gblCfgParams.globalRegs;
if (ptrEdmaccRegs != NULL)
indexl = 1u;
indexh = 1u;
- if((shadowRegs->IPR !=0 ) || (shadowRegs->IPRH !=0 ))
+ if (numTCCs > 32)
+ isIPR = shadowRegs->IPR | shadowRegs->IPRH;
+ else
+ isIPR = shadowRegs->IPR;
+
+ if(isIPR)
{
/**
* Since an interrupt has found, we have to make sure that this
pendingIrqs >>= 1u;
}
- indexh = 0u;
- pendingIrqs = shadowRegs->IPRH;
-
- /**
- * Choose interrupts coming from our allocated TCCs
- * and MASK remaining ones.
- */
- pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][1u]);
-
- while (pendingIrqs)
- {
- /*Process all the pending interrupts*/
- if((pendingIrqs & 1u)==TRUE)
- {
- /**
- * If the user has not given any callback function
- * while requesting the TCC, its TCC specific bit
- * in the IPRH register will NOT be cleared.
- */
- if(edma3IntrParams[edma3Id][32u+indexh].tccCb!=NULL)
- {
- /* here write to ICR to clear the corresponding IPR bits*/
- shadowRegs->ICRH = (1u << indexh);
-
- edma3IntrParams[edma3Id][32u+indexh].tccCb(32u+indexh,
- EDMA3_RM_XFER_COMPLETE,
- edma3IntrParams[edma3Id][32u+indexh].cbData);
- }
- }
- ++indexh;
- pendingIrqs >>= 1u;
- }
+ if(numTCCs > 32)
+ {
+ indexh = 0u;
+ pendingIrqs = shadowRegs->IPRH;
+
+ /**
+ * Choose interrupts coming from our allocated TCCs
+ * and MASK remaining ones.
+ */
+ pendingIrqs = (pendingIrqs & allocatedTCCs[edma3Id][1u]);
+
+ while (pendingIrqs)
+ {
+ /*Process all the pending interrupts*/
+ if((pendingIrqs & 1u)==TRUE)
+ {
+ /**
+ * If the user has not given any callback function
+ * while requesting the TCC, its TCC specific bit
+ * in the IPRH register will NOT be cleared.
+ */
+ if(edma3IntrParams[edma3Id][32u+indexh].tccCb!=NULL)
+ {
+ /* here write to ICR to clear the corresponding IPR bits*/
+ shadowRegs->ICRH = (1u << indexh);
+
+ edma3IntrParams[edma3Id][32u+indexh].tccCb(32u+indexh,
+ EDMA3_RM_XFER_COMPLETE,
+ edma3IntrParams[edma3Id][32u+indexh].cbData);
+ }
+ }
+ ++indexh;
+ pendingIrqs >>= 1u;
+ }
+ }
Cnt++;
}
indexl = (shadowRegs->IPR & allocatedTCCs[edma3Id][0u]);
- indexh = (shadowRegs->IPRH & allocatedTCCs[edma3Id][1u]);
+ if (numTCCs > 32)
+ indexh = (shadowRegs->IPRH & allocatedTCCs[edma3Id][1u]);
if((indexl !=0 ) || (indexh !=0 ))
{