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raw | patch | inline | side by side (parent: 23a7b64)
| author | Anuj Aggarwal <anuj.aggarwal@ti.com> | |
| Fri, 10 Jul 2009 11:31:02 +0000 (17:01 +0530) | ||
| committer | Anuj Aggarwal <anuj.aggarwal@ti.com> | |
| Fri, 10 Jul 2009 11:31:02 +0000 (17:01 +0530) |
249 files changed:
index 77d8d775a8575fdd3a848822b973018fd3381bb1..713ea0a53a6b03923d54e474970d25ea1ce91774 100644 (file)
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index 33dffeec3f481818ae2b137db8725eb387a643a9..8ebd6dcf80a983cd237f9755f0d5fb61a97db78a 100644 (file)
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diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/******************************************************************************\
-* Copyright (C) 2000 Texas Instruments Incorporated.
-* All Rights Reserved
-*------------------------------------------------------------------------------
-* FILENAME...... csl.h
-* DATE CREATED.. 06/13/2000
-* LAST MODIFIED. 08/02/2004 - Adding support for C6418
-* 07/24/2004 - Re-introducing BIOS components from CSL due to compatibility issues.
-* 06/26/2003 Added CHIP_6411
-* 06/17/2003 Added CHIP_6712C
-* 05/28/2003 Added CHIP_6711C
-* 03/26/2003 - 6412,DM642 check libraries
-* 10/10/2001 - 6712-6713-6414-6416-6415 check libraries
-* 11/19/2003 - Removed BIOS components from CSL - _CSL_Config
-*
-\******************************************************************************/
-#ifndef _CSL_H_
-#define _CSL_H_
-
-#include <csl_chip.h>
-#include <csl_irq.h>
-#include <csl_timer.h>
-
-
-/******************************************************************************\
-* scope and inline control macros
-\******************************************************************************/
-#ifdef __cplusplus
-#define CSLAPI extern "C" far
-#else
-#define CSLAPI extern far
-#endif
-
-#undef USEDEFS
-#undef IDECL
-#undef IDEF
-
-#ifdef _CSL_MOD_
- #define IDECL CSLAPI
- #define USEDEFS
- #define IDEF
-#else
- #ifdef _INLINE
- #define IDECL static inline
- #define USEDEFS
- #define IDEF static inline
- #else
- #define IDECL CSLAPI
- #endif
-#endif
-
-
-/******************************************************************************\
-* global macro declarations
-\******************************************************************************/
-
-
-/******************************************************************************\
-* global typedef declarations
-\******************************************************************************/
-
-/* if this structure changes, be sure to also change it in csl_irq_.asm */
-typedef union {
- struct {
- Uint32 biosPresent;
- _IRQ_Dispatch *dispatchTable;
- Uint32 timerUsed;
- Uint32 timerNum;
- } args;
- struct {
- TIMER_Handle hTimer;
- Uint32 *event2IntTbl;
- Uint32 *int2EventTbl;
- } ret;
-} _CSL_Config;
-/******************************************************************************\
-* global variable declarations
-\******************************************************************************/
-
-/******************************************************************************\
-* global function declarations
-\******************************************************************************/
-CSLAPI void _CSL_init(_CSL_Config *config);
-
-CSLAPI void CSL6201_LIB_();
-CSLAPI void CSL6202_LIB_();
-CSLAPI void CSL6203_LIB_();
-CSLAPI void CSL6204_LIB_();
-CSLAPI void CSL6205_LIB_();
-CSLAPI void CSL6211_LIB_();
-CSLAPI void CSL6701_LIB_();
-CSLAPI void CSL6711_LIB_();
-CSLAPI void CSL6712_LIB_();
-CSLAPI void CSL6713_LIB_();
-CSLAPI void CSLDA610_LIB_();
-CSLAPI void CSLDM642_LIB_();
-CSLAPI void CSLDM640_LIB_();
-CSLAPI void CSLDM641_LIB_();
-CSLAPI void CSL6412_LIB_();
-CSLAPI void CSL6414_LIB_();
-CSLAPI void CSL6415_LIB_();
-CSLAPI void CSL6416_LIB_();
-CSLAPI void CSL6711C_LIB_();
-CSLAPI void CSL6712C_LIB_();
-CSLAPI void CSL6411_LIB_();
-/* next two options are DRI300 versions */
-CSLAPI void CSL6410_LIB_();
-CSLAPI void CSL6413_LIB_();
-CSLAPI void CSL6418_LIB_();
-
-/******************************************************************************\
-* inline function declarations
-\******************************************************************************/
-
-
-/******************************************************************************\
-* special inline function
-\******************************************************************************/
-
-/* This function checks to make sure that the correct library is being */
-/* linked in compared to the CHIP_XXXX definition. */
-
-static inline void CSL_init() {
-
- #if (CHIP_6201)
- CSL6201_LIB_();
- #elif (CHIP_6202)
- CSL6202_LIB_();
- #elif (CHIP_6203)
- CSL6203_LIB_();
- #elif (CHIP_6204)
- CSL6204_LIB_();
- #elif (CHIP_6205)
- CSL6205_LIB_();
- #elif (CHIP_6211)
- CSL6211_LIB_();
- #elif (CHIP_6701)
- CSL6701_LIB_();
- #elif (CHIP_6711)
- CSL6711_LIB_();
- #elif (CHIP_6712)
- CSL6712_LIB_();
- #elif (CHIP_6713)
- CSL6713_LIB_();
- #elif (CHIP_DA610)
- CSLDA610_LIB_();
- #elif (CHIP_DM642)
- CSLDM642_LIB_();
- #elif (CHIP_DM640)
- CSLDM640_LIB_();
- #elif (CHIP_DM641)
- CSLDM641_LIB_();
- #elif (CHIP_6412)
- CSL6412_LIB_();
- #elif (CHIP_6414)
- CSL6414_LIB_();
- #elif (CHIP_6415)
- CSL6415_LIB_();
- #elif (CHIP_6416)
- CSL6416_LIB_();
- #elif (CHIP_6711C)
- CSL6711C_LIB_();
- #elif (CHIP_6712C)
- CSL6712C_LIB_();
- #elif (CHIP_6411)
- CSL6411_LIB_();
-/* next three are DRI300 versions */
- #elif (CHIP_6410)
- CSL6410_LIB_();
- #elif (CHIP_6413)
- CSL6413_LIB_();
- #elif (CHIP_6418)
- CSL6418_LIB_();
- #endif
-
- _CSL_init((_CSL_Config*)INV);
-}
-
-/*----------------------------------------------------------------------------*/
-
-
-/******************************************************************************\
-* inline function definitions
-\******************************************************************************/
-#ifdef USEDEFS
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------*/
-#endif /* USEDEFS */
-
-
-#endif /* _CSL_H_ */
-/******************************************************************************\
-* End of csl.h
-\******************************************************************************/
-
diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_atl.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_atl.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... csl_atl.h\r
-* DATE CREATED.. 07/01/2003 \r
-* LAST MODIFIED. \r
-\******************************************************************************/\r
-#ifndef _CSL_ATL_H_\r
-#define _CSL_ATL_H_\r
-\r
-#include <csl_chip.h>\r
-#include <csl_irq.h>\r
-#include <csl_atlhal.h>\r
-\r
-\r
-#if (ATL_SUPPORT)\r
-/******************************************************************************\\r
-* scope and inline control macros\r
-\******************************************************************************/\r
-#ifdef __cplusplus\r
-#define CSLAPI extern "C" far\r
-#else\r
-#define CSLAPI extern far\r
-#endif\r
-\r
-#undef USEDEFS\r
-#undef IDECL\r
-#undef IDEF\r
-\r
-#ifdef _I2C_MOD_\r
- #define IDECL CSLAPI\r
- #define USEDEFS\r
- #define IDEF\r
-#else\r
- #ifdef _INLINE\r
- #define IDECL static inline\r
- #define USEDEFS\r
- #define IDEF static inline\r
- #else\r
- #define IDECL CSLAPI\r
- #endif\r
-#endif\r
-\r
-\r
-/******************************************************************************\\r
-* global macro declarations\r
-\******************************************************************************/\r
-\r
-/******************************************************************************\\r
-* global typedef declarations\r
-\******************************************************************************/\r
-\r
-/* device configuration structure */\r
-typedef struct {\r
- Uint32 atlppmr;\r
- Uint32 atlcr;\r
-} ATL_Config;\r
-\r
-/******************************************************************************\\r
-* global variable declarations\r
-\******************************************************************************/\r
-\r
-/******************************************************************************\\r
-* global function declarations\r
-\******************************************************************************/\r
-\r
-/******************************************************************************\\r
-* inline function declarations\r
-\******************************************************************************/\r
-IDECL void ATL_config(ATL_Config *config);\r
-IDECL void ATL_configArgs(Uint32 atlppmr, Uint32 atlcr);\r
-IDECL void ATL_getConfig(ATL_Config *config);\r
-\r
-/******************************************************************************\\r
-* inline function definitions\r
-\******************************************************************************/\r
-#ifdef USEDEFS\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void ATL_config(ATL_Config *config) {\r
-\r
- Uint32 gie;\r
- volatile Uint32 *base = (volatile Uint32 *)_ATL_BASE_PORT;\r
- register int x0,x1;\r
-\r
- gie = IRQ_globalDisable();\r
-\r
- /* the compiler generates more efficient code if the loads */\r
- /* and stores are grouped together raher than intermixed */\r
- x0 = config->atlppmr;\r
- x1 = config->atlcr;\r
-\r
- base[_ATL_ATLPPMR_OFFSET] = x0;\r
- base[_ATL_ATLCR_OFFSET] = x1;\r
-\r
- IRQ_globalRestore(gie);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void ATL_configArgs(Uint32 atlppmr, Uint32 atlcr) {\r
-\r
- Uint32 gie;\r
- volatile Uint32 *base = (volatile Uint32 *)_ATL_BASE_PORT;\r
-\r
- gie = IRQ_globalDisable();\r
-\r
- base[_ATL_ATLPPMR_OFFSET] = atlppmr;\r
- base[_ATL_ATLCR_OFFSET] = atlcr;\r
-\r
- IRQ_globalRestore(gie);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void ATL_getConfig(ATL_Config *config) {\r
-\r
- Uint32 gie;\r
- volatile Uint32 *base = (volatile Uint32 *)_ATL_BASE_PORT;\r
- volatile ATL_Config* cfg = (volatile ATL_Config*)config;\r
- register int x0,x1;\r
-\r
- gie = IRQ_globalDisable();\r
-\r
- /* the compiler generates more efficient code if the loads */\r
- /* and stores are grouped together raher than intermixed */\r
-\r
- x0 = base[_ATL_ATLPPMR_OFFSET];\r
- x1 = base[_ATL_ATLCR_OFFSET];\r
-\r
- cfg->atlppmr = x0;\r
- cfg->atlcr = x1;\r
-\r
- IRQ_globalRestore(gie);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-#endif /* USEDEFS */\r
-\r
-#endif /* ATL_SUPPORT */\r
-\r
-#endif /* _CSL_ATL_H_ */\r
-/******************************************************************************\\r
-* End of csl_atl.h\r
-\******************************************************************************/\r
-\r
diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_atlhal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_atlhal.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... csl_atlhal.h\r
-* DATE CREATED.. 07/01/2003 \r
-* .............. 07/02/2003 first draft completed\r
-* LAST MODIFIED.\r
-* \r
-*------------------------------------------------------------------------------\r
-* REGISTERS\r
-*\r
-* ATLPPMR - ATL Parts Per Million Register \r
-* ATLSCNTR - ATL Sample Count Register\r
-* ATLCR - ATL Control Register\r
-*\r
-\******************************************************************************/\r
-#ifndef _CSL_ATLHAL_H_\r
-#define _CSL_ATLHAL_H_\r
-\r
-#include <csl_stdinc.h>\r
-#include <csl_chip.h>\r
-#if (ATL_SUPPORT)\r
-/******************************************************************************\\r
-* MISC section\r
-\******************************************************************************/\r
- #define _ATL_BASE_PORT 0x01B7F000u\r
- \r
-\r
-/******************************************************************************\\r
-* module level register/field access macros\r
-\******************************************************************************/\r
-\r
- /* ----------------- */\r
- /* FIELD MAKE MACROS */\r
- /* ----------------- */\r
-\r
- #define ATL_FMK(REG,FIELD,x)\\r
- _PER_FMK(ATL,##REG,##FIELD,x)\r
-\r
- #define ATL_FMKS(REG,FIELD,SYM)\\r
- _PER_FMKS(ATL,##REG,##FIELD,##SYM)\r
-\r
-\r
- /* -------------------------------- */\r
- /* RAW REGISTER/FIELD ACCESS MACROS */\r
- /* -------------------------------- */\r
-\r
- #define ATL_ADDR(REG)\\r
- _ATL_##REG##_ADDR\r
-\r
- #define ATL_RGET(REG)\\r
- _PER_RGET(_ATL_##REG##_ADDR,ATL,##REG)\r
-\r
- #define ATL_RSET(REG,x)\\r
- _PER_RSET(_ATL_##REG##_ADDR,ATL,##REG,x)\r
-\r
- #define ATL_FGET(REG,FIELD)\\r
- _ATL_##REG##_FGET(##FIELD)\r
-\r
- #define ATL_FSET(REG,FIELD,x)\\r
- _ATL_##REG##_FSET(##FIELD,##x)\r
-\r
- #define ATL_FSETS(REG,FIELD,SYM)\\r
- _ATL_##REG##_FSETS(##FIELD,##SYM)\r
-\r
-\r
- /* ------------------------------------------ */\r
- /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */\r
- /* ------------------------------------------ */\r
-\r
- #define ATL_RGETA(addr,REG)\\r
- _PER_RGET(addr,ATL,##REG)\r
-\r
- #define ATL_RSETA(addr,REG,x)\\r
- _PER_RSET(addr,ATL,##REG,x)\r
-\r
- #define ATL_FGETA(addr,REG,FIELD)\\r
- _PER_FGET(addr,ATL,##REG,##FIELD)\r
-\r
- #define ATL_FSETA(addr,REG,FIELD,x)\\r
- _PER_FSET(addr,ATL,##REG,##FIELD,x)\r
-\r
- #define ATL_FSETSA(addr,REG,FIELD,SYM)\\r
- _PER_FSETS(addr,ATL,##REG,##FIELD,##SYM)\r
-\r
-/******************************************************************************\\r
-* ___________________\r
-* | |\r
-* | A T L P P M R |\r
-* |___________________|\r
-*\r
-* ATLPPMR - ATL Parts Per Million register\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) PPMSD\r
-* (rw) PPMSET\r
-*\r
-\******************************************************************************/\r
- #define _ATL_ATLPPMR_OFFSET 0\r
-\r
- #define _ATL_ATLPPMR_ADDR 0x01B7F000\r
-\r
- #define _ATL_ATLPPMR_PPMSD_MASK 0x00008000u\r
- #define _ATL_ATLPPMR_PPMSD_SHIFT 0x0000000Fu\r
- #define ATL_ATLPPMR_PPMSD_DEFAULT 0x00000000u\r
- #define ATL_ATLPPMR_PPMSD_OF(x) _VALUEOF(x)\r
- #define ATL_ATLPPMR_PPMSD_SLOWDOWN 0x00000000u\r
- #define ATL_ATLPPMR_PPMSD_SPEEDUP 0x00000001u\r
-\r
- #define _ATL_ATLPPMR_PPMSET_MASK 0x000001FFu\r
- #define _ATL_ATLPPMR_PPMSET_SHIFT 0x00000000u\r
- #define ATL_ATLPPMR_PPMSET_DEFAULT 0x00000000u\r
- #define ATL_ATLPPMR_PPMSET_OF(x) _VALUEOF(x)\r
-\r
- #define ATL_ATLPPMR_OF(x) _VALUEOF(x)\r
-\r
- #define ATL_ATLPPMR_DEFAULT (Uint32)(\\r
- _PER_FDEFAULT(ATL,ATLPPMR,PPMSD)\\r
- |_PER_FDEFAULT(ATL,ATLPPMR,PPMSET)\\r
- )\r
-\r
- #define ATL_ATLPPMR_RMK(ppmsd,ppmset) (Uint32)(\\r
- _PER_FMK(ATL,ATLPPMR,PPMSD,ppmsd)\\r
- |_PER_FMK(ATL,ATLPPMR,PPMSET,ppmset)\\r
- )\r
- \r
- #define _ATL_ATLPPMR_FGET(N,FIELD)\\r
- _PER_FGET(_ATL_ATLPPMR##N##_ADDR,ATL,ATLPPMR,##FIELD)\r
-\r
- #define _ATL_ATLPPMR_FSET(N,FIELD,field)\\r
- _PER_FSET(_ATL_ATLPPMR##N##_ADDR,ATL,ATLPPMR,##FIELD,field)\r
-\r
- #define _ATL_ATLPPMR_FSETS(N,FIELD,SYM)\\r
- _PER_FSETS(_ATL_ATLPPMR##N##_ADDR,ATL,ATLPPMR,##FIELD,##SYM)\r
-\r
-/******************************************************************************\\r
-* ___________________\r
-* | |\r
-* | A T L S C N T R |\r
-* |___________________|\r
-*\r
-* ATLSCNTR - ATL Sample Count register\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (r) SCNT\r
-*\r
-\******************************************************************************/\r
- #define _ATL_ATLSCNTR_OFFSET 1\r
-\r
- #define _ATL_ATLSCNTR_ADDR 0x01B7F004\r
-\r
- #define _ATL_ATLSCNTR_SCNT_MASK 0x0000FFFFu\r
- #define _ATL_ATLSCNTR_SCNT_SHIFT 0x00000000u\r
- #define ATL_ATLSCNTR_SCNT_DEFAULT 0x00000000u\r
- #define ATL_ATLSCNTR_SCNT_OF(x) _VALUEOF(x)\r
-\r
- #define ATL_ATLSCNTR_OF(x) _VALUEOF(x)\r
-\r
- #define ATL_ATLSCNTR_DEFAULT (Uint32)(\\r
- _PER_FDEFAULT(ATL,ATLSCNTR,SCNT)\\r
- )\r
-\r
- #define ATL_ATLSCNTR_RMK(scnt) (Uint32)(\\r
- _PER_FMK(ATL,ATLSCNTR,SCNT,scnt)\\r
- )\r
- \r
- #define _ATL_ATLSCNTR_FGET(N,FIELD)\\r
- _PER_FGET(_ATL_ATLSCNTR##N##_ADDR,ATL,ATLSCNTR,##FIELD)\r
-\r
-/******************************************************************************\\r
-* _______________\r
-* | |\r
-* | A T L C R |\r
-* |_______________|\r
-*\r
-* ATLCR - ATL Control register\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) MUXCLKSEL\r
-* (rw) MCDSEL\r
-* (rw) ATLIDIV\r
-*\r
-\******************************************************************************/\r
- #define _ATL_ATLCR_OFFSET 2\r
-\r
- #define _ATL_ATLCR_ADDR 0x01B7F008\r
-\r
- #define _ATL_ATLCR_MUXCLKSEL_MASK 0x00000040u\r
- #define _ATL_ATLCR_MUXCLKSEL_SHIFT 0x00000006u\r
- #define ATL_ATLCR_MUXCLKSEL_DEFAULT 0x00000000u\r
- #define ATL_ATLCR_MUXCLKSEL_OF(x) _VALUEOF(x)\r
- #define ATL_ATLCR_MUXCLKSEL_ATLPCLK 0x00000000u\r
- #define ATL_ATLCR_MUXCLKSEL_EATCLK 0x00000001u\r
-\r
- #define _ATL_ATLCR_MCDSEL_MASK 0x00000020u\r
- #define _ATL_ATLCR_MCDSEL_SHIFT 0x00000005u\r
- #define ATL_ATLCR_MCDSEL_DEFAULT 0x00000000u\r
- #define ATL_ATLCR_MCDSEL_OF(x) _VALUEOF(x)\r
- #define ATL_ATLCR_MCDSEL_BY2P16 0x00000000u\r
- #define ATL_ATLCR_MCDSEL_BY2P14 0x00000001u\r
-\r
- #define _ATL_ATLCR_ATLIDIV_MASK 0x0000001Fu\r
- #define _ATL_ATLCR_ATLIDIV_SHIFT 0x00000000u\r
- #define ATL_ATLCR_ATLIDIV_DEFAULT 0x00000018u\r
- #define ATL_ATLCR_ATLIDIV_OF(x) _VALUEOF(x)\r
-\r
- #define ATL_ATLCR_OF(x) _VALUEOF(x)\r
-\r
- #define ATL_ATLCR_DEFAULT (Uint32)(\\r
- _PER_FDEFAULT(ATL,ATLCR,MUXCLKSEL)\\r
- |_PER_FDEFAULT(ATL,ATLCR,MCDSEL)\\r
- |_PER_FDEFAULT(ATL,ATLCR,ATLIDIV)\\r
- )\r
-\r
- #define ATL_ATLCR_RMK(muxclksel,mcdsel,atlidiv) (Uint32)(\\r
- _PER_FMK(ATL,ATLCR,MUXCLKSEL,muxclksel)\\r
- |_PER_FMK(ATL,ATLCR,MCDCLK,mcdsel)\\r
- |_PER_FMK(ATL,ATLCR,ATLIDIV,atlidiv)\\r
- )\r
- \r
- #define _ATL_ATLCR_FGET(N,FIELD)\\r
- _PER_FGET(_ATL_ATLCR##N##_ADDR,ATL,ATLCR,##FIELD)\r
-\r
- #define _ATL_ATLCR_FSET(N,FIELD,field)\\r
- _PER_FSET(_ATL_ATLCR##N##_ADDR,ATL,ATLCR,##FIELD,field)\r
-\r
- #define _ATL_ATLCR_FSETS(N,FIELD,SYM)\\r
- _PER_FSETS(_ATL_ATLCR##N##_ADDR,ATL,ATLCR,##FIELD,##SYM)\r
-\r
-#endif /* ATL_SUPPORT */\r
-#endif /* _CSL_ATLHAL_H_ */\r
-/******************************************************************************\\r
-* End of csl_atlhal.h\r
-\******************************************************************************/\r
diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_cache.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_cache.h
+++ /dev/null
@@ -1,471 +0,0 @@
-/******************************************************************************\
-* Copyright (C) 1999-2001 Texas Instruments Incorporated.
-* All Rights Reserved
-*------------------------------------------------------------------------------
-* FILENAME...... csl_cache.h
-* DATE CREATED.. 06/11/1999
-* LAST MODIFIED. 10/01/2001 - Addition of 192K L2 SRAM for 6713
-* 04/16/2004 - Modified CACHE_ROUND_TO_LINESIZE implementation
-\******************************************************************************/
-#ifndef _CSL_CACHE_H_
-#define _CSL_CACHE_H_
-
-#include <csl_chip.h>
-#include <csl_irq.h>
-#include <csl_cachehal.h>
-
-
-#if (CACHE_SUPPORT)
-/******************************************************************************\
-* scope and inline control macros
-\******************************************************************************/
-#ifdef __cplusplus
-#define CSLAPI extern "C" far
-#else
-#define CSLAPI extern far
-#endif
-
-#undef USEDEFS
-#undef IDECL
-#undef IDEF
-
-#ifdef _CACHE_MOD_
- #define IDECL CSLAPI
- #define USEDEFS
- #define IDEF
-#else
- #ifdef _INLINE
- #define IDECL static inline
- #define USEDEFS
- #define IDEF static inline
- #else
- #define IDECL CSLAPI
- #endif
-#endif
-
-
-/******************************************************************************\
-* global macro declarations
-\******************************************************************************/
-#if (!C64_SUPPORT)
- #define CACHE_CE00 CACHE_ADDR(MAR0)
- #define CACHE_CE01 CACHE_ADDR(MAR1)
- #define CACHE_CE02 CACHE_ADDR(MAR2)
- #define CACHE_CE03 CACHE_ADDR(MAR3)
- #define CACHE_CE10 CACHE_ADDR(MAR4)
- #define CACHE_CE11 CACHE_ADDR(MAR5)
- #define CACHE_CE12 CACHE_ADDR(MAR6)
- #define CACHE_CE13 CACHE_ADDR(MAR7)
- #define CACHE_CE20 CACHE_ADDR(MAR8)
- #define CACHE_CE21 CACHE_ADDR(MAR9)
- #define CACHE_CE22 CACHE_ADDR(MAR10)
- #define CACHE_CE23 CACHE_ADDR(MAR11)
- #define CACHE_CE30 CACHE_ADDR(MAR12)
- #define CACHE_CE31 CACHE_ADDR(MAR13)
- #define CACHE_CE32 CACHE_ADDR(MAR14)
- #define CACHE_CE33 CACHE_ADDR(MAR15)
-#else
-
- #if (CHIP_6414 | CHIP_6415 | CHIP_6416)
-
- #define CACHE_EMIFB_CE00 CACHE_ADDR(MAR96)
- #define CACHE_EMIFB_CE01 CACHE_ADDR(MAR97)
- #define CACHE_EMIFB_CE02 CACHE_ADDR(MAR98)
- #define CACHE_EMIFB_CE03 CACHE_ADDR(MAR99)
- #define CACHE_EMIFB_CE10 CACHE_ADDR(MAR100)
- #define CACHE_EMIFB_CE11 CACHE_ADDR(MAR101)
- #define CACHE_EMIFB_CE12 CACHE_ADDR(MAR102)
- #define CACHE_EMIFB_CE13 CACHE_ADDR(MAR103)
- #define CACHE_EMIFB_CE20 CACHE_ADDR(MAR104)
- #define CACHE_EMIFB_CE21 CACHE_ADDR(MAR105)
- #define CACHE_EMIFB_CE22 CACHE_ADDR(MAR106)
- #define CACHE_EMIFB_CE23 CACHE_ADDR(MAR107)
- #define CACHE_EMIFB_CE30 CACHE_ADDR(MAR108)
- #define CACHE_EMIFB_CE31 CACHE_ADDR(MAR109)
- #define CACHE_EMIFB_CE32 CACHE_ADDR(MAR110)
- #define CACHE_EMIFB_CE33 CACHE_ADDR(MAR111)
-
- #endif
-
- #define CACHE_EMIFA_CE00 CACHE_ADDR(MAR128)
- #define CACHE_EMIFA_CE01 CACHE_ADDR(MAR129)
- #define CACHE_EMIFA_CE02 CACHE_ADDR(MAR130)
- #define CACHE_EMIFA_CE03 CACHE_ADDR(MAR131)
- #define CACHE_EMIFA_CE04 CACHE_ADDR(MAR132)
- #define CACHE_EMIFA_CE05 CACHE_ADDR(MAR133)
- #define CACHE_EMIFA_CE06 CACHE_ADDR(MAR134)
- #define CACHE_EMIFA_CE07 CACHE_ADDR(MAR135)
- #define CACHE_EMIFA_CE08 CACHE_ADDR(MAR136)
- #define CACHE_EMIFA_CE09 CACHE_ADDR(MAR137)
- #define CACHE_EMIFA_CE010 CACHE_ADDR(MAR138)
- #define CACHE_EMIFA_CE011 CACHE_ADDR(MAR139)
- #define CACHE_EMIFA_CE012 CACHE_ADDR(MAR140)
- #define CACHE_EMIFA_CE013 CACHE_ADDR(MAR141)
- #define CACHE_EMIFA_CE014 CACHE_ADDR(MAR142)
- #define CACHE_EMIFA_CE015 CACHE_ADDR(MAR143)
-
- #define CACHE_EMIFA_CE10 CACHE_ADDR(MAR144)
- #define CACHE_EMIFA_CE11 CACHE_ADDR(MAR145)
- #define CACHE_EMIFA_CE12 CACHE_ADDR(MAR146)
- #define CACHE_EMIFA_CE13 CACHE_ADDR(MAR147)
- #define CACHE_EMIFA_CE14 CACHE_ADDR(MAR148)
- #define CACHE_EMIFA_CE15 CACHE_ADDR(MAR149)
- #define CACHE_EMIFA_CE16 CACHE_ADDR(MAR150)
- #define CACHE_EMIFA_CE17 CACHE_ADDR(MAR151)
- #define CACHE_EMIFA_CE18 CACHE_ADDR(MAR152)
- #define CACHE_EMIFA_CE19 CACHE_ADDR(MAR153)
- #define CACHE_EMIFA_CE110 CACHE_ADDR(MAR154)
- #define CACHE_EMIFA_CE111 CACHE_ADDR(MAR155)
- #define CACHE_EMIFA_CE112 CACHE_ADDR(MAR156)
- #define CACHE_EMIFA_CE113 CACHE_ADDR(MAR157)
- #define CACHE_EMIFA_CE114 CACHE_ADDR(MAR158)
- #define CACHE_EMIFA_CE115 CACHE_ADDR(MAR159)
-
- #define CACHE_EMIFA_CE20 CACHE_ADDR(MAR160)
- #define CACHE_EMIFA_CE21 CACHE_ADDR(MAR161)
- #define CACHE_EMIFA_CE22 CACHE_ADDR(MAR162)
- #define CACHE_EMIFA_CE23 CACHE_ADDR(MAR163)
- #define CACHE_EMIFA_CE24 CACHE_ADDR(MAR164)
- #define CACHE_EMIFA_CE25 CACHE_ADDR(MAR165)
- #define CACHE_EMIFA_CE26 CACHE_ADDR(MAR166)
- #define CACHE_EMIFA_CE27 CACHE_ADDR(MAR167)
- #define CACHE_EMIFA_CE28 CACHE_ADDR(MAR168)
- #define CACHE_EMIFA_CE29 CACHE_ADDR(MAR169)
- #define CACHE_EMIFA_CE210 CACHE_ADDR(MAR170)
- #define CACHE_EMIFA_CE211 CACHE_ADDR(MAR171)
- #define CACHE_EMIFA_CE212 CACHE_ADDR(MAR172)
- #define CACHE_EMIFA_CE213 CACHE_ADDR(MAR173)
- #define CACHE_EMIFA_CE214 CACHE_ADDR(MAR174)
- #define CACHE_EMIFA_CE215 CACHE_ADDR(MAR175)
-
- #define CACHE_EMIFA_CE30 CACHE_ADDR(MAR176)
- #define CACHE_EMIFA_CE31 CACHE_ADDR(MAR177)
- #define CACHE_EMIFA_CE32 CACHE_ADDR(MAR178)
- #define CACHE_EMIFA_CE33 CACHE_ADDR(MAR179)
- #define CACHE_EMIFA_CE34 CACHE_ADDR(MAR180)
- #define CACHE_EMIFA_CE35 CACHE_ADDR(MAR181)
- #define CACHE_EMIFA_CE36 CACHE_ADDR(MAR182)
- #define CACHE_EMIFA_CE37 CACHE_ADDR(MAR183)
- #define CACHE_EMIFA_CE38 CACHE_ADDR(MAR184)
- #define CACHE_EMIFA_CE39 CACHE_ADDR(MAR185)
- #define CACHE_EMIFA_CE310 CACHE_ADDR(MAR186)
- #define CACHE_EMIFA_CE311 CACHE_ADDR(MAR187)
- #define CACHE_EMIFA_CE312 CACHE_ADDR(MAR188)
- #define CACHE_EMIFA_CE313 CACHE_ADDR(MAR189)
- #define CACHE_EMIFA_CE314 CACHE_ADDR(MAR190)
- #define CACHE_EMIFA_CE315 CACHE_ADDR(MAR191)
-
-#endif
-
-
-#if (C64_SUPPORT)
- #define CACHE_L2_LINESIZE 128
- #define CACHE_L1D_LINESIZE 64
- #define CACHE_L1P_LINESIZE 32
-#else
- #define CACHE_L2_LINESIZE 128
- #define CACHE_L1D_LINESIZE 32
- #define CACHE_L1P_LINESIZE 64
-#endif /* C64_SUPPORT */
-
-//#define CACHE_ROUND_TO_LINESIZE(CACHE,ELCNT,ELSIZE) \
-// ((CACHE_##CACHE##_LINESIZE * \
-// (( (((ELCNT)*(ELSIZE)) -1)/CACHE_##CACHE##_LINESIZE ) + 1))/ \
-// (ELSIZE))
-
-#define CACHE_ROUND_TO_LINESIZE(CACHE,ELCNT,ELSIZE)\
-( ( ( ( (ELCNT) * (ELSIZE)\
- + CACHE_##CACHE##_LINESIZE - 1\
- ) / CACHE_##CACHE##_LINESIZE\
- * CACHE_##CACHE##_LINESIZE\
- ) + (ELSIZE) - 1\
- ) / (ELSIZE)\
-)
-
-/******************************************************************************\
-* global typedef declarations
-\******************************************************************************/
-#if(!C64_SUPPORT && !CHIP_6713 && !CHIP_DA610)
-typedef enum {
- CACHE_64KSRAM = 0,
- CACHE_0KCACHE = 0,
- CACHE_48KSRAM = 1,
- CACHE_16KCACHE = 1,
- CACHE_32KSRAM = 2,
- CACHE_32KCACHE = 2,
- CACHE_16KSRAM = 3,
- CACHE_48KCACHE = 3,
- CACHE_0KSRAM = 7,
- CACHE_64KCACHE = 7
-} CACHE_L2Mode;
-#endif
-
-#if (CHIP_6414 | CHIP_6415 | CHIP_6416)
-typedef enum {
- CACHE_1024KSRAM = 0,
- CACHE_0KCACHE = 0,
- CACHE_992KSRAM = 1,
- CACHE_32KCACHE = 1,
- CACHE_960KSRAM = 2,
- CACHE_64KCACHE = 2,
- CACHE_896KSRAM = 3,
- CACHE_128KCACHE = 3,
- CACHE_768KSRAM = 7,
- CACHE_256KCACHE = 7 /* 4-way cache 128Kbytes max */
-} CACHE_L2Mode;
- #endif
-
-#if (CHIP_6713 || CHIP_DA610)
- typedef enum {
- CACHE_256KSRAM = 0,
- CACHE_0KCACHE = 0,
- CACHE_240KSRAM = 1,
- CACHE_16KCACHE = 1,
- CACHE_224KSRAM = 2,
- CACHE_32KCACHE = 2,
- CACHE_208KSRAM = 3,
- CACHE_48KCACHE = 3,
- CACHE_192KSRAM = 7,
- CACHE_64KCACHE = 7
-} CACHE_L2Mode;
- #endif
-
-#if (CHIP_DM642 | CHIP_6412 | CHIP_6411)
- typedef enum {
- CACHE_256KSRAM = 0,
- CACHE_0KCACHE = 0,
- CACHE_224KSRAM = 1,
- CACHE_32KCACHE = 1,
- CACHE_192KSRAM = 2,
- CACHE_64KCACHE = 2,
- CACHE_128KSRAM = 3,
- CACHE_128KCACHE = 3,
- CACHE_0KSRAM = 7,
- CACHE_256KCACHE = 7
-} CACHE_L2Mode;
-#endif
-
-/* Cache sizes for the DRI300 variants
- - 6418 : 512 K
- - 6413 : 256 K
- - 6410 : 128 K
-*/
-
-#if (CHIP_6418)
- typedef enum {
- CACHE_512KSRAM = 0,
- CACHE_0KCACHE = 0,
- CACHE_480KSRAM = 1,
- CACHE_32KCACHE = 1,
- CACHE_448KSRAM = 2,
- CACHE_64KCACHE = 2,
- CACHE_384KSRAM = 3,
- CACHE_128KCACHE = 3,
- CACHE_256KSRAM = 7,
- CACHE_256KCACHE = 7
-} CACHE_L2Mode;
-#endif
-
-#if (CHIP_6413)
- typedef enum {
- CACHE_256KSRAM = 0,
- CACHE_0KCACHE = 0,
- CACHE_224KSRAM = 1,
- CACHE_32KCACHE = 1,
- CACHE_192KSRAM = 2,
- CACHE_64KCACHE = 2,
- CACHE_128KSRAM = 3,
- CACHE_128KCACHE = 3,
- CACHE_256KCACHE = 7
-} CACHE_L2Mode;
-#endif
-
-#if (CHIP_6410 | CHIP_DM641 | CHIP_DM640)
- typedef enum {
- CACHE_128KSRAM = 0,
- CACHE_0KCACHE = 0,
- CACHE_96KSRAM = 1,
- CACHE_32KCACHE = 1,
- CACHE_64KSRAM = 2,
- CACHE_64KCACHE = 2,
- CACHE_128KCACHE = 3 /* All other modes are invalid */
-} CACHE_L2Mode;
-#endif
-
-typedef enum {
- CACHE_L2,
- CACHE_L2ALL,
- CACHE_L1P,
- CACHE_L1PALL,
- CACHE_L1D,
- CACHE_L1DALL
-} CACHE_Region;
-
-typedef enum {
- CACHE_PCC_MAPPED = 0,
- CACHE_PCC_ENABLE = 2,
- CACHE_PCC_FREEZE = 3,
- CACHE_PCC_BYPASS = 4
-} CACHE_Pcc;
-
-/* Define macros for L2 priority Level */
-#define CACHE_L2PRIURG 0
-#define CACHE_L2PRIHIGH 1
-#define CACHE_L2PRIMED 2
-#define CACHE_L2PRILOW 3
-
-/* Define macros for L2 Queues */
-#define CACHE_L2Q0 0
-#define CACHE_L2Q1 1
-#define CACHE_L2Q2 2
-#define CACHE_L2Q3 3
-
-/* Define CACHE wait flag */
-typedef enum {
- CACHE_NOWAIT = 0,
- CACHE_WAIT = 1
-} CACHE_Wait;
-
-#define CACHE_WAIT_L2WB 0x00000001
-#define CACHE_WAIT_L2INV 0x00000002
-#define CACHE_WAIT_L2WBINV 0x00000004
-#define CACHE_WAIT_L2WBALL 0x00000008
-#define CACHE_WAIT_L2WBINVALL 0x00000010
-#define CACHE_WAIT_L1DINV 0x00000020
-#define CACHE_WAIT_L1DWBINV 0x00000040
-#define CACHE_WAIT_L1PINV 0x00000080
-
-/* Renaming Function */
-
-#define CACHE_resetEMIFA CACHE_resetEmifa
-
-#if (CHIP_6414 | CHIP_6415 | CHIP_6416)
- #define CACHE_resetEMIFB CACHE_resetEmifb
-#endif
-
-/******************************************************************************\
-* global variable declarations
-\******************************************************************************/
-
-
-/******************************************************************************\
-* global function declarations
-\******************************************************************************/
-CSLAPI void CACHE_reset();
-CSLAPI void CACHE_resetEmifa();
-
-#if (CHIP_6414 | CHIP_6415 | CHIP_6416)
- CSLAPI void CACHE_resetEmifb();
-#endif
-
-CSLAPI CACHE_L2Mode CACHE_setL2Mode(CACHE_L2Mode newMode);
-CSLAPI CACHE_L2Mode CACHE_getL2Mode();
-CSLAPI CACHE_Pcc CACHE_setPccMode(CACHE_Pcc newMode);
-CSLAPI void CACHE_flush(CACHE_Region region,void *addr,Uint32 wordCnt);
-CSLAPI void CACHE_clean(CACHE_Region region,void *addr,Uint32 wordCnt);
-CSLAPI void CACHE_invalidate(CACHE_Region region,void *addr,Uint32 wordCnt);
-CSLAPI Uint32 CACHE_getL2SramSize();
-
-/* New API base on SPRU609 and SPRU610 */
-CSLAPI void CACHE_wbL2(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait);
-CSLAPI void CACHE_wbInvL2(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait);
-CSLAPI void CACHE_wbAllL2(CACHE_Wait wait);
-CSLAPI void CACHE_wbInvAllL2(CACHE_Wait wait);
-//CSLAPI void CACHE_invAllL1d();
-CSLAPI void CACHE_wbInvL1d(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait);
-CSLAPI void CACHE_invL1p(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait);
-CSLAPI void CACHE_invAllL1p();
-CSLAPI void CACHE_wait();
-
-#if (C64_SUPPORT)
-CSLAPI void CACHE_invL2(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait);
-CSLAPI void CACHE_invL1d(void *blockPtr,Uint32 byteCnt,CACHE_Wait wait);
-#endif
-
-/* new APIs with user-determined blocksize option */
-CSLAPI void CACHE_wbInvL2_blocks(void *blockPtr,Uint32 byteCnt, Uint32 blockSize);
-CSLAPI void CACHE_wbL2_blocks(void *blockPtr,Uint32 byteCnt, Uint32 blockSize);
-
-
-/*#if (C64_SUPPORT)
-CSLAPI void CACHE_freezeL1P();
-CSLAPI void CACHE_freezeL1D();
-#endif */
-
-/******************************************************************************\
-* inline function declarations
-\******************************************************************************/
-IDECL void CACHE_enableCaching(Uint32 block);
-#if (CHIP_6414 | CHIP_6415 | CHIP_6416| CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412 | CHIP_6411 | CHIP_6410 | CHIP_6413 | CHIP_6418)
-IDECL void CACHE_setPriL2Req(Uint32 priority);
-IDECL void CACHE_setL2Queue(Uint32 queueNum,Uint32 length);
-IDECL void CACHE_resetL2Queue(Uint32 queueNum);
-#endif
-
-/******************************************************************************\
-* inline function definitions
-\******************************************************************************/
-#ifdef USEDEFS
-/*----------------------------------------------------------------------------*/
-IDEF void CACHE_enableCaching(Uint32 block) {
-
- #if (L2CACHE_SUPPORT)
- CACHE_FSETA(block,MAR,CE,1);
- while (!CACHE_FGETA(block,MAR,CE))
- ;
- #else
- UNREFERENCED_PARAMETER(block);
- #endif
-}
-
-/*----------------------------------------------------------------------------*/
-#if (CHIP_6414 | CHIP_6415 | CHIP_6416| CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412 | CHIP_6411 | CHIP_6410 | CHIP_6413 | CHIP_6418)
-IDEF void CACHE_setPriL2Req(Uint32 priority) {
- CACHE_FSET(CCFG,P,priority);
- }
-/*----------------------------------------------------------------------------*/
-IDEF void CACHE_setL2Queue(Uint32 queueNum,Uint32 length) {
- if (queueNum == 0 ){
- CACHE_FSET(L2ALLOC0,Q0CNT,length);
- } else {
- if (queueNum == 1 ){
- CACHE_FSET(L2ALLOC1,Q1CNT,length);
- } else {
- if (queueNum == 2 ){
- CACHE_FSET(L2ALLOC2,Q2CNT,length);
- } else {
- if (queueNum == 3 ){
- CACHE_FSET(L2ALLOC3,Q3CNT,length);
- }
- }
- }
- }
-}
-/*----------------------------------------------------------------------------*/
-IDEF void CACHE_resetL2Queue(Uint32 queueNum) {
- if (queueNum == 0 ) {
- CACHE_FSET(L2ALLOC0,Q0CNT,6);
- } else {
- if (queueNum == 1 ) {
- CACHE_FSET(L2ALLOC1,Q1CNT,2);
- } else {
- if (queueNum == 2 ) {
- CACHE_FSET(L2ALLOC2,Q2CNT,2);
- } else {
- if (queueNum == 3 ) {
- CACHE_FSET(L2ALLOC3,Q3CNT,2);
- }
- }
- }
- }
-}
-#endif
-/*----------------------------------------------------------------------------*/
-
-#endif /* USEDEFS */
-
-#endif /* CACHE_SUPPORT */
-#endif /* _CSL_CACHE_H_ */
-/******************************************************************************\
-* End of csl_cache.h
-\******************************************************************************/
diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_cachehal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_cachehal.h
+++ /dev/null
@@ -1,1989 +0,0 @@
-/******************************************************************************\
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.
-* All Rights Reserved
-*------------------------------------------------------------------------------
-* FILENAME...... csl_cachehal.h
-* DATE CREATED.. 06/12/1999
-* LAST MODIFIED. 04/13/2001
-*------------------------------------------------------------------------------
-* REGISTERS
-*
-* CCFG - cache configuration register
-* L2FBAR - L2 flush base address register
-* L2FWC - L2 flush word count register
-* L2CBAR - L2 clean base register
-* L2CWC - L2 clean word count register
-* L1PFBAR - L1P flush base address register
-* L1PFWC - L1P flush word count register
-* L1DFBAR - L1D flush base address register
-* L1DFWC - L1D flush word count register
-* L2FLUSH - L2 flush register
-* L2CLEAN - L2 clean register
-*
-*
-*
-*
-*
-* New Register Names based on SPRU609 for C621x/C671x
-* and
-* New Register Names based on SPRU610 for C64x
-*
-*
-* L2WBAR - L2 writeback base address register
-* L2WWC - L2 writeback word count register
-* L2WIBAR - L2 writeback-invalidate base address register
-* L2WIWC - L2 writeback-invalidate word count register
-* L2IBAR - L2 invalidate base address register(2)
-* L2IWC - L2 invalidate word count register(2)
-* L1PIBAR - L1P invalidate base address register
-* L1PIWC - L1P invalidate word count register
-* L1DWIBAR - L1D writeback-invalidate base address register
-* L1DWIWC - L1D writeback-invalidate word count register
-* L1DIBAR - L1D invalidate base address register(2)
-* L1DIWC - L1D invalidate word count register(2)
-* L2WB - L2 writeback all register
-* L2WBINV - L2 writeback-invalidate all register
-*
-* MAR0 - memory attribute register 0
-* MAR1 - memory attribute register 1
-* ... - ...
-* MARn - memory attribute register n (1)
-* L2ALLOC0 - L2 Allocation register 0 (2)
-* L2ALLOC1 - L2 Allocation register 1 (2)
-* L2ALLOC2 - L2 Allocation register 2 (2)
-* L2ALLOC3 - L2 Allocation register 3 (2)
-*
-* (1) n is different between C6x1x and C64x
-* (2) C64x devices only
-*
-\******************************************************************************/
-#ifndef _CSL_CACHEHAL_H_
-#define _CSL_CACHEHAL_H_
-
-#include <csl_stdinc.h>
-#include <csl_chip.h>
-
-#if (CACHE_SUPPORT)
-/******************************************************************************\
-* MISC section
-\******************************************************************************/
-#define _CACHE_BASE_GLOBAL 0x01840000u
-#define CACHE_L2_SUPPORT L2CACHE_SUPPORT
-
-
-/******************************************************************************\
-* module level register/field access macros
-\******************************************************************************/
-
- /* ----------------- */
- /* FIELD MAKE MACROS */
- /* ----------------- */
-
- #define CACHE_FMK(REG,FIELD,x)\
- _PER_FMK(CACHE,##REG,##FIELD,x)
-
- #define CACHE_FMKS(REG,FIELD,SYM)\
- _PER_FMKS(CACHE,##REG,##FIELD,##SYM)
-
-
- /* -------------------------------- */
- /* RAW REGISTER/FIELD ACCESS MACROS */
- /* -------------------------------- */
-
- #define CACHE_ADDR(REG)\
- _CACHE_##REG##_ADDR
-
- #define CACHE_RGET(REG)\
- _PER_RGET(_CACHE_##REG##_ADDR,CACHE,##REG)
-
- #define CACHE_RSET(REG,x)\
- _PER_RSET(_CACHE_##REG##_ADDR,CACHE,##REG,x)
-
- #define CACHE_FGET(REG,FIELD)\
- _CACHE_##REG##_FGET(##FIELD)
-
- #define CACHE_FSET(REG,FIELD,x)\
- _CACHE_##REG##_FSET(##FIELD,x)
-
- #define CACHE_FSETS(REG,FIELD,SYM)\
- _CACHE_##REG##_FSETS(##FIELD,##SYM)
-
-
- /* ------------------------------------------ */
- /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */
- /* ------------------------------------------ */
-
- #define CACHE_RGETA(addr,REG)\
- _PER_RGET(addr,CACHE,##REG)
-
- #define CACHE_RSETA(addr,REG,x)\
- _PER_RSET(addr,CACHE,##REG,x)
-
- #define CACHE_FGETA(addr,REG,FIELD)\
- _PER_FGET(addr,CACHE,##REG,##FIELD)
-
- #define CACHE_FSETA(addr,REG,FIELD,x)\
- _PER_FSET(addr,CACHE,##REG,##FIELD,x)
-
- #define CACHE_FSETSA(addr,REG,FIELD,SYM)\
- _PER_FSETS(addr,CACHE,##REG,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | C C F G |
-* |___________________|
-*
-* CCFG - cache configuration register
-*
-* FIELDS (msb -> lsb)
-* (rw) P (1)
-* (w) IP
-* (w) ID
-* (rw) L2MODE
-*
-* (1) only supported for C64x devices
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_CCFG_ADDR 0x01840000u
-
-#if (C64_SUPPORT)
- #define _CACHE_CCFG_P_MASK 0xE0000000u
- #define _CACHE_CCFG_P_SHIFT 0x0000001Du
- #define CACHE_CCFG_P_DEFAULT 0x00000000u
- #define CACHE_CCFG_P_OF(x) _VALUEOF(x)
- #define CACHE_CCFG_P_URGENT 0x00000000u
- #define CACHE_CCFG_P_HIGH 0x00000001u
- #define CACHE_CCFG_P_MEDIUM 0x00000002u
- #define CACHE_CCFG_P_LOW 0x00000003u
-#endif
-
- #define _CACHE_CCFG_IP_MASK 0x00000200u
- #define _CACHE_CCFG_IP_SHIFT 0x00000009u
- #define CACHE_CCFG_IP_DEFAULT 0x00000000u
- #define CACHE_CCFG_IP_OF(x) _VALUEOF(x)
- #define CACHE_CCFG_IP_NORMAL 0x00000000u
- #define CACHE_CCFG_IP_INVALIDATE 0x00000001u
-
- #define _CACHE_CCFG_ID_MASK 0x00000100u
- #define _CACHE_CCFG_ID_SHIFT 0x00000008u
- #define CACHE_CCFG_ID_DEFAULT 0x00000000u
- #define CACHE_CCFG_ID_OF(x) _VALUEOF(x)
- #define CACHE_CCFG_ID_NORMAL 0x00000000u
- #define CACHE_CCFG_ID_INVALIDATE 0x00000001u
-
-#if (!C64_SUPPORT)
- #define _CACHE_CCFG_L2MODE_MASK 0x00000007u
- #define _CACHE_CCFG_L2MODE_SHIFT 0x00000000u
- #define CACHE_CCFG_L2MODE_DEFAULT 0x00000000u
- #define CACHE_CCFG_L2MODE_OF(x) _VALUEOF(x)
- #define CACHE_CCFG_L2MODE_0KC 0x00000000u
- #define CACHE_CCFG_L2MODE_16KC 0x00000001u
- #define CACHE_CCFG_L2MODE_32KC 0x00000002u
- #define CACHE_CCFG_L2MODE_48KC 0x00000003u
- #define CACHE_CCFG_L2MODE_64KC 0x00000007u
-#else
- #define _CACHE_CCFG_L2MODE_MASK 0x00000007u
- #define _CACHE_CCFG_L2MODE_SHIFT 0x00000000u
- #define CACHE_CCFG_L2MODE_DEFAULT 0x00000000u
- #define CACHE_CCFG_L2MODE_OF(x) _VALUEOF(x)
- #define CACHE_CCFG_L2MODE_0KC 0x00000000u
- #define CACHE_CCFG_L2MODE_32KC 0x00000001u
- #define CACHE_CCFG_L2MODE_64KC 0x00000002u
- #define CACHE_CCFG_L2MODE_128KC 0x00000003u
-
- #if (!(CHIP_6410 | CHIP_DM641 | CHIP_DM640))
- #define CACHE_CCFG_L2MODE_256KC 0x00000007u /* This is an invalid mode for C6410,DM641,DM640 */
- #endif
-
-#endif
-
- #define CACHE_CCFG_OF(x) _VALUEOF(x)
-
-#if (!C64_SUPPORT)
- #define CACHE_CCFG_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,CCFG,IP) \
- |_PER_FDEFAULT(CACHE,CCFG,ID) \
- |_PER_FDEFAULT(CACHE,CCFG,L2MODE) \
- )
-
- #define CACHE_CCFG_RMK(ip,id,l2mode) (Uint32)( \
- _PER_FMK(CACHE,CCFG,IP,ip) \
- |_PER_FMK(CACHE,CCFG,ID,id) \
- |_PER_FMK(CACHE,CCFG,L2MODE,l2mode) \
- )
-#else
- #define CACHE_CCFG_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,CCFG,P) \
- |_PER_FDEFAULT(CACHE,CCFG,IP) \
- |_PER_FDEFAULT(CACHE,CCFG,ID) \
- |_PER_FDEFAULT(CACHE,CCFG,L2MODE) \
- )
-
- #define CACHE_CCFG_RMK(p,ip,id,l2mode) (Uint32)( \
- _PER_FMK(CACHE,CCFG,P,p) \
- |_PER_FMK(CACHE,CCFG,IP,ip) \
- |_PER_FMK(CACHE,CCFG,ID,id) \
- |_PER_FMK(CACHE,CCFG,L2MODE,l2mode) \
- )
-#endif
-
- #define _CACHE_CCFG_FGET(FIELD)\
- _PER_FGET(_CACHE_CCFG_ADDR,CACHE,CCFG,##FIELD)
-
- #define _CACHE_CCFG_FSET(FIELD,field)\
- _PER_FSET(_CACHE_CCFG_ADDR,CACHE,CCFG,##FIELD,field)
-
- #define _CACHE_CCFG_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_CCFG_ADDR,CACHE,CCFG,##FIELD,##SYM)
-
-#endif /* L2CACHE_SUPPORT */
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 F B A R |
-* |___________________|
-*
-* L2FBAR - L2 flush base address register
-*
-* Fields:
-* (rw) L2FBAR
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2FBAR_ADDR 0x01844000u
-
- #define _CACHE_L2FBAR_L2FBAR_MASK 0xFFFFFFFFu
- #define _CACHE_L2FBAR_L2FBAR_SHIFT 0x00000000u
- #define CACHE_L2FBAR_L2FBAR_DEFAULT 0x00000000u
- #define CACHE_L2FBAR_L2FBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L2FBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L2FBAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2FBAR,L2FBAR) \
- )
-
- #define CACHE_L2FBAR_RMK(l2fbar) (Uint32)( \
- _PER_FMK(CACHE,L2FBAR,L2FBAR,l2fbar) \
- )
-
- #define _CACHE_L2FBAR_FGET(FIELD)\
- _PER_FGET(_CACHE_L2FBAR_ADDR,CACHE,L2FBAR,##FIELD)
-
- #define _CACHE_L2FBAR_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2FBAR_ADDR,CACHE,L2FBAR,##FIELD,field)
-
- #define _CACHE_L2FBAR_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2FBAR_ADDR,CACHE,L2FBAR,##FIELD,##SYM)
-#endif
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 F W C |
-* |___________________|
-*
-* L2FWC - L2 flush word count register
-*
-* Fields:
-* (rw) L2FWC
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2FWC_ADDR 0x01844004u
-
- #define _CACHE_L2FWC_L2FWC_MASK 0x0000FFFFu
- #define _CACHE_L2FWC_L2FWC_SHIFT 0x00000000u
- #define CACHE_L2FWC_L2FWC_DEFAULT 0x00000000u
- #define CACHE_L2FWC_L2FWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L2FWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L2FWC_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2FWC,L2FWC) \
- )
-
- #define CACHE_L2FWC_RMK(l2fwc) (Uint32)( \
- _PER_FMK(CACHE,L2FWC,L2FWC,l2fwc) \
- )
-
- #define _CACHE_L2FWC_FGET(FIELD)\
- _PER_FGET(_CACHE_L2FWC_ADDR,CACHE,L2FWC,##FIELD)
-
- #define _CACHE_L2FWC_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2FWC_ADDR,CACHE,L2FWC,##FIELD,field)
-
- #define _CACHE_L2FWC_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2FWC_ADDR,CACHE,L2FWC,##FIELD,##SYM)
-#endif
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 C B A R |
-* |___________________|
-*
-* L2CBAR - L2 clean base address register
-*
-* Fields:
-* (rw) L2CBAR
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2CBAR_ADDR 0x01844010u
-
- #define _CACHE_L2CBAR_L2CBAR_MASK 0xFFFFFFFFu
- #define _CACHE_L2CBAR_L2CBAR_SHIFT 0x00000000u
- #define CACHE_L2CBAR_L2CBAR_DEFAULT 0x00000000u
- #define CACHE_L2CBAR_L2CBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L2CBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L2CBAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2CBAR,L2CBAR) \
- )
-
- #define CACHE_L2CBAR_RMK(l2cbar) (Uint32)( \
- _PER_FMK(CACHE,L2CBAR,L2CBAR,l2cbar) \
- )
-
- #define _CACHE_L2CBAR_FGET(FIELD)\
- _PER_FGET(_CACHE_L2CBAR_ADDR,CACHE,L2CBAR,##FIELD)
-
- #define _CACHE_L2CBAR_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2CBAR_ADDR,CACHE,L2CBAR,##FIELD,field)
-
- #define _CACHE_L2CBAR_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2CBAR_ADDR,CACHE,L2CBAR,##FIELD,##SYM)
-#endif
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 C W C |
-* |___________________|
-*
-* L2CWC - L2 clean word count register
-*
-* Fields:
-* (rw) L2CWC
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2CWC_ADDR 0x01844014u
-
- #define _CACHE_L2CWC_L2CWC_MASK 0x0000FFFFu
- #define _CACHE_L2CWC_L2CWC_SHIFT 0x00000000u
- #define CACHE_L2CWC_L2CWC_DEFAULT 0x00000000u
- #define CACHE_L2CWC_L2CWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L2CWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L2CWC_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2CWC,L2CWC) \
- )
-
- #define CACHE_L2CWC_RMK(l2cwc) (Uint32)( \
- _PER_FMK(CACHE,L2CWC,L2CWC,l2cwc) \
- )
-
- #define _CACHE_L2CWC_FGET(FIELD)\
- _PER_FGET(_CACHE_L2CWC_ADDR,CACHE,L2CWC,##FIELD)
-
- #define _CACHE_L2CWC_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2CWC_ADDR,CACHE,L2CWC,##FIELD,field)
-
- #define _CACHE_L2CWC_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2CWC_ADDR,CACHE,L2CWC,##FIELD,##SYM)
-#endif
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 1 P F B A R |
-* |___________________|
-*
-* L1PFBAR - L1P flush base address register
-*
-* Fields:
-* (rw) L1PFBAR
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L1PFBAR_ADDR 0x01844020u
-
- #define _CACHE_L1PFBAR_L1PFBAR_MASK 0xFFFFFFFFu
- #define _CACHE_L1PFBAR_L1PFBAR_SHIFT 0x00000000u
- #define CACHE_L1PFBAR_L1PFBAR_DEFAULT 0x00000000u
- #define CACHE_L1PFBAR_L1PFBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L1PFBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L1PFBAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L1PFBAR,L1PFBAR) \
- )
-
- #define _CACHE_L1PFBAR_FGET(FIELD)\
- _PER_FGET(_CACHE_L1PFBAR_ADDR,CACHE,L1PFBAR,##FIELD)
-
- #define _CACHE_L1PFBAR_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L1PFBAR_ADDR,CACHE,L1PFBAR,##FIELD,field)
-
- #define _CACHE_L1PFBAR_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L1PFBAR_ADDR,CACHE,L1PFBAR,##FIELD,##SYM)
-#endif
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 1 P F W C |
-* |___________________|
-*
-* L1PFWC - L1P flush word count register
-*
-* Fields:
-* (rw) L1PFWC
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L1PFWC_ADDR 0x01844024u
-
- #define _CACHE_L1PFWC_L1PFWC_MASK 0x0000FFFFu
- #define _CACHE_L1PFWC_L1PFWC_SHIFT 0x00000000u
- #define CACHE_L1PFWC_L1PFWC_DEFAULT 0x00000000u
- #define CACHE_L1PFWC_L1PFWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L1PFWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L1PFWC_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L1PFWC,L1PFWC) \
- )
-
- #define CACHE_L1PFWC_RMK(l1pfwc) (Uint32)( \
- _PER_FMK(CACHE,L1PFWC,L1PFWC,l1pfwc) \
- )
-
- #define _CACHE_L1PFWC_FGET(FIELD)\
- _PER_FGET(_CACHE_L1PFWC_ADDR,CACHE,L1PFWC,##FIELD)
-
- #define _CACHE_L1PFWC_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L1PFWC_ADDR,CACHE,L1PFWC,##FIELD,field)
-
- #define _CACHE_L1PFWC_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L1PFWC_ADDR,CACHE,L1PFWC,##FIELD,##SYM)
-#endif
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 1 D F B A R |
-* |___________________|
-*
-* L1DFBAR - L1D flush base address register
-*
-* Fields:
-* (rw) L1DFBAR
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L1DFBAR_ADDR 0x01844030u
-
- #define _CACHE_L1DFBAR_L1DFBAR_MASK 0xFFFFFFFFu
- #define _CACHE_L1DFBAR_L1DFBAR_SHIFT 0x00000000u
- #define CACHE_L1DFBAR_L1DFBAR_DEFAULT 0x00000000u
- #define CACHE_L1DFBAR_L1DFBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DFBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DFBAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L1DFBAR,L1DFBAR) \
- )
-
- #define CACHE_L1DFBAR_RMK(l1dfbar) (Uint32)( \
- _PER_FMK(CACHE,L1DFBAR,L1DFBAR,l1dfbar) \
- )
-
- #define _CACHE_L1DFBAR_FGET(FIELD)\
- _PER_FGET(_CACHE_L1DFBAR_ADDR,CACHE,L1DFBAR,##FIELD)
-
- #define _CACHE_L1DFBAR_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L1DFBAR_ADDR,CACHE,L1DFBAR,##FIELD,field)
-
- #define _CACHE_L1DFBAR_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L1DFBAR_ADDR,CACHE,L1DFBAR,##FIELD,##SYM)
-#endif
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 1 D F W C |
-* |___________________|
-*
-* L1DFWC - L1D flush word count register
-*
-* Fields:
-* (rw) L1DFWC
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L1DFWC_ADDR 0x01844034u
-
- #define _CACHE_L1DFWC_L1DFWC_MASK 0x0000FFFFu
- #define _CACHE_L1DFWC_L1DFWC_SHIFT 0x00000000u
- #define CACHE_L1DFWC_L1DFWC_DEFAULT 0x00000000u
- #define CACHE_L1DFWC_L1DFWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DFWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DFWC_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L1DFWC,L1DFWC) \
- )
-
- #define CACHE_L1DFWC_RMK(l1dfwc) (Uint32)( \
- _PER_FMK(CACHE,L1DFWC,L1DFWC,l1dfwc) \
- )
-
- #define _CACHE_L1DFWC_FGET(FIELD)\
- _PER_FGET(_CACHE_L1DFWC_ADDR,CACHE,L1DFWC,##FIELD)
-
- #define _CACHE_L1DFWC_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L1DFWC_ADDR,CACHE,L1DFWC,##FIELD,field)
-
- #define _CACHE_L1DFWC_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L1DFWC_ADDR,CACHE,L1DFWC,##FIELD,##SYM)
-#endif
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 F L U S H |
-* |___________________|
-*
-* L2FLUSH - L2 flush register
-*
-* Fields:
-* (rw) F
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2FLUSH_ADDR 0x01845000u
-
- #define _CACHE_L2FLUSH_F_MASK 0x00000001u
- #define _CACHE_L2FLUSH_F_SHIFT 0x00000000u
- #define CACHE_L2FLUSH_F_DEFAULT 0x00000000u
- #define CACHE_L2FLUSH_F_OF(x) _VALUEOF(x)
- #define CACHE_L2FLUSH_F_NORMAL 0x00000000u
- #define CACHE_L2FLUSH_F_FLUSH 0x00000001u
-
- #define CACHE_L2FLUSH_OF(x) _VALUEOF(x)
-
- #define CACHE_L2FLUSH_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2FLUSH,F) \
- )
-
- #define CACHE_L2FLUSH_RMK(f) (Uint32)( \
- _PER_FMK(CACHE,L2FLUSH,F,f) \
- )
-
- #define _CACHE_L2FLUSH_FGET(FIELD)\
- _PER_FGET(_CACHE_L2FLUSH_ADDR,CACHE,L2FLUSH,##FIELD)
-
- #define _CACHE_L2FLUSH_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2FLUSH_ADDR,CACHE,L2FLUSH,##FIELD,field)
-
- #define _CACHE_L2FLUSH_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2FLUSH_ADDR,CACHE,L2FLUSH,##FIELD,##SYM)
-#endif
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 C L E A N |
-* |___________________|
-*
-* L2CLEAN - L2 clean register
-*
-* Fields:
-* (rw) C
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2CLEAN_ADDR 0x01845004u
-
- #define _CACHE_L2CLEAN_C_MASK 0x00000001u
- #define _CACHE_L2CLEAN_C_SHIFT 0x00000000u
- #define CACHE_L2CLEAN_C_DEFAULT 0x00000000u
- #define CACHE_L2CLEAN_C_OF(x) _VALUEOF(x)
- #define CACHE_L2CLEAN_C_NORMAL 0x00000000u
- #define CACHE_L2CLEAN_C_CLEAN 0x00000001u
-
- #define CACHE_L2CLEAN_OF(x) _VALUEOF(x)
-
- #define CACHE_L2CLEAN_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2CLEAN,C) \
- )
-
- #define CACHE_L2CLEAN_RMK(c) (Uint32)( \
- _PER_FMK(CACHE,L2CLEAN,C,c) \
- )
-
- #define _CACHE_L2CLEAN_FGET(FIELD)\
- _PER_FGET(_CACHE_L2CLEAN_ADDR,CACHE,L2CLEAN,##FIELD)
-
- #define _CACHE_L2CLEAN_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2CLEAN_ADDR,CACHE,L2CLEAN,##FIELD,field)
-
- #define _CACHE_L2CLEAN_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2CLEAN_ADDR,CACHE,L2CLEAN,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 A L L O C 0 |
-* |___________________|
-*
-* L2ALLOC0 - L2 allocation register 0 (1)
-*
-* Fields:
-* (rw) Q0CNT (2) (3)
-*
-* (1) only supported for C6400
-* (2) default value is different from L2ALLOC1, L2ALLOC2, L2ALLOC3
-* (3) Rename bit filed based on spru610
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT && C64_SUPPORT)
- #define _CACHE_L2ALLOC0_ADDR 0x01842000u
-
- #define _CACHE_L2ALLOC0_Q0CNT_MASK 0x00000007u
- #define _CACHE_L2ALLOC0_Q0CNT_SHIFT 0x00000000u
- #define CACHE_L2ALLOC0_Q0CNT_DEFAULT 0x00000006u
- #define CACHE_L2ALLOC0_Q0CNT_OF(x) _VALUEOF(x)
-
- #define _CACHE_L2ALLOC0_L2ALLOC_MASK _CACHE_L2ALLOC0_Q0CNT_MASK
- #define _CACHE_L2ALLOC0_L2ALLOC_SHIFT _CACHE_L2ALLOC0_Q0CNT_SHIFT
- #define CACHE_L2ALLOC0_L2ALLOC_DEFAULT CACHE_L2ALLOC0_Q0CNT_DEFAULT
- #define CACHE_L2ALLOC0_L2ALLOC_OF(x) CACHE_L2ALLOC0_Q0CNT_OF(x)
-
- #define CACHE_L2ALLOC0_OF(x) _VALUEOF(x)
-
- #define CACHE_L2ALLOC0_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2ALLOC0,Q0CNT) \
- )
-
- #define CACHE_L2ALLOC0_RMK(q0cnt)(Uint32)( \
- _PER_FMK(CACHE,L2ALLOC0,Q0CNT,q0cnt) \
- )
-
- #define _CACHE_L2ALLOC0_FGET(FIELD)\
- _PER_FGET(_CACHE_L2ALLOC0_ADDR,CACHE,L2ALLOC0,##FIELD)
-
- #define _CACHE_L2ALLOC0_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2ALLOC0_ADDR,CACHE,L2ALLOC0,##FIELD,field)
-
- #define _CACHE_L2ALLOC0_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2ALLOC0_ADDR,CACHE,L2ALLOC0,##FIELD,##SYM)
-
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 A L L O C 1 |
-* |___________________|
-*
-* L2ALLOC1 - L2 allocation register 1 (1)
-*
-* Fields:
-* (rw) Q1CNT (2)
-*
-* (1) only supported for C6400
-* (2) Rename bit filed based on spru610
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT && C64_SUPPORT)
- #define _CACHE_L2ALLOC1_ADDR 0x01842004u
-
- #define _CACHE_L2ALLOC1_Q1CNT_MASK 0x00000007u
- #define _CACHE_L2ALLOC1_Q1CNT_SHIFT 0x00000000u
- #define CACHE_L2ALLOC1_Q1CNT_DEFAULT 0x00000002u
- #define CACHE_L2ALLOC1_Q1CNT_OF(x) _VALUEOF(x)
-
- #define _CACHE_L2ALLOC1_L2ALLOC_MASK _CACHE_L2ALLOC1_Q1CNT_MASK
- #define _CACHE_L2ALLOC1_L2ALLOC_SHIFT _CACHE_L2ALLOC1_Q1CNT_SHIFT
- #define CACHE_L2ALLOC1_L2ALLOC_DEFAULT CACHE_L2ALLOC1_Q1CNT_DEFAULT
- #define CACHE_L2ALLOC1_L2ALLOC_OF(x) CACHE_L2ALLOC1_Q1CNT_OF(x)
-
- #define CACHE_L2ALLOC1_OF(x) _VALUEOF(x)
-
- #define CACHE_L2ALLOC1_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2ALLOC1,Q1CNT) \
- )
-
- #define CACHE_L2ALLOC1_RMK(q1cnt) (Uint32)( \
- _PER_FMK(CACHE,L2ALLOC1,Q1CNT,q1cnt) \
- )
-
- #define _CACHE_L2ALLOC1_FGET(FIELD)\
- _PER_FGET(_CACHE_L2ALLOC1_ADDR,CACHE,L2ALLOC1,##FIELD)
-
- #define _CACHE_L2ALLOC1_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2ALLOC1_ADDR,CACHE,L2ALLOC1,##FIELD,field)
-
- #define _CACHE_L2ALLOC1_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2ALLOC1_ADDR,CACHE,L2ALLOC1,##FIELD,##SYM)
-
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 A L L O C 2 |
-* |___________________|
-*
-* L2ALLOC2 - L2 allocation register 2 (1)
-*
-* Fields:
-* (rw) Q2CNT (2)
-*
-* (1) only supported for C6400
-* (2) Rename bit filed based on spru610
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT && C64_SUPPORT)
- #define _CACHE_L2ALLOC2_ADDR 0x01842008u
-
- #define _CACHE_L2ALLOC2_Q2CNT_MASK 0x00000007u
- #define _CACHE_L2ALLOC2_Q2CNT_SHIFT 0x00000000u
- #define CACHE_L2ALLOC2_Q2CNT_DEFAULT 0x00000002u
- #define CACHE_L2ALLOC2_Q2CNT_OF(x) _VALUEOF(x)
-
- #define _CACHE_L2ALLOC2_L2ALLOC_MASK _CACHE_L2ALLOC2_Q2CNT_MASK
- #define _CACHE_L2ALLOC2_L2ALLOC_SHIFT _CACHE_L2ALLOC2_Q2CNT_SHIFT
- #define CACHE_L2ALLOC2_L2ALLOC_DEFAULT CACHE_L2ALLOC2_Q2CNT_DEFAULT
- #define CACHE_L2ALLOC2_L2ALLOC_OF(x) CACHE_L2ALLOC2_Q2CNT_OF(x)
-
- #define CACHE_L2ALLOC2_OF(x) _VALUEOF(x)
-
- #define CACHE_L2ALLOC2_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2ALLOC2,Q2CNT) \
- )
-
- #define CACHE_L2ALLOC2_RMK(q2cnt) (Uint32)( \
- _PER_FMK(CACHE,L2ALLOC2,Q2CNT,q2cnt) \
- )
-
- #define _CACHE_L2ALLOC2_FGET(FIELD)\
- _PER_FGET(_CACHE_L2ALLOC2_ADDR,CACHE,L2ALLOC2,##FIELD)
-
- #define _CACHE_L2ALLOC2_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2ALLOC2_ADDR,CACHE,L2ALLOC2,##FIELD,field)
-
- #define _CACHE_L2ALLOC2_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2ALLOC2_ADDR,CACHE,L2ALLOC2,##FIELD,##SYM)
-
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 A L L O C 3 |
-* |___________________|
-*
-* L2ALLOC3 - L2 allocation register 3 (1)
-*
-* Fields:
-* (rw) Q2CNT (2)
-*
-* (1) only supported for C6400
-* (2) Rename bit filed based on spru610
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT && C64_SUPPORT)
- #define _CACHE_L2ALLOC3_ADDR 0x0184200Cu
-
- #define _CACHE_L2ALLOC3_Q3CNT_MASK 0x00000007u
- #define _CACHE_L2ALLOC3_Q3CNT_SHIFT 0x00000000u
- #define CACHE_L2ALLOC3_Q3CNT_DEFAULT 0x00000002u
- #define CACHE_L2ALLOC3_Q3CNT_OF(x) _VALUEOF(x)
-
- #define _CACHE_L2ALLOC3_L2ALLOC_MASK _CACHE_L2ALLOC3_Q3CNT_MASK
- #define _CACHE_L2ALLOC3_L2ALLOC_SHIFT _CACHE_L2ALLOC3_Q3CNT_SHIFT
- #define CACHE_L2ALLOC3_L2ALLOC_DEFAULT CACHE_L2ALLOC3_Q3CNT_DEFAULT
- #define CACHE_L2ALLOC3_L2ALLOC_OF(x) CACHE_L2ALLOC3_Q3CNT_OF(x)
-
- #define CACHE_L2ALLOC3_OF(x) _VALUEOF(x)
-
- #define CACHE_L2ALLOC3_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2ALLOC3,Q3CNT) \
- )
-
- #define CACHE_L2ALLOC3_RMK(q3cnt) (Uint32)( \
- _PER_FMK(CACHE,L2ALLOC3,Q3CNT,q3cnt) \
- )
-
- #define _CACHE_L2ALLOC3_FGET(FIELD)\
- _PER_FGET(_CACHE_L2ALLOC3_ADDR,CACHE,L2ALLOC3,##FIELD)
-
- #define _CACHE_L2ALLOC3_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2ALLOC3_ADDR,CACHE,L2ALLOC3,##FIELD,field)
-
- #define _CACHE_L2ALLOC3_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2ALLOC3_ADDR,CACHE,L2ALLOC3,##FIELD,##SYM)
-
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | M A R |
-* |___________________|
-*
-* MAR0 - memory attribute register 0 (1)
-* MAR1 - memory attribute register 1 (1)
-* MAR2 - memory attribute register 2 (1)
-* ... - ...
-* MARn - memory attribute register n (2)
-*
-* Fields:
-* (rw) NR (3)
-* (rw) NW (3)
-* (rw) PE (3)
-* (rw) CE (4)
-*
-* (1) register values are read only for C6400
-* (2) n = 15 for C6211/C6711, n = 255 for C6400
-* (3) only supported for C6400
-* (4) only supported for C6211/C6711
-* (5) MARn range for C6211/C6711 are from MAR0 ~ MAR15,
-* MARn range for C6400 are:
-* MAR0 ~ MAR2 : register values read only
-* MAR48 ~ MAR51 : McBSP0
-* MAR52 ~ MAR55 : McBSP1
-* MAR56 ~ MAR59 : McBSP2
-* MAR60 ~ MAR63 : UTOPIAII
-* MAR64 ~ MAR79 : HPI/PCI
-* MAR96 ~ MAR111 : EMIFB (1)
-* MAR128 ~ MAR191 : EMIFA
-*
-* (1) only in C6414, C6415, C6416 variants
-\******************************************************************************/
-#if (L2CACHE_SUPPORT && !C64_SUPPORT)
- #define _CACHE_MAR0_ADDR _CACHE_MAR128_ADDR
- #define _CACHE_MAR1_ADDR _CACHE_MAR129_ADDR
- #define _CACHE_MAR2_ADDR _CACHE_MAR130_ADDR
- #define _CACHE_MAR3_ADDR _CACHE_MAR131_ADDR
- #define _CACHE_MAR4_ADDR _CACHE_MAR144_ADDR
- #define _CACHE_MAR5_ADDR _CACHE_MAR145_ADDR
- #define _CACHE_MAR6_ADDR _CACHE_MAR146_ADDR
- #define _CACHE_MAR7_ADDR _CACHE_MAR147_ADDR
- #define _CACHE_MAR8_ADDR _CACHE_MAR160_ADDR
- #define _CACHE_MAR9_ADDR _CACHE_MAR161_ADDR
- #define _CACHE_MAR10_ADDR _CACHE_MAR162_ADDR
- #define _CACHE_MAR11_ADDR _CACHE_MAR163_ADDR
- #define _CACHE_MAR12_ADDR _CACHE_MAR176_ADDR
- #define _CACHE_MAR13_ADDR _CACHE_MAR177_ADDR
- #define _CACHE_MAR14_ADDR _CACHE_MAR178_ADDR
- #define _CACHE_MAR15_ADDR _CACHE_MAR179_ADDR
-
- #define _CACHE_MAR128_ADDR 0x01848200u
- #define _CACHE_MAR129_ADDR 0x01848204u
- #define _CACHE_MAR130_ADDR 0x01848208u
- #define _CACHE_MAR131_ADDR 0x0184820Cu
- #define _CACHE_MAR144_ADDR 0x01848240u
- #define _CACHE_MAR145_ADDR 0x01848244u
- #define _CACHE_MAR146_ADDR 0x01848248u
- #define _CACHE_MAR147_ADDR 0x0184824Cu
- #define _CACHE_MAR160_ADDR 0x01848280u
- #define _CACHE_MAR161_ADDR 0x01848284u
- #define _CACHE_MAR162_ADDR 0x01848288u
- #define _CACHE_MAR163_ADDR 0x0184828Cu
- #define _CACHE_MAR176_ADDR 0x018482C0u
- #define _CACHE_MAR177_ADDR 0x018482C4u
- #define _CACHE_MAR178_ADDR 0x018482C8u
- #define _CACHE_MAR179_ADDR 0x018482CCu
-
- #define _CACHE_MAR_CE_MASK 0x00000001u
- #define _CACHE_MAR_CE_SHIFT 0x00000000u
- #define CACHE_MAR_CE_DEFAULT 0x00000000u
- #define CACHE_MAR_CE_OF(x) _VALUEOF(x)
- #define CACHE_MAR_CE_DISABLE 0x00000000u
- #define CACHE_MAR_CE_ENABLE 0x00000001u
-
- #define CACHE_MAR_OF(x) _VALUEOF(x)
-
- #define CACHE_MAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,MAR,CE) \
- )
-
- #define CACHE_MAR_RMK(ce) (Uint32)( \
- _PER_FMK(CACHE,MAR,CE,ce) \
- )
-
- #define _CACHE_MAR_FGET(N,FIELD)\
- _PER_FGET(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD)
-
- #define _CACHE_MAR_FSET(N,FIELD,field)\
- _PER_FSET(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD,field)
-
- #define _CACHE_MAR_FSETS(N,FIELD,SYM)\
- _PER_FSETS(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD,##SYM)
-
- #define _CACHE_MAR0_FGET(FIELD) _CACHE_MAR_FGET(128,##FIELD)
- #define _CACHE_MAR1_FGET(FIELD) _CACHE_MAR_FGET(129,##FIELD)
- #define _CACHE_MAR2_FGET(FIELD) _CACHE_MAR_FGET(130,##FIELD)
- #define _CACHE_MAR3_FGET(FIELD) _CACHE_MAR_FGET(131,##FIELD)
- #define _CACHE_MAR4_FGET(FIELD) _CACHE_MAR_FGET(144,##FIELD)
- #define _CACHE_MAR5_FGET(FIELD) _CACHE_MAR_FGET(145,##FIELD)
- #define _CACHE_MAR6_FGET(FIELD) _CACHE_MAR_FGET(146,##FIELD)
- #define _CACHE_MAR7_FGET(FIELD) _CACHE_MAR_FGET(147,##FIELD)
- #define _CACHE_MAR8_FGET(FIELD) _CACHE_MAR_FGET(160,##FIELD)
- #define _CACHE_MAR9_FGET(FIELD) _CACHE_MAR_FGET(161,##FIELD)
- #define _CACHE_MAR10_FGET(FIELD) _CACHE_MAR_FGET(162,##FIELD)
- #define _CACHE_MAR11_FGET(FIELD) _CACHE_MAR_FGET(163,##FIELD)
- #define _CACHE_MAR12_FGET(FIELD) _CACHE_MAR_FGET(176,##FIELD)
- #define _CACHE_MAR13_FGET(FIELD) _CACHE_MAR_FGET(177,##FIELD)
- #define _CACHE_MAR14_FGET(FIELD) _CACHE_MAR_FGET(178,##FIELD)
- #define _CACHE_MAR15_FGET(FIELD) _CACHE_MAR_FGET(179,##FIELD)
-
- #define _CACHE_MAR0_FSET(FIELD,f) _CACHE_MAR_FSET(128,##FIELD,f)
- #define _CACHE_MAR1_FSET(FIELD,f) _CACHE_MAR_FSET(129,##FIELD,f)
- #define _CACHE_MAR2_FSET(FIELD,f) _CACHE_MAR_FSET(130,##FIELD,f)
- #define _CACHE_MAR3_FSET(FIELD,f) _CACHE_MAR_FSET(131,##FIELD,f)
- #define _CACHE_MAR4_FSET(FIELD,f) _CACHE_MAR_FSET(144,##FIELD,f)
- #define _CACHE_MAR5_FSET(FIELD,f) _CACHE_MAR_FSET(145,##FIELD,f)
- #define _CACHE_MAR6_FSET(FIELD,f) _CACHE_MAR_FSET(146,##FIELD,f)
- #define _CACHE_MAR7_FSET(FIELD,f) _CACHE_MAR_FSET(147,##FIELD,f)
- #define _CACHE_MAR8_FSET(FIELD,f) _CACHE_MAR_FSET(160,##FIELD,f)
- #define _CACHE_MAR9_FSET(FIELD,f) _CACHE_MAR_FSET(161,##FIELD,f)
- #define _CACHE_MAR10_FSET(FIELD,f) _CACHE_MAR_FSET(162,##FIELD,f)
- #define _CACHE_MAR11_FSET(FIELD,f) _CACHE_MAR_FSET(163,##FIELD,f)
- #define _CACHE_MAR12_FSET(FIELD,f) _CACHE_MAR_FSET(176,##FIELD,f)
- #define _CACHE_MAR13_FSET(FIELD,f) _CACHE_MAR_FSET(177,##FIELD,f)
- #define _CACHE_MAR14_FSET(FIELD,f) _CACHE_MAR_FSET(178,##FIELD,f)
- #define _CACHE_MAR15_FSET(FIELD,f) _CACHE_MAR_FSET(179,##FIELD,f)
-
- #define _CACHE_MAR0_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(128,##FIELD,##SYM)
- #define _CACHE_MAR1_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(129,##FIELD,##SYM)
- #define _CACHE_MAR2_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(130,##FIELD,##SYM)
- #define _CACHE_MAR3_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(131,##FIELD,##SYM)
- #define _CACHE_MAR4_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(144,##FIELD,##SYM)
- #define _CACHE_MAR5_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(145,##FIELD,##SYM)
- #define _CACHE_MAR6_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(146,##FIELD,##SYM)
- #define _CACHE_MAR7_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(147,##FIELD,##SYM)
- #define _CACHE_MAR8_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(160,##FIELD,##SYM)
- #define _CACHE_MAR9_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(161,##FIELD,##SYM)
- #define _CACHE_MAR10_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(162,##FIELD,##SYM)
- #define _CACHE_MAR11_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(163,##FIELD,##SYM)
- #define _CACHE_MAR12_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(176,##FIELD,##SYM)
- #define _CACHE_MAR13_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(177,##FIELD,##SYM)
- #define _CACHE_MAR14_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(178,##FIELD,##SYM)
- #define _CACHE_MAR15_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(179,##FIELD,##SYM)
-
- #define _CACHE_MAR128_FGET(FIELD) _CACHE_MAR_FGET(128,##FIELD)
- #define _CACHE_MAR129_FGET(FIELD) _CACHE_MAR_FGET(129,##FIELD)
- #define _CACHE_MAR130_FGET(FIELD) _CACHE_MAR_FGET(130,##FIELD)
- #define _CACHE_MAR131_FGET(FIELD) _CACHE_MAR_FGET(131,##FIELD)
- #define _CACHE_MAR144_FGET(FIELD) _CACHE_MAR_FGET(144,##FIELD)
- #define _CACHE_MAR145_FGET(FIELD) _CACHE_MAR_FGET(145,##FIELD)
- #define _CACHE_MAR146_FGET(FIELD) _CACHE_MAR_FGET(146,##FIELD)
- #define _CACHE_MAR147_FGET(FIELD) _CACHE_MAR_FGET(147,##FIELD)
- #define _CACHE_MAR160_FGET(FIELD) _CACHE_MAR_FGET(160,##FIELD)
- #define _CACHE_MAR161_FGET(FIELD) _CACHE_MAR_FGET(161,##FIELD)
- #define _CACHE_MAR162_FGET(FIELD) _CACHE_MAR_FGET(162,##FIELD)
- #define _CACHE_MAR163_FGET(FIELD) _CACHE_MAR_FGET(163,##FIELD)
- #define _CACHE_MAR176_FGET(FIELD) _CACHE_MAR_FGET(176,##FIELD)
- #define _CACHE_MAR177_FGET(FIELD) _CACHE_MAR_FGET(177,##FIELD)
- #define _CACHE_MAR178_FGET(FIELD) _CACHE_MAR_FGET(178,##FIELD)
- #define _CACHE_MAR179_FGET(FIELD) _CACHE_MAR_FGET(179,##FIELD)
-
- #define _CACHE_MAR128_FSET(FIELD,f) _CACHE_MAR_FSET(128,##FIELD,f)
- #define _CACHE_MAR129_FSET(FIELD,f) _CACHE_MAR_FSET(129,##FIELD,f)
- #define _CACHE_MAR130_FSET(FIELD,f) _CACHE_MAR_FSET(130,##FIELD,f)
- #define _CACHE_MAR131_FSET(FIELD,f) _CACHE_MAR_FSET(131,##FIELD,f)
- #define _CACHE_MAR144_FSET(FIELD,f) _CACHE_MAR_FSET(144,##FIELD,f)
- #define _CACHE_MAR145_FSET(FIELD,f) _CACHE_MAR_FSET(145,##FIELD,f)
- #define _CACHE_MAR146_FSET(FIELD,f) _CACHE_MAR_FSET(146,##FIELD,f)
- #define _CACHE_MAR147_FSET(FIELD,f) _CACHE_MAR_FSET(147,##FIELD,f)
- #define _CACHE_MAR160_FSET(FIELD,f) _CACHE_MAR_FSET(160,##FIELD,f)
- #define _CACHE_MAR161_FSET(FIELD,f) _CACHE_MAR_FSET(161,##FIELD,f)
- #define _CACHE_MAR162_FSET(FIELD,f) _CACHE_MAR_FSET(162,##FIELD,f)
- #define _CACHE_MAR163_FSET(FIELD,f) _CACHE_MAR_FSET(163,##FIELD,f)
- #define _CACHE_MAR176_FSET(FIELD,f) _CACHE_MAR_FSET(176,##FIELD,f)
- #define _CACHE_MAR177_FSET(FIELD,f) _CACHE_MAR_FSET(177,##FIELD,f)
- #define _CACHE_MAR178_FSET(FIELD,f) _CACHE_MAR_FSET(178,##FIELD,f)
- #define _CACHE_MAR179_FSET(FIELD,f) _CACHE_MAR_FSET(179,##FIELD,f)
-
- #define _CACHE_MAR128_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(128,##FIELD,##SYM)
- #define _CACHE_MAR129_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(129,##FIELD,##SYM)
- #define _CACHE_MAR130_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(130,##FIELD,##SYM)
- #define _CACHE_MAR131_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(131,##FIELD,##SYM)
- #define _CACHE_MAR144_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(144,##FIELD,##SYM)
- #define _CACHE_MAR145_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(145,##FIELD,##SYM)
- #define _CACHE_MAR146_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(146,##FIELD,##SYM)
- #define _CACHE_MAR147_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(147,##FIELD,##SYM)
- #define _CACHE_MAR160_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(160,##FIELD,##SYM)
- #define _CACHE_MAR161_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(161,##FIELD,##SYM)
- #define _CACHE_MAR162_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(162,##FIELD,##SYM)
- #define _CACHE_MAR163_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(163,##FIELD,##SYM)
- #define _CACHE_MAR176_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(176,##FIELD,##SYM)
- #define _CACHE_MAR177_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(177,##FIELD,##SYM)
- #define _CACHE_MAR178_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(178,##FIELD,##SYM)
- #define _CACHE_MAR179_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(179,##FIELD,##SYM)
-
-#else
-
- /* MAR96 to MAR111 are associated with EMIFB memory space. This is supported only in
- * the C6414, C6415 and C6416 chips */
-
- #if (CHIP_6414 | CHIP_6415 | CHIP_6416)
- #define _CACHE_MAR96_ADDR 0x01848180u
- #define _CACHE_MAR97_ADDR 0x01848184u
- #define _CACHE_MAR98_ADDR 0x01848188u
- #define _CACHE_MAR99_ADDR 0x0184818Cu
- #define _CACHE_MAR100_ADDR 0x01848190u
- #define _CACHE_MAR101_ADDR 0x01848194u
- #define _CACHE_MAR102_ADDR 0x01848198u
- #define _CACHE_MAR103_ADDR 0x0184819Cu
- #define _CACHE_MAR104_ADDR 0x018481A0u
- #define _CACHE_MAR105_ADDR 0x018481A4u
- #define _CACHE_MAR106_ADDR 0x018481A8u
- #define _CACHE_MAR107_ADDR 0x018481ACu
- #define _CACHE_MAR108_ADDR 0x018481B0u
- #define _CACHE_MAR109_ADDR 0x018481B4u
- #define _CACHE_MAR110_ADDR 0x018481B8u
- #define _CACHE_MAR111_ADDR 0x018481BCu
- #endif
-
- #define _CACHE_MAR128_ADDR 0x01848200u
- #define _CACHE_MAR129_ADDR 0x01848204u
- #define _CACHE_MAR130_ADDR 0x01848208u
- #define _CACHE_MAR131_ADDR 0x0184820Cu
- #define _CACHE_MAR132_ADDR 0x01848210u
- #define _CACHE_MAR133_ADDR 0x01848214u
- #define _CACHE_MAR134_ADDR 0x01848218u
- #define _CACHE_MAR135_ADDR 0x0184821Cu
- #define _CACHE_MAR136_ADDR 0x01848220u
- #define _CACHE_MAR137_ADDR 0x01848224u
- #define _CACHE_MAR138_ADDR 0x01848228u
- #define _CACHE_MAR139_ADDR 0x0184822Cu
- #define _CACHE_MAR140_ADDR 0x01848230u
- #define _CACHE_MAR141_ADDR 0x01848234u
- #define _CACHE_MAR142_ADDR 0x01848238u
- #define _CACHE_MAR143_ADDR 0x0184823Cu
- #define _CACHE_MAR144_ADDR 0x01848240u
- #define _CACHE_MAR145_ADDR 0x01848244u
- #define _CACHE_MAR146_ADDR 0x01848248u
- #define _CACHE_MAR147_ADDR 0x0184824Cu
- #define _CACHE_MAR148_ADDR 0x01848250u
- #define _CACHE_MAR149_ADDR 0x01848254u
- #define _CACHE_MAR150_ADDR 0x01848258u
- #define _CACHE_MAR151_ADDR 0x0184825Cu
- #define _CACHE_MAR152_ADDR 0x01848260u
- #define _CACHE_MAR153_ADDR 0x01848264u
- #define _CACHE_MAR154_ADDR 0x01848268u
- #define _CACHE_MAR155_ADDR 0x0184826Cu
- #define _CACHE_MAR156_ADDR 0x01848270u
- #define _CACHE_MAR157_ADDR 0x01848274u
- #define _CACHE_MAR158_ADDR 0x01848278u
- #define _CACHE_MAR159_ADDR 0x0184827Cu
- #define _CACHE_MAR160_ADDR 0x01848280u
- #define _CACHE_MAR161_ADDR 0x01848284u
- #define _CACHE_MAR162_ADDR 0x01848288u
- #define _CACHE_MAR163_ADDR 0x0184828Cu
- #define _CACHE_MAR164_ADDR 0x01848290u
- #define _CACHE_MAR165_ADDR 0x01848294u
- #define _CACHE_MAR166_ADDR 0x01848298u
- #define _CACHE_MAR167_ADDR 0x0184829Cu
- #define _CACHE_MAR168_ADDR 0x018482A0u
- #define _CACHE_MAR169_ADDR 0x018482A4u
- #define _CACHE_MAR170_ADDR 0x018482A8u
- #define _CACHE_MAR171_ADDR 0x018482ACu
- #define _CACHE_MAR172_ADDR 0x018482B0u
- #define _CACHE_MAR173_ADDR 0x018482B4u
- #define _CACHE_MAR174_ADDR 0x018482B8u
- #define _CACHE_MAR175_ADDR 0x018482BCu
- #define _CACHE_MAR176_ADDR 0x018482C0u
- #define _CACHE_MAR177_ADDR 0x018482C4u
- #define _CACHE_MAR178_ADDR 0x018482C8u
- #define _CACHE_MAR179_ADDR 0x018482CCu
- #define _CACHE_MAR180_ADDR 0x018482D0u
- #define _CACHE_MAR181_ADDR 0x018482D4u
- #define _CACHE_MAR182_ADDR 0x018482D8u
- #define _CACHE_MAR183_ADDR 0x018482DCu
- #define _CACHE_MAR184_ADDR 0x018482E0u
- #define _CACHE_MAR185_ADDR 0x018482E4u
- #define _CACHE_MAR186_ADDR 0x018482E8u
- #define _CACHE_MAR187_ADDR 0x018482ECu
- #define _CACHE_MAR188_ADDR 0x018482F0u
- #define _CACHE_MAR189_ADDR 0x018482F4u
- #define _CACHE_MAR190_ADDR 0x018482F8u
- #define _CACHE_MAR191_ADDR 0x018482FCu
-
- #define _CACHE_MAR_CE_MASK 0x00000001u
- #define _CACHE_MAR_CE_SHIFT 0x00000000u
- #define CACHE_MAR_CE_DEFAULT 0x00000000u
- #define CACHE_MAR_CE_OF(x) _VALUEOF(x)
- #define CACHE_MAR_CE_DISABLE 0x00000000u
- #define CACHE_MAR_CE_ENABLE 0x00000001u
-
- #define CACHE_MAR_OF(x) _VALUEOF(x)
-
- #define CACHE_MAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,MAR,CE) \
- )
-
- #define CACHE_MAR_RMK(ce) (Uint32)( \
- _PER_FMK(CACHE,MAR,CE,ce) \
- )
-
- #define _CACHE_MAR_FGET(N,FIELD)\
- _PER_FGET(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD)
-
- #define _CACHE_MAR_FSET(N,FIELD,field)\
- _PER_FSET(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD,field)
-
- #define _CACHE_MAR_FSETS(N,FIELD,SYM)\
- _PER_FSETS(_CACHE_MAR##N##_ADDR,CACHE,MAR,##FIELD,##SYM)
-
- #if (CHIP_6414 | CHIP_6415 | CHIP_6416)
- #define _CACHE_MAR96_FGET(FIELD) _CACHE_MAR_FGET(96,##FIELD)
- #define _CACHE_MAR97_FGET(FIELD) _CACHE_MAR_FGET(97,##FIELD)
- #define _CACHE_MAR98_FGET(FIELD) _CACHE_MAR_FGET(98,##FIELD)
- #define _CACHE_MAR99_FGET(FIELD) _CACHE_MAR_FGET(99,##FIELD)
- #define _CACHE_MAR100_FGET(FIELD) _CACHE_MAR_FGET(100,##FIELD)
- #define _CACHE_MAR101_FGET(FIELD) _CACHE_MAR_FGET(101,##FIELD)
- #define _CACHE_MAR102_FGET(FIELD) _CACHE_MAR_FGET(102,##FIELD)
- #define _CACHE_MAR103_FGET(FIELD) _CACHE_MAR_FGET(103,##FIELD)
- #define _CACHE_MAR104_FGET(FIELD) _CACHE_MAR_FGET(104,##FIELD)
- #define _CACHE_MAR105_FGET(FIELD) _CACHE_MAR_FGET(105,##FIELD)
- #define _CACHE_MAR106_FGET(FIELD) _CACHE_MAR_FGET(106,##FIELD)
- #define _CACHE_MAR107_FGET(FIELD) _CACHE_MAR_FGET(107,##FIELD)
- #define _CACHE_MAR108_FGET(FIELD) _CACHE_MAR_FGET(108,##FIELD)
- #define _CACHE_MAR109_FGET(FIELD) _CACHE_MAR_FGET(109,##FIELD)
- #define _CACHE_MAR110_FGET(FIELD) _CACHE_MAR_FGET(110,##FIELD)
- #define _CACHE_MAR111_FGET(FIELD) _CACHE_MAR_FGET(111,##FIELD)
- #endif
-
- #define _CACHE_MAR128_FGET(FIELD) _CACHE_MAR_FGET(128,##FIELD)
- #define _CACHE_MAR129_FGET(FIELD) _CACHE_MAR_FGET(129,##FIELD)
- #define _CACHE_MAR130_FGET(FIELD) _CACHE_MAR_FGET(130,##FIELD)
- #define _CACHE_MAR131_FGET(FIELD) _CACHE_MAR_FGET(131,##FIELD)
- #define _CACHE_MAR132_FGET(FIELD) _CACHE_MAR_FGET(132,##FIELD)
- #define _CACHE_MAR133_FGET(FIELD) _CACHE_MAR_FGET(133,##FIELD)
- #define _CACHE_MAR134_FGET(FIELD) _CACHE_MAR_FGET(134,##FIELD)
- #define _CACHE_MAR135_FGET(FIELD) _CACHE_MAR_FGET(135,##FIELD)
- #define _CACHE_MAR136_FGET(FIELD) _CACHE_MAR_FGET(136,##FIELD)
- #define _CACHE_MAR137_FGET(FIELD) _CACHE_MAR_FGET(137,##FIELD)
- #define _CACHE_MAR138_FGET(FIELD) _CACHE_MAR_FGET(138,##FIELD)
- #define _CACHE_MAR139_FGET(FIELD) _CACHE_MAR_FGET(139,##FIELD)
- #define _CACHE_MAR140_FGET(FIELD) _CACHE_MAR_FGET(140,##FIELD)
- #define _CACHE_MAR141_FGET(FIELD) _CACHE_MAR_FGET(141,##FIELD)
- #define _CACHE_MAR142_FGET(FIELD) _CACHE_MAR_FGET(142,##FIELD)
- #define _CACHE_MAR143_FGET(FIELD) _CACHE_MAR_FGET(143,##FIELD)
- #define _CACHE_MAR144_FGET(FIELD) _CACHE_MAR_FGET(144,##FIELD)
- #define _CACHE_MAR145_FGET(FIELD) _CACHE_MAR_FGET(145,##FIELD)
- #define _CACHE_MAR146_FGET(FIELD) _CACHE_MAR_FGET(146,##FIELD)
- #define _CACHE_MAR147_FGET(FIELD) _CACHE_MAR_FGET(147,##FIELD)
- #define _CACHE_MAR148_FGET(FIELD) _CACHE_MAR_FGET(148,##FIELD)
- #define _CACHE_MAR149_FGET(FIELD) _CACHE_MAR_FGET(149,##FIELD)
- #define _CACHE_MAR150_FGET(FIELD) _CACHE_MAR_FGET(150,##FIELD)
- #define _CACHE_MAR151_FGET(FIELD) _CACHE_MAR_FGET(151,##FIELD)
- #define _CACHE_MAR152_FGET(FIELD) _CACHE_MAR_FGET(152,##FIELD)
- #define _CACHE_MAR153_FGET(FIELD) _CACHE_MAR_FGET(153,##FIELD)
- #define _CACHE_MAR154_FGET(FIELD) _CACHE_MAR_FGET(154,##FIELD)
- #define _CACHE_MAR155_FGET(FIELD) _CACHE_MAR_FGET(155,##FIELD)
- #define _CACHE_MAR156_FGET(FIELD) _CACHE_MAR_FGET(156,##FIELD)
- #define _CACHE_MAR157_FGET(FIELD) _CACHE_MAR_FGET(157,##FIELD)
- #define _CACHE_MAR158_FGET(FIELD) _CACHE_MAR_FGET(158,##FIELD)
- #define _CACHE_MAR159_FGET(FIELD) _CACHE_MAR_FGET(159,##FIELD)
- #define _CACHE_MAR160_FGET(FIELD) _CACHE_MAR_FGET(160,##FIELD)
- #define _CACHE_MAR161_FGET(FIELD) _CACHE_MAR_FGET(161,##FIELD)
- #define _CACHE_MAR162_FGET(FIELD) _CACHE_MAR_FGET(162,##FIELD)
- #define _CACHE_MAR163_FGET(FIELD) _CACHE_MAR_FGET(163,##FIELD)
- #define _CACHE_MAR164_FGET(FIELD) _CACHE_MAR_FGET(164,##FIELD)
- #define _CACHE_MAR165_FGET(FIELD) _CACHE_MAR_FGET(165,##FIELD)
- #define _CACHE_MAR166_FGET(FIELD) _CACHE_MAR_FGET(166,##FIELD)
- #define _CACHE_MAR167_FGET(FIELD) _CACHE_MAR_FGET(167,##FIELD)
- #define _CACHE_MAR168_FGET(FIELD) _CACHE_MAR_FGET(168,##FIELD)
- #define _CACHE_MAR169_FGET(FIELD) _CACHE_MAR_FGET(169,##FIELD)
- #define _CACHE_MAR170_FGET(FIELD) _CACHE_MAR_FGET(170,##FIELD)
- #define _CACHE_MAR171_FGET(FIELD) _CACHE_MAR_FGET(171,##FIELD)
- #define _CACHE_MAR172_FGET(FIELD) _CACHE_MAR_FGET(172,##FIELD)
- #define _CACHE_MAR173_FGET(FIELD) _CACHE_MAR_FGET(173,##FIELD)
- #define _CACHE_MAR174_FGET(FIELD) _CACHE_MAR_FGET(174,##FIELD)
- #define _CACHE_MAR175_FGET(FIELD) _CACHE_MAR_FGET(175,##FIELD)
- #define _CACHE_MAR176_FGET(FIELD) _CACHE_MAR_FGET(176,##FIELD)
- #define _CACHE_MAR177_FGET(FIELD) _CACHE_MAR_FGET(177,##FIELD)
- #define _CACHE_MAR178_FGET(FIELD) _CACHE_MAR_FGET(178,##FIELD)
- #define _CACHE_MAR179_FGET(FIELD) _CACHE_MAR_FGET(179,##FIELD)
- #define _CACHE_MAR180_FGET(FIELD) _CACHE_MAR_FGET(180,##FIELD)
- #define _CACHE_MAR181_FGET(FIELD) _CACHE_MAR_FGET(181,##FIELD)
- #define _CACHE_MAR182_FGET(FIELD) _CACHE_MAR_FGET(182,##FIELD)
- #define _CACHE_MAR183_FGET(FIELD) _CACHE_MAR_FGET(183,##FIELD)
- #define _CACHE_MAR184_FGET(FIELD) _CACHE_MAR_FGET(184,##FIELD)
- #define _CACHE_MAR185_FGET(FIELD) _CACHE_MAR_FGET(185,##FIELD)
- #define _CACHE_MAR186_FGET(FIELD) _CACHE_MAR_FGET(186,##FIELD)
- #define _CACHE_MAR187_FGET(FIELD) _CACHE_MAR_FGET(187,##FIELD)
- #define _CACHE_MAR188_FGET(FIELD) _CACHE_MAR_FGET(188,##FIELD)
- #define _CACHE_MAR189_FGET(FIELD) _CACHE_MAR_FGET(189,##FIELD)
- #define _CACHE_MAR190_FGET(FIELD) _CACHE_MAR_FGET(190,##FIELD)
- #define _CACHE_MAR191_FGET(FIELD) _CACHE_MAR_FGET(191,##FIELD)
-
- #if (CHIP_6414 | CHIP_6415 | CHIP_6416)
- #define _CACHE_MAR96_FSET(FIELD,f) _CACHE_MAR_FSET(96,##FIELD,f)
- #define _CACHE_MAR97_FSET(FIELD,f) _CACHE_MAR_FSET(97,##FIELD,f)
- #define _CACHE_MAR98_FSET(FIELD,f) _CACHE_MAR_FSET(98,##FIELD,f)
- #define _CACHE_MAR99_FSET(FIELD,f) _CACHE_MAR_FSET(99,##FIELD,f)
- #define _CACHE_MAR100_FSET(FIELD,f) _CACHE_MAR_FSET(100,##FIELD,f)
- #define _CACHE_MAR101_FSET(FIELD,f) _CACHE_MAR_FSET(101,##FIELD,f)
- #define _CACHE_MAR102_FSET(FIELD,f) _CACHE_MAR_FSET(102,##FIELD,f)
- #define _CACHE_MAR103_FSET(FIELD,f) _CACHE_MAR_FSET(103,##FIELD,f)
- #define _CACHE_MAR104_FSET(FIELD,f) _CACHE_MAR_FSET(104,##FIELD,f)
- #define _CACHE_MAR105_FSET(FIELD,f) _CACHE_MAR_FSET(105,##FIELD,f)
- #define _CACHE_MAR106_FSET(FIELD,f) _CACHE_MAR_FSET(106,##FIELD,f)
- #define _CACHE_MAR107_FSET(FIELD,f) _CACHE_MAR_FSET(107,##FIELD,f)
- #define _CACHE_MAR108_FSET(FIELD,f) _CACHE_MAR_FSET(108,##FIELD,f)
- #define _CACHE_MAR109_FSET(FIELD,f) _CACHE_MAR_FSET(109,##FIELD,f)
- #define _CACHE_MAR110_FSET(FIELD,f) _CACHE_MAR_FSET(110,##FIELD,f)
- #define _CACHE_MAR111_FSET(FIELD,f) _CACHE_MAR_FSET(111,##FIELD,f)
- #endif
-
- #define _CACHE_MAR128_FSET(FIELD,f) _CACHE_MAR_FSET(128,##FIELD,f)
- #define _CACHE_MAR129_FSET(FIELD,f) _CACHE_MAR_FSET(129,##FIELD,f)
- #define _CACHE_MAR130_FSET(FIELD,f) _CACHE_MAR_FSET(130,##FIELD,f)
- #define _CACHE_MAR131_FSET(FIELD,f) _CACHE_MAR_FSET(131,##FIELD,f)
- #define _CACHE_MAR132_FSET(FIELD,f) _CACHE_MAR_FSET(132,##FIELD,f)
- #define _CACHE_MAR133_FSET(FIELD,f) _CACHE_MAR_FSET(133,##FIELD,f)
- #define _CACHE_MAR134_FSET(FIELD,f) _CACHE_MAR_FSET(134,##FIELD,f)
- #define _CACHE_MAR135_FSET(FIELD,f) _CACHE_MAR_FSET(135,##FIELD,f)
- #define _CACHE_MAR136_FSET(FIELD,f) _CACHE_MAR_FSET(136,##FIELD,f)
- #define _CACHE_MAR137_FSET(FIELD,f) _CACHE_MAR_FSET(137,##FIELD,f)
- #define _CACHE_MAR138_FSET(FIELD,f) _CACHE_MAR_FSET(138,##FIELD,f)
- #define _CACHE_MAR139_FSET(FIELD,f) _CACHE_MAR_FSET(139,##FIELD,f)
- #define _CACHE_MAR140_FSET(FIELD,f) _CACHE_MAR_FSET(140,##FIELD,f)
- #define _CACHE_MAR141_FSET(FIELD,f) _CACHE_MAR_FSET(141,##FIELD,f)
- #define _CACHE_MAR142_FSET(FIELD,f) _CACHE_MAR_FSET(142,##FIELD,f)
- #define _CACHE_MAR143_FSET(FIELD,f) _CACHE_MAR_FSET(143,##FIELD,f)
- #define _CACHE_MAR144_FSET(FIELD,f) _CACHE_MAR_FSET(144,##FIELD,f)
- #define _CACHE_MAR145_FSET(FIELD,f) _CACHE_MAR_FSET(145,##FIELD,f)
- #define _CACHE_MAR146_FSET(FIELD,f) _CACHE_MAR_FSET(146,##FIELD,f)
- #define _CACHE_MAR147_FSET(FIELD,f) _CACHE_MAR_FSET(147,##FIELD,f)
- #define _CACHE_MAR148_FSET(FIELD,f) _CACHE_MAR_FSET(148,##FIELD,f)
- #define _CACHE_MAR149_FSET(FIELD,f) _CACHE_MAR_FSET(149,##FIELD,f)
- #define _CACHE_MAR150_FSET(FIELD,f) _CACHE_MAR_FSET(150,##FIELD,f)
- #define _CACHE_MAR151_FSET(FIELD,f) _CACHE_MAR_FSET(151,##FIELD,f)
- #define _CACHE_MAR152_FSET(FIELD,f) _CACHE_MAR_FSET(152,##FIELD,f)
- #define _CACHE_MAR153_FSET(FIELD,f) _CACHE_MAR_FSET(153,##FIELD,f)
- #define _CACHE_MAR154_FSET(FIELD,f) _CACHE_MAR_FSET(154,##FIELD,f)
- #define _CACHE_MAR155_FSET(FIELD,f) _CACHE_MAR_FSET(155,##FIELD,f)
- #define _CACHE_MAR156_FSET(FIELD,f) _CACHE_MAR_FSET(156,##FIELD,f)
- #define _CACHE_MAR157_FSET(FIELD,f) _CACHE_MAR_FSET(157,##FIELD,f)
- #define _CACHE_MAR158_FSET(FIELD,f) _CACHE_MAR_FSET(158,##FIELD,f)
- #define _CACHE_MAR159_FSET(FIELD,f) _CACHE_MAR_FSET(159,##FIELD,f)
- #define _CACHE_MAR160_FSET(FIELD,f) _CACHE_MAR_FSET(160,##FIELD,f)
- #define _CACHE_MAR161_FSET(FIELD,f) _CACHE_MAR_FSET(161,##FIELD,f)
- #define _CACHE_MAR162_FSET(FIELD,f) _CACHE_MAR_FSET(162,##FIELD,f)
- #define _CACHE_MAR163_FSET(FIELD,f) _CACHE_MAR_FSET(163,##FIELD,f)
- #define _CACHE_MAR164_FSET(FIELD,f) _CACHE_MAR_FSET(164,##FIELD,f)
- #define _CACHE_MAR165_FSET(FIELD,f) _CACHE_MAR_FSET(165,##FIELD,f)
- #define _CACHE_MAR166_FSET(FIELD,f) _CACHE_MAR_FSET(166,##FIELD,f)
- #define _CACHE_MAR167_FSET(FIELD,f) _CACHE_MAR_FSET(167,##FIELD,f)
- #define _CACHE_MAR168_FSET(FIELD,f) _CACHE_MAR_FSET(168,##FIELD,f)
- #define _CACHE_MAR169_FSET(FIELD,f) _CACHE_MAR_FSET(169,##FIELD,f)
- #define _CACHE_MAR170_FSET(FIELD,f) _CACHE_MAR_FSET(170,##FIELD,f)
- #define _CACHE_MAR171_FSET(FIELD,f) _CACHE_MAR_FSET(171,##FIELD,f)
- #define _CACHE_MAR172_FSET(FIELD,f) _CACHE_MAR_FSET(172,##FIELD,f)
- #define _CACHE_MAR173_FSET(FIELD,f) _CACHE_MAR_FSET(173,##FIELD,f)
- #define _CACHE_MAR174_FSET(FIELD,f) _CACHE_MAR_FSET(174,##FIELD,f)
- #define _CACHE_MAR175_FSET(FIELD,f) _CACHE_MAR_FSET(175,##FIELD,f)
- #define _CACHE_MAR176_FSET(FIELD,f) _CACHE_MAR_FSET(176,##FIELD,f)
- #define _CACHE_MAR177_FSET(FIELD,f) _CACHE_MAR_FSET(177,##FIELD,f)
- #define _CACHE_MAR178_FSET(FIELD,f) _CACHE_MAR_FSET(178,##FIELD,f)
- #define _CACHE_MAR179_FSET(FIELD,f) _CACHE_MAR_FSET(179,##FIELD,f)
- #define _CACHE_MAR180_FSET(FIELD,f) _CACHE_MAR_FSET(180,##FIELD,f)
- #define _CACHE_MAR181_FSET(FIELD,f) _CACHE_MAR_FSET(181,##FIELD,f)
- #define _CACHE_MAR182_FSET(FIELD,f) _CACHE_MAR_FSET(182,##FIELD,f)
- #define _CACHE_MAR183_FSET(FIELD,f) _CACHE_MAR_FSET(183,##FIELD,f)
- #define _CACHE_MAR184_FSET(FIELD,f) _CACHE_MAR_FSET(184,##FIELD,f)
- #define _CACHE_MAR185_FSET(FIELD,f) _CACHE_MAR_FSET(185,##FIELD,f)
- #define _CACHE_MAR186_FSET(FIELD,f) _CACHE_MAR_FSET(186,##FIELD,f)
- #define _CACHE_MAR187_FSET(FIELD,f) _CACHE_MAR_FSET(187,##FIELD,f)
- #define _CACHE_MAR188_FSET(FIELD,f) _CACHE_MAR_FSET(188,##FIELD,f)
- #define _CACHE_MAR189_FSET(FIELD,f) _CACHE_MAR_FSET(189,##FIELD,f)
- #define _CACHE_MAR190_FSET(FIELD,f) _CACHE_MAR_FSET(190,##FIELD,f)
- #define _CACHE_MAR191_FSET(FIELD,f) _CACHE_MAR_FSET(191,##FIELD,f)
-
- #if (CHIP_6414 | CHIP_6415 | CHIP_6416)
- #define _CACHE_MAR96_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(96,##FIELD,##SYM)
- #define _CACHE_MAR97_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(97,##FIELD,##SYM)
- #define _CACHE_MAR98_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(98,##FIELD,##SYM)
- #define _CACHE_MAR99_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(99,##FIELD,##SYM)
- #define _CACHE_MAR100_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(100,##FIELD,##SYM)
- #define _CACHE_MAR101_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(101,##FIELD,##SYM)
- #define _CACHE_MAR102_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(102,##FIELD,##SYM)
- #define _CACHE_MAR103_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(103,##FIELD,##SYM)
- #define _CACHE_MAR104_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(104,##FIELD,##SYM)
- #define _CACHE_MAR105_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(105,##FIELD,##SYM)
- #define _CACHE_MAR106_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(106,##FIELD,##SYM)
- #define _CACHE_MAR107_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(107,##FIELD,##SYM)
- #define _CACHE_MAR108_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(108,##FIELD,##SYM)
- #define _CACHE_MAR109_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(109,##FIELD,##SYM)
- #define _CACHE_MAR110_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(110,##FIELD,##SYM)
- #define _CACHE_MAR111_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(111,##FIELD,##SYM)
- #endif
-
- #define _CACHE_MAR128_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(128,##FIELD,##SYM)
- #define _CACHE_MAR129_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(129,##FIELD,##SYM)
- #define _CACHE_MAR130_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(130,##FIELD,##SYM)
- #define _CACHE_MAR131_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(131,##FIELD,##SYM)
- #define _CACHE_MAR132_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(132,##FIELD,##SYM)
- #define _CACHE_MAR133_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(133,##FIELD,##SYM)
- #define _CACHE_MAR134_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(134,##FIELD,##SYM)
- #define _CACHE_MAR135_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(135,##FIELD,##SYM)
- #define _CACHE_MAR136_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(136,##FIELD,##SYM)
- #define _CACHE_MAR137_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(137,##FIELD,##SYM)
- #define _CACHE_MAR138_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(138,##FIELD,##SYM)
- #define _CACHE_MAR139_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(139,##FIELD,##SYM)
- #define _CACHE_MAR140_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(140,##FIELD,##SYM)
- #define _CACHE_MAR141_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(141,##FIELD,##SYM)
- #define _CACHE_MAR142_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(142,##FIELD,##SYM)
- #define _CACHE_MAR143_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(143,##FIELD,##SYM)
- #define _CACHE_MAR144_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(144,##FIELD,##SYM)
- #define _CACHE_MAR145_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(145,##FIELD,##SYM)
- #define _CACHE_MAR146_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(146,##FIELD,##SYM)
- #define _CACHE_MAR147_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(147,##FIELD,##SYM)
- #define _CACHE_MAR148_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(148,##FIELD,##SYM)
- #define _CACHE_MAR149_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(149,##FIELD,##SYM)
- #define _CACHE_MAR150_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(150,##FIELD,##SYM)
- #define _CACHE_MAR151_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(151,##FIELD,##SYM)
- #define _CACHE_MAR152_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(152,##FIELD,##SYM)
- #define _CACHE_MAR153_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(153,##FIELD,##SYM)
- #define _CACHE_MAR154_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(154,##FIELD,##SYM)
- #define _CACHE_MAR155_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(155,##FIELD,##SYM)
- #define _CACHE_MAR156_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(156,##FIELD,##SYM)
- #define _CACHE_MAR157_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(157,##FIELD,##SYM)
- #define _CACHE_MAR158_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(158,##FIELD,##SYM)
- #define _CACHE_MAR159_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(159,##FIELD,##SYM)
- #define _CACHE_MAR160_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(160,##FIELD,##SYM)
- #define _CACHE_MAR161_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(161,##FIELD,##SYM)
- #define _CACHE_MAR162_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(162,##FIELD,##SYM)
- #define _CACHE_MAR163_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(163,##FIELD,##SYM)
- #define _CACHE_MAR164_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(164,##FIELD,##SYM)
- #define _CACHE_MAR165_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(165,##FIELD,##SYM)
- #define _CACHE_MAR166_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(166,##FIELD,##SYM)
- #define _CACHE_MAR167_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(167,##FIELD,##SYM)
- #define _CACHE_MAR168_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(168,##FIELD,##SYM)
- #define _CACHE_MAR169_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(169,##FIELD,##SYM)
- #define _CACHE_MAR170_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(170,##FIELD,##SYM)
- #define _CACHE_MAR171_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(171,##FIELD,##SYM)
- #define _CACHE_MAR172_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(172,##FIELD,##SYM)
- #define _CACHE_MAR173_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(173,##FIELD,##SYM)
- #define _CACHE_MAR174_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(174,##FIELD,##SYM)
- #define _CACHE_MAR175_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(175,##FIELD,##SYM)
- #define _CACHE_MAR176_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(176,##FIELD,##SYM)
- #define _CACHE_MAR177_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(177,##FIELD,##SYM)
- #define _CACHE_MAR178_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(178,##FIELD,##SYM)
- #define _CACHE_MAR179_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(179,##FIELD,##SYM)
- #define _CACHE_MAR180_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(180,##FIELD,##SYM)
- #define _CACHE_MAR181_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(181,##FIELD,##SYM)
- #define _CACHE_MAR182_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(182,##FIELD,##SYM)
- #define _CACHE_MAR183_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(183,##FIELD,##SYM)
- #define _CACHE_MAR184_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(184,##FIELD,##SYM)
- #define _CACHE_MAR185_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(185,##FIELD,##SYM)
- #define _CACHE_MAR186_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(186,##FIELD,##SYM)
- #define _CACHE_MAR187_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(187,##FIELD,##SYM)
- #define _CACHE_MAR188_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(188,##FIELD,##SYM)
- #define _CACHE_MAR189_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(189,##FIELD,##SYM)
- #define _CACHE_MAR190_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(190,##FIELD,##SYM)
- #define _CACHE_MAR191_FSETS(FIELD,SYM) _CACHE_MAR_FSETS(191,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 W B A R |
-* |___________________|
-*
-* L2WBAR - L2 writeback base address register
-*
-* Fields:
-* (rw) L2WBAR
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2WBAR_ADDR 0x01844000u
-
- #define _CACHE_L2WBAR_L2WBAR_MASK 0xFFFFFFFFu
- #define _CACHE_L2WBAR_L2WBAR_SHIFT 0x00000000u
- #define CACHE_L2WBAR_L2WBAR_DEFAULT 0x00000000u
- #define CACHE_L2WBAR_L2WBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L2WBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L2WBAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2WBAR,L2WBAR) \
- )
-
- #define CACHE_L2WBAR_RMK(l2wbar) (Uint32)( \
- _PER_FMK(CACHE,L2WBAR,L2WBAR,l2wbar) \
- )
-
- #define _CACHE_L2WBAR_FGET(FIELD)\
- _PER_FGET(_CACHE_L2WBAR_ADDR,CACHE,L2WBAR,##FIELD)
-
- #define _CACHE_L2WBAR_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2WBAR_ADDR,CACHE,L2WBAR,##FIELD,field)
-
- #define _CACHE_L2WBAR_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2WBAR_ADDR,CACHE,L2WBAR,##FIELD,##SYM)
-#endif
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 W W C |
-* |___________________|
-*
-* L2WWC - L2 writeback word count register
-*
-* Fields:
-* (rw) L2WWC
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2WWC_ADDR 0x01844004u
-
- #define _CACHE_L2WWC_L2WWC_MASK 0x0000FFFFu
- #define _CACHE_L2WWC_L2WWC_SHIFT 0x00000000u
- #define CACHE_L2WWC_L2WWC_DEFAULT 0x00000000u
- #define CACHE_L2WWC_L2WWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L2WWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L2WWC_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2WWC,L2WWC) \
- )
-
- #define CACHE_L2WWC_RMK(l2wwc) (Uint32)( \
- _PER_FMK(CACHE,L2WWC,L2WWC,l2wwc) \
- )
-
- #define _CACHE_L2WWC_FGET(FIELD)\
- _PER_FGET(_CACHE_L2WWC_ADDR,CACHE,L2WWC,##FIELD)
-
- #define _CACHE_L2WWC_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2WWC_ADDR,CACHE,L2WWC,##FIELD,field)
-
- #define _CACHE_L2WWC_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2WWC_ADDR,CACHE,L2WWC,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 W I B A R |
-* |___________________|
-*
-* L2WIBAR - L2 writeback-invalidate base address register
-*
-* Fields:
-* (rw) L2WIBAR
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2WIBAR_ADDR 0x01844010u
-
- #define _CACHE_L2WIBAR_L2WIBAR_MASK 0xFFFFFFFFu
- #define _CACHE_L2WIBAR_L2WIBAR_SHIFT 0x00000000u
- #define CACHE_L2WIBAR_L2WIBAR_DEFAULT 0x00000000u
- #define CACHE_L2WIBAR_L2WIBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L2WIBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L2WIBAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2WIBAR,L2WIBAR) \
- )
-
- #define CACHE_L2WIBAR_RMK(l2wibar) (Uint32)( \
- _PER_FMK(CACHE,L2WIBAR,L2WIBAR,l2wibar) \
- )
-
- #define _CACHE_L2WIBAR_FGET(FIELD)\
- _PER_FGET(_CACHE_L2WIBAR_ADDR,CACHE,L2WIBAR,##FIELD)
-
- #define _CACHE_L2WIBAR_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2WIBAR_ADDR,CACHE,L2WIBAR,##FIELD,field)
-
- #define _CACHE_L2WIBAR_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2WIBAR_ADDR,CACHE,L2WIBAR,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 W I W C |
-* |___________________|
-*
-* L2WIWC - L2 writeback-invalidate word count register
-*
-* Fields:
-* (rw) L2WIWC
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2WIWC_ADDR 0x01844014u
-
- #define _CACHE_L2WIWC_L2WIWC_MASK 0x0000FFFFu
- #define _CACHE_L2WIWC_L2WIWC_SHIFT 0x00000000u
- #define CACHE_L2WIWC_L2WIWC_DEFAULT 0x00000000u
- #define CACHE_L2WIWC_L2WIWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L2WIWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L2WIWC_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2WIWC,L2WIWC) \
- )
-
- #define CACHE_L2WIWC_RMK(l2wiwc) (Uint32)( \
- _PER_FMK(CACHE,L2WIWC,L2WIWC,l2wiwc) \
- )
-
- #define _CACHE_L2WIWC_FGET(FIELD)\
- _PER_FGET(_CACHE_L2WIWC_ADDR,CACHE,L2WIWC,##FIELD)
-
- #define _CACHE_L2WIWC_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2WIWC_ADDR,CACHE,L2WIWC,##FIELD,field)
-
- #define _CACHE_L2WIWC_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2WIWC_ADDR,CACHE,L2WIWC,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* ___________________
-* | |
-* | L 2 I B A R |
-* |_________________|
-*
-* L2IBAR - L2 invalidate base address register
-*
-* Fields:
-* (rw) L2IBAR
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT && C64_SUPPORT)
- #define _CACHE_L2IBAR_ADDR 0x01844018u
-
- #define _CACHE_L2IBAR_L2IBAR_MASK 0xFFFFFFFFu
- #define _CACHE_L2IBAR_L2IBAR_SHIFT 0x00000000u
- #define CACHE_L2IBAR_L2IBAR_DEFAULT 0x00000000u
- #define CACHE_L2IBAR_L2IBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L2IBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L2IBAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2IBAR,L2IBAR) \
- )
-
- #define CACHE_L2IBAR_RMK(l2ibar) (Uint32)( \
- _PER_FMK(CACHE,L2IBAR,L2IBAR,l2ibar) \
- )
-
- #define _CACHE_L2IBAR_FGET(FIELD)\
- _PER_FGET(_CACHE_L2IBAR_ADDR,CACHE,L2IBAR,##FIELD)
-
- #define _CACHE_L2IBAR_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2IBAR_ADDR,CACHE,L2IBAR,##FIELD,field)
-
- #define _CACHE_L2IBAR_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2IBAR_ADDR,CACHE,L2IBAR,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* ___________________
-* | |
-* | L 2 I W C |
-* |_________________|
-*
-* L2IWC - L2 invalidate word count register
-*
-* Fields:
-* (rw) L2IWC
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT && C64_SUPPORT)
- #define _CACHE_L2IWC_ADDR 0x0184401Cu
-
- #define _CACHE_L2IWC_L2IWC_MASK 0x0000FFFFu
- #define _CACHE_L2IWC_L2IWC_SHIFT 0x00000000u
- #define CACHE_L2IWC_L2IWC_DEFAULT 0x00000000u
- #define CACHE_L2IWC_L2IWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L2IWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L2IWC_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2IWC,L2IWC) \
- )
-
- #define CACHE_L2IWC_RMK(l2iwc) (Uint32)( \
- _PER_FMK(CACHE,L2IWC,L2IWC,l2iwc) \
- )
-
- #define _CACHE_L2IWC_FGET(FIELD)\
- _PER_FGET(_CACHE_L2IWC_ADDR,CACHE,L2IWC,##FIELD)
-
- #define _CACHE_L2IWC_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2IWC_ADDR,CACHE,L2IWC,##FIELD,field)
-
- #define _CACHE_L2IWC_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2IWC_ADDR,CACHE,L2IWC,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 1 P I B A R |
-* |___________________|
-*
-* L1PIBAR - L1P invalidate base address register
-*
-* Fields:
-* (rw) L1PIBAR
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L1PIBAR_ADDR 0x01844020u
-
- #define _CACHE_L1PIBAR_L1PIBAR_MASK 0xFFFFFFFFu
- #define _CACHE_L1PIBAR_L1PIBAR_SHIFT 0x00000000u
- #define CACHE_L1PIBAR_L1PIBAR_DEFAULT 0x00000000u
- #define CACHE_L1PIBAR_L1PIBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L1PIBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L1PIBAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L1PIBAR,L1PIBAR) \
- )
-
- #define CACHE_L1PIBAR_RMK(l1pibar) (Uint32)( \
- _PER_FMK(CACHE,L1PIBAR,L1PIBAR,l1pibar) \
- )
-
- #define _CACHE_L1PIBAR_FGET(FIELD)\
- _PER_FGET(_CACHE_L1PIBAR_ADDR,CACHE,L1PIBAR,##FIELD)
-
- #define _CACHE_L1PIBAR_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L1PIBAR_ADDR,CACHE,L1PIBAR,##FIELD,field)
-
- #define _CACHE_L1PIBAR_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L1PIBAR_ADDR,CACHE,L1PIBAR,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 1 P I W C |
-* |___________________|
-*
-* L1PIWC - L1P invalidate word count register
-*
-* Fields:
-* (rw) L1PFWC
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L1PIWC_ADDR 0x01844024u
-
- #define _CACHE_L1PIWC_L1PIWC_MASK 0x0000FFFFu
- #define _CACHE_L1PIWC_L1PIWC_SHIFT 0x00000000u
- #define CACHE_L1PIWC_L1PIWC_DEFAULT 0x00000000u
- #define CACHE_L1PIWC_L1PIWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L1PIWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L1PIWC_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L1PIWC,L1PIWC) \
- )
-
- #define CACHE_L1PIWC_RMK(l1piwc) (Uint32)( \
- _PER_FMK(CACHE,L1PIWC,L1PIWC,l1piwc) \
- )
-
- #define _CACHE_L1PIWC_FGET(FIELD)\
- _PER_FGET(_CACHE_L1PIWC_ADDR,CACHE,L1PIWC,##FIELD)
-
- #define _CACHE_L1PIWC_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L1PIWC_ADDR,CACHE,L1PIWC,##FIELD,field)
-
- #define _CACHE_L1PIWC_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L1PIWC_ADDR,CACHE,L1PIWC,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 1 D W I B A R |
-* |___________________|
-*
-* L1DWIBAR - L1D writeback-invalidate base address register
-*
-* Fields:
-* (rw) L1DWIBAR
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L1DWIBAR_ADDR 0x01844030u
-
- #define _CACHE_L1DWIBAR_L1DWIBAR_MASK 0xFFFFFFFFu
- #define _CACHE_L1DWIBAR_L1DWIBAR_SHIFT 0x00000000u
- #define CACHE_L1DWIBAR_L1DWIBAR_DEFAULT 0x00000000u
- #define CACHE_L1DWIBAR_L1DWIBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DWIBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DWIBAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L1DWIBAR,L1DWIBAR) \
- )
-
- #define CACHE_L1DWIBAR_RMK(l1dwibar) (Uint32)( \
- _PER_FMK(CACHE,L1DWIBAR,L1DWIBAR,l1dwibar) \
- )
-
- #define _CACHE_L1DWIBAR_FGET(FIELD)\
- _PER_FGET(_CACHE_L1DWIBAR_ADDR,CACHE,L1DWIBAR,##FIELD)
-
- #define _CACHE_L1DWIBAR_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L1DWIBAR_ADDR,CACHE,L1DWIBAR,##FIELD,field)
-
- #define _CACHE_L1DWIBAR_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L1DWIBAR_ADDR,CACHE,L1DWIBAR,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 1 D W I W C |
-* |___________________|
-*
-* L1DWIWC - L1D writeback-invalidate word count register
-*
-* Fields:
-* (rw) L1DWIWC
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L1DWIWC_ADDR 0x01844034u
-
- #define _CACHE_L1DWIWC_L1DWIWC_MASK 0x0000FFFFu
- #define _CACHE_L1DWIWC_L1DWIWC_SHIFT 0x00000000u
- #define CACHE_L1DWIWC_L1DWIWC_DEFAULT 0x00000000u
- #define CACHE_L1DWIWC_L1DWIWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DWIWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DWIWC_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L1DWIWC,L1DWIWC) \
- )
-
- #define CACHE_L1DWIWC_RMK(l1dwiwc) (Uint32)( \
- _PER_FMK(CACHE,L1DWIWC,L1DWIWC,l1dwiwc) \
- )
-
- #define _CACHE_L1DWIWC_FGET(FIELD)\
- _PER_FGET(_CACHE_L1DWIWC_ADDR,CACHE,L1DWIWC,##FIELD)
-
- #define _CACHE_L1DWIWC_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L1DWIWC_ADDR,CACHE,L1DWIWC,##FIELD,field)
-
- #define _CACHE_L1DWIWC_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L1DWIWC_ADDR,CACHE,L1DWIWC,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* ___________________
-* | |
-* | L 1 D I B A R |
-* |_________________|
-*
-* L1DIBAR - L1D invalidate base address register
-*
-* Fields:
-* (rw) L1DIBAR
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT && C64_SUPPORT)
- #define _CACHE_L1DIBAR_ADDR 0x01844048u
-
- #define _CACHE_L1DIBAR_L1DIBAR_MASK 0xFFFFFFFFu
- #define _CACHE_L1DIBAR_L1DIBAR_SHIFT 0x00000000u
- #define CACHE_L1DIBAR_L1DIBAR_DEFAULT 0x00000000u
- #define CACHE_L1DIBAR_L1DIBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DIBAR_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DIBAR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L1DIBAR,L1DIBAR) \
- )
-
- #define CACHE_L1DIBAR_RMK(l1dibar) (Uint32)( \
- _PER_FMK(CACHE,L1DIBAR,L1DIBAR,l1dibar) \
- )
-
- #define _CACHE_L1DIBAR_FGET(FIELD)\
- _PER_FGET(_CACHE_L1DIBAR_ADDR,CACHE,L1DIBAR,##FIELD)
-
- #define _CACHE_L1DIBAR_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L1DIBAR_ADDR,CACHE,L1DIBAR,##FIELD,field)
-
- #define _CACHE_L1DIBAR_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L1DIBAR_ADDR,CACHE,L1DIBAR,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* ___________________
-* | |
-* | L 1 D I W C |
-* |_________________|
-*
-* L1DIWC - L1D invalidate word count register
-*
-* Fields:
-* (rw) L1DIWC
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT && C64_SUPPORT)
- #define _CACHE_L1DIWC_ADDR 0x0184404Cu
-
- #define _CACHE_L1DIWC_L1DIWC_MASK 0x0000FFFFu
- #define _CACHE_L1DIWC_L1DIWC_SHIFT 0x00000000u
- #define CACHE_L1DIWC_L1DIWC_DEFAULT 0x00000000u
- #define CACHE_L1DIWC_L1DIWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DIWC_OF(x) _VALUEOF(x)
-
- #define CACHE_L1DIWC_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L1DIWC,L1DIWC) \
- )
-
- #define CACHE_L1DIWC_RMK(l1diwc) (Uint32)( \
- _PER_FMK(CACHE,L1DIWC,L1DIWC,l1diwc) \
- )
-
- #define _CACHE_L1DIWC_FGET(FIELD)\
- _PER_FGET(_CACHE_L1DIWC_ADDR,CACHE,L1DIWC,##FIELD)
-
- #define _CACHE_L1DIWC_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L1DIWC_ADDR,CACHE,L1DIWC,##FIELD,field)
-
- #define _CACHE_L1DIWC_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L1DIWC_ADDR,CACHE,L1DIWC,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* _______________
-* | |
-* | L 2 W B |
-* |_____________|
-*
-* L2WB - L2 writeback all register
-*
-* Fields:
-* (rw) L2WB
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2WB_ADDR 0x01845000u
-
- #define _CACHE_L2WB_C_MASK 0x00000001u
- #define _CACHE_L2WB_C_SHIFT 0x00000000u
- #define CACHE_L2WB_C_DEFAULT 0x00000000u
- #define CACHE_L2WB_C_OF(x) _VALUEOF(x)
- #define CACHE_L2WB_C_NORMAL 0x00000000u
- #define CACHE_L2WB_C_FLUSH 0x00000001u
-
- #define CACHE_L2WB_OF(x) _VALUEOF(x)
-
- #define CACHE_L2WB_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2WB,C) \
- )
-
- #define CACHE_L2WB_RMK(c) (Uint32)( \
- _PER_FMK(CACHE,L2WB,C,c) \
- )
-
- #define _CACHE_L2WB_FGET(FIELD)\
- _PER_FGET(_CACHE_L2WB_ADDR,CACHE,L2WB,##FIELD)
-
- #define _CACHE_L2WB_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2WB_ADDR,CACHE,L2WB,##FIELD,field)
-
- #define _CACHE_L2WB_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2WB_ADDR,CACHE,L2WB,##FIELD,##SYM)
-#endif
-
-/******************************************************************************\
-* _____________________
-* | |
-* | L 2 W B I N V |
-* |___________________|
-*
-* L2WBINV - L2 writeback-invalidate all register
-*
-* Fields:
-* (rw) C
-*
-\******************************************************************************/
-#if (L2CACHE_SUPPORT)
- #define _CACHE_L2WBINV_ADDR 0x01845004u
-
- #define _CACHE_L2WBINV_C_MASK 0x00000001u
- #define _CACHE_L2WBINV_C_SHIFT 0x00000000u
- #define CACHE_L2WBINV_C_DEFAULT 0x00000000u
- #define CACHE_L2WBINV_C_OF(x) _VALUEOF(x)
- #define CACHE_L2WBINV_C_NORMAL 0x00000000u
- #define CACHE_L2WBINV_C_CLEAN 0x00000001u
-
- #define CACHE_L2WBINV_OF(x) _VALUEOF(x)
-
- #define CACHE_L2WBINV_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CACHE,L2WBINV,C) \
- )
-
- #define CACHE_L2WBINV_RMK(c) (Uint32)( \
- _PER_FMK(CACHE,L2WBINV,C,c) \
- )
-
- #define _CACHE_L2WBINV_FGET(FIELD)\
- _PER_FGET(_CACHE_L2WBINV_ADDR,CACHE,L2WBINV,##FIELD)
-
- #define _CACHE_L2WBINV_FSET(FIELD,field)\
- _PER_FSET(_CACHE_L2WBINV_ADDR,CACHE,L2WBINV,##FIELD,field)
-
- #define _CACHE_L2WBINV_FSETS(FIELD,SYM)\
- _PER_FSETS(_CACHE_L2WBINV_ADDR,CACHE,L2WBINV,##FIELD,##SYM)
-#endif
-
-/*----------------------------------------------------------------------------*/
-
-#endif /* CACHE_SUPPORT */
-#endif /* _CSL_CACHEHAL_H_ */
-/******************************************************************************\
-* End of csl_cachehal.h
-\******************************************************************************/
-
diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_chip.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_chip.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/******************************************************************************\
-* Copyright (C) 1999-2001 Texas Instruments Incorporated.
-* All Rights Reserved
-*------------------------------------------------------------------------------
-* FILENAME...... csl_chip.h
-* DATE CREATED.. 08/19/1999
-* LAST MODIFIED. 08/02/2004 - Adding support for C6418
-* 06/17/2003 - Added support for 6712C
-* 06/09/2003 - Added support for 6711C
-* 12/03/2001 - CHIP_configArgs
-* 11/08/2001 - CHIP_getSiliconRevId()
-* - CHIP_config() / CHIP_getConfig DM642
-\******************************************************************************/
-#ifndef _CSL_CHIP_H_
-#define _CSL_CHIP_H_
-
-#include <csl_stdinc.h>
-
-#include <csl_chiphal.h>
-#include <csl_emifhal.h>
-
-/******************************************************************************\
-* scope and inline control macros
-\******************************************************************************/
-#ifdef __cplusplus
-#define CSLAPI extern "C" far
-#else
-#define CSLAPI extern far
-#endif
-
-#undef USEDEFS
-#undef IDECL
-#undef IDEF
-
-#ifdef _CHIP_MOD_
- #define IDECL CSLAPI
- #define USEDEFS
- #define IDEF
-#else
- #ifdef _INLINE
- #define IDECL static inline
- #define USEDEFS
- #define IDEF static inline
- #else
- #define IDECL CSLAPI
- #endif
-#endif
-
-
-/******************************************************************************\
-* global macro declarations
-\******************************************************************************/
-#define CHIP_ENDIAN_BIG 0
-#define CHIP_ENDIAN_LITTLE 1
-
-#define CHIP_MAP_0 0
-#define CHIP_MAP_1 1
-
-/* Selected devices masks*/
-#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C)
-#define CHIP_EKSRC_SYSCLK3 0x00000000u
-#define CHIP_EKSRC_ECLKIN 0x00000010u
-#endif
-
-#if (CHIP_6713 || CHIP_DA610)
-#define CHIP_TOUT1 0x00000000u
-#define CHIP_AXR04_AXR111 0x00000008u
-
-#define CHIP_TOUT0 0x00000000u
-#define CHIP_AXR02_AXR113 0x00000004u
-
-#define CHIP_MCASP0 0x00000002u
-#define CHIP_MCBSP0 0x00000000u
-
-#define CHIP_I2C1 0x00000001u
-#define CHIP_MCBSP1 0x00000000u
-/* Full mask value */
-#define _CHIP_DEVCFG_MASK 0x0000001Fu
-#endif
-
-#if CHIP_DM642
-#define CHIP_VP2 0x00000040u
-#define CHIP_VP1 0x00000020u
-#define CHIP_VP0 0x00000010u
-#define CHIP_I2C 0x00000008u
-#define CHIP_MCBSP1 0x00000004u
-#define CHIP_MCBSP0 0x00000002u
-#define CHIP_MCASP0 0x00000001u
-
-#define _CHIP_PERCFG_MASK 0x0000007Fu
-#endif
-
-#if CHIP_DM641
-#define CHIP_VP1 0x00000020u
-#define CHIP_VP0 0x00000010u
-#define CHIP_I2C 0x00000008u
-#define CHIP_MCBSP1 0x00000004u
-#define CHIP_MCBSP0 0x00000002u
-#define CHIP_MCASP0 0x00000001u
-
-#define _CHIP_PERCFG_MASK 0x0000003Fu
-#endif
-
-#if CHIP_DM640
-#define CHIP_VP0 0x00000010u
-#define CHIP_I2C 0x00000008u
-#define CHIP_MCBSP1 0x00000004u
-#define CHIP_MCBSP0 0x00000002u
-#define CHIP_MCASP0 0x00000001u
-
-#define _CHIP_PERCFG_MASK 0x0000001Fu
-#endif
-
-#if CHIP_6412
-#define CHIP_I2C 0x00000008u
-#define CHIP_MCBSP1 0x00000004u
-#define CHIP_MCBSP0 0x00000002u
-#define _CHIP_PERCFG_MASK 0x0000000Eu
-#endif
-
-#if (CHIP_6410 || CHIP_6413 || CHIP_6418)
-#define CHIP_AFCMUX 0x00000600u
-#define CHIP_MCASP1 0x00000100u
-#define CHIP_I2C1 0x00000080u
-#define CHIP_I2C0 0x00000008u
-#define CHIP_MCBSP1 0x00000004u
-#define CHIP_MCBSP0 0x00000002u
-#define CHIP_MCASP0 0x00000001u
-
-#define _CHIP_PERCFG_MASK 0x0000078Fu
-#endif
-
-/******************************************************************************\
-* global typedef declarations
-\******************************************************************************/
-#if( CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713 )
-typedef struct{
- Uint32 devcfg;
-} CHIP_Config;
-#elif (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418)
-typedef struct{
- Uint32 percfg;
-} CHIP_Config;
-#endif
-/******************************************************************************\
-* global variable declarations
-\******************************************************************************/
-
-
-/******************************************************************************\
-* global function declarations
-\******************************************************************************/
-
-
-/******************************************************************************\
-* inline function declarations
-\******************************************************************************/
-IDECL Uint32 CHIP_getCpuId();
-IDECL Uint32 CHIP_getRevId();
-IDECL Uint32 CHIP_getSiliconRevId();
-IDECL int CHIP_getEndian();
-IDECL int CHIP_getMapMode();
-
-#if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418)
-IDECL void CHIP_config(CHIP_Config *config);
-IDECL void CHIP_configArgs(Uint32 percfg);
-IDECL void CHIP_getConfig(CHIP_Config *config);
-#elif ( CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713 )
-IDECL void CHIP_config(CHIP_Config *config);
-IDECL void CHIP_configArgs(Uint32 devcfg);
-IDECL void CHIP_getConfig(CHIP_Config *config);
-#endif
-
-/******************************************************************************\
-* inline function definitions
-\******************************************************************************/
-#ifdef USEDEFS
-/*----------------------------------------------------------------------------*/
-IDEF Uint32 CHIP_getCpuId() {
- return CHIP_FGET(CSR,CPUID);
-}
-/*----------------------------------------------------------------------------*/
-IDEF Uint32 CHIP_getRevId() {
- return CHIP_FGET(CSR,REVID);
-}
-/*----------------------------------------------------------------------------*/
-IDEF Uint32 CHIP_getSiliconRevId() {
- return (( 0x000F0000 & REG32(0x01B00200))>>16);
-}
-/*----------------------------------------------------------------------------*/
-IDEF int CHIP_getEndian() {
- return CHIP_FGET(CSR,EN);
-}
-/*----------------------------------------------------------------------------*/
-IDEF int CHIP_getMapMode() {
- int mapmode = 0;
- #if (!C11_SUPPORT && !C64_SUPPORT)
- mapmode = EMIF_FGET(GBLCTL,MAP);
- #endif
- return mapmode;
-}
-/*----------------------------------------------------------------------------*/
-#if (CHIP_6713 || CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_DA610 || CHIP_6412 || CHIP_6711C || CHIP_6712C || CHIP_6410 || CHIP_6413 || CHIP_6418)
-IDEF void CHIP_config(CHIP_Config *config) {
- Uint32 gie = CHIP_FGET(CSR,GIE);
-
-#if( CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713 )
- volatile Uint32 *base = (volatile Uint32 *)(_CHIP_DEVCFG_ADDR);
- register int x0;
- CHIP_FSET(CSR,GIE,0);
- x0 = config->devcfg;
- base[_CHIP_DEVCFG_OFFSET] = x0;
- CHIP_FSET(CSR,GIE,gie);
-
-#else
- volatile Uint32 *base = (volatile Uint32 *)(_CHIP_PERCFG_ADDR);
- register int x0;
- CHIP_FSET(CSR,GIE,0);
- CHIP_FSETS(PCFGLOCK,LOCK,UNLOCK);
- x0 = config->percfg;
- base[_CHIP_PERCFG_OFFSET] = x0;
- CHIP_FSET(CSR,GIE,gie);
-
-#endif
-}
-#endif
-/*----------------------------------------------------------------------------*/
-#if (CHIP_6713 || CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_DA610 || CHIP_6412 || CHIP_6711C || CHIP_6712C || CHIP_6410 || CHIP_6413 || CHIP_6418)
-IDEF void CHIP_getConfig(CHIP_Config *config) {
- Uint32 gie = CHIP_FGET(CSR,GIE);
-
-#if( CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713 )
- volatile Uint32 *base = (volatile Uint32 *)(_CHIP_DEVCFG_ADDR);
- register int x0;
-
- CHIP_FSET(CSR,GIE,0);
-
- x0 = base[_CHIP_DEVCFG_OFFSET];
- config->devcfg=x0;
-
- CHIP_FSET(CSR,GIE,gie);
-
-#else
- volatile Uint32 *base = (volatile Uint32 *)(_CHIP_PERCFG_ADDR);
- register int x0;
-
- CHIP_FSET(CSR,GIE,0);
-
- x0 = base[_CHIP_PERCFG_OFFSET];
- config->percfg=x0;
-
- CHIP_FSET(CSR,GIE,gie);
-
-#endif
-}
-#endif
-/*----------------------------------------------------------------------------*/
-
-#if( CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713 )
- IDEF void CHIP_configArgs(Uint32 devcfg) {
- Uint32 gie = CHIP_FGET(CSR,GIE);
- volatile Uint32 *base = (volatile Uint32 *)(_CHIP_DEVCFG_ADDR);
- CHIP_FSET(CSR,GIE,0);
- base[_CHIP_DEVCFG_OFFSET]= devcfg;
- CHIP_FSET(CSR,GIE,gie);
-}
-#elif (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418)
- IDEF void CHIP_configArgs(Uint32 percfg) {
- Uint32 gie = CHIP_FGET(CSR,GIE);
- volatile Uint32 *base = (volatile Uint32 *)(_CHIP_PERCFG_ADDR);
-
- CHIP_FSET(CSR,GIE,0);
-
-#if(CHIP_DM642 || CHIP_6412)
- CHIP_FSETS(PCFGLOCK,LOCK,UNLOCK);
-#endif
-
- base[_CHIP_PERCFG_OFFSET]= percfg;
-
- CHIP_FSET(CSR,GIE,gie);
-}
-#endif
-
-
-/*----------------------------------------------------------------------------*/
-#endif /* USEDEFS */
-
-
-#endif /* _CSL_CHIP_H_ */
-/******************************************************************************\
-* End of csl_chip.h
-\******************************************************************************/
-
diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_chiphal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_chiphal.h
+++ /dev/null
@@ -1,1797 +0,0 @@
-/******************************************************************************\
-* Copyright (C) 2000 Texas Instruments Incorporated.
-* All Rights Reserved
-*------------------------------------------------------------------------------
-* FILENAME...... csl_chiphal.h
-* DATE CREATED.. 14 Aug 2000
-* LAST MODIFIED. 14 Jan 2004 Adding support for DRI300 versions (6410, 6413)
-* 05 Aug 2003 Removing external control cregisters EM,ER,IN,OUT and DIER.
-* 26 Jun 2003 Added support for 6411
-* 17 Jun 2003 Added support for 6712C
-* 28 May 2003 Added support for 6711C
-* 05 Nov 2001 DM642 , 6411 remove 6400
-* 03 Oct 2001 - CHIP_6713 - MCASP_SUPPORT - IIC_SUPPORT
-* - PERCFG register
-* - redefinition of CHIP_RSET() / CHIP_RGET()
-* - new CHIP_CRSET() / CHIP_CRGET() => modification of csl_irq.h
-* 04 Apr 2004- Removing external control cregisters EM,ER,IN,OUT and DIER.
-* 12 Jan 2005- Removing external control cregisters FMCR,FADCR,FAUCR and GFPGFR
-* 06 Apr 2005- Removing the macros ATLEN,ATLMEN and ADIV according to data manual
-* tms320c6410(13)-sprs247 dated: Feb26 2004 specifications.
-* 26 Jul 2005- Added C++ support.
-*------------------------------------------------------------------------------
-* REGISTERS
-*
-* CSR - control/status register
-* IFR - interrupt flag register
-* ISR - interrupt set register
-* ICR - interrupt clear register
-* IER - interrupt enable register
-* ISTP - interrupt service table pointer register
-* IRP - interrupt return pointer
-* NRP - non-maskable interrupt return pointer
-* AMR - addressing mode reister
-* PERCFG - Device Configuration register (4)
-* DEVSTAT - Device Status Register (5)
-* JTAGID - JTAG ID register (5)
-*
-* (1) only supported on 67xx
-* (2) only supported on floating point devices
-* (3) only supported on 6411/14/15/16 devices
-* (4) only supported on 6713/DA610/DM642/6412/6711C/6712C devices
-* (5) only supported on DM642/6412/6410/6413 devices
-*
-\******************************************************************************/
-#ifndef _CSL_CHIPHAL_H_
-#define _CSL_CHIPHAL_H_
-
-#include <csl_stdinc.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/******************************************************************************\
-* CHIP identification section
-\******************************************************************************/
-#ifdef CHIP_BASELINE
- #undef CHIP_BASELINE
- #define CHIP_BASELINE 1
-#else
- #define CHIP_BASELINE 0
-#endif
-
-#if (CHIP_BASELINE)
- #define CHIP_6201 1
-#endif
-
-#ifdef CHIP_6201
- #undef CHIP_6201
- #define CHIP_6201 1
-#else
- #define CHIP_6201 0
-#endif
-
-#ifdef CHIP_6202
- #undef CHIP_6202
- #define CHIP_6202 1
-#else
- #define CHIP_6202 0
-#endif
-
-#ifdef CHIP_6203
- #undef CHIP_6203
- #define CHIP_6203 1
-#else
- #define CHIP_6203 0
-#endif
-
-#ifdef CHIP_6204
- #undef CHIP_6204
- #define CHIP_6204 1
-#else
- #define CHIP_6204 0
-#endif
-
-#ifdef CHIP_6205
- #undef CHIP_6205
- #define CHIP_6205 1
-#else
- #define CHIP_6205 0
-#endif
-
-#ifdef CHIP_6211
- #undef CHIP_6211
- #define CHIP_6211 1
-#else
- #define CHIP_6211 0
-#endif
-
-#ifdef CHIP_6701
- #undef CHIP_6701
- #define CHIP_6701 1
-#else
- #define CHIP_6701 0
-#endif
-
-#ifdef CHIP_6711
- #undef CHIP_6711
- #define CHIP_6711 1
-#else
- #define CHIP_6711 0
-#endif
-
-#ifdef CHIP_6712
- #undef CHIP_6712
- #define CHIP_6712 1
-#else
- #define CHIP_6712 0
-#endif
-
-
-#ifdef CHIP_6713
- #undef CHIP_6713
- #define CHIP_6713 1
-#else
- #define CHIP_6713 0
-#endif
-
-#ifdef CHIP_DA610
- #undef CHIP_DA610
- #define CHIP_DA610 1
-#else
- #define CHIP_DA610 0
-#endif
-
-#ifdef CHIP_DM642
- #undef CHIP_DM642
- #define CHIP_DM642 1
-#else
- #define CHIP_DM642 0
-#endif
-
-#ifdef CHIP_DM641
- #undef CHIP_DM641
- #define CHIP_DM641 1
-#else
- #define CHIP_DM641 0
-#endif
-
-#ifdef CHIP_DM640
- #undef CHIP_DM640
- #define CHIP_DM640 1
-#else
- #define CHIP_DM640 0
-#endif
-
-#ifdef CHIP_6412
- #undef CHIP_6412
- #define CHIP_6412 1
-#else
- #define CHIP_6412 0
-#endif
-
-#ifdef CHIP_6414
- #undef CHIP_6414
- #define CHIP_6414 1
-#else
- #define CHIP_6414 0
-#endif
-
-#ifdef CHIP_6415
- #undef CHIP_6415
- #define CHIP_6415 1
-#else
- #define CHIP_6415 0
-#endif
-
-#ifdef CHIP_6416
- #undef CHIP_6416
- #define CHIP_6416 1
-#else
- #define CHIP_6416 0
-#endif
-
-#ifdef CHIP_6711C
- #undef CHIP_6711C
- #define CHIP_6711C 1
-#else
- #define CHIP_6711C 0
-#endif
-
-#ifdef CHIP_6712C
- #undef CHIP_6712C
- #define CHIP_6712C 1
-#else
- #define CHIP_6712C 0
-#endif
-
-#ifdef CHIP_6411
- #undef CHIP_6411
- #define CHIP_6411 1
-#else
- #define CHIP_6411 0
-#endif
-
-/* next two are DRI300 versions */
-#ifdef CHIP_6410
- #undef CHIP_6410
- #define CHIP_6410 1
-#else
- #define CHIP_6410 0
-#endif
-
-#ifdef CHIP_6413
- #undef CHIP_6413
- #define CHIP_6413 1
-#else
- #define CHIP_6413 0
-#endif
-
-#ifdef CHIP_6418
- #undef CHIP_6418
- #define CHIP_6418 1
-#else
- #define CHIP_6418 0
-#endif\r
-\r
-/* Adding for DM6446 */\r
-#ifdef CHIP_DM6446
- #undef CHIP_DM6446
- #define CHIP_DM6446 1
-#else
- #define CHIP_DM6446 0
-#endif\r
-
-
-#define CHIP_OROFALL (\
- CHIP_6201 | \
- CHIP_6202 | \
- CHIP_6203 | \
- CHIP_6204 | \
- CHIP_6205 | \
- CHIP_6211 | \
- CHIP_6701 | \
- CHIP_6711 | \
- CHIP_6712 | \
- CHIP_6713 | \
- CHIP_DA610 | \
- CHIP_DM642 | \
- CHIP_DM641 | \
- CHIP_DM640 | \
- CHIP_6412 | \
- CHIP_6414 | \
- CHIP_6415 | \
- CHIP_6416 | \
- CHIP_6711C | \
- CHIP_6712C | \
- CHIP_6411 |\
- CHIP_6410 |\
- CHIP_6413 |\
- CHIP_6418 \
-)
-
-#if (CHIP_OROFALL==0)
- #error NO CHIP DEFINED (use -dCHIP_XXXX where XXXX is chip number, i.e. 6201)
-#endif
-
-#define CHIP_NONE 0
-
-#define CHIP_SUPPORT(c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24) ( \
- ( c0*CHIP_6201) | \
- ( c1*CHIP_6202) | \
- ( c2*CHIP_6203) | \
- ( c3*CHIP_6204) | \
- ( c4*CHIP_6205) | \
- ( c5*CHIP_6211) | \
- ( c6*CHIP_6701) | \
- ( c7*CHIP_6711) | \
- ( c8*CHIP_6712) | \
- ( c9*CHIP_6713) | \
- ( c10*CHIP_DA610)| \
- ( c11*CHIP_DM642)| \
- ( c12*CHIP_DM641)| \
- ( c13*CHIP_DM640)| \
- ( c14*CHIP_6412) | \
- ( c15*CHIP_6414) | \
- ( c16*CHIP_6415) | \
- ( c17*CHIP_6416) | \
- ( c18*CHIP_6711C) | \
- ( c19*CHIP_6712C) | \
- ( c20*CHIP_6411) | \
- ( c21*CHIP_6410) | \
- ( c22*CHIP_6413) | \
- ( c23*CHIP_6418) | \
- ( c24*CHIP_NONE) \
- )
-
-/*---------------------------------------------------------------------------------------*/
-/* 6 6 6 6 6 6 6 6 6 6 D D D D 6 6 6 6 6 6 6 6 6 6 N */
-/* 2 2 2 2 2 2 7 7 7 7 A M M M 4 4 4 4 7 7 4 4 4 4 O */
-/* 0 0 0 0 0 1 0 1 1 1 6 6 6 6 1 1 1 1 1 1 1 1 1 1 N */
-/* 1 2 3 4 5 1 1 1 2 3 1 4 4 4 2 4 5 6 1 2 1 0 3 8 E */
-/* 0 2 1 0 C C */
-/*---------------------------------------------------------------------------------------*/
-#define CACHE_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
-#define DMA_SUPPORT CHIP_SUPPORT(1,1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
-#define EDMA_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
-#define EMIF_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0)
-#define EMIFA_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,1,1,1,1,0)
-#define EMIFB_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0)
-#define GPIO_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
-#define HPI_SUPPORT CHIP_SUPPORT(1,0,0,0,0,1,1,1,0,1,1,1,1,0,1,1,1,1,1,0,1,1,1,1,0)
-#define I2C_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,1,1,1,0)
-#define IRQ_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
-#define MCASP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,0)
-#define MCBSP_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
-#define PLL_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0)
-#define TIMER_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
-#define XBUS_SUPPORT CHIP_SUPPORT(0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
-#define PCI_SUPPORT CHIP_SUPPORT(0,0,0,0,1,0,0,0,0,0,0,1,0,0,1,0,1,1,0,0,1,0,0,0,0)
-/*---------------------------------------------------------------------------------------*/
-/* 6 6 6 6 6 6 6 6 6 6 D D D D 6 6 6 6 6 6 6 6 6 6 N */
-/* 2 2 2 2 2 2 7 7 7 7 A M M M 4 4 4 4 7 7 4 4 4 4 O */
-/* 0 0 0 0 0 1 0 1 1 1 6 6 6 6 1 1 1 1 1 1 1 1 1 1 N */
-/* 1 2 3 4 5 1 1 1 2 3 1 4 4 4 2 4 5 6 1 2 1 0 3 8 E */
-/* 0 2 1 0 C C */
-/*---------------------------------------------------------------------------------------*/
-#define VP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
-#define VIC_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
-#define DAT_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
-#define PWR_SUPPORT CHIP_SUPPORT(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
-#define UTOP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0)
-#define TCP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0)
-#define VCP_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,0)
-#define EMAC_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0)
-#define MDIO_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0)
-#define EMU_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0)
-
-#define L2CACHE_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
-#define TC_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0)
-#define FPU_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0)
-#define C01_SUPPORT CHIP_SUPPORT(1,1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
-#define C11_SUPPORT CHIP_SUPPORT(0,0,0,0,0,1,0,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0,0,0)
-#define C64_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,1,1,1,1,0)
-#define ATL_SUPPORT CHIP_SUPPORT(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,0)
-
-#define CACHE_L2_SUPPORT L2CACHE_SUPPORT
-/*----------------------------------------------------------------------*/
-
-
-/******************************************************************************\
-* module level register/field access macros
-\******************************************************************************/
-
- /* ----------------- */
- /* FIELD MAKE MACROS */
- /* ----------------- */
-
- #define CHIP_FMK(REG,FIELD,x)\
- _PER_FMK(CHIP,##REG,##FIELD,x)
-
- #define CHIP_FMKS(REG,FIELD,SYM)\
- _PER_FMKS(CHIP,##REG,##FIELD,##SYM)
-
-
- /* -------------------------------- */
- /* RAW REGISTER/FIELD ACCESS MACROS */
- /* -------------------------------- */
-
- #define CHIP_CRGET(REG)\
- _PER_CRGET(CHIP,##REG)
-
- #define CHIP_CRSET(REG,x)\
- _PER_CRSET(CHIP,##REG,x)
-
- #define CHIP_RGET(REG)\
- _PER_RGET(_CHIP_##REG##_ADDR,CHIP,##REG)
-
- #define CHIP_RSET(REG,x)\
- _PER_RSET(_CHIP_##REG##_ADDR,CHIP,##REG,x)
-
-
- #define CHIP_FGET(REG,FIELD)\
- _CHIP_##REG##_FGET(##FIELD)
-
- #define CHIP_FSET(REG,FIELD,x)\
- _CHIP_##REG##_FSET(##FIELD,x)
-
- #define CHIP_FSETS(REG,FIELD,SYM)\
- _CHIP_##REG##_FSETS(##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | C S R |
-* |___________________|
-*
-* CSR - control/status register
-*
-* FIELDS (msb -> lsb)
-* (r) CPUID
-* (r) REVID
-* (rw) PWRD
-* (rc) SAT
-* (r) EN
-* (rw) PCC
-* (rw) DCC
-* (rw) PGIE
-* (rw) GIE
-*
-\******************************************************************************/
- extern far cregister volatile unsigned int CSR;
-
- #define _CHIP_CSR_CPUID_MASK 0xFF000000u
- #define _CHIP_CSR_CPUID_SHIFT 0x00000018u
- #define CHIP_CSR_CPUID_DEFAULT 0x00000000u
- #define CHIP_CSR_CPUID_OF(x) _VALUEOF(x)
- #define CHIP_CSR_CPUID_C62X 0x00000000u
- #define CHIP_CSR_CPUID_C67X 0x00000002u
- #define CHIP_CSR_CPUID_C64X 0x00000004u
-
- #define _CHIP_CSR_REVID_MASK 0x00FF0000u
- #define _CHIP_CSR_REVID_SHIFT 0x00000010u
- #define CHIP_CSR_REVID_DEFAULT 0x00000000u
- #define CHIP_CSR_REVID_OF(x) _VALUEOF(x)
- #define CHIP_CSR_REVID_620120 0x00000001u
- #define CHIP_CSR_REVID_620121 0x00000001u
- #define CHIP_CSR_REVID_620130 0x00000002u
- #define CHIP_CSR_REVID_670100 0x00000201u
- #define CHIP_CSR_REVID_670110 0x00000202u
- #define CHIP_CSR_REVID_621110 0x00000002u
- #define CHIP_CSR_REVID_640010 0x00000801u
- #define CHIP_CSR_REVID_6202 0x00000002u
- #define CHIP_CSR_REVID_6202B 0x00000003u
- #define CHIP_CSR_REVID_6711 0x00000002u
- #define CHIP_CSR_REVID_6711C 0x00000003u
- #define CHIP_CSR_REVID_6712 0x00000002u
- #define CHIP_CSR_REVID_6712C 0x00000003u
-
- #define _CHIP_CSR_PWRD_MASK 0x0000FC00u
- #define _CHIP_CSR_PWRD_SHIFT 0x0000000Au
- #define CHIP_CSR_PWRD_DEFAULT 0x00000000u
- #define CHIP_CSR_PWRD_OF(x) _VALUEOF(x)
- #define CHIP_CSR_PWRD_NONE 0x00000000u
- #define CHIP_CSR_PWRD_PD1A 0x00000009u
- #define CHIP_CSR_PWRD_PD1B 0x00000011u
- #define CHIP_CSR_PWRD_PD2 0x0000001Au
- #define CHIP_CSR_PWRD_PD3 0x0000001Cu
-
- #define _CHIP_CSR_SAT_MASK 0x00000200u
- #define _CHIP_CSR_SAT_SHIFT 0x00000009u
- #define CHIP_CSR_SAT_DEFAULT 0x00000000u
- #define CHIP_CSR_SAT_OF(x) _VALUEOF(x)
- #define CHIP_CSR_SAT_0 0x00000000u
- #define CHIP_CSR_SAT_1 0x00000001u
-
- #define _CHIP_CSR_EN_MASK 0x00000100u
- #define _CHIP_CSR_EN_SHIFT 0x00000008u
- #define CHIP_CSR_EN_DEFAULT 0x00000000u
- #define CHIP_CSR_EN_OF(x) _VALUEOF(x)
- #define CHIP_CSR_EN_BIG 0x00000000u
- #define CHIP_CSR_EN_LITTLE 0x00000001u
-
- #define _CHIP_CSR_PCC_MASK 0x000000E0u
- #define _CHIP_CSR_PCC_SHIFT 0x00000005u
- #define CHIP_CSR_PCC_DEFAULT 0x00000000u
- #define CHIP_CSR_PCC_OF(x) _VALUEOF(x)
- #define CHIP_CSR_PCC_MAPPED 0x00000000u
- #define CHIP_CSR_PCC_ENABLE 0x00000002u
- #define CHIP_CSR_PCC_FREEZE 0x00000003u
- #define CHIP_CSR_PCC_BYPASS 0x00000004u
-
- #define _CHIP_CSR_DCC_MASK 0x0000001Cu
- #define _CHIP_CSR_DCC_SHIFT 0x00000002u
- #define CHIP_CSR_DCC_DEFAULT 0x00000000u
- #define CHIP_CSR_DCC_OF(x) _VALUEOF(x)
- #define CHIP_CSR_DCC_MAPPED 0x00000000u
- #define CHIP_CSR_DCC_ENABLE 0x00000002u
- #define CHIP_CSR_DCC_FREEZE 0x00000003u
- #define CHIP_CSR_DCC_BYPASS 0x00000004u
-
- #define _CHIP_CSR_PGIE_MASK 0x00000002u
- #define _CHIP_CSR_PGIE_SHIFT 0x00000001u
- #define CHIP_CSR_PGIE_DEFAULT 0x00000000u
- #define CHIP_CSR_PGIE_OF(x) _VALUEOF(x)
- #define CHIP_CSR_PGIE_0 0x00000000u
- #define CHIP_CSR_PGIE_1 0x00000001u
-
- #define _CHIP_CSR_GIE_MASK 0x00000001u
- #define _CHIP_CSR_GIE_SHIFT 0x00000000u
- #define CHIP_CSR_GIE_DEFAULT 0x00000000u
- #define CHIP_CSR_GIE_OF(x) _VALUEOF(x)
- #define CHIP_CSR_GIE_0 0x00000000u
- #define CHIP_CSR_GIE_1 0x00000001u
-
- #define CHIP_CSR_OF(x) _VALUEOF(x)
-
- #define CHIP_CSR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,CSR,CPUID) \
- |_PER_FDEFAULT(CHIP,CSR,REVID) \
- |_PER_FDEFAULT(CHIP,CSR,PWRD) \
- |_PER_FDEFAULT(CHIP,CSR,SAT) \
- |_PER_FDEFAULT(CHIP,CSR,EN) \
- |_PER_FDEFAULT(CHIP,CSR,PCC) \
- |_PER_FDEFAULT(CHIP,CSR,DCC) \
- |_PER_FDEFAULT(CHIP,CSR,PGIE) \
- |_PER_FDEFAULT(CHIP,CSR,GIE) \
- )
-
- #define CHIP_CSR_RMK(pwrd,pcc,dcc,pgie,gie) (Uint32)( \
- _PER_FMK(CHIP,CSR,PWRD,pwrd) \
- |_PER_FMK(CHIP,CSR,PCC,pcc) \
- |_PER_FMK(CHIP,CSR,DCC,dcc) \
- |_PER_FMK(CHIP,CSR,PGIE,pgie) \
- |_PER_FMK(CHIP,CSR,GIE,gie) \
- )
-
- #define _CHIP_CSR_FGET(FIELD)\
- _PER_CFGET(CHIP,CSR,##FIELD)
-
- #define _CHIP_CSR_FSET(FIELD,field)\
- _PER_CFSET(CHIP,CSR,##FIELD,field)
-
- #define _CHIP_CSR_FSETS(FIELD,SYM)\
- _PER_CFSETS(CHIP,CSR,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | I F R |
-* |___________________|
-*
-* IFR - interruppt flag register
-*
-* FIELDS (msb -> lsb)
-* (rw) IF
-*
-\******************************************************************************/
- extern far cregister volatile unsigned int IFR;
-
- #define _CHIP_IFR_IF_MASK 0x0000FFFFu
- #define _CHIP_IFR_IF_SHIFT 0x00000000u
- #define CHIP_IFR_IF_DEFAULT 0x00000000u
- #define CHIP_IFR_IF_OF(x) _VALUEOF(x)
-
- #define CHIP_IFR_OF(x) _VALUEOF(x)
-
- #define CHIP_IFR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,IFR,IF)\
- )
-
- #define CHIP_IFR_RMK(if) (Uint32)( \
- _PER_FMK(CHIP,IFR,IF,if)\
- )
-
- #define _CHIP_IFR_FGET(FIELD)\
- _PER_CFGET(CHIP,IFR,##FIELD)
-
- #define _CHIP_IFR_FSET(FIELD,field)\
- _PER_CFSET(CHIP,IFR,##FIELD,field)
-
- #define _CHIP_IFR_FSETS(FIELD,SYM)\
- _PER_CFSETS(CHIP,IFR,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | I S R |
-* |___________________|
-*
-* ISR - interruppt set register
-*
-* FIELDS (msb -> lsb)
-* (w) IS
-*
-\******************************************************************************/
- extern far cregister volatile unsigned int ISR;
-
- #define _CHIP_ISR_IS_MASK 0x0000FFFFu
- #define _CHIP_ISR_IS_SHIFT 0x00000000u
- #define CHIP_ISR_IS_DEFAULT 0x00000000u
- #define CHIP_ISR_IS_OF(x) _VALUEOF(x)
-
- #define CHIP_ISR_OF(x) _VALUEOF(x)
-
- #define CHIP_ISR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,ISR,IS)\
- )
-
- #define CHIP_ISR_RMK(is) (Uint32)( \
- _PER_FMK(CHIP,ISR,IS,is)\
- )
-
- #define _CHIP_ISR_FGET(FIELD)\
- _PER_CFGET(CHIP,ISR,##FIELD)
-
- #define _CHIP_ISR_FSET(FIELD,field)\
- _PER_CFSET(CHIP,ISR,##FIELD,field)
-
- #define _CHIP_ISR_FSETS(FIELD,SYM)\
- _PER_CFSETS(CHIP,ISR,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | I C R |
-* |___________________|
-*
-* ICR - interruppt clear register
-*
-* FIELDS (msb -> lsb)
-* (w) IC
-*
-\******************************************************************************/
- extern far cregister volatile unsigned int ICR;
-
- #define _CHIP_ICR_IC_MASK 0x0000FFFFu
- #define _CHIP_ICR_IC_SHIFT 0x00000000u
- #define CHIP_ICR_IC_DEFAULT 0x00000000u
- #define CHIP_ICR_IC_OF(x) _VALUEOF(x)
-
- #define CHIP_ICR_OF(x) _VALUEOF(x)
-
- #define CHIP_ICR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,ICR,IC)\
- )
-
- #define CHIP_ICR_RMK(ic) (Uint32)( \
- _PER_FMK(CHIP,ICR,IC,ic)\
- )
-
- #define _CHIP_ICR_FGET(FIELD)\
- _PER_CFGET(CHIP,ICR,##FIELD)
-
- #define _CHIP_ICR_FSET(FIELD,field)\
- _PER_CFSET(CHIP,ICR,##FIELD,field)
-
- #define _CHIP_ICR_FSETS(FIELD,SYM)\
- _PER_CFSETS(CHIP,ICR,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | I E R |
-* |___________________|
-*
-* IER - interruppt enable register
-*
-* FIELDS (msb -> lsb)
-* (rw) IE
-*
-\******************************************************************************/
- extern far cregister volatile unsigned int IER;
-
- #define _CHIP_IER_IE_MASK 0x0000FFFFu
- #define _CHIP_IER_IE_SHIFT 0x00000000u
- #define CHIP_IER_IE_DEFAULT 0x00000000u
- #define CHIP_IER_IE_OF(x) _VALUEOF(x)
-
- #define CHIP_IER_OF(x) _VALUEOF(x)
-
- #define CHIP_IER_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,IER,IE)\
- )
-
- #define CHIP_IER_RMK(ie) (Uint32)( \
- _PER_FMK(CHIP,IER,IE,ie)\
- )
-
- #define _CHIP_IER_FGET(FIELD)\
- _PER_CFGET(CHIP,IER,##FIELD)
-
- #define _CHIP_IER_FSET(FIELD,field)\
- _PER_CFSET(CHIP,IER,##FIELD,field)
-
- #define _CHIP_IER_FSETS(FIELD,SYM)\
- _PER_CFSETS(CHIP,IER,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | I S T P |
-* |___________________|
-*
-* ISTP - interrupt service table pointer
-*
-* FIELDS (msb -> lsb)
-* (r) HPEINT
-* (rw) ISTB
-*
-\******************************************************************************/
- extern far cregister volatile unsigned int ISTP;
-
- #define _CHIP_ISTP_ISTB_MASK 0xFFFFFC00u
- #define _CHIP_ISTP_ISTB_SHIFT 0x0000000Au
- #define CHIP_ISTP_ISTB_DEFAULT 0x00000000u
- #define CHIP_ISTP_ISTB_OF(x) _VALUEOF(x)
-
- #define _CHIP_ISTP_HPEINT_MASK 0x000003E0u
- #define _CHIP_ISTP_HPEINT_SHIFT 0x00000005u
- #define CHIP_ISTP_HPEINT_DEFAULT 0x00000000u
- #define CHIP_ISTP_HPEINT_OF(x) _VALUEOF(x)
-
- #define CHIP_ISTP_OF(x) _VALUEOF(x)
-
- #define CHIP_ISTP_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,ISTP,ISTB)\
- |_PER_FDEFAULT(CHIP,ISTP,HPEINT)\
- )
-
- #define CHIP_ISTP_RMK(istb) (Uint32)( \
- _PER_FMK(CHIP,ISTP,ISTB,istb)\
- )
-
- #define _CHIP_ISTP_FGET(FIELD)\
- _PER_CFGET(CHIP,ISTP,##FIELD)
-
- #define _CHIP_ISTP_FSET(FIELD,field)\
- _PER_CFSET(CHIP,ISTP,##FIELD,field)
-
- #define _CHIP_ISTP_FSETS(FIELD,SYM)\
- _PER_CFSETS(CHIP,ISTP,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | I R P |
-* |___________________|
-*
-* IRP - interrupt return pointer
-*
-* FIELDS (msb -> lsb)
-* (rw) IRP
-*
-\******************************************************************************/
- extern far cregister volatile unsigned int IRP;
-
- #define _CHIP_IRP_IRP_MASK 0xFFFFFFFFu
- #define _CHIP_IRP_IRP_SHIFT 0x00000000u
- #define CHIP_IRP_IRP_DEFAULT 0x00000000u
- #define CHIP_IRP_IRP_OF(x) _VALUEOF(x)
-
- #define CHIP_IRP_OF(x) _VALUEOF(x)
-
- #define CHIP_IRP_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,IRP,IRP)\
- )
-
- #define CHIP_IRP_RMK(irp) (Uint32)( \
- _PER_FMK(CHIP,IRP,IRP,irp)\
- )
-
- #define _CHIP_IRP_FGET(FIELD)\
- _PER_CFGET(CHIP,IRP,##FIELD)
-
- #define _CHIP_IRP_FSET(FIELD,field)\
- _PER_CFSET(CHIP,IRP,##FIELD,field)
-
- #define _CHIP_IRP_FSETS(FIELD,SYM)\
- _PER_CFSETS(CHIP,IRP,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | N R P |
-* |___________________|
-*
-* NRP - non-maskable interrupt return pointer
-*
-* FIELDS (msb -> lsb)
-* (rw) NRP
-*
-\******************************************************************************/
- extern far cregister volatile unsigned int NRP;
-
- #define _CHIP_NRP_NRP_MASK 0xFFFFFFFFu
- #define _CHIP_NRP_NRP_SHIFT 0x00000000u
- #define CHIP_NRP_NRP_DEFAULT 0x00000000u
- #define CHIP_NRP_NRP_OF(x) _VALUEOF(x)
-
- #define CHIP_NRP_OF(x) _VALUEOF(x)
-
- #define CHIP_NRP_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,NRP,NRP)\
- )
-
- #define CHIP_NRP_RMK(nrp) (Uint32)( \
- _PER_FMK(CHIP,NRP,NRP,nrp)\
- )
-
- #define _CHIP_NRP_FGET(FIELD)\
- _PER_CFGET(CHIP,NRP,##FIELD)
-
- #define _CHIP_NRP_FSET(FIELD,field)\
- _PER_CFSET(CHIP,NRP,##FIELD,field)
-
- #define _CHIP_NRP_FSETS(FIELD,SYM)\
- _PER_CFSETS(CHIP,NRP,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | A M R |
-* |___________________|
-*
-* AMR - addressing mode register
-*
-* FIELDS (msb -> lsb)
-* (rw) BK1
-* (rw) BK0
-* (rw) B7MODE
-* (rw) B6MODE
-* (rw) B5MODE
-* (rw) B4MODE
-* (rw) A7MODE
-* (rw) A6MODE
-* (rw) A5MODE
-* (rw) A4MODE
-*
-\******************************************************************************/
- extern far cregister volatile unsigned int AMR;
-
- #define _CHIP_AMR_BK1_MASK 0x02E00000u
- #define _CHIP_AMR_BK1_SHIFT 0x00000015u
- #define CHIP_AMR_BK1_DEFAULT 0x00000000u
- #define CHIP_AMR_BK1_OF(x) _VALUEOF(x)
- #define CHIP_AMR_BK1_2 0x00000000u
- #define CHIP_AMR_BK1_4 0x00000001u
- #define CHIP_AMR_BK1_8 0x00000002u
- #define CHIP_AMR_BK1_16 0x00000003u
- #define CHIP_AMR_BK1_32 0x00000004u
- #define CHIP_AMR_BK1_64 0x00000005u
- #define CHIP_AMR_BK1_128 0x00000006u
- #define CHIP_AMR_BK1_256 0x00000007u
- #define CHIP_AMR_BK1_512 0x00000008u
- #define CHIP_AMR_BK1_1K 0x00000009u
- #define CHIP_AMR_BK1_2K 0x0000000Au
- #define CHIP_AMR_BK1_4K 0x0000000Bu
- #define CHIP_AMR_BK1_8K 0x0000000Cu
- #define CHIP_AMR_BK1_16K 0x0000000Du
- #define CHIP_AMR_BK1_32K 0x0000000Eu
- #define CHIP_AMR_BK1_64K 0x0000000Fu
- #define CHIP_AMR_BK1_128K 0x00000010u
- #define CHIP_AMR_BK1_256K 0x00000011u
- #define CHIP_AMR_BK1_512K 0x00000012u
- #define CHIP_AMR_BK1_1M 0x00000013u
- #define CHIP_AMR_BK1_2M 0x00000014u
- #define CHIP_AMR_BK1_4M 0x00000015u
- #define CHIP_AMR_BK1_8M 0x00000016u
- #define CHIP_AMR_BK1_16M 0x00000017u
- #define CHIP_AMR_BK1_32M 0x00000018u
- #define CHIP_AMR_BK1_64M 0x00000019u
- #define CHIP_AMR_BK1_128M 0x0000001Au
- #define CHIP_AMR_BK1_256M 0x0000001Bu
- #define CHIP_AMR_BK1_512M 0x0000001Cu
- #define CHIP_AMR_BK1_1G 0x0000001Du
- #define CHIP_AMR_BK1_2G 0x0000001Eu
- #define CHIP_AMR_BK1_4G 0x0000001Fu
-
- #define _CHIP_AMR_BK0_MASK 0x001F0000u
- #define _CHIP_AMR_BK0_SHIFT 0x00000010u
- #define CHIP_AMR_BK0_DEFAULT 0x00000000u
- #define CHIP_AMR_BK0_OF(x) _VALUEOF(x)
- #define CHIP_AMR_BK0_2 0x00000000u
- #define CHIP_AMR_BK0_4 0x00000001u
- #define CHIP_AMR_BK0_8 0x00000002u
- #define CHIP_AMR_BK0_16 0x00000003u
- #define CHIP_AMR_BK0_32 0x00000004u
- #define CHIP_AMR_BK0_64 0x00000005u
- #define CHIP_AMR_BK0_128 0x00000006u
- #define CHIP_AMR_BK0_256 0x00000007u
- #define CHIP_AMR_BK0_512 0x00000008u
- #define CHIP_AMR_BK0_1K 0x00000009u
- #define CHIP_AMR_BK0_2K 0x0000000Au
- #define CHIP_AMR_BK0_4K 0x0000000Bu
- #define CHIP_AMR_BK0_8K 0x0000000Cu
- #define CHIP_AMR_BK0_16K 0x0000000Du
- #define CHIP_AMR_BK0_32K 0x0000000Eu
- #define CHIP_AMR_BK0_64K 0x0000000Fu
- #define CHIP_AMR_BK0_128K 0x00000010u
- #define CHIP_AMR_BK0_256K 0x00000011u
- #define CHIP_AMR_BK0_512K 0x00000012u
- #define CHIP_AMR_BK0_1M 0x00000013u
- #define CHIP_AMR_BK0_2M 0x00000014u
- #define CHIP_AMR_BK0_4M 0x00000015u
- #define CHIP_AMR_BK0_8M 0x00000016u
- #define CHIP_AMR_BK0_16M 0x00000017u
- #define CHIP_AMR_BK0_32M 0x00000018u
- #define CHIP_AMR_BK0_64M 0x00000019u
- #define CHIP_AMR_BK0_128M 0x0000001Au
- #define CHIP_AMR_BK0_256M 0x0000001Bu
- #define CHIP_AMR_BK0_512M 0x0000001Cu
- #define CHIP_AMR_BK0_1G 0x0000001Du
- #define CHIP_AMR_BK0_2G 0x0000001Eu
- #define CHIP_AMR_BK0_4G 0x0000001Fu
-
-
- #define _CHIP_AMR_B7MODE_MASK 0x0000C000u
- #define _CHIP_AMR_B7MODE_SHIFT 0x0000000Eu
- #define CHIP_AMR_B7MODE_DEFAULT 0x00000000u
- #define CHIP_AMR_B7MODE_OF(x) _VALUEOF(x)
- #define CHIP_AMR_B7MODE_LINEAR 0x00000000u
- #define CHIP_AMR_B7MODE_CIRCULAR0 0x00000001u
- #define CHIP_AMR_B7MODE_CIRCULAR1 0x00000002u
-
- #define _CHIP_AMR_B6MODE_MASK 0x00003000u
- #define _CHIP_AMR_B6MODE_SHIFT 0x0000000Cu
- #define CHIP_AMR_B6MODE_DEFAULT 0x00000000u
- #define CHIP_AMR_B6MODE_OF(x) _VALUEOF(x)
- #define CHIP_AMR_B6MODE_LINEAR 0x00000000u
- #define CHIP_AMR_B6MODE_CIRCULAR0 0x00000001u
- #define CHIP_AMR_B6MODE_CIRCULAR1 0x00000002u
-
- #define _CHIP_AMR_B5MODE_MASK 0x00000C00u
- #define _CHIP_AMR_B5MODE_SHIFT 0x0000000Au
- #define CHIP_AMR_B5MODE_DEFAULT 0x00000000u
- #define CHIP_AMR_B5MODE_OF(x) _VALUEOF(x)
- #define CHIP_AMR_B5MODE_LINEAR 0x00000000u
- #define CHIP_AMR_B5MODE_CIRCULAR0 0x00000001u
- #define CHIP_AMR_B5MODE_CIRCULAR1 0x00000002u
-
- #define _CHIP_AMR_B4MODE_MASK 0x00000300u
- #define _CHIP_AMR_B4MODE_SHIFT 0x00000008u
- #define CHIP_AMR_B4MODE_DEFAULT 0x00000000u
- #define CHIP_AMR_B4MODE_OF(x) _VALUEOF(x)
- #define CHIP_AMR_B4MODE_LINEAR 0x00000000u
- #define CHIP_AMR_B4MODE_CIRCULAR0 0x00000001u
- #define CHIP_AMR_B4MODE_CIRCULAR1 0x00000002u
-
- #define _CHIP_AMR_A7MODE_MASK 0x000000C0u
- #define _CHIP_AMR_A7MODE_SHIFT 0x00000006u
- #define CHIP_AMR_A7MODE_DEFAULT 0x00000000u
- #define CHIP_AMR_A7MODE_OF(x) _VALUEOF(x)
- #define CHIP_AMR_A7MODE_LINEAR 0x00000000u
- #define CHIP_AMR_A7MODE_CIRCULAR0 0x00000001u
- #define CHIP_AMR_A7MODE_CIRCULAR1 0x00000002u
-
- #define _CHIP_AMR_A6MODE_MASK 0x00000030u
- #define _CHIP_AMR_A6MODE_SHIFT 0x00000004u
- #define CHIP_AMR_A6MODE_DEFAULT 0x00000000u
- #define CHIP_AMR_A6MODE_OF(x) _VALUEOF(x)
- #define CHIP_AMR_A6MODE_LINEAR 0x00000000u
- #define CHIP_AMR_A6MODE_CIRCULAR0 0x00000001u
- #define CHIP_AMR_A6MODE_CIRCULAR1 0x00000002u
-
- #define _CHIP_AMR_A5MODE_MASK 0x0000000Cu
- #define _CHIP_AMR_A5MODE_SHIFT 0x00000002u
- #define CHIP_AMR_A5MODE_DEFAULT 0x00000000u
- #define CHIP_AMR_A5MODE_OF(x) _VALUEOF(x)
- #define CHIP_AMR_A5MODE_LINEAR 0x00000000u
- #define CHIP_AMR_A5MODE_CIRCULAR0 0x00000001u
- #define CHIP_AMR_A5MODE_CIRCULAR1 0x00000002u
-
- #define _CHIP_AMR_A4MODE_MASK 0x00000003u
- #define _CHIP_AMR_A4MODE_SHIFT 0x00000000u
- #define CHIP_AMR_A4MODE_DEFAULT 0x00000000u
- #define CHIP_AMR_A4MODE_OF(x) _VALUEOF(x)
- #define CHIP_AMR_A4MODE_LINEAR 0x00000000u
- #define CHIP_AMR_A4MODE_CIRCULAR0 0x00000001u
- #define CHIP_AMR_A4MODE_CIRCULAR1 0x00000002u
-
- #define CHIP_AMR_OF(x) _VALUEOF(x)
-
- #define CHIP_AMR_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,AMR,BK1)\
- |_PER_FDEFAULT(CHIP,AMR,BK0)\
- |_PER_FDEFAULT(CHIP,AMR,B7MODE)\
- |_PER_FDEFAULT(CHIP,AMR,B6MODE)\
- |_PER_FDEFAULT(CHIP,AMR,B5MODE)\
- |_PER_FDEFAULT(CHIP,AMR,B4MODE)\
- |_PER_FDEFAULT(CHIP,AMR,A7MODE)\
- |_PER_FDEFAULT(CHIP,AMR,A6MODE)\
- |_PER_FDEFAULT(CHIP,AMR,A5MODE)\
- |_PER_FDEFAULT(CHIP,AMR,A4MODE)\
- )
-
- #define CHIP_AMR_RMK(bk1,bk0,b7mode,b6mode,b5mode,b4mode,a7,ode,\
- a6mode,a5mode,a4mode) (Uint32)( \
- _PER_FMK(CHIP,AMR,BK1,bk1)\
- |_PER_FMK(CHIP,AMR,BK0,bk0)\
- |_PER_FMK(CHIP,AMR,B7MODE,b7mode)\
- |_PER_FMK(CHIP,AMR,B6MODE,b6mode)\
- |_PER_FMK(CHIP,AMR,B5MODE,b5mode)\
- |_PER_FMK(CHIP,AMR,B4MODE,b4mode)\
- |_PER_FMK(CHIP,AMR,A7MODE,a7mode)\
- |_PER_FMK(CHIP,AMR,A6MODE,a6mode)\
- |_PER_FMK(CHIP,AMR,A5MODE,a5mode)\
- |_PER_FMK(CHIP,AMR,A4MODE,a4mode)\
- )
-
- #define _CHIP_AMR_FGET(FIELD)\
- _PER_CFGET(CHIP,AMR,##FIELD)
-
- #define _CHIP_AMR_FSET(FIELD,field)\
- _PER_CFSET(CHIP,AMR,##FIELD,field)
-
- #define _CHIP_AMR_FSETS(FIELD,SYM)\
- _PER_CFSETS(CHIP,AMR,##FIELD,##SYM)
-
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | D E V C F G |
-* |___________________|
-*
-* PERCFG - Device Configuration register (1)
-*
-* FIELDS (msb -> lsb) CHIP_6713/CHIP_DA610
-* (rw) EKSRC
-* (rw) TOUT1SEL
-* (rw) TOUT0SEL
-* (rw) MCBSP0DIS
-* (rw) MCBSP1DIS
-* (rw) GPIO1EN (only for CHIP_DA610)
-*
-* FIELDS (msb -> lsb) CHIP_DM642
-* (rw) VP2EN
-* (rw) VP1EN
-* (rw) VP0EN
-* (rw) I2C0EN
-* (rw) MCBSP1EN
-* (rw) MCBSP0EN
-* (rw) MCASP0EN
-*
-* FIELDS (msb -> lsb) CHIP_6412
-* (rw) I2C0EN
-* (rw) MCBSP1EN
-* (rw) MCBSP0EN
-*
-* FIELDS (msb -> lsb) CHIP_6711C/CHIP_6712C
-* (rw) EKSRC
-*
-* FIELDS (msb -> lsb) CHIP_6410/CHIP_6413/CHIP_6418
-* (rw) AFCMUX
-* (rw) MCASP1EN
-* (rw) I2C1EN
-* (rw) I2C0EN
-* (r) MCBSP1EN
-* (r) MCBSP0EN
-* (rw) MCASP0EN
-*
-\******************************************************************************/
-
-#if (CHIP_DA610)
-
- #define _CHIP_DEVCFG_ADDR 0x019C0200u
- #define _CHIP_DEVCFG_OFFSET 0
-
- #define _CHIP_DEVCFG_GPIO1EN_MASK 0x00010000u
- #define _CHIP_DEVCFG_GPIO1EN_SHIFT 0x0000000Fu
- #define CHIP_DEVCFG_GPIO1EN_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_GPIO1EN_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_GPIO1EN_0 0x00000000u
- #define CHIP_DEVCFG_GPIO1EN_1 0x00000001u
-
- #define _CHIP_DEVCFG_EKSRC_MASK 0x00000010u
- #define _CHIP_DEVCFG_EKSRC_SHIFT 0x00000004u
- #define CHIP_DEVCFG_EKSRC_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_EKSRC_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_EKSRC_SYSCLK3 0x00000000u
- #define CHIP_DEVCFG_EKSRC_ECLKIN 0x00000001u
-
- #define _CHIP_DEVCFG_TOUT1SEL_MASK 0x00000008u
- #define _CHIP_DEVCFG_TOUT1SEL_SHIFT 0x00000003u
- #define CHIP_DEVCFG_TOUT1SEL_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_TOUT1SEL_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_TOUT1SEL_TOUT1PIN 0x00000000u
- #define CHIP_DEVCFG_TOUT1SEL_MCASPPIN 0x00000001u
-
- #define _CHIP_DEVCFG_TOUT0SEL_MASK 0x00000004u
- #define _CHIP_DEVCFG_TOUT0SEL_SHIFT 0x00000002u
- #define CHIP_DEVCFG_TOUT0SEL_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_TOUT0SEL_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_TOUT0SEL_TOUT0PIN 0x00000000u
- #define CHIP_DEVCFG_TOUT0SEL_MCASPPIN 0x00000001u
-
- #define _CHIP_DEVCFG_MCBSP0DIS_MASK 0x00000002u
- #define _CHIP_DEVCFG_MCBSP0DIS_SHIFT 0x00000001u
- #define CHIP_DEVCFG_MCBSP0DIS_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_MCBSP0DIS_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_MCBSP0DIS_0 0x00000000u
- #define CHIP_DEVCFG_MCBSP0DIS_1 0x00000001u
-
- #define _CHIP_DEVCFG_MCBSP1DIS_MASK 0x00000001u
- #define _CHIP_DEVCFG_MCBSP1DIS_SHIFT 0x00000000u
- #define CHIP_DEVCFG_MCBSP1DIS_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_MCBSP1DIS_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_MCBSP1DIS_0 0x00000000u
- #define CHIP_DEVCFG_MCBSP1DIS_1 0x00000001u
-
-
- #define CHIP_DEVCFG_OF(x) _VALUEOF(x)
-
- #define CHIP_DEVCFG_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,DEVCFG,EKSRC) \
- |_PER_FDEFAULT(CHIP,DEVCFG,TOUT1SEL) \
- |_PER_FDEFAULT(CHIP,DEVCFG,TOUT0SEL) \
- |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP0DIS) \
- |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP1DIS) \
- |_PER_FDEFAULT(CHIP,DEVCFG,GPIO1EN) \
- )
-
- #define CHIP_DEVCFG_RMK(eksrc,tout1sel,tout0sel,mcbsp0dis,mcbsp1dis,\
- gpio1en ) (Uint32)( \
- _PER_FMK(CHIP,DEVCFG,EKSRC,eksrc) \
- |_PER_FMK(CHIP,DEVCFG,TOUT1SEL,tout1sel) \
- |_PER_FMK(CHIP,DEVCFG,TOUT0SEL,tout0sel) \
- |_PER_FMK(CHIP,DEVCFG,MCBSP0DIS,mcbsp0dis) \
- |_PER_FMK(CHIP,DEVCFG,MCBSP1DIS,mcbsp1dis) \
- |_PER_FMK(CHIP,DEVCFG,GPIO1EN,gpio1en) \
-)
-#elif (CHIP_6713)
- #define _CHIP_DEVCFG_ADDR 0x019C0200u
- #define _CHIP_DEVCFG_OFFSET 0
-
- #define _CHIP_DEVCFG_EKSRC_MASK 0x00000010u
- #define _CHIP_DEVCFG_EKSRC_SHIFT 0x00000004u
- #define CHIP_DEVCFG_EKSRC_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_EKSRC_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_EKSRC_SYSCLK3 0x00000000u
- #define CHIP_DEVCFG_EKSRC_ECLKIN 0x00000001u
-
- #define _CHIP_DEVCFG_TOUT1SEL_MASK 0x00000008u
- #define _CHIP_DEVCFG_TOUT1SEL_SHIFT 0x00000003u
- #define CHIP_DEVCFG_TOUT1SEL_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_TOUT1SEL_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_TOUT1SEL_TOUT1PIN 0x00000000u
- #define CHIP_DEVCFG_TOUT1SEL_MCASPPIN 0x00000001u
-
- #define _CHIP_DEVCFG_TOUT0SEL_MASK 0x00000004u
- #define _CHIP_DEVCFG_TOUT0SEL_SHIFT 0x00000002u
- #define CHIP_DEVCFG_TOUT0SEL_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_TOUT0SEL_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_TOUT0SEL_TOUT0PIN 0x00000000u
- #define CHIP_DEVCFG_TOUT0SEL_MCASPPIN 0x00000001u
-
- #define _CHIP_DEVCFG_MCBSP0DIS_MASK 0x00000002u
- #define _CHIP_DEVCFG_MCBSP0DIS_SHIFT 0x00000001u
- #define CHIP_DEVCFG_MCBSP0DIS_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_MCBSP0DIS_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_MCBSP0DIS_0 0x00000000u
- #define CHIP_DEVCFG_MCBSP0DIS_1 0x00000001u
-
- #define _CHIP_DEVCFG_MCBSP1DIS_MASK 0x00000001u
- #define _CHIP_DEVCFG_MCBSP1DIS_SHIFT 0x00000000u
- #define CHIP_DEVCFG_MCBSP1DIS_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_MCBSP1DIS_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_MCBSP1DIS_0 0x00000000u
- #define CHIP_DEVCFG_MCBSP1DIS_1 0x00000001u
-
-
- #define CHIP_DEVCFG_OF(x) _VALUEOF(x)
-
- #define CHIP_DEVCFG_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,DEVCFG,EKSRC) \
- |_PER_FDEFAULT(CHIP,DEVCFG,TOUT1SEL) \
- |_PER_FDEFAULT(CHIP,DEVCFG,TOUT0SEL) \
- |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP0DIS) \
- |_PER_FDEFAULT(CHIP,DEVCFG,MCBSP1DIS) \
- )
-
- #define CHIP_DEVCFG_RMK(eksrc,tout1sel,tout0sel,mcbsp0dis,mcbsp1dis\
- ) (Uint32)( \
- _PER_FMK(CHIP,DEVCFG,EKSRC,eksrc) \
- |_PER_FMK(CHIP,DEVCFG,TOUT1SEL,tout1sel) \
- |_PER_FMK(CHIP,DEVCFG,TOUT0SEL,tout0sel) \
- |_PER_FMK(CHIP,DEVCFG,MCBSP0DIS,mcbsp0dis) \
- |_PER_FMK(CHIP,DEVCFG,MCBSP1DIS,mcbsp1dis) \
-)
-
-#endif
-
-#if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412)
-
- #define _CHIP_PERCFG_ADDR 0x01B3F000u
- #define _CHIP_PERCFG_OFFSET 0
-
-#if (CHIP_DM642)
- #define _CHIP_PERCFG_VP2EN_MASK 0x00000040u
- #define _CHIP_PERCFG_VP2EN_SHIFT 0x00000006u
- #define CHIP_PERCFG_VP2EN_DEFAULT 0x00000000u
- #define CHIP_PERCFG_VP2EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_VP2EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_VP2EN_ENABLE 0x00000001u
-#endif
-
-#if (CHIP_DM642 | CHIP_DM641)
- #define _CHIP_PERCFG_VP1EN_MASK 0x00000020u
- #define _CHIP_PERCFG_VP1EN_SHIFT 0x00000005u
- #define CHIP_PERCFG_VP1EN_DEFAULT 0x00000000u
- #define CHIP_PERCFG_VP1EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_VP1EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_VP1EN_ENABLE 0x00000001u
-#endif
-
-#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640)
- #define _CHIP_PERCFG_VP0EN_MASK 0x00000010u
- #define _CHIP_PERCFG_VP0EN_SHIFT 0x00000004u
- #define CHIP_PERCFG_VP0EN_DEFAULT 0x00000000u
- #define CHIP_PERCFG_VP0EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_VP0EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_VP0EN_ENABLE 0x00000001u
-#endif
-
- #define _CHIP_PERCFG_I2C0EN_MASK 0x00000008u
- #define _CHIP_PERCFG_I2C0EN_SHIFT 0x00000003u
- #define CHIP_PERCFG_I2C0EN_DEFAULT 0x00000000u
- #define CHIP_PERCFG_I2C0EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_I2C0EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_I2C0EN_ENABLE 0x00000001u
-
- #define _CHIP_PERCFG_MCBSP1EN_MASK 0x00000004u
- #define _CHIP_PERCFG_MCBSP1EN_SHIFT 0x00000002u
- #define CHIP_PERCFG_MCBSP1EN_DEFAULT 0x00000001u
- #define CHIP_PERCFG_MCBSP1EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_MCBSP1EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_MCBSP1EN_ENABLE 0x00000001u
-
- #define _CHIP_PERCFG_MCBSP0EN_MASK 0x00000002u
- #define _CHIP_PERCFG_MCBSP0EN_SHIFT 0x00000001u
- #define CHIP_PERCFG_MCBSP0EN_DEFAULT 0x00000001u
- #define CHIP_PERCFG_MCBSP0EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_MCBSP0EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_MCBSP0EN_ENABLE 0x00000001u
-
-#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640)
- #define _CHIP_PERCFG_MCASP0EN_MASK 0x00000001u
- #define _CHIP_PERCFG_MCASP0EN_SHIFT 0x00000000u
- #define CHIP_PERCFG_MCASP0EN_DEFAULT 0x00000000u
- #define CHIP_PERCFG_MCASP0EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_MCASP0EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_MCASP0EN_ENABLE 0x00000001u
-#endif
-
-
- #define CHIP_PERCFG_OF(x) _VALUEOF(x)
-
-#if (CHIP_DM642)
- #define CHIP_PERCFG_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,PERCFG,VP2EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,VP1EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,VP0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \
- )
-
-
- #define CHIP_PERCFG_RMK(vp2en,vp1en,vp0en,i2c0en,mcbsp1en,mcbsp0en,mcasp0en) (Uint32)( \
- _PER_FMK(CHIP,PERCFG,VP2EN,vp2en) \
- |_PER_FMK(CHIP,PERCFG,VP1EN,vp1en) \
- |_PER_FMK(CHIP,PERCFG,VP0EN,vp0en) \
- |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \
- |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \
- |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \
- |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \
- )
-#endif
-
-#if (CHIP_DM641)
- #define CHIP_PERCFG_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,PERCFG,VP1EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,VP0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \
- )
-
-
- #define CHIP_PERCFG_RMK(vp1en,vp0en,i2c0en,mcbsp1en,mcbsp0en,mcasp0en) (Uint32)( \
- _PER_FMK(CHIP,PERCFG,VP1EN,vp1en) \
- |_PER_FMK(CHIP,PERCFG,VP0EN,vp0en) \
- |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \
- |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \
- |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \
- |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \
- )
-#endif
-
-#if (CHIP_DM640)
- #define CHIP_PERCFG_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,PERCFG,VP0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \
- )
-
-
- #define CHIP_PERCFG_RMK(vp0en,i2c0en,mcbsp1en,mcbsp0en,mcasp0en) (Uint32)( \
- _PER_FMK(CHIP,PERCFG,VP0EN,vp0en) \
- |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \
- |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \
- |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \
- |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \
- )
-#endif
-
-#if (CHIP_6412)
- #define CHIP_PERCFG_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \
- )
-
-
- #define CHIP_PERCFG_RMK(i2c0en,mcbsp1en,mcbsp0en) (Uint32)( \
- |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \
- |_PER_FMK(CHIP,PERCFG,MCBSP1EN,mcbsp1en) \
- |_PER_FMK(CHIP,PERCFG,MCBSP0EN,mcbsp0en) \
- )
-#endif
-
-#endif /* CHIP_DM642 || CHIP_6412 */
-
-#if (CHIP_6410 || CHIP_6413 || CHIP_6418)
-
- #define _CHIP_PERCFG_ADDR 0x01B3F000u
- #define _CHIP_PERCFG_OFFSET 0
-
- #define _CHIP_PERCFG_AFCMUX_MASK 0x00000600u
- #define _CHIP_PERCFG_AFCMUX_SHIFT 0x00000009u
- #define CHIP_PERCFG_AFCMUX_DEFAULT 0x00000000u
- #define CHIP_PERCFG_AFCMUX_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_AFCMUX_PIN0 0x00000000u
- #define CHIP_PERCFG_AFCMUX_PIN1 0x00000001u
- #define CHIP_PERCFG_AFCMUX_PIN2 0x00000002u
- #define CHIP_PERCFG_AFCMUX_PIN3 0x00000003u
-
- #define _CHIP_PERCFG_MCASP1EN_MASK 0x00000100u
- #define _CHIP_PERCFG_MCASP1EN_SHIFT 0x00000008u
- #define CHIP_PERCFG_MCASP1EN_DEFAULT 0x00000000u
- #define CHIP_PERCFG_MCASP1EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_MCASP1EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_MCASP1EN_ENABLE 0x00000001u
-
- #define _CHIP_PERCFG_I2C1EN_MASK 0x00000080u
- #define _CHIP_PERCFG_I2C1EN_SHIFT 0x00000007u
- #define CHIP_PERCFG_I2C1EN_DEFAULT 0x00000000u
- #define CHIP_PERCFG_I2C1EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_I2C1EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_I2C1EN_ENABLE 0x00000001u
-
- #define _CHIP_PERCFG_I2C0EN_MASK 0x00000008u
- #define _CHIP_PERCFG_I2C0EN_SHIFT 0x00000003u
- #define CHIP_PERCFG_I2C0EN_DEFAULT 0x00000000u
- #define CHIP_PERCFG_I2C0EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_I2C0EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_I2C0EN_ENABLE 0x00000001u
-
- #define _CHIP_PERCFG_MCBSP1EN_MASK 0x00000004u
- #define _CHIP_PERCFG_MCBSP1EN_SHIFT 0x00000002u
- #define CHIP_PERCFG_MCBSP1EN_DEFAULT 0x00000001u
- #define CHIP_PERCFG_MCBSP1EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_MCBSP1EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_MCBSP1EN_ENABLE 0x00000001u
-
- #define _CHIP_PERCFG_MCBSP0EN_MASK 0x00000002u
- #define _CHIP_PERCFG_MCBSP0EN_SHIFT 0x00000001u
- #define CHIP_PERCFG_MCBSP0EN_DEFAULT 0x00000001u
- #define CHIP_PERCFG_MCBSP0EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_MCBSP0EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_MCBSP0EN_ENABLE 0x00000001u
-
- #define _CHIP_PERCFG_MCASP0EN_MASK 0x00000001u
- #define _CHIP_PERCFG_MCASP0EN_SHIFT 0x00000000u
- #define CHIP_PERCFG_MCASP0EN_DEFAULT 0x00000000u
- #define CHIP_PERCFG_MCASP0EN_OF(x) _VALUEOF(x)
- #define CHIP_PERCFG_MCASP0EN_DISABLE 0x00000000u
- #define CHIP_PERCFG_MCASP0EN_ENABLE 0x00000001u
-
- #define CHIP_PERCFG_OF(x) _VALUEOF(x)
-
- #define CHIP_PERCFG_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,PERCFG,AFCMUX) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCASP1EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,I2C1EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,I2C0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCBSP1EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCBSP0EN) \
- |_PER_FDEFAULT(CHIP,PERCFG,MCASP0EN) \
- )
-
-
- #define CHIP_PERCFG_RMK(afcmux,mcasp1en,i2c1en,i2c0en,mcasp0en) (Uint32)( \
- _PER_FMK(CHIP,PERCFG,AFCMUX,afcmux) \
- |_PER_FMK(CHIP,PERCFG,MCASP1EN,mcasp1en) \
- |_PER_FMK(CHIP,PERCFG,I2C1EN,i2c1en) \
- |_PER_FMK(CHIP,PERCFG,I2C0EN,i2c0en) \
- |_PER_FMK(CHIP,PERCFG,MCASP0EN,mcasp0en) \
- )
-
-#endif /* CHIP_6410 || CHIP_6413 || CHIP_6418 */
-
-#if (CHIP_6711C || CHIP_6712C)
- #define _CHIP_DEVCFG_ADDR 0x019C0200u
- #define _CHIP_DEVCFG_OFFSET 0
-
- #define _CHIP_DEVCFG_EKSRC_MASK 0x00000010u
- #define _CHIP_DEVCFG_EKSRC_SHIFT 0x00000004u
- #define CHIP_DEVCFG_EKSRC_DEFAULT 0x00000000u
- #define CHIP_DEVCFG_EKSRC_OF(x) _VALUEOF(x)
- #define CHIP_DEVCFG_EKSRC_SYSCLK3 0x00000000u
- #define CHIP_DEVCFG_EKSRC_ECLKIN 0x00000001u
-
- #define CHIP_DEVCFG_OF(x) _VALUEOF(x)
-
- #define CHIP_DEVCFG_DEFAULT (Uint32)( \
- _PER_FDEFAULT(CHIP,DEVCFG,EKSRC) \
- )
-
- #define CHIP_PERCFG_RMK(eksrc) (Uint32)( \
- _PER_FMK(CHIP,PERCFG,EKSRC,eksrc) \
-)
-
-#endif /* CHIP_6711C || CHIP_6712C */
-
-#if (CHIP_6711C || CHIP_6712C || CHIP_DA610 || CHIP_6713)
- #define _CHIP_DEVCFG_FGET(FIELD)\
- _PER_FGET(_CHIP_DEVCFG_ADDR,CHIP,DEVCFG,##FIELD)
-
- #define _CHIP_DEVCFG_FSET(FIELD,field)\
- _PER_FSET(_CHIP_DEVCFG_ADDR,CHIP,DEVCFG,##FIELD,field)
-
- #define _CHIP_DEVCFG_FSETS(FIELD,SYM)\
- _PER_FSETS(_CHIP_DEVCFG_ADDR,CHIP,DEVCFG,##FIELD,##SYM)
-
-#else
-
- #define _CHIP_PERCFG_FGET(FIELD)\
- _PER_FGET(_CHIP_PERCFG_ADDR,CHIP,PERCFG,##FIELD)
-
- #define _CHIP_PERCFG_FSET(FIELD,field)\
- _PER_FSET(_CHIP_PERCFG_ADDR,CHIP,PERCFG,##FIELD,field)
-
- #define _CHIP_PERCFG_FSETS(FIELD,SYM)\
- _PER_FSETS(_CHIP_PERCFG_ADDR,CHIP,PERCFG,##FIELD,##SYM)
-#endif
-
-/*----------------------------------------------------------------------------*/
-/******************************************************************************\
-* _____________________
-* | |
-* | D E V S T A T |
-* |___________________|
-*
-* DEVSTAT - Device Status Register (1)
-*
-* FIELDS (msb -> lsb)
-* DM642
-* (r) MACEN
-* (r) HPIWIDTH
-* (r) PCIEEAI
-* (r) PCIEN
-* (r) CLKMODE
-* (r) LENDIAN
-* (r) BOOTMODE
-* (r) AECLKINSEL
-*
-* DRI300
-* (r) PLLM
-* (r) OSCEXTRES
-* (r) CLKINSEL
-* (r) CLKMODE3
-* (r) HPIWIDTH
-* (r) HPIENZ
-* (r) CLKMODE2
-* (r) CLKMODE1
-* (r) CLKMODE0
-* (r) LENDIAN
-* (r) BOOTMODE
-* (r) AECLKINSEL
-*
-*
-\******************************************************************************/
-#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412)
-
- #define _CHIP_DEVSTAT_ADDR 0x01B3F004u
- #define _CHIP_DEVSTAT_OFFSET 0
-
- #define _CHIP_DEVSTAT_MACEN_MASK 0x00000800u
- #define _CHIP_DEVSTAT_MACEN_SHIFT 0x0000000Bu
- #define CHIP_DEVSTAT_MACEN_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_MACEN_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_MACEN_DISABLE 0x00000000u
- #define CHIP_DEVSTAT_MACEN_ENABLE 0x00000001u
-
- #if !(CHIP_DM640)
- #define _CHIP_DEVSTAT_HPIWIDTH_MASK 0x00000400u
- #define _CHIP_DEVSTAT_HPIWIDTH_SHIFT 0x0000000Au
- #define CHIP_DEVSTAT_HPIWIDTH_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_HPIWIDTH_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_HPIWIDTH_16 0x00000000u
- #define CHIP_DEVSTAT_HPIWIDTH_32 0x00000001u
- #endif
-
- #if !(CHIP_DM641 | CHIP_DM640)
- #define _CHIP_DEVSTAT_PCIEEAI_MASK 0x00000200u
- #define _CHIP_DEVSTAT_PCIEEAI_SHIFT 0x00000009u
- #define CHIP_DEVSTAT_PCIEEAI_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_PCIEEAI_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_PCIEEAI_NONE 0x00000000u
- #define CHIP_DEVSTAT_PCIEEAI_INIT 0x00000001u
-
- #define _CHIP_DEVSTAT_PCIEN_MASK 0x00000100u
- #define _CHIP_DEVSTAT_PCIEN_SHIFT 0x00000008u
- #define CHIP_DEVSTAT_PCIEN_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_PCIEN_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_PCIEN_DISABLE 0x00000000u
- #define CHIP_DEVSTAT_PCIEN_ENABLE 0x00000001u
- #endif
-
- #define _CHIP_DEVSTAT_CLKMODE_MASK 0x00000060u
- #define _CHIP_DEVSTAT_CLKMODE_SHIFT 0x00000005u
- #define CHIP_DEVSTAT_CLKMODE_DEFAULT 0x00000001u
- #define CHIP_DEVSTAT_CLKMODE_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_CLKMODE_X1 0x00000000u
- #define CHIP_DEVSTAT_CLKMODE_X6 0x00000001u
- #define CHIP_DEVSTAT_CLKMODE_X12 0x00000002u
- #define CHIP_DEVSTAT_CLKMODE_X20 0x00000003u
-
- #define _CHIP_DEVSTAT_LENDIAN_MASK 0x00000010u
- #define _CHIP_DEVSTAT_LENDIAN_SHIFT 0x00000004u
- #define CHIP_DEVSTAT_LENDIAN_DEFAULT 0x00000001u
- #define CHIP_DEVSTAT_LENDIAN_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_LENDIAN_BIG 0x00000000u
- #define CHIP_DEVSTAT_LENDIAN_LITTLE 0x00000001u
-
- #define _CHIP_DEVSTAT_BOOTMODE_MASK 0x0000000Cu
- #define _CHIP_DEVSTAT_BOOTMODE_SHIFT 0x00000002u
- #define CHIP_DEVSTAT_BOOTMODE_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_BOOTMODE_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_BOOTMODE_NONE 0x00000000u
- #define CHIP_DEVSTAT_BOOTMODE_HPIPCI 0x00000001u
- #define CHIP_DEVSTAT_BOOTMODE_EMIFA 0x00000003u
-
- #define _CHIP_DEVSTAT_AECLKINSEL_MASK 0x00000003u
- #define _CHIP_DEVSTAT_AECLKINSEL_SHIFT 0x00000000u
- #define CHIP_DEVSTAT_AECLKINSEL_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_AECLKINSEL_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_AECLKINSEL_ECLKIN 0x00000000u
- #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT4 0x00000001u
- #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT6 0x00000002u
- #define CHIP_DEVSTAT_OF(x) _VALUEOF(x)
-
- #define CHIP_DEVSTAT_OF(x) _VALUEOF(x)
-
- /* Read only Register */
-
- #define _CHIP_DEVSTAT_FGET(FIELD)\
- _PER_FGET(_CHIP_DEVSTAT_ADDR,CHIP,DEVSTAT,##FIELD)
-
-
-#endif /* CHIP_DM642 | CHIP_6412 */
-
-#if (CHIP_6410 || CHIP_6413 || CHIP_6418)
-
- #define _CHIP_DEVSTAT_ADDR 0x01B3F004u
- #define _CHIP_DEVSTAT_OFFSET 0
-
- #define _CHIP_DEVSTAT_PLLM_MASK 0x00F10000u
- #define _CHIP_DEVSTAT_PLLM_SHIFT 0x00000013u
- #define CHIP_DEVSTAT_PLLM_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_PLLM_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_PLLM_BYPASS 0x00000000u
- #define CHIP_DEVSTAT_PLLM_5 0x00000001u
- #define CHIP_DEVSTAT_PLLM_6 0x00000002u
- #define CHIP_DEVSTAT_PLLM_7 0x00000003u
- #define CHIP_DEVSTAT_PLLM_8 0x00000004u
- #define CHIP_DEVSTAT_PLLM_9 0x00000005u
- #define CHIP_DEVSTAT_PLLM_10 0x00000006u
- #define CHIP_DEVSTAT_PLLM_11 0x00000007u
- #define CHIP_DEVSTAT_PLLM_12 0x00000008u
- #define CHIP_DEVSTAT_PLLM_16 0x00000009u
- #define CHIP_DEVSTAT_PLLM_18 0x0000000Au
- #define CHIP_DEVSTAT_PLLM_19 0x0000000Bu
- #define CHIP_DEVSTAT_PLLM_20 0x0000000Cu
- #define CHIP_DEVSTAT_PLLM_21 0x0000000Du
- #define CHIP_DEVSTAT_PLLM_22 0x0000000Eu
- #define CHIP_DEVSTAT_PLLM_24 0x0000000Fu
-
- #define _CHIP_DEVSTAT_OSCEXTRES_MASK 0x00020000u
- #define _CHIP_DEVSTAT_OSCEXTRES_SHIFT 0x00000011u
- #define CHIP_DEVSTAT_OSCEXTRES_DEFAUL 0x00000001u
- #define CHIP_DEVSTAT_OSCEXTRES_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_OSCEXTRES_DISABL 0x00000000u
- #define CHIP_DEVSTAT_OSCEXTRES_ENABLE 0x00000001u
-
- #define _CHIP_DEVSTAT_CLKINSEL_MASK 0x00010000u
- #define _CHIP_DEVSTAT_CLKINSEL_SHIFT 0x00000010u
- #define CHIP_DEVSTAT_CLKINSEL_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_CLKINSEL_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_CLKINSEL_DISABLE 0x00000000u
- #define CHIP_DEVSTAT_CLKINSEL_ENABLE 0x00000001u
-
- #define _CHIP_DEVSTAT_HPIWIDTH_MASK 0x00000400u
- #define _CHIP_DEVSTAT_HPIWIDTH_SHIFT 0x0000000Au
- #define CHIP_DEVSTAT_HPIWIDTH_DEFAUL 0x00000000u
- #define CHIP_DEVSTAT_HPIWIDTH_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_HPIWIDTH_16 0x00000000u
- #define CHIP_DEVSTAT_HPIWIDTH_32 0x00000001u
-
- #define _CHIP_DEVSTAT_HPIENZ_MASK 0x00000100u
- #define _CHIP_DEVSTAT_HPIENZ_SHIFT 0x00000008u
- #define CHIP_DEVSTAT_HPIENZ_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_HPIENZ_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_HPIENZ_ENABLE 0x00000000u
- #define CHIP_DEVSTAT_HPIENZ_DISABLE 0x00000001u
-
- #define _CHIP_DEVSTAT_CLKMODE_MASK 0x000010E0u
- #define _CHIP_DEVSTAT_CLKMODE_SHIFT 0x00000005u
- #define CHIP_DEVSTAT_CLKMODE_DEFAULT 0x00000001u
- #define CHIP_DEVSTAT_CLKMODE_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_CLKMODE_0 0x00000000u
- #define CHIP_DEVSTAT_CLKMODE_1 0x00000001u
- #define CHIP_DEVSTAT_CLKMODE_2 0x00000002u
- #define CHIP_DEVSTAT_CLKMODE_3 0x00000003u
- #define CHIP_DEVSTAT_CLKMODE_4 0x00000004u
- #define CHIP_DEVSTAT_CLKMODE_5 0x00000005u
- #define CHIP_DEVSTAT_CLKMODE_6 0x00000006u
- #define CHIP_DEVSTAT_CLKMODE_7 0x00000007u
- #define CHIP_DEVSTAT_CLKMODE_8 0x00000080u
- #define CHIP_DEVSTAT_CLKMODE_9 0x00000081u
- #define CHIP_DEVSTAT_CLKMODE_10 0x00000082u
- #define CHIP_DEVSTAT_CLKMODE_11 0x00000083u
- #define CHIP_DEVSTAT_CLKMODE_12 0x00000084u
- #define CHIP_DEVSTAT_CLKMODE_13 0x00000085u
- #define CHIP_DEVSTAT_CLKMODE_14 0x00000086u
- #define CHIP_DEVSTAT_CLKMODE_15 0x00000087u
-
- #define _CHIP_DEVSTAT_LENDIAN_MASK 0x00000010u
- #define _CHIP_DEVSTAT_LENDIAN_SHIFT 0x00000004u
- #define CHIP_DEVSTAT_LENDIAN_DEFAULT 0x00000001u
- #define CHIP_DEVSTAT_LENDIAN_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_LENDIAN_BIG 0x00000000u
- #define CHIP_DEVSTAT_LENDIAN_LITTLE 0x00000001u
-
- #define _CHIP_DEVSTAT_BOOTMODE_MASK 0x0000000Cu
- #define _CHIP_DEVSTAT_BOOTMODE_SHIFT 0x00000002u
- #define CHIP_DEVSTAT_BOOTMODE_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_BOOTMODE_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_BOOTMODE_NONE 0x00000000u
- #define CHIP_DEVSTAT_BOOTMODE_HPI 0x00000001u
- #define CHIP_DEVSTAT_BOOTMODE_EMIFA 0x00000003u
-
- #define _CHIP_DEVSTAT_AECLKINSEL_MASK 0x00000003u
- #define _CHIP_DEVSTAT_AECLKINSEL_SHIFT 0x00000000u
- #define CHIP_DEVSTAT_AECLKINSEL_DEFAULT 0x00000000u
- #define CHIP_DEVSTAT_AECLKINSEL_OF(x) _VALUEOF(x)
- #define CHIP_DEVSTAT_AECLKINSEL_ECLKIN 0x00000000u
- #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT4 0x00000001u
- #define CHIP_DEVSTAT_AECLKINSEL_CLKOUT6 0x00000002u
-
- #define CHIP_DEVSTAT_OF(x) _VALUEOF(x)
-
- /* Read only Register */
-
- #define _CHIP_DEVSTAT_FGET(FIELD)\
- _PER_FGET(_CHIP_DEVSTAT_ADDR,CHIP,DEVSTAT,##FIELD)
-
-
-#endif /* CHIP_6410 || CHIP_6413 || CHIP_6418 */
-
-/******************************************************************************\
-* _____________________
-* | |
-* | J T A G I D |
-* |___________________|
-*
-* JTAGID - JTAG ID register (1)
-*
-* FIELDS (msb -> lsb)
-* (r) VARIANT
-* (r) PART
-* (r) MANNUFACTURE
-* (r) LSB
-*
-* (1) Only for DM642
-*
-\******************************************************************************/
-
-
-#if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 )
-
- #define _CHIP_JTAGID_ADDR 0x01B3F008u
- #define _CHIP_JTAGID_OFFSET 0
-
- #define _CHIP_JTAGID_VARIANT_MASK 0xF0000000u
- #define _CHIP_JTAGID_VARIANT_SHIFT 0x0000001Cu
- #define CHIP_JTAGID_VARIANT_DEFAULT 0x00000000u
- #define CHIP_JTAGID_VARIANT_OF(x) _VALUEOF(x)
-
- #define _CHIP_JTAGID_PART_MASK 0x0FFFF000u
- #define _CHIP_JTAGID_PART_SHIFT 0x0000000Cu
- #define CHIP_JTAGID_PART_DEFAULT 0x00000079u
- #define CHIP_JTAGID_PART_OF(x) _VALUEOF(x)
-
- #define _CHIP_JTAGID_MANUFACTURE_MASK 0x00000FFEu
- #define _CHIP_JTAGID_MANUFACTURE_SHIFT 0x00000001u
- #define CHIP_JTAGID_MANUFACTURE_DEFAULT 0x00000017u
- #define CHIP_JTAGID_MANUFACTURE_OF(x) _VALUEOF(x)
-
- #define _CHIP_JTAGID_LSB_MASK 0x00000001u
- #define _CHIP_JTAGID_LSB_SHIFT 0x00000000u
- #define CHIP_JTAGID_LSB_DEFAULT 0x00000001u
- #define CHIP_JTAGID_LSB_OF(x) _VALUEOF(x)
-
- #define CHIP_JTAGID_OF(x) _VALUEOF(x)
-
- #define _CHIP_JTAGID_FGET(FIELD)\
- _PER_FGET(_CHIP_JTAGID_ADDR,CHIP,JTAGID,##FIELD)
-
-#endif /* CHIP_DM642 || CHIP_6412 */
-
-/******************************************************************************\
-* _____________________
-* | |
-* | P C F G L O C K |
-* |___________________|
-*
-* PCFGLOCK - Peripheral Configuration Lock register (1)
-*
-* FIELDS (msb -> lsb)
-* (r) LOCKSTAT
-* (w) LOCK
-*
-* (1) Only for DM642
-*
-\******************************************************************************/
-
-#if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418)
-
- #define _CHIP_PCFGLOCK_ADDR 0x01B3F018u
- #define _CHIP_PCFGLOCK_OFFSET 0
-
- #define _CHIP_PCFGLOCK_LOCKSTAT_MASK 0x00000001u
- #define _CHIP_PCFGLOCK_LOCKSTAT_SHIFT 0x00000000u
- #define CHIP_PCFGLOCK_LOCKSTAT_DEFAULT 0x00000001u
- #define CHIP_PCFGLOCK_LOCKSTAT_OF(x) _VALUEOF(x)
- #define CHIP_PCFGLOCK_LOCKSTAT_UNLOCK 0x00000000u
- #define CHIP_PCFGLOCK_LOCKSTAT_LOCK 0x00000001u
-
- #define _CHIP_PCFGLOCK_LOCK_MASK 0xFFFFFFFFu
- #define _CHIP_PCFGLOCK_LOCK_SHIFT 0x00000000u
- #define CHIP_PCFGLOCK_LOCK_DEFAULT 0x00000000u
- #define CHIP_PCFGLOCK_LOCK_OF(x) _VALUEOF(x)
- #define CHIP_PCFGLOCK_LOCK_UNLOCK 0x10C0010Cu
- #define CHIP_PCFGLOCK_LOCK_DISABLE 0x10C0010Cu
-
- #define CHIP_PCFGLOCK_OF(x) _VALUEOF(x)
-
- #define _CHIP_PCFGLOCK_FGET(FIELD)\
- _PER_FGET(_CHIP_PCFGLOCK_ADDR,CHIP,PCFGLOCK,##FIELD)
-
- #define _CHIP_PCFGLOCK_FSET(FIELD,field)\
- _PER_FSET(_CHIP_PCFGLOCK_ADDR,CHIP,PCFGLOCK,##FIELD,field)
-
- #define _CHIP_PCFGLOCK_FSETS(FIELD,SYM)\
- _PER_FSETS(_CHIP_PCFGLOCK_ADDR,CHIP,PCFGLOCK,##FIELD,##SYM)
-
-
-#endif /* CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412 || CHIP_6410 || CHIP_6413 || CHIP_6418*/
-
-#ifdef __cplusplus
-}
-#endif
-
-/*----------------------------------------------------------------------------*/
-#endif /* _CSL_CHIPHAL_H_ */
-/******************************************************************************\
-* End of csl_chiphal.h
-\******************************************************************************/
-
diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dma.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dma.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... csl_dma.h\r
-* DATE CREATED.. 06/11/1999 \r
-* LAST MODIFIED. 09/20/2000\r
-*\r
-\******************************************************************************/\r
-#ifndef _CSL_DMA_H_\r
-#define _CSL_DMA_H_\r
-\r
-#include <csl_chip.h>\r
-#include <csl_dmahal.h>\r
-#include <csl_irq.h>\r
-\r
-\r
-#if (DMA_SUPPORT)\r
-/******************************************************************************\\r
-* scope and inline control macros\r
-\******************************************************************************/\r
-#ifdef __cplusplus\r
-#define CSLAPI extern "C" far \r
-#else\r
-#define CSLAPI extern far\r
-#endif\r
-\r
-#undef USEDEFS\r
-#undef IDECL\r
-#undef IDEF\r
-\r
-#ifdef _DMA_MOD_\r
- #define IDECL CSLAPI\r
- #define USEDEFS\r
- #define IDEF\r
-#else\r
- #ifdef _INLINE\r
- #define IDECL static inline\r
- #define USEDEFS\r
- #define IDEF static inline\r
- #else\r
- #define IDECL CSLAPI\r
- #endif\r
-#endif\r
-\r
-\r
-/******************************************************************************\\r
-* global macro declarations\r
-\******************************************************************************/\r
-#define DMA_CHA_CNT 4\r
-\r
-/* DMA_open() flags */\r
-#define DMA_OPEN_RESET 0x00000001u\r
-\r
-/* channel identifiers for DMA_open() */\r
-#define DMA_CHAANY (-1)\r
-#define DMA_CHA0 (0)\r
-#define DMA_CHA1 (1)\r
-#define DMA_CHA2 (2)\r
-#define DMA_CHA3 (3)\r
-\r
-/* DMA status state */\r
-#define DMA_STATUS_STOPPED DMA_PRICTL_STATUS_STOPPED\r
-#define DMA_STATUS_RUNNING DMA_PRICTL_STATUS_RUNNING\r
-#define DMA_STATUS_PAUSED DMA_PRICTL_STATUS_PAUSED\r
-#define DMA_STATUS_AUTORUNNING DMA_PRICTL_STATUS_AUTORUNNING\r
-\r
-/* predefined global register IDs */\r
-#define DMA_GBL_ADDRRLDB 0x00000001u\r
-#define DMA_GBL_ADDRRLDC 0x00000002u\r
-#define DMA_GBL_ADDRRLDD 0x00000003u\r
-#define DMA_GBL_INDEXA 0x00000004u\r
-#define DMA_GBL_INDEXB 0x00000005u\r
-#define DMA_GBL_CNTRLDA 0x00000008u\r
-#define DMA_GBL_CNTRLDB 0x00000009u\r
-#define DMA_GBL_SPLITA 0x0000000Du\r
-#define DMA_GBL_SPLITB 0x0000000Eu\r
-#define DMA_GBL_SPLITC 0x0000000Fu\r
-\r
-#define DMA_GBLADDRA 0x00000001u\r
-#define DMA_GBLADDRB 0x00000002u\r
-#define DMA_GBLADDRC 0x00000004u\r
-#define DMA_GBLADDRD 0x00000008u\r
-#define DMA_GBLIDXA 0x00000010u\r
-#define DMA_GBLIDXB 0x00000020u\r
-#define DMA_GBLCNTA 0x00000040u\r
-#define DMA_GBLCNTB 0x00000080u\r
-\r
-#define _DMA_GBLREG_CNT 16\r
-#define _DMA_GBLREG_MASK (_DMA_GBLREG_CNT-1)\r
-\r
-/****************************************************************/\r
-/* The two following macros are used to get/clear the condition */\r
-/* flags of the DMA SECCTL register in a safe manner. */\r
-/* */\r
-/* The X argument MUST be one of the following: */\r
-/* DMA_SECCTL_SXCOND */\r
-/* DMA_SECCTL_FRAMECOND */\r
-/* DMA_SECCTL_LASTCOND */\r
-/* DMA_SECCTL_BLOCKCOND */\r
-/* DMA_SECCTL_RDROPCOND */\r
-/* DMA_SECCTL_WDROPCOND */\r
-/****************************************************************/\r
-\r
-#define DMA_GET_CONDITION(hDma,X) \\r
- ((DMA_RGETH(hDma,SECCTL)&_##X##_MASK)>>_##X##_SHIFT)\r
-\r
-#define DMA_CLEAR_CONDITION(hDma,X) \\r
- _PER_RAOI(DMA_ADDRH(hDma,SECCTL),DMA,SECCTL,\\r
- (0xFFFF0AAA&~_##X##_MASK),\\r
- (0x00000555&~_##X##_MASK),\\r
- 0x00000000\\r
- )\r
-\r
-\r
-/******************************************************************************\\r
-* global typedef declarations\r
-\******************************************************************************/\r
-\r
-/* private object, not to be used by application code */\r
-typedef struct {\r
- Uint32 allocated;\r
- Uint32 eventId;\r
- Uint32 volatile *baseAddr;\r
-} DMA_Obj,*DMA_Handle;\r
-\r
-/* channel configuration structure */\r
-typedef struct {\r
- Uint32 prictl;\r
- Uint32 secctl;\r
- Uint32 src;\r
- Uint32 dst;\r
- Uint32 xfrcnt;\r
-} DMA_Config;\r
-\r
-typedef enum {\r
- DMA_GBL_ADDRRLD = 0x00,\r
- DMA_GBL_INDEX = 0x04,\r
- DMA_GBL_CNTRLD = 0x08,\r
- DMA_GBL_SPLIT = 0x0C\r
-} DMA_Gbl;\r
-\r
-typedef struct {\r
- Uint32 addrA;\r
- Uint32 addrB;\r
- Uint32 addrC;\r
- Uint32 addrD;\r
- Uint32 idxA;\r
- Uint32 idxB;\r
- Uint32 cntA;\r
- Uint32 cntB;\r
-} DMA_GlobalConfig;\r
-\r
-\r
-/******************************************************************************\\r
-* global variable declarations\r
-\******************************************************************************/\r
-extern far Uint32 _DMA_gblRegTbl[_DMA_GBLREG_CNT];\r
-\r
-/* Predefined channel handles, these are only here for legacy */\r
-/* purposes and should not be used. */\r
-extern far DMA_Handle _DMA_hCha0;\r
-extern far DMA_Handle _DMA_hCha1;\r
-extern far DMA_Handle _DMA_hCha2;\r
-extern far DMA_Handle _DMA_hCha3;\r
-\r
-\r
-/******************************************************************************\\r
-* global function declarations\r
-\******************************************************************************/\r
-CSLAPI void DMA_reset(DMA_Handle hDma);\r
-\r
-CSLAPI DMA_Handle DMA_open(int chaNum, Uint32 flags);\r
-CSLAPI void DMA_close(DMA_Handle hDma);\r
-\r
-CSLAPI Uint32 DMA_allocGlobalReg(DMA_Gbl regType, Uint32 initVal);\r
-CSLAPI void DMA_freeGlobalReg(Uint32 regId); \r
-\r
-CSLAPI Uint32 DMA_globalAlloc(Uint32 regs);\r
-CSLAPI void DMA_globalFree(Uint32 regs);\r
-\r
-\r
-/******************************************************************************\\r
-* inline function declarations\r
-\******************************************************************************/\r
-IDECL Uint32 DMA_getEventId(DMA_Handle hDma);\r
-IDECL Uint32 DMA_getStatus(DMA_Handle hDma);\r
-IDECL void DMA_restoreStatus(DMA_Handle hDma,Uint32 status); \r
-\r
-IDECL void DMA_start(DMA_Handle hDma);\r
-IDECL void DMA_stop(DMA_Handle hDma);\r
-IDECL void DMA_pause(DMA_Handle hDma);\r
-IDECL void DMA_autoStart(DMA_Handle hDma);\r
-IDECL void DMA_wait(DMA_Handle hDma);\r
-\r
-IDECL void DMA_setAuxCtl(Uint32 auxCtl);\r
-\r
-IDECL Uint32 DMA_getGlobalRegAddr(Uint32 regId);\r
-IDECL Uint32 DMA_getGlobalReg(Uint32 regId);\r
-IDECL void DMA_setGlobalReg(Uint32 regId, Uint32 val);\r
-\r
-IDECL void DMA_config(DMA_Handle hDma, DMA_Config *config);\r
-IDECL void DMA_configArgs(DMA_Handle hDma, Uint32 prictl, Uint32 secctl, \r
- Uint32 src, Uint32 dst, Uint32 xfrcnt);\r
-IDECL void DMA_getConfig(DMA_Handle hDma, DMA_Config *config);\r
- \r
-IDECL void DMA_globalConfig(Uint32 regs, DMA_GlobalConfig *cfg); \r
-IDECL void DMA_globalConfigArgs(Uint32 regs, Uint32 addrA, Uint32 addrB,\r
- Uint32 addrC,Uint32 addrD,Uint32 idxA,Uint32 idxB,Uint32 cntA,Uint32 cntB);\r
-IDECL void DMA_globalGetConfig(Uint32 regs, DMA_GlobalConfig *cfg); \r
-\r
-\r
-/******************************************************************************\\r
-* inline function definitions\r
-\******************************************************************************/\r
-#ifdef USEDEFS\r
-/*----------------------------------------------------------------------------*/\r
-IDEF Uint32 DMA_getEventId(DMA_Handle hDma) {\r
- return (Uint32)(hDma->eventId);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF Uint32 DMA_getStatus(DMA_Handle hDma) {\r
- return (Uint32)DMA_FGETH(hDma,PRICTL,STATUS);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_restoreStatus(DMA_Handle hDma,Uint32 status) {\r
- DMA_FSETH(hDma,PRICTL,START,status);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_start(DMA_Handle hDma) {\r
- DMA_FSETSH(hDma,PRICTL,START,NORMAL);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_stop(DMA_Handle hDma) {\r
- DMA_FSETSH(hDma,PRICTL,START,STOP);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_pause(DMA_Handle hDma) {\r
- DMA_FSETSH(hDma,PRICTL,START,PAUSE);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_autoStart(DMA_Handle hDma) {\r
- DMA_FSETSH(hDma,PRICTL,START,AUTOINIT);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_wait(DMA_Handle hDma) {\r
- while (DMA_getStatus(hDma) & DMA_STATUS_RUNNING);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_setAuxCtl(Uint32 auxCtl) {\r
- DMA_RSET(AUXCTL,auxCtl);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF Uint32 DMA_getGlobalRegAddr(Uint32 regId) {\r
- return _DMA_gblRegTbl[regId&_DMA_GBLREG_MASK];\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF Uint32 DMA_getGlobalReg(Uint32 regId) {\r
- return DMA_RGETA(_DMA_gblRegTbl[regId&_DMA_GBLREG_MASK],REG);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_setGlobalReg(Uint32 regId, Uint32 val) {\r
- DMA_RSETA(_DMA_gblRegTbl[regId&_DMA_GBLREG_MASK],REG,val);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_config(DMA_Handle hDma, DMA_Config *config) {\r
-\r
- Uint32 gie;\r
- volatile Uint32 *base = (volatile Uint32 *)(hDma->baseAddr);\r
- register int prictl,secctl,src,dst,xfrcnt;\r
-\r
- gie = IRQ_globalDisable();\r
-\r
- /* the compiler generates more efficient code if the loads */\r
- /* and stores are grouped together rather than intermixed */\r
- prictl = config->prictl;\r
- secctl = config->secctl;\r
- src = config->src;\r
- dst = config->dst;\r
- xfrcnt = config->xfrcnt;\r
-\r
- base[_DMA_PRICTL_OFFSET] = 0x00000000;\r
- base[_DMA_SECCTL_OFFSET] = secctl;\r
- base[_DMA_SRC_OFFSET] = src;\r
- base[_DMA_DST_OFFSET] = dst;\r
- base[_DMA_XFRCNT_OFFSET] = xfrcnt;\r
- base[_DMA_PRICTL_OFFSET] = prictl;\r
-\r
- IRQ_globalRestore(gie);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_configArgs(DMA_Handle hDma, Uint32 prictl, Uint32 secctl, \r
- Uint32 src, Uint32 dst, Uint32 xfrcnt) {\r
-\r
- Uint32 gie;\r
- volatile Uint32 *base = (volatile Uint32 *)(hDma->baseAddr);\r
-\r
- gie = IRQ_globalDisable();\r
- base[_DMA_PRICTL_OFFSET] = 0x00000000;\r
- base[_DMA_SECCTL_OFFSET] = secctl;\r
- base[_DMA_SRC_OFFSET] = src;\r
- base[_DMA_DST_OFFSET] = dst;\r
- base[_DMA_XFRCNT_OFFSET] = xfrcnt;\r
- base[_DMA_PRICTL_OFFSET] = prictl;\r
- IRQ_globalRestore(gie);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_getConfig(DMA_Handle hDma, DMA_Config *config) {\r
-\r
- Uint32 gie;\r
- volatile Uint32 *base = (volatile Uint32 *)(hDma->baseAddr);\r
- volatile DMA_Config*cfg = (volatile DMA_Config*)config;\r
- register int prictl,secctl,src,dst,xfrcnt;\r
-\r
- gie = IRQ_globalDisable();\r
-\r
- /* the compiler generates more efficient code if the loads */\r
- /* and stores are grouped together rather than intermixed */\r
- prictl = base[_DMA_PRICTL_OFFSET];\r
- secctl = base[_DMA_SECCTL_OFFSET];\r
- src = base[_DMA_SRC_OFFSET];\r
- dst = base[_DMA_DST_OFFSET];\r
- xfrcnt = base[_DMA_XFRCNT_OFFSET];\r
-\r
- cfg->prictl = prictl;\r
- cfg->secctl = secctl;\r
- cfg->src = src;\r
- cfg->dst = dst;\r
- cfg->xfrcnt = xfrcnt;\r
-\r
- IRQ_globalRestore(gie);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_globalConfig(Uint32 regs, DMA_GlobalConfig *cfg) {\r
-\r
- Uint32 gie;\r
- gie = IRQ_globalDisable();\r
- if (regs & DMA_GBLADDRA) DMA_RSET(GBLADDRA,cfg->addrA);\r
- if (regs & DMA_GBLADDRB) DMA_RSET(GBLADDRB,cfg->addrB);\r
- if (regs & DMA_GBLADDRC) DMA_RSET(GBLADDRC,cfg->addrC);\r
- if (regs & DMA_GBLADDRD) DMA_RSET(GBLADDRD,cfg->addrD);\r
- if (regs & DMA_GBLIDXA) DMA_RSET(GBLIDXA,cfg->idxA);\r
- if (regs & DMA_GBLIDXB) DMA_RSET(GBLIDXB,cfg->idxB);\r
- if (regs & DMA_GBLCNTA) DMA_RSET(GBLCNTA,cfg->cntA);\r
- if (regs & DMA_GBLCNTB) DMA_RSET(GBLCNTB,cfg->cntB);\r
- IRQ_globalRestore(gie);\r
-}\r
-\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_globalConfigArgs(Uint32 regs, Uint32 addrA, Uint32 addrB,\r
- Uint32 addrC,Uint32 addrD,Uint32 idxA,Uint32 idxB,Uint32 cntA,Uint32 cntB) {\r
-\r
- Uint32 gie;\r
- gie = IRQ_globalDisable();\r
- if (regs & DMA_GBLADDRA) DMA_RSET(GBLADDRA,addrA);\r
- if (regs & DMA_GBLADDRB) DMA_RSET(GBLADDRB,addrB);\r
- if (regs & DMA_GBLADDRC) DMA_RSET(GBLADDRC,addrC);\r
- if (regs & DMA_GBLADDRD) DMA_RSET(GBLADDRD,addrD);\r
- if (regs & DMA_GBLIDXA) DMA_RSET(GBLIDXA,idxA);\r
- if (regs & DMA_GBLIDXB) DMA_RSET(GBLIDXB,idxB);\r
- if (regs & DMA_GBLCNTA) DMA_RSET(GBLCNTA,cntA);\r
- if (regs & DMA_GBLCNTB) DMA_RSET(GBLCNTB,cntB);\r
- IRQ_globalRestore(gie);\r
-}\r
-\r
-/*----------------------------------------------------------------------------*/\r
-IDEF void DMA_globalGetConfig(Uint32 regs, DMA_GlobalConfig *config) {\r
-\r
- Uint32 gie;\r
- volatile DMA_GlobalConfig* cfg = (volatile DMA_GlobalConfig*)config;\r
-\r
- gie = IRQ_globalDisable();\r
- if (regs & DMA_GBLADDRA) cfg->addrA = DMA_RGET(GBLADDRA);\r
- if (regs & DMA_GBLADDRB) cfg->addrB = DMA_RGET(GBLADDRB);\r
- if (regs & DMA_GBLADDRC) cfg->addrC = DMA_RGET(GBLADDRC);\r
- if (regs & DMA_GBLADDRD) cfg->addrD = DMA_RGET(GBLADDRD);\r
- if (regs & DMA_GBLIDXA) cfg->idxA = DMA_RGET(GBLIDXA);\r
- if (regs & DMA_GBLIDXB) cfg->idxB = DMA_RGET(GBLIDXB);\r
- if (regs & DMA_GBLCNTA) cfg->cntA = DMA_RGET(GBLCNTA);\r
- if (regs & DMA_GBLCNTB) cfg->cntB = DMA_RGET(GBLCNTB);\r
- IRQ_globalRestore(gie);\r
-}\r
-/*----------------------------------------------------------------------------*/\r
-#endif /* USEDEFS */\r
-\r
-\r
-#endif /* DMA_SUPPORT */\r
-#endif /* _CSL_DMA_H_ */\r
-/******************************************************************************\\r
-* End of csl_dma.h\r
-\******************************************************************************/\r
-\r
diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dmahal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_dmahal.h
+++ /dev/null
@@ -1,1197 +0,0 @@
-/******************************************************************************\\r
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.\r
-* All Rights Reserved\r
-*------------------------------------------------------------------------------\r
-* FILENAME...... csl_dmahal.h\r
-* DATE CREATED.. 03/12/1999 \r
-* LAST MODIFIED. 02/05/2002 added 6204/6205 to DMA_COND1\r
-*------------------------------------------------------------------------------\r
-* REGISTERS\r
-*\r
-* AUXCTL - auxiliary control register \r
-* PRICTL0 - channel primary control register 0\r
-* PRICTL1 - channel primary control register 1\r
-* PRICTL2 - channel primary control register 2\r
-* PRICTL3 - channel primary control register 3\r
-* SECCTL0 - channel seccondary control register 0\r
-* SECCTL1 - channel seccondary control register 1\r
-* SECCTL2 - channel seccondary control register 2\r
-* SECCTL3 - channel seccondary control register 3\r
-* SRC0 - channel src address register 0\r
-* SRC1 - channel src address register 1\r
-* SRC2 - channel src address register 2\r
-* SRC3 - channel src address register 3\r
-* DST0 - channel destination address register 0\r
-* DST1 - channel destination address register 1\r
-* DST2 - channel destination address register 2\r
-* DST3 - channel destination address register 3\r
-* XFRCNT0 - channel transfer count register 0\r
-* XFRCNT1 - channel transfer count register 1\r
-* XFRCNT2 - channel transfer count register 2\r
-* XFRCNT3 - channel transfer count register 3\r
-* GBLCNTA - global count reload register A\r
-* GBLCNTB - global count reload register B\r
-* GBLIDXA - global index register A\r
-* GBLIDXB - global index register B\r
-* GBLADDRA - global address reload register A\r
-* GBLADDRB - global address reload register B\r
-* GBLADDRC - global address reload register C\r
-* GBLADDRD - global address reload register D\r
-*\r
-\******************************************************************************/\r
-#ifndef _CSL_DMAHAL_H_\r
-#define _CSL_DMAHAL_H_\r
-\r
-#include <csl_stdinc.h>\r
-#include <csl_chip.h>\r
-\r
-#if (DMA_SUPPORT)\r
-/******************************************************************************\\r
-* MISC section\r
-\******************************************************************************/\r
-\r
- #define _DMA_COND1 (CHIP_6202|CHIP_6203|CHIP_6204|CHIP_6205)\r
-\r
- #define _DMA_BASE_CHA0 0x01840000u\r
- #define _DMA_BASE_CHA1 0x01840040u\r
- #define _DMA_BASE_CHA2 0x01840004u\r
- #define _DMA_BASE_CHA3 0x01840044u\r
-\r
-\r
-/******************************************************************************\\r
-* module level register/field access macros\r
-\******************************************************************************/\r
-\r
- /* ----------------- */\r
- /* FIELD MAKE MACROS */\r
- /* ----------------- */\r
-\r
- #define DMA_FMK(REG,FIELD,x)\\r
- _PER_FMK(DMA,##REG,##FIELD,x)\r
-\r
- #define DMA_FMKS(REG,FIELD,SYM)\\r
- _PER_FMKS(DMA,##REG,##FIELD,##SYM)\r
-\r
-\r
- /* -------------------------------- */\r
- /* RAW REGISTER/FIELD ACCESS MACROS */\r
- /* -------------------------------- */\r
-\r
- #define DMA_ADDR(REG)\\r
- _DMA_##REG##_ADDR\r
-\r
- #define DMA_RGET(REG)\\r
- _PER_RGET(_DMA_##REG##_ADDR,DMA,##REG)\r
-\r
- #define DMA_RSET(REG,x)\\r
- _PER_RSET(_DMA_##REG##_ADDR,DMA,##REG,x)\r
-\r
- #define DMA_FGET(REG,FIELD)\\r
- _DMA_##REG##_FGET(##FIELD)\r
-\r
- #define DMA_FSET(REG,FIELD,x)\\r
- _DMA_##REG##_FSET(##FIELD,##x)\r
-\r
- #define DMA_FSETS(REG,FIELD,SYM)\\r
- _DMA_##REG##_FSETS(##FIELD,##SYM)\r
-\r
-\r
- /* ------------------------------------------ */\r
- /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */\r
- /* ------------------------------------------ */\r
-\r
- #define DMA_RGETA(addr,REG)\\r
- _PER_RGET(addr,DMA,##REG)\r
-\r
- #define DMA_RSETA(addr,REG,x)\\r
- _PER_RSET(addr,DMA,##REG,x)\r
-\r
- #define DMA_FGETA(addr,REG,FIELD)\\r
- _PER_FGET(addr,DMA,##REG,##FIELD)\r
-\r
- #define DMA_FSETA(addr,REG,FIELD,x)\\r
- _PER_FSET(addr,DMA,##REG,##FIELD,x)\r
-\r
- #define DMA_FSETSA(addr,REG,FIELD,SYM)\\r
- _PER_FSETS(addr,DMA,##REG,##FIELD,##SYM)\r
-\r
-\r
- /* ----------------------------------------- */\r
- /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */\r
- /* ----------------------------------------- */\r
-\r
- #define DMA_ADDRH(h,REG)\\r
- (Uint32)(&((h)->baseAddr[_DMA_##REG##_OFFSET]))\r
-\r
- #define DMA_RGETH(h,REG)\\r
- DMA_RGETA(DMA_ADDRH(h,##REG),##REG)\r
-\r
-\r
- #define DMA_RSETH(h,REG,x)\\r
- DMA_RSETA(DMA_ADDRH(h,##REG),##REG,x)\r
-\r
-\r
- #define DMA_FGETH(h,REG,FIELD)\\r
- DMA_FGETA(DMA_ADDRH(h,##REG),##REG,##FIELD)\r
-\r
-\r
- #define DMA_FSETH(h,REG,FIELD,x)\\r
- DMA_FSETA(DMA_ADDRH(h,##REG),##REG,##FIELD,x)\r
-\r
-\r
- #define DMA_FSETSH(h,REG,FIELD,SYM)\\r
- DMA_FSETSA(DMA_ADDRH(h,##REG),##REG,##FIELD,##SYM)\r
-\r
-\r
-\r
-/******************************************************************************\\r
-* _____________________\r
-* | |\r
-* | A U X C T L |\r
-* |___________________|\r
-*\r
-* AUXCTL - auxiliary control register\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) AUXPRI\r
-* (rw) CHPRI\r
-*\r
-\******************************************************************************/\r
- #define _DMA_AUXCTL_ADDR 0x01840070u\r
-\r
- #define _DMA_AUXCTL_AUXPRI_MASK 0x00000010u\r
- #define _DMA_AUXCTL_AUXPRI_SHIFT 0x00000004u\r
- #define DMA_AUXCTL_AUXPRI_DEFAULT 0x00000000u\r
- #define DMA_AUXCTL_AUXPRI_OF(x) _VALUEOF(x)\r
- #define DMA_AUXCTL_AUXPRI_CPU 0x00000000u\r
- #define DMA_AUXCTL_AUXPRI_DMA 0x00000001u\r
-\r
- #define _DMA_AUXCTL_CHPRI_MASK 0x0000000Fu\r
- #define _DMA_AUXCTL_CHPRI_SHIFT 0x00000000u\r
- #define DMA_AUXCTL_CHPRI_DEFAULT 0x00000000u\r
- #define DMA_AUXCTL_CHPRI_OF(x) _VALUEOF(x)\r
- #define DMA_AUXCTL_CHPRI_HIGHEST 0x00000000u\r
- #define DMA_AUXCTL_CHPRI_2ND 0x00000001u\r
- #define DMA_AUXCTL_CHPRI_3RD 0x00000002u\r
- #define DMA_AUXCTL_CHPRI_4TH 0x00000003u\r
- #define DMA_AUXCTL_CHPRI_LOWEST 0x00000004u\r
-\r
- #define DMA_AUXCTL_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_AUXCTL_DEFAULT (Uint32)( \\r
- _PER_FDEFAULT(DMA,AUXCTL,AUXPRI) \\r
- |_PER_FDEFAULT(DMA,AUXCTL,CHPRI) \\r
- )\r
-\r
- #define DMA_AUXCTL_RMK(auxpri,chpri) (Uint32)( \\r
- _PER_FMK(DMA,AUXCTL,AUXPRI,auxpri) \\r
- |_PER_FMK(DMA,AUXCTL,CHPRI,chpri) \\r
- )\r
-\r
- #define _DMA_AUXCTL_FGET(FIELD)\\r
- _PER_FGET(_DMA_AUXCTL_ADDR,DMA,AUXCTL,##FIELD)\r
-\r
- #define _DMA_AUXCTL_FSET(FIELD,field)\\r
- _PER_FSET(_DMA_AUXCTL_ADDR,DMA,AUXCTL,##FIELD,field)\r
-\r
- #define _DMA_AUXCTL_FSETS(FIELD,SYM)\\r
- _PER_FSETS(_DMA_AUXCTL_ADDR,DMA,AUXCTL,##FIELD,##SYM)\r
-\r
-\r
-/******************************************************************************\\r
-* _____________________\r
-* | |\r
-* | P R I C T L |\r
-* |___________________|\r
-*\r
-* PRICTL0 - channel primary control register 0\r
-* PRICTL1 - channel primary control register 1\r
-* PRICTL2 - channel primary control register 2\r
-* PRICTL3 - channel primary control register 3\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) DSTRLD\r
-* (rw) SRCRLD\r
-* (rw) EMOD\r
-* (rw) FS\r
-* (rw) TCINT\r
-* (rw) PRI\r
-* (rw) WSYNC\r
-* (rw) RSYNC\r
-* (rw) INDEX\r
-* (rw) CNTRLD\r
-* (rw) SPLIT\r
-* (rw) ESIZE\r
-* (rw) DSTDIR\r
-* (rw) SRCDIR\r
-* (r) STATUS\r
-* (rw) START\r
-*\r
-\******************************************************************************/\r
- #define _DMA_PRICTL_OFFSET 0\r
-\r
- #define _DMA_PRICTL0_ADDR 0x01840000u\r
- #define _DMA_PRICTL1_ADDR 0x01840040u\r
- #define _DMA_PRICTL2_ADDR 0x01840004u\r
- #define _DMA_PRICTL3_ADDR 0x01840044u\r
-\r
- #define _DMA_PRICTL_DSTRLD_MASK 0xC0000000u\r
- #define _DMA_PRICTL_DSTRLD_SHIFT 0x0000001Eu\r
- #define DMA_PRICTL_DSTRLD_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_DSTRLD_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_DSTRLD_NONE 0x00000000u\r
- #define DMA_PRICTL_DSTRLD_B 0x00000001u\r
- #define DMA_PRICTL_DSTRLD_C 0x00000002u\r
- #define DMA_PRICTL_DSTRLD_D 0x00000003u\r
-\r
- #define _DMA_PRICTL_SRCRLD_MASK 0x30000000u\r
- #define _DMA_PRICTL_SRCRLD_SHIFT 0x0000001Cu\r
- #define DMA_PRICTL_SRCRLD_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_SRCRLD_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_SRCRLD_NONE 0x00000000u\r
- #define DMA_PRICTL_SRCRLD_B 0x00000001u\r
- #define DMA_PRICTL_SRCRLD_C 0x00000002u\r
- #define DMA_PRICTL_SRCRLD_D 0x00000003u\r
-\r
- #define _DMA_PRICTL_EMOD_MASK 0x08000000u\r
- #define _DMA_PRICTL_EMOD_SHIFT 0x0000001Bu\r
- #define DMA_PRICTL_EMOD_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_EMOD_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_EMOD_NOHALT 0x00000000u\r
- #define DMA_PRICTL_EMOD_HALT 0x00000001u\r
-\r
- #define _DMA_PRICTL_FS_MASK 0x04000000u\r
- #define _DMA_PRICTL_FS_SHIFT 0x0000001Au\r
- #define DMA_PRICTL_FS_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_FS_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_FS_DISABLE 0x00000000u\r
- #define DMA_PRICTL_FS_RSYNC 0x00000001u\r
-\r
- #define _DMA_PRICTL_TCINT_MASK 0x02000000u\r
- #define _DMA_PRICTL_TCINT_SHIFT 0x00000019u\r
- #define DMA_PRICTL_TCINT_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_TCINT_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_TCINT_DISABLE 0x00000000u\r
- #define DMA_PRICTL_TCINT_ENABLE 0x00000001u\r
-\r
- #define _DMA_PRICTL_PRI_MASK 0x01000000u\r
- #define _DMA_PRICTL_PRI_SHIFT 0x00000018u\r
- #define DMA_PRICTL_PRI_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_PRI_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_PRI_CPU 0x00000000u\r
- #define DMA_PRICTL_PRI_DMA 0x00000001u\r
-\r
- #define _DMA_PRICTL_WSYNC_MASK 0x00F80000u\r
- #define _DMA_PRICTL_WSYNC_SHIFT 0x00000013u\r
- #define DMA_PRICTL_WSYNC_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_WSYNC_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_WSYNC_NONE 0x00000000u\r
- #define DMA_PRICTL_WSYNC_TINT0 0x00000001u\r
- #define DMA_PRICTL_WSYNC_TINT1 0x00000002u\r
- #define DMA_PRICTL_WSYNC_SDINT 0x00000003u\r
- #define DMA_PRICTL_WSYNC_EXTINT4 0x00000004u\r
- #define DMA_PRICTL_WSYNC_EXTINT5 0x00000005u\r
- #define DMA_PRICTL_WSYNC_EXTINT6 0x00000006u\r
- #define DMA_PRICTL_WSYNC_EXTINT7 0x00000007u\r
- #define DMA_PRICTL_WSYNC_DMAINT0 0x00000008u\r
- #define DMA_PRICTL_WSYNC_DMAINT1 0x00000009u\r
- #define DMA_PRICTL_WSYNC_DMAINT2 0x0000000Au\r
- #define DMA_PRICTL_WSYNC_DMAINT3 0x0000000Bu\r
- #define DMA_PRICTL_WSYNC_XEVT0 0x0000000Cu\r
- #define DMA_PRICTL_WSYNC_REVT0 0x0000000Du\r
- #define DMA_PRICTL_WSYNC_XEVT1 0x0000000Eu\r
- #define DMA_PRICTL_WSYNC_REVT1 0x0000000Fu\r
- #define DMA_PRICTL_WSYNC_DSPINT 0x00000010u\r
- #define DMA_PRICTL_WSYNC_XEVT2 0x00000011u\r
- #define DMA_PRICTL_WSYNC_REVT2 0x00000012u\r
-\r
- #define _DMA_PRICTL_RSYNC_MASK 0x0007C000u\r
- #define _DMA_PRICTL_RSYNC_SHIFT 0x0000000Eu\r
- #define DMA_PRICTL_RSYNC_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_RSYNC_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_RSYNC_NONE 0x00000000u\r
- #define DMA_PRICTL_RSYNC_TINT0 0x00000001u\r
- #define DMA_PRICTL_RSYNC_TINT1 0x00000002u\r
- #define DMA_PRICTL_RSYNC_SDINT 0x00000003u\r
- #define DMA_PRICTL_RSYNC_EXTINT4 0x00000004u\r
- #define DMA_PRICTL_RSYNC_EXTINT5 0x00000005u\r
- #define DMA_PRICTL_RSYNC_EXTINT6 0x00000006u\r
- #define DMA_PRICTL_RSYNC_EXTINT7 0x00000007u\r
- #define DMA_PRICTL_RSYNC_DMAINT0 0x00000008u\r
- #define DMA_PRICTL_RSYNC_DMAINT1 0x00000009u\r
- #define DMA_PRICTL_RSYNC_DMAINT2 0x0000000Au\r
- #define DMA_PRICTL_RSYNC_DMAINT3 0x0000000Bu\r
- #define DMA_PRICTL_RSYNC_XEVT0 0x0000000Cu\r
- #define DMA_PRICTL_RSYNC_REVT0 0x0000000Du\r
- #define DMA_PRICTL_RSYNC_XEVT1 0x0000000Eu\r
- #define DMA_PRICTL_RSYNC_REVT1 0x0000000Fu\r
- #define DMA_PRICTL_RSYNC_DSPINT 0x00000010u\r
- #define DMA_PRICTL_RSYNC_XEVT2 0x00000011u\r
- #define DMA_PRICTL_RSYNC_REVT2 0x00000012u\r
-\r
- #define _DMA_PRICTL_INDEX_MASK 0x00002000u\r
- #define _DMA_PRICTL_INDEX_SHIFT 0x0000000Du\r
- #define DMA_PRICTL_INDEX_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_INDEX_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_INDEX_NA 0x00000000u\r
- #define DMA_PRICTL_INDEX_A 0x00000000u\r
- #define DMA_PRICTL_INDEX_B 0x00000001u\r
-\r
- #define _DMA_PRICTL_CNTRLD_MASK 0x00001000u\r
- #define _DMA_PRICTL_CNTRLD_SHIFT 0x0000000Cu\r
- #define DMA_PRICTL_CNTRLD_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_CNTRLD_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_CNTRLD_NA 0x00000000u\r
- #define DMA_PRICTL_CNTRLD_A 0x00000000u\r
- #define DMA_PRICTL_CNTRLD_B 0x00000001u\r
-\r
- #define _DMA_PRICTL_SPLIT_MASK 0x00000C00u\r
- #define _DMA_PRICTL_SPLIT_SHIFT 0x0000000Au\r
- #define DMA_PRICTL_SPLIT_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_SPLIT_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_SPLIT_DISABLE 0x00000000u\r
- #define DMA_PRICTL_SPLIT_A 0x00000001u\r
- #define DMA_PRICTL_SPLIT_B 0x00000002u\r
- #define DMA_PRICTL_SPLIT_C 0x00000003u\r
-\r
- #define _DMA_PRICTL_ESIZE_MASK 0x00000300u\r
- #define _DMA_PRICTL_ESIZE_SHIFT 0x00000008u\r
- #define DMA_PRICTL_ESIZE_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_ESIZE_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_ESIZE_32BIT 0x00000000u\r
- #define DMA_PRICTL_ESIZE_16BIT 0x00000001u\r
- #define DMA_PRICTL_ESIZE_8BIT 0x00000002u\r
-\r
- #define _DMA_PRICTL_DSTDIR_MASK 0x000000C0u\r
- #define _DMA_PRICTL_DSTDIR_SHIFT 0x00000006u\r
- #define DMA_PRICTL_DSTDIR_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_DSTDIR_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_DSTDIR_NONE 0x00000000u\r
- #define DMA_PRICTL_DSTDIR_INC 0x00000001u\r
- #define DMA_PRICTL_DSTDIR_DEC 0x00000002u\r
- #define DMA_PRICTL_DSTDIR_IDX 0x00000003u\r
-\r
- #define _DMA_PRICTL_SRCDIR_MASK 0x00000030u\r
- #define _DMA_PRICTL_SRCDIR_SHIFT 0x00000004u\r
- #define DMA_PRICTL_SRCDIR_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_SRCDIR_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_SRCDIR_NONE 0x00000000u\r
- #define DMA_PRICTL_SRCDIR_INC 0x00000001u\r
- #define DMA_PRICTL_SRCDIR_DEC 0x00000002u\r
- #define DMA_PRICTL_SRCDIR_IDX 0x00000003u\r
-\r
- #define _DMA_PRICTL_STATUS_MASK 0x0000000Cu\r
- #define _DMA_PRICTL_STATUS_SHIFT 0x00000002u\r
- #define DMA_PRICTL_STATUS_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_STATUS_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_STATUS_STOPPED 0x00000000u\r
- #define DMA_PRICTL_STATUS_RUNNING 0x00000001u\r
- #define DMA_PRICTL_STATUS_PAUSED 0x00000002u\r
- #define DMA_PRICTL_STATUS_AUTORUNNING 0x00000003u\r
-\r
- #define _DMA_PRICTL_START_MASK 0x00000003u\r
- #define _DMA_PRICTL_START_SHIFT 0x00000000u\r
- #define DMA_PRICTL_START_DEFAULT 0x00000000u\r
- #define DMA_PRICTL_START_OF(x) _VALUEOF(x)\r
- #define DMA_PRICTL_START_STOP 0x00000000u\r
- #define DMA_PRICTL_START_NORMAL 0x00000001u\r
- #define DMA_PRICTL_START_PAUSE 0x00000002u\r
- #define DMA_PRICTL_START_AUTOINIT 0x00000003u\r
-\r
- #define DMA_PRICTL_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_PRICTL_DEFAULT (Uint32)( \\r
- _PER_FDEFAULT(DMA,PRICTL,DSTRLD)\\r
- |_PER_FDEFAULT(DMA,PRICTL,SRCRLD)\\r
- |_PER_FDEFAULT(DMA,PRICTL,EMOD)\\r
- |_PER_FDEFAULT(DMA,PRICTL,FS)\\r
- |_PER_FDEFAULT(DMA,PRICTL,TCINT)\\r
- |_PER_FDEFAULT(DMA,PRICTL,PRI)\\r
- |_PER_FDEFAULT(DMA,PRICTL,WSYNC)\\r
- |_PER_FDEFAULT(DMA,PRICTL,RSYNC)\\r
- |_PER_FDEFAULT(DMA,PRICTL,INDEX)\\r
- |_PER_FDEFAULT(DMA,PRICTL,CNTRLD)\\r
- |_PER_FDEFAULT(DMA,PRICTL,SPLIT)\\r
- |_PER_FDEFAULT(DMA,PRICTL,ESIZE)\\r
- |_PER_FDEFAULT(DMA,PRICTL,DSTDIR)\\r
- |_PER_FDEFAULT(DMA,PRICTL,SRCDIR)\\r
- |_PER_FDEFAULT(DMA,PRICTL,STATUS)\\r
- |_PER_FDEFAULT(DMA,PRICTL,START)\\r
- )\r
-\r
- #define DMA_PRICTL_RMK(dstrld,srcrld,emod,fs,tcint,pri,wsync,rsync,index,\\r
- cntrld,split,esize,dstdir,srcdir,start) (Uint32)( \\r
- _PER_FMK(DMA,PRICTL,DSTRLD,dstrld)\\r
- |_PER_FMK(DMA,PRICTL,SRCRLD,srcrld)\\r
- |_PER_FMK(DMA,PRICTL,EMOD,emod)\\r
- |_PER_FMK(DMA,PRICTL,FS,fs)\\r
- |_PER_FMK(DMA,PRICTL,TCINT,tcint)\\r
- |_PER_FMK(DMA,PRICTL,PRI,pri)\\r
- |_PER_FMK(DMA,PRICTL,WSYNC,wsync)\\r
- |_PER_FMK(DMA,PRICTL,RSYNC,rsync)\\r
- |_PER_FMK(DMA,PRICTL,INDEX,index)\\r
- |_PER_FMK(DMA,PRICTL,CNTRLD,cntrld)\\r
- |_PER_FMK(DMA,PRICTL,SPLIT,split)\\r
- |_PER_FMK(DMA,PRICTL,ESIZE,esize)\\r
- |_PER_FMK(DMA,PRICTL,DSTDIR,dstdir)\\r
- |_PER_FMK(DMA,PRICTL,SRCDIR,srcdir)\\r
- |_PER_FMK(DMA,PRICTL,START,start)\\r
- )\r
-\r
- #define _DMA_PRICTL_FGET(N,FIELD)\\r
- _PER_FGET(_DMA_PRICTL##N##_ADDR,DMA,PRICTL,##FIELD)\r
-\r
- #define _DMA_PRICTL_FSET(N,FIELD,field)\\r
- _PER_FSET(_DMA_PRICTL##N##_ADDR,DMA,PRICTL,##FIELD,field)\r
-\r
- #define _DMA_PRICTL_FSETS(N,FIELD,SYM)\\r
- _PER_FSETS(_DMA_PRICTL##N##_ADDR,DMA,PRICTL,##FIELD,##SYM)\r
-\r
- #define _DMA_PRICTL0_FGET(FIELD) _DMA_PRICTL_FGET(0,##FIELD)\r
- #define _DMA_PRICTL1_FGET(FIELD) _DMA_PRICTL_FGET(1,##FIELD)\r
- #define _DMA_PRICTL2_FGET(FIELD) _DMA_PRICTL_FGET(2,##FIELD)\r
- #define _DMA_PRICTL3_FGET(FIELD) _DMA_PRICTL_FGET(3,##FIELD)\r
-\r
- #define _DMA_PRICTL0_FSET(FIELD,f) _DMA_PRICTL_FSET(0,##FIELD,f)\r
- #define _DMA_PRICTL1_FSET(FIELD,f) _DMA_PRICTL_FSET(1,##FIELD,f)\r
- #define _DMA_PRICTL2_FSET(FIELD,f) _DMA_PRICTL_FSET(2,##FIELD,f)\r
- #define _DMA_PRICTL3_FSET(FIELD,f) _DMA_PRICTL_FSET(3,##FIELD,f)\r
-\r
- #define _DMA_PRICTL0_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(0,##FIELD,##SYM)\r
- #define _DMA_PRICTL1_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(1,##FIELD,##SYM)\r
- #define _DMA_PRICTL2_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(2,##FIELD,##SYM)\r
- #define _DMA_PRICTL3_FSETS(FIELD,SYM) _DMA_PRICTL_FSETS(3,##FIELD,##SYM)\r
-\r
-\r
-/******************************************************************************\\r
-* _____________________\r
-* | |\r
-* | S E C C T L |\r
-* |___________________|\r
-*\r
-* SECCTL0 - channel seccondary control register 0\r
-* SECCTL1 - channel seccondary control register 1\r
-* SECCTL2 - channel seccondary control register 2\r
-* SECCTL3 - channel seccondary control register 3\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) WSPOL (1)\r
-* (rw) RSPOL (1)\r
-* (rw) FSIG (1)\r
-* (rw) DMACEN\r
-* (rw) WSYNCCLR\r
-* (rw) WSYNCSTAT\r
-* (rw) RSYNCCLR\r
-* (rw) RSYNCSTAT\r
-* (rw) WDROPIE\r
-* (rw) WDROPCOND\r
-* (rw) RDROPIE\r
-* (rw) RDROPCOND\r
-* (rw) BLOCKIE\r
-* (rw) BLOCKCOND\r
-* (rw) LASTIE\r
-* (rw) LASTCOND\r
-* (rw) FRAMEIE\r
-* (rw) FRAMECOND\r
-* (rw) SXIE\r
-* (rw) SXCOND\r
-*\r
-* (1) only on 6202 / 6203 /6204 /6205 devices\r
-*\r
-\******************************************************************************/\r
- #define _DMA_SECCTL_OFFSET 2\r
-\r
- #define _DMA_SECCTL0_ADDR 0x01840008u\r
- #define _DMA_SECCTL1_ADDR 0x01840048u\r
- #define _DMA_SECCTL2_ADDR 0x0184000Cu\r
- #define _DMA_SECCTL3_ADDR 0x0184004Cu\r
-\r
-#if (_DMA_COND1)\r
- #define _DMA_SECCTL_WSPOL_MASK 0x00200000u\r
- #define _DMA_SECCTL_WSPOL_SHIFT 0x00000015u\r
- #define DMA_SECCTL_WSPOL_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_WSPOL_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_WSPOL_NA 0x00000000u\r
- #define DMA_SECCTL_WSPOL_ACTIVEHIGH 0x00000000u\r
- #define DMA_SECCTL_WSPOL_ACTIVELOW 0x00000001u\r
-\r
- #define _DMA_SECCTL_RSPOL_MASK 0x00100000u\r
- #define _DMA_SECCTL_RSPOL_SHIFT 0x00000014u\r
- #define DMA_SECCTL_RSPOL_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_RSPOL_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_RSPOL_NA 0x00000000u\r
- #define DMA_SECCTL_RSPOL_ACTIVEHIGH 0x00000000u\r
- #define DMA_SECCTL_RSPOL_ACTIVELOW 0x00000001u\r
-\r
- #define _DMA_SECCTL_FSIG_MASK 0x00080000u\r
- #define _DMA_SECCTL_FSIG_SHIFT 0x00000013u\r
- #define DMA_SECCTL_FSIG_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_FSIG_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_FSIG_NA 0x00000000u\r
- #define DMA_SECCTL_FSIG_NORMAL 0x00000000u\r
- #define DMA_SECCTL_FSIG_IGNORE 0x00000001u\r
-#endif\r
-\r
- #define _DMA_SECCTL_DMACEN_MASK 0x00070000u\r
- #define _DMA_SECCTL_DMACEN_SHIFT 0x00000010u\r
- #define DMA_SECCTL_DMACEN_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_DMACEN_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_DMACEN_LOW 0x00000000u\r
- #define DMA_SECCTL_DMACEN_HIGH 0x00000001u\r
- #define DMA_SECCTL_DMACEN_RSYNCSTAT 0x00000002u\r
- #define DMA_SECCTL_DMACEN_WSYNCSTAT 0x00000003u\r
- #define DMA_SECCTL_DMACEN_FRAMECOND 0x00000004u\r
- #define DMA_SECCTL_DMACEN_BLOCKCOND 0x00000005u\r
-\r
- #define _DMA_SECCTL_WSYNCCLR_MASK 0x00008000u\r
- #define _DMA_SECCTL_WSYNCCLR_SHIFT 0x0000000Fu\r
- #define DMA_SECCTL_WSYNCCLR_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_WSYNCCLR_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_WSYNCCLR_NOTHING 0x00000000u\r
- #define DMA_SECCTL_WSYNCCLR_CLEAR 0x00000001u\r
-\r
- #define _DMA_SECCTL_WSYNCSTAT_MASK 0x00004000u\r
- #define _DMA_SECCTL_WSYNCSTAT_SHIFT 0x0000000Eu\r
- #define DMA_SECCTL_WSYNCSTAT_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_WSYNCSTAT_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_WSYNCSTAT_CLEAR 0x00000000u\r
- #define DMA_SECCTL_WSYNCSTAT_SET 0x00000001u\r
-\r
- #define _DMA_SECCTL_RSYNCCLR_MASK 0x00002000u\r
- #define _DMA_SECCTL_RSYNCCLR_SHIFT 0x0000000Du\r
- #define DMA_SECCTL_RSYNCCLR_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_RSYNCCLR_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_RSYNCCLR_NOTHING 0x00000000u\r
- #define DMA_SECCTL_RSYNCCLR_CLEAR 0x00000001u\r
-\r
- #define _DMA_SECCTL_RSYNCSTAT_MASK 0x00001000u\r
- #define _DMA_SECCTL_RSYNCSTAT_SHIFT 0x0000000Cu\r
- #define DMA_SECCTL_RSYNCSTAT_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_RSYNCSTAT_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_RSYNCSTAT_CLEAR 0x00000000u\r
- #define DMA_SECCTL_RSYNCSTAT_SET 0x00000001u\r
-\r
- #define _DMA_SECCTL_WDROPIE_MASK 0x00000800u\r
- #define _DMA_SECCTL_WDROPIE_SHIFT 0x0000000Bu\r
- #define DMA_SECCTL_WDROPIE_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_WDROPIE_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_WDROPIE_DISABLE 0x00000000u\r
- #define DMA_SECCTL_WDROPIE_ENABLE 0x00000001u\r
-\r
- #define _DMA_SECCTL_WDROPCOND_MASK 0x00000400u\r
- #define _DMA_SECCTL_WDROPCOND_SHIFT 0x0000000Au\r
- #define DMA_SECCTL_WDROPCOND_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_WDROPCOND_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_WDROPCOND_CLEAR 0x00000000u\r
- #define DMA_SECCTL_WDROPCOND_SET 0x00000001u\r
-\r
- #define _DMA_SECCTL_RDROPIE_MASK 0x00000200u\r
- #define _DMA_SECCTL_RDROPIE_SHIFT 0x00000009u\r
- #define DMA_SECCTL_RDROPIE_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_RDROPIE_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_RDROPIE_DISABLE 0x00000000u\r
- #define DMA_SECCTL_RDROPIE_ENABLE 0x00000001u\r
-\r
- #define _DMA_SECCTL_RDROPCOND_MASK 0x00000100u\r
- #define _DMA_SECCTL_RDROPCOND_SHIFT 0x00000008u\r
- #define DMA_SECCTL_RDROPCOND_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_RDROPCOND_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_RDROPCOND_CLEAR 0x00000000u\r
- #define DMA_SECCTL_RDROPCOND_SET 0x00000001u\r
-\r
- #define _DMA_SECCTL_BLOCKIE_MASK 0x00000080u\r
- #define _DMA_SECCTL_BLOCKIE_SHIFT 0x00000007u\r
- #define DMA_SECCTL_BLOCKIE_DEFAULT 0x00000001u\r
- #define DMA_SECCTL_BLOCKIE_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_BLOCKIE_DISABLE 0x00000000u\r
- #define DMA_SECCTL_BLOCKIE_ENABLE 0x00000001u\r
-\r
- #define _DMA_SECCTL_BLOCKCOND_MASK 0x00000040u\r
- #define _DMA_SECCTL_BLOCKCOND_SHIFT 0x00000006u\r
- #define DMA_SECCTL_BLOCKCOND_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_BLOCKCOND_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_BLOCKCOND_CLEAR 0x00000000u\r
- #define DMA_SECCTL_BLOCKCOND_SET 0x00000001u\r
-\r
- #define _DMA_SECCTL_LASTIE_MASK 0x00000020u\r
- #define _DMA_SECCTL_LASTIE_SHIFT 0x00000005u\r
- #define DMA_SECCTL_LASTIE_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_LASTIE_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_LASTIE_DISABLE 0x00000000u\r
- #define DMA_SECCTL_LASTIE_ENABLE 0x00000001u\r
-\r
- #define _DMA_SECCTL_LASTCOND_MASK 0x00000010u\r
- #define _DMA_SECCTL_LASTCOND_SHIFT 0x00000004u\r
- #define DMA_SECCTL_LASTCOND_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_LASTCOND_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_LASTCOND_CLEAR 0x00000000u\r
- #define DMA_SECCTL_LASTCOND_SET 0x00000001u\r
-\r
- #define _DMA_SECCTL_FRAMEIE_MASK 0x00000008u\r
- #define _DMA_SECCTL_FRAMEIE_SHIFT 0x00000003u\r
- #define DMA_SECCTL_FRAMEIE_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_FRAMEIE_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_FRAMEIE_DISABLE 0x00000000u\r
- #define DMA_SECCTL_FRAMEIE_ENABLE 0x00000001u\r
-\r
- #define _DMA_SECCTL_FRAMECOND_MASK 0x00000004u\r
- #define _DMA_SECCTL_FRAMECOND_SHIFT 0x00000002u\r
- #define DMA_SECCTL_FRAMECOND_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_FRAMECOND_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_FRAMECOND_CLEAR 0x00000000u\r
- #define DMA_SECCTL_FRAMECOND_SET 0x00000001u\r
-\r
- #define _DMA_SECCTL_SXIE_MASK 0x00000002u\r
- #define _DMA_SECCTL_SXIE_SHIFT 0x00000001u\r
- #define DMA_SECCTL_SXIE_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_SXIE_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_SXIE_DISABLE 0x00000000u\r
- #define DMA_SECCTL_SXIE_ENABLE 0x00000001u\r
-\r
- #define _DMA_SECCTL_SXCOND_MASK 0x00000001u\r
- #define _DMA_SECCTL_SXCOND_SHIFT 0x00000000u\r
- #define DMA_SECCTL_SXCOND_DEFAULT 0x00000000u\r
- #define DMA_SECCTL_SXCOND_OF(x) _VALUEOF(x)\r
- #define DMA_SECCTL_SXCOND_CLEAR 0x00000000u\r
- #define DMA_SECCTL_SXCOND_SET 0x00000001u\r
-\r
- #define DMA_SECCTL_OF(x) _VALUEOF(x)\r
-\r
-#if (_DMA_COND1)\r
- #define DMA_SECCTL_DEFAULT (Uint32)( \\r
- _PER_FDEFAULT(DMA,SECCTL,WSPOL)\\r
- |_PER_FDEFAULT(DMA,SECCTL,RSPOL)\\r
- |_PER_FDEFAULT(DMA,SECCTL,FSIG)\\r
- |_PER_FDEFAULT(DMA,SECCTL,DMACEN)\\r
- |_PER_FDEFAULT(DMA,SECCTL,WSYNCCLR)\\r
- |_PER_FDEFAULT(DMA,SECCTL,WSYNCSTAT)\\r
- |_PER_FDEFAULT(DMA,SECCTL,RSYNCCLR)\\r
- |_PER_FDEFAULT(DMA,SECCTL,RSYNCSTAT)\\r
- |_PER_FDEFAULT(DMA,SECCTL,WDROPIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,WDROPCOND)\\r
- |_PER_FDEFAULT(DMA,SECCTL,RDROPIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,RDROPCOND)\\r
- |_PER_FDEFAULT(DMA,SECCTL,BLOCKIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,BLOCKCOND)\\r
- |_PER_FDEFAULT(DMA,SECCTL,LASTIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,LASTCOND)\\r
- |_PER_FDEFAULT(DMA,SECCTL,FRAMEIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,FRAMECOND)\\r
- |_PER_FDEFAULT(DMA,SECCTL,SXIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,SXCOND)\\r
- )\r
-\r
- #define DMA_SECCTL_RMK(wspol,rspol,fsig,dmacen,wsyncclr,wsyncstat,rsyncclr,\\r
- rsyncstat,wdropie,wdropcond,rdropie,rdropcond,blockie,blockcond,\\r
- lastie,lastcond,frameie,framecond,sxie,sxcond) (Uint32)( \\r
- _PER_FMK(DMA,SECCTL,WSPOL,wspol)\\r
- |_PER_FMK(DMA,SECCTL,RSPOL,rspol)\\r
- |_PER_FMK(DMA,SECCTL,FSIG,fsig)\\r
- |_PER_FMK(DMA,SECCTL,DMACEN,dmacen)\\r
- |_PER_FMK(DMA,SECCTL,WSYNCCLR,wsyncclr)\\r
- |_PER_FMK(DMA,SECCTL,WSYNCSTAT,wsyncstat)\\r
- |_PER_FMK(DMA,SECCTL,RSYNCCLR,rsyncclr)\\r
- |_PER_FMK(DMA,SECCTL,RSYNCSTAT,rsyncstat)\\r
- |_PER_FMK(DMA,SECCTL,WDROPIE,wdropie)\\r
- |_PER_FMK(DMA,SECCTL,WDROPCOND,wdropcond)\\r
- |_PER_FMK(DMA,SECCTL,RDROPIE,rdropie)\\r
- |_PER_FMK(DMA,SECCTL,RDROPCOND,rdropcond)\\r
- |_PER_FMK(DMA,SECCTL,BLOCKIE,blockie)\\r
- |_PER_FMK(DMA,SECCTL,BLOCKCOND,blockcond)\\r
- |_PER_FMK(DMA,SECCTL,LASTIE,lastie)\\r
- |_PER_FMK(DMA,SECCTL,LASTCOND,lastcond)\\r
- |_PER_FMK(DMA,SECCTL,FRAMEIE,frameie)\\r
- |_PER_FMK(DMA,SECCTL,FRAMECOND,framecond)\\r
- |_PER_FMK(DMA,SECCTL,SXIE,sxie)\\r
- |_PER_FMK(DMA,SECCTL,SXCOND,sxcond)\\r
- )\r
-#endif\r
-\r
-#if (!_DMA_COND1)\r
- #define DMA_SECCTL_DEFAULT (Uint32)( \\r
- _PER_FDEFAULT(DMA,SECCTL,DMACEN)\\r
- |_PER_FDEFAULT(DMA,SECCTL,WSYNCCLR)\\r
- |_PER_FDEFAULT(DMA,SECCTL,WSYNCSTAT)\\r
- |_PER_FDEFAULT(DMA,SECCTL,RSYNCCLR)\\r
- |_PER_FDEFAULT(DMA,SECCTL,RSYNCSTAT)\\r
- |_PER_FDEFAULT(DMA,SECCTL,WDROPIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,WDROPCOND)\\r
- |_PER_FDEFAULT(DMA,SECCTL,RDROPIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,RDROPCOND)\\r
- |_PER_FDEFAULT(DMA,SECCTL,BLOCKIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,BLOCKCOND)\\r
- |_PER_FDEFAULT(DMA,SECCTL,LASTIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,LASTCOND)\\r
- |_PER_FDEFAULT(DMA,SECCTL,FRAMEIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,FRAMECOND)\\r
- |_PER_FDEFAULT(DMA,SECCTL,SXIE)\\r
- |_PER_FDEFAULT(DMA,SECCTL,SXCOND)\\r
- )\r
-\r
- #define DMA_SECCTL_RMK(dmacen,wsyncclr,wsyncstat,rsyncclr,\\r
- rsyncstat,wdropie,wdropcond,rdropie,rdropcond,blockie,blockcond,\\r
- lastie,lastcond,frameie,framecond,sxie,sxcond) (Uint32)( \\r
- _PER_FMK(DMA,SECCTL,DMACEN,dmacen)\\r
- |_PER_FMK(DMA,SECCTL,WSYNCCLR,wsyncclr)\\r
- |_PER_FMK(DMA,SECCTL,WSYNCSTAT,wsyncstat)\\r
- |_PER_FMK(DMA,SECCTL,RSYNCCLR,rsyncclr)\\r
- |_PER_FMK(DMA,SECCTL,RSYNCSTAT,rsyncstat)\\r
- |_PER_FMK(DMA,SECCTL,WDROPIE,wdropie)\\r
- |_PER_FMK(DMA,SECCTL,WDROPCOND,wdropcond)\\r
- |_PER_FMK(DMA,SECCTL,RDROPIE,rdropie)\\r
- |_PER_FMK(DMA,SECCTL,RDROPCOND,rdropcond)\\r
- |_PER_FMK(DMA,SECCTL,BLOCKIE,blockie)\\r
- |_PER_FMK(DMA,SECCTL,BLOCKCOND,blockcond)\\r
- |_PER_FMK(DMA,SECCTL,LASTIE,lastie)\\r
- |_PER_FMK(DMA,SECCTL,LASTCOND,lastcond)\\r
- |_PER_FMK(DMA,SECCTL,FRAMEIE,frameie)\\r
- |_PER_FMK(DMA,SECCTL,FRAMECOND,framecond)\\r
- |_PER_FMK(DMA,SECCTL,SXIE,sxie)\\r
- |_PER_FMK(DMA,SECCTL,SXCOND,sxcond)\\r
- )\r
-#endif\r
-\r
- #define _DMA_SECCTL_COND_MASK (\\r
- _DMA_SECCTL_WDROPCOND_MASK\\r
- |_DMA_SECCTL_RDROPCOND_MASK\\r
- |_DMA_SECCTL_BLOCKCOND_MASK\\r
- |_DMA_SECCTL_LASTCOND_MASK\\r
- |_DMA_SECCTL_FRAMECOND_MASK\\r
- |_DMA_SECCTL_SXCOND_MASK\\r
- )\r
-\r
- #define _DMA_SECCTL_IE_MASK (\\r
- _DMA_SECCTL_WDROPIE_MASK\\r
- |_DMA_SECCTL_RDROPIE_MASK\\r
- |_DMA_SECCTL_BLOCKIE_MASK\\r
- |_DMA_SECCTL_LASTIE_MASK\\r
- |_DMA_SECCTL_FRAMEIE_MASK\\r
- |_DMA_SECCTL_SXIE_MASK\\r
- )\r
-\r
- #define _DMA_SECCTL_STAT_MASK (\\r
- _DMA_SECCTL_WSYNCSTAT_MASK\\r
- |_DMA_SECCTL_RSYNCSTAT_MASK\\r
- )\r
-\r
- #define _DMA_SECCTL_CLR_MASK (\\r
- _DMA_SECCTL_WSYNCCLR_MASK\\r
- |_DMA_SECCTL_RSYNCCLR_MASK\\r
- )\r
-\r
- #define _DMA_SECCTL_FGET(N,FIELD)\\r
- _PER_FGET(_DMA_SECCTL##N##_ADDR,DMA,SECCTL,##FIELD)\r
-\r
- #define _DMA_SECCTL_FSET(N,FIELD,field)\\r
- _PER_RAOI(_DMA_SECCTL##N##_ADDR,DMA,SECCTL,\\r
- (0xFFFF0AAA&~_DMA_SECCTL_##FIELD##_MASK),\\r
- (0x00000555&~_DMA_SECCTL_##FIELD##_MASK)\\r
- |_PER_FMK(DMA,SECCTL,##FIELD,field),\\r
- 0x00000000\\r
- )\r
-\r
- #define _DMA_SECCTL_FSETS(N,FIELD,SYM)\\r
- _PER_RAOI(_DMA_SECCTL##N##_ADDR,DMA,SECCTL,\\r
- (0xFFFF0AAA&~_DMA_SECCTL_##FIELD##_MASK),\\r
- (0x00000555&~_DMA_SECCTL_##FIELD##_MASK)\\r
- |_PER_FMKS(DMA,SECCTL,##FIELD,##SYM),\\r
- 0x00000000\\r
- )\r
-\r
- #define _DMA_SECCTL0_FGET(FIELD) _DMA_SECCTL_FGET(0,##FIELD)\r
- #define _DMA_SECCTL1_FGET(FIELD) _DMA_SECCTL_FGET(1,##FIELD)\r
- #define _DMA_SECCTL2_FGET(FIELD) _DMA_SECCTL_FGET(2,##FIELD)\r
- #define _DMA_SECCTL3_FGET(FIELD) _DMA_SECCTL_FGET(3,##FIELD)\r
-\r
- #define _DMA_SECCTL0_FSET(FIELD,f) _DMA_SECCTL_FSET(0,##FIELD,f)\r
- #define _DMA_SECCTL1_FSET(FIELD,f) _DMA_SECCTL_FSET(1,##FIELD,f)\r
- #define _DMA_SECCTL2_FSET(FIELD,f) _DMA_SECCTL_FSET(2,##FIELD,f)\r
- #define _DMA_SECCTL3_FSET(FIELD,f) _DMA_SECCTL_FSET(3,##FIELD,f)\r
-\r
- #define _DMA_SECCTL0_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(0,##FIELD,##SYM)\r
- #define _DMA_SECCTL1_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(1,##FIELD,##SYM)\r
- #define _DMA_SECCTL2_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(2,##FIELD,##SYM)\r
- #define _DMA_SECCTL3_FSETS(FIELD,SYM) _DMA_SECCTL_FSETS(3,##FIELD,##SYM)\r
-\r
-\r
-/******************************************************************************\\r
-* _____________________\r
-* | |\r
-* | S R C |\r
-* |___________________|\r
-*\r
-* SRC0 - channel src address register 0\r
-* SRC1 - channel src address register 1\r
-* SRC2 - channel src address register 2\r
-* SRC3 - channel src address register 3\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) SRC\r
-*\r
-\******************************************************************************/\r
- #define _DMA_SRC_OFFSET 4\r
-\r
- #define _DMA_SRC0_ADDR 0x01840010u\r
- #define _DMA_SRC1_ADDR 0x01840050u\r
- #define _DMA_SRC2_ADDR 0x01840014u\r
- #define _DMA_SRC3_ADDR 0x01840054u\r
-\r
- #define _DMA_SRC_SRC_MASK 0xFFFFFFFFu\r
- #define _DMA_SRC_SRC_SHIFT 0x00000000u\r
- #define DMA_SRC_SRC_DEFAULT 0x00000000u\r
- #define DMA_SRC_SRC_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_SRC_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_SRC_DEFAULT (Uint32)( \\r
- _PER_FDEFAULT(DMA,SRC,SRC) \\r
- )\r
-\r
- #define DMA_SRC_RMK(src) (Uint32)( \\r
- _PER_FMK(DMA,SRC,SRC,src) \\r
- )\r
-\r
- #define _DMA_SRC_FGET(N,FIELD)\\r
- _PER_FGET(_DMA_SRC##N##_ADDR,DMA,SRC,##FIELD)\r
-\r
- #define _DMA_SRC_FSET(N,FIELD,field)\\r
- _PER_FSET(_DMA_SRC##N##_ADDR,DMA,SRC,##FIELD,field)\r
-\r
- #define _DMA_SRC_FSETS(N,FIELD,SYM)\\r
- _PER_FSETS(_DMA_SRC##N##_ADDR,DMA,SRC,##FIELD,##SYM)\r
-\r
- #define _DMA_SRC0_FGET(FIELD) _DMA_SRC_FGET(0,##FIELD)\r
- #define _DMA_SRC1_FGET(FIELD) _DMA_SRC_FGET(1,##FIELD)\r
- #define _DMA_SRC2_FGET(FIELD) _DMA_SRC_FGET(2,##FIELD)\r
- #define _DMA_SRC3_FGET(FIELD) _DMA_SRC_FGET(3,##FIELD)\r
-\r
- #define _DMA_SRC0_FSET(FIELD,f) _DMA_SRC_FSET(0,##FIELD,f)\r
- #define _DMA_SRC1_FSET(FIELD,f) _DMA_SRC_FSET(1,##FIELD,f)\r
- #define _DMA_SRC2_FSET(FIELD,f) _DMA_SRC_FSET(2,##FIELD,f)\r
- #define _DMA_SRC3_FSET(FIELD,f) _DMA_SRC_FSET(3,##FIELD,f)\r
-\r
- #define _DMA_SRC0_FSETS(FIELD,SYM) _DMA_SRC_FSETS(0,##FIELD,##SYM)\r
- #define _DMA_SRC1_FSETS(FIELD,SYM) _DMA_SRC_FSETS(1,##FIELD,##SYM)\r
- #define _DMA_SRC2_FSETS(FIELD,SYM) _DMA_SRC_FSETS(2,##FIELD,##SYM)\r
- #define _DMA_SRC3_FSETS(FIELD,SYM) _DMA_SRC_FSETS(3,##FIELD,##SYM)\r
-\r
-\r
-/******************************************************************************\\r
-* _____________________\r
-* | |\r
-* | D S T |\r
-* |___________________|\r
-*\r
-* DST0 - channel destination address register 0\r
-* DST1 - channel destination address register 1\r
-* DST2 - channel destination address register 2\r
-* DST3 - channel destination address register 3\r
-*\r
-* * - handle based\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) DST\r
-*\r
-\******************************************************************************/\r
- #define _DMA_DST_OFFSET 6\r
-\r
- #define _DMA_DST0_ADDR 0x01840018u\r
- #define _DMA_DST1_ADDR 0x01840058u\r
- #define _DMA_DST2_ADDR 0x0184001Cu\r
- #define _DMA_DST3_ADDR 0x0184005Cu\r
-\r
- #define _DMA_DST_DST_MASK 0xFFFFFFFFu\r
- #define _DMA_DST_DST_SHIFT 0x00000000u\r
- #define DMA_DST_DST_DEFAULT 0x00000000u\r
- #define DMA_DST_DST_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_DST_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_DST_DEFAULT (Uint32)( \\r
- _PER_FDEFAULT(DMA,DST,DST) \\r
- )\r
-\r
- #define DMA_DST_RMK(dst) (Uint32)( \\r
- _PER_FMK(DMA,DST,DST,dst) \\r
- )\r
-\r
- #define _DMA_DST_FGET(N,FIELD)\\r
- _PER_FGET(_DMA_DST##N##_ADDR,DMA,DST,##FIELD)\r
-\r
- #define _DMA_DST_FSET(N,FIELD,field)\\r
- _PER_FSET(_DMA_DST##N##_ADDR,DMA,DST,##FIELD,field)\r
-\r
- #define _DMA_DST_FSETS(N,FIELD,SYM)\\r
- _PER_FSETS(_DMA_DST##N##_ADDR,DMA,DST,##FIELD,##SYM)\r
-\r
- #define _DMA_DST0_FGET(FIELD) _DMA_DST_FGET(0,##FIELD)\r
- #define _DMA_DST1_FGET(FIELD) _DMA_DST_FGET(1,##FIELD)\r
- #define _DMA_DST2_FGET(FIELD) _DMA_DST_FGET(2,##FIELD)\r
- #define _DMA_DST3_FGET(FIELD) _DMA_DST_FGET(3,##FIELD)\r
-\r
- #define _DMA_DST0_FSET(FIELD,f) _DMA_DST_FSET(0,##FIELD,f)\r
- #define _DMA_DST1_FSET(FIELD,f) _DMA_DST_FSET(1,##FIELD,f)\r
- #define _DMA_DST2_FSET(FIELD,f) _DMA_DST_FSET(2,##FIELD,f)\r
- #define _DMA_DST3_FSET(FIELD,f) _DMA_DST_FSET(3,##FIELD,f)\r
-\r
- #define _DMA_DST0_FSETS(FIELD,SYM) _DMA_DST_FSETS(0,##FIELD,##SYM)\r
- #define _DMA_DST1_FSETS(FIELD,SYM) _DMA_DST_FSETS(1,##FIELD,##SYM)\r
- #define _DMA_DST2_FSETS(FIELD,SYM) _DMA_DST_FSETS(2,##FIELD,##SYM)\r
- #define _DMA_DST3_FSETS(FIELD,SYM) _DMA_DST_FSETS(3,##FIELD,##SYM)\r
-\r
-\r
-/******************************************************************************\\r
-* _____________________\r
-* | |\r
-* | X F R C N T |\r
-* |___________________|\r
-*\r
-* XFRCNT0 - channel transfer count register 0\r
-* XFRCNT1 - channel transfer count register 1\r
-* XFRCNT2 - channel transfer count register 2\r
-* XFRCNT3 - channel transfer count register 3\r
-*\r
-* * - handle based\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) FRMCNT\r
-* (rw) ELECNT\r
-*\r
-\******************************************************************************/\r
- #define _DMA_XFRCNT_OFFSET 8\r
-\r
- #define _DMA_XFRCNT0_ADDR 0x01840020u\r
- #define _DMA_XFRCNT1_ADDR 0x01840060u\r
- #define _DMA_XFRCNT2_ADDR 0x01840024u\r
- #define _DMA_XFRCNT3_ADDR 0x01840064u\r
-\r
- #define _DMA_XFRCNT_FRMCNT_MASK 0xFFFF0000u\r
- #define _DMA_XFRCNT_FRMCNT_SHIFT 0x00000010u\r
- #define DMA_XFRCNT_FRMCNT_DEFAULT 0x00000000u\r
- #define DMA_XFRCNT_FRMCNT_OF(x) _VALUEOF(x)\r
-\r
- #define _DMA_XFRCNT_ELECNT_MASK 0x0000FFFFu\r
- #define _DMA_XFRCNT_ELECNT_SHIFT 0x00000000u\r
- #define DMA_XFRCNT_ELECNT_DEFAULT 0x00000000u\r
- #define DMA_XFRCNT_ELECNT_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_XFRCNT_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_XFRCNT_DEFAULT (Uint32)( \\r
- _PER_FDEFAULT(DMA,XFRCNT,FRMCNT) \\r
- |_PER_FDEFAULT(DMA,XFRCNT,ELECNT) \\r
- )\r
-\r
- #define DMA_XFRCNT_RMK(frmcnt,elecnt) (Uint32)( \\r
- _PER_FMK(DMA,XFRCNT,FRMCNT,frmcnt) \\r
- |_PER_FMK(DMA,XFRCNT,ELECNT,elecnt) \\r
- )\r
-\r
- #define _DMA_XFRCNT_FGET(N,FIELD)\\r
- _PER_FGET(_DMA_XFRCNT##N##_ADDR,DMA,XFRCNT,##FIELD)\r
-\r
- #define _DMA_XFRCNT_FSET(N,FIELD,field)\\r
- _PER_FSET(_DMA_XFRCNT##N##_ADDR,DMA,XFRCNT,##FIELD,field)\r
-\r
- #define _DMA_XFRCNT_FSETS(N,FIELD,SYM)\\r
- _PER_FSETS(_DMA_XFRCNT##N##_ADDR,DMA,XFRCNT,##FIELD,##SYM)\r
-\r
- #define _DMA_XFRCNT0_FGET(FIELD) _DMA_XFRCNT_FGET(0,##FIELD)\r
- #define _DMA_XFRCNT1_FGET(FIELD) _DMA_XFRCNT_FGET(1,##FIELD)\r
- #define _DMA_XFRCNT2_FGET(FIELD) _DMA_XFRCNT_FGET(2,##FIELD)\r
- #define _DMA_XFRCNT3_FGET(FIELD) _DMA_XFRCNT_FGET(3,##FIELD)\r
-\r
- #define _DMA_XFRCNT0_FSET(FIELD,f) _DMA_XFRCNT_FSET(0,##FIELD,f)\r
- #define _DMA_XFRCNT1_FSET(FIELD,f) _DMA_XFRCNT_FSET(1,##FIELD,f)\r
- #define _DMA_XFRCNT2_FSET(FIELD,f) _DMA_XFRCNT_FSET(2,##FIELD,f)\r
- #define _DMA_XFRCNT3_FSET(FIELD,f) _DMA_XFRCNT_FSET(3,##FIELD,f)\r
-\r
- #define _DMA_XFRCNT0_FSETS(FIELD,SYM) _DMA_XFRCNT_FSETS(0,##FIELD,##SYM)\r
- #define _DMA_XFRCNT1_FSETS(FIELD,SYM) _DMA_XFRCNT_FSETS(1,##FIELD,##SYM)\r
- #define _DMA_XFRCNT2_FSETS(FIELD,SYM) _DMA_XFRCNT_FSETS(2,##FIELD,##SYM)\r
- #define _DMA_XFRCNT3_FSETS(FIELD,SYM) _DMA_XFRCNT_FSETS(3,##FIELD,##SYM)\r
-\r
-\r
-/******************************************************************************\\r
-* _____________________\r
-* | |\r
-* | G B L C N T |\r
-* |___________________|\r
-*\r
-* GBLCNTA - global count reload register A\r
-* GBLCNTB - global count reload register B\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) FRMCNT\r
-* (rw) ELECNT\r
-*\r
-\******************************************************************************/\r
- #define _DMA_GBLCNTA_ADDR 0x01840028u\r
- #define _DMA_GBLCNTB_ADDR 0x0184002Cu\r
-\r
- #define _DMA_GBLCNT_FRMCNT_MASK 0xFFFF0000u\r
- #define _DMA_GBLCNT_FRMCNT_SHIFT 0x00000010u\r
- #define DMA_GBLCNT_FRMCNT_DEFAULT 0x00000000u\r
- #define DMA_GBLCNT_FRMCNT_OF(x) _VALUEOF(x)\r
-\r
- #define _DMA_GBLCNT_ELECNT_MASK 0x0000FFFFu\r
- #define _DMA_GBLCNT_ELECNT_SHIFT 0x00000000u\r
- #define DMA_GBLCNT_ELECNT_DEFAULT 0x00000000u\r
- #define DMA_GBLCNT_ELECNT_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_GBLCNT_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_GBLCNT_DEFAULT (Uint32)( \\r
- _PER_FDEFAULT(DMA,GBLCNT,FRMCNT) \\r
- |_PER_FDEFAULT(DMA,GBLCNT,ELECNT) \\r
- )\r
-\r
- #define DMA_GBLCNT_RMK(frmcnt,elecnt) (Uint32)( \\r
- _PER_FMK(DMA,GBLCNT,FRMCNT,frmcnt) \\r
- |_PER_FMK(DMA,GBLCNT,ELECNT,elecnt) \\r
- )\r
-\r
- #define _DMA_GBLCNT_FGET(N,FIELD)\\r
- _PER_FGET(_DMA_GBLCNT##N##_ADDR,DMA,GBLCNT,##FIELD)\r
-\r
- #define _DMA_GBLCNT_FSET(N,FIELD,field)\\r
- _PER_FSET(_DMA_GBLCNT##N##_ADDR,DMA,GBLCNT,##FIELD,field)\r
-\r
- #define _DMA_GBLCNT_FSETS(N,FIELD,SYM)\\r
- _PER_FSETS(_DMA_GBLCNT##N##_ADDR,DMA,GBLCNT,##FIELD,##SYM)\r
-\r
- #define _DMA_GBLCNTA_FGET(FIELD) _DMA_GBLCNT_FGET(A,FIELD)\r
- #define _DMA_GBLCNTB_FGET(FIELD) _DMA_GBLCNT_FGET(B,FIELD)\r
-\r
- #define _DMA_GBLCNTA_FSET(FIELD,f) _DMA_GBLCNT_FSET(A,FIELD,f)\r
- #define _DMA_GBLCNTB_FSET(FIELD,f) _DMA_GBLCNT_FSET(B,FIELD,f)\r
-\r
- #define _DMA_GBLCNTA_FSETS(FIELD,SYM) _DMA_GBLCNT_FSETS(A,FIELD,SYM)\r
- #define _DMA_GBLCNTB_FSETS(FIELD,SYM) _DMA_GBLCNT_FSETS(B,FIELD,SYM)\r
-\r
-\r
-/******************************************************************************\\r
-* _____________________\r
-* | |\r
-* | G B L I D X |\r
-* |___________________|\r
-*\r
-* GBLIDXA - global index register A\r
-* GBLIDXB - global index register B\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) FRMIDX\r
-* (rw) ELEIDX\r
-*\r
-\******************************************************************************/\r
- #define _DMA_GBLIDXA_ADDR 0x01840030u\r
- #define _DMA_GBLIDXB_ADDR 0x01840034u\r
-\r
- #define _DMA_GBLIDX_FRMIDX_MASK 0xFFFF0000u\r
- #define _DMA_GBLIDX_FRMIDX_SHIFT 0x00000010u\r
- #define DMA_GBLIDX_FRMIDX_DEFAULT 0x00000000u\r
- #define DMA_GBLIDX_FRMIDX_OF(x) _VALUEOF(x)\r
-\r
- #define _DMA_GBLIDX_ELEIDX_MASK 0x0000FFFFu\r
- #define _DMA_GBLIDX_ELEIDX_SHIFT 0x00000000u\r
- #define DMA_GBLIDX_ELEIDX_DEFAULT 0x00000000u\r
- #define DMA_GBLIDX_ELEIDX_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_GBLIDX_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_GBLIDX_DEFAULT (Uint32)( \\r
- _PER_FDEFAULT(DMA,GBLIDX,FRMIDX) \\r
- |_PER_FDEFAULT(DMA,GBLIDX,ELEIDX) \\r
- )\r
-\r
- #define DMA_GBLIDX_RMK(frmidx,eleidx) (Uint32)( \\r
- _PER_FMK(DMA,GBLIDX,FRMIDX,frmidx) \\r
- |_PER_FMK(DMA,GBLIDX,ELEIDX,eleidx) \\r
- )\r
-\r
- #define _DMA_GBLIDX_FGET(N,FIELD)\\r
- _PER_FGET(_DMA_GBLIDX##N##_ADDR,DMA,GBLIDX,##FIELD)\r
-\r
- #define _DMA_GBLIDX_FSET(N,FIELD,field)\\r
- _PER_FSET(_DMA_GBLIDX##N##_ADDR,DMA,GBLIDX,##FIELD,field)\r
-\r
- #define _DMA_GBLIDX_FSETS(N,FIELD,SYM)\\r
- _PER_FSETS(_DMA_GBLIDX##N##_ADDR,DMA,GBLIDX,##FIELD,##SYM)\r
-\r
- #define _DMA_GBLIDXA_FGET(FIELD) _DMA_GBLIDX_FGET(A,FIELD)\r
- #define _DMA_GBLIDXB_FGET(FIELD) _DMA_GBLIDX_FGET(B,FIELD)\r
-\r
- #define _DMA_GBLIDXA_FSET(FIELD,f) _DMA_GBLIDX_FSET(A,FIELD,f)\r
- #define _DMA_GBLIDXB_FSET(FIELD,f) _DMA_GBLIDX_FSET(B,FIELD,f)\r
-\r
- #define _DMA_GBLIDXA_FSETS(FIELD,SYM) _DMA_GBLIDX_FSETS(A,FIELD,SYM)\r
- #define _DMA_GBLIDXB_FSETS(FIELD,SYM) _DMA_GBLIDX_FSETS(B,FIELD,SYM)\r
-\r
-\r
-/******************************************************************************\\r
-* _____________________\r
-* | |\r
-* | G B L A D D R |\r
-* |___________________|\r
-*\r
-* GBLADDRA - global address reload register A\r
-* GBLADDRB - global address reload register B\r
-* GBLADDRC - global address reload register C\r
-* GBLADDRD - global address reload register D\r
-*\r
-* FIELDS (msb -> lsb)\r
-* (rw) GBLADDR\r
-*\r
-\******************************************************************************/\r
- #define _DMA_GBLADDRA_ADDR 0x01840038u\r
- #define _DMA_GBLADDRB_ADDR 0x0184003Cu\r
- #define _DMA_GBLADDRC_ADDR 0x01840068u\r
- #define _DMA_GBLADDRD_ADDR 0x0184006Cu\r
-\r
- #define _DMA_GBLADDR_GBLADDR_MASK 0xFFFFFFFFu\r
- #define _DMA_GBLADDR_GBLADDR_SHIFT 0x00000000u\r
- #define DMA_GBLADDR_GBLADDR_DEFAULT 0x00000000u\r
- #define DMA_GBLADDR_GBLADDR_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_GBLADDR_OF(x) _VALUEOF(x)\r
-\r
- #define DMA_GBLADDR_DEFAULT (Uint32)( \\r
- _PER_FDEFAULT(DMA,GBLADDR,GBLADDR) \\r
- )\r
-\r
- #define DMA_GBLADDR_RMK(gbladdr) (Uint32)( \\r
- _PER_FMK(DMA,GBLADDR,GBLADDR,gbladdr) \\r
- )\r
-\r
- #define _DMA_GBLADDR_FGET(N,FIELD)\\r
- _PER_FGET(_DMA_GBLADDR##N##_ADDR,DMA,GBLADDR,##FIELD)\r
-\r
- #define _DMA_GBLADDR_FSET(N,FIELD,field)\\r
- _PER_FSET(_DMA_GBLADDR##N##_ADDR,DMA,GBLADDR,##FIELD,field)\r
-\r
- #define _DMA_GBLADDR_FSETS(N,FIELD,SYM)\\r
- _PER_FSETS(_DMA_GBLADDR##N##_ADDR,DMA,GBLADDR,##FIELD,##SYM)\r
-\r
- #define _DMA_GBLADDRA_FGET(FIELD) _DMA_GBLADDR_FGET(A,FIELD)\r
- #define _DMA_GBLADDRB_FGET(FIELD) _DMA_GBLADDR_FGET(B,FIELD)\r
- #define _DMA_GBLADDRC_FGET(FIELD) _DMA_GBLADDR_FGET(C,FIELD)\r
- #define _DMA_GBLADDRD_FGET(FIELD) _DMA_GBLADDR_FGET(D,FIELD)\r
-\r
- #define _DMA_GBLADDRA_FSET(FIELD,f) _DMA_GBLADDR_FSET(A,FIELD,f)\r
- #define _DMA_GBLADDRB_FSET(FIELD,f) _DMA_GBLADDR_FSET(B,FIELD,f)\r
- #define _DMA_GBLADDRC_FSET(FIELD,f) _DMA_GBLADDR_FSET(C,FIELD,f)\r
- #define _DMA_GBLADDRD_FSET(FIELD,f) _DMA_GBLADDR_FSET(D,FIELD,f)\r
-\r
- #define _DMA_GBLADDRA_FSETS(FIELD,SYM) _DMA_GBLADDR_FSETS(A,FIELD,SYM)\r
- #define _DMA_GBLADDRB_FSETS(FIELD,SYM) _DMA_GBLADDR_FSETS(B,FIELD,SYM)\r
- #define _DMA_GBLADDRC_FSETS(FIELD,SYM) _DMA_GBLADDR_FSETS(C,FIELD,SYM)\r
- #define _DMA_GBLADDRD_FSETS(FIELD,SYM) _DMA_GBLADDR_FSETS(D,FIELD,SYM)\r
-\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#endif /* DMA_SUPPORT */\r
-#endif /* _CSL_DMAHAL_H_ */\r
-/******************************************************************************\\r
-* End of csl_dmahal.h\r
-\******************************************************************************/\r
diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_edma.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_edma.h
+++ /dev/null
@@ -1,891 +0,0 @@
-/******************************************************************************\
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.
-* All Rights Reserved
-*------------------------------------------------------------------------------
-* FILENAME...... csl_edma.h
-* DATE CREATED.. 06/11/1999
-* LAST MODIFIED. 14/9/2005 Modified EDMA_getChannel and EDMA_setEvtPolarity to return
-* proper values and can set polarities properly respectively.
-* 08/13/2004 Modified tccAllocTable type from static to global fn.
-* 08/02/2004 - Adding support for C6418
-* 04/16/2004 Modified tccAllocTable[0] entry to 0.
-* 02/09/2004 Removed volatile variable type from EDMA_chain inline fn.
-* 06/17/2003 added support for 6712C
-* 05/28/2003 added support for 6711C
-* 02/15/2002 added EDMA channel events 6713/DM642 - EDMA_map()
-* 04/16/2001
-\******************************************************************************/
-#ifndef _CSL_EDMA_H_
-#define _CSL_EDMA_H_
-
-#include <csl_chip.h>
-#include <csl_irq.h>
-#include <csl_edmahal.h>
-
-
-#if (EDMA_SUPPORT)
-/******************************************************************************\
-* scope and inline control macros
-\******************************************************************************/
-#ifdef __cplusplus
-#define CSLAPI extern "C" far
-#else
-#define CSLAPI extern far
-#endif
-
-#undef USEDEFS
-#undef IDECL
-#undef IDEF
-
-#ifdef _EDMA_MOD_
- #define IDECL CSLAPI
- #define USEDEFS
- #define IDEF
-#else
- #ifdef _INLINE
- #define IDECL static inline
- #define USEDEFS
- #define IDEF static inline
- #else
- #define IDECL CSLAPI
- #endif
-#endif
-
-
-/******************************************************************************\
-* global macro declarations
-\******************************************************************************/
-#define EDMA_CHA_CNT (_EDMA_CHA_CNT)
-#define EDMA_TABLE_CNT (_EDMA_LINK_CNT)
-#define EDMA_ALLOC_ANY (-1)
-
-#define EDMA_OPEN_RESET (0x00000001)
-#define EDMA_OPEN_ENABLE (0x00000002)
-
-
-#if(CHIP_6201|CHIP_6202|CHIP_6203|CHIP_6204|CHIP_6205|CHIP_6701|C11_SUPPORT)
- #define EDMA_CHA_ANY -1
- #define EDMA_CHA_DSPINT 0
- #define EDMA_CHA_TINT0 1
- #define EDMA_CHA_TINT1 2
- #define EDMA_CHA_SDINT 3
- #define EDMA_CHA_EXTINT4 4
- #define EDMA_CHA_EXTINT5 5
- #define EDMA_CHA_EXTINT6 6
- #define EDMA_CHA_EXTINT7 7
- #define EDMA_CHA_TCC8 8
- #define EDMA_CHA_TCC9 9
- #define EDMA_CHA_TCC10 10
- #define EDMA_CHA_TCC11 11
- #define EDMA_CHA_XEVT0 12
- #define EDMA_CHA_REVT0 13
- #define EDMA_CHA_XEVT1 14
- #define EDMA_CHA_REVT1 15
-#endif
-#if (CHIP_6711C || CHIP_6712C)
- #define EDMA_CHA_GPINT4 4
- #define EDMA_CHA_GPINT5 5
- #define EDMA_CHA_GPINT6 6
- #define EDMA_CHA_GPINT7 7
- #define EDMA_CHA_GPINT2 10
-#endif
-
-#if (CHIP_6713 | CHIP_DA610 | CHIP_6414 | CHIP_6415 | CHIP_6416 | \
- CHIP_6411 | CHIP_6410 | CHIP_6413 | CHIP_6418)
- #define EDMA_CHA_ANY -1
- #define EDMA_CHA_DSPINT 0
- #define EDMA_CHA_TINT0 1
- #define EDMA_CHA_TINT1 2
- #define EDMA_CHA_SDINT 3
- #define EDMA_CHA_EXTINT4 4
- #define EDMA_CHA_GPINT4 4
- #define EDMA_CHA_EXTINT5 5
- #define EDMA_CHA_GPINT5 5
- #define EDMA_CHA_EXTINT6 6
- #define EDMA_CHA_GPINT6 6
- #define EDMA_CHA_EXTINT7 7
- #define EDMA_CHA_GPINT7 7
- #define EDMA_CHA_TCC8 8
- #define EDMA_CHA_GPINT0 8
- #define EDMA_CHA_TCC9 9
- #define EDMA_CHA_GPINT1 9
- #define EDMA_CHA_TCC10 10
- #define EDMA_CHA_GPINT2 10
- #define EDMA_CHA_TCC11 11
- #define EDMA_CHA_GPINT3 11
- #define EDMA_CHA_XEVT0 12
- #define EDMA_CHA_REVT0 13
- #define EDMA_CHA_XEVT1 14
- #define EDMA_CHA_REVT1 15
-
-/* Individual mappings for next few events are specified under #ifdefs below. */
-
- #define EDMA_CHA_GPINT8 48
- #define EDMA_CHA_GPINT9 49
- #define EDMA_CHA_GPINT10 50
- #define EDMA_CHA_GPINT11 51
- #define EDMA_CHA_GPINT12 52
- #define EDMA_CHA_GPINT13 53
- #define EDMA_CHA_GPINT14 54
- #define EDMA_CHA_GPINT15 55
-#endif
-
-
-/* 3rd MCBSP/ PCI / UTOPIA / VCP / TCP channel numbers for EDMA_open() */
-#if (CHIP_6414 || CHIP_6415 || CHIP_6416 )
- #define EDMA_CHA_XEVT2 17
- #define EDMA_CHA_REVT2 18
- #define EDMA_CHA_TINT2 19
- #define EDMA_CHA_SDINTB 20
- #define EDMA_CHA_PCI 21
- #define EDMA_CHA_VCPREVT 28
- #define EDMA_CHA_VCPXEVT 29
- #define EDMA_CHA_TCPREVT 30
- #define EDMA_CHA_TCPXEVT 31
- #define EDMA_CHA_UREVT 32
- #define EDMA_CHA_UREVT0 32
- #define EDMA_CHA_UREVT1 33
- #define EDMA_CHA_UREVT2 34
- #define EDMA_CHA_UREVT3 35
- #define EDMA_CHA_UREVT4 36
- #define EDMA_CHA_UREVT5 37
- #define EDMA_CHA_UREVT6 38
- #define EDMA_CHA_UREVT7 39
- #define EDMA_CHA_UXEVT 40
- #define EDMA_CHA_UXEVT0 40
- #define EDMA_CHA_UXEVT1 41
- #define EDMA_CHA_UXEVT2 42
- #define EDMA_CHA_UXEVT3 43
- #define EDMA_CHA_UXEVT4 44
- #define EDMA_CHA_UXEVT5 45
- #define EDMA_CHA_UXEVT6 46
- #define EDMA_CHA_UXEVT7 47
-#endif
-
-/* 2 MCASPs - 2 I2Cs channels */
-#if (CHIP_6713 || CHIP_DA610)
- #define EDMA_CHA_AXEVTE0 32
- #define EDMA_CHA_AXEVTO0 33
- #define EDMA_CHA_AXEVT0 34
- #define EDMA_CHA_AREVTE0 35
- #define EDMA_CHA_AREVTO0 36
- #define EDMA_CHA_AREVT0 37
- #define EDMA_CHA_AXEVTE1 38
- #define EDMA_CHA_AXEVTO1 39
- #define EDMA_CHA_AXEVT1 40
- #define EDMA_CHA_AREVTE1 41
- #define EDMA_CHA_AREVTO1 42
- #define EDMA_CHA_AREVT1 43
- #define EDMA_CHA_ICREVT0 44
- #define EDMA_CHA_ICXEVT0 45
- #define EDMA_CHA_ICREVT1 46
- #define EDMA_CHA_ICXEVT1 47
-#endif
-
-#if (CHIP_6410 || CHIP_6413| CHIP_6418)
- #define EDMA_CHA_TINT2 19
-
- #if (CHIP_6418)
- #define EDMA_CHA_VCPREVT0 28
- #define EDMA_CHA_VCPXEVT0 29
- #endif
-
- #define EDMA_CHA_AXEVTE0 32
- #define EDMA_CHA_AXEVTO0 33
- #define EDMA_CHA_AXEVT0 34
- #define EDMA_CHA_AREVTE0 35
- #define EDMA_CHA_AREVTO0 36
- #define EDMA_CHA_AREVT0 37
- #define EDMA_CHA_AXEVTE1 38
- #define EDMA_CHA_AXEVTO1 39
- #define EDMA_CHA_AXEVT1 40
- #define EDMA_CHA_AREVTE1 41
- #define EDMA_CHA_AREVTO1 42
- #define EDMA_CHA_AREVT1 43
- #define EDMA_CHA_ICREVT0 44
- #define EDMA_CHA_ICXEVT0 45
- #define EDMA_CHA_ICREVT1 46
- #define EDMA_CHA_ICXEVT1 47
-#endif
-
-#if (CHIP_DM642 || CHIP_DM641 || CHIP_DM640 || CHIP_6412)
- #define EDMA_CHA_ANY -1
-
- #if !(CHIP_DM640)
- #define EDMA_CHA_DSPINT 0
- #endif
-
- #define EDMA_CHA_TINT0 1
- #define EDMA_CHA_TINT1 2
- #define EDMA_CHA_SDINT 3
- #define EDMA_CHA_EXTINT4 4
- #define EDMA_CHA_GPINT4 4
- #define EDMA_CHA_EXTINT5 5
- #define EDMA_CHA_GPINT5 5
- #define EDMA_CHA_EXTINT6 6
- #define EDMA_CHA_GPINT6 6
- #define EDMA_CHA_EXTINT7 7
- #define EDMA_CHA_GPINT7 7
- #define EDMA_CHA_GPINT0 8
- #define EDMA_CHA_TCC8 8
- #define EDMA_CHA_GPINT1 9
- #define EDMA_CHA_TCC9 9
- #define EDMA_CHA_GPINT2 10
- #define EDMA_CHA_TCC10 10
- #define EDMA_CHA_GPINT3 11
- #define EDMA_CHA_TCC11 11
- #define EDMA_CHA_XEVT0 12
- #define EDMA_CHA_REVT0 13
- #define EDMA_CHA_XEVT1 14
- #define EDMA_CHA_REVT1 15
-
-/* Note: EDMA_CHA_TCC8, EDMA_CHA_TCC9, EDMA_CHA_TCC10 and EDMA_CHA_TCC11 are
- NOT defined here, but they are included here for C64x consistency purposes */
-
- #if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640)
- #define EDMA_CHA_VP0EVTYA 16
- #define EDMA_CHA_VP0EVTUA 17
- #define EDMA_CHA_VP0EVTVA 18
- #endif
-
- #define EDMA_CHA_TINT2 19
-
- #if (CHIP_DM642)
- #define EDMA_CHA_VP0EVTYB 24
- #define EDMA_CHA_VP0EVTUB 25
- #define EDMA_CHA_VP0EVTVB 26
- #endif
-
- #if !(CHIP_6412)
- #define EDMA_CHA_AXEVTE0 32
- #define EDMA_CHA_AXEVTO0 33
- #define EDMA_CHA_AXEVT0 34
- #define EDMA_CHA_AREVTE0 35
- #define EDMA_CHA_AREVTO0 36
- #define EDMA_CHA_AREVT0 37
- #endif
-
- #if (CHIP_DM642)
- #define EDMA_CHA_VP1EVTYB 38
- #define EDMA_CHA_VP1EVTUB 39
- #define EDMA_CHA_VP1EVTVB 40
- #define EDMA_CHA_VP2EVTYB 41
- #define EDMA_CHA_VP2EVTUB 42
- #define EDMA_CHA_VP2EVTVB 43
- #endif
-
- #define EDMA_CHA_ICREVT0 44
- #define EDMA_CHA_ICXEVT0 45
-
- #define EDMA_CHA_GPINT8 48
- #define EDMA_CHA_GPINT9 49
- #define EDMA_CHA_GPINT10 50
- #define EDMA_CHA_GPINT11 51
- #define EDMA_CHA_GPINT12 52
- #define EDMA_CHA_GPINT13 53
- #define EDMA_CHA_GPINT14 54
- #define EDMA_CHA_GPINT15 55
-
-
- #if (CHIP_DM642 | CHIP_DM641)
- #define EDMA_CHA_VP1EVTYA 56
- #define EDMA_CHA_VP1EVTUA 57
- #define EDMA_CHA_VP1EVTVA 58
- #endif
-
- #if (CHIP_DM642)
- #define EDMA_CHA_VP2EVTYA 59
- #define EDMA_CHA_VP2EVTUA 60
- #define EDMA_CHA_VP2EVTVA 61
- #endif
-
-#endif
-
-#define _EDMA_TYPE_C (0x80000000)
-#define _EDMA_TYPE_T (0x40000000)
-#define _EDMA_TYPE_Q (0x20000000)
-#define _EDMA_TYPE_S (0x10000000)
-
-
-#define _EDMA_MK_HANDLE(base,index,flags) (EDMA_Handle)(\
- ((base)&0x0000FFFF)|(((index)<<16)&0x00FF0000)|((flags)&0xFF000000)\
-)
-
-#define EDMA_HQDMA _EDMA_MK_HANDLE(0x00000000,0,_EDMA_TYPE_Q)
-#define EDMA_HQSDMA _EDMA_MK_HANDLE(0x00000000,0,_EDMA_TYPE_S)
-#define EDMA_HINV _EDMA_MK_HANDLE(0x00000000,0,0)
-
-#define EDMA_HNULL _EDMA_MK_HANDLE(_EDMA_NULL_PARAM,0,_EDMA_TYPE_T)
-#define NULL_FUNC 0
-
-/* Priority Queues */
-#define EDMA_Q0 0
-#define EDMA_Q1 1
-#define EDMA_Q2 2
-#define EDMA_Q3 3
-
-/* Event Polarity */
-#define EDMA_EVT_LOWHIGH 0
-#define EDMA_EVT_HIGHLOW 1
-
-/* Chaining Flag */
-#define EDMA_TCC_SET 1
-#define EDMA_ATCC_SET 1
-
-/******************************************************************************\
-* global typedef declarations
-\******************************************************************************/
-typedef Uint32 EDMA_Handle;
-
-typedef struct {
- Uint32 opt;
- Uint32 src;
- Uint32 cnt;
- Uint32 dst;
- Uint32 idx;
- Uint32 rld;
-} EDMA_Config;
-
-typedef void (*EDMA_IntHandler)(int tccNum);
-
-/******************************************************************************\
-* global variable declarations
-\******************************************************************************/
-#define EDMA_hNull EDMA_HNULL
-
-extern far Uint8 tccAllocTable[64];
-
-/******************************************************************************\
-* global function declarations
-\******************************************************************************/
-CSLAPI void EDMA_reset(EDMA_Handle hEdma);
-CSLAPI void EDMA_resetAll();
-
-CSLAPI EDMA_Handle EDMA_open(int chaNum, Uint32 flags);
-CSLAPI void EDMA_close(EDMA_Handle hEdma);
-CSLAPI EDMA_Handle EDMA_allocTable(int tableNum);
-CSLAPI void EDMA_freeTable(EDMA_Handle hEdma);
-
-CSLAPI int EDMA_allocTableEx(int cnt, EDMA_Handle *array);
-CSLAPI void EDMA_freeTableEx(int cnt, EDMA_Handle *array);
-
-CSLAPI void EDMA_clearPram(Uint32 val);
-
-CSLAPI int EDMA_intAlloc(int tcc);
-CSLAPI void EDMA_intFree(int tcc);
-/* 6713? */
-
-#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C)
-CSLAPI int EDMA_map(int eventNum,int chaNum);
-#endif
-
-CSLAPI EDMA_IntHandler EDMA_intHook(int tccNum, EDMA_IntHandler funcAddr);
-CSLAPI void EDMA_intDefaultHandler(int tccNum);
-CSLAPI void EDMA_intDispatcher();
-
-/******************************************************************************\
-* inline function declarations
-\******************************************************************************/
-IDECL Uint32 EDMA_getScratchAddr();
-IDECL Uint32 EDMA_getScratchSize();
-IDECL Uint32 EDMA_getPriQStatus();
-#if (C64_SUPPORT)
-IDECL void EDMA_setPriQLength(Uint32 priNum, Uint32 length);
-IDECL void EDMA_resetPriQLength(Uint32 priNum);
-#endif
-
-IDECL void EDMA_enableChannel(EDMA_Handle hEdma);
-IDECL void EDMA_disableChannel(EDMA_Handle hEdma);
-IDECL void EDMA_setChannel(EDMA_Handle hEdma);
-IDECL Uint32 EDMA_getChannel(EDMA_Handle hEdma);
-IDECL void EDMA_clearChannel(EDMA_Handle hEdma);
-#if (C64_SUPPORT)
-IDECL void EDMA_setEvtPolarity(EDMA_Handle hEdma,int polarity);
-#endif
-IDECL Uint32 EDMA_getTableAddress(EDMA_Handle hEdma);
-
-IDECL void EDMA_intEnable(Uint32 tccIntNum);
-IDECL void EDMA_intDisable(Uint32 tccIntNum);
-IDECL void EDMA_intClear(Uint32 tccIntNum);
-IDECL Uint32 EDMA_intTest(Uint32 tccIntNum);
-IDECL void EDMA_intReset(Uint32 tccIntNum);
-IDECL void EDMA_intResetAll();
-
-IDECL void EDMA_link(EDMA_Handle parent, EDMA_Handle child);
-
-IDECL void EDMA_config(EDMA_Handle hEdma, EDMA_Config *config);
-IDECL void EDMA_configArgs(EDMA_Handle hEdma, Uint32 opt, Uint32 src,
- Uint32 cnt, Uint32 dst, Uint32 idx, Uint32 rld);
-IDECL void EDMA_getConfig(EDMA_Handle hEdma, EDMA_Config *config);
-
-IDECL void EDMA_qdmaConfig(EDMA_Config *config);
-IDECL void EDMA_qdmaConfigArgs(Uint32 opt, Uint32 src, Uint32 cnt, Uint32 dst,
- Uint32 idx);
-IDECL void EDMA_qdmaGetConfig(EDMA_Config *config);
-
-IDECL void EDMA_enableChaining(EDMA_Handle hEdma);
-IDECL void EDMA_disableChaining(EDMA_Handle hEdma);
-IDECL void EDMA_chain(EDMA_Handle parent, EDMA_Handle nextChannel,int tccflag, int atccflag);
-
-/******************************************************************************\
-* inline function definitions
-\******************************************************************************/
-#ifdef USEDEFS
-/*----------------------------------------------------------------------------*/
-IDEF Uint32 EDMA_getScratchAddr() {
- return (Uint32)_EDMA_SCRATCH_START;
-}
-/*----------------------------------------------------------------------------*/
-IDEF Uint32 EDMA_getScratchSize() {
- return (Uint32)_EDMA_SCRATCH_SIZE;
-}
-/*----------------------------------------------------------------------------*/
-IDEF Uint32 EDMA_getPriQStatus() {
- return (Uint32)EDMA_RGET(PQSR);
-}
-/*----------------------------------------------------------------------------*/
-#if (C64_SUPPORT)
-IDEF void EDMA_setPriQLength(Uint32 priNum, Uint32 length) {
- if (priNum == 0x0) {
- EDMA_RSET(PQAR0,(0x00000007 & length));
- } else {
- if (priNum == 0x1) {
- EDMA_RSET(PQAR1,(0x00000007 & length));
- }else {
- if (priNum == 0x2) {
- EDMA_RSET(PQAR2,(0x00000007 & length));
- } else {
- if (priNum == 0x3) {
- EDMA_RSET(PQAR3,(0x00000007 & length));
- }
- }
- }
- }
-}
-/*----------------------------------------------------------------------------*/
-
-IDEF void EDMA_resetPriQLength(Uint32 priNum) {
- if (priNum == 0x0) {
- EDMA_FSET(PQAR0,PQA,EDMA_PQAR0_PQA_DEFAULT);
- } else {
- if (priNum == 0x1) {
- EDMA_FSET(PQAR1,PQA,EDMA_PQAR1_PQA_DEFAULT);
- } else {
- if (priNum == 0x2) {
- EDMA_FSET(PQAR2,PQA,EDMA_PQAR2_PQA_DEFAULT);
- }else {
- if (priNum == 0x3) {
- EDMA_FSET(PQAR3,PQA,EDMA_PQAR3_PQA_DEFAULT);
- }
- }
- }
- }
-}
-#endif
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_enableChannel(EDMA_Handle hEdma) {
-
- int gie;
- int chaNum = (hEdma & 0x00FF0000)>>16;
-
- gie = IRQ_globalDisable();
- #if (C64_SUPPORT)
- if (chaNum < 32) EDMA_RSET(EERL,EDMA_RGET(EERL) | (1<<chaNum));
- else EDMA_RSET(EERH,EDMA_RGET(EERH) | (1<<(chaNum-32)));
- #else
- EDMA_RSET(EER,EDMA_RGET(EER) | (1<<chaNum));
- #endif
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_enableChaining(EDMA_Handle hEdma) {
-
- int gie;
- int chaNum = (hEdma & 0x00FF0000)>>16;
-
- gie = IRQ_globalDisable();
- #if (C64_SUPPORT)
- if (chaNum < 32) EDMA_RSET(CCERL,EDMA_RGET(CCERL) | (1<<chaNum));
- else EDMA_RSET(CCERH,EDMA_RGET(CCERH) | (1<<(chaNum-32)));
- #else
-
- EDMA_RSET(CCER,EDMA_RGET(CCER) | (1<<chaNum));
- #endif
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_chain(EDMA_Handle parent, EDMA_Handle nextChannel,int tccflag, int atccflag) {
- #if (C64_SUPPORT)
- Uint32 tccm,tcc;
- #endif
- int TccNum = (nextChannel & 0x00FF0000)>>16;
- int gie;
-
- gie = IRQ_globalDisable();
-
- if (tccflag) {
- #if (C64_SUPPORT) /* SET TCCM and TCC fields */
- if (TccNum < 16) { tccm = 0 ; tcc = TccNum;}
- else {
- if ( TccNum > 15 && TccNum < 32 ) { tccm = 1 ; tcc = TccNum-16;}
- else {
- if ( TccNum > 31 && TccNum < 48 ) { tccm = 2 ; tcc = TccNum-32;}
- else { /* channel > 47 */
- tccm = 3 ; tcc = TccNum-48;
- }
- }
- }
- EDMA_FSETH(parent,OPT,TCCM,tccm);
- EDMA_FSETH(parent,OPT,TCC,tcc);
- EDMA_FSETH(parent,OPT,TCINT,1);
- #else
- EDMA_FSETH(parent,OPT,TCC,TccNum);
- EDMA_FSETH(parent,OPT,TCINT,1);
- #endif
-}
-/* ATCC */
-if (atccflag) {
- #if C64_SUPPORT
- EDMA_FSETH(parent,OPT,ATCC,TccNum);
- EDMA_FSETH(parent,OPT,ATCINT,1);
- #endif
-}
- tccAllocTable[TccNum] = 1;
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_disableChannel(EDMA_Handle hEdma) {
-
- int chaNum = (hEdma & 0x00FF0000)>>16;
- int gie;
-
- gie = IRQ_globalDisable();
-
- #if (C64_SUPPORT)
- if (chaNum < 32) EDMA_RSET(EERL,EDMA_RGET(EERL) & ~(1<<chaNum));
- else EDMA_RSET(EERH,EDMA_RGET(EERH) & ~(1<<(chaNum-32)));
- #else
- EDMA_RSET(EER,EDMA_RGET(EER) & ~(1<<chaNum));
- #endif
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_disableChaining(EDMA_Handle hEdma) {
-
- int chaNum = (hEdma & 0x00FF0000)>>16;
- int gie;
-
- gie = IRQ_globalDisable();
- #if (C64_SUPPORT)
- if (chaNum < 32) EDMA_RSET(CCERL,EDMA_RGET(CCERL) & ~(1<<chaNum));
- else EDMA_RSET(CCERH,EDMA_RGET(CCERH) & ~(1<<(chaNum-32)));
- #else
- EDMA_RSET(CCER,EDMA_RGET(CCER) & ~(1<<chaNum));
- #endif
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_setChannel(EDMA_Handle hEdma) {
-
- int chaNum = (hEdma & 0x00FF0000)>>16;
-
- #if (C64_SUPPORT)
- if (chaNum < 32) EDMA_RSET(ESRL,1<<chaNum);
- else EDMA_RSET(ESRH,1<<(chaNum-32));
- #else
- EDMA_RSET(ESR,1<<chaNum);
- #endif
-}
-/*----------------------------------------------------------------------------*/
-IDEF Uint32 EDMA_getChannel(EDMA_Handle hEdma) {
-
- int chaNum = (hEdma & 0x00FF0000)>>16;
-
- #if (C64_SUPPORT)
- if (chaNum < 32) return (Uint32)(((EDMA_RGET(ERL) >> chaNum) & 1)==1);
- else return (Uint32)(((EDMA_RGET(ERH) >> (chaNum-32)) & 1)==1);
-
- #else
- return (Uint32)(((EDMA_RGET(ER) >>chaNum) & 1)==1);
- #endif
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_clearChannel(EDMA_Handle hEdma) {
-
- int chaNum = (hEdma & 0x00FF0000)>>16;
-
- #if (C64_SUPPORT)
- if (chaNum < 32) EDMA_RSET(ECRL,1<<chaNum);
- else EDMA_RSET(ECRH,1<<(chaNum-32));
- #else
- EDMA_RSET(ECR,1<<chaNum);
- #endif
-}
-/*----------------------------------------------------------------------------*/
-#if (C64_SUPPORT)
-IDEF void EDMA_setEvtPolarity(EDMA_Handle hEdma,int polarity) {
-
- int chaNum = (hEdma & 0x00FF0000)>>16;
-
- #if (C64_SUPPORT)
- if (chaNum < 32) EDMA_RSET(EPRL,(polarity<<chaNum) | EDMA_RGET(EPRL));
- else EDMA_RSET(EPRH,(polarity<<(chaNum-32)) | EDMA_RGET(EPRH));
- #endif
-}
-#endif
-/*----------------------------------------------------------------------------*/
-IDEF Uint32 EDMA_getTableAddress(EDMA_Handle hEdma) {
-
- return (hEdma&0x0000FFFF)+_EDMA_PRAM_START;
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_intEnable(Uint32 tccIntNum) {
- int gie;
-
- gie = IRQ_globalDisable();
-
- #if (C64_SUPPORT)
- if (tccIntNum < 32) EDMA_RSET(CIERL,EDMA_RGET(CIERL) | (1<<tccIntNum));
- else EDMA_RSET(CIERH,EDMA_RGET(CIERH) | (1<<(tccIntNum-32)));
- #else
- EDMA_RSET(CIER,EDMA_RGET(CIER) | (1<<tccIntNum));
- #endif
-
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_intDisable(Uint32 tccIntNum) {
- int gie;
-
- gie = IRQ_globalDisable();
-
- #if (C64_SUPPORT)
- if (tccIntNum < 32) EDMA_RSET(CIERL,EDMA_RGET(CIERL) & ~(1<<tccIntNum));
- else EDMA_RSET(CIERH,EDMA_RGET(CIERH) & ~(1<<(tccIntNum-32)));
- #else
- EDMA_RSET(CIER,EDMA_RGET(CIER) & ~(1<<tccIntNum));
- #endif
-
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_intClear(Uint32 tccIntNum) {
-
- #if (C64_SUPPORT)
- if (tccIntNum < 32) EDMA_RSET(CIPRL,1<<tccIntNum);
- else EDMA_RSET(CIPRH,1<<(tccIntNum-32));
- #else
- EDMA_RSET(CIPR,1<<tccIntNum);
- #endif
-}
-/*----------------------------------------------------------------------------*/
-IDEF Uint32 EDMA_intTest(Uint32 tccIntNum) {
-
- #if (C64_SUPPORT)
- if (tccIntNum < 32) return ((EDMA_RGET(CIPRL) & (1<<tccIntNum)) ? 1 : 0);
- else return ((EDMA_RGET(CIPRH) & (1<<(tccIntNum-32))) ? 1 : 0);
- #else
- return ((EDMA_RGET(CIPR) & (1<<tccIntNum)) ? 1 : 0);
- #endif
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_intReset(Uint32 tccIntNum) {
- int gie;
-
- gie = IRQ_globalDisable();
-
- /* disable then clear interrupt */
- #if (C64_SUPPORT)
- if (tccIntNum < 32) {
- EDMA_RSET(CIERL,EDMA_RGET(CIERL) & ~(1<<tccIntNum));
- EDMA_RSET(CIPRL,1<<tccIntNum);
- } else {
- EDMA_RSET(CIERH,EDMA_RGET(CIERH) & ~(1<<(tccIntNum-32)));
- EDMA_RSET(CIPRH,1<<(tccIntNum-32));
- }
- #else
- EDMA_RSET(CIER,EDMA_RGET(CIER) & ~(1<<tccIntNum));
- EDMA_RSET(CIPR,1<<tccIntNum);
- #endif
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_intResetAll() {
-
- int gie = IRQ_globalDisable();
- /* disable then clear all interrupts */
-
- #if (C64_SUPPORT)
- EDMA_RSET(CIERL, 0x00000000);
- EDMA_RSET(CIERH, 0x00000000);
- EDMA_RSET(CIPRL, 0xFFFFFFFF);
- EDMA_RSET(CIPRH, 0xFFFFFFFF);
- #else
- EDMA_RSET(CIER, 0x00000000);
- EDMA_RSET(CIPR, 0xFFFFFFFF);
- #endif
-
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_link(EDMA_Handle parent, EDMA_Handle child) {
- EDMA_FSETH(parent,RLD,LINK,child);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_config(EDMA_Handle hEdma, EDMA_Config *config) {
-
- Uint32 gie;
- volatile Uint32 *base;
- register Uint32 x0,x1,x2,x3,x4,x5;
-
-/* Test if QDMA handle was passed with CCS 1.2 */
- if ( hEdma == (0x20000000) || hEdma == (0x10000000)) {
- EDMA_qdmaConfig(config);
- }else{
-
- gie = IRQ_globalDisable();
-
- x0 = config->opt;
- x1 = config->src;
- x2 = config->cnt;
- x3 = config->dst;
- x4 = config->idx;
- x5 = config->rld;
-
- base = (volatile Uint32 *)((hEdma&0x0000FFFF)+_EDMA_PRAM_START);
- base[_EDMA_OPT_OFFSET] = 0x00000000;
- base[_EDMA_SRC_OFFSET] = x1;
- base[_EDMA_CNT_OFFSET] = x2;
- base[_EDMA_DST_OFFSET] = x3;
- base[_EDMA_IDX_OFFSET] = x4;
- base[_EDMA_RLD_OFFSET] = x5;
- base[_EDMA_OPT_OFFSET] = x0;
- IRQ_globalRestore(gie);
- }
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_configArgs(EDMA_Handle hEdma, Uint32 opt, Uint32 src,
- Uint32 cnt, Uint32 dst, Uint32 idx, Uint32 rld) {
-
- Uint32 gie;
- volatile Uint32 *base;
- /* Test if QDMA handle was passed with CCS 1.2 */
- if ( hEdma == (0x20000000) || hEdma == (0x10000000)) {
- EDMA_qdmaConfigArgs(opt, src, cnt, dst, idx);
- }else{
- gie = IRQ_globalDisable();
- base = (volatile Uint32*)((hEdma&0x0000FFFF)+_EDMA_PRAM_START);
- base[_EDMA_OPT_OFFSET] = 0x00000000;
- base[_EDMA_SRC_OFFSET] = src;
- base[_EDMA_CNT_OFFSET] = cnt;
- base[_EDMA_DST_OFFSET] = dst;
- base[_EDMA_IDX_OFFSET] = idx;
- base[_EDMA_RLD_OFFSET] = rld;
- base[_EDMA_OPT_OFFSET] = opt;
- IRQ_globalRestore(gie);
- }
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_getConfig(EDMA_Handle hEdma, EDMA_Config *config) {
-
- Uint32 gie;
- volatile Uint32 *base;
- register Uint32 x0,x1,x2,x3,x4,x5;
-
- gie = IRQ_globalDisable();
-
- base = (volatile Uint32 *)((hEdma&0x0000FFFF)+_EDMA_PRAM_START);
- x0 = base[_EDMA_OPT_OFFSET];
- x1 = base[_EDMA_SRC_OFFSET];
- x2 = base[_EDMA_CNT_OFFSET];
- x3 = base[_EDMA_DST_OFFSET];
- x4 = base[_EDMA_IDX_OFFSET];
- x5 = base[_EDMA_RLD_OFFSET];
-
- config->opt = x0;
- config->src = x1;
- config->cnt = x2;
- config->dst = x3;
- config->idx = x4;
- config->rld = x5;
-
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_qdmaConfig(EDMA_Config *config) {
-
- Uint32 gie;
- volatile Uint32 *base;
- register Uint32 x0,x1,x2,x3,x4;
-
- gie = IRQ_globalDisable();
-
- x0 = config->opt;
- x1 = config->src;
- x2 = config->cnt;
- x3 = config->dst;
- x4 = config->idx;
-
- base = (volatile Uint32 *)(_EDMA_QOPT_ADDR);
- base[_EDMA_QSRC_OFFSET] = x1;
- base[_EDMA_QCNT_OFFSET] = x2;
- base[_EDMA_QDST_OFFSET] = x3;
- base[_EDMA_QIDX_OFFSET] = x4;
- base[_EDMA_QSOPT_OFFSET] = x0;
-
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_qdmaConfigArgs(Uint32 opt, Uint32 src, Uint32 cnt, Uint32 dst,
- Uint32 idx) {
-
- Uint32 gie;
- volatile Uint32 *base;
-
- gie = IRQ_globalDisable();
-
- base = (volatile Uint32*)(_EDMA_QOPT_ADDR);
- base[_EDMA_QSRC_OFFSET] = src;
- base[_EDMA_QCNT_OFFSET] = cnt;
- base[_EDMA_QDST_OFFSET] = dst;
- base[_EDMA_QIDX_OFFSET] = idx;
- base[_EDMA_QSOPT_OFFSET] = opt;
-
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-IDEF void EDMA_qdmaGetConfig(EDMA_Config *config) {
-
- Uint32 gie;
- volatile Uint32 *base;
- volatile EDMA_Config* cfg = (volatile EDMA_Config*)config;
- register Uint32 x0,x1,x2,x3,x4;
-
- gie = IRQ_globalDisable();
-
- base = (volatile Uint32 *)(_EDMA_QOPT_ADDR);
- x0 = base[_EDMA_QOPT_OFFSET];
- x1 = base[_EDMA_QSRC_OFFSET];
- x2 = base[_EDMA_QCNT_OFFSET];
- x3 = base[_EDMA_QDST_OFFSET];
- x4 = base[_EDMA_QIDX_OFFSET];
-
- cfg->opt = x0;
- cfg->src = x1;
- cfg->cnt = x2;
- cfg->dst = x3;
- cfg->idx = x4;
- cfg->rld = 0x00000000;
-
- IRQ_globalRestore(gie);
-}
-/*----------------------------------------------------------------------------*/
-#endif /* USEDEFS */
-
-
-#endif /* EDMA_SUPPORT */
-#endif /* _CSL_EDMA_H_ */
-/******************************************************************************\
-* End of csl_edma.h
-\******************************************************************************/
-
diff --git a/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_edmahal.h b/examples/CSL2_DAT_DEMO/csl2_legacy_include/csl_edmahal.h
+++ /dev/null
@@ -1,2226 +0,0 @@
-/*****************************************************************************\
-* Copyright (C) 1999-2000 Texas Instruments Incorporated.
-* All Rights Reserved
-*------------------------------------------------------------------------------
-* FILENAME...... csl_edmahal.h
-* DATE CREATED.. 12 Jun 1999
-* LAST MODIFIED. 02 Aug 2004 Adding support for C6418
-* 17 Jun 2003 6712C
-* 28 May 2003 6711C
-* 22 Feb 2002 DM642
-*------------------------------------------------------------------------------
-* REGISTERS/PARAMETERS
-*
-* OPT - options parameter
-* SRC - source address parameter
-* CNT - transfer count parameter
-* DST - destination address parameter
-* IDX - index parameter
-* RLD - count reload + link parameter
-* QOPT - QDMA options register
-* QSRC - QDMA source address register
-* QCNT - QDMA transfer count register
-* QDST - QDMA destination address register
-* QIDX - QDMA index register
-* QSOPT - QDMA options pseudo register
-* QSSRC - QDMA source address pseudo register
-* QSCNT - QDMA transfer count pseudo register
-* QSDST - QDMA destination address pseudo register
-* QSIDX - QDMA index pseudo register
-* PQSR - priority queue status register
-* PQAR0 - priority queue allocation register 0
-* PQAR1 - priority queue allocation register 1
-* PQAR2 - priority queue allocation register 2
-* PQAR3 - priority queue allocation register 3
-* CIPR - channel interrupt pending register
-* CIPRL - channel interrupt pending register, low half (1)
-* CIPRH - channel interrupt pending register, high half (1)
-* CIER - channel interrupt enable register
-* CIERL - channel interrupt enable register, low half (1)
-* CIERH - channel interrupt enable register, high half (1)
-* CCER - channel chain enable register
-* CCERL - channel chain enable register, low half (1)
-* CCERH - channel chain enable register, high half (1)
-* ER - event register
-* ERL - event register, low half (1)
-* ERH - event register, high half (1)
-* EER - event enable register
-* EERL - event enable register, low half (1)
-* EERH - event enable register, high half (1)
-* EPRL - event polarity register, low half (1)
-* EPRH - event polarity register, high half (1)
-* ECR - event clear register
-* ECRL - event clear register, low half (1)
-* ECRH - event clear register, high half (1)
-* ESR - event set register
-* ESRL - event set register, low half (1)
-* ESRH - event set register, high half (1)
-*
-*
-* CHIP_6713, CHIP_DA610, CHIP_6711C and CHIP_6712C
-* ESEL0 - event selection register 0 (2)
-* ESEL1 - event selection register 1 (2)
-* ESEL2 - event selection register 2 (2) (3)
-* ESEL3 - event selection register 3 (2)
-*
-* (1) - only supported on C64x devices
-* (2) - only supported on C6713, DA610, 6711C and 6712C
-* (3) - the whole register is reserved
-\******************************************************************************/
-#ifndef _CSL_EDMAHAL_H
-#define _CSL_EDMAHAL_H_
-
-#include <csl_stdinc.h>
-#include <csl_chip.h>
-
-#if (EDMA_SUPPORT)
-/******************************************************************************\
-* MISC section
-\******************************************************************************/
-
-#if (CHIP_6414 | CHIP_6415 | CHIP_6416 | CHIP_6411 )
- #define _EDMA_CHA_CNT 64
- #define _EDMA_BASE_PRAM 0x01A00000u
- #define _EDMA_PRAM_START _EDMA_BASE_PRAM
- #define _EDMA_PRAM_SIZE 0x00000800u
- #define _EDMA_PRAM_ERASE 0x00000600u
-#endif
-
-#if (CHIP_DM642 | CHIP_DM641 | CHIP_DM640 | CHIP_6412 | CHIP_6410 | CHIP_6413 | CHIP_6418)
- #define _EDMA_CHA_CNT 64
- #define _EDMA_BASE_PRAM 0x01A00000u
- #define _EDMA_PRAM_START _EDMA_BASE_PRAM
- #define _EDMA_PRAM_SIZE 0x00001400u
- #define _EDMA_PRAM_ERASE 0x00000600u
-#endif
-
-#if (CHIP_6211 | CHIP_6711 | CHIP_6712 | CHIP_6713 | CHIP_DA610 | CHIP_6711C | CHIP_6712C)
- #define _EDMA_CHA_CNT 16
- #define _EDMA_BASE_PRAM 0x01A00000u
- #define _EDMA_PRAM_START _EDMA_BASE_PRAM
- #define _EDMA_PRAM_SIZE 0x00000800u
- #define _EDMA_PRAM_ERASE 0x00000180u
-#endif
-
- #define _EDMA_ENTRY_SIZE 0x00000018u
- #define _EDMA_NULL_PARAM (_EDMA_PRAM_START+_EDMA_ENTRY_SIZE*_EDMA_CHA_CNT)
- #define _EDMA_RSVD_PARAM (_EDMA_NULL_PARAM+_EDMA_ENTRY_SIZE)
- #define _EDMA_LINK_START (_EDMA_RSVD_PARAM+_EDMA_ENTRY_SIZE)
- #define _EDMA_LINK_CNT ((_EDMA_PRAM_SIZE/_EDMA_ENTRY_SIZE)-(_EDMA_CHA_CNT+2))
- #define _EDMA_SCRATCH_START (_EDMA_LINK_START+_EDMA_LINK_CNT*_EDMA_ENTRY_SIZE)
- #define _EDMA_SCRATCH_SIZE (_EDMA_PRAM_START+_EDMA_PRAM_SIZE-_EDMA_SCRATCH_START)
-
-/******************************************************************************\
-* module level register/field access macros
-\******************************************************************************/
-
- /* ----------------- */
- /* FIELD MAKE MACROS */
- /* ----------------- */
-
- #define EDMA_FMK(REG,FIELD,x)\
- _PER_FMK(EDMA,##REG,##FIELD,x)
-
- #define EDMA_FMKS(REG,FIELD,SYM)\
- _PER_FMKS(EDMA,##REG,##FIELD,##SYM)
-
-
- /* -------------------------------- */
- /* RAW REGISTER/FIELD ACCESS MACROS */
- /* -------------------------------- */
-
- #define EDMA_REG(REG) (*(volatile Uint32*)(_EDMA_##REG##_ADDR))
-
- #define EDMA_ADDR(REG)\
- _EDMA_##REG##_ADDR
-
- #define EDMA_RGET(REG)\
- _PER_RGET(_EDMA_##REG##_ADDR,EDMA,##REG)
-
- #define EDMA_RSET(REG,x)\
- _PER_RSET(_EDMA_##REG##_ADDR,EDMA,##REG,x)
-
- #define EDMA_FGET(REG,FIELD)\
- _EDMA_##REG##_FGET(##FIELD)
-
- #define EDMA_FSET(REG,FIELD,x)\
- _EDMA_##REG##_FSET(##FIELD,##x)
-
- #define EDMA_FSETS(REG,FIELD,SYM)\
- _EDMA_##REG##_FSETS(##FIELD,##SYM)
-
-
- /* ------------------------------------------ */
- /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */
- /* ------------------------------------------ */
-
- #define EDMA_RGETA(addr,REG)\
- _PER_RGET(addr,EDMA,##REG)
-
- #define EDMA_RSETA(addr,REG,x)\
- _PER_RSET(addr,EDMA,##REG,x)
-
- #define EDMA_FGETA(addr,REG,FIELD)\
- _PER_FGET(addr,EDMA,##REG,##FIELD)
-
- #define EDMA_FSETA(addr,REG,FIELD,x)\
- _PER_FSET(addr,EDMA,##REG,##FIELD,x)
-
- #define EDMA_FSETSA(addr,REG,FIELD,SYM)\
- _PER_FSETS(addr,EDMA,##REG,##FIELD,##SYM)
-
-
- /* ----------------------------------------- */
- /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */
- /* ----------------------------------------- */
-
- #define EDMA_ADDRH(h,REG)\
- ((((Uint32)(h))&0x0000FFFF)+_EDMA_PRAM_START+(_EDMA_##REG##_OFFSET<<2))
-
- #define EDMA_RGETH(h,REG)\
- EDMA_RGETA(EDMA_ADDRH(h,##REG),##REG)
-
-
- #define EDMA_RSETH(h,REG,x)\
- EDMA_RSETA(EDMA_ADDRH(h,##REG),##REG,x)
-
-
- #define EDMA_FGETH(h,REG,FIELD)\
- EDMA_FGETA(EDMA_ADDRH(h,##REG),##REG,##FIELD)
-
-
- #define EDMA_FSETH(h,REG,FIELD,x)\
- EDMA_FSETA(EDMA_ADDRH(h,##REG),##REG,##FIELD,x)
-
-
- #define EDMA_FSETSH(h,REG,FIELD,SYM)\
- EDMA_FSETSA(EDMA_ADDRH(h,##REG),##REG,##FIELD,##SYM)
-
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | O P T |
-* | Q O P T |
-* | Q S O P T |
-* |___________________|
-*
-* OPT - options parameter
-* QOPT - QDMA options register
-* QSOPT - QDMA options pseudo register
-*
-* FIELDS (msb -> lsb)
-* (rw) PRI
-* (rw) ESIZE
-* (rw) 2DS
-* (rw) SUM
-* (rw) 2DD
-* (rw) DUM
-* (rw) TCINT
-* (rw) TCC
-* (rw) TCCM (1)
-* (rw) ATCINT (1)
-* (rw) ATCC (1)
-* (rw) PDTS (1)
-* (rw) PDTD (1)
-* (rw) LINK
-* (rw) FS
-*
-* (1) - only supported on C64x devices
-*
-\******************************************************************************/
- #define _EDMA_OPT_OFFSET 0
- #define _EDMA_QOPT_OFFSET 0
- #define _EDMA_QSOPT_OFFSET 8
-
- #define _EDMA_QOPT_ADDR 0x02000000u
- #define _EDMA_QSOPT_ADDR 0x02000020u
-
- #define EDMA_QOPT EDMA_REG(QOPT)
- #define EDMA_QSOPT EDMA_REG(QSOPT)
-
- #define _EDMA_OPT_PRI_MASK 0xE0000000u
- #define _EDMA_OPT_PRI_SHIFT 0x0000001Du
- #define EDMA_OPT_PRI_DEFAULT 0x00000000u
- #define EDMA_OPT_PRI_OF(x) _VALUEOF(x)
- #if (C64_SUPPORT)
- #define EDMA_OPT_PRI_URGENT 0x00000000u
- #define EDMA_OPT_PRI_HIGH 0x00000001u
- #define EDMA_OPT_PRI_MEDIUM 0x00000002u
- #define EDMA_OPT_PRI_LOW 0x00000003u
- #else
- #define EDMA_OPT_PRI_HIGH 0x00000001u
- #define EDMA_OPT_PRI_LOW 0x00000002u
- #endif
-
- #define _EDMA_OPT_ESIZE_MASK 0x18000000u
- #define _EDMA_OPT_ESIZE_SHIFT 0x0000001Bu
- #define EDMA_OPT_ESIZE_DEFAULT 0x00000000u
- #define EDMA_OPT_ESIZE_OF(x) _VALUEOF(x)
- #define EDMA_OPT_ESIZE_32BIT 0x00000000u
- #define EDMA_OPT_ESIZE_16BIT 0x00000001u
- #define EDMA_OPT_ESIZE_8BIT 0x00000002u
-
- #define _EDMA_OPT_2DS_MASK 0x04000000u
- #define _EDMA_OPT_2DS_SHIFT 0x0000001Au
- #define EDMA_OPT_2DS_DEFAULT 0x00000000u
- #define EDMA_OPT_2DS_OF(x) _VALUEOF(x)
- #define EDMA_OPT_2DS_NO 0x00000000u
- #define EDMA_OPT_2DS_YES 0x00000001u
-
- #define _EDMA_OPT_SUM_MASK 0x03000000u
- #define _EDMA_OPT_SUM_SHIFT 0x00000018u
- #define EDMA_OPT_SUM_DEFAULT 0x00000000u
- #define EDMA_OPT_SUM_OF(x) _VALUEOF(x)
- #define EDMA_OPT_SUM_NONE 0x00000000u
- #define EDMA_OPT_SUM_INC 0x00000001u
- #define EDMA_OPT_SUM_DEC 0x00000002u
- #define EDMA_OPT_SUM_IDX 0x00000003u
-
- #define _EDMA_OPT_2DD_MASK 0x00800000u
- #define _EDMA_OPT_2DD_SHIFT 0x00000017u
- #define EDMA_OPT_2DD_DEFAULT 0x00000000u
- #define EDMA_OPT_2DD_OF(x) _VALUEOF(x)
- #define EDMA_OPT_2DD_NO 0x00000000u
- #define EDMA_OPT_2DD_YES 0x00000001u
-
- #define _EDMA_OPT_DUM_MASK 0x00600000u
- #define _EDMA_OPT_DUM_SHIFT 0x00000015u
- #define EDMA_OPT_DUM_DEFAULT 0x00000000u
- #define EDMA_OPT_DUM_OF(x) _VALUEOF(x)
- #define EDMA_OPT_DUM_NONE 0x00000000u
- #define EDMA_OPT_DUM_INC 0x00000001u
- #define EDMA_OPT_DUM_DEC 0x00000002u
- #define EDMA_OPT_DUM_IDX 0x00000003u
-
- #define _EDMA_OPT_TCINT_MASK 0x00100000u
- #define _EDMA_OPT_TCINT_SHIFT 0x00000014u
- #define EDMA_OPT_TCINT_DEFAULT 0x00000000u
- #define EDMA_OPT_TCINT_OF(x) _VALUEOF(x)
- #define EDMA_OPT_TCINT_NO 0x00000000u
- #define EDMA_OPT_TCINT_YES 0x00000001u
-
- #define _EDMA_OPT_TCC_MASK 0x000F0000u
- #define _EDMA_OPT_TCC_SHIFT 0x00000010u
- #define EDMA_OPT_TCC_DEFAULT 0x00000000u
- #define EDMA_OPT_TCC_OF(x) _VALUEOF(x)
-
-#if (C64_SUPPORT)
- #define _EDMA_OPT_TCCM_MASK 0x00006000u
- #define _EDMA_OPT_TCCM_SHIFT 0x0000000Du
- #define EDMA_OPT_TCCM_DEFAULT 0x00000000u
- #define EDMA_OPT_TCCM_OF(x) _VALUEOF(x)
-
- #define _EDMA_OPT_ATCINT_MASK 0x00001000u
- #define _EDMA_OPT_ATCINT_SHIFT 0x0000000Cu
- #define EDMA_OPT_ATCINT_DEFAULT 0x00000000u
- #define EDMA_OPT_ATCINT_OF(x) _VALUEOF(x)
- #define EDMA_OPT_ATCINT_NO 0x00000000u
- #define EDMA_OPT_ATCINT_YES 0x00000001u
-
- #define _EDMA_OPT_ATCC_MASK 0x000007E0u
- #define _EDMA_OPT_ATCC_SHIFT 0x00000005u
- #define EDMA_OPT_ATCC_DEFAULT 0x00000000u
- #define EDMA_OPT_ATCC_OF(x) _VALUEOF(x)
-
- #define _EDMA_OPT_PDTS_MASK 0x00000008u
- #define _EDMA_OPT_PDTS_SHIFT 0x00000003u
- #define EDMA_OPT_PDTS_DEFAULT 0x00000000u
- #define EDMA_OPT_PDTS_OF(x) _VALUEOF(x)
- #define EDMA_OPT_PDTS_DISABLE 0x00000000u
- #define EDMA_OPT_PDTS_ENABLE 0x00000001u
-
- #define _EDMA_OPT_PDTD_MASK 0x00000004u
- #define _EDMA_OPT_PDTD_SHIFT 0x00000002u
- #define EDMA_OPT_PDTD_DEFAULT 0x00000000u
- #define EDMA_OPT_PDTD_OF(x) _VALUEOF(x)
- #define EDMA_OPT_PDTD_DISABLE 0x00000000u
- #define EDMA_OPT_PDTD_ENABLE 0x00000001u
-#endif
-
- #define _EDMA_OPT_LINK_MASK 0x00000002u
- #define _EDMA_OPT_LINK_SHIFT 0x00000001u
- #define EDMA_OPT_LINK_DEFAULT 0x00000000u
- #define EDMA_OPT_LINK_OF(x) _VALUEOF(x)
- #define EDMA_OPT_LINK_NA 0x00000000u
- #define EDMA_OPT_LINK_NO 0x00000000u
- #define EDMA_OPT_LINK_YES 0x00000001u
-
- #define _EDMA_OPT_FS_MASK 0x00000001u
- #define _EDMA_OPT_FS_SHIFT 0x00000000u
- #define EDMA_OPT_FS_DEFAULT 0x00000000u
- #define EDMA_OPT_FS_OF(x) _VALUEOF(x)
- #define EDMA_OPT_FS_NO 0x00000000u
- #define EDMA_OPT_FS_YES 0x00000001u
-
- #define EDMA_OPT_OF(x) _VALUEOF(x)
-
-#if (C64_SUPPORT)
- #define EDMA_OPT_DEFAULT (Uint32)(\
- _PER_FDEFAULT(EDMA,OPT,PRI)\
- |_PER_FDEFAULT(EDMA,OPT,ESIZE)\
- |_PER_FDEFAULT(EDMA,OPT,2DS)\
- |_PER_FDEFAULT(EDMA,OPT,SUM)\
- |_PER_FDEFAULT(EDMA,OPT,2DD)\
- |_PER_FDEFAULT(EDMA,OPT,DUM)\
- |_PER_FDEFAULT(EDMA,OPT,TCINT)\
- |_PER_FDEFAULT(EDMA,OPT,TCC)\
- |_PER_FDEFAULT(EDMA,OPT,TCCM)\
- |_PER_FDEFAULT(EDMA,OPT,ATCINT) \
- |_PER_FDEFAULT(EDMA,OPT,ATCC) \
- |_PER_FDEFAULT(EDMA,OPT,PDTS) \
- |_PER_FDEFAULT(EDMA,OPT,PDTD) \
- |_PER_FDEFAULT(EDMA,OPT,LINK)\
- |_PER_FDEFAULT(EDMA,OPT,FS)\
- )
-
- #define EDMA_OPT_RMK(pri,esize,ds2,sum,dd2,dum,tcint,tcc,tccm,atcint,atcc,\
- pdts,pdtd,link,fs) (Uint32)(\
- _PER_FMK(EDMA,OPT,PRI,pri) \
- |_PER_FMK(EDMA,OPT,ESIZE,esize) \
- |_PER_FMK(EDMA,OPT,2DS,ds2) \
- |_PER_FMK(EDMA,OPT,SUM,sum) \
- |_PER_FMK(EDMA,OPT,2DD,dd2) \
- |_PER_FMK(EDMA,OPT,DUM,dum) \
- |_PER_FMK(EDMA,OPT,TCINT,tcint) \
- |_PER_FMK(EDMA,OPT,TCC,tcc) \
- |_PER_FMK(EDMA,OPT,TCCM,tccm) \
- |_PER_FMK(EDMA,OPT,ATCINT,atcint) \
- |_PER_FMK(EDMA,OPT,ATCC,atcc) \
- |_PER_FMK(EDMA,OPT,PDTS,pdts) \
- |_PER_FMK(EDMA,OPT,PDTD,pdtd) \
- |_PER_FMK(EDMA,OPT,LINK,link) \
- |_PER_FMK(EDMA,OPT,FS,fs) \
- )
-#endif
-
-#if (!C64_SUPPORT)
- #define EDMA_OPT_DEFAULT (Uint32)(\
- _PER_FDEFAULT(EDMA,OPT,PRI)\
- |_PER_FDEFAULT(EDMA,OPT,ESIZE)\
- |_PER_FDEFAULT(EDMA,OPT,2DS)\
- |_PER_FDEFAULT(EDMA,OPT,SUM)\
- |_PER_FDEFAULT(EDMA,OPT,2DD)\
- |_PER_FDEFAULT(EDMA,OPT,DUM)\
- |_PER_FDEFAULT(EDMA,OPT,TCINT)\
- |_PER_FDEFAULT(EDMA,OPT,TCC)\
- |_PER_FDEFAULT(EDMA,OPT,LINK)\
- |_PER_FDEFAULT(EDMA,OPT,FS)\
- )
-
- #define EDMA_OPT_RMK(pri,esize,ds2,sum,dd2,dum,tcint,tcc,link,fs) (Uint32)(\
- _PER_FMK(EDMA,OPT,PRI,pri) \
- |_PER_FMK(EDMA,OPT,ESIZE,esize) \
- |_PER_FMK(EDMA,OPT,2DS,ds2) \
- |_PER_FMK(EDMA,OPT,SUM,sum) \
- |_PER_FMK(EDMA,OPT,2DD,dd2) \
- |_PER_FMK(EDMA,OPT,DUM,dum) \
- |_PER_FMK(EDMA,OPT,TCINT,tcint) \
- |_PER_FMK(EDMA,OPT,TCC,tcc) \
- |_PER_FMK(EDMA,OPT,LINK,link) \
- |_PER_FMK(EDMA,OPT,FS,fs) \
- )
-#endif
-
- #define _EDMA_QOPT_FGET(FIELD)\
- _PER_FGET(_EDMA_QOPT_ADDR,EDMA,OPT,##FIELD)
-
- #define _EDMA_QOPT_FSET(FIELD,field)\
- _PER_FSET(_EDMA_QOPT_ADDR,EDMA,OPT,##FIELD,field)
-
- #define _EDMA_QOPT_FSETS(FIELD,SYM)\
- _PER_FSETS(_EDMA_QOPT_ADDR,EDMA,OPT,##FIELD,##SYM)
-
- #define _EDMA_QSOPT_FGET(FIELD)\
- _PER_FGET(_EDMA_QSOPT_ADDR,EDMA,OPT,##FIELD)
-
- #define _EDMA_QSOPT_FSET(FIELD,field)\
- _PER_FSET(_EDMA_QSOPT_ADDR,EDMA,OPT,##FIELD,field)
-
- #define _EDMA_QSOPT_FSETS(FIELD,SYM)\
- _PER_FSETS(_EDMA_QSOPT_ADDR,EDMA,OPT,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | S R C |
-* | Q S R C |
-* | Q S S R C |
-* |___________________|
-*
-* SRC - source address parameter
-* QSRC - QDMA source address register
-* QSSRC - QDMA source address pseudo register
-*
-* FIELDS (msb -> lsb)
-* (rw) SRC
-*
-\******************************************************************************/
- #define _EDMA_SRC_OFFSET 1
- #define _EDMA_QSRC_OFFSET 1
- #define _EDMA_QSSRC_OFFSET 9
-
- #define _EDMA_QSRC_ADDR 0x02000004u
- #define _EDMA_QSSRC_ADDR 0x02000024u
-
- #define EDMA_QSRC EDMA_REG(QSRC)
- #define EDMA_QSSRC EDMA_REG(QSSRC)
-
- #define _EDMA_SRC_SRC_MASK 0xFFFFFFFFu
- #define _EDMA_SRC_SRC_SHIFT 0x00000000u
- #define EDMA_SRC_SRC_DEFAULT 0x00000000u
- #define EDMA_SRC_SRC_OF(x) _VALUEOF(x)
-
- #define EDMA_SRC_OF(x) _VALUEOF(x)
-
- #define EDMA_SRC_DEFAULT (Uint32)(\
- _PER_FDEFAULT(EDMA,SRC,SRC)\
- )
-
- #define EDMA_SRC_RMK(src) (Uint32)(\
- _PER_FMK(EDMA,SRC,SRC,src) \
- )
-
- #define _EDMA_QSRC_FGET(FIELD)\
- _PER_FGET(_EDMA_QSRC_ADDR,EDMA,SRC,##FIELD)
-
- #define _EDMA_QSRC_FSET(FIELD,field)\
- _PER_FSET(_EDMA_QSRC_ADDR,EDMA,SRC,##FIELD,field)
-
- #define _EDMA_QSRC_FSETS(FIELD,SYM)\
- _PER_FSETS(_EDMA_QSRC_ADDR,EDMA,SRC,##FIELD,##SYM)
-
- #define _EDMA_QSSRC_FGET(FIELD)\
- _PER_FGET(_EDMA_QSSRC_ADDR,EDMA,SRC,##FIELD)
-
- #define _EDMA_QSSRC_FSET(FIELD,field)\
- _PER_FSET(_EDMA_QSSRC_ADDR,EDMA,SRC,##FIELD,field)
-
- #define _EDMA_QSSRC_FSETS(FIELD,SYM)\
- _PER_FSETS(_EDMA_QSSRC_ADDR,EDMA,SRC,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | C N T |
-* | Q C N T |
-* | Q S C N T |
-* |___________________|
-*
-* CNT - transfer count parameter
-* QCNT - QDMA transfer count register
-* QSCNT - QDMA transfer count pseudo register
-*
-* FIELDS (msb -> lsb)
-* (rw) FRMCNT
-* (rw) ELECNT
-*
-\******************************************************************************/
- #define _EDMA_CNT_OFFSET 2
- #define _EDMA_QCNT_OFFSET 2
- #define _EDMA_QSCNT_OFFSET 10
-
- #define _EDMA_QCNT_ADDR 0x02000008u
- #define _EDMA_QSCNT_ADDR 0x02000028u
-
- #define EDMA_QCNT EDMA_REG(QCNT)
- #define EDMA_QSCNT EDMA_REG(QSCNT)
-
- #define _EDMA_CNT_FRMCNT_MASK 0xFFFF0000u
- #define _EDMA_CNT_FRMCNT_SHIFT 0x00000010u
- #define EDMA_CNT_FRMCNT_DEFAULT 0x00000000u
- #define EDMA_CNT_FRMCNT_OF(x) _VALUEOF(x)
-
- #define _EDMA_CNT_ELECNT_MASK 0x0000FFFFu
- #define _EDMA_CNT_ELECNT_SHIFT 0x00000000u
- #define EDMA_CNT_ELECNT_DEFAULT 0x00000000u
- #define EDMA_CNT_ELECNT_OF(x) _VALUEOF(x)
-
- #define EDMA_CNT_OF(x) _VALUEOF(x)
-
- #define EDMA_CNT_DEFAULT (Uint32)(\
- _PER_FDEFAULT(EDMA,CNT,FRMCNT)\
- |_PER_FDEFAULT(EDMA,CNT,ELECNT)\
- )
-
- #define EDMA_CNT_RMK(frmcnt,elecnt) (Uint32)(\
- _PER_FMK(EDMA,CNT,FRMCNT,frmcnt) \
- |_PER_FMK(EDMA,CNT,ELECNT,elecnt) \
- )
-
- #define _EDMA_QCNT_FGET(FIELD)\
- _PER_FGET(_EDMA_QCNT_ADDR,EDMA,CNT,##FIELD)
-
- #define _EDMA_QCNT_FSET(FIELD,field)\
- _PER_FSET(_EDMA_QCNT_ADDR,EDMA,CNT,##FIELD,field)
-
- #define _EDMA_QCNT_FSETS(FIELD,SYM)\
- _PER_FSETS(_EDMA_QCNT_ADDR,EDMA,CNT,##FIELD,##SYM)
-
- #define _EDMA_QSCNT_FGET(FIELD)\
- _PER_FGET(_EDMA_QSCNT_ADDR,EDMA,CNT,##FIELD)
-
- #define _EDMA_QSCNT_FSET(FIELD,field)\
- _PER_FSET(_EDMA_QSCNT_ADDR,EDMA,CNT,##FIELD,field)
-
- #define _EDMA_QSCNT_FSETS(FIELD,SYM)\
- _PER_FSETS(_EDMA_QSCNT_ADDR,EDMA,CNT,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | D S T |
-* | Q D S T |
-* | Q S D S T |
-* |___________________|
-*
-* DST - destination address parameter
-* QDST - QDMA destination address register
-* QSDST - QDMA destination address pseudo register
-*
-* FIELDS (msb -> lsb)
-* (rw) DST
-*
-\******************************************************************************/
- #define _EDMA_DST_OFFSET 3
- #define _EDMA_QDST_OFFSET 3
- #define _EDMA_QSDST_OFFSET 11
-
- #define _EDMA_QDST_ADDR 0x0200000Cu
- #define _EDMA_QSDST_ADDR 0x0200002Cu
-
- #define EDMA_QDST EDMA_REG(QDST)
- #define EDMA_QSDST EDMA_REG(QSDST)
-
- #define _EDMA_DST_DST_MASK 0xFFFFFFFFu
- #define _EDMA_DST_DST_SHIFT 0x00000000u
- #define EDMA_DST_DST_DEFAULT 0x00000000u
- #define EDMA_DST_DST_OF(x) _VALUEOF(x)
-
- #define EDMA_DST_OF(x) _VALUEOF(x)
-
- #define EDMA_DST_DEFAULT (Uint32)(\
- _PER_FDEFAULT(EDMA,DST,DST)\
- )
-
- #define EDMA_DST_RMK(dst) (Uint32)(\
- _PER_FMK(EDMA,DST,DST,dst) \
- )
-
- #define _EDMA_QDST_FGET(FIELD)\
- _PER_FGET(_EDMA_QDST_ADDR,EDMA,DST,##FIELD)
-
- #define _EDMA_QDST_FSET(FIELD,field)\
- _PER_FSET(_EDMA_QDST_ADDR,EDMA,DST,##FIELD,field)
-
- #define _EDMA_QDST_FSETS(FIELD,SYM)\
- _PER_FSETS(_EDMA_QDST_ADDR,EDMA,DST,##FIELD,##SYM)
-
- #define _EDMA_QSDST_FGET(FIELD)\
- _PER_FGET(_EDMA_QSDST_ADDR,EDMA,DST,##FIELD)
-
- #define _EDMA_QSDST_FSET(FIELD,field)\
- _PER_FSET(_EDMA_QSDST_ADDR,EDMA,DST,##FIELD,field)
-
- #define _EDMA_QSDST_FSETS(FIELD,SYM)\
- _PER_FSETS(_EDMA_QSDST_ADDR,EDMA,DST,##FIELD,##SYM)
-
-
-/******************************************************************************\
-* _____________________
-* | |
-* | I D X |
-* | Q I D X |
-* | Q S I D X |
-* |___________________|
-*
-* IDX - index parameter
-* QIDX - QDMA index register
-* QSIDX - QDMA index pseudo register
-*
-* FIELDS (msb -> lsb)
-* (rw) FRMIDX
-* (rw) ELEIDX
-*
-\******************************************************************************/
- #define _EDMA_IDX_OFFSET 4
- #define _EDMA_QIDX_OFFSET 4
- #define _EDMA_QSIDX_OFFSET 12
-
- #define _EDMA_QIDX_ADDR 0x02000010u
- #define _EDMA_QSIDX_ADDR 0x02000030u
-
- #define EDMA_QIDX EDMA_REG(QIDX)
- #define EDMA_QSIDX EDMA_REG(QSIDX)
-
- #define _EDMA_IDX_FRMIDX_MASK 0xFFFF0000u
- #define _EDMA_IDX_FRMIDX_SHIFT 0x00000010u
- #define EDMA_IDX_FRMIDX_DEFAULT 0x00000000u
- #define EDMA_IDX_FRMIDX_OF(x) _VALUEOF(x)
-
- #define _EDMA_IDX_ELEIDX_MASK 0x0000FFFFu
- #define _EDMA_IDX_ELEIDX_SHIFT 0x00000000u
- #define EDMA_IDX_ELEIDX_DEFAULT 0x00000000u
- #define EDMA_IDX_ELEIDX_OF(x) _VALUEOF(x)
-
- #define EDMA_IDX_OF(x) _VALUEOF(x)
-
- #define EDMA_IDX_DEFAULT (Uint32)(\
- _PER_FDEFAULT(EDMA,IDX,FRMIDX)\
- |_PER_FDEFAULT(EDMA,IDX,ELEIDX)\
- )
-
- #define EDMA_IDX_RMK(frmidx,eleidx) (Uint32)(\
- _PER_FMK(EDMA,IDX,FRMIDX,frmidx) \
- |_PER_FMK(EDMA,IDX,ELEIDX,eleidx) \
- )
-
- #define _EDMA_QIDX_FGET(FIELD)\
- _PER_FGET(_EDMA_QIDX_ADDR,EDMA,IDX,##FIELD)
-
- #define _EDMA_QIDX_FSET(FIELD,field