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raw | patch | inline | side by side (parent: 8a86ef7)
author | Raghu Nambiath <rnambiath@ti.com> | |
Mon, 14 Feb 2011 12:08:45 +0000 (17:38 +0530) | ||
committer | Sundaram Raju <sundaram@ti.com> | |
Mon, 14 Feb 2011 12:37:54 +0000 (18:07 +0530) |
Signed-off-by: Sundaram Raju <sundaram@ti.com>
index 368f1a3fab8e6682fa8d9a164fc1dfe6a3d6ed1b..039f4a3e64fe25adae5abd6e4af9f5865a4ef5ea 100755 (executable)
#ifndef _EDMA3_DRV_H_
#define _EDMA3_DRV_H_
+#include <stdint.h>
/* Include the Resource Manager header file */
#include <ti/sdo/edma3/rm/edma3_rm.h>
/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
@{ */
+ /**
+ * @brief This is the EDMA3 LLD Version. Versions numbers are encoded in the following
+ * format:
+ * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
+ */
+#define EDMA3_LLD_DRV_VERSION_ID (0x020B0002)
+
+/**
+ * @brief This is the version string which describes the EDMA3 LLD along with the
+ * date and build information.
+ */
+#define EDMA3_LLD_DRV_VERSION_STR "EDMA3 LLD Revision: 02.11.00.02"
+
+
/** @brief EDMA3 Driver Error Codes Base define */
#define EDMA3_DRV_E_BASE (-128)
*/
typedef struct {
/** Number of DMA Channels supported by the underlying EDMA3 Controller. */
- unsigned int numDmaChannels;
+ uint32_t numDmaChannels;
/** Number of QDMA Channels supported by the underlying EDMA3 Controller */
- unsigned int numQdmaChannels;
+ uint32_t numQdmaChannels;
/**
* Number of Interrupt Channels supported by the underlying EDMA3
* Controller
*/
- unsigned int numTccs;
+ uint32_t numTccs;
/** Number of PaRAM Sets supported by the underlying EDMA3 Controller */
- unsigned int numPaRAMSets;
+ uint32_t numPaRAMSets;
/** Number of Event Queues in the underlying EDMA3 Controller */
- unsigned int numEvtQueue;
+ uint32_t numEvtQueue;
/**
* Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller
*/
- unsigned int numTcs;
+ uint32_t numTcs;
/** Number of Regions in the underlying EDMA3 Controller */
- unsigned int numRegions;
+ uint32_t numRegions;
/**
* \brief Channel mapping existence
* any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA
* channel (like QDMA Channels).
*/
- unsigned int dmaChPaRAMMapExists;
+ uint32_t dmaChPaRAMMapExists;
/** Existence of memory protection feature */
- unsigned int memProtectionExists;
+ uint32_t memProtectionExists;
/** Base address of EDMA3 CC memory mapped registers. */
void *globalRegs;
* EDMA3 transfer completion interrupt line (could be different for ARM
* and DSP)
*/
- unsigned int xferCompleteInt;
+ uint32_t xferCompleteInt;
/** EDMA3 CC error interrupt line (could be different for ARM and DSP) */
- unsigned int ccError;
+ uint32_t ccError;
/** EDMA3 TCs error interrupt line (could be different for ARM and DSP) */
- unsigned int tcError[EDMA3_MAX_TC];
+ uint32_t tcError[EDMA3_MAX_TC];
/**
* \brief EDMA3 TC priority setting
* relative to IO initiated by the other bus masters on the
* device (ARM, DSP, USB, etc)
*/
- unsigned int evtQPri [EDMA3_MAX_EVT_QUE];
+ uint32_t evtQPri [EDMA3_MAX_EVT_QUE];
/**
* \brief Event Queues Watermark Levels
* or equals the threshold/watermark value that is set
* in the queue watermark threshold register (QWMTHRA).
*/
- unsigned int evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
+ uint32_t evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
/**
* \brief Default Burst Size (DBS) of TCs.
* default burst size (DBS). Different TCs can have different
* DBS values. It is defined in Bytes.
*/
- unsigned int tcDefaultBurstSize[EDMA3_MAX_TC];
+ uint32_t tcDefaultBurstSize[EDMA3_MAX_TC];
/**
* \brief Mapping from DMA channels to PaRAM Sets
* automatically uses the right PaRAM Set for that DMA channel.
* Useful only if mapping exists, otherwise of no use.
*/
- unsigned int dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
+ uint32_t dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
/**
* \brief Mapping from DMA channels to TCCs
* TCC code will be returned when the transfer is completed
* on the mapped DMA channel.
*/
- unsigned int dmaChannelTccMap [EDMA3_MAX_DMA_CH];
+ uint32_t dmaChannelTccMap [EDMA3_MAX_DMA_CH];
/**
* \brief Mapping from DMA channels to Hardware Events
* channel.
* All channels need not be mapped, some can be free also.
*/
- unsigned int dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
+ uint32_t dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
} EDMA3_DRV_GblConfigParams;
/**\struct EDMA3_DRV_InstanceInitConfig
typedef struct
{
/** PaRAM Sets owned by the EDMA3 Driver Instance. */
- unsigned int ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
+ uint32_t ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
/** DMA Channels owned by the EDMA3 Driver Instance. */
- unsigned int ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
+ uint32_t ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
/** QDMA Channels owned by the EDMA3 Driver Instance. */
- unsigned int ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
+ uint32_t ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
/** TCCs owned by the EDMA3 Driver Instance. */
- unsigned int ownTccs[EDMA3_MAX_TCC_DWRDS];
+ uint32_t ownTccs[EDMA3_MAX_TCC_DWRDS];
/**
* \brief Reserved PaRAM Sets
* be given when user requests for ANY available PaRAM Set for linking
* using 'EDMA3_DRV_LINK_CHANNEL' as channel id.
*/
- unsigned int resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
+ uint32_t resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
/**
* \brief Reserved DMA channels
* not be given when user requests for ANY available DMA channel using
* 'EDMA3_DRV_DMA_CHANNEL_ANY' as channel id.
*/
- unsigned int resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
+ uint32_t resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
/**
* \brief Reserved QDMA channels
* not be given when user requests for ANY available QDMA channel using
* 'EDMA3_DRV_QDMA_CHANNEL_ANY' as channel id.
*/
- unsigned int resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
+ uint32_t resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
/**
* \brief Reserved TCCs
* be given when user requests for ANY available TCC using
* 'EDMA3_DRV_TCC_ANY' as resource id.
*/
- unsigned int resvdTccs[EDMA3_MAX_TCC_DWRDS];
+ uint32_t resvdTccs[EDMA3_MAX_TCC_DWRDS];
}EDMA3_DRV_InstanceInitConfig;
/**\struct EDMA3_DRV_InitConfig
* region associated with this master instance will receive the EDMA3
* interrupts (if enabled).
*/
- unsigned int isMaster;
+ uint32_t isMaster;
/**
* EDMA3 resources related shadow region specific information. Which all
* program the global EDMA3 registers (like Queue priority, Queue water-
* mark level, error registers etc).
*/
- unsigned short isSlave;
+ uint16_t isSlave;
/** For future use **/
- unsigned short param;
+ uint16_t param;
}EDMA3_DRV_MiscParam;
/**
*
* \return EDMA3_DRV_SOK or EDMA3_DRV Error code
*/
-EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
+EDMA3_DRV_Result EDMA3_DRV_create (uint32_t phyCtrllerInstId,
const EDMA3_DRV_GblConfigParams *gblCfgParams,
const void *miscParam);
/**
*
* \return EDMA3_DRV_SOK or EDMA3_DRV Error code
*/
-EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int phyCtrllerInstId,
+EDMA3_DRV_Result EDMA3_DRV_delete (uint32_t phyCtrllerInstId,
const void *param);
/**
* EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data
* structures, to make it re-entrant.
*/
-EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId,
+EDMA3_DRV_Handle EDMA3_DRV_open (uint32_t phyCtrllerInstId,
const EDMA3_DRV_InitConfig *initCfg,
EDMA3_DRV_Result *errorCode);
* function (ISR context).
*/
EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
- unsigned int *pLCh,
- unsigned int *pTcc,
+ uint32_t *pLCh,
+ uint32_t *pTcc,
EDMA3_RM_EventQueue evtQueue,
EDMA3_RM_TccCallback tccCb,
void *cbData);
* de-allocation. It is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
- unsigned int channelId);
+ uint32_t channelId);
/**
* \brief Disables the DMA Channel by clearing the Event Enable Register and
* re-entrant for same channelId value.
*/
EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
- unsigned int channelId);
+ uint32_t channelId);
/**
@}
* non-re-entrant for same lCh1 & lCh2 values.
*/
EDMA3_DRV_Result EDMA3_DRV_linkChannel ( EDMA3_DRV_Handle hEdma,
- unsigned int lCh1,
- unsigned int lCh2);
+ uint32_t lCh1,
+ uint32_t lCh2);
/**
* \brief Unlink the channel from the earlier linked logical channel.
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh);
+ uint32_t lCh);
/**
@}
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_OptField optField,
- unsigned int newOptFieldVal);
+ uint32_t newOptFieldVal);
/**
* \brief Get a particular OPT field in the PaRAM set associated with the
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_OptField optField,
- unsigned int *optFieldVal);
+ uint32_t *optFieldVal);
/**
* \brief DMA source parameters setup
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setSrcParams ( EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int srcAddr,
+ uint32_t lCh,
+ uint32_t srcAddr,
EDMA3_DRV_AddrMode addrMode,
EDMA3_DRV_FifoWidth fifoWidth);
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setDestParams ( EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int destAddr,
+ uint32_t lCh,
+ uint32_t destAddr,
EDMA3_DRV_AddrMode addrMode,
EDMA3_DRV_FifoWidth fifoWidth );
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setSrcIndex ( EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- int srcBIdx,
- int srcCIdx );
+ uint32_t lCh,
+ int32_t srcBIdx,
+ int32_t srcCIdx );
/**
* \brief DMA destination index setup
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- int destBIdx,
- int destCIdx);
+ uint32_t lCh,
+ int32_t destBIdx,
+ int32_t destCIdx);
/**
* \brief DMA transfer parameters setup
*/
EDMA3_DRV_Result EDMA3_DRV_setTransferParams (
EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int aCnt,
- unsigned int bCnt,
- unsigned int cCnt,
- unsigned int bCntReload,
+ uint32_t lCh,
+ uint32_t aCnt,
+ uint32_t bCnt,
+ uint32_t cCnt,
+ uint32_t bCntReload,
EDMA3_DRV_SyncType syncType);
/**
* non-re-entrant for same lCh1 & lCh2 values.
*/
EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh1,
- unsigned int lCh2,
+ uint32_t lCh1,
+ uint32_t lCh2,
const EDMA3_DRV_ChainOptions *chainOptions);
/**
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh);
+ uint32_t lCh);
/**
@}
/** @addtogroup EDMA3_LLD_DRV_FUNCTION_BASIC
@{ */
+/**
+ * \brief Version information
+ *
+ * The function is used to get the version information of the EDMA LLD.
+ *
+ * \return Version Information.
+ */
+uint32_t EDMA3_DRV_getVersion (void);
+
+/**
+ * \brief Version string querry
+ *
+ * The function is used to get the version string for the EDMA LLD.
+ *
+ * \return Version Information.
+ */
+const char* EDMA3_DRV_getVersionStr (void);
+
/**
* \brief Start EDMA transfer on the specified channel.
*
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_TrigMode trigMode);
/**
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_TrigMode trigMode);
/**
*/
EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (
EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_TrigMode trigMode);
/**
* \brief PaRAM Set Entry type
*
* Use this enum to set or get any of the
- * 8 DWords(unsigned int) within a Parameter RAM set
+ * 8 DWords(uint32_t) within a Parameter RAM set
*/
typedef enum
{
*/
typedef struct {
/** OPT field of PaRAM Set */
- volatile unsigned int OPT;
+ volatile uint32_t OPT;
/**
* \brief Starting byte address of Source
* For FIFO mode, srcAddr must be a 256-bit aligned address.
*/
- volatile unsigned int SRC;
+ volatile uint32_t SRC;
/**
* Number of bytes in each Array (ACNT) (16 bits) and
* Number of Arrays in each Frame (BCNT) (16 bits).
*/
- volatile unsigned int A_B_CNT;
+ volatile uint32_t A_B_CNT;
/**
* \brief Starting byte address of destination
* For FIFO mode, destAddr must be a 256-bit aligned address.
* i.e. 5 LSBs should be 0.
*/
- volatile unsigned int DST;
+ volatile uint32_t DST;
/**
* Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and
* If DAM is set to 1 (via channelOptions) then destInterArrIndex should
* be an even multiple of 32 bytes
*/
- volatile unsigned int SRC_DST_BIDX;
+ volatile uint32_t SRC_DST_BIDX;
/**
* \brief Address for linking (AutoReloading of a PaRAM Set) (16 bits)
*
* B count reload field is relevant only for A-sync transfers.
*/
- volatile unsigned int LINK_BCNTRLD;
+ volatile uint32_t LINK_BCNTRLD;
/**
* \brief Index between consecutive frames of a Source Block (SRCCIDX)
* (16 bits) and Index between consecutive frames of a Dest Block
* (DSTCIDX) (16 bits).
*/
- volatile unsigned int SRC_DST_CIDX;
+ volatile uint32_t SRC_DST_CIDX;
/**
* \brief Number of Frames in a block (CCNT) (16 bits).
*/
- volatile unsigned int CCNT;
+ volatile uint32_t CCNT;
} EDMA3_DRV_ParamentryRegs;
/* LITTLE_ENDIAN_MODE */
typedef struct {
/** OPT field of PaRAM Set */
- volatile unsigned int opt;
+ volatile uint32_t opt;
/**
* \brief Starting byte address of Source
* For FIFO mode, srcAddr must be a 256-bit aligned address.
*/
- volatile unsigned int srcAddr;
+ volatile uint32_t srcAddr;
/**
* \brief Number of bytes in each Array (ACNT)
*/
- volatile unsigned short aCnt;
+ volatile uint16_t aCnt;
/**
* \brief Number of Arrays in each Frame (BCNT)
*/
- volatile unsigned short bCnt;
+ volatile uint16_t bCnt;
/**
* \brief Starting byte address of destination
* For FIFO mode, destAddr must be a 256-bit aligned address.
* i.e. 5 LSBs should be 0.
*/
- volatile unsigned int destAddr;
+ volatile uint32_t destAddr;
/**
* \brief Index between consec. arrays of a Source Frame (SRCBIDX)
* If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
* be an even multiple of 32 bytes.
*/
- volatile short srcBIdx;
+ volatile int16_t srcBIdx;
/**
* \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
* If DAM is set to 1 (via channelOptions) then destInterArrIndex should
* be an even multiple of 32 bytes
*/
- volatile short destBIdx;
+ volatile int16_t destBIdx;
/**
* \brief Address for linking (AutoReloading of a PaRAM Set)
* Linking is especially useful for use with ping-pong buffers and
* circular buffers
*/
- volatile unsigned short linkAddr;
+ volatile uint16_t linkAddr;
/**
* \brief Reload value of the numArrInFrame (BCNT)
* Relevant only for A-sync transfers
*/
- volatile unsigned short bCntReload;
+ volatile uint16_t bCntReload;
/**
* \brief Index between consecutive frames of a Source Block (SRCCIDX)
*/
- volatile short srcCIdx;
+ volatile int16_t srcCIdx;
/**
* \brief Index between consecutive frames of a Dest Block (DSTCIDX)
*/
- volatile short destCIdx;
+ volatile int16_t destCIdx;
/**
* \brief Number of Frames in a block (CCNT)
*/
- volatile unsigned short cCnt;
+ volatile uint16_t cCnt;
/**
* \brief Reserved
*/
- volatile short reserved;
+ volatile int16_t reserved;
} EDMA3_DRV_PaRAMRegs;
#else
/* BIG_ENDIAN_MODE */
typedef struct {
/** OPT field of PaRAM Set */
- volatile unsigned int opt;
+ volatile uint32_t opt;
/**
* \brief Starting byte address of Source
* For FIFO mode, srcAddr must be a 256-bit aligned address.
*/
- volatile unsigned int srcAddr;
+ volatile uint32_t srcAddr;
/**
* \brief Number of Arrays in each Frame (BCNT)
*/
- volatile unsigned short bCnt;
+ volatile uint16_t bCnt;
/**
* \brief Number of bytes in each Array (ACNT)
*/
- volatile unsigned short aCnt;
+ volatile uint16_t aCnt;
/**
* \brief Starting byte address of destination
* For FIFO mode, destAddr must be a 256-bit aligned address.
* i.e. 5 LSBs should be 0.
*/
- volatile unsigned int destAddr;
+ volatile uint32_t destAddr;
/**
* \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
* If DAM is set to 1 (via channelOptions) then destInterArrIndex should
* be an even multiple of 32 bytes
*/
- volatile short destBIdx;
+ volatile int16_t destBIdx;
/**
* \brief Index between consec. arrays of a Source Frame (SRCBIDX)
* If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
* be an even multiple of 32 bytes.
*/
- volatile short srcBIdx;
+ volatile int16_t srcBIdx;
/**
* \brief Reload value of the numArrInFrame (BCNT)
* Relevant only for A-sync transfers
*/
- volatile unsigned short bCntReload;
+ volatile uint16_t bCntReload;
/**
* \brief Address for linking (AutoReloading of a PaRAM Set)
* Linking is especially useful for use with ping-pong buffers and
* circular buffers
*/
- volatile unsigned short linkAddr;
+ volatile uint16_t linkAddr;
/**
* \brief Index between consecutive frames of a Dest Block (DSTCIDX)
*/
- volatile short destCIdx;
+ volatile int16_t destCIdx;
/**
* \brief Index between consecutive frames of a Source Block (SRCCIDX)
*/
- volatile short srcCIdx;
+ volatile int16_t srcCIdx;
/**
* \brief Reserved
*/
- volatile short reserved;
+ volatile int16_t reserved;
/**
* \brief Number of Frames in a block (CCNT)
*/
- volatile unsigned short cCnt;
+ volatile uint16_t cCnt;
} EDMA3_DRV_PaRAMRegs;
#endif /* #ifndef _BIG_ENDIAN */
/**
* \brief Event Queue Priorities
*/
- unsigned int evtQPri[EDMA3_MAX_EVT_QUE];
+ uint32_t evtQPri[EDMA3_MAX_EVT_QUE];
}EDMA3_DRV_EvtQuePriority;
/**
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_RM_QdmaTrigWord trigWord);
/**
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setPaRAM ( EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
const EDMA3_DRV_PaRAMRegs *newPaRAM);
/**
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMRegs *currPaRAM);
/**
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMEntry paRAMEntry,
- unsigned int newPaRAMEntryVal);
+ uint32_t newPaRAMEntryVal);
/**
* \brief Get a particular PaRAM set entry of the specified PaRAM set
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMEntry paRAMEntry,
- unsigned int *paRAMEntryVal);
+ uint32_t *paRAMEntryVal);
/**
* \brief Set a particular PaRAM set field of the specified PaRAM set
* re-entrant for same lCh value.
*/
EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMField paRAMField,
- unsigned int newPaRAMFieldVal);
+ uint32_t newPaRAMFieldVal);
/**
* \brief Get a particular PaRAM set field of the specified PaRAM set
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMField paRAMField,
- unsigned int *currPaRAMFieldVal);
+ uint32_t *currPaRAMFieldVal);
/**
* \brief Sets EDMA TC priority
* the global CC Registers, to make it re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma,
- unsigned int channelId,
+ uint32_t channelId,
EDMA3_RM_EventQueue eventQ);
/**
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
- unsigned int channelId,
- unsigned int *mappedEvtQ);
+ uint32_t channelId,
+ uint32_t *mappedEvtQ);
/**
* \brief Set the Channel Controller (CC) Register value
* EDMA handles, this function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
- unsigned int regOffset,
- unsigned int newRegValue);
+ uint32_t regOffset,
+ uint32_t newRegValue);
/**
* \brief Get the Channel Controller (CC) Register value
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma,
- unsigned int regOffset,
- unsigned int *regValue);
+ uint32_t regOffset,
+ uint32_t *regValue);
/**
* \brief Wait for a transfer completion interrupt to occur and clear it.
* \note This function is re-entrant for different tccNo.
*/
EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
- unsigned int tccNo);
+ uint32_t tccNo);
/**
* \brief Returns the status of a previously initiated transfer.
* \note This function is re-entrant for different tccNo.
*/
EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
- unsigned int tccNo,
- unsigned short *tccStatus);
+ uint32_t tccNo,
+ uint16_t *tccStatus);
/**
* \brief Get the PaRAM Set Physical Address associated with a logical channel
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int *paramPhyAddr);
+ uint32_t lCh,
+ uint32_t *paramPhyAddr);
/**
@}
* If the value read is '0', it means that PaRAM Sets are NOT getting cleared
* during allocation.
* For e.g.,
- * unsigned short isParamClearingDone;
+ * uint16_t isParamClearingDone;
* cmdArg = ¶mClearingRequired;
*/
EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION,
*
* 2) This function is re-entrant.
*/
-EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId,
+EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(uint32_t phyCtrllerInstId,
EDMA3_RM_RegionId regionId,
EDMA3_DRV_Result *errorCode);
* re-entrant for same channelId value.
*/
EDMA3_DRV_Result EDMA3_DRV_registerTccCb(EDMA3_DRV_Handle hEdma,
- const unsigned int channelId,
+ const uint32_t channelId,
EDMA3_RM_TccCallback tccCb,
void *cbData);
* non-re-entrant for same channelId.
*/
EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb(EDMA3_DRV_Handle hEdma,
- const unsigned int channelId);
+ const uint32_t channelId);
/**
@}
* \note This function is re-entrant for unique combination of EDMA3 hw and
* TC. It is non-re-entrant for same combination.
*/
-EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(unsigned int phyCtrllerInstId,
- unsigned int tcId,
+EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(uint32_t phyCtrllerInstId,
+ uint32_t tcId,
EDMA3_DRV_Tc_Err tcErr);
/**
* \note This function is re-entrant.
*/
EDMA3_DRV_Result EDMA3_DRV_getChannelStatus(EDMA3_DRV_Handle hEdma,
- unsigned int lCh, unsigned int *lchStatus);
+ uint32_t lCh, uint32_t *lchStatus);
/**
* non-re-entrant for same linkCh values.
*/
EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh (EDMA3_DRV_Handle hEdma,
- unsigned int linkCh,
- unsigned int tcc);
+ uint32_t linkCh,
+ uint32_t tcc);
#define EDMA3_DRV_MAX_XBAR_EVENTS (31u)
* For the cross bar event mapped to DMA channel, appropriate Control Config
* register of TPCC event mux register should be configured.
*/
- int dmaMapXbarToChan [EDMA3_DRV_MAX_XBAR_EVENTS];
+ int32_t dmaMapXbarToChan [EDMA3_DRV_MAX_XBAR_EVENTS];
} EDMA3_DRV_GblXbarToChanConfigParams;
* \note This function is re-entrant for unique event values. It is
* non-re-entrant for same event values.
*/
-typedef EDMA3_DRV_Result (*EDMA3_DRV_mapXbarEvtToChan) (unsigned int eventNum,
- unsigned int *chanNum,
+typedef EDMA3_DRV_Result (*EDMA3_DRV_mapXbarEvtToChan) (uint32_t eventNum,
+ uint32_t *chanNum,
const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
/**
@@ -3088,8 +3121,8 @@ typedef EDMA3_DRV_Result (*EDMA3_DRV_mapXbarEvtToChan) (unsigned int eventNum,
* \note This function is re-entrant for unique event values. It is
* non-re-entrant for same event values.
*/
-typedef EDMA3_DRV_Result (*EDMA3_DRV_xbarConfigScr) (unsigned int eventNum,
- unsigned int chanNum);
+typedef EDMA3_DRV_Result (*EDMA3_DRV_xbarConfigScr) (uint32_t eventNum,
+ uint32_t chanNum);
/**
* \brief Initialize the cross bar mapped event to channel function
index accefbe9bb2014486feaed2f56fcdd10b8276e8d..6c7ff02ddad3d83b97c23a2aec7c85dd64479f2c 100755 (executable)
typedef struct
{
/** Physical Instance ID of EDMA3 Controller */
- unsigned int phyCtrllerInstId;
+ uint32_t phyCtrllerInstId;
/** State information of the EDMA3 Driver object */
EDMA3_DRV_ObjState state;
/** Number of EDMA3 Driver instances */
- unsigned int numOpens;
+ uint32_t numOpens;
/**
* \brief Init-time Configuration structure for EDMA3
* Only the master instance shadow region will receive the
* EDMA3 interrupts, if enabled.
*/
- unsigned int isMaster;
+ uint32_t isMaster;
/**
* EDMA3 Driver Instance (Shadow Region) specific
*/
typedef struct {
/** PaRAM Set number associated with the particular channel */
- int paRAMId;
+ int32_t paRAMId;
/** TCC associated with the particular channel */
- unsigned int tcc;
+ uint32_t tcc;
/** Mode of triggering transfer */
EDMA3_DRV_TrigMode trigMode;
*/
#ifdef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
typedef struct {
- unsigned int dmaChannelQueueNum [EDMA3_MAX_DMA_CH];
- unsigned int qdmaChannelQueueNum [EDMA3_MAX_QDMA_CH];
+ uint32_t dmaChannelQueueNum [EDMA3_MAX_DMA_CH];
+ uint32_t qdmaChannelQueueNum [EDMA3_MAX_QDMA_CH];
} EDMA3_DRV_DmaQdmaQueueNum;
#endif
diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_adv.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_adv.c
index 3e1b9b05d539fce3bc2f3468b2952a3a9f50f2fd..7da2012ca8875400a39f4c3556b63c88578acc8d 100755 (executable)
/**
* Maximum Resource Manager Instances supported by the EDMA3 Package.
*/
-extern const unsigned int EDMA3_MAX_RM_INSTANCES;
+extern const uint32_t EDMA3_MAX_RM_INSTANCES;
/**
extern EDMA3_RM_Instance *ptrRMIArray;
/** Local MemZero function */
-extern void edma3MemZero(void *dst, unsigned int len);
+extern void edma3MemZero(void *dst, uint32_t len);
/** Local MemCpy function to copy PaRAM Set ONLY */
extern void edma3ParamCpy(void *dst, const void *src);
@@ -132,33 +132,33 @@ extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGI
extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
/** Max of DMA Channels */
-extern unsigned int edma3_dma_ch_max_val[];
+extern uint32_t edma3_dma_ch_max_val[];
/** Min of Link Channels */
-extern unsigned int edma3_link_ch_min_val[];
+extern uint32_t edma3_link_ch_min_val[];
/** Max of Link Channels */
-extern unsigned int edma3_link_ch_max_val[];
+extern uint32_t edma3_link_ch_max_val[];
/** Min of QDMA Channels */
-extern unsigned int edma3_qdma_ch_min_val[];
+extern uint32_t edma3_qdma_ch_min_val[];
/** Max of QDMA Channels */
-extern unsigned int edma3_qdma_ch_max_val[];
+extern uint32_t edma3_qdma_ch_max_val[];
/** Max of Logical Channels */
-extern unsigned int edma3_log_ch_max_val[];
+extern uint32_t edma3_log_ch_max_val[];
EDMA3_DRV_Result EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh1, unsigned int lCh2)
+ uint32_t lCh1, uint32_t lCh2)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- unsigned int linkBcntReld;
- int paRAM1Id = 0;
- int paRAM2Id = 0;
- unsigned int oldTccVal = 0;
- unsigned int optVal = 0;
- unsigned int newOptVal = 0;
+ uint32_t linkBcntReld;
+ int32_t paRAM1Id = 0;
+ int32_t paRAM2Id = 0;
+ uint32_t oldTccVal = 0;
+ uint32_t optVal = 0;
+ uint32_t newOptVal = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
if (result == EDMA3_DRV_SOK)
{
/* Get the Link-bcntReload PaRAM set entry */
- linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAM1Id].OPT) +
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
+ linkBcntReld = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAM1Id].OPT) +
+ (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
linkBcntReld &= 0xFFFF0000u;
/* Update the Link field with lch2 PaRAM set */
- linkBcntReld |= (0xFFFFu & (unsigned int)(&(globalRegs->PARAMENTRY [paRAM2Id].OPT)));
+ linkBcntReld |= (0xFFFFu & (uint32_t)(&(globalRegs->PARAMENTRY [paRAM2Id].OPT)));
/* Store it back */
*((&globalRegs->PARAMENTRY[paRAM1Id].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;
/*
* Set the TCC field of PaRAM set associated with lch2 to
if (edma3DrvChBoundRes[edma3Id][lCh2].tcc == EDMA3_MAX_TCC)
{
/* for channel 1 */
- optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAM1Id].OPT));
+ optVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAM1Id].OPT));
oldTccVal = EDMA3_DRV_OPT_TCC_GET_MASK(optVal);
/* for channel 2 */
- optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAM2Id].OPT));
+ optVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAM2Id].OPT));
newOptVal = (optVal & EDMA3_DRV_OPT_TCC_CLR_MASK)
|
(EDMA3_DRV_OPT_TCC_SET_MASK(oldTccVal));
return result;
}
-EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
+EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, uint32_t lCh)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
- unsigned int linkBcntReld;
- int paRAMId = 0;
+ uint32_t linkBcntReld;
+ int32_t paRAMId = 0;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -323,15 +323,15 @@ EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int l
else
{
/* Get the Link-bcntReload PaRAM set entry */
- linkBcntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
+ linkBcntReld = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
/* Remove any linking */
linkBcntReld |= 0xFFFFu;
/* Store it back */
*((&globalRegs->PARAMENTRY[paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBcntReld;
}
}
@@ -347,17 +347,17 @@ EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int l
}
EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh1,
- unsigned int lCh2,
+ uint32_t lCh1,
+ uint32_t lCh2,
const EDMA3_DRV_ChainOptions *chainOptions)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
- unsigned int opt = 0x0;
+ uint32_t opt = 0x0;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
if (result == EDMA3_DRV_SOK)
{
- opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+ opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
/* set Transfer complete chaining */
if (chainOptions->tcchEn == EDMA3_DRV_TCCHEN_EN)
}
EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh)
+ uint32_t lCh)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
- unsigned int opt;
+ uint32_t opt;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
if (result == EDMA3_DRV_SOK)
{
- opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+ opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
/* Reset TCCHEN */
opt &= EDMA3_DRV_OPT_TCCHEN_CLR_MASK;
}
EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_RM_QdmaTrigWord trigWord)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
EDMA3_DRV_Result EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
const EDMA3_DRV_PaRAMRegs *newPaRAM)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMRegs *currPaRAM)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMEntry paRAMEntry,
- unsigned int newPaRAMEntryVal)
+ uint32_t newPaRAMEntryVal)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
else
{
*((&globalRegs->PARAMENTRY[paRAMId].OPT) +
- (unsigned int)paRAMEntry) = newPaRAMEntryVal;
+ (uint32_t)paRAMEntry) = newPaRAMEntryVal;
}
}
}
EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMEntry paRAMEntry,
- unsigned int *paRAMEntryVal)
+ uint32_t *paRAMEntryVal)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
else
{
- *paRAMEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
- + (unsigned int)paRAMEntry));
+ *paRAMEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)paRAMEntry));
}
}
}
EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMField paRAMField,
- unsigned int newPaRAMFieldVal)
+ uint32_t newPaRAMFieldVal)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- unsigned int paramEntryVal = 0;
- int paRAMId = 0;
+ uint32_t paramEntryVal = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
break;
case EDMA3_DRV_PARAM_FIELD_ACNT:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT));
paramEntryVal &= 0xFFFF0000u;
newPaRAMFieldVal &= 0x0000FFFFu;
paramEntryVal |= newPaRAMFieldVal;
break;
case EDMA3_DRV_PARAM_FIELD_BCNT:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT));
paramEntryVal &= 0x0000FFFFu;
newPaRAMFieldVal <<= 0x10u;
paramEntryVal |= newPaRAMFieldVal;
break;
case EDMA3_DRV_PARAM_FIELD_SRCBIDX:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
paramEntryVal &= 0xFFFF0000u;
newPaRAMFieldVal &= 0x0000FFFFu;
paramEntryVal |= newPaRAMFieldVal;
break;
case EDMA3_DRV_PARAM_FIELD_DESTBIDX:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
paramEntryVal &= 0x0000FFFFu;
newPaRAMFieldVal <<= 0x10u;
paramEntryVal |= newPaRAMFieldVal;
break;
case EDMA3_DRV_PARAM_FIELD_LINKADDR:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
paramEntryVal &= 0xFFFF0000u;
newPaRAMFieldVal &= 0x0000FFFFu;
paramEntryVal |= newPaRAMFieldVal;
break;
case EDMA3_DRV_PARAM_FIELD_BCNTRELOAD:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
paramEntryVal &= 0x0000FFFFu;
newPaRAMFieldVal <<= 0x10u;
paramEntryVal |= newPaRAMFieldVal;
break;
case EDMA3_DRV_PARAM_FIELD_SRCCIDX:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
paramEntryVal &= 0xFFFF0000u;
newPaRAMFieldVal &= 0x0000FFFFu;
paramEntryVal |= newPaRAMFieldVal;
break;
case EDMA3_DRV_PARAM_FIELD_DESTCIDX:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
paramEntryVal &= 0x0000FFFFu;
newPaRAMFieldVal <<= 0x10u;
paramEntryVal |= newPaRAMFieldVal;
}
EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_PaRAMField paRAMField,
- unsigned int *currPaRAMFieldVal)
+ uint32_t *currPaRAMFieldVal)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- unsigned int paramEntryVal = 0;
- int paRAMId = 0;
+ uint32_t paramEntryVal = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
switch (paRAMField)
{
case EDMA3_DRV_PARAM_FIELD_OPT:
- *currPaRAMFieldVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_OPT));
+ *currPaRAMFieldVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_OPT));
break;
case EDMA3_DRV_PARAM_FIELD_SRCADDR:
- *currPaRAMFieldVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC));
+ *currPaRAMFieldVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC));
break;
case EDMA3_DRV_PARAM_FIELD_ACNT:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT));
paramEntryVal &= 0x0000FFFFu;
*currPaRAMFieldVal = paramEntryVal;
break;
case EDMA3_DRV_PARAM_FIELD_BCNT:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT));
paramEntryVal = paramEntryVal >> 0x10u;
*currPaRAMFieldVal = paramEntryVal;
break;
case EDMA3_DRV_PARAM_FIELD_DESTADDR:
- *currPaRAMFieldVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_DST));
+ *currPaRAMFieldVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_DST));
break;
case EDMA3_DRV_PARAM_FIELD_SRCBIDX:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
paramEntryVal &= 0x0000FFFFu;
*currPaRAMFieldVal = paramEntryVal;
break;
case EDMA3_DRV_PARAM_FIELD_DESTBIDX:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
paramEntryVal = paramEntryVal >> 0x10u;
*currPaRAMFieldVal = paramEntryVal;
break;
case EDMA3_DRV_PARAM_FIELD_LINKADDR:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
paramEntryVal &= 0x0000FFFFu;
*currPaRAMFieldVal = paramEntryVal;
break;
case EDMA3_DRV_PARAM_FIELD_BCNTRELOAD:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
paramEntryVal = paramEntryVal >> 0x10u;
*currPaRAMFieldVal = paramEntryVal;
break;
case EDMA3_DRV_PARAM_FIELD_SRCCIDX:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
paramEntryVal &= 0x0000FFFFu;
*currPaRAMFieldVal = paramEntryVal;
break;
case EDMA3_DRV_PARAM_FIELD_DESTCIDX:
- paramEntryVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+ paramEntryVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
paramEntryVal = paramEntryVal >> 0x10u;
*currPaRAMFieldVal = paramEntryVal;
break;
case EDMA3_DRV_PARAM_FIELD_CCNT:
- *currPaRAMFieldVal = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_CCNT));
+ *currPaRAMFieldVal = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT) + (unsigned)EDMA3_DRV_PARAM_ENTRY_CCNT));
break;
default:
EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,
const EDMA3_DRV_EvtQuePriority *evtQPriObj)
{
- unsigned int intState;
+ uint32_t intState;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
- unsigned int evtQNum = 0;
+ uint32_t evtQNum = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
evtQNum = 0;
while (evtQNum < drvObject->gblCfgParams.numEvtQueue)
{
- globalRegs->QUEPRI = globalRegs->QUEPRI & (unsigned int)EDMA3_RM_QUEPRI_CLR_MASK(evtQNum);
+ globalRegs->QUEPRI = globalRegs->QUEPRI & (uint32_t)EDMA3_RM_QUEPRI_CLR_MASK(evtQNum);
globalRegs->QUEPRI |= EDMA3_RM_QUEPRI_SET_MASK(evtQNum, evtQPriObj->evtQPri[evtQNum]);
evtQNum++;
}
EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ(EDMA3_DRV_Handle hEdma,
- unsigned int channelId,
+ uint32_t channelId,
EDMA3_RM_EventQueue eventQ)
{
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- unsigned int intState;
- unsigned int edma3Id;
+ uint32_t intState;
+ uint32_t edma3Id;
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
}
EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
- unsigned int channelId,
- unsigned int *mappedEvtQ)
+ uint32_t channelId,
+ uint32_t *mappedEvtQ)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
- unsigned int regOffset,
- unsigned int newRegValue)
+ uint32_t regOffset,
+ uint32_t newRegValue)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- volatile unsigned int regPhyAddr = 0x0u;
+ volatile uint32_t regPhyAddr = 0x0u;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
if (EDMA3_DRV_SOK == result)
{
/* Semaphore taken successfully, modify the registers. */
- regPhyAddr = (unsigned int)(drvObject->gblCfgParams.globalRegs) + regOffset;
+ regPhyAddr = (uint32_t)(drvObject->gblCfgParams.globalRegs) + regOffset;
- *(unsigned int *)regPhyAddr = newRegValue;
+ *(uint32_t *)regPhyAddr = newRegValue;
/* Return the semaphore back */
result = edma3OsSemGive(drvInst->drvSemHandle);
}
EDMA3_DRV_Result EDMA3_DRV_getCCRegister ( EDMA3_DRV_Handle hEdma,
- unsigned int regOffset,
- unsigned int *regValue)
+ uint32_t regOffset,
+ uint32_t *regValue)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- volatile unsigned int regPhyAddr = 0x0u;
+ volatile uint32_t regPhyAddr = 0x0u;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
{
if (drvObject->gblCfgParams.globalRegs != NULL)
{
- regPhyAddr = (unsigned int)(drvObject->gblCfgParams.globalRegs) + regOffset;
+ regPhyAddr = (uint32_t)(drvObject->gblCfgParams.globalRegs) + regOffset;
- *regValue = *(unsigned int *)regPhyAddr;
+ *regValue = *(uint32_t *)regPhyAddr;
}
}
}
}
EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
- unsigned int tccNo)
+ uint32_t tccNo)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- unsigned int tccBitMask = 0x0u;
+ uint32_t tccBitMask = 0x0u;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
- unsigned int tccNo,
- unsigned short *tccStatus)
+ uint32_t tccNo,
+ uint16_t *tccStatus)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- unsigned int tccBitMask = 0x0u;
+ uint32_t tccBitMask = 0x0u;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int *paramPhyAddr)
+ uint32_t lCh,
+ uint32_t *paramPhyAddr)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
else
{
- *paramPhyAddr = (unsigned int)&(globalRegs->PARAMENTRY [paRAMId].OPT);
+ *paramPhyAddr = (uint32_t)&(globalRegs->PARAMENTRY [paRAMId].OPT);
}
}
return result;
}
-EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId,
+EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(uint32_t phyCtrllerInstId,
EDMA3_RM_RegionId regionId,
EDMA3_DRV_Result *errorCode)
{
}
EDMA3_DRV_Result EDMA3_DRV_registerTccCb(EDMA3_DRV_Handle hEdma,
- const unsigned int channelId,
+ const uint32_t channelId,
EDMA3_RM_TccCallback tccCb,
void *cbData)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
EDMA3_RM_ResDesc channelObj;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
}
EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb(EDMA3_DRV_Handle hEdma,
- const unsigned int channelId)
+ const uint32_t channelId)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
EDMA3_RM_ResDesc channelObj;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
return result;
}
-EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(unsigned int phyCtrllerInstId,
- unsigned int tcId,
+EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(uint32_t phyCtrllerInstId,
+ uint32_t tcId,
EDMA3_DRV_Tc_Err tcErr)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
}
EDMA3_DRV_Result EDMA3_DRV_getChannelStatus(EDMA3_DRV_Handle hEdma,
- unsigned int lCh, unsigned int *lchStatus)
+ uint32_t lCh, uint32_t *lchStatus)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- unsigned int edma3Id;
- unsigned int status = 0x0;
- unsigned int tcc;
+ uint32_t edma3Id;
+ uint32_t status = 0x0;
+ uint32_t tcc;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
if (lCh >= edma3_qdma_ch_min_val[edma3Id]
&& lCh <= edma3_qdma_ch_max_val[edma3Id])
{
- unsigned int qdma_ch = lCh - edma3_qdma_ch_min_val[edma3Id];
+ uint32_t qdma_ch = lCh - edma3_qdma_ch_min_val[edma3Id];
if((globalRegs->QEMR & (1u << qdma_ch)) != FALSE)
{
}
EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh ( EDMA3_DRV_Handle hEdma,
- unsigned int linkCh,
- unsigned int tcc)
+ uint32_t linkCh,
+ uint32_t tcc)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId;
+ int32_t paRAMId;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
/* If parameter checking is enabled... */
#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c
index 6aa81c7f56fbbbe0339053a3f805f94357b02b67..a89a86460b25bc537af8c6f492004eab68916610 100755 (executable)
/**
* Maximum Resource Manager Instances supported by the EDMA3 Package.
*/
-extern const unsigned int EDMA3_MAX_RM_INSTANCES;
+extern const uint32_t EDMA3_MAX_RM_INSTANCES;
/**
extern EDMA3_RM_Instance *ptrRMIArray;
/** Local MemSet function */
-extern void edma3MemZero(void *dst, unsigned int len);
+extern void edma3MemZero(void *dst, uint32_t len);
/** Local MemCpy function */
-extern void edma3MemCpy(void *dst, const void *src, unsigned int len);
+extern void edma3MemCpy(void *dst, const void *src, uint32_t len);
/**
* \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller.
@@ -140,29 +140,31 @@ extern EDMA3_DRV_Instance drvInstance [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGI
extern EDMA3_DRV_ChBoundResources edma3DrvChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_LOGICAL_CH];
/** Max of DMA Channels */
-extern unsigned int edma3_dma_ch_max_val[];
+extern uint32_t edma3_dma_ch_max_val[];
/** Min of Link Channels */
-extern unsigned int edma3_link_ch_min_val[];
+extern uint32_t edma3_link_ch_min_val[];
/** Max of Link Channels */
-extern unsigned int edma3_link_ch_max_val[];
+extern uint32_t edma3_link_ch_max_val[];
/** Min of QDMA Channels */
-extern unsigned int edma3_qdma_ch_min_val[];
+extern uint32_t edma3_qdma_ch_min_val[];
/** Max of QDMA Channels */
-extern unsigned int edma3_qdma_ch_max_val[];
+extern uint32_t edma3_qdma_ch_max_val[];
/** Max of Logical Channels */
-extern unsigned int edma3_log_ch_max_val[];
+extern uint32_t edma3_log_ch_max_val[];
/* Local functions prototypes */
/*---------------------------------------------------------------------------*/
/** Remove various mappings and do cleanup for DMA/QDMA channels */
static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
- unsigned int channelId);
+ uint32_t channelId);
+/** @brief Global Variable which describes the EDMA3 LLD Version Information */
+const char edma3LldVersionStr[] = EDMA3_LLD_DRV_VERSION_STR ":" __DATE__ ":" __TIME__;
/*---------------------------------------------------------------------------*/
EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
- unsigned int *pLCh,
- unsigned int *pTcc,
+ uint32_t *pLCh,
+ uint32_t *pTcc,
EDMA3_RM_EventQueue evtQueue,
EDMA3_RM_TccCallback tccCb,
void *cbData)
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- unsigned int mappedTcc = EDMA3_DRV_CH_NO_TCC_MAP;
- int paRAMId = (int)EDMA3_RM_RES_ANY;
+ uint32_t mappedTcc = EDMA3_DRV_CH_NO_TCC_MAP;
+ int32_t paRAMId = (int32_t)EDMA3_RM_RES_ANY;
EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_QDMA;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- int mappedPaRAMId;
- unsigned int edma3Id;
- unsigned int freeDmaQdmaChannel = FALSE;
- unsigned int mapXbarEvtToChanFlag = FALSE;
- unsigned int xBarEvtBeforeMap = 0;
+ int32_t mappedPaRAMId;
+ uint32_t edma3Id;
+ uint32_t freeDmaQdmaChannel = FALSE;
+ uint32_t mapXbarEvtToChanFlag = FALSE;
+ uint32_t xBarEvtBeforeMap = 0;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
if (EDMA3_DRV_SOK == result)
{
resObj.type = EDMA3_RM_RES_PARAM_SET;
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
result = EDMA3_RM_allocResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
}
if (EDMA3_DRV_SOK == result)
{
- paRAMId = (int)resObj.resId;
+ paRAMId = (int32_t)resObj.resId;
if (chType == EDMA3_DRV_CHANNEL_TYPE_LINK)
{
else
{
#ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
- unsigned int intState = 0;
+ uint32_t intState = 0;
edma3OsProtectEntry(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
&intState);
/* Step 5: Associate DMA Channel to Event Queue */
case EDMA3_DRV_CHANNEL_TYPE_QDMA:
{
- unsigned int qdmaChannel = channelObj.resId;
+ uint32_t qdmaChannel = channelObj.resId;
/* Step 4: Register the callback function, if required */
if (NULL != tccCb)
else
{
#ifndef EDMA3_PROGRAM_QUEUE_NUM_REGISTER_INIT_TIME
- unsigned int intState = 0;
+ uint32_t intState = 0;
edma3OsProtectEntry(edma3Id, EDMA3_OS_PROTECT_INTERRUPT,
&intState);
/* Step 5: Associate QDMA Channel to Event Queue */
{
/* TCC allocation failed, free the PaRAM Set, */
resObj.type = EDMA3_RM_RES_PARAM_SET;
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
/* And free the DMA/QDMA channel */
}
EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
- unsigned int channelId)
+ uint32_t channelId)
{
EDMA3_RM_ResDesc resObj;
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId;
- unsigned int tcc;
+ int32_t paRAMId;
+ uint32_t tcc;
EDMA3_DRV_ChannelType chType = EDMA3_DRV_CHANNEL_TYPE_NONE;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
resObj.type = EDMA3_RM_RES_PARAM_SET;
/* Get the PaRAM id from the book-keeping info. */
- resObj.resId = (unsigned int)(edma3DrvChBoundRes[edma3Id][channelId].paRAMId);
+ resObj.resId = (uint32_t)(edma3DrvChBoundRes[edma3Id][channelId].paRAMId);
result = EDMA3_RM_freeResource(drvInst->resMgrInstance,
(EDMA3_RM_ResDesc *)&resObj);
{
/* Now Free the PARAM set and TCC */
resObj.type = EDMA3_RM_RES_PARAM_SET;
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
result = EDMA3_RM_freeResource(drvInst->resMgrInstance, (EDMA3_RM_ResDesc *)&resObj);
if (EDMA3_DRV_SOK == result)
}
EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
- unsigned int channelId)
+ uint32_t channelId)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int count;
- unsigned int value = 0;
- unsigned int edma3Id;
+ uint32_t count;
+ uint32_t value = 0;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_OptField optField,
- unsigned int newOptFieldVal)
+ uint32_t newOptFieldVal)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- unsigned int newOptVal = 0;
- unsigned int oldOptVal = 0;
- int paRAMId = 0;
+ uint32_t newOptVal = 0;
+ uint32_t oldOptVal = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
if (EDMA3_DRV_SOK == result)
{
- oldOptVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+ oldOptVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
switch (optField)
{
}
EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_OptField optField,
- unsigned int *optFieldVal)
+ uint32_t *optFieldVal)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- unsigned int optVal = 0;
- int paRAMId = 0;
+ uint32_t optVal = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
if (EDMA3_DRV_SOK == result)
{
- optVal = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+ optVal = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
switch (optField)
{
}
EDMA3_DRV_Result EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int srcAddr,
+ uint32_t lCh,
+ uint32_t srcAddr,
EDMA3_DRV_AddrMode addrMode,
EDMA3_DRV_FifoWidth fifoWidth)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
- unsigned int opt = 0;
+ uint32_t opt = 0;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int mappedEvtQ = 0;
- unsigned int defaultBurstSize = 0;
- unsigned int edma3Id;
+ uint32_t mappedEvtQ = 0;
+ uint32_t defaultBurstSize = 0;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
{
/* Set Src Address */
*((&globalRegs->PARAMENTRY[paRAMId].OPT) +
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC) = srcAddr;
+ (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC) = srcAddr;
- opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+ opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
/* Set SAM */
opt &= EDMA3_DRV_OPT_SAM_CLR_MASK;
}
EDMA3_DRV_Result EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- unsigned int destAddr,
+ uint32_t lCh,
+ uint32_t destAddr,
EDMA3_DRV_AddrMode addrMode,
EDMA3_DRV_FifoWidth fifoWidth)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
- unsigned int opt = 0;
+ uint32_t opt = 0;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int mappedEvtQ = 0;
- unsigned int defaultBurstSize = 0;
- unsigned int edma3Id;
+ uint32_t mappedEvtQ = 0;
+ uint32_t defaultBurstSize = 0;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
{
/* Set the Dest address */
*((&globalRegs->PARAMENTRY[paRAMId].OPT) +
- (unsigned int)EDMA3_DRV_PARAM_ENTRY_DST) = destAddr;
+ (uint32_t)EDMA3_DRV_PARAM_ENTRY_DST) = destAddr;
- opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+ opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
/* Set DAM */
opt &= EDMA3_DRV_OPT_DAM_CLR_MASK;
}
EDMA3_DRV_Result EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
- int srcBIdx, int srcCIdx)
+ uint32_t lCh,
+ int32_t srcBIdx, int32_t srcCIdx)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
- unsigned int srcDstBidx;
- unsigned int srcDstCidx;
+ uint32_t srcDstBidx;
+ uint32_t srcDstCidx;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
else
{
/* Get SrcDestBidx PaRAM Set entry */
- srcDstBidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
+ srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
srcDstBidx &= 0xFFFF0000u;
/* Update it */
- srcDstBidx |= (unsigned int)(srcBIdx & 0xFFFF);
+ srcDstBidx |= (uint32_t)(srcBIdx & 0xFFFF);
/* Store it back */
*((&globalRegs->PARAMENTRY[paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
/* Get SrcDestCidx PaRAM Set entry */
- srcDstCidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+ srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
srcDstCidx &= 0xFFFF0000u;
/* Update it */
- srcDstCidx |= (unsigned int)(srcCIdx & 0xFFFF);
+ srcDstCidx |= (uint32_t)(srcCIdx & 0xFFFF);
/* Store it back */
*((&globalRegs->PARAMENTRY[paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
}
}
return result;
}
-EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh,
- int destBIdx, int destCIdx)
+EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, uint32_t lCh,
+ int32_t destBIdx, int32_t destCIdx)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
- unsigned int srcDstBidx;
- unsigned int srcDstCidx;
+ uint32_t srcDstBidx;
+ uint32_t srcDstCidx;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -1640,28 +1642,28 @@ EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int l
else
{
/* Get SrcDestBidx PaRAM Set entry */
- srcDstBidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
+ srcDstBidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX));
srcDstBidx &= 0xFFFFu;
/* Update it */
- srcDstBidx |= (unsigned int)((destBIdx & 0xFFFF) << 16u);
+ srcDstBidx |= (uint32_t)((destBIdx & 0xFFFF) << 16u);
/* Store it back */
*((&globalRegs->PARAMENTRY[paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX) = srcDstBidx;
/* Get SrcDestCidx PaRAM Set entry */
- srcDstCidx = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
+ srcDstCidx = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX));
srcDstCidx &= 0xFFFFu;
/* Update it */
- srcDstCidx |= (unsigned int)((destCIdx & 0xFFFF) << 16u);
+ srcDstCidx |= (uint32_t)((destCIdx & 0xFFFF) << 16u);
/* Store it back */
*((&globalRegs->PARAMENTRY[paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX) = srcDstCidx;
}
}
@@ -1677,18 +1679,18 @@ EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int l
}
EDMA3_DRV_Result EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma,
- unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt,
- unsigned int bCntReload, EDMA3_DRV_SyncType syncType)
+ uint32_t lCh, uint32_t aCnt, uint32_t bCnt, uint32_t cCnt,
+ uint32_t bCntReload, EDMA3_DRV_SyncType syncType)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
- unsigned int abCnt = 0;
- unsigned int linkBCntReld = 0;
- unsigned int opt = 0;
+ uint32_t abCnt = 0;
+ uint32_t linkBCntReld = 0;
+ uint32_t opt = 0;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- int paRAMId = 0;
+ int32_t paRAMId = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
/* Set aCnt and bCnt */
*((&globalRegs->PARAMENTRY[paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = abCnt;
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT) = abCnt;
/* Set cCnt */
*((&globalRegs->PARAMENTRY[paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_CCNT) = cCnt;
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_CCNT) = cCnt;
- linkBCntReld = (unsigned int)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
+ linkBCntReld = (uint32_t)(*((&globalRegs->PARAMENTRY [paRAMId].OPT)
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD));
linkBCntReld |= ((bCntReload & 0xFFFFu) << 16u);
/* Set bCntReload */
*((&globalRegs->PARAMENTRY[paRAMId].OPT)
- + (unsigned int)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBCntReld;
+ + (uint32_t)EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD) = linkBCntReld;
- opt = (unsigned int)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
+ opt = (uint32_t)(*(&globalRegs->PARAMENTRY [paRAMId].OPT));
/* Set Sync Type */
opt &= EDMA3_DRV_OPT_SYNCDIM_CLR_MASK;
}
EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
- unsigned int lCh,
+ uint32_t lCh,
EDMA3_DRV_TrigMode trigMode)
{
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
- unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
+ uint32_t lCh, EDMA3_DRV_TrigMode trigMode)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
- unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
+ uint32_t lCh, EDMA3_DRV_TrigMode trigMode)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
/* Definitions of Local functions - Start */
/** Remove various mappings and do cleanup for DMA/QDMA channels */
static EDMA3_DRV_Result edma3RemoveMapping (EDMA3_DRV_Handle hEdma,
- unsigned int channelId)
+ uint32_t channelId)
{
- unsigned int intState=0;
+ uint32_t intState=0;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
EDMA3_RM_ResDesc channelObj;
- unsigned int edma3Id;
+ uint32_t edma3Id;
assert (hEdma != NULL);
return result;
}
+uint32_t EDMA3_DRV_getVersion (void)
+{
+ return EDMA3_LLD_DRV_VERSION_ID;
+}
+
+const char* EDMA3_DRV_getVersionStr (void)
+{
+ return edma3LldVersionStr;
+}
/* Definitions of Local functions - End */
/* End of File */
diff --git a/packages/ti/sdo/edma3/drv/src/edma3_drv_init.c b/packages/ti/sdo/edma3/drv/src/edma3_drv_init.c
index c2c6d550fc2f16174aa1183e1118f86307f82d3a..206b9362b4dc116e245795674f112813be4be8a4 100755 (executable)
/**
* Maximum Resource Manager Instances supported by the EDMA3 Package.
*/
-extern const unsigned int EDMA3_MAX_RM_INSTANCES;
+extern const uint32_t EDMA3_MAX_RM_INSTANCES;
/**
extern EDMA3_RM_Instance *ptrRMIArray;
/** Local MemZero function */
-extern void edma3MemZero(void *dst, unsigned int len);
+extern void edma3MemZero(void *dst, uint32_t len);
/** Local MemCpy function */
-extern void edma3MemCpy(void *dst, const void *src, unsigned int len);
+extern void edma3MemCpy(void *dst, const void *src, uint32_t len);
/**
* \brief EDMA3 Driver Objects, tied to each EDMA3 HW Controller.
* Local function to prepare the init config structure for
* open of Resource Manager
*/
-static EDMA3_DRV_Result edma3OpenResMgr (unsigned int instId,
- unsigned int regionId,
- unsigned short flag);
+static EDMA3_DRV_Result edma3OpenResMgr (uint32_t instId,
+ uint32_t regionId,
+ uint16_t flag);
/*---------------------------------------------------------------------------*/
-EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
+EDMA3_DRV_Result EDMA3_DRV_create (uint32_t phyCtrllerInstId,
const EDMA3_DRV_GblConfigParams *gblCfgParams,
const void *miscParam)
{
- unsigned int count = 0;
+ uint32_t count = 0;
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_RM_GblConfigParams rmGblCfgParams;
/**
* Used to reset the Internal EDMA3 Driver Data Structures for the first time.
*/
- static unsigned short drvInitDone = FALSE;
+ static uint16_t drvInitDone = FALSE;
/**
* We are NOT checking 'gblCfgParams' for NULL. Whatever user has passed
return result;
}
-EDMA3_DRV_Result EDMA3_DRV_delete(unsigned int phyCtrllerInstId,
+EDMA3_DRV_Result EDMA3_DRV_delete(uint32_t phyCtrllerInstId,
const void *param)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
return result;
}
-EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId,
+EDMA3_DRV_Handle EDMA3_DRV_open (uint32_t phyCtrllerInstId,
const EDMA3_DRV_InitConfig *initCfg,
EDMA3_DRV_Result *errorCode)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Object *drvObject = NULL;
EDMA3_DRV_Instance *drvInstanceHandle = NULL;
- unsigned int intState = 0;
+ uint32_t intState = 0;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned short flag = 0;
+ uint16_t flag = 0;
/* If parameter checking is enabled... */
#ifndef EDMA3_DRV_PARAM_CHECK_DISABLE
EDMA3_DRV_Result EDMA3_DRV_close(EDMA3_DRV_Handle hEdma,
const void *param)
{
- unsigned int intState = 0;
+ uint32_t intState = 0;
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_DRV_Instance *drvInst = NULL;
EDMA3_DRV_Object *drvObject = NULL;
/* Definitions of Local functions - Start */
/* Local function to prepare the init config structure for open of Resource Manager */
-static EDMA3_DRV_Result edma3OpenResMgr (unsigned int instId,
- unsigned int regionId,
- unsigned short flag)
+static EDMA3_DRV_Result edma3OpenResMgr (uint32_t instId,
+ uint32_t regionId,
+ uint16_t flag)
{
EDMA3_DRV_Result result = EDMA3_DRV_SOK;
EDMA3_RM_Param initParam;
EDMA3_RM_InstanceInitConfig rmInstanceCfg;
EDMA3_RM_Handle hResMgr = NULL;
EDMA3_RM_Result rmResult;
- unsigned int resMgrIdx = 0u;
+ uint32_t resMgrIdx = 0u;
EDMA3_RM_Instance *temp_rm_instance = NULL;
assert ((instId < EDMA3_MAX_EDMA3_INSTANCES)
index a56a96c8b0849609cd880fd886008b2261cd2e7c..d8d5164845e0154496f7da7915ae33e096e5c255 100755 (executable)
#endif
/** EDMA3_RM Result - return value of a function */
-typedef int EDMA3_RM_Result;
+typedef int32_t EDMA3_RM_Result;
/** EDMA3_DRV Result - return value of a function */
-typedef int EDMA3_DRV_Result;
+typedef int32_t EDMA3_DRV_Result;
/** EDMA3 Resource Manager Result OK */
#define EDMA3_RM_SOK (0u)
* available Transfer Controllers).
*/
/** EDMA3 Completion Handler ISR Routine */
-extern void lisrEdma3ComplHandler0 (unsigned int arg);
+extern void lisrEdma3ComplHandler0 (uint32_t arg);
/** EDMA3 CC Error Interrupt Handler ISR Routine */
-extern void lisrEdma3CCErrHandler0 (unsigned int arg);
+extern void lisrEdma3CCErrHandler0 (uint32_t arg);
/** EDMA3 TC0 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC0ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC0ErrHandler0(uint32_t arg);
/** EDMA3 TC1 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC1ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC1ErrHandler0(uint32_t arg);
/** EDMA3 TC2 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC2ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC2ErrHandler0(uint32_t arg);
/** EDMA3 TC3 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC3ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC3ErrHandler0(uint32_t arg);
/** EDMA3 TC4 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC4ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC4ErrHandler0(uint32_t arg);
/** EDMA3 TC5 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC5ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC5ErrHandler0(uint32_t arg);
/** EDMA3 TC6 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC6ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC6ErrHandler0(uint32_t arg);
/** EDMA3 TC7 Error Interrupt Handler ISR Routine */
-extern void lisrEdma3TC7ErrHandler0(unsigned int arg);
+extern void lisrEdma3TC7ErrHandler0(uint32_t arg);
/**
* Defines for the level of OS protection needed when calling
*
* \return None
*/
-extern void edma3OsProtectEntry (unsigned int edma3InstanceId,
- int level,
- unsigned int *intState);
+extern void edma3OsProtectEntry (uint32_t edma3InstanceId,
+ int32_t level,
+ uint32_t *intState);
/**
* \brief EDMA3 OS Protect Exit
*
* \return None
*/
-extern void edma3OsProtectExit (unsigned int edma3InstanceId,
- int level,
- unsigned int intState);
+extern void edma3OsProtectExit (uint32_t edma3InstanceId,
+ int32_t level,
+ uint32_t intState);
/**
* Counting Semaphore related functions (OS dependent) should be
* \return EDMA3_DRV_Result if successful else a suitable error code
*/
extern EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle hSem,
- int mSecTimeout);
+ int32_t mSecTimeout);
/**
* \brief EDMA3 OS Semaphore Give
index 0b68628d2ed66fee5be104294e2b36814ca61dec..c431427474aabcab3a03b9334d66a20c034b3149 100755 (executable)
#ifndef _EDMA3_RM_H_
#define _EDMA3_RM_H_
+#include <stdint.h>
/** Include common header file */
#include <ti/sdo/edma3/rm/edma3_common.h>
* gblerrData is application provided data when open'ing the Resource Manager.
*/
typedef void (* EDMA3_RM_GblErrCallback)(EDMA3_RM_GlobalError deviceStatus,
- unsigned int instanceId,
- void *gblerrData);
+ uint32_t instanceId,
+ void *gblerrData);
/**
@}
* appData is passed by the application during Register'ing of
* TCC Callback function.
*/
-typedef void (* EDMA3_RM_TccCallback)(unsigned int tcc,
+typedef void (* EDMA3_RM_TccCallback)(uint32_t tcc,
EDMA3_RM_TccStatus status,
void *appData);
* Or
* resId can take the value EDMA3_RM_RES_ANY.
*/
- unsigned int resId;
+ uint32_t resId;
/** Resource Type */
EDMA3_RM_ResType type;
*/
EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr,
const EDMA3_RM_ResDesc *channelObj,
- unsigned int tcc,
+ uint32_t tcc,
EDMA3_RM_TccCallback tccCb,
void *cbData);
*
* Use this to assign channels/PaRAM sets/TCCs to a particular Region.
*/
-typedef unsigned int EDMA3_RM_RegionId;
+typedef uint32_t EDMA3_RM_RegionId;
/**\typedef EDMA3_RM_EventQueue
* \brief EDMA3 Event Queue assignment
* to a DMA/QDMA channel using this.
*
*/
-typedef unsigned int EDMA3_RM_EventQueue;
+typedef uint32_t EDMA3_RM_EventQueue;
/**
@}
*/
typedef struct {
/** Number of DMA Channels supported by the underlying EDMA3 Controller. */
- unsigned int numDmaChannels;
+ uint32_t numDmaChannels;
/** Number of QDMA Channels supported by the underlying EDMA3 Controller */
- unsigned int numQdmaChannels;
+ uint32_t numQdmaChannels;
/**
* Number of Interrupt Channels supported by the underlying EDMA3
* Controller
*/
- unsigned int numTccs;
+ uint32_t numTccs;
/** Number of PaRAM Sets supported by the underlying EDMA3 Controller */
- unsigned int numPaRAMSets;
+ uint32_t numPaRAMSets;
/** Number of Event Queues in the underlying EDMA3 Controller */
- unsigned int numEvtQueue;
+ uint32_t numEvtQueue;
/**
* Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller
*/
- unsigned int numTcs;
+ uint32_t numTcs;
/** Number of Regions in the underlying EDMA3 Controller */
- unsigned int numRegions;
+ uint32_t numRegions;
/**
* \brief Channel mapping existence
* any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA
* channel (like QDMA Channels).
*/
- unsigned int dmaChPaRAMMapExists;
+ uint32_t dmaChPaRAMMapExists;
/** Existence of memory protection feature */
- unsigned int memProtectionExists;
+ uint32_t memProtectionExists;
/** Base address of EDMA3 CC memory mapped registers. */
void *globalRegs;
* EDMA3 transfer completion interrupt line (could be different for ARM
* and DSP)
*/
- unsigned int xferCompleteInt;
+ uint32_t xferCompleteInt;
/** EDMA3 CC error interrupt line (could be different for ARM and DSP) */
- unsigned int ccError;
+ uint32_t ccError;
/** EDMA3 TCs error interrupt line (could be different for ARM and DSP) */
- unsigned int tcError[EDMA3_MAX_TC];
+ uint32_t tcError[EDMA3_MAX_TC];
/**
* \brief EDMA3 TC priority setting
* relative to IO initiated by the other bus masters on the
* device (ARM, DSP, USB, etc)
*/
- unsigned int evtQPri [EDMA3_MAX_EVT_QUE];
+ uint32_t evtQPri [EDMA3_MAX_EVT_QUE];
/**
* \brief Event Queues Watermark Levels
* or equals the threshold/watermark value that is set
* in the queue watermark threshold register (QWMTHRA).
*/
- unsigned int evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
+ uint32_t evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
/**
* \brief Default Burst Size (DBS) of TCs.
* default burst size (DBS). Different TCs can have different
* DBS values. It is defined in Bytes.
*/
- unsigned int tcDefaultBurstSize[EDMA3_MAX_TC];
+ uint32_t tcDefaultBurstSize[EDMA3_MAX_TC];
/**
* \brief Mapping from DMA channels to PaRAM Sets
* automatically uses the right PaRAM Set for that DMA channel.
* Useful only if mapping exists, otherwise of no use.
*/
- unsigned int dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
+ uint32_t dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
/**
* \brief Mapping from DMA channels to TCCs
* TCC code will be returned when the transfer is completed
* on the mapped DMA channel.
*/
- unsigned int dmaChannelTccMap [EDMA3_MAX_DMA_CH];
+ uint32_t dmaChannelTccMap [EDMA3_MAX_DMA_CH];
/**
* \brief Mapping from DMA channels to Hardware Events
* channel.
* All channels need not be mapped, some can be free also.
*/
- unsigned int dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
+ uint32_t dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
} EDMA3_RM_GblConfigParams;
/**\struct EDMA3_RM_InstanceInitConfig
typedef struct
{
/** PaRAM Sets owned by the EDMA3 RM Instance. */
- unsigned int ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
+ uint32_t ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
/** DMA Channels owned by the EDMA3 RM Instance. */
- unsigned int ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
+ uint32_t ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
/** QDMA Channels owned by the EDMA3 RM Instance. */
- unsigned int ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
+ uint32_t ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
/** TCCs owned by the EDMA3 RM Instance. */
- unsigned int ownTccs[EDMA3_MAX_TCC_DWRDS];
+ uint32_t ownTccs[EDMA3_MAX_TCC_DWRDS];
/**
* \brief Reserved PaRAM Sets
* be given when user requests for ANY available PaRAM Set using
* 'EDMA3_RM_PARAM_ANY' as resource/channel id.
*/
- unsigned int resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
+ uint32_t resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
/**
* \brief Reserved DMA channels
* not be given when user requests for ANY available DMA channel using
* 'EDMA3_RM_DMA_CHANNEL_ANY' as resource/channel id.
*/
- unsigned int resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
+ uint32_t resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
/**
* \brief Reserved QDMA channels
* not be given when user requests for ANY available QDMA channel using
* 'EDMA3_RM_QDMA_CHANNEL_ANY' as resource/channel id.
*/
- unsigned int resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
+ uint32_t resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
/**
* \brief Reserved TCCs
* be given when user requests for ANY available TCC using
* 'EDMA3_RM_TCC_ANY' as resource/channel id.
*/
- unsigned int resvdTccs[EDMA3_MAX_TCC_DWRDS];
+ uint32_t resvdTccs[EDMA3_MAX_TCC_DWRDS];
}EDMA3_RM_InstanceInitConfig;
/**\struct EDMA3_RM_Param
* region associated with this master instance will receive the EDMA3
* interrupts (if enabled).
*/
- unsigned int isMaster;
+ uint32_t isMaster;
/**
* EDMA3 resources related shadow region specific information. Which all
/**
* Whether initialization of Region Specific Registers is required or not?
*/
- unsigned int regionInitEnable;
+ uint32_t regionInitEnable;
/** Instance wide Global Error callback parameters */
EDMA3_RM_GblErrCallbackParams gblerrCbParams;
* program the global EDMA3 registers (like Queue priority, Queue water-
* mark level, error registers etc).
*/
- unsigned short isSlave;
+ uint16_t isSlave;
/** For future use **/
- unsigned short param;
+ uint16_t param;
}EDMA3_RM_MiscParam;
/**
*
* \return EDMA3_RM_SOK or EDMA3_RM Error Code
*/
-EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
+EDMA3_RM_Result EDMA3_RM_create (uint32_t phyCtrllerInstId,
const EDMA3_RM_GblConfigParams *gblCfgParams,
const void *miscParam);
*
* \return EDMA3_RM_SOK or EDMA3_RM Error Code
*/
-EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId,
+EDMA3_RM_Result EDMA3_RM_delete (uint32_t phyCtrllerInstId,
const void *param);
/**
* EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data
* structures, to make it re-entrant.
*/
-EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
+EDMA3_RM_Handle EDMA3_RM_open (uint32_t phyCtrllerInstId,
const EDMA3_RM_Param *initParam,
EDMA3_RM_Result *errorCode);
*/
EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *firstResIdObj,
- unsigned int numResources);
+ uint32_t numResources);
/**
* \brief Free a contiguous region of specified EDMA3 Resource
*/
EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *firstResIdObj,
- unsigned int numResources);
+ uint32_t numResources);
/**
@}
*/
EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *lChObj,
- unsigned int *pParam,
- unsigned int *pTcc);
+ uint32_t *pParam,
+ uint32_t *pTcc);
/** \fn EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle
* hEdmaResMgr, EDMA3_RM_ResDesc *lChObj)
*/
typedef struct {
/** OPT field of PaRAM Set */
- volatile unsigned int OPT;
+ volatile uint32_t OPT;
/**
* \brief Starting byte address of Source
* For FIFO mode, srcAddr must be a 256-bit aligned address.
*/
- volatile unsigned int SRC;
+ volatile uint32_t SRC;
/**
* Number of bytes in each Array (ACNT) (16 bits) and
* Number of Arrays in each Frame (BCNT) (16 bits).
*/
- volatile unsigned int A_B_CNT;
+ volatile uint32_t A_B_CNT;
/**
* \brief Starting byte address of destination
* For FIFO mode, destAddr must be a 256-bit aligned address.
* i.e. 5 LSBs should be 0.
*/
- volatile unsigned int DST;
+ volatile uint32_t DST;
/**
* Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and
* If DAM is set to 1 (via channelOptions) then destInterArrIndex should
* be an even multiple of 32 bytes
*/
- volatile unsigned int SRC_DST_BIDX;
+ volatile uint32_t SRC_DST_BIDX;
/**
* \brief Address for linking (AutoReloading of a PaRAM Set) (16 bits)
*
* B count reload field is relevant only for A-sync transfers.
*/
- volatile unsigned int LINK_BCNTRLD;
+ volatile uint32_t LINK_BCNTRLD;
/**
* \brief Index between consecutive frames of a Source Block (SRCCIDX)
* (16 bits) and Index between consecutive frames of a Dest Block
* (DSTCIDX) (16 bits).
*/
- volatile unsigned int SRC_DST_CIDX;
+ volatile uint32_t SRC_DST_CIDX;
/**
* \brief Number of Frames in a block (CCNT) (16 bits).
*/
- volatile unsigned int CCNT;
+ volatile uint32_t CCNT;
} EDMA3_RM_ParamentryRegs;
/**\struct EDMA3_RM_PaRAMRegs
/* LITTLE_ENDIAN_MODE */
typedef struct {
/** OPT field of PaRAM Set */
- volatile unsigned int opt;
+ volatile uint32_t opt;
/**
* \brief Starting byte address of Source
* For FIFO mode, srcAddr must be a 256-bit aligned address.
*/
- volatile unsigned int srcAddr;
+ volatile uint32_t srcAddr;
/**
* \brief Number of bytes in each Array (ACNT)
*/
- volatile unsigned short aCnt;
+ volatile uint16_t aCnt;
/**
* \brief Number of Arrays in each Frame (BCNT)
*/
- volatile unsigned short bCnt;
+ volatile uint16_t bCnt;
/**
* \brief Starting byte address of destination
* For FIFO mode, destAddr must be a 256-bit aligned address.
* i.e. 5 LSBs should be 0.
*/
- volatile unsigned int destAddr;
+ volatile uint32_t destAddr;
/**
* \brief Index between consec. arrays of a Source Frame (SRCBIDX)
* If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
* be an even multiple of 32 bytes.
*/
- volatile short srcBIdx;
+ volatile int16_t srcBIdx;
/**
* \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
* If DAM is set to 1 (via channelOptions) then destInterArrIndex should
* be an even multiple of 32 bytes
*/
- volatile short destBIdx;
+ volatile int16_t destBIdx;
/**
* \brief Address for linking (AutoReloading of a PaRAM Set)
* Linking is especially useful for use with ping-pong buffers and
* circular buffers
*/
- volatile unsigned short linkAddr;
+ volatile uint16_t linkAddr;
/**
* \brief Reload value of the numArrInFrame (BCNT)
* Relevant only for A-sync transfers
*/
- volatile unsigned short bCntReload;
+ volatile uint16_t bCntReload;
/**
* \brief Index between consecutive frames of a Source Block (SRCCIDX)
*/
- volatile short srcCIdx;
+ volatile int16_t srcCIdx;
/**
* \brief Index between consecutive frames of a Dest Block (DSTCIDX)
*/
- volatile short destCIdx;
+ volatile int16_t destCIdx;
/**
* \brief Number of Frames in a block (CCNT)
*/
- volatile unsigned short cCnt;
+ volatile uint16_t cCnt;
/**
* \brief Reserved
*/
- volatile short reserved;
+ volatile int16_t reserved;
} EDMA3_RM_PaRAMRegs;
#else
/* BIG_ENDIAN_MODE */
typedef struct {
/** OPT field of PaRAM Set */
- volatile unsigned int opt;
+ volatile uint32_t opt;
/**
* \brief Starting byte address of Source
* For FIFO mode, srcAddr must be a 256-bit aligned address.
*/
- volatile unsigned int srcAddr;
+ volatile uint32_t srcAddr;
/**
* \brief Number of Arrays in each Frame (BCNT)
*/
- volatile unsigned short bCnt;
+ volatile uint16_t bCnt;
/**
* \brief Number of bytes in each Array (ACNT)
*/
- volatile unsigned short aCnt;
+ volatile uint16_t aCnt;
/**
* \brief Starting byte address of destination
* For FIFO mode, destAddr must be a 256-bit aligned address.
* i.e. 5 LSBs should be 0.
*/
- volatile unsigned int destAddr;
+ volatile uint32_t destAddr;
/**
* \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
* If DAM is set to 1 (via channelOptions) then destInterArrIndex should
* be an even multiple of 32 bytes
*/
- volatile short destBIdx;
+ volatile int16_t destBIdx;
/**
* \brief Index between consec. arrays of a Source Frame (SRCBIDX)
* If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
* be an even multiple of 32 bytes.
*/
- volatile short srcBIdx;
+ volatile int16_t srcBIdx;
/**
* \brief Reload value of the numArrInFrame (BCNT)
* Relevant only for A-sync transfers
*/
- volatile unsigned short bCntReload;
+ volatile uint16_t bCntReload;
/**
* \brief Address for linking (AutoReloading of a PaRAM Set)
* Linking is especially useful for use with ping-pong buffers and
* circular buffers
*/
- volatile unsigned short linkAddr;
+ volatile uint16_t linkAddr;
/**
* \brief Index between consecutive frames of a Dest Block (DSTCIDX)
*/
- volatile short destCIdx;
+ volatile int16_t destCIdx;
/**
* \brief Index between consecutive frames of a Source Block (SRCCIDX)
*/
- volatile short srcCIdx;
+ volatile int16_t srcCIdx;
/**
* \brief Reserved
*/
- volatile short reserved;
+ volatile int16_t reserved;
/**
* \brief Number of Frames in a block (CCNT)
*/
- volatile unsigned short cCnt;
+ volatile uint16_t cCnt;
} EDMA3_RM_PaRAMRegs;
#endif /* #ifndef _BIG_ENDIAN */
* \brief QDMA Trigger Word
*
* Use this enum to set the QDMA trigger word to any of the
- * 8 DWords(unsigned int) within a Parameter RAM set
+ * 8 DWords(uint32_t) within a Parameter RAM set
*/
typedef enum
{
* non-re-entrant for same channelId values.
*/
EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int channelId,
- unsigned int paRAMId);
+ uint32_t channelId,
+ uint32_t paRAMId);
/**
* \brief Bind the resources QDMA Channel and PaRAM Set. Also, Set the
* for same channelId values.
*/
EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int channelId,
- unsigned int paRAMId,
+ uint32_t channelId,
+ uint32_t paRAMId,
EDMA3_RM_QdmaTrigWord trigWord);
/**
* For users using different RM handles, this function is re-entrant.
*/
EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int regOffset,
- unsigned int newRegValue);
+ uint32_t regOffset,
+ uint32_t newRegValue);
/**
* \brief Get the Channel Controller (CC) Register value
* \note This function is re-entrant.
*/
EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int regOffset,
- unsigned int *regValue);
+ uint32_t regOffset,
+ uint32_t *regValue);
/**
* \brief Wait for a transfer completion interrupt to occur and clear it.
*
*/
EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int tccNo);
+ uint32_t tccNo);
/**
* \brief Returns the status of a previously initiated transfer.
* \note This function is re-entrant for different tccNo.
*/
EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int tccNo,
- unsigned short *tccStatus);
+ uint32_t tccNo,
+ uint16_t *tccStatus);
/**
* \brief Copy the user specified PaRAM Set onto the PaRAM Set
*/
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *lChObj,
- unsigned int *paramPhyAddr);
+ uint32_t *paramPhyAddr);
/**
* \brief Get the Channel Controller or Transfer Controller (n) Physical
*/
EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_Cntrlr_PhyAddr controllerId,
- unsigned int *phyAddress);
+ uint32_t *phyAddress);
/**
* \brief Get the SoC specific configuration structure for the EDMA3 Hardware.
*
* \note This function is re-entrant.
*/
-EDMA3_RM_Result EDMA3_RM_getGblConfigParams (unsigned int phyCtrllerInstId,
- EDMA3_RM_GblConfigParams *gblCfgParams);
+EDMA3_RM_Result EDMA3_RM_getGblConfigParams (uint32_t phyCtrllerInstId,
+ EDMA3_RM_GblConfigParams *gblCfgParams);
/**
* \brief Get the RM Instance specific configuration structure for different
* during allocation.
*
* For e.g.,
- * unsigned int *isParamClearingDone = (unsigned int *)cmdArg;
+ * uint32_t *isParamClearingDone = (uint32_t *)cmdArg;
* (*isParamClearingDone) = paramClearingRequired;
*/
EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION,
* during allocation.
*
* For e.g.,
- * unsigned int *isParamClearingDone = (unsigned int *)cmdArg;
+ * uint32_t *isParamClearingDone = (uint32_t *)cmdArg;
* (*isParamClearingDone) = paramClearingRequired;
*/
EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION,
* For the cross bar event mapped to DMA channel, appropriate Control Config
* register of TPCC event mux register should be configured.
*/
- int dmaMapXbarToChan [EDMA3_RM_MAX_XBAR_EVENTS];
+ int32_t dmaMapXbarToChan [EDMA3_RM_MAX_XBAR_EVENTS];
} EDMA3_RM_GblXbarToChanConfigParams;
* \note This function is re-entrant for unique event values. It is
* non-re-entrant for same event values.
*/
-typedef EDMA3_RM_Result (*EDMA3_RM_mapXbarEvtToChan) (unsigned int eventNum,
- unsigned int *chanNum,
+typedef EDMA3_RM_Result (*EDMA3_RM_mapXbarEvtToChan) (uint32_t eventNum,
+ uint32_t *chanNum,
const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig);
/**
* \note This function is re-entrant for unique event values. It is
* non-re-entrant for same event values.
*/
-typedef EDMA3_RM_Result (*EDMA3_RM_xbarConfigScr) (unsigned int eventNum,
- unsigned int chanNum);
+typedef EDMA3_RM_Result (*EDMA3_RM_xbarConfigScr) (uint32_t eventNum,
+ uint32_t chanNum);
/**
* \brief Initialize the cross bar mapped event to channel function
diff --git a/packages/ti/sdo/edma3/rm/src/edma3_rl_cc.h b/packages/ti/sdo/edma3/rm/src/edma3_rl_cc.h
index c1f2010146b7ec3b83afd41415ed28aa37f1d648..03854cc5e67234edc0ef5364c43f3632514cdcba 100644 (file)
* Register Overlay Structure for DRA
\**************************************************************************/
typedef struct {
- volatile unsigned int DRAE;
- volatile unsigned int DRAEH;
+ volatile uint32_t DRAE;
+ volatile uint32_t DRAEH;
} EDMA3_CCRL_DraRegs;
/**************************************************************************\
* Register Overlay Structure for QUEEVTENTRY
\**************************************************************************/
typedef struct {
- volatile unsigned int QUEEVT_ENTRY;
+ volatile uint32_t QUEEVT_ENTRY;
} EDMA3_CCRL_QueevtentryRegs;
/**************************************************************************\
* Register Overlay Structure for SHADOW
\**************************************************************************/
typedef struct {
- volatile unsigned int ER;
- volatile unsigned int ERH;
- volatile unsigned int ECR;
- volatile unsigned int ECRH;
- volatile unsigned int ESR;
- volatile unsigned int ESRH;
- volatile unsigned int CER;
- volatile unsigned int CERH;
- volatile unsigned int EER;
- volatile unsigned int EERH;
- volatile unsigned int EECR;
- volatile unsigned int EECRH;
- volatile unsigned int EESR;
- volatile unsigned int EESRH;
- volatile unsigned int SER;
- volatile unsigned int SERH;
- volatile unsigned int SECR;
- volatile unsigned int SECRH;
- volatile unsigned char RSVD0[8];
- volatile unsigned int IER;
- volatile unsigned int IERH;
- volatile unsigned int IECR;
- volatile unsigned int IECRH;
- volatile unsigned int IESR;
- volatile unsigned int IESRH;
- volatile unsigned int IPR;
- volatile unsigned int IPRH;
- volatile unsigned int ICR;
- volatile unsigned int ICRH;
- volatile unsigned int IEVAL;
- volatile unsigned char RSVD1[4];
- volatile unsigned int QER;
- volatile unsigned int QEER;
- volatile unsigned int QEECR;
- volatile unsigned int QEESR;
- volatile unsigned int QSER;
- volatile unsigned int QSECR;
- volatile unsigned char RSVD2[360];
+ volatile uint32_t ER;
+ volatile uint32_t ERH;
+ volatile uint32_t ECR;
+ volatile uint32_t ECRH;
+ volatile uint32_t ESR;
+ volatile uint32_t ESRH;
+ volatile uint32_t CER;
+ volatile uint32_t CERH;
+ volatile uint32_t EER;
+ volatile uint32_t EERH;
+ volatile uint32_t EECR;
+ volatile uint32_t EECRH;
+ volatile uint32_t EESR;
+ volatile uint32_t EESRH;
+ volatile uint32_t SER;
+ volatile uint32_t SERH;
+ volatile uint32_t SECR;
+ volatile uint32_t SECRH;
+ volatile uint8_t RSVD0[8];
+ volatile uint32_t IER;
+ volatile uint32_t IERH;
+ volatile uint32_t IECR;
+ volatile uint32_t IECRH;
+ volatile uint32_t IESR;
+ volatile uint32_t IESRH;
+ volatile uint32_t IPR;
+ volatile uint32_t IPRH;
+ volatile uint32_t ICR;
+ volatile uint32_t ICRH;
+ volatile uint32_t IEVAL;
+ volatile uint8_t RSVD1[4];
+ volatile uint32_t QER;
+ volatile uint32_t QEER;
+ volatile uint32_t QEECR;
+ volatile uint32_t QEESR;
+ volatile uint32_t QSER;
+ volatile uint32_t QSECR;
+ volatile uint8_t RSVD2[360];
} EDMA3_CCRL_ShadowRegs;
typedef volatile EDMA3_CCRL_ShadowRegs *EDMA3_CCRL_ShadowRegsOvly;
* Register Overlay Structure for PARAMENTRY
\**************************************************************************/
typedef struct {
- volatile unsigned int OPT;
- volatile unsigned int SRC;
- volatile unsigned int A_B_CNT;
- volatile unsigned int DST;
- volatile unsigned int SRC_DST_BIDX;
- volatile unsigned int LINK_BCNTRLD;
- volatile unsigned int SRC_DST_CIDX;
- volatile unsigned int CCNT;
+ volatile uint32_t OPT;
+ volatile uint32_t SRC;
+ volatile uint32_t A_B_CNT;
+ volatile uint32_t DST;
+ volatile uint32_t SRC_DST_BIDX;
+ volatile uint32_t LINK_BCNTRLD;
+ volatile uint32_t SRC_DST_CIDX;
+ volatile uint32_t CCNT;
} EDMA3_CCRL_ParamentryRegs;
typedef volatile EDMA3_CCRL_ParamentryRegs *EDMA3_CCRL_ParamentryRegsOvly;
* Register Overlay Structure
\**************************************************************************/
typedef struct {
- volatile unsigned int REV;
- volatile unsigned int CCCFG;
- volatile unsigned char RSVD0[248];
- volatile unsigned int DCHMAP[64];
- volatile unsigned int QCHMAP[8];
- volatile unsigned char RSVD1[32];
- volatile unsigned int DMAQNUM[8];
- volatile unsigned int QDMAQNUM;
- volatile unsigned char RSVD2[28];
- volatile unsigned int QUETCMAP;
- volatile unsigned int QUEPRI;
- volatile unsigned char RSVD3[120];
- volatile unsigned int EMR;
- volatile unsigned int EMRH;
- volatile unsigned int EMCR;
- volatile unsigned int EMCRH;
- volatile unsigned int QEMR;
- volatile unsigned int QEMCR;
- volatile unsigned int CCERR;
- volatile unsigned int CCERRCLR;
- volatile unsigned int EEVAL;
- volatile unsigned char RSVD4[28];
+ volatile uint32_t REV;
+ volatile uint32_t CCCFG;
+ volatile uint8_t RSVD0[248];
+ volatile uint32_t DCHMAP[64];
+ volatile uint32_t QCHMAP[8];
+ volatile uint8_t RSVD1[32];
+ volatile uint32_t DMAQNUM[8];
+ volatile uint32_t QDMAQNUM;
+ volatile uint8_t RSVD2[28];
+ volatile uint32_t QUETCMAP;
+ volatile uint32_t QUEPRI;
+ volatile uint8_t RSVD3[120];
+ volatile uint32_t EMR;
+ volatile uint32_t EMRH;
+ volatile uint32_t EMCR;
+ volatile uint32_t EMCRH;
+ volatile uint32_t QEMR;
+ volatile uint32_t QEMCR;
+ volatile uint32_t CCERR;
+ volatile uint32_t CCERRCLR;
+ volatile uint32_t EEVAL;
+ volatile uint8_t RSVD4[28];
EDMA3_CCRL_DraRegs DRA[8];
- volatile unsigned int QRAE[8];
- volatile unsigned char RSVD5[96];
+ volatile uint32_t QRAE[8];
+ volatile uint8_t RSVD5[96];
EDMA3_CCRL_QueevtentryRegs QUEEVTENTRY[8][16];
- volatile unsigned int QSTAT[8];
- volatile unsigned int QWMTHRA;
- volatile unsigned int QWMTHRB;
- volatile unsigned char RSVD6[24];
- volatile unsigned int CCSTAT;
- volatile unsigned char RSVD7[188];
- volatile unsigned int AETCTL;
- volatile unsigned int AETSTAT;
- volatile unsigned int AETCMD;
- volatile unsigned char RSVD8[244];
- volatile unsigned int MPFAR;
- volatile unsigned int MPFSR;
- volatile unsigned int MPFCR;
- volatile unsigned int MPPAG;
- volatile unsigned int MPPA[8];
- volatile unsigned char RSVD9[2000];
- volatile unsigned int ER;
- volatile unsigned int ERH;
- volatile unsigned int ECR;
- volatile unsigned int ECRH;
- volatile unsigned int ESR;
- volatile unsigned int ESRH;
- volatile unsigned int CER;
- volatile unsigned int CERH;
- volatile unsigned int EER;
- volatile unsigned int EERH;
- volatile unsigned int EECR;
- volatile unsigned int EECRH;
- volatile unsigned int EESR;
- volatile unsigned int EESRH;
- volatile unsigned int SER;
- volatile unsigned int SERH;
- volatile unsigned int SECR;
- volatile unsigned int SECRH;
- volatile unsigned char RSVD10[8];
- volatile unsigned int IER;
- volatile unsigned int IERH;
- volatile unsigned int IECR;
- volatile unsigned int IECRH;
- volatile unsigned int IESR;
- volatile unsigned int IESRH;
- volatile unsigned int IPR;
- volatile unsigned int IPRH;
- volatile unsigned int ICR;
- volatile unsigned int ICRH;
- volatile unsigned int IEVAL;
- volatile unsigned char RSVD11[4];
- volatile unsigned int QER;
- volatile unsigned int QEER;
- volatile unsigned int QEECR;
- volatile unsigned int QEESR;
- volatile unsigned int QSER;
- volatile unsigned int QSECR;
- volatile unsigned char RSVD12[3944];
+ volatile uint32_t QSTAT[8];
+ volatile uint32_t QWMTHRA;
+ volatile uint32_t QWMTHRB;
+ volatile uint8_t RSVD6[24];
+ volatile uint32_t CCSTAT;
+ volatile uint8_t RSVD7[188];
+ volatile uint32_t AETCTL;
+ volatile uint32_t AETSTAT;
+ volatile uint32_t AETCMD;
+ volatile uint8_t RSVD8[244];
+ volatile uint32_t MPFAR;
+ volatile uint32_t MPFSR;
+ volatile uint32_t MPFCR;
+ volatile uint32_t MPPAG;
+ volatile uint32_t MPPA[8];
+ volatile uint8_t RSVD9[2000];
+ volatile uint32_t ER;
+ volatile uint32_t ERH;
+ volatile uint32_t ECR;
+ volatile uint32_t ECRH;
+ volatile uint32_t ESR;
+ volatile uint32_t ESRH;
+ volatile uint32_t CER;
+ volatile uint32_t CERH;
+ volatile uint32_t EER;
+ volatile uint32_t EERH;
+ volatile uint32_t EECR;
+ volatile uint32_t EECRH;
+ volatile uint32_t EESR;
+ volatile uint32_t EESRH;
+ volatile uint32_t SER;
+ volatile uint32_t SERH;
+ volatile uint32_t SECR;
+ volatile uint32_t SECRH;
+ volatile uint8_t RSVD10[8];
+ volatile uint32_t IER;
+ volatile uint32_t IERH;
+ volatile uint32_t IECR;
+ volatile uint32_t IECRH;
+ volatile uint32_t IESR;
+ volatile uint32_t IESRH;
+ volatile uint32_t IPR;
+ volatile uint32_t IPRH;
+ volatile uint32_t ICR;
+ volatile uint32_t ICRH;
+ volatile uint32_t IEVAL;
+ volatile uint8_t RSVD11[4];
+ volatile uint32_t QER;
+ volatile uint32_t QEER;
+ volatile uint32_t QEECR;
+ volatile uint32_t QEESR;
+ volatile uint32_t QSER;
+ volatile uint32_t QSECR;
+ volatile uint8_t RSVD12[3944];
EDMA3_CCRL_ShadowRegs SHADOW[8];
- volatile unsigned char RSVD13[4096];
+ volatile uint8_t RSVD13[4096];
EDMA3_CCRL_ParamentryRegs PARAMENTRY[512];
} EDMA3_CCRL_Regs;
diff --git a/packages/ti/sdo/edma3/rm/src/edma3_rl_tc.h b/packages/ti/sdo/edma3/rm/src/edma3_rl_tc.h
index 0e6cb91a5d650e5dfdb0296d7e8ea71c45c826d2..71733f1e3fbcef667b60b5df3c381d76792b6d5e 100644 (file)
* Register Overlay Structure for DFIREG
\**************************************************************************/
typedef struct {
- volatile unsigned int DFOPT;
- volatile unsigned int DFSRC;
- volatile unsigned int DFCNT;
- volatile unsigned int DFDST;
- volatile unsigned int DFBIDX;
- volatile unsigned int DFMPPRXY;
- volatile unsigned char RSVD0[40];
+ volatile uint32_t DFOPT;
+ volatile uint32_t DFSRC;
+ volatile uint32_t DFCNT;
+ volatile uint32_t DFDST;
+ volatile uint32_t DFBIDX;
+ volatile uint32_t DFMPPRXY;
+ volatile uint8_t RSVD0[40];
} EDMA3_TCRL_DfiregRegs;
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
- volatile unsigned int REV;
- volatile unsigned int TCCFG;
- volatile unsigned char RSVD0[248];
- volatile unsigned int TCSTAT;
- volatile unsigned int INTSTAT;
- volatile unsigned int INTEN;
- volatile unsigned int INTCLR;
- volatile unsigned int INTCMD;
- volatile unsigned char RSVD1[12];
- volatile unsigned int ERRSTAT;
- volatile unsigned int ERREN;
- volatile unsigned int ERRCLR;
- volatile unsigned int ERRDET;
- volatile unsigned int ERRCMD;
- volatile unsigned char RSVD2[12];
- volatile unsigned int RDRATE;
- volatile unsigned char RSVD3[188];
- volatile unsigned int POPT;
- volatile unsigned int PSRC;
- volatile unsigned int PCNT;
- volatile unsigned int PDST;
- volatile unsigned int PBIDX;
- volatile unsigned int PMPPRXY;
- volatile unsigned char RSVD4[40];
- volatile unsigned int SAOPT;
- volatile unsigned int SASRC;
- volatile unsigned int SACNT;
- volatile unsigned int SADST;
- volatile unsigned int SABIDX;
- volatile unsigned int SAMPPRXY;
- volatile unsigned int SACNTRLD;
- volatile unsigned int SASRCBREF;
- volatile unsigned int SADSTBREF;
- volatile unsigned char RSVD5[28];
- volatile unsigned int DFCNTRLD;
- volatile unsigned int DFSRCBREF;
- volatile unsigned int DFDSTBREF;
- volatile unsigned char RSVD6[116];
+ volatile uint32_t REV;
+ volatile uint32_t TCCFG;
+ volatile uint8_t RSVD0[248];
+ volatile uint32_t TCSTAT;
+ volatile uint32_t INTSTAT;
+ volatile uint32_t INTEN;
+ volatile uint32_t INTCLR;
+ volatile uint32_t INTCMD;
+ volatile uint8_t RSVD1[12];
+ volatile uint32_t ERRSTAT;
+ volatile uint32_t ERREN;
+ volatile uint32_t ERRCLR;
+ volatile uint32_t ERRDET;
+ volatile uint32_t ERRCMD;
+ volatile uint8_t RSVD2[12];
+ volatile uint32_t RDRATE;
+ volatile uint8_t RSVD3[188];
+ volatile uint32_t POPT;
+ volatile uint32_t PSRC;
+ volatile uint32_t PCNT;
+ volatile uint32_t PDST;
+ volatile uint32_t PBIDX;
+ volatile uint32_t PMPPRXY;
+ volatile uint8_t RSVD4[40];
+ volatile uint32_t SAOPT;
+ volatile uint32_t SASRC;
+ volatile uint32_t SACNT;
+ volatile uint32_t SADST;
+ volatile uint32_t SABIDX;
+ volatile uint32_t SAMPPRXY;
+ volatile uint32_t SACNTRLD;
+ volatile uint32_t SASRCBREF;
+ volatile uint32_t SADSTBREF;
+ volatile uint8_t RSVD5[28];
+ volatile uint32_t DFCNTRLD;
+ volatile uint32_t DFSRCBREF;
+ volatile uint32_t DFDSTBREF;
+ volatile uint8_t RSVD6[116];
EDMA3_TCRL_DfiregRegs DFIREG[4];
} EDMA3_TCRL_Regs;
diff --git a/packages/ti/sdo/edma3/rm/src/edma3_rm_gbl_data.c b/packages/ti/sdo/edma3/rm/src/edma3_rm_gbl_data.c
index 2fe7dc2360bc5bf66fb4aca41d36105dfe042f52..5920b187b55083d6f514b309ed7ab4f96a377e7e 100755 (executable)
/* This #define is needed for array declarations. */
#define MAX_EDMA3_RM_INSTANCES (8u)
/* This const is required to access this constant in other header files */
-const unsigned int EDMA3_MAX_RM_INSTANCES = 8u;
+const uint32_t EDMA3_MAX_RM_INSTANCES = 8u;
/**
* \brief Region Specific Configuration structure for
diff --git a/packages/ti/sdo/edma3/rm/src/edma3resmgr.c b/packages/ti/sdo/edma3/rm/src/edma3resmgr.c
index 8edab241f010c27cc9ca013e8882df0c9a1463bc..eff554b8fbf7d48e1de89bfc9cc5870e0a902040 100755 (executable)
/**
* Maximum Resource Manager Instances supported by the EDMA3 Package.
*/
-extern const unsigned int EDMA3_MAX_RM_INSTANCES;
+extern const uint32_t EDMA3_MAX_RM_INSTANCES;
#ifndef GENERIC
extern EDMA3_RM_Instance *ptrRMIArray;
/** Max of DMA Channels */
-unsigned int edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_dma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
/** Min of Link Channels */
-unsigned int edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_link_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
/** Max of Link Channels */
-unsigned int edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_link_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
/** Min of QDMA Channels */
-unsigned int edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_qdma_ch_min_val[EDMA3_MAX_EDMA3_INSTANCES];
/** Max of QDMA Channels */
-unsigned int edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_qdma_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
/** Max of Logical Channels */
-unsigned int edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
+uint32_t edma3_log_ch_max_val[EDMA3_MAX_EDMA3_INSTANCES];
/* Globals */
/*---------------------------------------------------------------------------*/
* scenario, this DMA channel <-> TCC mapping will be used to point to
* the correct callback function.
*/
-static unsigned int edma3DmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_DMA_CH];
+static uint32_t edma3DmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_DMA_CH];
/**
@@ -184,7 +184,7 @@ static unsigned int edma3DmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_D
* scenario, this QDMA channel <-> TCC mapping will be used to point to
* the correct callback function.
*/
-static unsigned int edma3QdmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_QDMA_CH];
+static uint32_t edma3QdmaChTccMapping [EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_QDMA_CH];
/**
* masterExists[] is per EDMA3 hardware, hence it is created
* as an array.
*/
-static unsigned int masterExists [EDMA3_MAX_EDMA3_INSTANCES] = {FALSE,FALSE,FALSE};
+static uint32_t masterExists [EDMA3_MAX_EDMA3_INSTANCES] = {FALSE,FALSE,FALSE};
/**
* Number of PaRAM Sets actually present on the SoC. This will be updated
* while creating the Resource Manager Object.
*/
-unsigned int edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS;
+uint32_t edma3NumPaRAMSets = EDMA3_MAX_PARAM_SETS;
/**
* The list of Interrupt Channels which get allocated while requesting the
* TCC. It will be used while checking the IPR/IPRH bits in the RM ISR.
*/
-static unsigned int allocatedTCCs[EDMA3_MAX_EDMA3_INSTANCES][2u] =
+static uint32_t allocatedTCCs[EDMA3_MAX_EDMA3_INSTANCES][2u] =
{
{0x0u, 0x0u},
{0x0u, 0x0u},
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
-static unsigned int contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u};
+static uint32_t contiguousDmaRes[EDMA3_MAX_DMA_CHAN_DWRDS] = {0x0u, 0x0u};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
-static unsigned int contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u};
+static uint32_t contiguousQdmaRes[EDMA3_MAX_QDMA_CHAN_DWRDS] = {0x0u};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
-static unsigned int contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u};
+static uint32_t contiguousTccRes[EDMA3_MAX_TCC_DWRDS] = {0x0u, 0x0u};
/**
* Arrays ownDmaChannels[], resvdDmaChannels and avlblDmaChannels will be ANDed
* and stored in this array. It will be referenced in
* EDMA3_RM_allocContiguousResource () to look for contiguous resources.
*/
-static unsigned int contiguousParamRes[EDMA3_MAX_PARAM_DWRDS];
+static uint32_t contiguousParamRes[EDMA3_MAX_PARAM_DWRDS];
/**
@@ -277,21 +277,21 @@ static EDMA3_RM_ChBoundResources edma3RmChBoundRes [EDMA3_MAX_EDMA3_INSTANCES][E
/* Local functions prototypes */
/*---------------------------------------------------------------------------*/
/** EDMA3 Instance 0 Completion Handler Interrupt Service Routine */
-void lisrEdma3ComplHandler0(unsigned int arg);
+void lisrEdma3ComplHandler0(uint32_t arg);
/** EDMA3 Instance 0 CC Error Interrupt Service Routine */
-void lisrEdma3CCErrHandler0(unsigned int arg);
+void lisrEdma3CCErrHandler0(uint32_t arg);
/**
* EDMA3 Instance 0 TC[0-7] Error Interrupt Service Routines
* for a maximum of 8 TCs (Transfer Controllers).
*/
-void lisrEdma3TC0ErrHandler0(unsigned int arg);
-void lisrEdma3TC1ErrHandler0(unsigned int arg);
-void lisrEdma3TC2ErrHandler0(unsigned int arg);
-void lisrEdma3TC3ErrHandler0(unsigned int arg);
-void lisrEdma3TC4ErrHandler0(unsigned int arg);
-void lisrEdma3TC5ErrHandler0(unsigned int arg);
-void lisrEdma3TC6ErrHandler0(unsigned int arg);
-void lisrEdma3TC7ErrHandler0(unsigned int arg);
+void lisrEdma3TC0ErrHandler0(uint32_t arg);
+void lisrEdma3TC1ErrHandler0(uint32_t arg);
+void lisrEdma3TC2ErrHandler0(uint32_t arg);
+void lisrEdma3TC3ErrHandler0(uint32_t arg);
+void lisrEdma3TC4ErrHandler0(uint32_t arg);
+void lisrEdma3TC5ErrHandler0(uint32_t arg);
+void lisrEdma3TC6ErrHandler0(uint32_t arg);
+void lisrEdma3TC7ErrHandler0(uint32_t arg);
/** Interrupt Handler for the Transfer Completion interrupt */
/** Interrupt Handler for the Channel Controller Error interrupt */
static void edma3CCErrHandler (const EDMA3_RM_Obj *rmObj);
/** Interrupt Handler for the Transfer Controller Error interrupt */
-static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum);
+static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, uint32_t tcNum);
/** Local MemZero function */
-void edma3MemZero(void *dst, unsigned int len);
+void edma3MemZero(void *dst, uint32_t len);
/** Local MemCpy function */
-void edma3MemCpy(void *dst, const void *src, unsigned int len);
+void edma3MemCpy(void *dst, const void *src, uint32_t len);
/* Local MemCopy function to copy Param Set ONLY */
void edma3ParamCpy(void *dst, const void *src);
/** Initialization of the Global region registers of the EDMA3 Controller */
-static void edma3GlobalRegionInit (unsigned int phyCtrllerInstId);
+static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId);
/** Initialization of the Shadow region registers of the EDMA3 Controller */
static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance);
* Finds a particular bit ('0' or '1') in the particular word from 'start'.
* If found, returns the position, else return -1.
*/
-static int findBitInWord (int source, unsigned int start, unsigned short bit);
+static int32_t findBitInWord (int32_t source, uint32_t start, uint16_t bit);
/**
* Finds a particular bit ('0' or '1') in the specified resources' array
* from 'start' to 'end'. If found, returns the position, else return -1.
*/
-static int findBit (EDMA3_RM_ResType resType,
- unsigned int start,
- unsigned int end,
- unsigned short bit);
+static int32_t findBit (EDMA3_RM_ResType resType,
+ uint32_t start,
+ uint32_t end,
+ uint16_t bit);
/**
* If successful, this function returns EDMA3_RM_SOK and the position
* of first available resource in 'positionRes'. Else returns error.
*/
static EDMA3_RM_Result allocAnyContigRes(EDMA3_RM_ResType resType,
- unsigned int numResources,
- unsigned int *positionRes);
+ uint32_t numResources,
+ uint32_t *positionRes);
/**
* Starting from 'firstResIdObj', this function makes the next 'numResources'
*/
static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,
const EDMA3_RM_ResDesc *firstResIdObj,
- unsigned int numResources);
+ uint32_t numResources);
/*---------------------------------------------------------------------------*/
-EDMA3_RM_Result EDMA3_RM_create (unsigned int phyCtrllerInstId,
+EDMA3_RM_Result EDMA3_RM_create (uint32_t phyCtrllerInstId,
const EDMA3_RM_GblConfigParams *gblCfgParams,
const void *miscParam)
{
- unsigned int count = 0u;
+ uint32_t count = 0u;
EDMA3_RM_Result result = EDMA3_RM_SOK;
/**
* Used to reset the Internal EDMA3 Resource Manager Data Structures for the first time.
return result;
}
-EDMA3_RM_Result EDMA3_RM_delete (unsigned int phyCtrllerInstId,
+EDMA3_RM_Result EDMA3_RM_delete (uint32_t phyCtrllerInstId,
const void *param)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
return result;
}
-EDMA3_RM_Handle EDMA3_RM_open (unsigned int phyCtrllerInstId,
+EDMA3_RM_Handle EDMA3_RM_open (uint32_t phyCtrllerInstId,
const EDMA3_RM_Param *initParam,
EDMA3_RM_Result *errorCode)
{
- unsigned int intState = 0u;
- unsigned int resMgrIdx = 0u;
+ uint32_t intState = 0u;
+ uint32_t resMgrIdx = 0u;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Instance *temp_ptr_rm_inst = NULL;
EDMA3_RM_Handle retVal = NULL;
- unsigned int dmaChDwrds = 0u;
- unsigned int paramSetDwrds = 0u;
- unsigned int tccDwrds = 0u;
+ uint32_t dmaChDwrds = 0u;
+ uint32_t paramSetDwrds = 0u;
+ uint32_t tccDwrds = 0u;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
#ifdef GENERIC
const void *param)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
- unsigned int intState = 0u;
- unsigned int resMgrIdx = 0u;
+ uint32_t intState = 0u;
+ uint32_t resMgrIdx = 0u;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Instance *rmInstance = NULL;
- unsigned int dmaChDwrds;
- unsigned int paramSetDwrds;
- unsigned int tccDwrds;
+ uint32_t dmaChDwrds;
+ uint32_t paramSetDwrds;
+ uint32_t tccDwrds;
/*to remove CCS remark: parameter "param" was never referenced */
(void)param;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Result semResult = EDMA3_RM_SOK;
- unsigned int avlblIdx = 0u;
- unsigned int resIdClr = 0x0;
- unsigned int resIdSet = 0x0;
- unsigned int resId;
+ uint32_t avlblIdx = 0u;
+ uint32_t resIdClr = 0x0;
+ uint32_t resIdSet = 0x0;
+ uint32_t resId;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
- unsigned int mapXbarEvtToChanFlag = FALSE;
- unsigned int xBarEvtBeforeMap = 0;
- unsigned int edma3Id;
+ uint32_t mapXbarEvtToChanFlag = FALSE;
+ uint32_t xBarEvtBeforeMap = 0;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
edma3Id = rmObj->phyCtrllerInstId;
resId = resObj->resId;
- resIdClr = (unsigned int)(~(1u << (resId%32u)));
+ resIdClr = (uint32_t)(~(1u << (resId%32u)));
resIdSet = (1u << (resId%32u));
if ( rmInstance->mapXbarToChan != NULL)
* Mark the 'match found' resource as "Not Available"
* for future requests
*/
- rmInstance->avlblDmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblDmaChannels[avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
/**
* Check if the register modification flag is
(1u << (avlblIdx%32u))) != FALSE)
{
resObj->resId = avlblIdx;
- rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
/**
* Check if the register modification flag is
& (1u << (avlblIdx%32u)))!=FALSE)
{
resObj->resId = avlblIdx;
- rmInstance->avlblTccs [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblTccs [avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
/**
* Check if the register modification flag is
(1u << (avlblIdx%32u)))!=FALSE)
{
resObj->resId = avlblIdx;
- rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
/**
* Also, make the actual PARAM Set NULL, checking the flag
EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr,
const EDMA3_RM_ResDesc *resObj)
{
- unsigned int intState;
+ uint32_t intState;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
- unsigned int resId;
- unsigned int resIdSet = 0x0;
+ uint32_t resId;
+ uint32_t resIdSet = 0x0;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *lChObj,
- unsigned int *pParam,
- unsigned int *pTcc)
+ uint32_t *pParam,
+ uint32_t *pTcc)
{
EDMA3_RM_ResDesc *chObj;
EDMA3_RM_ResDesc resObj;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- unsigned int mappedPaRAMId=0u;
- unsigned int mappedTcc = EDMA3_RM_CH_NO_TCC_MAP;
- int paRAMId = (int)EDMA3_RM_RES_ANY;
+ uint32_t mappedPaRAMId=0u;
+ uint32_t mappedTcc = EDMA3_RM_CH_NO_TCC_MAP;
+ int32_t paRAMId = (int32_t)EDMA3_RM_RES_ANY;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
- unsigned int qdmaChId = EDMA3_MAX_PARAM_SETS;
- unsigned int edma3Id;
+ uint32_t qdmaChId = EDMA3_MAX_PARAM_SETS;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
/** If some PaRAM set is statically mapped to the returned
* channel number, use that.
*/
- paRAMId = (int)mappedPaRAMId;
+ paRAMId = (int32_t)mappedPaRAMId;
}
}
else
/* User specified some PaRAM Set; check that can be used or not. */
if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)
{
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
else
{
}
else
{
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
}
}
/** If some PaRAM set is statically mapped to the returned
* channel number, use that.
*/
- paRAMId = (int)mappedPaRAMId;
+ paRAMId = (int32_t)mappedPaRAMId;
}
}
else
/* User specified some PaRAM Set; check that can be used or not. */
if (TRUE == rmObj->gblCfgParams.dmaChPaRAMMapExists)
{
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
else
{
}
else
{
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
}
}
if ((*pParam) != EDMA3_RM_PARAM_ANY)
{
/* User specified ANY PaRAM Set; Check the mapping. */
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
}
}
if ((*pParam) != EDMA3_RM_PARAM_ANY)
{
/* User specified ANY PaRAM Set; Check the mapping. */
- paRAMId = (int)(*pParam);
+ paRAMId = (int32_t)(*pParam);
}
}
}
|| (chObj->resId == EDMA3_RM_RES_ANY))
{
/* Request for ANY LINK channel. */
- paRAMId = (int)EDMA3_RM_RES_ANY;
+ paRAMId = (int32_t)EDMA3_RM_RES_ANY;
}
else
{
if (chObj->resId < edma3NumPaRAMSets)
{
/* Request for a Specific LINK channel. */
- paRAMId = (int)(chObj->resId);
+ paRAMId = (int32_t)(chObj->resId);
}
else
{
{
/* Try to allocate the link channel */
resObj.type = EDMA3_RM_RES_PARAM_SET;
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
if (result == EDMA3_RM_SOK)
{
- unsigned int linkCh = edma3_link_ch_min_val[edma3Id];
+ uint32_t linkCh = edma3_link_ch_min_val[edma3Id];
/* Return the actual PaRAM Id. */
chObj->resId = resObj.resId;
else
{
/* Save the PaRAM Id for the Link Channel. */
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId = (int)(chObj->resId);
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][linkCh].paRAMId = (int32_t)(chObj->resId);
/**
* Remove any linking. Before doing that, check
if (TRUE == rmInstance->regModificationRequired)
{
*((&gblRegs->PARAMENTRY[chObj->resId].OPT)
- + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
}
}
}
/* First allocate a PaRAM Set */
resObj.type = EDMA3_RM_RES_PARAM_SET;
/* Use the saved param id now. */
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
if (result == EDMA3_RM_SOK)
{
* Save the PaRAM Set first.
*/
*pParam = resObj.resId;
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].paRAMId = (int)(resObj.resId);
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][chObj->resId].paRAMId = (int32_t)(resObj.resId);
/* Allocate the TCC now. */
resObj.type = EDMA3_RM_RES_TCC;
/* Remove any linking */
*((&gblRegs->PARAMENTRY[*pParam].OPT)
- + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
}
}
else
/* First allocate a PaRAM Set */
resObj.type = EDMA3_RM_RES_PARAM_SET;
/* Use the saved param id now. */
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
result = EDMA3_RM_allocResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
if (result == EDMA3_RM_SOK)
{
* Save the PaRAM Set first.
*/
*pParam = resObj.resId;
- edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = (int)(resObj.resId);
+ edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId = (int32_t)(resObj.resId);
/* Allocate the TCC now. */
resObj.type = EDMA3_RM_RES_TCC;
/* Remove any linking */
*((&gblRegs->PARAMENTRY[*pParam].OPT)
- + (unsigned int)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
+ + (uint32_t)EDMA3_RM_PARAM_ENTRY_LINK_BCNTRLD) = 0xFFFFu;
/* Enable the transfer also. */
rmInstance->shadowRegs->QEESR = (1u << chObj->resId);
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int paRAMId;
- unsigned int tcc;
+ int32_t paRAMId;
+ uint32_t tcc;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int qdmaChId;
- unsigned int dmaChId;
+ uint32_t qdmaChId;
+ uint32_t dmaChId;
EDMA3_RM_InstanceInitConfig *rmConfig = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
/* Free the PaRAM Set Now. */
paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][dmaChId].paRAMId;
resObj.type = EDMA3_RM_RES_PARAM_SET;
- resObj.resId = (unsigned int)paRAMId;
+ resObj.resId = (uint32_t)paRAMId;
result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
}
else
/* Free the PaRAM Set now */
paRAMId = edma3RmChBoundRes[rmObj->phyCtrllerInstId][qdmaChId].paRAMId;
resObj.type = EDMA3_RM_RES_PARAM_SET;
- resObj.resId = (int)paRAMId;
+ resObj.resId = (int32_t)paRAMId;
result = EDMA3_RM_freeResource(hEdmaResMgr, (EDMA3_RM_ResDesc *)&resObj);
}
else
if (result == EDMA3_RM_SOK)
{
/* PaRAM Set freed successfully. */
- unsigned int linkCh = edma3_link_ch_min_val[edma3Id];
+ uint32_t linkCh = edma3_link_ch_min_val[edma3Id];
/* Reset the Logical-Link channel */
/* Search for the Logical-Link channel first */
}
EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int channelId,
- unsigned int paRAMId)
+ uint32_t channelId,
+ uint32_t paRAMId)
{
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
}
EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int channelId,
- unsigned int paRAMId,
+ uint32_t channelId,
+ uint32_t paRAMId,
EDMA3_RM_QdmaTrigWord trigWord)
{
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr,
const EDMA3_RM_ResDesc *channelObj,
- unsigned int tcc,
+ uint32_t tcc,
EDMA3_RM_TccCallback tccCb,
void *cbData)
{
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
- unsigned int edma3Id;
+ uint32_t edma3Id;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
- unsigned int mappedTcc = EDMA3_MAX_TCC;
- unsigned int edma3Id;
+ uint32_t mappedTcc = EDMA3_MAX_TCC;
+ uint32_t edma3Id;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *firstResIdObj,
- unsigned int numResources)
+ uint32_t numResources)
{
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_ResDesc *resObj = NULL;
- unsigned int resAllocIdx = 0u;
- unsigned int firstResId;
- unsigned int lastResId = 0u;
- unsigned int maxNumResources = 0u;
+ uint32_t resAllocIdx = 0u;
+ uint32_t firstResId;
+ uint32_t lastResId = 0u;
+ uint32_t maxNumResources = 0u;
EDMA3_RM_Result semResult = EDMA3_RM_SOK;
- unsigned int resIdClr = 0x0;
- unsigned int resIdSet = 0x0;
+ uint32_t resIdClr = 0x0;
+ uint32_t resIdSet = 0x0;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
- unsigned int i = 0u;
- unsigned int position = 0u;
- unsigned int edma3Id;
+ uint32_t i = 0u;
+ uint32_t position = 0u;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u)));
+ resIdClr = (uint32_t)(~(1u << (resAllocIdx%32u)));
resIdSet = (1u << (resAllocIdx%32u));
/* Check whether it is owned or not */
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (unsigned int)(~(1u << resAllocIdx));
+ resIdClr = (uint32_t)(~(1u << resAllocIdx));
resIdSet = (1u << resAllocIdx);
/* Check whether it is owned or not */
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u)));
+ resIdClr = (uint32_t)(~(1u << (resAllocIdx%32u)));
resIdSet = (1u << (resAllocIdx%32u));
/* Check whether it is owned or not */
{
for (resAllocIdx = firstResId; resAllocIdx < lastResId; ++resAllocIdx)
{
- resIdClr = (unsigned int)(~(1u << (resAllocIdx%32u)));
+ resIdClr = (uint32_t)(~(1u << (resAllocIdx%32u)));
resIdSet = (1u << (resAllocIdx%32u));
/* Check whether it is owned or not */
@@ -3876,16 +3876,16 @@ EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *firstResIdObj,
- unsigned int numResources)
+ uint32_t numResources)
{
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_ResDesc *resObj;
- unsigned int resFreeIdx = 0u;
- unsigned int firstResId;
- unsigned int lastResId;
- unsigned int maxNumResources = 0u;
+ uint32_t resFreeIdx = 0u;
+ uint32_t firstResId;
+ uint32_t lastResId;
+ uint32_t maxNumResources = 0u;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
@@ -3976,13 +3976,13 @@ EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
}
EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int regOffset,
- unsigned int newRegValue)
+ uint32_t regOffset,
+ uint32_t newRegValue)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- volatile unsigned int regPhyAddr = 0x0u;
+ volatile uint32_t regPhyAddr = 0x0u;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
if (EDMA3_RM_SOK == result)
{
/* Semaphore taken successfully, modify the registers. */
- regPhyAddr = (unsigned int)(rmObj->gblCfgParams.globalRegs) + regOffset;
+ regPhyAddr = (uint32_t)(rmObj->gblCfgParams.globalRegs) + regOffset;
- *(unsigned int *)regPhyAddr = newRegValue;
+ *(uint32_t *)regPhyAddr = newRegValue;
/* Return the semaphore back */
result = edma3OsSemGive(rmInstance->initParam.rmSemHandle);
}
EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int regOffset,
- unsigned int *regValue)
+ uint32_t regOffset,
+ uint32_t *regValue)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- volatile unsigned int regPhyAddr = 0x0u;
+ volatile uint32_t regPhyAddr = 0x0u;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
{
if (rmObj->gblCfgParams.globalRegs != NULL)
{
- regPhyAddr = (unsigned int)(rmObj->gblCfgParams.globalRegs) + regOffset;
+ regPhyAddr = (uint32_t)(rmObj->gblCfgParams.globalRegs) + regOffset;
- *regValue = *(unsigned int *)regPhyAddr;
+ *regValue = *(uint32_t *)regPhyAddr;
}
}
}
}
EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int tccNo)
+ uint32_t tccNo)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- unsigned int tccBitMask = 0x0u;
+ uint32_t tccBitMask = 0x0u;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
}
EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
- unsigned int tccNo,
- unsigned short *tccStatus)
+ uint32_t tccNo,
+ uint16_t *tccStatus)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- unsigned int tccBitMask = 0x0u;
+ uint32_t tccBitMask = 0x0u;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int paRAMId = 0u;
- unsigned int qdmaChId = 0u;
+ int32_t paRAMId = 0u;
+ uint32_t qdmaChId = 0u;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
* User has passed the actual param set value here.
* Use this value only
*/
- paRAMId = (int)(lChObj->resId);
+ paRAMId = (int32_t)(lChObj->resId);
}
else
{
if (result == EDMA3_RM_SOK)
{
/* Check the param id first. */
- if ((paRAMId != -1) && ((unsigned int)paRAMId < edma3NumPaRAMSets))
+ if ((paRAMId != -1) && ((uint32_t)paRAMId < edma3NumPaRAMSets))
{
/* Set the PaRAM Set now. */
edma3ParamCpy ((void *)(&(globalRegs->PARAMENTRY[paRAMId].OPT)),
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int paRAMId = 0u;
- unsigned int qdmaChId = 0u;
+ int32_t paRAMId = 0u;
+ uint32_t qdmaChId = 0u;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
* User has passed the actual param set value here.
* Use this value only
*/
- paRAMId = (int)(lChObj->resId);
+ paRAMId = (int32_t)(lChObj->resId);
}
else
{
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_ResDesc *lChObj,
- unsigned int *paramPhyAddr)
+ uint32_t *paramPhyAddr)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- int paRAMId = 0u;
- unsigned int qdmaChId = 0u;
+ int32_t paRAMId = 0u;
+ uint32_t qdmaChId = 0u;
volatile EDMA3_CCRL_Regs *globalRegs = NULL;
- unsigned int edma3Id;
+ uint32_t edma3Id;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
* User has passed the actual param set value here.
* Use this value only
*/
- paRAMId = (int)(lChObj->resId);
+ paRAMId = (int32_t)(lChObj->resId);
}
else
{
if ((paRAMId != -1) && (paRAMId < edma3NumPaRAMSets))
{
/* Get the PaRAM Set Address now. */
- *paramPhyAddr = (unsigned int)(&(globalRegs->PARAMENTRY [paRAMId].OPT));
+ *paramPhyAddr = (uint32_t)(&(globalRegs->PARAMENTRY [paRAMId].OPT));
}
else
{
EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr,
EDMA3_RM_Cntrlr_PhyAddr controllerId,
- unsigned int *phyAddress)
+ uint32_t *phyAddress)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
if (controllerId == EDMA3_RM_CC_PHY_ADDR)
{
/* EDMA3 Channel Controller Address */
- *phyAddress = (unsigned int)(rmObj->gblCfgParams.globalRegs);
+ *phyAddress = (uint32_t)(rmObj->gblCfgParams.globalRegs);
}
else
{
* Since the TCs enum start from 1, and TCs start from 0,
* subtract 1 from the enum to get the actual address.
*/
- *phyAddress = (unsigned int)(rmObj->gblCfgParams.tcRegs[controllerId-1u]);
+ *phyAddress = (uint32_t)(rmObj->gblCfgParams.tcRegs[controllerId-1u]);
}
}
}
}
EDMA3_RM_Result EDMA3_RM_getGblConfigParams (
- unsigned int phyCtrllerInstId,
+ uint32_t phyCtrllerInstId,
EDMA3_RM_GblConfigParams *gblCfgParams)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- unsigned int resMgrIdx = 0u;
- unsigned int hwId;
+ uint32_t resMgrIdx = 0u;
+ uint32_t hwId;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
EDMA3_RM_Instance *rmInstance = NULL;
- unsigned int paramInitRequired = 0xFFu;
- unsigned int regModificationRequired = 0xFFu;
- unsigned int *ret_val = NULL;
+ uint32_t paramInitRequired = 0xFFu;
+ uint32_t regModificationRequired = 0xFFu;
+ uint32_t *ret_val = NULL;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
{
case EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION:
{
- paramInitRequired = (unsigned int)cmdArg;
+ paramInitRequired = (uint32_t)cmdArg;
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
/* Check if the parameters are OK. */
if (EDMA3_RM_SOK == result)
{
- ret_val = (unsigned int *)cmdArg;
+ ret_val = (uint32_t *)cmdArg;
/* Get the flag which is being used to do the PaRAM clearing. */
*ret_val = rmInstance->paramInitRequired;
case EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION:
{
- regModificationRequired = (unsigned int)cmdArg;
+ regModificationRequired = (uint32_t)cmdArg;
/* If parameter checking is enabled... */
#ifndef EDMA3_RM_PARAM_CHECK_DISABLE
/* Check if the parameters are OK. */
if (EDMA3_RM_SOK == result)
{
- ret_val = (unsigned int *)cmdArg;
+ ret_val = (uint32_t *)cmdArg;
/**
* Get the flag which is being used to do the global
*/
static void edma3ComplHandler (const EDMA3_RM_Obj *rmObj)
{
- unsigned int Cnt;
+ uint32_t Cnt;
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- volatile unsigned int pendingIrqs;
- volatile unsigned int isIPR = 0;
+ volatile uint32_t pendingIrqs;
+ volatile uint32_t isIPR = 0;
- unsigned int indexl;
- unsigned int indexh;
- unsigned int edma3Id;
- unsigned int numTCCs;
+ uint32_t indexl;
+ uint32_t indexh;
+ uint32_t edma3Id;
+ uint32_t numTCCs;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3",
}
-void lisrEdma3ComplHandler0(unsigned int edma3InstanceId)
+void lisrEdma3ComplHandler0(uint32_t edma3InstanceId)
{
/* Invoke Completion Handler ISR */
edma3ComplHandler(&resMgrObj[edma3InstanceId]);
*/
static void edma3CCErrHandler(const EDMA3_RM_Obj *rmObj)
{
- unsigned int Cnt = 0u;
- unsigned int resMgrInstIdx = 0u;
+ uint32_t Cnt = 0u;
+ uint32_t resMgrInstIdx = 0u;
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *shadowRegs = NULL;
- volatile unsigned int pendingIrqs;
- unsigned int index;
- unsigned int evtqueNum;
+ volatile uint32_t pendingIrqs;
+ uint32_t index;
+ uint32_t evtqueNum;
EDMA3_RM_Instance *rm_instance = NULL;
- unsigned int edma3Id;
- unsigned int num_rm_instances_opened;
+ uint32_t edma3Id;
+ uint32_t num_rm_instances_opened;
EDMA3_RM_Instance *rmInstance = NULL;
- unsigned int ownedDmaError = 0;
- unsigned int ownedDmaHError = 0;
- unsigned int ownedQdmaError = 0;
+ uint32_t ownedDmaError = 0;
+ uint32_t ownedDmaHError = 0;
+ uint32_t ownedQdmaError = 0;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_CCERR",
/*Process all the pending interrupts*/
if((pendingIrqs & 1u)==TRUE)
{
- unsigned int mappedTcc = 0u;
+ uint32_t mappedTcc = 0u;
/**
* Using the 'index' value (basically the DMA
/*Process all the pending interrupts*/
if((pendingIrqs & 1u)==TRUE)
{
- unsigned int mappedTcc = 0u;
+ uint32_t mappedTcc = 0u;
/**
* Using the 'index' value (basically the DMA
/*Process all the pending interrupts*/
if((pendingIrqs & 1u)==TRUE)
{
- unsigned int mappedTcc = 0u;
+ uint32_t mappedTcc = 0u;
/**
* Using the 'index' value (basically the QDMA
#endif /* EDMA3_INSTRUMENTATION_ENABLED */
}
-void lisrEdma3CCErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3CCErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke CC Error Handler ISR */
edma3CCErrHandler(&resMgrObj[edma3InstanceId]);
*
* \return None.
*/
-static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, unsigned int tcNum)
+static void edma3TCErrHandler (const EDMA3_RM_Obj *rmObj, uint32_t tcNum)
{
volatile EDMA3_TCRL_Regs *tcRegs = NULL;
- unsigned int tcMemErrRdWr = 0u;
- unsigned int resMgrInstIdx = 0u;
+ uint32_t tcMemErrRdWr = 0u;
+ uint32_t resMgrInstIdx = 0u;
EDMA3_RM_Instance *rm_instance = NULL;
- unsigned int edma3Id;
- unsigned int num_rm_instances_opened;
+ uint32_t edma3Id;
+ uint32_t num_rm_instances_opened;
#ifdef EDMA3_INSTRUMENTATION_ENABLED
EDMA3_LOG_EVENT(&DVTEvent_Log,"EDMA3_TCERR",
* ======== lisrEdma3TC0ErrHandler0 ========
* EDMA3 instance 0 TC0 Error Interrupt Service Routine
*/
-void lisrEdma3TC0ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC0ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC0*/
edma3TCErrHandler(&resMgrObj[edma3InstanceId], 0u);
* ======== lisrEdma3TC1ErrHandler0 ========
* EDMA3 instance 0 TC1 Error Interrupt Service Routine
*/
-void lisrEdma3TC1ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC1ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC1*/
edma3TCErrHandler(&resMgrObj[edma3InstanceId], 1u);
* ======== lisrEdma3TC2ErrHandler0 ========
* EDMA3 instance 0 TC2 Error Interrupt Service Routine
*/
-void lisrEdma3TC2ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC2ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC2*/
edma3TCErrHandler(&resMgrObj[edma3InstanceId], 2u);
* ======== lisrEdma3TC3ErrHandler0 ========
* EDMA3 instance 0 TC3 Error Interrupt Service Routine
*/
-void lisrEdma3TC3ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC3ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC3*/
edma3TCErrHandler(&resMgrObj[edma3InstanceId], 3u);
* ======== lisrEdma3TC4ErrHandler0 ========
* EDMA3 instance 0 TC4 Error Interrupt Service Routine
*/
-void lisrEdma3TC4ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC4ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC4*/
edma3TCErrHandler(&resMgrObj[edma3InstanceId], 4u);
* ======== lisrEdma3TC5ErrHandler0 ========
* EDMA3 instance 0 TC5 Error Interrupt Service Routine
*/
-void lisrEdma3TC5ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC5ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC5*/
edma3TCErrHandler(&resMgrObj[edma3InstanceId], 5u);
* EDMA3 instance 0 TC6 Error Interrupt Service Routine
*/
/* ARGSUSED */
-void lisrEdma3TC6ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC6ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC6*/
edma3TCErrHandler(&resMgrObj[edma3InstanceId], 6u);
* ======== lisrEdma3TC7ErrHandler0 ========
* EDMA3 instance 0 TC7 Error Interrupt Service Routine
*/
-void lisrEdma3TC7ErrHandler0(unsigned int edma3InstanceId)
+void lisrEdma3TC7ErrHandler0(uint32_t edma3InstanceId)
{
/* Invoke Error Handler ISR for TC7*/
edma3TCErrHandler(&resMgrObj[edma3InstanceId], 7u);
/* Resource Manager Internal functions - Start */
/** Initialization of the Global region registers of the EDMA3 Controller */
-static void edma3GlobalRegionInit (unsigned int phyCtrllerInstId)
+static void edma3GlobalRegionInit (uint32_t phyCtrllerInstId)
{
- unsigned int evtQNum = 0u;
+ uint32_t evtQNum = 0u;
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
assert (phyCtrllerInstId < EDMA3_MAX_EDMA3_INSTANCES);
/** Initialization of the Shadow region registers of the EDMA3 Controller */
static void edma3ShadowRegionInit (const EDMA3_RM_Instance *pRMInstance)
{
- unsigned int intState = 0u;
+ uint32_t intState = 0u;
volatile EDMA3_CCRL_Regs *ptrEdmaccRegs = NULL;
volatile EDMA3_CCRL_ShadowRegs *ptrEdmaShadowRegs = NULL;
- unsigned int phyCtrllerInstId;
- unsigned int regionId;
+ uint32_t phyCtrllerInstId;
+ uint32_t regionId;
const EDMA3_RM_InstanceInitConfig *rmInstInitConfig = pRMInstance->initParam.rmInstInitConfig;
assert (pRMInstance != NULL);
/** Local MemZero function */
-void edma3MemZero(void *dst, unsigned int len)
+void edma3MemZero(void *dst, uint32_t len)
{
- unsigned int i = 0u;
- unsigned int *ds = NULL;
+ uint32_t i = 0u;
+ uint32_t *ds = NULL;
assert (dst != NULL);
- ds = (unsigned int *)dst;
+ ds = (uint32_t *)dst;
for (i = 0 ; i < len/4 ; i++)
{
/* Local MemCopy function */
-void edma3MemCpy(void *dst, const void *src, unsigned int len)
+void edma3MemCpy(void *dst, const void *src, uint32_t len)
{
- unsigned int i=0u;
- const unsigned int *sr;
- unsigned int *ds;
+ uint32_t i=0u;
+ const uint32_t *sr;
+ uint32_t *ds;
assert ((src != NULL) && (dst != NULL) && ((len)%4 == 0));
- sr = (const unsigned int *)src;
- ds = (unsigned int *)dst;
+ sr = (const uint32_t *)src;
+ ds = (uint32_t *)dst;
for (i = 0 ; i < len/4 ; i++)
{
/* Local MemCopy function to copy Param Set ONLY */
void edma3ParamCpy(void *dst, const void *src)
{
- unsigned int i = 0u;
- const unsigned int *sr;
- unsigned int *ds;
+ uint32_t i = 0u;
+ const uint32_t *sr;
+ uint32_t *ds;
assert ((src != NULL) && (dst != NULL));
- sr = (const unsigned int *)src;
- ds = (unsigned int *)dst;
+ sr = (const uint32_t *)src;
+ ds = (uint32_t *)dst;
for (i = 0; i < 8; i++)
{
* Finds a particular bit ('0' or '1') in the particular word from 'start'.
* If found, returns the position, else return -1.
*/
-static int findBitInWord (int source, unsigned int start, unsigned short bit)
+static int32_t findBitInWord (int32_t source, uint32_t start, uint16_t bit)
{
- unsigned int position = start;
- unsigned short found = 0;
- unsigned int iterations_left = 0;
+ uint32_t position = start;
+ uint16_t found = 0;
+ uint32_t iterations_left = 0;
switch (bit)
{
break;
}
- return (found ? (int)position : -1);
+ return (found ? (int32_t)position : -1);
}
@@ -6248,17 +6248,17 @@ static int findBitInWord (int source, unsigned int start, unsigned short bit)
* Finds a particular bit ('0' or '1') in the specified resources' array
* from 'start' to 'end'. If found, returns the position, else return -1.
*/
-static int findBit (EDMA3_RM_ResType resType,
- unsigned int start,
- unsigned int end,
- unsigned short bit)
+static int32_t findBit (EDMA3_RM_ResType resType,
+ uint32_t start,
+ uint32_t end,
+ uint16_t bit)
{
- int position = -1;
- unsigned int start_index = start / 32u;
- unsigned int end_index = end / 32u;
- int i;
- unsigned int *resPtr = 0x0;
- int ret = -1;
+ int32_t position = -1;
+ uint32_t start_index = start / 32u;
+ uint32_t end_index = end / 32u;
+ int32_t i;
+ uint32_t *resPtr = 0x0;
+ int32_t ret = -1;
EDMA3_RM_Result result = EDMA3_RM_SOK;
assert (start <= end);
else
{
/* '1' NOT found, look into other words. */
- for (i = (int)(start_index + 1u); i <= (int)(end_index - 1u); i++)
+ for (i = (int32_t)(start_index + 1u); i <= (int32_t)(end_index - 1u); i++)
{
position = findBitInWord (resPtr[i], 0u, 1u);
if (position != -1)
* of first available resource in 'positionRes'. Else returns error.
*/
static EDMA3_RM_Result allocAnyContigRes(EDMA3_RM_ResType resType,
- unsigned int numResources,
- unsigned int *positionRes)
+ uint32_t numResources,
+ uint32_t *positionRes)
{
- unsigned short found = 0u;
- int first_one, next_zero;
- unsigned int num_available;
- int ret = -1;
- unsigned int start = 0;
- unsigned int end;
+ uint16_t found = 0u;
+ int32_t first_one, next_zero;
+ uint32_t num_available;
+ int32_t ret = -1;
+ uint32_t start = 0;
+ uint32_t end;
EDMA3_RM_Result result = EDMA3_RM_SOK;
assert (positionRes != NULL);
if (found == 1u)
{
/* required resources found, retrun the first available res id. */
- *positionRes = (unsigned int)ret;
+ *positionRes = (uint32_t)ret;
}
else
{
*/
static EDMA3_RM_Result gblChngAllocContigRes(EDMA3_RM_Instance *rmInstance,
const EDMA3_RM_ResDesc *firstResIdObj,
- unsigned int numResources)
+ uint32_t numResources)
{
EDMA3_RM_Result result = EDMA3_RM_SOK;
volatile EDMA3_CCRL_Regs *gblRegs = NULL;
EDMA3_RM_Obj *rmObj = NULL;
- unsigned int avlblIdx = 0u;
- unsigned int firstResId=0u;
- unsigned int lastResId=0u;
- unsigned int edma3Id;
+ uint32_t avlblIdx = 0u;
+ uint32_t firstResId=0u;
+ uint32_t lastResId=0u;
+ uint32_t edma3Id;
assert ((rmInstance != NULL) && (firstResIdObj != NULL));
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblDmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblDmaChannels[avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
/**
* Enable the DMA channel in the DRAE/DRAEH registers also.
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblQdmaChannels[avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
/**
* Enable the QDMA channel in the QRAE register also.
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblTccs[avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblTccs[avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
/**
* If the region id coming from this
for (avlblIdx=firstResId; avlblIdx <= lastResId; ++avlblIdx)
{
- rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (unsigned int)(~(1u << (avlblIdx%32u)));
+ rmInstance->avlblPaRAMSets [avlblIdx/32u] &= (uint32_t)(~(1u << (avlblIdx%32u)));
/**
* Also, make the actual PARAM Set NULL, checking the flag