Added source files and example application project for supporting TI814X
authorVinay K Nooji <x0101786@ti.com>
Mon, 6 Sep 2010 12:48:55 +0000 (18:18 +0530)
committerSundaram Raju <sundaram@ti.com>
Tue, 7 Sep 2010 23:48:41 +0000 (05:18 +0530)
Signed-off-by: Vinay K Nooji <x0101786@ti.com>
12 files changed:
examples/edma3_driver/evmTI814X/.ccsproject [new file with mode: 0755]
examples/edma3_driver/evmTI814X/.cdtbuild [new file with mode: 0755]
examples/edma3_driver/evmTI814X/.cdtproject [new file with mode: 0755]
examples/edma3_driver/evmTI814X/.project [new file with mode: 0755]
examples/edma3_driver/evmTI814X/.settings/org.eclipse.cdt.managedbuilder.core.prefs [new file with mode: 0755]
examples/edma3_driver/evmTI814X/edma3_drv_bios6_ti814x_st_sample.cfg [new file with mode: 0755]
examples/edma3_driver/evmTI814X/linker.cmd [new file with mode: 0755]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c [new file with mode: 0755]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_int_reg.c [new file with mode: 0755]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_cfg.c [new file with mode: 0755]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_int_reg.c [new file with mode: 0755]
packages/ti/sdo/edma3/rm/src/configs/edma3_ti814x_cfg.c [new file with mode: 0755]

diff --git a/examples/edma3_driver/evmTI814X/.ccsproject b/examples/edma3_driver/evmTI814X/.ccsproject
new file mode 100755 (executable)
index 0000000..424146c
--- /dev/null
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
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+\r
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+<isElfFormat value="false"/>\r
+<rts value="libc.a"/>\r
+</projectOptions>\r
diff --git a/examples/edma3_driver/evmTI814X/.cdtbuild b/examples/edma3_driver/evmTI814X/.cdtbuild
new file mode 100755 (executable)
index 0000000..56cc1a1
--- /dev/null
@@ -0,0 +1,115 @@
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diff --git a/examples/edma3_driver/evmTI814X/.cdtproject b/examples/edma3_driver/evmTI814X/.cdtproject
new file mode 100755 (executable)
index 0000000..1be6b75
--- /dev/null
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+<?eclipse-cdt version="2.0"?>\r
+\r
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diff --git a/examples/edma3_driver/evmTI814X/.project b/examples/edma3_driver/evmTI814X/.project
new file mode 100755 (executable)
index 0000000..aa3f83e
--- /dev/null
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+       <name>edma_drv_bios6_ti814x_st_sample</name>\r
+       <comment></comment>\r
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+       </projects>\r
+       <buildSpec>\r
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+                       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
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+       <natures>\r
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+                       <type>1</type>\r
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+                       <type>1</type>\r
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+               <link>\r
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+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>\r
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diff --git a/examples/edma3_driver/evmTI814X/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evmTI814X/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100755 (executable)
index 0000000..5c39c16
--- /dev/null
@@ -0,0 +1,13 @@
+#Fri Sep 03 15:48:48 IST 2010\r
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+com.ti.ccstudio.buildDefinitions.C6000.Debug.2023887093/internalBuilder/ignoreErr=true\r
+com.ti.ccstudio.buildDefinitions.C6000.Debug.316309808/internalBuilder/enabled=false\r
+com.ti.ccstudio.buildDefinitions.C6000.Debug.316309808/internalBuilder/ignoreErr=true\r
+com.ti.ccstudio.buildDefinitions.C6000.Release.1950320679/internalBuilder/enabled=false\r
+com.ti.ccstudio.buildDefinitions.C6000.Release.1950320679/internalBuilder/ignoreErr=true\r
+com.ti.ccstudio.buildDefinitions.C6000.Release.2087931291/internalBuilder/enabled=false\r
+com.ti.ccstudio.buildDefinitions.C6000.Release.2087931291/internalBuilder/ignoreErr=true\r
+eclipse.preferences.version=1\r
+environment/project=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.316309808=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
+environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.1950320679=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<environment/>\r\n\r
diff --git a/examples/edma3_driver/evmTI814X/edma3_drv_bios6_ti814x_st_sample.cfg b/examples/edma3_driver/evmTI814X/edma3_drv_bios6_ti814x_st_sample.cfg
new file mode 100755 (executable)
index 0000000..3bd14ea
--- /dev/null
@@ -0,0 +1,22 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
+var ECM       = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi   = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Startup   = xdc.useModule ("xdc.runtime.Startup");
+var System    = xdc.useModule ("xdc.runtime.System");
+var Log       = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* USE EDMA3 Sample App */
+xdc.loadPackage('ti.sdo.edma3.drv.sample');
+
+Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+Timer.timerSettings[0].intNum = 14;
diff --git a/examples/edma3_driver/evmTI814X/linker.cmd b/examples/edma3_driver/evmTI814X/linker.cmd
new file mode 100755 (executable)
index 0000000..000c07d
--- /dev/null
@@ -0,0 +1,5 @@
+SECTIONS
+{
+    .my_sect_iram > DDR3_RAM
+    .my_sect_ddr  > DDR3_RAM
+}
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c
new file mode 100755 (executable)
index 0000000..e24ee12
--- /dev/null
@@ -0,0 +1,845 @@
+/*
+ * sample_ti814x_cfg.c
+ *
+ * SoC specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                    1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+{
+    return 1;
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+{
+    (void) dspNum;
+
+    return 1;
+}
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available                                            */
+#define EDMA3_NUM_PARAMSET                              (512u)
+
+/** Number of TCCS available                                                  */
+#define EDMA3_NUM_TCC                                   (64u)
+
+/** Number of DMA Channels available                                          */
+#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+
+/** Number of QDMA Channels available                                         */
+#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_0_NUM_EVTQUE                              (4u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_0_NUM_TC                                  (4u)
+
+/** Number of Regions                                                         */
+#define EDMA3_0_NUM_REGIONS                             (2u)
+
+
+/** Interrupt no. for Transfer Completion                                     */
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (20u)
+/** Interrupt no. for CC Error                                                */
+#define EDMA3_0_CC_ERROR_INT                            (21u)
+/** Interrupt no. for TCs Error                                               */
+#define EDMA3_0_TC0_ERROR_INT                           (22u)
+#define EDMA3_0_TC1_ERROR_INT                           (27u)
+#define EDMA3_0_TC2_ERROR_INT                           (28u)
+#define EDMA3_0_TC3_ERROR_INT                           (29u)
+#define EDMA3_0_TC4_ERROR_INT                           (0u)
+#define EDMA3_0_TC5_ERROR_INT                           (0u)
+#define EDMA3_0_TC6_ERROR_INT                           (0u)
+#define EDMA3_0_TC7_ERROR_INT                           (0u)
+
+/**
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+ * ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file.
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+ * to transfer completion interrupt.
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+ * to CC error interrupts.
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+ * to TC error interrupts.
+ */
+/* EDMA 0 */
+
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_0_HWI_INT_CC_ERR                              (7u)
+#define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC2_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC3_ERR                             (7u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                      /* 31     0 */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFFFFFFFFu)  /* TBD */
+
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in omapl138. */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFFFFFFFFu) /* TBD */
+
+
+/* Variable which will be used internally for referring number of Event Queues*/
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+                                                        EDMA3_0_NUM_EVTQUE,
+                                                    };
+
+/* Variable which will be used internally for referring number of TCs.        */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+                                                    EDMA3_0_NUM_TC,
+                                                };
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    {
+        0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+    },
+};
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_CC_ERROR_INT,
+                                               };
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
+{
+   {
+       EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
+       EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
+       EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
+       EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
+   }
+};
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_HWI_INT_XFER_COMP
+                                                  };
+
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+                                                   EDMA3_0_HWI_INT_CC_ERR
+                                               };
+
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+                                                     {
+                                                        EDMA3_0_HWI_INT_TC0_ERR,
+                                                        EDMA3_0_HWI_INT_TC1_ERR,
+                                                        EDMA3_0_HWI_INT_TC2_ERR,
+                                                        EDMA3_0_HWI_INT_TC3_ERR
+                                                     }
+                                               };
+
+/* Driver Object Initialization Configuration */
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+{
+    {
+        /* EDMA3 INSTANCE# 0 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        EDMA3_NUM_DMA_CHANNELS,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        EDMA3_NUM_QDMA_CHANNELS,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        EDMA3_NUM_TCC,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        EDMA3_NUM_PARAMSET,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        EDMA3_0_NUM_EVTQUE,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        EDMA3_0_NUM_TC,
+        /** Number of Regions on this EDMA3 controller                        */
+        EDMA3_0_NUM_REGIONS,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        0u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        (void *)0x49000000u,
+        /** Transfer Controller (TC) Registers */
+        {
+            (void *)0x49800000u,
+            (void *)0x49900000u,
+            (void *)0x49A00000u,
+            (void *)0x49B00000u,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_0_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_0_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            EDMA3_0_TC0_ERROR_INT,
+            EDMA3_0_TC1_ERROR_INT,
+            EDMA3_0_TC2_ERROR_INT,
+            EDMA3_0_TC3_ERROR_INT,
+            EDMA3_0_TC4_ERROR_INT,
+            EDMA3_0_TC5_ERROR_INT,
+            EDMA3_0_TC6_ERROR_INT,
+            EDMA3_0_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            2u,
+            3u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            16u,
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u,
+            36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u,
+            44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u,
+            52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u,
+            60u, 61u, 62u, 63u
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            }
+        },
+};
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Resources owned/reserved by region 0 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+        /* Resources owned/reserved by region 1 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31       0 */
+            {0xFF3FF3FFu,
+            /* 63..32 */
+            0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+        },
+        /* Resources owned/reserved by region 2 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 3 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 4 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 5 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 6 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 7 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+    }
+};
+
+/* Driver Instance Cross bar event to channel map Initialization Configuration */
+EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Event to channel map for region 0 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 1 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 2 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 3 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 4 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 5 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 6 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 7 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+    }
+};
+
+/* End of File */
+
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_int_reg.c
new file mode 100755 (executable)
index 0000000..6dc5cc1
--- /dev/null
@@ -0,0 +1,306 @@
+/*
+ * sample_ti814x_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+extern unsigned int dsp_num;
+
+/* External Instance Specific Configuration Structure */
+extern EDMA3_DRV_GblXbarToChanConfigParams 
+                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+
+typedef struct  {
+    volatile Uint32 DSP_INTMUX[21];
+    volatile Uint32 DUCATI_INTMUX[15];
+    volatile Uint32 TPCC_EVTMUX[16];
+    volatile Uint32 TIMER_EVTCAPT;
+    volatile Uint32 GPIO_MUX;
+} CSL_IntmuxRegs;
+
+typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+
+
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (64u)
+#define EDMA3_NUM_TCC                     (64u)
+
+/*
+ * Forward decleration
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum);
+
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Enable the Xfer Completion Event Interrupt */
+    EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
+                               edma3Id, 1);
+    EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Enable the CC Error Event Interrupt */
+    EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
+                                               edma3Id, 1);
+    EventCombiner_enableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
+                            (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
+                            edma3Id, 1);
+        EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
+    Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
+    Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Disable the Xfer Completion Event Interrupt */
+       EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Disable the CC Error Event Interrupt */
+       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+       {
+        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**
+ * \brief   sampleMapXbarEvtToChan
+ *
+ * This function reads from the sample configuration structure which specifies 
+ * cross bar events mapped to DMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+    unsigned int xbarEvtNum = 0;
+    int          edmaChanNum = 0;
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum != NULL) &&
+               (edmaGblXbarConfig != NULL))
+               {
+               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
+               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
+               if (edmaChanNum != -1)
+                       {
+                       *chanNum = edmaChanNum;
+                       edma3Result = EDMA3_DRV_SOK;
+                       }
+               }
+       return (edma3Result);
+       }
+
+
+/**
+ * \brief   sampleConfigScr
+ *
+ * This function configures control config registers for the cross bar events 
+ * mapped to the EDMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum)
+       {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
+    unsigned int scrChanOffset = 0;
+    unsigned int scrRegOffset  = 0;
+    unsigned int xBarEvtNum    = 0;
+    CSL_IntmuxRegsOvly scrEvtMux = (unsigned int)(0x0);
+
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
+               (chanNum < EDMA3_NUM_TCC))
+               {
+               scrRegOffset = chanNum / 4;
+               scrChanOffset = chanNum - (scrRegOffset * 4);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+               
+               switch(scrChanOffset)
+                       {
+                       case 0:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
+                               break;
+                       case 1:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
+                                       (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK)));
+                               break;
+                       case 2:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
+                                       (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK)));
+                               break;
+                       case 3:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
+                                       (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK)));
+                               break;
+                       default:
+                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+                               break;
+                       }
+               }
+       else
+               {
+               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+               }
+       return edma3Result;
+       }
+
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
+                                   unsigned int edma3Id)
+    {
+    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
+    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
+                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
+    if (hEdma != NULL)
+        {
+        retVal = EDMA3_DRV_initXbarEventMap(hEdma, 
+                                                                       sampleXbarToChanConfig, 
+                                                                       &sampleMapXbarEvtToChan, 
+                                                                       &sampleConfigScr);
+        }
+    
+    return retVal;
+    }
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_cfg.c
new file mode 100755 (executable)
index 0000000..86dec63
--- /dev/null
@@ -0,0 +1,846 @@
+/*
+ * sample_omapl138_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         1u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                    1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+{
+    return 1;
+}
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+{
+    (void) dspNum;
+
+    return 1;
+}
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
+
+/** Number of PaRAM Sets available                                            */
+#define EDMA3_NUM_PARAMSET                              (512u)
+
+/** Number of TCCS available                                                  */
+#define EDMA3_NUM_TCC                                   (64u)
+
+/** Number of DMA Channels available                                          */
+#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+
+/** Number of QDMA Channels available                                         */
+#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_0_NUM_EVTQUE                              (4u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_0_NUM_TC                                  (4u)
+
+/** Number of Regions                                                         */
+#define EDMA3_0_NUM_REGIONS                             (2u)
+
+
+/** Interrupt no. for Transfer Completion                                     */
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (20u)
+/** Interrupt no. for CC Error                                                */
+#define EDMA3_0_CC_ERROR_INT                            (21u)
+/** Interrupt no. for TCs Error                                               */
+#define EDMA3_0_TC0_ERROR_INT                           (22u)
+#define EDMA3_0_TC1_ERROR_INT                           (27u)
+#define EDMA3_0_TC2_ERROR_INT                           (28u)
+#define EDMA3_0_TC3_ERROR_INT                           (29u)
+#define EDMA3_0_TC4_ERROR_INT                           (0u)
+#define EDMA3_0_TC5_ERROR_INT                           (0u)
+#define EDMA3_0_TC6_ERROR_INT                           (0u)
+#define EDMA3_0_TC7_ERROR_INT                           (0u)
+
+/**
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+ * ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file.
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+ * to transfer completion interrupt.
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+ * to CC error interrupts.
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+ * to TC error interrupts.
+ */
+/* EDMA 0 */
+
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_0_HWI_INT_CC_ERR                              (7u)
+#define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC2_ERR                             (7u)
+#define EDMA3_0_HWI_INT_TC3_ERR                             (7u)
+
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                      /* 31     0 */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFFFFFFFFu)  /* TBD */
+
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in omapl138. */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFFFFFFFFu) /* TBD */
+
+
+/* Variable which will be used internally for referring number of Event Queues*/
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+                                                        EDMA3_0_NUM_EVTQUE,
+                                                    };
+
+/* Variable which will be used internally for referring number of TCs.        */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+                                                    EDMA3_0_NUM_TC,
+                                                };
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    {
+        0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+    },
+};
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_CC_ERROR_INT,
+                                               };
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
+{
+   {
+       EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
+       EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
+       EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
+       EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
+   }
+};
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_HWI_INT_XFER_COMP
+                                                  };
+
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+                                                   EDMA3_0_HWI_INT_CC_ERR
+                                               };
+
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+                                                     {
+                                                        EDMA3_0_HWI_INT_TC0_ERR,
+                                                        EDMA3_0_HWI_INT_TC1_ERR,
+                                                        EDMA3_0_HWI_INT_TC2_ERR,
+                                                        EDMA3_0_HWI_INT_TC3_ERR
+                                                     }
+                                               };
+
+/* Driver Object Initialization Configuration                                 */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+{
+    {
+        /* EDMA3 INSTANCE# 0 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        EDMA3_NUM_DMA_CHANNELS,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        EDMA3_NUM_QDMA_CHANNELS,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        EDMA3_NUM_TCC,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        EDMA3_NUM_PARAMSET,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        EDMA3_0_NUM_EVTQUE,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        EDMA3_0_NUM_TC,
+        /** Number of Regions on this EDMA3 controller                        */
+        EDMA3_0_NUM_REGIONS,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        0u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        (void *)0x49000000u,
+        /** Transfer Controller (TC) Registers */
+        {
+            (void *)0x49800000u,
+            (void *)0x49900000u,
+            (void *)0x49A00000u,
+            (void *)0x49B00000u,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_0_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_0_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            EDMA3_0_TC0_ERROR_INT,
+            EDMA3_0_TC1_ERROR_INT,
+            EDMA3_0_TC2_ERROR_INT,
+            EDMA3_0_TC3_ERROR_INT,
+            EDMA3_0_TC4_ERROR_INT,
+            EDMA3_0_TC5_ERROR_INT,
+            EDMA3_0_TC6_ERROR_INT,
+            EDMA3_0_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            2u,
+            3u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            16u,
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+            },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            32u, 33u, 34u, 35u,
+            36u, 37u, 38u, 39u,
+            40u, 41u, 42u, 43u,
+            44u, 45u, 46u, 47u,
+            48u, 49u, 50u, 51u,
+            52u, 53u, 54u, 55u,
+            56u, 57u, 58u, 59u,
+            60u, 61u, 62u, 63u
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            }
+        },
+
+};
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Resources owned/reserved by region 0 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+        /* Resources owned/reserved by region 1 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31       0 */
+            {0xFF3FF3FFu,
+            /* 63..32 */
+            0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+        },
+        /* Resources owned/reserved by region 2 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 3 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 4 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 5 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 6 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 7 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+    },
+};
+
+/* Driver Instance Cross bar event to channel map Initialization Configuration */
+EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Event to channel map for region 0 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 1 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 2 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 3 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 4 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 5 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 6 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 7 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+    }
+};
+
+/* End of File */
+
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_int_reg.c
new file mode 100755 (executable)
index 0000000..d39f8b1
--- /dev/null
@@ -0,0 +1,306 @@
+/*
+ * sample_omapl138_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+
+#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+extern unsigned int dsp_num;
+
+/* External Instance Specific Configuration Structure */
+extern EDMA3_RM_GblXbarToChanConfigParams 
+                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
+
+typedef struct  {
+    volatile Uint32 DSP_INTMUX[21];
+    volatile Uint32 DUCATI_INTMUX[15];
+    volatile Uint32 TPCC_EVTMUX[16];
+    volatile Uint32 TIMER_EVTCAPT;
+    volatile Uint32 GPIO_MUX;
+} CSL_IntmuxRegs;
+
+typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
+
+
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
+
+
+#define EDMA3_MAX_CROSS_BAR_EVENTS_DM8148 (64u)
+#define EDMA3_NUM_TCC                     (64u)
+
+/*
+ * Forward decleration
+ */
+EDMA3_RM_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig);
+EDMA3_RM_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum);
+
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Enable the Xfer Completion Event Interrupt */
+    EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
+                               edma3Id, 1);
+    EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Enable the CC Error Event Interrupt */
+    EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
+                                               edma3Id, 1);
+    EventCombiner_enableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
+                            (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
+                            edma3Id, 1);
+        EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
+    Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
+    Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Disable the Xfer Completion Event Interrupt */
+       EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Disable the CC Error Event Interrupt */
+       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+       {
+        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**
+ * \brief   sampleMapXbarEvtToChan
+ *
+ * This function reads from the sample configuration structure which specifies 
+ * cross bar events mapped to DMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_RM_Result sampleMapXbarEvtToChan (unsigned int eventNum,
+                 unsigned int *chanNum,
+                 const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig)
+       {
+    EDMA3_RM_Result edma3Result = EDMA3_RM_E_INVALID_PARAM;
+    unsigned int xbarEvtNum = 0;
+    int          edmaChanNum = 0;
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DM8148) &&
+               (chanNum != NULL) &&
+               (edmaGblXbarConfig != NULL))
+               {
+               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
+               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
+               if (edmaChanNum != -1)
+                       {
+                       *chanNum = edmaChanNum;
+                       edma3Result = EDMA3_RM_SOK;
+                       }
+               }
+       return (edma3Result);
+       }
+
+
+/**
+ * \brief   sampleConfigScr
+ *
+ * This function configures control config registers for the cross bar events 
+ * mapped to the EDMA channel.
+ *
+ * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
+                                  unsigned int chanNum)
+       {
+    EDMA3_RM_Result edma3Result = EDMA3_RM_SOK;
+    unsigned int scrChanOffset = 0;
+    unsigned int scrRegOffset  = 0;
+    unsigned int xBarEvtNum    = 0;
+    CSL_IntmuxRegsOvly scrEvtMux = (unsigned int)(0x0);
+
+
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DM8148) &&
+               (chanNum < EDMA3_NUM_TCC))
+               {
+               scrRegOffset = chanNum / 4;
+               scrChanOffset = chanNum - (scrRegOffset * 4);
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
+               
+               switch(scrChanOffset)
+                       {
+                       case 0:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
+                               break;
+                       case 1:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
+                                       (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK)));
+                               break;
+                       case 2:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
+                                       (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK)));
+                               break;
+                       case 3:
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
+                                       ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
+                                       (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK)));
+                               break;
+                       default:
+                               edma3Result = EDMA3_RM_E_INVALID_PARAM;
+                               break;
+                       }
+               }
+       else
+               {
+               edma3Result = EDMA3_RM_E_INVALID_PARAM;
+               }
+       return edma3Result;
+       }
+
+EDMA3_RM_Result sampleInitXbarEvt(EDMA3_RM_Handle hEdma, 
+                                   unsigned int edma3Id)
+    {
+    EDMA3_DRV_Result retVal = EDMA3_RM_E_INVALID_PARAM;
+    const EDMA3_RM_GblXbarToChanConfigParams *sampleXbarToChanConfig =
+                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
+    if (hEdma != NULL)
+        {
+        retVal = EDMA3_RM_initXbarEventMap(hEdma, 
+                                                                       sampleXbarToChanConfig, 
+                                                                       &sampleMapXbarEvtToChan, 
+                                                                       &sampleConfigScr);
+        }
+    
+    return retVal;
+    }
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_ti814x_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_ti814x_cfg.c
new file mode 100755 (executable)
index 0000000..e655e2c
--- /dev/null
@@ -0,0 +1,568 @@
+/*
+ * edma3_omapl138_cfg.c
+ *
+ * EDMA3 Driver Adaptation Configuration File (Soc Specific) for OMAPL138.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+#define NUM_SHADOW_REGIONS                      (4u)
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         1u
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* EDMA3 0 */
+                                                /* 31     0 */
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0        (0xFF3FF3FFu)
+/**
+ * EDMA channels 22 and 23, which correspond to GPIO
+ * bank interrupts will be used for memory-to-memory data transfers.
+ */
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+/* EDMA3 0 */
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1        (0x0u)
+
+/** Number of PaRAM Sets available                                            */
+#define EDMA3_NUM_PARAMSET                              (512u)
+
+/** Number of TCCS available                                                  */
+#define EDMA3_NUM_TCC                                   (64u)
+
+/** Number of DMA Channels available                                          */
+#define EDMA3_NUM_DMA_CHANNELS                          (64u)
+
+/** Number of QDMA Channels available                                         */
+#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_0_NUM_EVTQUE                              (4u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_0_NUM_TC                                  (4u)
+
+/** Number of Regions                                                         */
+#define EDMA3_0_NUM_REGIONS                             (2u)
+
+
+/** Interrupt no. for Transfer Completion                                     */
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (20u)
+/** Interrupt no. for CC Error                                                */
+#define EDMA3_0_CC_ERROR_INT                            (21u)
+/** Interrupt no. for TCs Error                                               */
+#define EDMA3_0_TC0_ERROR_INT                           (22u)
+#define EDMA3_0_TC1_ERROR_INT                           (27u)
+#define EDMA3_0_TC2_ERROR_INT                           (28u)
+#define EDMA3_0_TC3_ERROR_INT                           (29u)
+#define EDMA3_0_TC4_ERROR_INT                           (0u)
+#define EDMA3_0_TC5_ERROR_INT                           (0u)
+#define EDMA3_0_TC6_ERROR_INT                           (0u)
+#define EDMA3_0_TC7_ERROR_INT                           (0u)
+
+EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+    /** Total number of DMA Channels supported by the EDMA3 Controller */
+    EDMA3_NUM_DMA_CHANNELS,
+    /** Total number of QDMA Channels supported by the EDMA3 Controller */
+    EDMA3_NUM_QDMA_CHANNELS,
+    /** Total number of TCCs supported by the EDMA3 Controller */
+    EDMA3_NUM_TCC,
+    /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+    EDMA3_NUM_PARAMSET,
+    /** Total number of Event Queues in the EDMA3 Controller */
+    EDMA3_0_NUM_EVTQUE,
+    /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+    EDMA3_0_NUM_TC,
+    /** Number of Regions on this EDMA3 controller */
+    EDMA3_0_NUM_REGIONS,
+
+    /**
+     * \brief Channel mapping existence
+     * A value of 0 (No channel mapping) implies that there is fixed association
+     * for a channel number to a parameter entry number or, in other words,
+     * PaRAM entry n corresponds to channel n.
+     */
+    0u,
+
+    /** Existence of memory protection feature */
+    0u,
+
+    /** Global Register Region of CC Registers */
+    (void *)(0x01C00000u),
+    /** Transfer Controller (TC) Registers */
+        {
+        (void *)(0x01C08000u),
+        (void *)(0x01C08400u),
+        (void *)NULL,
+        (void *)NULL,
+        (void *)NULL,
+        (void *)NULL,
+        (void *)NULL,
+        (void *)NULL,
+        },
+    /** Interrupt no. for Transfer Completion */
+    EDMA3_0_CC_XFER_COMPLETION_INT,
+    /** Interrupt no. for CC Error */
+    EDMA3_0_CC_ERROR_INT,
+    /** Interrupt no. for TCs Error */
+        {
+        EDMA3_0_TC0_ERROR_INT,
+        EDMA3_0_TC1_ERROR_INT,
+        EDMA3_0_TC2_ERROR_INT,
+        EDMA3_0_TC3_ERROR_INT,
+        EDMA3_0_TC4_ERROR_INT,
+        EDMA3_0_TC5_ERROR_INT,
+        EDMA3_0_TC6_ERROR_INT,
+        EDMA3_0_TC7_ERROR_INT
+        },
+
+   /**
+     * \brief EDMA3 TC priority setting
+     *
+     * User can program the priority of the Event Queues
+     * at a system-wide level.  This means that the user can set the
+     * priority of an IO initiated by either of the TCs (Transfer Controllers)
+     * relative to IO initiated by the other bus masters on the
+     * device (ARM, DSP, USB, etc)
+     */
+        {
+        0u,
+        1u,
+        2u,
+        3u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+    /**
+     * \brief To Configure the Threshold level of number of events
+     * that can be queued up in the Event queues. EDMA3CC error register
+     * (CCERR) will indicate whether or not at any instant of time the
+     * number of events queued up in any of the event queues exceeds
+     * or equals the threshold/watermark value that is set
+     * in the queue watermark threshold register (QWMTHRA).
+     */
+        {
+        16u,
+        16u,
+        16u,
+        16u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+
+    /**
+     * \brief To Configure the Default Burst Size (DBS) of TCs.
+     * An optimally-sized command is defined by the transfer controller
+     * default burst size (DBS). Different TCs can have different
+     * DBS values. It is defined in Bytes.
+     */
+        {
+        16u,
+        16u,
+        16u,
+        16u,
+        0u,
+        0u,
+        0u,
+        0u
+        },
+
+    /**
+     * \brief Mapping from each DMA channel to a Parameter RAM set,
+     * if it exists, otherwise of no use.
+     */
+        {
+        0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+        16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+        /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+        EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+        },
+
+     /**
+      * \brief Mapping from each DMA channel to a TCC. This specific
+      * TCC code will be returned when the transfer is completed
+      * on the mapped channel.
+      */
+        {
+        0u, 1u, 2u, 3u,
+        4u, 5u, 6u, 7u,
+        8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        12u, 13u, 14u, 15u,
+        16u, 17u, 18u, 19u,
+        20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        24u, 25u, 26u, 27u,
+        28u, 29u, 30u, 31u,
+        /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+        EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+        },
+
+    /**
+     * \brief Mapping of DMA channels to Hardware Events from
+     * various peripherals, which use EDMA for data transfer.
+     * All channels need not be mapped, some can be free also.
+     */
+        {
+        DMA_CHANNEL_TO_EVENT_MAPPING_0_0,
+        DMA_CHANNEL_TO_EVENT_MAPPING_0_1
+        }
+    },
+};
+
+
+/* Default RM Instance Initialization Configuration */
+EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SHADOW_REGIONS] =
+{
+        /* EDMA3 INSTANCE# 0 */
+        {
+          {
+            /* Resources owned by Region 0 */
+             /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* Resources reserved by Region 0 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+          },
+
+          {
+            /* Resources owned by Region 1 */
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31      0  63..32 */
+            {DMA_CHANNEL_TO_EVENT_MAPPING_0_0, DMA_CHANNEL_TO_EVENT_MAPPING_0_1},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31      0  63..32 */
+            {DMA_CHANNEL_TO_EVENT_MAPPING_0_0, DMA_CHANNEL_TO_EVENT_MAPPING_0_1},
+          },
+
+          {
+            /* Resources owned by Region 2 */
+             /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* Resources reserved by Region 2 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+          },
+
+          {
+            /* Resources owned by Region 3 */
+             /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* Resources reserved by Region 3 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+          },
+        },
+};
+
+/* Driver Instance Cross bar event to channel map Initialization Configuration */
+EDMA3_RM_GblXbarToChanConfigParams defXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Event to channel map for region 0 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 1 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 2 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 3 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 4 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 5 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 6 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+        /* Event to channel map for region 7 */
+        {
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1, -1,
+            -1, -1, -1, -1, -1, -1, -1
+        },
+    }
+};
+
+/* End of File */
+
+
+