Single cfg file for Netra and Centaurus in drv sample
authorPrasad Konnur <prasad.konnur@ti.com>
Thu, 10 Nov 2011 14:54:46 +0000 (20:24 +0530)
committerPrasad Konnur <prasad.konnur@ti.com>
Thu, 10 Nov 2011 14:54:46 +0000 (20:24 +0530)
14 files changed:
packages/ti/sdo/edma3/drv/sample/makefile
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_cfg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_int_reg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_cfg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_int_reg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_cfg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_int_reg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_arm_int_reg.c [moved from packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3video_int_reg.c with 100% similarity]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3video_cfg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3vpss_cfg.c [deleted file]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3vpss_int_reg.c [deleted file]
packages/ti/sdo/edma3/rm/sample/makefile

index 84b5ddc5ec5fcd7a2ad9f06f186bf7f3d3a5be96..a17facdeccb9c886fc18ca7141534b5b5b97107c 100755 (executable)
@@ -31,28 +31,34 @@ SRCS_c6678-evm   = sample_c6678_cfg.c sample_c6678_int_reg.c
 SRCS_omapl138-evm = sample_omapl138_cfg.c sample_omapl138_int_reg.c
 SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_int_reg.c
 SRCS_omap4-evm   = sample_omap4_cfg.c sample_omap4_int_reg.c
+CFLAGS_LOCAL_ti816x-evm = -DBUILD_NETRA_DSP
+CFLAGS_LOCAL_ti814x-evm = -DBUILD_CENTAURUS_DSP
 SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_int_reg.c
-SRCS_ti816x-sim = sample_ti816x_cfg.c sample_ti816x_int_reg.c
 else
 SRCS_omapl138-evm = sample_omapl138_arm_cfg.c sample_omapl138_arm_int_reg.c
 endif
 ifeq ($(CORE),a8host)
-SRCS_ti814x-evm = sample_ti814x_arm_cfg.c sample_ti814x_arm_int_reg.c
+CFLAGS_LOCAL_ti816x-evm = -DBUILD_NETRA_A8
+CFLAGS_LOCAL_ti814x-evm = -DBUILD_CENTAURUS_A8
+SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_arm_int_reg.c
+SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_arm_int_reg.c
 endif
 ifeq ($(CORE),m3video)
-SRCS_ti816x-evm = sample_ti816x_m3video_cfg.c sample_ti816x_m3video_int_reg.c
-SRCS_ti816x-sim = sample_ti816x_m3video_cfg.c sample_ti816x_m3video_int_reg.c
-SRCS_ti814x-evm = sample_ti814x_m3video_cfg.c sample_ti814x_m3video_int_reg.c
+CFLAGS_LOCAL_ti816x-evm = -DBUILD_NETRA_M3VIDEO
+CFLAGS_LOCAL_ti814x-evm = -DBUILD_CENTAURUS_M3VIDEO
+SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_arm_int_reg.c
+SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_arm_int_reg.c
 endif
 ifeq ($(CORE),m3vpss)
-SRCS_ti816x-evm = sample_ti816x_m3vpss_cfg.c sample_ti816x_m3vpss_int_reg.c
-SRCS_ti816x-sim = sample_ti816x_m3vpss_cfg.c sample_ti816x_m3vpss_int_reg.c
-SRCS_ti814x-evm = sample_ti814x_m3vpss_cfg.c sample_ti814x_m3vpss_int_reg.c
+CFLAGS_LOCAL_ti816x-evm = -DBUILD_NETRA_M3VPSS
+CFLAGS_LOCAL_ti814x-evm = -DBUILD_CENTAURUS_M3VPSS
+SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_arm_int_reg.c
+SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_arm_int_reg.c
 endif
 SRCS_c6748-evm = sample_c6748_cfg.c sample_c6748_int_reg.c
 SRCS_da830-evm = sample_da830_cfg.c sample_da830_int_reg.c
 
-CFLAGS_LOCAL_ti814x-evm = -DCHIP_TI814X
+CFLAGS_LOCAL_ti814x-evm += -DCHIP_TI814X
 
 # Include common make files
 include $(ROOTDIR)/makerules/common.mk
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_cfg.c
deleted file mode 100755 (executable)
index 9692cc2..0000000
+++ /dev/null
@@ -1,858 +0,0 @@
-/*
- * sample_ti814x_cfg.c
- *
- * SoC specific EDMA3 hardware related information like number of transfer
- * controllers, various interrupt ids etc. It is used while interrupts
- * enabling / disabling. It needs to be ported for different SoCs.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sdo/edma3/drv/edma3_drv.h>
-
-/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES         1u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
-
-/* Number of DSPs present in the system */
-#define NUM_DSPS                    0u
-const unsigned int numDsps = NUM_DSPS;
-
-/* Determine the processor id by reading DNUM register. */
-unsigned short determineProcId()
-{
-    return 0;
-}
-
-signed char*  getGlobalAddr(signed char* addr)
-{
-     return (addr); /* The address is already a global address */
-}
-unsigned short isGblConfigRequired(unsigned int dspNum)
-{
-    (void) dspNum;
-    return 0;
-}
-
-/* Semaphore handles */
-EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
-
-/** Number of PaRAM Sets available                                            */
-#define EDMA3_NUM_PARAMSET                              (512u)
-
-/** Number of TCCS available                                                  */
-#define EDMA3_NUM_TCC                                   (64u)
-
-/** Number of DMA Channels available                                          */
-#define EDMA3_NUM_DMA_CHANNELS                          (64u)
-
-/** Number of QDMA Channels available                                         */
-#define EDMA3_NUM_QDMA_CHANNELS                         (8u)
-
-/** Number of Event Queues available                                          */
-#define EDMA3_0_NUM_EVTQUE                              (4u)
-
-/** Number of Transfer Controllers available                                  */
-#define EDMA3_0_NUM_TC                                  (4u)
-
-/** Number of Regions                                                         */
-#define EDMA3_0_NUM_REGIONS                             (4u)
-
-
-/** Interrupt no. for Transfer Completion                                     */
-#define EDMA3_0_CC_XFER_COMPLETION_INT                  (12u)
-/** Interrupt no. for CC Error                                                */
-#define EDMA3_0_CC_ERROR_INT                            (14u)
-/** Interrupt no. for TCs Error                                               */
-#define EDMA3_0_TC0_ERROR_INT                           (112u)
-#define EDMA3_0_TC1_ERROR_INT                           (113u)
-#define EDMA3_0_TC2_ERROR_INT                           (114u)
-#define EDMA3_0_TC3_ERROR_INT                           (115u)
-#define EDMA3_0_TC4_ERROR_INT                           (0u)
-#define EDMA3_0_TC5_ERROR_INT                           (0u)
-#define EDMA3_0_TC6_ERROR_INT                           (0u)
-#define EDMA3_0_TC7_ERROR_INT                           (0u)
-
-/**
- * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
- * ECM events (SoC specific). These ECM events come
- * under ECM block XXX (handling those specific ECM events). Normally, block
- * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
- * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
- * is mapped to a specific HWI_INT YYY in the tcf file.
- * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
- * to transfer completion interrupt.
- * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
- * to CC error interrupts.
- * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
- * to TC error interrupts.
- */
-/* EDMA 0 */
-
-#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
-#define EDMA3_0_HWI_INT_CC_ERR                              (7u)
-#define EDMA3_0_HWI_INT_TC0_ERR                             (10u)
-#define EDMA3_0_HWI_INT_TC1_ERR                             (10u)
-#define EDMA3_0_HWI_INT_TC2_ERR                             (10u)
-#define EDMA3_0_HWI_INT_TC3_ERR                             (10u)
-
-
-/**
- * \brief Mapping of DMA channels 0-31 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                      /* 31     0 */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F00u)  /* TBD */
-
-
-/**
- * \brief Mapping of DMA channels 32-63 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-/* DMA channels 32-63 DOES NOT exist in omapl138. */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF003C00u) /* TBD */
-
-
-/* Variable which will be used internally for referring number of Event Queues*/
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
-                                                        EDMA3_0_NUM_EVTQUE,
-                                                    };
-
-/* Variable which will be used internally for referring number of TCs.        */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
-                                                    EDMA3_0_NUM_TC,
-                                                };
-
-/**
- * Variable which will be used internally for referring transfer completion
- * interrupt.
- */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    {
-        EDMA3_0_CC_XFER_COMPLETION_INT, 0, 0u, 0u, 0u, 0u, 0u, 0u,
-    },
-};
-
-/**
- * Variable which will be used internally for referring channel controller's
- * error interrupt.
- */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
-                                                    EDMA3_0_CC_ERROR_INT,
-                                               };
-
-/**
- * Variable which will be used internally for referring transfer controllers'
- * error interrupts.
- */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
-{
-   {
-       EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
-       EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
-       EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
-       EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
-   }
-};
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
-                                                    EDMA3_0_HWI_INT_XFER_COMP
-                                                  };
-
-unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
-                                                   EDMA3_0_HWI_INT_CC_ERR
-                                               };
-
-unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
-                                                     {
-                                                        EDMA3_0_HWI_INT_TC0_ERR,
-                                                        EDMA3_0_HWI_INT_TC1_ERR,
-                                                        EDMA3_0_HWI_INT_TC2_ERR,
-                                                        EDMA3_0_HWI_INT_TC3_ERR
-                                                     }
-                                               };
-
-/* Driver Object Initialization Configuration */
-EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
-{
-    {
-        /* EDMA3 INSTANCE# 0 */
-        /** Total number of DMA Channels supported by the EDMA3 Controller    */
-        EDMA3_NUM_DMA_CHANNELS,
-        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
-        EDMA3_NUM_QDMA_CHANNELS,
-        /** Total number of TCCs supported by the EDMA3 Controller            */
-        EDMA3_NUM_TCC,
-        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
-        EDMA3_NUM_PARAMSET,
-        /** Total number of Event Queues in the EDMA3 Controller              */
-        EDMA3_0_NUM_EVTQUE,
-        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
-        EDMA3_0_NUM_TC,
-        /** Number of Regions on this EDMA3 controller                        */
-        EDMA3_0_NUM_REGIONS,
-
-        /**
-         * \brief Channel mapping existence
-         * A value of 0 (No channel mapping) implies that there is fixed association
-         * for a channel number to a parameter entry number or, in other words,
-         * PaRAM entry n corresponds to channel n.
-         */
-        1u,
-
-        /** Existence of memory protection feature */
-        0u,
-
-        /** Global Register Region of CC Registers */
-        (void *)0x49000000u,
-        /** Transfer Controller (TC) Registers */
-        {
-            (void *)0x49800000u,
-            (void *)0x49900000u,
-            (void *)0x49A00000u,
-            (void *)0x49B00000u,
-            (void *)NULL,
-            (void *)NULL,
-            (void *)NULL,
-            (void *)NULL
-        },
-        /** Interrupt no. for Transfer Completion */
-        EDMA3_0_CC_XFER_COMPLETION_INT,
-        /** Interrupt no. for CC Error */
-        EDMA3_0_CC_ERROR_INT,
-        /** Interrupt no. for TCs Error */
-        {
-            EDMA3_0_TC0_ERROR_INT,
-            EDMA3_0_TC1_ERROR_INT,
-            EDMA3_0_TC2_ERROR_INT,
-            EDMA3_0_TC3_ERROR_INT,
-            EDMA3_0_TC4_ERROR_INT,
-            EDMA3_0_TC5_ERROR_INT,
-            EDMA3_0_TC6_ERROR_INT,
-            EDMA3_0_TC7_ERROR_INT
-        },
-
-        /**
-         * \brief EDMA3 TC priority setting
-         *
-         * User can program the priority of the Event Queues
-         * at a system-wide level.  This means that the user can set the
-         * priority of an IO initiated by either of the TCs (Transfer Controllers)
-         * relative to IO initiated by the other bus masters on the
-         * device (ARM, DSP, USB, etc)
-         */
-        {
-            0u,
-            1u,
-            2u,
-            3u,
-            0u,
-            0u,
-            0u,
-            0u
-        },
-        /**
-         * \brief To Configure the Threshold level of number of events
-         * that can be queued up in the Event queues. EDMA3CC error register
-         * (CCERR) will indicate whether or not at any instant of time the
-         * number of events queued up in any of the event queues exceeds
-         * or equals the threshold/watermark value that is set
-         * in the queue watermark threshold register (QWMTHRA).
-         */
-        {
-            16u,
-            16u,
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u
-        },
-
-        /**
-         * \brief To Configure the Default Burst Size (DBS) of TCs.
-         * An optimally-sized command is defined by the transfer controller
-         * default burst size (DBS). Different TCs can have different
-         * DBS values. It is defined in Bytes.
-         */
-            {
-            16u,
-            16u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u,
-            0u
-            },
-
-        /**
-         * \brief Mapping from each DMA channel to a Parameter RAM set,
-         * if it exists, otherwise of no use.
-         */
-            {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
-            },
-
-         /**
-          * \brief Mapping from each DMA channel to a TCC. This specific
-          * TCC code will be returned when the transfer is completed
-          * on the mapped channel.
-          */
-            {
-            0u, 1u, 2u, 3u,
-            4u, 5u, 6u, 7u,
-            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u,
-            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            24u, 25u, 26u, 27u,
-            28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
-            },
-
-        /**
-         * \brief Mapping of DMA channels to Hardware Events from
-         * various peripherals, which use EDMA for data transfer.
-         * All channels need not be mapped, some can be free also.
-         */
-            {
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
-            }
-        },
-};
-
-
-/* Driver Instance Initialization Configuration */
-EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-        /* Resources owned/reserved by region 0 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x000000FFu},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-            /* Resources reserved by Region 1 */
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31       0 */
-            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
-            /* 63..32 */
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31       0 */
-            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
-            /* 63..32 */
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
-        },
-        /* Resources owned/reserved by region 1 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x000000FFu},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
-
-            /* Resources reserved by Region 1 */
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* resvdDmaChannels */
-            /* 31       0 */
-            {0xFF3FF3FFu,
-            /* 63..32 */
-            0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31       0 */
-            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
-            /* 63..32 */
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
-        },
-        /* Resources owned/reserved by region 2 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x000000FFu},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
-
-            /* Resources reserved by Region 1 */
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* resvdDmaChannels */
-            /* 31       0 */
-            {0xFF3FF3FFu,
-            /* 63..32 */
-            0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31       0 */
-            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
-            /* 63..32 */
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
-        },
-
-        /* Resources owned/reserved by region 3 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-
-        /* Resources owned/reserved by region 4 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-
-        /* Resources owned/reserved by region 5 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-
-        /* Resources owned/reserved by region 6 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-
-        /* Resources owned/reserved by region 7 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-    }
-};
-
-/* Driver Instance Cross bar event to channel map Initialization Configuration */
-EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-        /* Event to channel map for region 0 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, 26, 27, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 1 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 2 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 3 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 4 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 5 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 6 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 7 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-    }
-};
-
-/* End of File */
-
index 4bb6a34020d79d95bda76f545d01a43c1cc6e479..4262c364d35b29fe610497635eb93399b8e05e1e 100755 (executable)
@@ -152,7 +152,7 @@ void registerEdma3Interrupts (unsigned int edma3Id)
        /* set the priority ID     */
        hwiParams.priority = hwIntXferComp[edma3Id];
     
-    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num],
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
                                        (&lisrEdma3ComplHandler0),
                                        (const Hwi_Params *) (&hwiParams),
                                        &eb);
@@ -212,7 +212,7 @@ void registerEdma3Interrupts (unsigned int edma3Id)
 #if 0
     Hwi_enableInterrupt(13);
 #endif
-    Hwi_enableInterrupt(ccXferCompInt[edma3Id][gpp_num]);
+    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
     numTc = 0;
     while (numTc < numEdma3Tc[edma3Id])
            {
index d731b4af43c094583ee75ddc7cb697ae4a9ac984..d6544f2b5d8d6cf19b95a8ddd74d0046f008191e 100755 (executable)
@@ -51,7 +51,17 @@ const unsigned int numDsps = NUM_DSPS;
 /* Determine the processor id by reading DNUM register. */
 unsigned short determineProcId()
 {
-    return 1;
+#ifdef BUILD_CENTAURUS_A8
+       return 0;
+#elif defined BUILD_CENTAURUS_DSP
+       return 1;
+#elif defined BUILD_CENTAURUS_M3VPSS
+       return 5;
+#elif defined BUILD_CENTAURUS_M3VIDEO
+       return 4;
+#else
+       return 1;
+#endif
 }
 
 signed char*  getGlobalAddr(signed char* addr)
@@ -61,8 +71,11 @@ signed char*  getGlobalAddr(signed char* addr)
 unsigned short isGblConfigRequired(unsigned int dspNum)
 {
     (void) dspNum;
-
-    return 1;
+#ifdef BUILD_CENTAURUS_DSP
+       return 1;
+#else
+       return 0;
+#endif
 }
 
 /* Semaphore handles */
@@ -81,28 +94,76 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_NUM_QDMA_CHANNELS                         (8u)
 
 /** Number of Event Queues available                                          */
-#define EDMA3_0_NUM_EVTQUE                              (4u)
+#define EDMA3_NUM_EVTQUE                              (4u)
 
 /** Number of Transfer Controllers available                                  */
-#define EDMA3_0_NUM_TC                                  (4u)
+#define EDMA3_NUM_TC                                  (4u)
 
 /** Number of Regions                                                         */
-#define EDMA3_0_NUM_REGIONS                             (2u)
-
-
-/** Interrupt no. for Transfer Completion                                     */
-#define EDMA3_0_CC_XFER_COMPLETION_INT                  (20u)
-/** Interrupt no. for CC Error                                                */
-#define EDMA3_0_CC_ERROR_INT                            (21u)
-/** Interrupt no. for TCs Error                                               */
-#define EDMA3_0_TC0_ERROR_INT                           (22u)
-#define EDMA3_0_TC1_ERROR_INT                           (27u)
-#define EDMA3_0_TC2_ERROR_INT                           (28u)
-#define EDMA3_0_TC3_ERROR_INT                           (29u)
-#define EDMA3_0_TC4_ERROR_INT                           (0u)
-#define EDMA3_0_TC5_ERROR_INT                           (0u)
-#define EDMA3_0_TC6_ERROR_INT                           (0u)
-#define EDMA3_0_TC7_ERROR_INT                           (0u)
+#define EDMA3_NUM_REGIONS                             (6u)
+
+
+/** Interrupt no. for Transfer Completion */
+#define EDMA3_CC_XFER_COMPLETION_INT_A8                 (12u)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (20u)
+#define EDMA3_CC_XFER_COMPLETION_INT_M3VPSS             (63u)
+#define EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO            (62u)
+
+#ifdef BUILD_CENTAURUS_A8
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A8
+#elif defined BUILD_CENTAURUS_DSP
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
+#elif defined BUILD_CENTAURUS_M3VIDEO
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO
+#elif defined BUILD_CENTAURUS_M3VPSS
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_M3VPSS
+#else
+#define EDMA3_CC_XFER_COMPLETION_INT                    {0u}
+#endif
+
+/** Interrupt no. for CC Error */
+#define EDMA3_CC_ERROR_INT_A8                           (14u)
+#define EDMA3_CC_ERROR_INT_DSP                          (21u)
+
+#ifdef BUILD_CENTAURUS_A8
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A8
+#elif defined BUILD_CENTAURUS_DSP
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP
+#else
+#define EDMA3_CC_ERROR_INT                              (0u)
+#endif
+
+/** Interrupt no. for TCs Error */
+#define EDMA3_TC0_ERROR_INT_DSP                         (22u)
+#define EDMA3_TC1_ERROR_INT_DSP                         (27u)
+#define EDMA3_TC2_ERROR_INT_DSP                         (28u)
+#define EDMA3_TC3_ERROR_INT_DSP                         (29u)
+#define EDMA3_TC0_ERROR_INT_A8                          (112u)
+#define EDMA3_TC1_ERROR_INT_A8                          (113u)
+#define EDMA3_TC2_ERROR_INT_A8                          (114u)
+#define EDMA3_TC3_ERROR_INT_A8                          (115u)
+
+#ifdef BUILD_CENTAURUS_A8
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A8
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC0_ERROR_INT_A8
+#define EDMA3_TC2_ERROR_INT                             EDMA3_TC0_ERROR_INT_A8
+#define EDMA3_TC3_ERROR_INT                             EDMA3_TC0_ERROR_INT_A8
+#elif defined BUILD_CENTAURUS_DSP
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_DSP
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_DSP
+#define EDMA3_TC2_ERROR_INT                             EDMA3_TC2_ERROR_INT_DSP
+#define EDMA3_TC3_ERROR_INT                             EDMA3_TC3_ERROR_INT_DSP
+#else
+#define EDMA3_TC0_ERROR_INT                             (0u)
+#define EDMA3_TC1_ERROR_INT                             (0u)
+#define EDMA3_TC2_ERROR_INT                             (0u)
+#define EDMA3_TC3_ERROR_INT                             (0u)
+#endif
+
+#define EDMA3_TC4_ERROR_INT                             (0u)
+#define EDMA3_TC5_ERROR_INT                             (0u)
+#define EDMA3_TC6_ERROR_INT                             (0u)
+#define EDMA3_TC7_ERROR_INT                             (0u)
 
 /**
  * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
@@ -120,12 +181,12 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  */
 /* EDMA 0 */
 
-#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
-#define EDMA3_0_HWI_INT_CC_ERR                              (7u)
-#define EDMA3_0_HWI_INT_TC0_ERR                             (7u)
-#define EDMA3_0_HWI_INT_TC1_ERR                             (7u)
-#define EDMA3_0_HWI_INT_TC2_ERR                             (7u)
-#define EDMA3_0_HWI_INT_TC3_ERR                             (7u)
+#define EDMA3_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_HWI_INT_CC_ERR                              (7u)
+#define EDMA3_HWI_INT_TC0_ERR                             (10u)
+#define EDMA3_HWI_INT_TC1_ERR                             (10u)
+#define EDMA3_HWI_INT_TC2_ERR                             (10u)
+#define EDMA3_HWI_INT_TC3_ERR                             (10u)
 
 
 /**
@@ -143,7 +204,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
                                                       /* 31     0 */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F00u)  /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFCFF3F00u)  /* TBD */
 
 
 /**
@@ -161,17 +222,17 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  * To allocate more DMA channels or TCCs, one has to modify the event mapping.
  */
 /* DMA channels 32-63 DOES NOT exist in omapl138. */
-#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF033C00u) /* TBD */
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0xFF003C00u) /* TBD */
 
 
 /* Variable which will be used internally for referring number of Event Queues*/
 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
-                                                        EDMA3_0_NUM_EVTQUE,
+                                                        EDMA3_NUM_EVTQUE,
                                                     };
 
 /* Variable which will be used internally for referring number of TCs.        */
 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
-                                                    EDMA3_0_NUM_TC,
+                                                    EDMA3_NUM_TC,
                                                 };
 
 /**
@@ -181,7 +242,8 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 {
     {
-        0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+        EDMA3_CC_XFER_COMPLETION_INT_A8, EDMA3_CC_XFER_COMPLETION_INT_DSP, 0u, 0u,
+        EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO, EDMA3_CC_XFER_COMPLETION_INT_M3VPSS, 0u, 0u,
     },
 };
 
@@ -190,7 +252,7 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
  * error interrupt.
  */
 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
-                                                    EDMA3_0_CC_ERROR_INT,
+                                                    EDMA3_CC_ERROR_INT,
                                                };
 
 /**
@@ -200,10 +262,10 @@ unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
 {
    {
-       EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
-       EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
-       EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
-       EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
+       EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
+       EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
+       EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
+       EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
    }
 };
 
@@ -212,22 +274,40 @@ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =
  * for various EDMA3 interrupts.
  */
 unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
-                                                    EDMA3_0_HWI_INT_XFER_COMP
+                                                    EDMA3_HWI_INT_XFER_COMP
                                                   };
 
 unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
-                                                   EDMA3_0_HWI_INT_CC_ERR
+                                                   EDMA3_HWI_INT_CC_ERR
                                                };
 
 unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
                                                      {
-                                                        EDMA3_0_HWI_INT_TC0_ERR,
-                                                        EDMA3_0_HWI_INT_TC1_ERR,
-                                                        EDMA3_0_HWI_INT_TC2_ERR,
-                                                        EDMA3_0_HWI_INT_TC3_ERR
+                                                        EDMA3_HWI_INT_TC0_ERR,
+                                                        EDMA3_HWI_INT_TC1_ERR,
+                                                        EDMA3_HWI_INT_TC2_ERR,
+                                                        EDMA3_HWI_INT_TC3_ERR
                                                      }
                                                };
 
+/**
+ * \brief Base address as seen from the different cores may be different
+ * And is defined based on the core
+ */
+#ifdef BUILD_CENTAURUS_DSP
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x09000000))
+#define EDMA3_TC0_BASE_ADDR                          ((void *)(0x09800000))
+#define EDMA3_TC1_BASE_ADDR                          ((void *)(0x09900000))
+#define EDMA3_TC2_BASE_ADDR                          ((void *)(0x09A00000))
+#define EDMA3_TC3_BASE_ADDR                          ((void *)(0x09B00000))
+#else
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x49000000))
+#define EDMA3_TC0_BASE_ADDR                          ((void *)(0x49800000))
+#define EDMA3_TC1_BASE_ADDR                          ((void *)(0x49900000))
+#define EDMA3_TC2_BASE_ADDR                          ((void *)(0x49A00000))
+#define EDMA3_TC3_BASE_ADDR                          ((void *)(0x49B00000))
+#endif
+
 /* Driver Object Initialization Configuration */
 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
 {
@@ -242,11 +322,11 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
         /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
         EDMA3_NUM_PARAMSET,
         /** Total number of Event Queues in the EDMA3 Controller              */
-        EDMA3_0_NUM_EVTQUE,
+        EDMA3_NUM_EVTQUE,
         /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
-        EDMA3_0_NUM_TC,
+        EDMA3_NUM_TC,
         /** Number of Regions on this EDMA3 controller                        */
-        EDMA3_0_NUM_REGIONS,
+        EDMA3_NUM_REGIONS,
 
         /**
          * \brief Channel mapping existence
@@ -260,32 +340,32 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
         0u,
 
         /** Global Register Region of CC Registers */
-        (void *)0x09000000u,
+        EDMA3_CC_BASE_ADDR,
         /** Transfer Controller (TC) Registers */
         {
-            (void *)0x09800000u,
-            (void *)0x09900000u,
-            (void *)0x09A00000u,
-            (void *)0x09B00000u,
+               EDMA3_TC0_BASE_ADDR,
+               EDMA3_TC1_BASE_ADDR,
+               EDMA3_TC2_BASE_ADDR,
+               EDMA3_TC3_BASE_ADDR,
             (void *)NULL,
             (void *)NULL,
             (void *)NULL,
             (void *)NULL
         },
         /** Interrupt no. for Transfer Completion */
-        EDMA3_0_CC_XFER_COMPLETION_INT,
+        EDMA3_CC_XFER_COMPLETION_INT,
         /** Interrupt no. for CC Error */
-        EDMA3_0_CC_ERROR_INT,
+        EDMA3_CC_ERROR_INT,
         /** Interrupt no. for TCs Error */
         {
-            EDMA3_0_TC0_ERROR_INT,
-            EDMA3_0_TC1_ERROR_INT,
-            EDMA3_0_TC2_ERROR_INT,
-            EDMA3_0_TC3_ERROR_INT,
-            EDMA3_0_TC4_ERROR_INT,
-            EDMA3_0_TC5_ERROR_INT,
-            EDMA3_0_TC6_ERROR_INT,
-            EDMA3_0_TC7_ERROR_INT
+            EDMA3_TC0_ERROR_INT,
+            EDMA3_TC1_ERROR_INT,
+            EDMA3_TC2_ERROR_INT,
+            EDMA3_TC3_ERROR_INT,
+            EDMA3_TC4_ERROR_INT,
+            EDMA3_TC5_ERROR_INT,
+            EDMA3_TC6_ERROR_INT,
+            EDMA3_TC7_ERROR_INT
         },
 
         /**
@@ -335,8 +415,8 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
             {
             16u,
             16u,
-            0u,
-            0u,
+            16u,
+            16u,
             0u,
             0u,
             0u,
@@ -388,403 +468,462 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
          * All channels need not be mapped, some can be free also.
          */
             {
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1
             }
         },
 };
 
+/**
+ * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
+ * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
+ * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
+ * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
+ *
+ * Only Resources owned by a perticular core are allocated by Driver
+ * Reserved resources are not allocated if requested for any available resource
+ */
+/* Defines for Own DMA channels For different cores */
+/* channels  0 to 31 */
+#define EDMA3_OWN_DMA_CHANNELS_0_A8    (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_0_DSP   (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO    (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_0_M3VPSS    (0xFFFFFFFFu)
+/* Channels 32 to 63 */
+#define EDMA3_OWN_DMA_CHANNELS_1_A8    (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_1_DSP   (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO    (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_1_M3VPSS    (0xFFFFFFFFu)
+
+/* Defines for Own QDMA channels For different cores */
+#define EDMA3_OWN_QDMA_CHANNELS_0_A8    (0x000000FFu)
+#define EDMA3_OWN_QDMA_CHANNELS_0_DSP   (0x000000FFu)
+#define EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO    (0x000000FFu)
+#define EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS    (0x000000FFu)
+
+/* Defines for Own TCCs For different cores */
+#define EDMA3_OWN_TCC_0_A8    (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_0_DSP   (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_0_M3VIDEO    (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_0_M3VPSS    (0xFFFFFFFFu)
+/* Channels 32 to 63 */
+#define EDMA3_OWN_TCC_1_A8    (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_1_DSP   (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_1_M3VIDEO    (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_1_M3VPSS    (0xFFFFFFFFu)
+
+/* Defines for Reserved DMA channels For different cores */
+/* channels  0 to 31 */
+#define EDMA3_RESERVED_DMA_CHANNELS_0_A8    (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_DSP   (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO    (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS    (0x00u)
+/* Channels 32 to 63 */
+#define EDMA3_RESERVED_DMA_CHANNELS_1_A8    (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_DSP   (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO    (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS    (0x00u)
+
+/* Defines for RESERVED QDMA channels For different cores */
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_A8    (0x00u)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_DSP   (0x00u)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO    (0x00u)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS    (0x00u)
+
+/* Defines for RESERVED TCCs For different cores */
+#define EDMA3_RESERVED_TCC_0_A8    (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
+#define EDMA3_RESERVED_TCC_0_DSP   (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0)
+#define EDMA3_RESERVED_TCC_0_M3VIDEO    (0x00u)
+#define EDMA3_RESERVED_TCC_0_M3VPSS    (0x00u)
+/* Channels 32 to 63 */
+#define EDMA3_RESERVED_TCC_1_A8    (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
+#define EDMA3_RESERVED_TCC_1_DSP   (EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1)
+#define EDMA3_RESERVED_TCC_1_M3VIDEO    (0x00u)
+#define EDMA3_RESERVED_TCC_1_M3VPSS    (0x00u)
 
 /* Driver Instance Initialization Configuration */
 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
     {
-        /* Resources owned/reserved by region 0 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x000000FFu},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0x00000000u},
-
-            /* Resources reserved by Region 1 */
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* resvdDmaChannels */
-            /* 31       0 */
-            {0xFF3FF3FFu,
-            /* 63..32 */
-            0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31       0 */
-            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
-            /* 63..32 */
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
-        },
-        /* Resources owned/reserved by region 1 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x000000FFu},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-            /* Resources reserved by Region 1 */
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-            /* resvdDmaChannels */
-            /* 31       0 */
-            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
-            /* 63..32 */
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31       0 */
-            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
-            /* 63..32 */
-            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
-        },
-        /* Resources owned/reserved by region 2 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-
-        /* Resources owned/reserved by region 3 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-
-        /* Resources owned/reserved by region 4 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-
-        /* Resources owned/reserved by region 5 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-
-        /* Resources owned/reserved by region 6 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-
-        /* Resources owned/reserved by region 7 */
-        {
-            /* ownPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* ownDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* ownQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* ownTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdPaRAMSets */
-            /* 31     0     63    32     95    64     127   96 */
-            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 159  128     191  160     223  192     255  224 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 287  256     319  288     351  320     383  352 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-            /* 415  384     447  416     479  448     511  480 */
-             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-            /* resvdDmaChannels */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-
-            /* resvdQdmaChannels */
-            /* 31     0 */
-            {0x00000000u},
-
-            /* resvdTccs */
-            /* 31     0     63    32 */
-            {0x00000000u, 0x00000000u},
-        },
-    }
-};
+               /* EDMA3 INSTANCE# 0 */
+               {
+                       /* Resources owned/reserved by region 0 (Configuration for Centaurus A8 Core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_OWN_DMA_CHANNELS_0_A8, EDMA3_OWN_DMA_CHANNELS_1_A8},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {EDMA3_OWN_QDMA_CHANNELS_0_A8},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {EDMA3_OWN_TCC_0_A8, EDMA3_OWN_TCC_1_A8},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_RESERVED_DMA_CHANNELS_0_A8, EDMA3_RESERVED_DMA_CHANNELS_1_A8},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {EDMA3_RESERVED_QDMA_CHANNELS_0_A8},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {EDMA3_RESERVED_TCC_0_A8, EDMA3_RESERVED_TCC_1_A8},
+                       },
+
+               /* Resources owned/reserved by region 1 (Configuration for Centaurus DSP Core)*/
+                   {
+                       /* ownPaRAMSets */
+                       /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                       /* ownDmaChannels */
+                       /* 31     0     63    32 */
+                       {EDMA3_OWN_DMA_CHANNELS_0_DSP, EDMA3_OWN_DMA_CHANNELS_1_DSP},
+
+                       /* ownQdmaChannels */
+                       /* 31     0 */
+                       {EDMA3_OWN_QDMA_CHANNELS_0_DSP},
+
+                       /* ownTccs */
+                       /* 31     0     63    32 */
+                       {EDMA3_OWN_TCC_0_DSP, EDMA3_OWN_TCC_1_DSP},
+
+                       /* resvdPaRAMSets */
+                       /* 31     0     63    32     95    64     127   96 */
+                       {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                       /* 159  128     191  160     223  192     255  224 */
+                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       /* 287  256     319  288     351  320     383  352 */
+                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       /* 415  384     447  416     479  448     511  480 */
+                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                       /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_RESERVED_DMA_CHANNELS_0_DSP, EDMA3_RESERVED_DMA_CHANNELS_1_DSP},
+
+                       /* resvdQdmaChannels */
+                       /* 31     0 */
+                       {EDMA3_RESERVED_QDMA_CHANNELS_0_DSP},
+
+                       /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {EDMA3_RESERVED_TCC_0_DSP, EDMA3_RESERVED_TCC_1_DSP},
+                   },
+
+               /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 (Configuration for Centaurus M3VIDEO Core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO, EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {EDMA3_OWN_TCC_0_M3VIDEO, EDMA3_OWN_TCC_0_M3VIDEO},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO, EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {EDMA3_RESERVED_TCC_0_M3VIDEO, EDMA3_RESERVED_TCC_1_M3VIDEO},
+                       },
+
+               /* Resources owned/reserved by region 5 (Configuration for Centaurus M3VPSS Core)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_OWN_DMA_CHANNELS_0_M3VPSS, EDMA3_OWN_DMA_CHANNELS_1_M3VPSS},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {EDMA3_OWN_TCC_0_M3VPSS, EDMA3_OWN_TCC_1_M3VPSS},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS, EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {EDMA3_RESERVED_TCC_0_M3VPSS, EDMA3_RESERVED_TCC_1_M3VPSS},
+                       },
+
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+           },
+    };
 
 /* Driver Instance Cross bar event to channel map Initialization Configuration */
 EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
@@ -796,7 +935,7 @@ EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES
             -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
             -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
+            -1, 26, 27, -1, -1, -1, -1
         },
         /* Event to channel map for region 1 */
         {
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_cfg.c
deleted file mode 100644 (file)
index f9f7d74..0000000
+++ /dev/null
@@ -1,824 +0,0 @@
-/*
- * sample_dm740_cfg.c
- *
- * Platform specific EDMA3 hardware related information like number of transfer
- * controllers, various interrupt ids etc. It is used while interrupts
- * enabling / disabling. It needs to be ported for different SoCs.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sdo/edma3/drv/edma3_drv.h>
-
-/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES                    1u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
-
-/* Number of DSPs present in the system */
-#define NUM_DSPS                                       1u
-const unsigned int numDsps = NUM_DSPS;
-
-/* Determine the processor id by reading DNUM register. */
-unsigned short determineProcId()
-       {
-#if 0
-       volatile unsigned int *addr;
-       unsigned int core_no;
-
-    /* Identify the core number */
-    addr = (unsigned int *)(CGEM_REG_START+0x40000);
-    core_no = ((*addr) & 0x000F0000)>>16;
-
-       return core_no;
-#endif
-       return 4;
-       }
-
-signed char*  getGlobalAddr(signed char* addr)
-{
-     return (addr); /* The address is already a global address */
-}
-
-unsigned short isGblConfigRequired(unsigned int dspNum)
-       {
-       (void) dspNum;
-
-       return 0;
-       }
-
-/* Semaphore handles */
-EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
-
-/** Number of PaRAM Sets available */
-#define EDMA3_NUM_PARAMSET                             (512u)
-/** Number of TCCS available */
-#define EDMA3_NUM_TCC                                  (64u)
-/** Number of Event Queues available */
-#define EDMA3_NUM_EVTQUE                                (4u)
-/** Number of Transfer Controllers available */
-#define EDMA3_NUM_TC                                    (4u)
-/** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT                    (62)
-/** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT                              (46u)
-/** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT                             (0u)
-#define EDMA3_TC1_ERROR_INT                             (0u)
-#define EDMA3_TC2_ERROR_INT                             (0u)
-#define EDMA3_TC3_ERROR_INT                             (0u)
-#define EDMA3_TC4_ERROR_INT                             (0u)
-#define EDMA3_TC5_ERROR_INT                             (0u)
-#define EDMA3_TC6_ERROR_INT                             (0u)
-#define EDMA3_TC7_ERROR_INT                             (0u)
-
-/**
-* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
-* ECM events (SoC specific). These ECM events come
-* under ECM block XXX (handling those specific ECM events). Normally, block
-* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
-* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
-* is mapped to a specific HWI_INT YYY in the tcf file.
-* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
-* to transfer completion interrupt.
-* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
-* to CC error interrupts.
-* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
-* to TC error interrupts.
-*/
-#define EDMA3_HWI_INT_XFER_COMP                                                        (7u)
-#define EDMA3_HWI_INT_CC_ERR                                                   (11u)
-#define EDMA3_HWI_INT_TC_ERR                                                   (11u)
-
-
-/**
- * \brief Mapping of DMA channels 0-31 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                                                                         /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
-
-/**
- * \brief Mapping of DMA channels 32-63 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                                                                         /* 63     32 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
-
-/* Variable which will be used internally for referring number of Event Queues. */
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
-
-/* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
-
-/**
- * Variable which will be used internally for referring transfer completion
- * interrupt.
- */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
-                                                       {
-                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
-                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
-                                                       },
-                        };
-
-/**
- * Variable which will be used internally for referring channel controller's
- * error interrupt.
- */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
-
-/**
- * Variable which will be used internally for referring transfer controllers'
- * error interrupts.
- */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
-                                {
-                                EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
-                                EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
-                                EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
-                                EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
-                                }
-                            };
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
-unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
-unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
-
-
-/* Driver Object Initialization Configuration */
-EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
-       {
-           {
-           /** Total number of DMA Channels supported by the EDMA3 Controller */
-           64u,
-           /** Total number of QDMA Channels supported by the EDMA3 Controller */
-           8u,
-           /** Total number of TCCs supported by the EDMA3 Controller */
-           64u,
-           /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-           512u,
-           /** Total number of Event Queues in the EDMA3 Controller */
-           4u,
-           /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-           4u,
-           /** Number of Regions on this EDMA3 controller */
-           6u,
-
-           /**
-            * \brief Channel mapping existence
-            * A value of 0 (No channel mapping) implies that there is fixed association
-            * for a channel number to a parameter entry number or, in other words,
-            * PaRAM entry n corresponds to channel n.
-            */
-           1u,
-
-           /** Existence of memory protection feature */
-           1u,
-
-           /** Global Register Region of CC Registers */
-           (void *)0x49000000u,
-           /** Transfer Controller (TC) Registers */
-               {
-               (void *)0x49800000u,
-               (void *)0x49900000u,
-               (void *)0x49A00000u,
-               (void *)0x49B00000u,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL
-               },
-           /** Interrupt no. for Transfer Completion */
-           EDMA3_CC_XFER_COMPLETION_INT,
-           /** Interrupt no. for CC Error */
-           EDMA3_CC_ERROR_INT,
-           /** Interrupt no. for TCs Error */
-               {
-               EDMA3_TC0_ERROR_INT,
-               EDMA3_TC1_ERROR_INT,
-               EDMA3_TC2_ERROR_INT,
-               EDMA3_TC3_ERROR_INT,
-               EDMA3_TC4_ERROR_INT,
-               EDMA3_TC5_ERROR_INT,
-               EDMA3_TC6_ERROR_INT,
-               EDMA3_TC7_ERROR_INT
-               },
-
-           /**
-            * \brief EDMA3 TC priority setting
-            *
-            * User can program the priority of the Event Queues
-            * at a system-wide level.  This means that the user can set the
-            * priority of an IO initiated by either of the TCs (Transfer Controllers)
-            * relative to IO initiated by the other bus masters on the
-            * device (ARM, DSP, USB, etc)
-            */
-               {
-               0u,
-               1u,
-               2u,
-               3u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-           /**
-            * \brief To Configure the Threshold level of number of events
-            * that can be queued up in the Event queues. EDMA3CC error register
-            * (CCERR) will indicate whether or not at any instant of time the
-            * number of events queued up in any of the event queues exceeds
-            * or equals the threshold/watermark value that is set
-            * in the queue watermark threshold register (QWMTHRA).
-            */
-               {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-           /**
-            * \brief To Configure the Default Burst Size (DBS) of TCs.
-            * An optimally-sized command is defined by the transfer controller
-            * default burst size (DBS). Different TCs can have different
-            * DBS values. It is defined in Bytes.
-            */
-               {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-           /**
-            * \brief Mapping from each DMA channel to a Parameter RAM set,
-            * if it exists, otherwise of no use.
-            */
-            {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
-            },
-
-            /**
-             * \brief Mapping from each DMA channel to a TCC. This specific
-             * TCC code will be returned when the transfer is completed
-             * on the mapped channel.
-             */
-            {
-            0u, 1u, 2u, 3u,
-            4u, 5u, 6u, 7u,
-            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u,
-            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            24u, 25u, 26u, 27u,
-            28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
-            },
-
-
-           /**
-            * \brief Mapping of DMA channels to Hardware Events from
-            * various peripherals, which use EDMA for data transfer.
-            * All channels need not be mapped, some can be free also.
-            */
-               {
-               0x00000000u,
-               0x00000000u
-               },
-               },
-       };
-
-
-/* Driver Instance Initialization Configuration */
-EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-       {
-               /* EDMA3 INSTANCE# 0 */
-               {
-                       /* Resources owned/reserved by region 0 */
-                       {
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000001u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-
-               /* Resources reserved by Region 0 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 1 */
-                   {
-                       /* ownPaRAMSets */
-                       /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000002u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 1 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                   },
-
-               /* Resources owned/reserved by region 2 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000004u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 2 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 3 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000008u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 3 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 4 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000008u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 4 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 5 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000008u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 5 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 6 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 7 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-           },
-       };
-
-/* Driver Instance Cross bar event to channel map Initialization Configuration */
-EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-        /* Event to channel map for region 0 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 1 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, 26, 27, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 2 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 3 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 4 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 5 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 6 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 7 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-    }
-};
-
-/* End of File */
-
-
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3video_int_reg.c
deleted file mode 100644 (file)
index 35459d6..0000000
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * sample_dm740_int_reg.c
- *
- * Platform specific interrupt registration and un-registration routines.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sysbios/knl/Semaphore.h>
-
-#include <ti/sysbios/hal/Hwi.h>
-#include <xdc/runtime/Error.h>
-#include <xdc/runtime/System.h>
-
-#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
-
-// #include <stdio.h>
-/**
-  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
-  * (Not all TC error ISRs need to be registered, register only for the
-  * available Transfer Controllers).
-  */
-void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
-                                                {
-                                                &lisrEdma3TC0ErrHandler0,
-                                                &lisrEdma3TC1ErrHandler0,
-                                                &lisrEdma3TC2ErrHandler0,
-                                                &lisrEdma3TC3ErrHandler0,
-                                                &lisrEdma3TC4ErrHandler0,
-                                                &lisrEdma3TC5ErrHandler0,
-                                                &lisrEdma3TC6ErrHandler0,
-                                                &lisrEdma3TC7ErrHandler0,
-                                                };
-
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
-
-/* External Instance Specific Configuration Structure */
-extern EDMA3_DRV_GblXbarToChanConfigParams 
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
-
-typedef struct  {
-    volatile Uint32 DSP_INTMUX[21];
-    volatile Uint32 DUCATI_INTMUX[15];
-    volatile Uint32 TPCC_EVTMUX[16];
-    volatile Uint32 TIMER_EVTCAPT;
-    volatile Uint32 GPIO_MUX;
-} CSL_IntmuxRegs;
-
-typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
-
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
-
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
-
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
-
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
-
-
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)
-#define EDMA3_NUM_TCC                     (64u)
-
-/*
- * Forward decleration
- */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
-                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
-
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-extern unsigned int hwIntXferComp;
-extern unsigned int hwIntCcErr;
-extern unsigned int hwIntTcErr;
-
-extern unsigned int dsp_num;
-/* This variable has to be used as an extern */
-//unsigned int gpp_num = 4;
-
-Hwi_Handle hwiCCXferCompInt;
-Hwi_Handle hwiCCErrInt;
-Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
-
-/**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
-    {
-    static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-    Hwi_Params hwiParams; 
-    Error_Block      eb;
-
-    /* Initialize the Error Block                                             */
-    Error_init(&eb);
-        
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    /* Initialize the HWI parameters with user specified values */
-    Hwi_Params_init(&hwiParams);
-    
-    /* argument for the ISR */
-    hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-       //hwiParams.priority = hwIntXferComp;
-       //hwiParams.enableInt = TRUE;
-    
-    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
-                                       (&lisrEdma3ComplHandler0),
-                                       (const Hwi_Params *) (&hwiParams),
-                                       &eb);
-    if (TRUE == Error_check(&eb))
-    {
-        System_printf("HWI Create Failed\n",Error_getCode(&eb));
-    }
-
-       
-       #if 0
-    /* Initialize the HWI parameters with user specified values */
-    Hwi_Params_init(&hwiParams);
-    /* argument for the ISR */
-    hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-       hwiParams.priority = hwIntCcErr;
-       //hwiParams.enableInt = TRUE;
-       
-       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
-                (&lisrEdma3CCErrHandler0),
-                (const Hwi_Params *) (&hwiParams),
-                &eb);
-
-    if (TRUE == Error_check(&eb))
-    {
-        System_printf("HWI Create Failed\n",Error_getCode(&eb));
-    }
-
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        /* Initialize the HWI parameters with user specified values */
-        Hwi_Params_init(&hwiParams);
-        /* argument for the ISR */
-        hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-        hwiParams.priority = hwIntTcErr;
-               //hwiParams.enableInt = TRUE;
-        
-        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
-                    (ptrEdma3TcIsrHandler[numTc]),
-                    (const Hwi_Params *) (&hwiParams),
-                    &eb);
-        if (TRUE == Error_check(&eb))
-        {
-            System_printf("HWI Create Failed\n",Error_getCode(&eb));
-        }
-        numTc++;
-       }
-   /**
-    * Enabling the HWI_ID.
-    * EDMA3 interrupts (transfer completion, CC error etc.)
-    * correspond to different ECM events (SoC specific). These ECM events come
-    * under ECM block XXX (handling those specific ECM events). Normally, block
-    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
-    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
-    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
-    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
-    * API C64_enableIER(), in which the YYY bit is SET.
-    */
-    Hwi_enableInterrupt(ccErrorInt[edma3Id]);
-    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
-    numTc = 0;
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
-        numTc++;
-       }
-               
-       #endif
-
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
-    {
-       static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    Hwi_delete(&hwiCCXferCompInt);
-    Hwi_delete(&hwiCCErrInt);
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        Hwi_delete(&hwiTCErrInt[numTc]);
-        numTc++;
-       }
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**
- * \brief   sampleMapXbarEvtToChan
- *
- * This function reads from the sample configuration structure which specifies 
- * cross bar events mapped to DMA channel.
- *
- * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
-                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
-       {
-    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
-
-       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
-               (chanNum != NULL) &&
-               (edmaGblXbarConfig != NULL))
-               {
-               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
-               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
-               if (edmaChanNum != -1)
-                       {
-                       *chanNum = edmaChanNum;
-                       edma3Result = EDMA3_DRV_SOK;
-                       }
-               }
-       return (edma3Result);
-       }
-       
-
-/**
- * \brief   sampleConfigScr
- *
- * This function configures control config registers for the cross bar events 
- * mapped to the EDMA channel.
- *
- * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
-       {
-    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
-    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);
-
-
-       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
-               (chanNum < EDMA3_NUM_TCC))
-               {
-               scrRegOffset = chanNum / 4;
-               scrChanOffset = chanNum - (scrRegOffset * 4);
-               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
-               
-               switch(scrChanOffset)
-                       {
-                       case 0:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
-                               break;
-                       case 1:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
-                               break;
-                       case 2:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
-                               break;
-                       case 3:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
-                               break;
-                       default:
-                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-                               break;
-                       }
-               }
-       else
-               {
-               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-               }
-       return edma3Result;
-       }
-
-
-EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
-                                   unsigned int edma3Id)
-    {
-    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
-    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
-                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
-    if (hEdma != NULL)
-        {
-        retVal = EDMA3_DRV_initXbarEventMap(hEdma, 
-                                                                       sampleXbarToChanConfig, 
-                                                                       &sampleMapXbarEvtToChan, 
-                                                                       &sampleConfigScr);
-        }
-    
-    return retVal;
-    }
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_cfg.c
deleted file mode 100644 (file)
index 12576f2..0000000
+++ /dev/null
@@ -1,824 +0,0 @@
-/*
- * sample_dm740_cfg.c
- *
- * Platform specific EDMA3 hardware related information like number of transfer
- * controllers, various interrupt ids etc. It is used while interrupts
- * enabling / disabling. It needs to be ported for different SoCs.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sdo/edma3/drv/edma3_drv.h>
-
-/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES                    1u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
-
-/* Number of DSPs present in the system */
-#define NUM_DSPS                                       1u
-const unsigned int numDsps = NUM_DSPS;
-
-/* Determine the processor id by reading DNUM register. */
-unsigned short determineProcId()
-       {
-#if 0
-       volatile unsigned int *addr;
-       unsigned int core_no;
-
-    /* Identify the core number */
-    addr = (unsigned int *)(CGEM_REG_START+0x40000);
-    core_no = ((*addr) & 0x000F0000)>>16;
-
-       return core_no;
-#endif
-       return 5;
-       }
-
-signed char*  getGlobalAddr(signed char* addr)
-{
-     return (addr); /* The address is already a global address */
-}
-
-unsigned short isGblConfigRequired(unsigned int dspNum)
-       {
-       (void) dspNum;
-
-       return 0;
-       }
-
-/* Semaphore handles */
-EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
-
-/** Number of PaRAM Sets available */
-#define EDMA3_NUM_PARAMSET                             (512u)
-/** Number of TCCS available */
-#define EDMA3_NUM_TCC                                  (64u)
-/** Number of Event Queues available */
-#define EDMA3_NUM_EVTQUE                                (4u)
-/** Number of Transfer Controllers available */
-#define EDMA3_NUM_TC                                    (4u)
-/** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT                    (63)
-/** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT                              (46u)
-/** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT                             (0u)
-#define EDMA3_TC1_ERROR_INT                             (0u)
-#define EDMA3_TC2_ERROR_INT                             (0u)
-#define EDMA3_TC3_ERROR_INT                             (0u)
-#define EDMA3_TC4_ERROR_INT                             (0u)
-#define EDMA3_TC5_ERROR_INT                             (0u)
-#define EDMA3_TC6_ERROR_INT                             (0u)
-#define EDMA3_TC7_ERROR_INT                             (0u)
-
-/**
-* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
-* ECM events (SoC specific). These ECM events come
-* under ECM block XXX (handling those specific ECM events). Normally, block
-* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
-* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
-* is mapped to a specific HWI_INT YYY in the tcf file.
-* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
-* to transfer completion interrupt.
-* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
-* to CC error interrupts.
-* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
-* to TC error interrupts.
-*/
-#define EDMA3_HWI_INT_XFER_COMP                                                        (7u)
-#define EDMA3_HWI_INT_CC_ERR                                                   (11u)
-#define EDMA3_HWI_INT_TC_ERR                                                   (11u)
-
-
-/**
- * \brief Mapping of DMA channels 0-31 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                                                                         /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
-
-/**
- * \brief Mapping of DMA channels 32-63 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                                                                         /* 63     32 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
-
-/* Variable which will be used internally for referring number of Event Queues. */
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
-
-/* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
-
-/**
- * Variable which will be used internally for referring transfer completion
- * interrupt.
- */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
-                                                       {
-                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
-                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
-                                                       },
-                        };
-
-/**
- * Variable which will be used internally for referring channel controller's
- * error interrupt.
- */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
-
-/**
- * Variable which will be used internally for referring transfer controllers'
- * error interrupts.
- */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
-                                {
-                                EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
-                                EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
-                                EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
-                                EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
-                                }
-                            };
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
-unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
-unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
-
-
-/* Driver Object Initialization Configuration */
-EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
-       {
-           {
-           /** Total number of DMA Channels supported by the EDMA3 Controller */
-           64u,
-           /** Total number of QDMA Channels supported by the EDMA3 Controller */
-           8u,
-           /** Total number of TCCs supported by the EDMA3 Controller */
-           64u,
-           /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-           512u,
-           /** Total number of Event Queues in the EDMA3 Controller */
-           4u,
-           /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-           4u,
-           /** Number of Regions on this EDMA3 controller */
-           6u,
-
-           /**
-            * \brief Channel mapping existence
-            * A value of 0 (No channel mapping) implies that there is fixed association
-            * for a channel number to a parameter entry number or, in other words,
-            * PaRAM entry n corresponds to channel n.
-            */
-           1u,
-
-           /** Existence of memory protection feature */
-           1u,
-
-           /** Global Register Region of CC Registers */
-           (void *)0x49000000u,
-           /** Transfer Controller (TC) Registers */
-               {
-               (void *)0x49800000u,
-               (void *)0x49900000u,
-               (void *)0x49A00000u,
-               (void *)0x49B00000u,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL
-               },
-           /** Interrupt no. for Transfer Completion */
-           EDMA3_CC_XFER_COMPLETION_INT,
-           /** Interrupt no. for CC Error */
-           EDMA3_CC_ERROR_INT,
-           /** Interrupt no. for TCs Error */
-               {
-               EDMA3_TC0_ERROR_INT,
-               EDMA3_TC1_ERROR_INT,
-               EDMA3_TC2_ERROR_INT,
-               EDMA3_TC3_ERROR_INT,
-               EDMA3_TC4_ERROR_INT,
-               EDMA3_TC5_ERROR_INT,
-               EDMA3_TC6_ERROR_INT,
-               EDMA3_TC7_ERROR_INT
-               },
-
-           /**
-            * \brief EDMA3 TC priority setting
-            *
-            * User can program the priority of the Event Queues
-            * at a system-wide level.  This means that the user can set the
-            * priority of an IO initiated by either of the TCs (Transfer Controllers)
-            * relative to IO initiated by the other bus masters on the
-            * device (ARM, DSP, USB, etc)
-            */
-               {
-               0u,
-               1u,
-               2u,
-               3u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-           /**
-            * \brief To Configure the Threshold level of number of events
-            * that can be queued up in the Event queues. EDMA3CC error register
-            * (CCERR) will indicate whether or not at any instant of time the
-            * number of events queued up in any of the event queues exceeds
-            * or equals the threshold/watermark value that is set
-            * in the queue watermark threshold register (QWMTHRA).
-            */
-               {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-           /**
-            * \brief To Configure the Default Burst Size (DBS) of TCs.
-            * An optimally-sized command is defined by the transfer controller
-            * default burst size (DBS). Different TCs can have different
-            * DBS values. It is defined in Bytes.
-            */
-               {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-           /**
-            * \brief Mapping from each DMA channel to a Parameter RAM set,
-            * if it exists, otherwise of no use.
-            */
-            {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
-            },
-
-            /**
-             * \brief Mapping from each DMA channel to a TCC. This specific
-             * TCC code will be returned when the transfer is completed
-             * on the mapped channel.
-             */
-            {
-            0u, 1u, 2u, 3u,
-            4u, 5u, 6u, 7u,
-            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u,
-            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            24u, 25u, 26u, 27u,
-            28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
-            },
-
-
-           /**
-            * \brief Mapping of DMA channels to Hardware Events from
-            * various peripherals, which use EDMA for data transfer.
-            * All channels need not be mapped, some can be free also.
-            */
-               {
-               0x00000000u,
-               0x00000000u
-               },
-               },
-       };
-
-
-/* Driver Instance Initialization Configuration */
-EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-       {
-               /* EDMA3 INSTANCE# 0 */
-               {
-                       /* Resources owned/reserved by region 0 */
-                       {
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000001u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-
-               /* Resources reserved by Region 0 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 1 */
-                   {
-                       /* ownPaRAMSets */
-                       /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000002u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 1 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                   },
-
-               /* Resources owned/reserved by region 2 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000004u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 2 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 3 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000008u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 3 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 4 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000008u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 4 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 5 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000008u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 5 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 6 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 7 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-           },
-       };
-
-/* Driver Instance Cross bar event to channel map Initialization Configuration */
-EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-{
-    /* EDMA3 INSTANCE# 0 */
-    {
-        /* Event to channel map for region 0 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 1 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, 26, 27, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 2 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 3 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 4 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 5 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 6 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-        /* Event to channel map for region 7 */
-        {
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1, -1,
-            -1, -1, -1, -1, -1, -1, -1
-        },
-    }
-};
-
-/* End of File */
-
-
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_m3vpss_int_reg.c
deleted file mode 100644 (file)
index 35459d6..0000000
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * sample_dm740_int_reg.c
- *
- * Platform specific interrupt registration and un-registration routines.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sysbios/knl/Semaphore.h>
-
-#include <ti/sysbios/hal/Hwi.h>
-#include <xdc/runtime/Error.h>
-#include <xdc/runtime/System.h>
-
-#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
-
-// #include <stdio.h>
-/**
-  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
-  * (Not all TC error ISRs need to be registered, register only for the
-  * available Transfer Controllers).
-  */
-void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
-                                                {
-                                                &lisrEdma3TC0ErrHandler0,
-                                                &lisrEdma3TC1ErrHandler0,
-                                                &lisrEdma3TC2ErrHandler0,
-                                                &lisrEdma3TC3ErrHandler0,
-                                                &lisrEdma3TC4ErrHandler0,
-                                                &lisrEdma3TC5ErrHandler0,
-                                                &lisrEdma3TC6ErrHandler0,
-                                                &lisrEdma3TC7ErrHandler0,
-                                                };
-
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
-extern unsigned int numEdma3Tc[];
-
-/* External Instance Specific Configuration Structure */
-extern EDMA3_DRV_GblXbarToChanConfigParams 
-                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];
-
-typedef struct  {
-    volatile Uint32 DSP_INTMUX[21];
-    volatile Uint32 DUCATI_INTMUX[15];
-    volatile Uint32 TPCC_EVTMUX[16];
-    volatile Uint32 TIMER_EVTCAPT;
-    volatile Uint32 GPIO_MUX;
-} CSL_IntmuxRegs;
-
-typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;
-
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)
-
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)
-
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)
-
-
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)
-#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)
-
-
-#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)
-#define EDMA3_NUM_TCC                     (64u)
-
-/*
- * Forward decleration
- */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
-                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum);
-
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-extern unsigned int hwIntXferComp;
-extern unsigned int hwIntCcErr;
-extern unsigned int hwIntTcErr;
-
-extern unsigned int dsp_num;
-/* This variable has to be used as an extern */
-//unsigned int gpp_num = 4;
-
-Hwi_Handle hwiCCXferCompInt;
-Hwi_Handle hwiCCErrInt;
-Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];
-
-/**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
-    {
-    static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-    Hwi_Params hwiParams; 
-    Error_Block      eb;
-
-    /* Initialize the Error Block                                             */
-    Error_init(&eb);
-        
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    /* Initialize the HWI parameters with user specified values */
-    Hwi_Params_init(&hwiParams);
-    
-    /* argument for the ISR */
-    hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-       //hwiParams.priority = hwIntXferComp;
-       //hwiParams.enableInt = TRUE;
-    
-    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],
-                                       (&lisrEdma3ComplHandler0),
-                                       (const Hwi_Params *) (&hwiParams),
-                                       &eb);
-    if (TRUE == Error_check(&eb))
-    {
-        System_printf("HWI Create Failed\n",Error_getCode(&eb));
-    }
-
-       
-       #if 0
-    /* Initialize the HWI parameters with user specified values */
-    Hwi_Params_init(&hwiParams);
-    /* argument for the ISR */
-    hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-       hwiParams.priority = hwIntCcErr;
-       //hwiParams.enableInt = TRUE;
-       
-       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],
-                (&lisrEdma3CCErrHandler0),
-                (const Hwi_Params *) (&hwiParams),
-                &eb);
-
-    if (TRUE == Error_check(&eb))
-    {
-        System_printf("HWI Create Failed\n",Error_getCode(&eb));
-    }
-
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        /* Initialize the HWI parameters with user specified values */
-        Hwi_Params_init(&hwiParams);
-        /* argument for the ISR */
-        hwiParams.arg = edma3Id;
-       /* set the priority ID     */
-        hwiParams.priority = hwIntTcErr;
-               //hwiParams.enableInt = TRUE;
-        
-        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],
-                    (ptrEdma3TcIsrHandler[numTc]),
-                    (const Hwi_Params *) (&hwiParams),
-                    &eb);
-        if (TRUE == Error_check(&eb))
-        {
-            System_printf("HWI Create Failed\n",Error_getCode(&eb));
-        }
-        numTc++;
-       }
-   /**
-    * Enabling the HWI_ID.
-    * EDMA3 interrupts (transfer completion, CC error etc.)
-    * correspond to different ECM events (SoC specific). These ECM events come
-    * under ECM block XXX (handling those specific ECM events). Normally, block
-    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
-    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
-    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
-    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
-    * API C64_enableIER(), in which the YYY bit is SET.
-    */
-    Hwi_enableInterrupt(ccErrorInt[edma3Id]);
-    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);
-    numTc = 0;
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);
-        numTc++;
-       }
-               
-       #endif
-
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
-    {
-       static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    Hwi_delete(&hwiCCXferCompInt);
-    Hwi_delete(&hwiCCErrInt);
-    while (numTc < numEdma3Tc[edma3Id])
-           {
-        Hwi_delete(&hwiTCErrInt[numTc]);
-        numTc++;
-       }
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**
- * \brief   sampleMapXbarEvtToChan
- *
- * This function reads from the sample configuration structure which specifies 
- * cross bar events mapped to DMA channel.
- *
- * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,
-                 unsigned int *chanNum,
-                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)
-       {
-    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-    unsigned int xbarEvtNum = 0;
-    int          edmaChanNum = 0;
-
-       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
-               (chanNum != NULL) &&
-               (edmaGblXbarConfig != NULL))
-               {
-               xbarEvtNum = eventNum - EDMA3_NUM_TCC;
-               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];
-               if (edmaChanNum != -1)
-                       {
-                       *chanNum = edmaChanNum;
-                       edma3Result = EDMA3_DRV_SOK;
-                       }
-               }
-       return (edma3Result);
-       }
-       
-
-/**
- * \brief   sampleConfigScr
- *
- * This function configures control config registers for the cross bar events 
- * mapped to the EDMA channel.
- *
- * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,
-                                  unsigned int chanNum)
-       {
-    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;
-    unsigned int scrChanOffset = 0;
-    unsigned int scrRegOffset  = 0;
-    unsigned int xBarEvtNum    = 0;
-    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);
-
-
-       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
-               (chanNum < EDMA3_NUM_TCC))
-               {
-               scrRegOffset = chanNum / 4;
-               scrChanOffset = chanNum - (scrRegOffset * 4);
-               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;
-               
-               switch(scrChanOffset)
-                       {
-                       case 0:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
-                               break;
-                       case 1:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & 
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
-                               break;
-                       case 2:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & 
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));
-                               break;
-                       case 3:
-                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
-                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & 
-                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));
-                               break;
-                       default:
-                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-                               break;
-                       }
-               }
-       else
-               {
-               edma3Result = EDMA3_DRV_E_INVALID_PARAM;
-               }
-       return edma3Result;
-       }
-
-
-EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, 
-                                   unsigned int edma3Id)
-    {
-    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;
-    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =
-                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);
-    if (hEdma != NULL)
-        {
-        retVal = EDMA3_DRV_initXbarEventMap(hEdma, 
-                                                                       sampleXbarToChanConfig, 
-                                                                       &sampleMapXbarEvtToChan, 
-                                                                       &sampleConfigScr);
-        }
-    
-    return retVal;
-    }
index f5e15ee9dac26b554071e5de442c046ec7902b8c..a15f8908f70bff39006ca0fde02275b0b051b961 100644 (file)
@@ -61,7 +61,18 @@ unsigned short determineProcId()
 
        return core_no;
 #endif
+
+#ifdef BUILD_NETRA_A8
+       return 0;
+#elif defined BUILD_NETRA_DSP
+       return 1;
+#elif defined BUILD_NETRA_M3VPSS
+       return 4;
+#elif defined BUILD_NETRA_M3VIDEO
+       return 5;
+#else
        return 1;
+#endif
        }
 
 signed char*  getGlobalAddr(signed char* addr)
@@ -72,8 +83,11 @@ signed char*  getGlobalAddr(signed char* addr)
 unsigned short isGblConfigRequired(unsigned int dspNum)
        {
        (void) dspNum;
-
+#ifdef BUILD_NETRA_DSP
        return 1;
+#else
+       return 0;
+#endif
        }
 
 /* Semaphore handles */
@@ -87,15 +101,61 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 #define EDMA3_NUM_EVTQUE                                (4u)
 /** Number of Transfer Controllers available */
 #define EDMA3_NUM_TC                                    (4u)
+
 /** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT                    (20u)
+#define EDMA3_CC_XFER_COMPLETION_INT_A8                 (12u)
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (20u)
+#define EDMA3_CC_XFER_COMPLETION_INT_M3VPSS             (63u)
+#define EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO            (62u)
+
+#ifdef BUILD_NETRA_A8
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A8
+#elif defined BUILD_NETRA_DSP
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP
+#elif defined BUILD_NETRA_M3VIDEO
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO
+#elif defined BUILD_NETRA_M3VPSS
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_M3VPSS
+#else
+#define EDMA3_CC_XFER_COMPLETION_INT                    {0u}
+#endif
+
 /** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT                              (21u)
+#define EDMA3_CC_ERROR_INT_A8                           (14u)
+#define EDMA3_CC_ERROR_INT_DSP                          (21u)
+
+#ifdef BUILD_NETRA_A8
+#define EDMA3_CC_ERROR_INT                              {EDMA3_CC_ERROR_INT_A8}
+#elif defined BUILD_NETRA_DSP
+#define EDMA3_CC_ERROR_INT                              {EDMA3_CC_ERROR_INT_DSP}
+#else
+#define EDMA3_CC_ERROR_INT                              (0u)
+#endif
+
 /** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT                             (22u)
+#define EDMA3_TC0_ERROR_INT_DSP                         (22u)
+#define EDMA3_TC0_ERROR_INT_A8                          (112u)
+#define EDMA3_TC1_ERROR_INT_A8                          (113u)
+#define EDMA3_TC2_ERROR_INT_A8                          (114u)
+#define EDMA3_TC3_ERROR_INT_A8                          (115u)
+
+#ifdef BUILD_NETRA_A8
+#define EDMA3_TC0_ERROR_INT                             {EDMA3_TC0_ERROR_INT_A8}
+#define EDMA3_TC1_ERROR_INT                             {EDMA3_TC0_ERROR_INT_A8}
+#define EDMA3_TC2_ERROR_INT                             {EDMA3_TC0_ERROR_INT_A8}
+#define EDMA3_TC3_ERROR_INT                             {EDMA3_TC0_ERROR_INT_A8}
+#elif defined BUILD_NETRA_DSP
+#define EDMA3_TC0_ERROR_INT                             {EDMA3_TC0_ERROR_INT_DSP}
+#define EDMA3_TC1_ERROR_INT                             (0u)
+#define EDMA3_TC2_ERROR_INT                             (0u)
+#define EDMA3_TC3_ERROR_INT                             (0u)
+#else
+#define EDMA3_TC0_ERROR_INT                             (0u)
 #define EDMA3_TC1_ERROR_INT                             (0u)
 #define EDMA3_TC2_ERROR_INT                             (0u)
 #define EDMA3_TC3_ERROR_INT                             (0u)
+#endif
+
 #define EDMA3_TC4_ERROR_INT                             (0u)
 #define EDMA3_TC5_ERROR_INT                             (0u)
 #define EDMA3_TC6_ERROR_INT                             (0u)
@@ -166,8 +226,8 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
  */
 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
                                                        {
-                                                       0u, EDMA3_CC_XFER_COMPLETION_INT, 0u, 0u,
-                                                       0u, 0u, 0u, 0u,
+                                                       EDMA3_CC_XFER_COMPLETION_INT_A8, EDMA3_CC_XFER_COMPLETION_INT_DSP, 0u, 0u,
+                                                       EDMA3_CC_XFER_COMPLETION_INT_M3VIDEO, EDMA3_CC_XFER_COMPLETION_INT_M3VPSS, 0u, 0u,
                                                        },
                         };
 
@@ -198,6 +258,24 @@ unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
 unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
 unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
 
+/**
+ * \brief Base address as seen from the different cores may be different
+ * And is defined based on the core
+ */
+#ifdef BUILD_NETRA_DSP
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x09000000))
+#define EDMA3_TC0_BASE_ADDR                          ((void *)(0x09800000))
+#define EDMA3_TC1_BASE_ADDR                          ((void *)(0x09900000))
+#define EDMA3_TC2_BASE_ADDR                          ((void *)(0x09A00000))
+#define EDMA3_TC3_BASE_ADDR                          ((void *)(0x09B00000))
+#else
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x49000000))
+#define EDMA3_TC0_BASE_ADDR                          ((void *)(0x49800000))
+#define EDMA3_TC1_BASE_ADDR                          ((void *)(0x49900000))
+#define EDMA3_TC2_BASE_ADDR                          ((void *)(0x49A00000))
+#define EDMA3_TC3_BASE_ADDR                          ((void *)(0x49B00000))
+#endif
+
 
 /* Driver Object Initialization Configuration */
 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
@@ -216,7 +294,7 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
            /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
            4u,
            /** Number of Regions on this EDMA3 controller */
-           5u,
+           6u,
 
            /**
             * \brief Channel mapping existence
@@ -230,13 +308,13 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
            1u,
 
            /** Global Register Region of CC Registers */
-           (void *)0x49000000u,
+           EDMA3_CC_BASE_ADDR,
            /** Transfer Controller (TC) Registers */
                {
-               (void *)0x49800000u,
-               (void *)0x49900000u,
-               (void *)0x49A00000u,
-               (void *)0x49B00000u,
+               EDMA3_TC0_BASE_ADDR,
+               EDMA3_TC1_BASE_ADDR,
+               EDMA3_TC2_BASE_ADDR,
+               EDMA3_TC3_BASE_ADDR,
                (void *)NULL,
                (void *)NULL,
                (void *)NULL,
@@ -358,14 +436,14 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
              * on the mapped channel.
              */
                {
-               0u, 1u, 2u, 3u,
-               4u, 5u, 6u, 7u,
-               8u, 9u, 10u, 11u,
-               12u, 13u, 14u, 15u,
-               16u, 17u, 18u, 19u,
-               20u, 21u, 22u, 23u,
-               24u, 25u, 26u, 27u,
-               28u, 29u, 30u, 31u,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
+               EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
                EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
                EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
                EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CH_NO_TCC_MAP,
@@ -388,39 +466,106 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                },
        };
 
+/**
+ * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs
+ * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig
+ * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels
+ * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict
+ *
+ * Only Resources owned by a perticular core are allocated by Driver
+ * Reserved resources are not allocated if requested for any available resource
+ */
+/* Defines for Own DMA channels For different cores */
+/* channels  0 to 31 */
+#define EDMA3_OWN_DMA_CHANNELS_0_A8    (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_0_DSP   (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO    (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_0_M3VPSS    (0xFFFFFFFFu)
+/* Channels 32 to 63 */
+#define EDMA3_OWN_DMA_CHANNELS_1_A8    (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_1_DSP   (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO    (0xFFFFFFFFu)
+#define EDMA3_OWN_DMA_CHANNELS_1_M3VPSS    (0xFFFFFFFFu)
+
+/* Defines for Own QDMA channels For different cores */
+#define EDMA3_OWN_QDMA_CHANNELS_0_A8    (0x000000FFu)
+#define EDMA3_OWN_QDMA_CHANNELS_0_DSP   (0x000000FFu)
+#define EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO    (0x000000FFu)
+#define EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS    (0x000000FFu)
+
+/* Defines for Own TCCs For different cores */
+#define EDMA3_OWN_TCC_0_A8    (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_0_DSP   (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_0_M3VIDEO    (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_0_M3VPSS    (0xFFFFFFFFu)
+/* Channels 32 to 63 */
+#define EDMA3_OWN_TCC_1_A8    (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_1_DSP   (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_1_M3VIDEO    (0xFFFFFFFFu)
+#define EDMA3_OWN_TCC_1_M3VPSS    (0xFFFFFFFFu)
+
+/* Defines for Reserved DMA channels For different cores */
+/* channels  0 to 31 */
+#define EDMA3_RESERVED_DMA_CHANNELS_0_A8    (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_DSP   (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO    (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS    (0x00u)
+/* Channels 32 to 63 */
+#define EDMA3_RESERVED_DMA_CHANNELS_1_A8    (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_DSP   (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO    (0x00u)
+#define EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS    (0x00u)
+
+/* Defines for RESERVED QDMA channels For different cores */
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_A8    (0x00u)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_DSP   (0x00u)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO    (0x00u)
+#define EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS    (0x00u)
+
+/* Defines for RESERVED TCCs For different cores */
+#define EDMA3_RESERVED_TCC_0_A8    (0x00u)
+#define EDMA3_RESERVED_TCC_0_DSP   (0x00u)
+#define EDMA3_RESERVED_TCC_0_M3VIDEO    (0x00u)
+#define EDMA3_RESERVED_TCC_0_M3VPSS    (0x00u)
+/* Channels 32 to 63 */
+#define EDMA3_RESERVED_TCC_1_A8    (0x00u)
+#define EDMA3_RESERVED_TCC_1_DSP   (0x00u)
+#define EDMA3_RESERVED_TCC_1_M3VIDEO    (0x00u)
+#define EDMA3_RESERVED_TCC_1_M3VPSS    (0x00u)
 
 /* Driver Instance Initialization Configuration */
 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
        {
                /* EDMA3 INSTANCE# 0 */
                {
-                       /* Resources owned/reserved by region 0 */
+                       /* Resources owned/reserved by region 0 (Configuration for Netra A8 Core)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x03FFFFF0u, 0x03E0FFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 159  128     191  160     223  192     255  224 */
                                 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 287  256     319  288     351  320     383  352 */
                                 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 415  384     447  416     479  448     511  480 */
-                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u},
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x03FFFFF0u, 0x03E0FFFFu},
+                               {EDMA3_OWN_DMA_CHANNELS_0_A8, EDMA3_OWN_DMA_CHANNELS_1_A8},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x0000000Fu},
+                               {EDMA3_OWN_QDMA_CHANNELS_0_A8},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x03FFFFF0u, 0x03E0FFFFu},
+                               {EDMA3_OWN_TCC_0_A8, EDMA3_OWN_TCC_1_A8},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x03FFFFF0u, 0x0060FFFFu, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -430,44 +575,44 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x03FFFFF0u, 0x0060FFFFu},
+                               {EDMA3_RESERVED_DMA_CHANNELS_0_A8, EDMA3_RESERVED_DMA_CHANNELS_1_A8},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {EDMA3_RESERVED_QDMA_CHANNELS_0_A8},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x03FFFFF0u, 0x0060FFFFu},
+                               {EDMA3_RESERVED_TCC_0_A8, EDMA3_RESERVED_TCC_1_A8},
                        },
 
-               /* Resources owned/reserved by region 1 */
+               /* Resources owned/reserved by region 1 (Configuration for Netra DSP Core)*/
                    {
                        /* ownPaRAMSets */
                        /* 31     0     63    32     95    64     127   96 */
-                       {0xFC00FF0Fu, 0xFC1F0000u, 0x00000000u, 0x00000000u,
-                       /* 159  128     191  160     223  192     255  224 */
-                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                       /* 287  256     319  288     351  320     383  352 */
-                        0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                       /* 415  384     447  416     479  448     511  480 */
-                        0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,},
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 
                        /* ownDmaChannels */
                        /* 31     0     63    32 */
-                       {0xFC00FF0Fu, 0xFC1F0000u},
+                       {EDMA3_OWN_DMA_CHANNELS_0_DSP, EDMA3_OWN_DMA_CHANNELS_1_DSP},
 
                        /* ownQdmaChannels */
                        /* 31     0 */
-                       {0x000000F0u},
+                       {EDMA3_OWN_QDMA_CHANNELS_0_DSP},
 
                        /* ownTccs */
                        /* 31     0     63    32 */
-                       {0xFC00FF0Fu, 0xFC1F0000u},
+                       {EDMA3_OWN_TCC_0_DSP, EDMA3_OWN_TCC_1_DSP},
 
                        /* resvdPaRAMSets */
                        /* 31     0     63    32     95    64     127   96 */
-                       {0x0000FF00u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                        /* 159  128     191  160     223  192     255  224 */
                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                        /* 287  256     319  288     351  320     383  352 */
@@ -477,18 +622,18 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                        /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x0000FF00u, 0x00000000u},
+                               {EDMA3_RESERVED_DMA_CHANNELS_0_DSP, EDMA3_RESERVED_DMA_CHANNELS_1_DSP},
 
                        /* resvdQdmaChannels */
                        /* 31     0 */
-                       {0x00000000u},
+                       {EDMA3_RESERVED_QDMA_CHANNELS_0_DSP},
 
                        /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x0000FF00u, 0x00000000u},
+                               {EDMA3_RESERVED_TCC_0_DSP, EDMA3_RESERVED_TCC_1_DSP},
                    },
 
-               /* Resources owned/reserved by region 2 */
+               /* Resources owned/reserved by region 2 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
@@ -535,7 +680,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                                {0x00000000u, 0x00000000u},
                        },
 
-               /* Resources owned/reserved by region 3 */
+               /* Resources owned/reserved by region 3 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
@@ -582,33 +727,33 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                                {0x00000000u, 0x00000000u},
                        },
 
-               /* Resources owned/reserved by region 4 */
+               /* Resources owned/reserved by region 4 (Configuration for Netra M3VIDEO Core)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_OWN_DMA_CHANNELS_0_M3VIDEO, EDMA3_OWN_DMA_CHANNELS_1_M3VIDEO},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {EDMA3_OWN_QDMA_CHANNELS_0_M3VIDEO},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_OWN_TCC_0_M3VIDEO, EDMA3_OWN_TCC_0_M3VIDEO},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -618,44 +763,44 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_RESERVED_DMA_CHANNELS_0_M3VIDEO, EDMA3_RESERVED_DMA_CHANNELS_1_M3VIDEO},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VIDEO},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_RESERVED_TCC_0_M3VIDEO, EDMA3_RESERVED_TCC_1_M3VIDEO},
                        },
 
-               /* Resources owned/reserved by region 5 */
+               /* Resources owned/reserved by region 5 (Configuration for Netra M3VPSS Core)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_OWN_DMA_CHANNELS_0_M3VPSS, EDMA3_OWN_DMA_CHANNELS_1_M3VPSS},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {EDMA3_OWN_QDMA_CHANNELS_0_M3VPSS},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_OWN_TCC_0_M3VPSS, EDMA3_OWN_TCC_1_M3VPSS},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
@@ -665,18 +810,18 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_RESERVED_DMA_CHANNELS_0_M3VPSS, EDMA3_RESERVED_DMA_CHANNELS_1_M3VPSS},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
-                               {0x00000000u},
+                               {EDMA3_RESERVED_QDMA_CHANNELS_0_M3VPSS},
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
+                               {EDMA3_RESERVED_TCC_0_M3VPSS, EDMA3_RESERVED_TCC_1_M3VPSS},
                        },
 
-               /* Resources owned/reserved by region 6 */
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
@@ -723,7 +868,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                                {0x00000000u, 0x00000000u},
                        },
 
-               /* Resources owned/reserved by region 7 */
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3video_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3video_cfg.c
deleted file mode 100755 (executable)
index 97e24c7..0000000
+++ /dev/null
@@ -1,762 +0,0 @@
-/*
- * sample_dm740_cfg.c
- *
- * Platform specific EDMA3 hardware related information like number of transfer
- * controllers, various interrupt ids etc. It is used while interrupts
- * enabling / disabling. It needs to be ported for different SoCs.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sdo/edma3/drv/edma3_drv.h>
-
-/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES                    1u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
-
-/* Number of DSPs present in the system */
-#define NUM_DSPS                                       1u
-const unsigned int numDsps = NUM_DSPS;
-
-/* Determine the processor id by reading DNUM register. */
-unsigned short determineProcId()
-       {
-#if 0
-       volatile unsigned int *addr;
-       unsigned int core_no;
-
-    /* Identify the core number */
-    addr = (unsigned int *)(CGEM_REG_START+0x40000);
-    core_no = ((*addr) & 0x000F0000)>>16;
-
-       return core_no;
-#endif
-       return 4;
-       }
-
-signed char*  getGlobalAddr(signed char* addr)
-{
-     return (addr); /* The address is already a global address */
-}
-
-unsigned short isGblConfigRequired(unsigned int dspNum)
-       {
-       (void) dspNum;
-
-       return 0;
-       }
-
-/* Semaphore handles */
-EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
-
-/** Number of PaRAM Sets available */
-#define EDMA3_NUM_PARAMSET                             (512u)
-/** Number of TCCS available */
-#define EDMA3_NUM_TCC                                  (64u)
-/** Number of Event Queues available */
-#define EDMA3_NUM_EVTQUE                                (4u)
-/** Number of Transfer Controllers available */
-#define EDMA3_NUM_TC                                    (4u)
-/** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT                    (62)
-/** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT                              (46u)
-/** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT                             (0u)
-#define EDMA3_TC1_ERROR_INT                             (0u)
-#define EDMA3_TC2_ERROR_INT                             (0u)
-#define EDMA3_TC3_ERROR_INT                             (0u)
-#define EDMA3_TC4_ERROR_INT                             (0u)
-#define EDMA3_TC5_ERROR_INT                             (0u)
-#define EDMA3_TC6_ERROR_INT                             (0u)
-#define EDMA3_TC7_ERROR_INT                             (0u)
-
-/**
-* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
-* ECM events (SoC specific). These ECM events come
-* under ECM block XXX (handling those specific ECM events). Normally, block
-* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
-* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
-* is mapped to a specific HWI_INT YYY in the tcf file.
-* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
-* to transfer completion interrupt.
-* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
-* to CC error interrupts.
-* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
-* to TC error interrupts.
-*/
-#define EDMA3_HWI_INT_XFER_COMP                                                        (7u)
-#define EDMA3_HWI_INT_CC_ERR                                                   (11u)
-#define EDMA3_HWI_INT_TC_ERR                                                   (11u)
-
-
-/**
- * \brief Mapping of DMA channels 0-31 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                                                                         /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
-
-/**
- * \brief Mapping of DMA channels 32-63 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                                                                         /* 63     32 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
-
-/* Variable which will be used internally for referring number of Event Queues. */
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
-
-/* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
-
-/**
- * Variable which will be used internally for referring transfer completion
- * interrupt.
- */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
-                                                       {
-                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
-                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
-                                                       },
-                        };
-
-/**
- * Variable which will be used internally for referring channel controller's
- * error interrupt.
- */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
-
-/**
- * Variable which will be used internally for referring transfer controllers'
- * error interrupts.
- */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
-                                {
-                                EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
-                                EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
-                                EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
-                                EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
-                                }
-                            };
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
-unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
-unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
-
-
-/* Driver Object Initialization Configuration */
-EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
-       {
-           {
-           /** Total number of DMA Channels supported by the EDMA3 Controller */
-           64u,
-           /** Total number of QDMA Channels supported by the EDMA3 Controller */
-           8u,
-           /** Total number of TCCs supported by the EDMA3 Controller */
-           64u,
-           /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-           512u,
-           /** Total number of Event Queues in the EDMA3 Controller */
-           4u,
-           /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-           4u,
-           /** Number of Regions on this EDMA3 controller */
-           6u,
-
-           /**
-            * \brief Channel mapping existence
-            * A value of 0 (No channel mapping) implies that there is fixed association
-            * for a channel number to a parameter entry number or, in other words,
-            * PaRAM entry n corresponds to channel n.
-            */
-           1u,
-
-           /** Existence of memory protection feature */
-           1u,
-
-           /** Global Register Region of CC Registers */
-           (void *)0x49000000u,
-           /** Transfer Controller (TC) Registers */
-               {
-               (void *)0x49800000u,
-               (void *)0x49900000u,
-               (void *)0x49A00000u,
-               (void *)0x49B00000u,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL
-               },
-           /** Interrupt no. for Transfer Completion */
-           EDMA3_CC_XFER_COMPLETION_INT,
-           /** Interrupt no. for CC Error */
-           EDMA3_CC_ERROR_INT,
-           /** Interrupt no. for TCs Error */
-               {
-               EDMA3_TC0_ERROR_INT,
-               EDMA3_TC1_ERROR_INT,
-               EDMA3_TC2_ERROR_INT,
-               EDMA3_TC3_ERROR_INT,
-               EDMA3_TC4_ERROR_INT,
-               EDMA3_TC5_ERROR_INT,
-               EDMA3_TC6_ERROR_INT,
-               EDMA3_TC7_ERROR_INT
-               },
-
-           /**
-            * \brief EDMA3 TC priority setting
-            *
-            * User can program the priority of the Event Queues
-            * at a system-wide level.  This means that the user can set the
-            * priority of an IO initiated by either of the TCs (Transfer Controllers)
-            * relative to IO initiated by the other bus masters on the
-            * device (ARM, DSP, USB, etc)
-            */
-               {
-               0u,
-               1u,
-               2u,
-               3u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-           /**
-            * \brief To Configure the Threshold level of number of events
-            * that can be queued up in the Event queues. EDMA3CC error register
-            * (CCERR) will indicate whether or not at any instant of time the
-            * number of events queued up in any of the event queues exceeds
-            * or equals the threshold/watermark value that is set
-            * in the queue watermark threshold register (QWMTHRA).
-            */
-               {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-           /**
-            * \brief To Configure the Default Burst Size (DBS) of TCs.
-            * An optimally-sized command is defined by the transfer controller
-            * default burst size (DBS). Different TCs can have different
-            * DBS values. It is defined in Bytes.
-            */
-               {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-           /**
-            * \brief Mapping from each DMA channel to a Parameter RAM set,
-            * if it exists, otherwise of no use.
-            */
-            {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
-            },
-
-            /**
-             * \brief Mapping from each DMA channel to a TCC. This specific
-             * TCC code will be returned when the transfer is completed
-             * on the mapped channel.
-             */
-            {
-            0u, 1u, 2u, 3u,
-            4u, 5u, 6u, 7u,
-            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u,
-            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            24u, 25u, 26u, 27u,
-            28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
-            },
-
-
-           /**
-            * \brief Mapping of DMA channels to Hardware Events from
-            * various peripherals, which use EDMA for data transfer.
-            * All channels need not be mapped, some can be free also.
-            */
-               {
-               0x00000000u,
-               0x00000000u
-               },
-               },
-       };
-
-
-/* Driver Instance Initialization Configuration */
-EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-       {
-               /* EDMA3 INSTANCE# 0 */
-               {
-                       /* Resources owned/reserved by region 0 */
-                       {
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000001u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-
-               /* Resources reserved by Region 0 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 1 */
-                   {
-                       /* ownPaRAMSets */
-                       /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000002u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 1 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                   },
-
-               /* Resources owned/reserved by region 2 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000004u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 2 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 3 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000008u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 3 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 4 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000008u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 4 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 5 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000008u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 5 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-               /* 31     0     63    32 */
-               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 6 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 7 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-           },
-       };
-
-
-
-/* End of File */
-
-
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3vpss_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti816x_m3vpss_cfg.c
deleted file mode 100755 (executable)
index d2abd5e..0000000
+++ /dev/null
@@ -1,762 +0,0 @@
-/*
- * sample_dm740_cfg.c
- *
- * Platform specific EDMA3 hardware related information like number of transfer
- * controllers, various interrupt ids etc. It is used while interrupts
- * enabling / disabling. It needs to be ported for different SoCs.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sdo/edma3/drv/edma3_drv.h>
-
-/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES                    1u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
-
-/* Number of DSPs present in the system */
-#define NUM_DSPS                                       1u
-const unsigned int numDsps = NUM_DSPS;
-
-/* Determine the processor id by reading DNUM register. */
-unsigned short determineProcId()
-       {
-#if 0
-       volatile unsigned int *addr;
-       unsigned int core_no;
-
-    /* Identify the core number */
-    addr = (unsigned int *)(CGEM_REG_START+0x40000);
-    core_no = ((*addr) & 0x000F0000)>>16;
-
-       return core_no;
-#endif
-       return 5;
-       }
-
-signed char*  getGlobalAddr(signed char* addr)
-{
-     return (addr); /* The address is already a global address */
-}
-
-unsigned short isGblConfigRequired(unsigned int dspNum)
-       {
-       (void) dspNum;
-
-       return 0;
-       }
-
-/* Semaphore handles */
-EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
-
-/** Number of PaRAM Sets available */
-#define EDMA3_NUM_PARAMSET                             (512u)
-/** Number of TCCS available */
-#define EDMA3_NUM_TCC                                  (64u)
-/** Number of Event Queues available */
-#define EDMA3_NUM_EVTQUE                                (4u)
-/** Number of Transfer Controllers available */
-#define EDMA3_NUM_TC                                    (4u)
-/** Interrupt no. for Transfer Completion */
-#define EDMA3_CC_XFER_COMPLETION_INT                    (63)
-/** Interrupt no. for CC Error */
-#define EDMA3_CC_ERROR_INT                              (46u)
-/** Interrupt no. for TCs Error */
-#define EDMA3_TC0_ERROR_INT                             (0u)
-#define EDMA3_TC1_ERROR_INT                             (0u)
-#define EDMA3_TC2_ERROR_INT                             (0u)
-#define EDMA3_TC3_ERROR_INT                             (0u)
-#define EDMA3_TC4_ERROR_INT                             (0u)
-#define EDMA3_TC5_ERROR_INT                             (0u)
-#define EDMA3_TC6_ERROR_INT                             (0u)
-#define EDMA3_TC7_ERROR_INT                             (0u)
-
-/**
-* EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
-* ECM events (SoC specific). These ECM events come
-* under ECM block XXX (handling those specific ECM events). Normally, block
-* 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
-* 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
-* is mapped to a specific HWI_INT YYY in the tcf file.
-* Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
-* to transfer completion interrupt.
-* Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
-* to CC error interrupts.
-* Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
-* to TC error interrupts.
-*/
-#define EDMA3_HWI_INT_XFER_COMP                                                        (7u)
-#define EDMA3_HWI_INT_CC_ERR                                                   (11u)
-#define EDMA3_HWI_INT_TC_ERR                                                   (11u)
-
-
-/**
- * \brief Mapping of DMA channels 0-31 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                                                                         /* 31     0 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0          (0xFFFFFFF0u)
-
-/**
- * \brief Mapping of DMA channels 32-63 to Hardware Events from
- * various peripherals, which use EDMA for data transfer.
- * All channels need not be mapped, some can be free also.
- * 1: Mapped
- * 0: Not mapped
- *
- * This mapping will be used to allocate DMA channels when user passes
- * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
- * copy). The same mapping is used to allocate the TCC when user passes
- * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
- *
- * To allocate more DMA channels or TCCs, one has to modify the event mapping.
- */
-                                                                                                         /* 63     32 */
-#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1          (0x3C7FFFFFu)
-
-/* Variable which will be used internally for referring number of Event Queues. */
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_EVTQUE};
-
-/* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {EDMA3_NUM_TC};
-
-/**
- * Variable which will be used internally for referring transfer completion
- * interrupt.
- */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
-                                                       {
-                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
-                                                       EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT, EDMA3_CC_XFER_COMPLETION_INT,
-                                                       },
-                        };
-
-/**
- * Variable which will be used internally for referring channel controller's
- * error interrupt.
- */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {EDMA3_CC_ERROR_INT};
-
-/**
- * Variable which will be used internally for referring transfer controllers'
- * error interrupts.
- */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =    {
-                                {
-                                EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,
-                                EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,
-                                EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,
-                                EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,
-                                }
-                            };
-
-/**
- * Variables which will be used internally for referring the hardware interrupt
- * for various EDMA3 interrupts.
- */
-unsigned int hwIntXferComp = EDMA3_HWI_INT_XFER_COMP;
-unsigned int hwIntCcErr = EDMA3_HWI_INT_CC_ERR;
-unsigned int hwIntTcErr = EDMA3_HWI_INT_TC_ERR;
-
-
-/* Driver Object Initialization Configuration */
-EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
-       {
-           {
-           /** Total number of DMA Channels supported by the EDMA3 Controller */
-           64u,
-           /** Total number of QDMA Channels supported by the EDMA3 Controller */
-           8u,
-           /** Total number of TCCs supported by the EDMA3 Controller */
-           64u,
-           /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-           512u,
-           /** Total number of Event Queues in the EDMA3 Controller */
-           4u,
-           /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-           4u,
-           /** Number of Regions on this EDMA3 controller */
-           6u,
-
-           /**
-            * \brief Channel mapping existence
-            * A value of 0 (No channel mapping) implies that there is fixed association
-            * for a channel number to a parameter entry number or, in other words,
-            * PaRAM entry n corresponds to channel n.
-            */
-           1u,
-
-           /** Existence of memory protection feature */
-           1u,
-
-           /** Global Register Region of CC Registers */
-           (void *)0x49000000u,
-           /** Transfer Controller (TC) Registers */
-               {
-               (void *)0x49800000u,
-               (void *)0x49900000u,
-               (void *)0x49A00000u,
-               (void *)0x49B00000u,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL
-               },
-           /** Interrupt no. for Transfer Completion */
-           EDMA3_CC_XFER_COMPLETION_INT,
-           /** Interrupt no. for CC Error */
-           EDMA3_CC_ERROR_INT,
-           /** Interrupt no. for TCs Error */
-               {
-               EDMA3_TC0_ERROR_INT,
-               EDMA3_TC1_ERROR_INT,
-               EDMA3_TC2_ERROR_INT,
-               EDMA3_TC3_ERROR_INT,
-               EDMA3_TC4_ERROR_INT,
-               EDMA3_TC5_ERROR_INT,
-               EDMA3_TC6_ERROR_INT,
-               EDMA3_TC7_ERROR_INT
-               },
-
-           /**
-            * \brief EDMA3 TC priority setting
-            *
-            * User can program the priority of the Event Queues
-            * at a system-wide level.  This means that the user can set the
-            * priority of an IO initiated by either of the TCs (Transfer Controllers)
-            * relative to IO initiated by the other bus masters on the
-            * device (ARM, DSP, USB, etc)
-            */
-               {
-               0u,
-               1u,
-               2u,
-               3u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-           /**
-            * \brief To Configure the Threshold level of number of events
-            * that can be queued up in the Event queues. EDMA3CC error register
-            * (CCERR) will indicate whether or not at any instant of time the
-            * number of events queued up in any of the event queues exceeds
-            * or equals the threshold/watermark value that is set
-            * in the queue watermark threshold register (QWMTHRA).
-            */
-               {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-           /**
-            * \brief To Configure the Default Burst Size (DBS) of TCs.
-            * An optimally-sized command is defined by the transfer controller
-            * default burst size (DBS). Different TCs can have different
-            * DBS values. It is defined in Bytes.
-            */
-               {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-           /**
-            * \brief Mapping from each DMA channel to a Parameter RAM set,
-            * if it exists, otherwise of no use.
-            */
-            {
-            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, 
-            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
-            },
-
-            /**
-             * \brief Mapping from each DMA channel to a TCC. This specific
-             * TCC code will be returned when the transfer is completed
-             * on the mapped channel.
-             */
-            {
-            0u, 1u, 2u, 3u,
-            4u, 5u, 6u, 7u,
-            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            12u, 13u, 14u, 15u,
-            16u, 17u, 18u, 19u,
-            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-            24u, 25u, 26u, 27u,
-            28u, 29u, 30u, 31u,
-            32u, 33u, 34u, 35u,
-            36u, 37u, 38u, 39u,
-            40u, 41u, 42u, 43u,
-            44u, 45u, 46u, 47u,
-            48u, 49u, 50u, 51u,
-            52u, 53u, 54u, 55u,
-            56u, 57u, 58u, 59u,
-            60u, 61u, 62u, 63u
-            },
-
-
-           /**
-            * \brief Mapping of DMA channels to Hardware Events from
-            * various peripherals, which use EDMA for data transfer.
-            * All channels need not be mapped, some can be free also.
-            */
-               {
-               0x00000000u,
-               0x00000000u
-               },
-               },
-       };
-
-
-/* Driver Instance Initialization Configuration */
-EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-       {
-               /* EDMA3 INSTANCE# 0 */
-               {
-                       /* Resources owned/reserved by region 0 */
-                       {
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000001u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-
-               /* Resources reserved by Region 0 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 1 */
-                   {
-                       /* ownPaRAMSets */
-                       /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000002u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 1 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                   },
-
-               /* Resources owned/reserved by region 2 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-               {0x00000004u},
-
-               /* ownTccs */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* Resources reserved by Region 2 */
-               /* resvdPaRAMSets */
-               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* resvdDmaChannels */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-
-               /* resvdQdmaChannels */
-               /* 31     0 */
-               {0x00000000u},
-
-               /* resvdTccs */
-        /* 31    0    63     32 */
-        {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 3 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-               /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
-               /* 287  256     319  288     351  320     383  352 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-               /* 415  384     447  416     479  448     511  480 */
-                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-               /* ownDmaChannels */
-               /* 31     0     63    32 */
-               {0xFFFFFFFFu, 0xFFFFFFFFu},
-
-               /* ownQdmaChannels */
-               /* 31     0 */
-           &nbs